mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-05-25 13:16:03 +08:00
delet old HC32F460 bsp and modify README.md (#6100)
This commit is contained in:
levizhxl
GitHub
@@ -41,7 +41,10 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下：
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| LED | 支持 | LED |
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| **片上外设** | **支持情况** | **备注** |
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| :------------ | :-----------: | :-----------------------------------: |
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| ADC | 支持 | ADC1: CH10, CH11, CH12,<br>ADC2: CH7 |
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| CAN | 支持 | CAN1 |
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| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
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| I2C | 支持 | 软件 |
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| UART | 支持 | UART1~4 |
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File diff suppressed because it is too large
Load Diff
@@ -1,42 +0,0 @@
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*.pyc
|
||||
*.map
|
||||
*.dblite
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*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
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||||
build
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||||
Debug
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||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
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||||
.config 3
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.config 4
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.config 5
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||||
Midea-X1
|
||||
*.uimg
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||||
GPATH
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||||
GRTAGS
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||||
GTAGS
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||||
.vscode
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||||
JLinkLog.txt
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||||
JLinkSettings.ini
|
||||
DebugConfig/
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||||
RTE/
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||||
settings/
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||||
*.uvguix*
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||||
cconfig.h
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||||
@@ -1,8 +0,0 @@
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||||
# files format check exclude path, please follow the instructions below to modify;
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||||
# If you need to exclude an entire folder, add the folder path in dir_path;
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||||
# If you need to exclude a file, add the path to the file in file_path.
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||||
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||||
file_path:
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dir_path:
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- Libraries
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@@ -1,9 +0,0 @@
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<?xml version="1.0" encoding="utf-8"?>
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<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
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|
||||
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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<events>
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</events>
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|
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</component_viewer>
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@@ -1,23 +0,0 @@
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mainmenu "RT-Thread Project Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "board/Kconfig"
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@@ -1,159 +0,0 @@
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/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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||||
* (the "License"); You may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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||||
/** \file ddl_config.h
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**
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** A detailed description is available at
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** @link DdlConfigGroup Ddl Config description @endlink
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**
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** - 2018-10-18 CDT First version for Device Driver Library config.
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**
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******************************************************************************/
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#ifndef __DDL_CONFIG_H__
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#define __DDL_CONFIG_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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|
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/* C binding of definitions if building with C++ compiler */
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||||
#ifdef __cplusplus
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extern "C"
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{
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#endif
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||||
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/**
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*******************************************************************************
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** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG)
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**
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******************************************************************************/
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//@{
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|
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/*******************************************************************************
|
||||
* Global type definitions ('typedef')
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******************************************************************************/
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||||
|
||||
/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*! Chip module on-off define */
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#define DDL_ON (1u)
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#define DDL_OFF (0u)
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/**
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*******************************************************************************
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** \brief This is the list of modules to be used in the device driver library
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** Select the modules you need to use to DDL_ON.
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**
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** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
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** properly.
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**
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** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
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** Library.
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**
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** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
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******************************************************************************/
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#define DDL_ICG_ENABLE (DDL_ON)
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#define DDL_UTILITY_ENABLE (DDL_ON)
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#define DDL_PRINT_ENABLE (DDL_ON)
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#define DDL_ADC_ENABLE (DDL_OFF)
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#define DDL_AES_ENABLE (DDL_OFF)
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#define DDL_CAN_ENABLE (DDL_OFF)
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#define DDL_CLK_ENABLE (DDL_ON)
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#define DDL_CMP_ENABLE (DDL_OFF)
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#define DDL_CRC_ENABLE (DDL_OFF)
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#define DDL_DCU_ENABLE (DDL_OFF)
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#define DDL_DMAC_ENABLE (DDL_ON)
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#define DDL_EFM_ENABLE (DDL_ON)
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#define DDL_EMB_ENABLE (DDL_OFF)
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#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
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#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON)
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#define DDL_GPIO_ENABLE (DDL_ON)
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#define DDL_HASH_ENABLE (DDL_OFF)
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#define DDL_I2C_ENABLE (DDL_OFF)
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#define DDL_I2S_ENABLE (DDL_OFF)
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#define DDL_INTERRUPTS_ENABLE (DDL_ON)
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#define DDL_KEYSCAN_ENABLE (DDL_OFF)
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#define DDL_MPU_ENABLE (DDL_OFF)
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#define DDL_OTS_ENABLE (DDL_OFF)
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#define DDL_PWC_ENABLE (DDL_ON)
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#define DDL_QSPI_ENABLE (DDL_OFF)
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#define DDL_RMU_ENABLE (DDL_OFF)
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#define DDL_RTC_ENABLE (DDL_ON)
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#define DDL_SDIOC_ENABLE (DDL_OFF)
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#define DDL_SPI_ENABLE (DDL_OFF)
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#define DDL_SRAM_ENABLE (DDL_ON)
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#define DDL_SWDT_ENABLE (DDL_OFF)
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#define DDL_TIMER0_ENABLE (DDL_ON)
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#define DDL_TIMER4_CNT_ENABLE (DDL_OFF)
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#define DDL_TIMER4_EMB_ENABLE (DDL_OFF)
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#define DDL_TIMER4_OCO_ENABLE (DDL_OFF)
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#define DDL_TIMER4_PWM_ENABLE (DDL_OFF)
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#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF)
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#define DDL_TIMER6_ENABLE (DDL_OFF)
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#define DDL_TIMERA_ENABLE (DDL_OFF)
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#define DDL_TRNG_ENABLE (DDL_OFF)
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#define DDL_USART_ENABLE (DDL_ON)
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#define DDL_USBFS_ENABLE (DDL_OFF)
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#define DDL_WDT_ENABLE (DDL_OFF)
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/*! Midware module on-off define */
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#define MW_ON (1u)
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#define MW_OFF (0u)
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/**
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*******************************************************************************
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** \brief This is the list of Midware modules to use
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** Select the modules you need to use to MW_ON.
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******************************************************************************/
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#define MW_SD_CARD_ENABLE (MW_OFF)
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#define MW_FS_ENABLE (MW_OFF)
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#define MW_W25QXX_ENABLE (MW_OFF)
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#define MW_WM8731_ENABLE (MW_OFF)
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/* BSP on-off define */
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#define BSP_ON (1u)
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#define BSP_OFF (0u)
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/**
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* @brief The following is a list of currently supported BSP boards.
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*/
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#define BSP_EV_HC32F460_LQFP100_V1 (1u)
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#define BSP_EV_HC32F460_LQFP100_V2 (2u)
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/**
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* @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently
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* in use.
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* The value should be set to one of the list of currently supported BSP boards.
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* @note If there is no supported BSP board or the BSP function is not used,
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* the value needs to be set to BSP_EV_HC32F460.
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*/
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#define BSP_EV_HC32F460 (BSP_EV_HC32F460)
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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||||
/*******************************************************************************
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||||
* Global function prototypes (definition in C source)
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******************************************************************************/
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//@} // DdlConfigGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DDL_CONFIG_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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@@ -1,234 +0,0 @@
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/*******************************************************************************
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||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
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/******************************************************************************/
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/** \file hc32_common.h
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**
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** A detailed description is available at
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** @link Hc32CommonGroup Hc32 Series Comm Part description @endlink
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**
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** - 2018-10-18 CDT First version for Hc32 Series of common part.
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**
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******************************************************************************/
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#ifndef __HC32_COMMON_H__
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#define __HC32_COMMON_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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||||
#include <string.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
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extern "C"
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{
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||||
#endif
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/**
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*******************************************************************************
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** \defgroup Hc32CommonGroup Hc32 Series Common Part(HC32COMMON)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
|
||||
* Global type definitions ('typedef')
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||||
******************************************************************************/
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||||
/**
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||||
*******************************************************************************
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** \brief single precision floating point number (4 byte)
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******************************************************************************/
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typedef float float32_t;
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|
||||
/**
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||||
*******************************************************************************
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||||
** \brief double precision floating point number (8 byte)
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******************************************************************************/
|
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typedef double float64_t;
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||||
|
||||
/**
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||||
*******************************************************************************
|
||||
** \brief function pointer type to void/void function
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||||
******************************************************************************/
|
||||
typedef void (*func_ptr_t)(void);
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief function pointer type to void/uint8_t function
|
||||
******************************************************************************/
|
||||
typedef void (*func_ptr_arg1_t)(uint8_t);
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|
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/**
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||||
*******************************************************************************
|
||||
** \brief functional state
|
||||
******************************************************************************/
|
||||
typedef enum en_functional_state
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{
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Disable = 0u,
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Enable = 1u,
|
||||
} en_functional_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief flag status
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||||
******************************************************************************/
|
||||
typedef enum en_flag_status
|
||||
{
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||||
Reset = 0u,
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Set = 1u,
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||||
} en_flag_status_t, en_int_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief generic error codes
|
||||
******************************************************************************/
|
||||
typedef enum en_result
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||||
{
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Ok = 0u, ///< No error
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||||
Error = 1u, ///< Non-specific error code
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||||
ErrorAddressAlignment = 2u, ///< Address alignment does not match
|
||||
ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set
|
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ErrorInvalidParameter = 4u, ///< Provided parameter is not valid
|
||||
ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress
|
||||
ErrorInvalidMode = 6u, ///< Operation not allowed in current mode
|
||||
ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly
|
||||
ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full
|
||||
ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.)
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||||
ErrorNotReady = 10u, ///< A requested final state is not reached
|
||||
OperationInProgress = 11u, ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.)
|
||||
} en_result_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Device include
|
||||
******************************************************************************/
|
||||
#if defined(HC32F460)
|
||||
#include "hc32f460.h"
|
||||
#include "system_hc32f460.h"
|
||||
#elif defined(HC32xxxx)
|
||||
#include "hc32xxxx.h"
|
||||
#include "system_hc32xxxx.h"
|
||||
#else
|
||||
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
|
||||
#endif
|
||||
|
||||
/*! Weak and Align compiler definition */
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned (4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif /* __UNUSED */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
|
||||
/* Usage: void __RAM_FUNC foo(void) */
|
||||
#endif /* __RAM_FUNC */
|
||||
#elif defined (__ICCARM__) ///< IAR Compiler
|
||||
#define __WEAKDEF __weak
|
||||
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#define __RAM_FUNC __ramfunc
|
||||
#elif defined (__CC_ARM) ///< ARM Compiler
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#define __UNUSED __attribute__((unused))
|
||||
/* RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. */
|
||||
#define __RAM_FUNC
|
||||
#else
|
||||
#error "unsupported compiler!!"
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/*! Pointer correspond to zero value */
|
||||
#if !defined (NULL)
|
||||
#define NULL (0)
|
||||
#endif
|
||||
|
||||
/*! Memory clear */
|
||||
#define MEM_ZERO_STRUCT(x) do { \
|
||||
memset((void*)&(x), 0l, (sizeof(x))); \
|
||||
}while(0)
|
||||
|
||||
/*! Decimal to BCD */
|
||||
#define DEC2BCD(x) ((((x) / 10u) << 4u) + ((x) % 10u))
|
||||
|
||||
/*! BCD to decimal */
|
||||
#define BCD2DEC(x) ((((x) >> 4u) * 10u) + ((x) & 0x0Fu))
|
||||
|
||||
/*! Returns the minimum value out of two values */
|
||||
#define MIN(x, y) ((x) < (y) ? (x) : (y))
|
||||
|
||||
/*! Returns the maximum value out of two values */
|
||||
#define MAX(x, y) ((x) > (y) ? (x) : (y))
|
||||
|
||||
/*! Returns the dimension of an array */
|
||||
#define ARRAY_SZ(X) (sizeof((X)) / sizeof((X)[0]))
|
||||
|
||||
/*! Check if it is a functional state */
|
||||
#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable))
|
||||
|
||||
#define BIT_SET(value,bit) ((value) |= (bit))
|
||||
|
||||
#define BIT_CLEAR(value,bit) ((value) &= ~(bit))
|
||||
|
||||
#define BIT_READ(value,bit) ((value) & (bit))
|
||||
|
||||
#define BIT_VALUE(index) (1ul << (index))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
|
||||
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
|
||||
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
|
||||
|
||||
#define READ_REG8(REG) (REG)
|
||||
#define READ_REG16(REG) (REG)
|
||||
#define READ_REG32(REG) (REG)
|
||||
|
||||
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
|
||||
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
|
||||
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
|
||||
|
||||
#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK)))))
|
||||
#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK)))))
|
||||
#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK)))))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
//@} // Hc32CommonGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_COMMON_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,262 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32_ddl.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Hc32DdlGroup Hc32 Series Ddl description @endlink
|
||||
**
|
||||
** - 2018-9-28 CDT First version for Hc32 Series Device Driver
|
||||
** Library.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32_DDL_H__
|
||||
#define __HC32_DDL_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Hc32DdlGroup Hc32 Series Device Driver Library(HC32DDL)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Defined use device driver library */
|
||||
#if !defined (USE_DEVICE_DRIVER_LIB)
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Comment the line below if you will not use the device driver library.
|
||||
** In this case, the application code will be based on direct access to
|
||||
** peripherals registers.
|
||||
******************************************************************************/
|
||||
/* #define USE_DEVICE_DRIVER_LIB */
|
||||
#endif /* USE_DEVICE_DRIVER_LIB */
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Hc32 Series device driver library version number v1.0.0
|
||||
******************************************************************************/
|
||||
#define HC32_DDL_VERSION_MAIN 0x01u ///< [31:24] main version
|
||||
#define HC32_DDL_VERSION_SUB1 0x00u ///< [23:16] sub1 version
|
||||
#define HC32_DDL_VERSION_SUB2 0x00u ///< [15:8] sub2 version
|
||||
#define HC32_DDL_VERSION_RC 0x00u ///< [7:0] release candidate
|
||||
#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \
|
||||
(HC32_DDL_VERSION_SUB1 << 16) | \
|
||||
(HC32_DDL_VERSION_SUB2 << 8 ) | \
|
||||
(HC32_DDL_VERSION_RC))
|
||||
|
||||
/*! Use device driver library */
|
||||
#if defined (USE_DEVICE_DRIVER_LIB)
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Include module's header file
|
||||
******************************************************************************/
|
||||
#if (DDL_ADC_ENABLE == DDL_ON)
|
||||
#include "hc32f460_adc.h"
|
||||
#endif /* DDL_ADC_ENABLE */
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
#include "hc32f460_aes.h"
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
#include "hc32f460_can.h"
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
#if (DDL_CMP_ENABLE == DDL_ON)
|
||||
#include "hc32f460_cmp.h"
|
||||
#endif /* DDL_CMP_ENABLE */
|
||||
|
||||
#if (DDL_CLK_ENABLE == DDL_ON)
|
||||
#include "hc32f460_clk.h"
|
||||
#endif /* DDL_CLK_ENABLE */
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
#include "hc32f460_dcu.h"
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
#if (DDL_DMAC_ENABLE == DDL_ON)
|
||||
#include "hc32f460_dmac.h"
|
||||
#endif /* DDL_DMAC_ENABLE */
|
||||
|
||||
#if (DDL_EFM_ENABLE == DDL_ON)
|
||||
#include "hc32f460_efm.h"
|
||||
#endif /* DDL_EFM_ENABLE */
|
||||
|
||||
#if (DDL_EMB_ENABLE == DDL_ON)
|
||||
#include "hc32f460_emb.h"
|
||||
#endif /* DDL_EMB_ENABLE */
|
||||
|
||||
#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON)
|
||||
#include "hc32f460_exint_nmi_swi.h"
|
||||
#endif /* DDL_EXINT_NMI_SWI_ENABLE */
|
||||
|
||||
#if (DDL_GPIO_ENABLE == DDL_ON)
|
||||
#include "hc32f460_gpio.h"
|
||||
#endif /* DDL_GPIO_ENABLE */
|
||||
|
||||
#if (DDL_HASH_ENABLE == DDL_ON)
|
||||
#include "hc32f460_hash.h"
|
||||
#endif /* DDL_HASH_ENABLE */
|
||||
|
||||
#if (DDL_I2C_ENABLE == DDL_ON)
|
||||
#include "hc32f460_i2c.h"
|
||||
#endif /* DDL_I2C_ENABLE */
|
||||
|
||||
#if (DDL_I2S_ENABLE == DDL_ON)
|
||||
#include "hc32f460_i2s.h"
|
||||
#endif /* DDL_I2S_ENABLE */
|
||||
|
||||
#if (DDL_ICG_ENABLE == DDL_ON)
|
||||
#include "hc32f460_icg.h"
|
||||
#endif /* DDL_ICG_ENABLE */
|
||||
|
||||
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
|
||||
#include "hc32f460_interrupts.h"
|
||||
#endif /* DDL_INTERRUPTS_ENABLE */
|
||||
|
||||
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
|
||||
#include "hc32f460_keyscan.h"
|
||||
#endif /* DDL_KEYSCAN_ENABLE */
|
||||
|
||||
#if (DDL_MPU_ENABLE == DDL_ON)
|
||||
#include "hc32f460_mpu.h"
|
||||
#endif /* DDL_MPU_ENABLE */
|
||||
|
||||
#if (DDL_OTS_ENABLE == DDL_ON)
|
||||
#include "hc32f460_ots.h"
|
||||
#endif /* DDL_OTS_ENABLE */
|
||||
|
||||
#if (DDL_PGA_ENABLE == DDL_ON)
|
||||
#include "hc32f460_pga.h"
|
||||
#endif /* DDL_PGA_ENABLE */
|
||||
|
||||
#if (DDL_PWC_ENABLE == DDL_ON)
|
||||
#include "hc32f460_pwc.h"
|
||||
#endif /* DDL_PWC_ENABLE */
|
||||
|
||||
#if (DDL_QSPI_ENABLE == DDL_ON)
|
||||
#include "hc32f460_qspi.h"
|
||||
#endif /* DDL_QSPI_ENABLE */
|
||||
|
||||
#if (DDL_RMU_ENABLE == DDL_ON)
|
||||
#include "hc32f460_rmu.h"
|
||||
#endif /* DDL_RMU_ENABLE */
|
||||
|
||||
#if (DDL_RTC_ENABLE == DDL_ON)
|
||||
#include "hc32f460_rtc.h"
|
||||
#endif /* DDL_RTC_ENABLE */
|
||||
|
||||
#if (DDL_SDIOC_ENABLE == DDL_ON)
|
||||
#include "hc32f460_sdioc.h"
|
||||
#endif /* DDL_SDIOC_ENABLE */
|
||||
|
||||
#if (DDL_SPI_ENABLE == DDL_ON)
|
||||
#include "hc32f460_spi.h"
|
||||
#endif /* DDL_SPI_ENABLE */
|
||||
|
||||
#if (DDL_SRAM_ENABLE == DDL_ON)
|
||||
#include "hc32f460_sram.h"
|
||||
#endif /* DDL_SRAM_ENABLE */
|
||||
|
||||
#if (DDL_SWDT_ENABLE == DDL_ON)
|
||||
#include "hc32f460_swdt.h"
|
||||
#endif /* DDL_SWDT_ENABLE */
|
||||
|
||||
#if (DDL_TIMER0_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer0.h"
|
||||
#endif /* DDL_TIMER0_ENABLE */
|
||||
|
||||
#if (DDL_TIMER4_CNT_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer4_cnt.h"
|
||||
#endif /* DDL_TIMER4_CNT_ENABLE */
|
||||
|
||||
#if (DDL_TIMER4_EMB_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer4_emb.h"
|
||||
#endif /* DDL_TIMER4_EMB_ENABLE */
|
||||
|
||||
#if (DDL_TIMER4_OCO_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer4_oco.h"
|
||||
#endif /* DDL_TIMER4_OCO_ENABLE */
|
||||
|
||||
#if (DDL_TIMER4_PWM_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer4_pwm.h"
|
||||
#endif /* DDL_TIMER4_PWM_ENABLE */
|
||||
|
||||
#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer4_sevt.h"
|
||||
#endif /* DDL_TIMER4_SEVT_ENABLE */
|
||||
|
||||
#if (DDL_TIMER6_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timer6.h"
|
||||
#endif /* DDL_TIMER6_ENABLE */
|
||||
|
||||
#if (DDL_TIMERA_ENABLE == DDL_ON)
|
||||
#include "hc32f460_timera.h"
|
||||
#endif /* DDL_TIMERA_ENABLE */
|
||||
|
||||
#if (DDL_TRNG_ENABLE == DDL_ON)
|
||||
#include "hc32f460_trng.h"
|
||||
#endif /* DDL_TRNG_ENABLE */
|
||||
|
||||
#if (DDL_USART_ENABLE == DDL_ON)
|
||||
#include "hc32f460_usart.h"
|
||||
#endif /* DDL_USART_ENABLE */
|
||||
|
||||
#if (DDL_USBFS_ENABLE == DDL_ON)
|
||||
#include "hc32f460_usbfs.h"
|
||||
#endif /* DDL_USBFS_ENABLE */
|
||||
|
||||
#if (DDL_UTILITY_ENABLE == DDL_ON)
|
||||
#include "hc32f460_utility.h"
|
||||
#endif /* DDL_UTILITY_ENABLE */
|
||||
|
||||
#if (DDL_WDT_ENABLE == DDL_ON)
|
||||
#include "hc32f460_wdt.h"
|
||||
#endif /* DDL_WDT_ENABLE */
|
||||
|
||||
#endif /* USE_DEVICE_DRIVER_LIB */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
//@} // Hc32DdlGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_DDL_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,105 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file system_hc32f460.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Hc32f460SystemGroup Hc32f460System description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __SYSTEM_HC32F460_H__
|
||||
#define __SYSTEM_HC32F460_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup Hc32f460SystemGroup HC32F460 System Configure
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Clock Setup macro definition
|
||||
**
|
||||
** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application
|
||||
** - 1: CLOCK_SETTING_CMSIS -
|
||||
******************************************************************************/
|
||||
#define CLOCK_SETTING_NONE 0u
|
||||
#define CLOCK_SETTING_CMSIS 1u
|
||||
|
||||
#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL)))
|
||||
|
||||
#if !defined (HRC_16MHz_VALUE)
|
||||
#define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (HRC_20MHz_VALUE)
|
||||
#define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (MRC_VALUE)
|
||||
#define MRC_VALUE ((uint32_t)8000000) /*!< Internal middle speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (LRC_VALUE)
|
||||
#define LRC_VALUE ((uint32_t)32768) /*!< Internal low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL_VALUE)
|
||||
#define XTAL_VALUE ((uint32_t)8000000) /*!< External high speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL32_VALUE)
|
||||
#define XTAL32_VALUE ((uint32_t)32768) /*!< External low speed OSC freq. */
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* START OF USER SETTINGS HERE */
|
||||
/* =========================== */
|
||||
/* */
|
||||
/* All lines with '<<<' can be set by user. */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Global function prototypes ('extern', definition in C source) */
|
||||
/******************************************************************************/
|
||||
extern uint32_t HRC_VALUE; // HRC Clock Frequency (Core Clock)
|
||||
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
|
||||
extern void SystemInit(void); // Initialize the system
|
||||
extern void SystemCoreClockUpdate(void); // Update SystemCoreClock variable
|
||||
|
||||
//@} // Hc32f460SystemGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_HC32F460_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,117 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file system_hc32f460.c
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link Hc32f460SystemGroup Hc32f460System description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \addtogroup Hc32f460SystemGroup
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
|
||||
//@{
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** System Clock Frequency (Core Clock) Variable according CMSIS
|
||||
******************************************************************************/
|
||||
uint32_t HRC_VALUE = HRC_16MHz_VALUE;
|
||||
uint32_t SystemCoreClock = MRC_VALUE;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief Setup the microcontroller system. Initialize the System and update
|
||||
** the SystemCoreClock variable.
|
||||
**
|
||||
** \param None
|
||||
** \return None
|
||||
******************************************************************************/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void) // Update SystemCoreClock variable
|
||||
{
|
||||
uint8_t tmp = 0u;
|
||||
uint32_t plln = 19u, pllp = 1u, pllm = 0u, pllsource = 0u;
|
||||
|
||||
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
|
||||
/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
|
||||
/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
|
||||
if (1UL == (HRC_FREQ_MON() & 1UL))
|
||||
{
|
||||
HRC_VALUE = HRC_16MHz_VALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
HRC_VALUE = HRC_20MHz_VALUE;
|
||||
}
|
||||
|
||||
tmp = M4_SYSREG->CMU_CKSWR_f.CKSW;
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* use internal high speed RC */
|
||||
SystemCoreClock = HRC_VALUE;
|
||||
break;
|
||||
case 0x01: /* use internal middle speed RC */
|
||||
SystemCoreClock = MRC_VALUE;
|
||||
break;
|
||||
case 0x02: /* use internal low speed RC */
|
||||
SystemCoreClock = LRC_VALUE;
|
||||
break;
|
||||
case 0x03: /* use external high speed OSC */
|
||||
SystemCoreClock = XTAL_VALUE;
|
||||
break;
|
||||
case 0x04: /* use external low speed OSC */
|
||||
SystemCoreClock = XTAL32_VALUE;
|
||||
break;
|
||||
case 0x05: /* use MPLL */
|
||||
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
|
||||
pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC;
|
||||
plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN;
|
||||
pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP;
|
||||
pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM;
|
||||
/* use exteranl high speed OSC as PLL source */
|
||||
if (0ul == pllsource)
|
||||
{
|
||||
SystemCoreClock = (XTAL_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul);
|
||||
}
|
||||
/* use interanl high RC as PLL source */
|
||||
else if (1ul == pllsource)
|
||||
{
|
||||
SystemCoreClock = (HRC_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reserved */
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,283 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,39 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.3
|
||||
* @date 24. June 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,272 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,346 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,81 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_aes.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link AesGroup Aes description @endlink
|
||||
**
|
||||
** - 2018-10-20 CDT First version for Device Driver Library of Aes.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_AES_H__
|
||||
#define __HC32F460_AES_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup AesGroup Advanced Encryption Standard(AES)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* AES key length in bytes is 16. */
|
||||
#define AES_KEYLEN ((uint8_t)16)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t AES_Encrypt(const uint8_t *pu8Plaintext,
|
||||
uint32_t u32PlaintextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t *pu8Ciphertext);
|
||||
|
||||
en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext,
|
||||
uint32_t u32CiphertextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t *pu8Plaintext);
|
||||
|
||||
//@} // AesGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_AES_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,279 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_cmp.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CmpGroup CMP @endlink
|
||||
**
|
||||
** - 2018-10-22 CDT First version for Device Driver Library of CMP.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CMP_H__
|
||||
#define __HC32F460_CMP_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CMP_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CmpGroup Comparator(CMP)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP function enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_func
|
||||
{
|
||||
CmpVcoutOutput = (1u << 12), ///< CMP vcout output enable function
|
||||
CmpOutpuInv = (1u << 13), ///< CMP output invert enable function
|
||||
CmpOutput = (1u << 14), ///< CMP output enable function
|
||||
} en_cmp_func_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP edge selection enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_edge_sel
|
||||
{
|
||||
CmpNoneEdge = 0u, ///< None edge detection
|
||||
CmpRisingEdge = 1u, ///< Rising edge detection
|
||||
CmpFaillingEdge = 2u, ///< Falling edge detection
|
||||
CmpBothEdge = 3u, ///< Falling or Rising edge detection
|
||||
} en_cmp_edge_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP filter sample clock division enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_fltclk_div
|
||||
{
|
||||
CmpNoneFlt = 0u, ///< Unuse filter
|
||||
CmpFltPclk3Div1 = 1u, ///< PCLK3/1
|
||||
CmpFltPclk3Div2 = 2u, ///< PCLK3/2
|
||||
CmpFltPclk3Div4 = 3u, ///< PCLK3/4
|
||||
CmpFltPclk3Div8 = 4u, ///< PCLK3/8
|
||||
CmpFltPclk3Div16 = 5u, ///< PCLK3/16
|
||||
CmpFltPclk3Div32 = 6u, ///< PCLK3/32
|
||||
CmpFltPclk3Div64 = 7u, ///< PCLK3/64
|
||||
} en_cmp_fltclk_div_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INP4 input enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inp4_sel
|
||||
{
|
||||
CmpInp4None = 0u, ///< None input
|
||||
CmpInp4PGAO = 1u, ///< PGAO output
|
||||
CmpInp4PGAO_BP = 2u, ///< PGAO_BP output
|
||||
CmpInp4CMP1_INP4 = 4u, ///< CMP1_INP4
|
||||
} en_cmp_inp4_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INP input enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inp_sel
|
||||
{
|
||||
CmpInpNone = 0u, ///< None input
|
||||
CmpInp1 = 1u, ///< INP1 input
|
||||
CmpInp2 = 2u, ///< INP2 input
|
||||
CmpInp1_Inp2 = 3u, ///< INP1 INP2 input
|
||||
CmpInp3 = 4u, ///< INP3 input
|
||||
CmpInp1_Inp3 = 5u, ///< INP1 INP3 input
|
||||
CmpInp2_Inp3 = 6u, ///< INP2 INP3 input
|
||||
CmpInp1_Inp2_Inp3 = 7u, ///< INP1 INP2 INP3 input
|
||||
CmpInp4 = 8u, ///< INP4 input
|
||||
CmpInp1_Inp4 = 9u, ///< INP1 INP4 input
|
||||
CmpInp2_Inp4 = 10u, ///< INP2 INP4 input
|
||||
CmpInp1_Inp2_Inp4 = 11u, ///< INP1 INP2 INP4 input
|
||||
CmpInp3_Inp4 = 12u, ///< INP3 INP4 input
|
||||
CmpInp1_Inp3_Inp4 = 13u, ///< INP1 INP3 INP4 input
|
||||
CmpInp2_Inp3_Inp4 = 14u, ///< INP2 INP3 INP4 input
|
||||
CmpInp1_Inp2_Inp3_Inp4 = 15u, ///< INP1 INP2 INP3 INP4 input
|
||||
} en_cmp_inp_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INM input enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inm_sel
|
||||
{
|
||||
CmpInmNone = 0u, ///< None input
|
||||
CmpInm1 = 1u, ///< INM1 input
|
||||
CmpInm2 = 2u, ///< INM2 input
|
||||
CmpInm3 = 4u, ///< INM3 input
|
||||
CmpInm4 = 8u, ///< INM4 input
|
||||
} en_cmp_inm_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP INP State enumeration (read only)
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_inp_state
|
||||
{
|
||||
CmpInpNoneState = 0u, ///< none input state
|
||||
CmpInp1State = 1u, ///< INP1 input state
|
||||
CmpInp2State = 2u, ///< INP2 input state
|
||||
CmpInp3State = 4u, ///< INP3 input state
|
||||
CmpInp4State = 8u, ///< INP4 input state
|
||||
} en_cmp_inp_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP Output State enumeration (read only)
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_output_state
|
||||
{
|
||||
CmpOutputLow = 0u, ///< Compare output Low "0"
|
||||
CmpOutputHigh = 1u, ///< Compare output High "1"
|
||||
} en_cmp_output_state_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP input selection
|
||||
******************************************************************************/
|
||||
typedef struct stc_cmp_input_sel
|
||||
{
|
||||
en_cmp_inm_sel_t enInmSel; ///< CMP INM sel
|
||||
|
||||
en_cmp_inp_sel_t enInpSel; ///< CMP INP sel
|
||||
|
||||
en_cmp_inp4_sel_t enInp4Sel; ///< CMP INP4 sel
|
||||
} stc_cmp_input_sel_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief DAC channel
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_dac_ch
|
||||
{
|
||||
CmpDac1 = 0u, ///< DAC1
|
||||
CmpDac2 = 1u, ///< DAC2
|
||||
} en_cmp_dac_ch_t;
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
** \brief ADC internal reference voltage path
|
||||
******************************************************************************/
|
||||
typedef enum en_cmp_adc_int_ref_volt_path
|
||||
{
|
||||
CmpAdcRefVoltPathDac1 = (1u << 0u), ///< ADC internal reference voltage path: DAC1
|
||||
CmpAdcRefVoltPathDac2 = (1u << 1u), ///< ADC internal reference voltage path: DAC2
|
||||
CmpAdcRefVoltPathVref = (1u << 4u), ///< ADC internal reference voltage path: VREF
|
||||
} en_cmp_adc_int_ref_volt_path_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP initialization structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_cmp_init
|
||||
{
|
||||
en_cmp_edge_sel_t enEdgeSel; ///< CMP edge sel
|
||||
|
||||
en_cmp_fltclk_div_t enFltClkDiv; ///< CMP FLTclock division
|
||||
|
||||
en_functional_state_t enCmpOutputEn; ///< CMP Output enable
|
||||
|
||||
en_functional_state_t enCmpVcoutOutputEn; ///< CMP output result enable
|
||||
|
||||
en_functional_state_t enCmpInvEn; ///< CMP INV sel for output
|
||||
|
||||
en_functional_state_t enCmpIntEN; ///< CMP interrupt enable
|
||||
} stc_cmp_init_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief CMP DAC initialization structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_cmp_dac_init
|
||||
{
|
||||
uint8_t u8DacData; ///< CMP DAC Data register value
|
||||
|
||||
en_functional_state_t enCmpDacEN; ///< CMP DAC enable
|
||||
} stc_cmp_dac_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg);
|
||||
en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd);
|
||||
en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd);
|
||||
en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx,
|
||||
uint8_t u8ScanStable,
|
||||
uint8_t u8ScanPeriod);
|
||||
en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx,
|
||||
en_cmp_func_t enFunc,
|
||||
en_functional_state_t enCmd);
|
||||
en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx,
|
||||
en_cmp_fltclk_div_t enFltClkDiv);
|
||||
en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx,
|
||||
en_cmp_edge_sel_t enEdgeSel);
|
||||
en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx,
|
||||
const stc_cmp_input_sel_t *pstcInputSel);
|
||||
en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel);
|
||||
en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel);
|
||||
en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel);
|
||||
en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx);
|
||||
en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx);
|
||||
en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx);
|
||||
en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh,
|
||||
const stc_cmp_dac_init_t *pstcInitCfg);
|
||||
en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh);
|
||||
en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd);
|
||||
en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData);
|
||||
uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh);
|
||||
en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath);
|
||||
|
||||
//@} // CmpGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CMP_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CMP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,118 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_crc.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link CrcGroup Crc description @endlink
|
||||
**
|
||||
** - 2019-03-07 CDT First version for Device Driver Library of Crc.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_CRC_H__
|
||||
#define __HC32F460_CRC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_CRC_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup CrcGroup Cyclic Redundancy Check(CRC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/* Bits definitions of CRC control register(CRC_CR). */
|
||||
/*
|
||||
* Definitions of CRC protocol.
|
||||
* NOTE: CRC16 polynomial is X16 + X12 + X5 + 1
|
||||
* CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \
|
||||
* X8 + X7 + X5 + X4 + X2 + X + 1
|
||||
*/
|
||||
#define CRC_SEL_16B ((uint32_t)0x0)
|
||||
#define CRC_SEL_32B ((uint32_t)(0x1ul << 1u))
|
||||
|
||||
/*
|
||||
* Identifies the transpose configuration of the source data.
|
||||
* If this function is enabled, the source data's bits in bytes are transposed.
|
||||
* e.g. There's a source data 0x1234 which will be calculated checksum and this
|
||||
* function is enabled, the final data be calculated is 0x482C.
|
||||
* 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48.
|
||||
* 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C.
|
||||
* The same to 32 bit data while using CRC32.
|
||||
*/
|
||||
#define CRC_REFIN_DISABLE ((uint32_t)0x0)
|
||||
#define CRC_REFIN_ENABLE ((uint32_t)(0x1ul << 2u))
|
||||
|
||||
/*
|
||||
* Identifies the transpose configuration of the checksum.
|
||||
* If this function is enabled, bits of the checksum will be transposed.
|
||||
* e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then
|
||||
* this function is enabled, the checksum will be 0x1E6A.
|
||||
* 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A.
|
||||
* The same to CRC32 checksum while using CRC32.
|
||||
*/
|
||||
#define CRC_REFOUT_DISABLE ((uint32_t)0x0)
|
||||
#define CRC_REFOUT_ENABLE ((uint32_t)(0x1ul << 3u))
|
||||
|
||||
/*
|
||||
* XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32).
|
||||
* e.g. There is a CRC16 checksum is 0x5678 before this function enabled.
|
||||
* If this function enabled, the checksum will be 0xA987.
|
||||
* The same to CRC32 checksum while using CRC32.
|
||||
*/
|
||||
#define CRC_XOROUT_DISABLE ((uint32_t)0x0)
|
||||
#define CRC_XOROUT_ENABLE ((uint32_t)(0x1ul << 4u))
|
||||
|
||||
#define CRC_CONFIG_MASK ((uint32_t)(0x1Eu))
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void CRC_Init(uint32_t u32Config);
|
||||
uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length);
|
||||
uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length);
|
||||
bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length);
|
||||
bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length);
|
||||
|
||||
//@} // CrcGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_CRC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_CRC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,216 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_dcu.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DcuGroup DCU description @endlink
|
||||
**
|
||||
** - 2018-10-15 CDT First version for Device Driver Library of DCU.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_DCU_H__
|
||||
#define __HC32F460_DCU_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DcuGroup Data Computing Unit(DCU)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU register data enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_data_register
|
||||
{
|
||||
DcuRegisterData0 = 0u, ///< DCU DATA0
|
||||
DcuRegisterData1 = 1u, ///< DCU DATA1
|
||||
DcuRegisterData2 = 2u, ///< DCU DATA2
|
||||
} en_dcu_data_register_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU operation enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_operation_mode
|
||||
{
|
||||
DcuInvalid = 0u, ///< DCU Invalid
|
||||
DcuOpAdd = 1u, ///< DCU operation: Add
|
||||
DcuOpSub = 2u, ///< DCU operation: Sub
|
||||
DcuHwTrigOpAdd = 3u, ///< DCU operation: Hardware trigger Add
|
||||
DcuHwTrigOpSub = 4u, ///< DCU operation: Hardware trigger Sub
|
||||
DcuOpCompare = 5u, ///< DCU operation: Compare
|
||||
} en_dcu_operation_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU data size enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_data_size
|
||||
{
|
||||
DcuDataBit8 = 0u, ///< DCU data size: 8 bit
|
||||
DcuDataBit16 = 1u, ///< DCU data size: 16 bit
|
||||
DcuDataBit32 = 2u, ///< DCU data size: 32 bit
|
||||
} en_dcu_data_size_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU compare operation trigger mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_cmp_trigger_mode
|
||||
{
|
||||
DcuCmpTrigbyData0 = 0u, ///< DCU compare triggered by DATA0
|
||||
DcuCmpTrigbyData012 = 1u, ///< DCU compare triggered by DATA0 or DATA1 or DATA2
|
||||
} en_dcu_cmp_trigger_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU interrupt selection enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_int_sel
|
||||
{
|
||||
DcuIntOp = (1ul << 0), ///< DCU overflow or underflow interrupt
|
||||
DcuIntLs2 = (1ul << 1), ///< DCU DATA0 < DATA2 interrupt
|
||||
DcuIntEq2 = (1ul << 2), ///< DCU DATA0 = DATA2 interrupt
|
||||
DcuIntGt2 = (1ul << 3), ///< DCU DATA0 > DATA2 interrupt
|
||||
DcuIntLs1 = (1ul << 4), ///< DCU DATA0 < DATA1 interrupt
|
||||
DcuIntEq1 = (1ul << 5), ///< DCU DATA0 = DATA1 interrupt
|
||||
DcuIntGt1 = (1ul << 6), ///< DCU DATA0 > DATA1 interrupt
|
||||
} en_dcu_int_sel_t, en_dcu_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU window interrupt mode enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dcu_int_win_mode
|
||||
{
|
||||
DcuIntInvalid = 0u, ///< DCU don't occur interrupt
|
||||
DcuWinIntInvalid = 1u, ///< DCU window interrupt is invalid.
|
||||
DcuInsideWinCmpInt = 2u, ///< DCU occur interrupt when DATA2 ≤ DATA0 ≤ DATA2
|
||||
DcuOutsideWinCmpInt = 3u, ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2
|
||||
} en_dcu_int_win_mode_t;
|
||||
|
||||
/* DCU common trigger source select */
|
||||
typedef enum en_dcu_com_trigger
|
||||
{
|
||||
DcuComTrigger_1 = 1u, ///< Select common trigger 1.
|
||||
DcuComTrigger_2 = 2u, ///< Select common trigger 2.
|
||||
DcuComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
|
||||
} en_dcu_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DCU initialization configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dcu_init
|
||||
{
|
||||
uint32_t u32IntSel; ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t
|
||||
|
||||
en_functional_state_t enIntCmd; ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function
|
||||
|
||||
en_dcu_int_win_mode_t enIntWinMode; ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t
|
||||
|
||||
en_dcu_data_size_t enDataSize; ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t
|
||||
|
||||
en_dcu_operation_mode_t enOperation; ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t
|
||||
|
||||
en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t
|
||||
|
||||
} stc_dcu_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg);
|
||||
en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_operation_mode_t enMode);
|
||||
en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize);
|
||||
en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_int_win_mode_t enIntWinMode);
|
||||
en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_cmp_trigger_mode_t enTriggerMode);
|
||||
en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx);
|
||||
en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx);
|
||||
en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag);
|
||||
en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag);
|
||||
en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_int_sel_t enIntSel,
|
||||
en_functional_state_t enCmd);
|
||||
uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg);
|
||||
en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg, uint8_t u8Data);
|
||||
uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg);
|
||||
en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint16_t u16Data);
|
||||
uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg);
|
||||
en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_data_register_t enDataReg,
|
||||
uint32_t u32Data);
|
||||
en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx,
|
||||
en_event_src_t enTriggerSrc);
|
||||
void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx,
|
||||
en_dcu_com_trigger_t enComTrigger,
|
||||
en_functional_state_t enState);
|
||||
|
||||
//@} // DcuGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_DCU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,363 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_dmac.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DmacGroup DMAC description @endlink
|
||||
**
|
||||
** - 2018-11-18 CDT First version for Device Driver Library of DMAC.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_DMAC_H__
|
||||
#define __HC32F460_DMAC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_DMAC_ENABLE == DDL_ON)
|
||||
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DmacGroup Direct Memory Access Control(DMAC)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA Channel
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_channel
|
||||
{
|
||||
DmaCh0 = 0u, ///< DMA channel 0
|
||||
DmaCh1 = 1u, ///< DMA channel 1
|
||||
DmaCh2 = 2u, ///< DMA channel 2
|
||||
DmaCh3 = 3u, ///< DMA channel 3
|
||||
DmaChMax = 4u ///< DMA channel max
|
||||
}en_dma_channel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA transfer data width
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_transfer_width
|
||||
{
|
||||
Dma8Bit = 0u, ///< 8 bit transfer via DMA
|
||||
Dma16Bit = 1u, ///< 16 bit transfer via DMA
|
||||
Dma32Bit = 2u ///< 32 bit transfer via DMA
|
||||
}en_dma_transfer_width_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA flag
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_flag
|
||||
{
|
||||
DmaTransferComplete = 0u, ///< DMA transfer complete
|
||||
DmaBlockComplete = 1u, ///< DMA block transfer complete
|
||||
DmaTransferErr = 2u, ///< DMA transfer error
|
||||
DmaReqErr = 3u, ///< DMA transfer request error
|
||||
DmaFlagMax = 4u
|
||||
}en_dma_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA address mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_address_mode
|
||||
{
|
||||
AddressFix = 0u, ///< Address fixed
|
||||
AddressIncrease = 1u, ///< Address increased
|
||||
AddressDecrease = 2u, ///< Address decreased
|
||||
}en_dma_address_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA link list pointer mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_llp_mode
|
||||
{
|
||||
LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request
|
||||
LlpRunNow = 1u, ///< DMA trigger transfer now
|
||||
}en_dma_llp_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA interrupt selection
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_irq_sel
|
||||
{
|
||||
TrnErrIrq = 0u, ///< Select DMA transfer error interrupt
|
||||
TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt
|
||||
TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt
|
||||
BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt
|
||||
DmaIrqSelMax = 4u
|
||||
}en_dma_irq_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config count mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_recfg_cnt_mode
|
||||
{
|
||||
CntFix = 0u, ///< Fix
|
||||
CntSrcAddr = 1u, ///< Source address mode
|
||||
CntDesAddr = 2u, ///< Destination address mode
|
||||
}en_dma_recfg_cnt_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config destination address mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_recfg_daddr_mode
|
||||
{
|
||||
DaddrFix = 0u, ///< Fix
|
||||
DaddrNseq = 1u, ///< No_sequence address
|
||||
DaddrRep = 2u, ///< Repeat address
|
||||
}en_dma_recfg_daddr_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config source address mode
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_recfg_saddr_mode
|
||||
{
|
||||
SaddrFix = 0u, ///< Fix
|
||||
SaddrNseq = 1u, ///< No_sequence address
|
||||
SaddrRep = 2u, ///< Repeat address
|
||||
}en_dma_recfg_saddr_mode_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA channel status
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_ch_flag
|
||||
{
|
||||
DmaSta = 0u, ///< DMA status.
|
||||
ReCfgSta = 1u, ///< DMA re_configuration status.
|
||||
DmaCh0Sta = 2u, ///< DMA channel 0 status.
|
||||
DmaCh1Sta = 3u, ///< DMA channel 1 status.
|
||||
DmaCh2Sta = 4u, ///< DMA channel 2 status.
|
||||
DmaCh3Sta = 5u, ///< DMA channel 3 status.
|
||||
}en_dma_ch_flag_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA common trigger source select
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_dma_com_trigger
|
||||
{
|
||||
DmaComTrigger_1 = 0x1, ///< Select common trigger 1.
|
||||
DmaComTrigger_2 = 0x2, ///< Select common trigger 2.
|
||||
DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
|
||||
} en_dma_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA llp descriptor
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_llp_descriptor
|
||||
{
|
||||
uint32_t SARx; ///< DMA source address register
|
||||
uint32_t DARx; ///< DMA destination address register
|
||||
union
|
||||
{
|
||||
uint32_t DTCTLx;
|
||||
stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t RPTx;
|
||||
stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t SNSEQCTLx;
|
||||
stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register
|
||||
};
|
||||
union
|
||||
{
|
||||
__IO uint32_t DNSEQCTLx;
|
||||
stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t LLPx;
|
||||
stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register
|
||||
};
|
||||
union
|
||||
{
|
||||
uint32_t CHxCTL;
|
||||
stc_dma_ch0ctl_field_t CHxCTL_f; ///< DMA channel control register
|
||||
};
|
||||
}stc_dma_llp_descriptor_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA no-sequence function configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_nseq_cfg
|
||||
{
|
||||
uint32_t u32Offset; ///< DMA no-sequence offset.
|
||||
uint16_t u16Cnt; ///< DMA no-sequence count.
|
||||
}stc_dma_nseq_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA no-sequence function configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_nseqb_cfg
|
||||
{
|
||||
uint32_t u32NseqDist; ///< DMA no-sequence district interval.
|
||||
uint16_t u16CntB; ///< DMA no-sequence count.
|
||||
}stc_dma_nseqb_cfg_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA re_config configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_recfg_ctl
|
||||
{
|
||||
uint16_t u16SrcRptBSize; ///< The source repeat size.
|
||||
uint16_t u16DesRptBSize; ///< The destination repeat size.
|
||||
en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode.
|
||||
en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode.
|
||||
en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode.
|
||||
stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config.
|
||||
stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config.
|
||||
}stc_dma_recfg_ctl_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA channel configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_ch_cfg
|
||||
{
|
||||
en_dma_address_mode_t enSrcInc; ///< DMA source address update mode.
|
||||
en_dma_address_mode_t enDesInc; ///< DMA destination address update mode.
|
||||
en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not.
|
||||
en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not.
|
||||
en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not.
|
||||
en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not.
|
||||
en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width.
|
||||
en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not.
|
||||
en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode.
|
||||
en_functional_state_t enIntEn; ///< Enable interrupt function or not.
|
||||
}stc_dma_ch_cfg_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief DMA configuration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_dma_config
|
||||
{
|
||||
uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set.
|
||||
uint16_t u16TransferCnt; ///< Transfer counter.
|
||||
uint32_t u32SrcAddr; ///< The source address.
|
||||
uint32_t u32DesAddr; ///< The destination address.
|
||||
uint16_t u16SrcRptSize; ///< The source repeat size.
|
||||
uint16_t u16DesRptSize; ///< The destination repeat size.
|
||||
uint32_t u32DmaLlp; ///< The Dma linked list pointer address
|
||||
stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration.
|
||||
stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration.
|
||||
stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration.
|
||||
}stc_dma_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState);
|
||||
en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
|
||||
en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg);
|
||||
void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState);
|
||||
en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag);
|
||||
|
||||
en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
|
||||
en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
|
||||
en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize);
|
||||
en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt);
|
||||
en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
|
||||
en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg);
|
||||
en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg);
|
||||
en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg);
|
||||
en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg);
|
||||
en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer);
|
||||
|
||||
void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc);
|
||||
void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc);
|
||||
void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
|
||||
void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
|
||||
|
||||
void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg);
|
||||
void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg);
|
||||
void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch);
|
||||
|
||||
|
||||
|
||||
//@} // DmacGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_DMAC_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_DMAC_H__*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,209 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_efm.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EfmGroup EFM description @endlink
|
||||
**
|
||||
** - 2018-10-29 CDT First version for Device Driver Library of EFM.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_EFM_H__
|
||||
#define __HC32F460_EFM_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EFM_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup EfmGroup Embedded Flash Management unit(EFM)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flash status.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_flash_status
|
||||
{
|
||||
FlashReady = 1u, ///< The flash ready flag.
|
||||
FlashRWErr = 2u, ///< The flash read/write error flag.
|
||||
FlashEOP = 3u, ///< The flash end of operation flag.
|
||||
FlashPgMissMatch = 4u, ///< The flash program miss match flag.
|
||||
FlashPgSizeErr = 5u, ///< The flash program size error flag.
|
||||
FlashPgareaPErr = 6u, ///< The flash program protect area error flag.
|
||||
FlashWRPErr = 7u, ///< The flash write protect error flag.
|
||||
}en_efm_flash_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flash read mode.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_read_md
|
||||
{
|
||||
NormalRead = 0u, ///< The flash normal read mode.
|
||||
UltraPowerRead = 1u, ///< The flash ultra power read mode.
|
||||
}en_efm_read_md_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The flash interrupt select.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_int_sel
|
||||
{
|
||||
PgmErsErrInt = 0u, ///< The flash program / erase error interrupt.
|
||||
EndPgmInt = 1u, ///< The flash end of program interrupt.
|
||||
ColErrInt = 2u, ///< The flash read collided error interrupt.
|
||||
}en_efm_int_sel_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief The bus state while flash program & erase.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_efm_bus_sta
|
||||
{
|
||||
BusBusy = 0u, ///< The bus busy while flash program & erase.
|
||||
BusRelease = 1u, ///< The bus release while flash program & erase.
|
||||
}en_efm_bus_sta_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Structure of windows protect address.
|
||||
**
|
||||
** \note None.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_efm_win_protect_addr
|
||||
{
|
||||
uint32_t StartAddr; ///< The protect start address.
|
||||
uint32_t EndAddr; ///< The protect end address.
|
||||
}stc_efm_win_protect_addr_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Structure of unique ID.
|
||||
**
|
||||
** \note None.
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef struct stc_efm_unique_id
|
||||
{
|
||||
uint32_t uniqueID1; ///< unique ID 1.
|
||||
uint32_t uniqueID2; ///< unique ID 2.
|
||||
uint32_t uniqueID3; ///< unique ID 3.
|
||||
}stc_efm_unique_id_t;
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Flach latency cycle (0~15) */
|
||||
#define EFM_LATENCY_0 (0ul)
|
||||
#define EFM_LATENCY_1 (1ul)
|
||||
#define EFM_LATENCY_2 (2ul)
|
||||
#define EFM_LATENCY_3 (3ul)
|
||||
#define EFM_LATENCY_4 (4ul)
|
||||
#define EFM_LATENCY_5 (5ul)
|
||||
#define EFM_LATENCY_6 (6ul)
|
||||
#define EFM_LATENCY_7 (7ul)
|
||||
#define EFM_LATENCY_8 (8ul)
|
||||
#define EFM_LATENCY_9 (9ul)
|
||||
#define EFM_LATENCY_10 (10ul)
|
||||
#define EFM_LATENCY_11 (11ul)
|
||||
#define EFM_LATENCY_12 (12ul)
|
||||
#define EFM_LATENCY_13 (13ul)
|
||||
#define EFM_LATENCY_14 (14ul)
|
||||
#define EFM_LATENCY_15 (15ul)
|
||||
|
||||
/* Flash flag */
|
||||
#define EFM_FLAG_WRPERR (0x00000001ul)
|
||||
#define EFM_FLAG_PEPRTERR (0x00000002ul)
|
||||
#define EFM_FLAG_PGSZERR (0x00000004ul)
|
||||
#define EFM_FLAG_PGMISMTCH (0x00000008ul)
|
||||
#define EFM_FLAG_EOP (0x00000010ul)
|
||||
#define EFM_FLAG_COLERR (0x00000020ul)
|
||||
#define EFM_FLAG_RDY (0x00000100ul)
|
||||
|
||||
/* Flash operate mode */
|
||||
#define EFM_MODE_READONLY (0ul)
|
||||
#define EFM_MODE_SINGLEPROGRAM (1ul)
|
||||
#define EFM_MODE_SINGLEPROGRAMRB (2ul)
|
||||
#define EFM_MODE_SEQUENCEPROGRAM (3ul)
|
||||
#define EFM_MODE_SECTORERASE (4ul)
|
||||
#define EFM_MODE_CHIPERASE (5ul)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
void EFM_Unlock(void);
|
||||
void EFM_Lock(void);
|
||||
|
||||
void EFM_FlashCmd(en_functional_state_t enNewState);
|
||||
void EFM_SetLatency(uint32_t u32Latency);
|
||||
void EFM_InstructionCacheCmd(en_functional_state_t enNewState);
|
||||
void EFM_DataCacheRstCmd(en_functional_state_t enNewState);
|
||||
void EFM_SetReadMode(en_efm_read_md_t enReadMD);
|
||||
void EFM_ErasePgmCmd(en_functional_state_t enNewState);
|
||||
en_result_t EFM_SetErasePgmMode(uint32_t u32Mode);
|
||||
void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag);
|
||||
en_flag_status_t EFM_GetSwitchStatus(void);
|
||||
void EFM_ClearFlag(uint32_t u32flag);
|
||||
en_efm_flash_status_t EFM_GetStatus(void);
|
||||
void EFM_SetBusState(en_efm_bus_sta_t enState);
|
||||
|
||||
void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr);
|
||||
|
||||
en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data);
|
||||
en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data);
|
||||
en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf);
|
||||
en_result_t EFM_SectorErase(uint32_t u32Addr);
|
||||
en_result_t EFM_MassErase(uint32_t u32Addr);
|
||||
|
||||
en_result_t EFM_OtpLock(uint32_t u32Addr);
|
||||
stc_efm_unique_id_t EFM_ReadUID(void);
|
||||
|
||||
|
||||
//@} // EfmGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EFM_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EFM_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -1,205 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_emb.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EMBGroup EMB description @endlink
|
||||
**
|
||||
** - 2018-11-24 CDT First version for Device Driver Library of EMB.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __HC32F460_EMB_H__
|
||||
#define __HC32F460_EMB_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EMB_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup EMBGroup Emergency Brake(EMB)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB status enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_status
|
||||
{
|
||||
EMBFlagPortIn = 0u, ///< EMB port in brake flag
|
||||
EMBFlagPWMSame = 1u, ///< EMB PWM same brake flag
|
||||
EMBFlagCmp = 2u, ///< EMB CMP brake flag
|
||||
EMBFlagOSCFail = 3u, ///< EMB oscillator fail brake flag
|
||||
EMBPortInState = 4u, ///< EMB port in state
|
||||
EMBPWMState = 5u, ///< EMB PWM same state
|
||||
} en_emb_status_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB status clear(recover) enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_status_clr
|
||||
{
|
||||
EMBPortInFlagClr = 0u, ///< EMB port in brake flag clear
|
||||
EMBPWMSameFlagCLr = 1u, ///< EMB PWM same brake flag clear
|
||||
EMBCmpFlagClr = 2u, ///< EMB CMP brake flag clear
|
||||
EMBOSCFailFlagCLr = 3u, ///< EMB oscillator fail brake flag clear
|
||||
} en_emb_status_clr_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB irq enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_irq_type
|
||||
{
|
||||
PORTBrkIrq = 0u, ///< EMB port brake interrupt
|
||||
PWMSmBrkIrq = 1u, ///< EMB PWM same brake interrupt
|
||||
CMPBrkIrq = 2u, ///< EMB CMP brake interrupt
|
||||
OSCFailBrkIrq = 3u, ///< EMB oscillator fail brake interrupt
|
||||
} en_emb_irq_type_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB port in filter enumeration
|
||||
******************************************************************************/
|
||||
typedef enum en_emb_port_filter
|
||||
{
|
||||
EMBPortFltDiv0 = 0u, ///< EMB port in filter with PCLK clock
|
||||
EMBPortFltDiv8 = 1u, ///< EMB port in filter with PCLK/8 clock
|
||||
EMBPortFltDiv32 = 2u, ///< EMB port in filter with PCLK/32 clock
|
||||
EMBPortFltDiv128 = 3u, ///< EMB port in filter with PCLK/128 clock
|
||||
} en_emb_port_filter_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB CR0 for timer6 config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_ctrl_timer6
|
||||
{
|
||||
bool bEnPortBrake; ///< Enable port brake
|
||||
bool bEnCmp1Brake; ///< Enable CMP1 brake
|
||||
bool bEnCmp2Brake; ///< Enable CMP2 brake
|
||||
bool bEnCmp3Brake; ///< Enable CMP3 brake
|
||||
bool bEnOSCFailBrake; ///< Enable OSC fail brake
|
||||
bool bEnTimer61PWMSBrake; ///< Enable tiemr61 PWM same brake
|
||||
bool bEnTimer62PWMSBrake; ///< Enable tiemr62 PWM same brake
|
||||
bool bEnTimer63PWMSBrake; ///< Enable tiemr63 PWM same brake
|
||||
en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection
|
||||
bool bEnPorInFlt; ///< Enable port in filter
|
||||
bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel
|
||||
}stc_emb_ctrl_timer6_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB CR1~3 for timer4x config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_ctrl_timer4
|
||||
{
|
||||
bool bEnPortBrake; ///< Enable port brake
|
||||
bool bEnCmp1Brake; ///< Enable CMP1 brake
|
||||
bool bEnCmp2Brake; ///< Enable CMP2 brake
|
||||
bool bEnCmp3Brake; ///< Enable CMP3 brake
|
||||
bool bEnOSCFailBrake; ///< Enable OS fail brake
|
||||
bool bEnTimer4xWHLSammeBrake; ///< Enable tiemr4x PWM WH WL same brake
|
||||
bool bEnTimer4xVHLSammeBrake; ///< Enable tiemr4x PWM VH VL same brake
|
||||
bool bEnTimer4xUHLSammeBrake; ///< Enable tiemr4x PWM UH UL same brake
|
||||
en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection
|
||||
bool bEnPorInFlt; ///< Enable port in filter
|
||||
bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel
|
||||
}stc_emb_ctrl_timer4_t;
|
||||
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB PWM level detect timer6 config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_pwm_level_timer6
|
||||
{
|
||||
bool bEnTimer61HighLevelDect; ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnTimer62HighLevelDect; ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnTimer63HighLevelDect; ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel
|
||||
}stc_emb_pwm_level_timer6_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief EMB PWM level detect timer4x config
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef struct stc_emb_pwm_level_timer4
|
||||
{
|
||||
bool bEnUHLPhaseHighLevelDect; ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnVHLPhaseHighLevelDect; ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel
|
||||
bool bEnWHLphaseHighLevelDect; ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel
|
||||
}stc_emb_pwm_level_timer4_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/* IRQ config */
|
||||
en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx,
|
||||
en_emb_irq_type_t enEMBIrq,
|
||||
bool bEn);
|
||||
/* Get status(flag) */
|
||||
bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus);
|
||||
/* Status(flag) clear (recover) */
|
||||
en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx,
|
||||
en_emb_status_clr_t enStatusClr);
|
||||
/* Control Register(CTL) config for timer6 */
|
||||
en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR);
|
||||
/* Control Register(CTL) config for timer4 */
|
||||
en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx,
|
||||
const stc_emb_ctrl_timer4_t* pstcEMBConfigCR);
|
||||
/* PWM level detect (short detection) selection config for timer6 */
|
||||
en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv);
|
||||
/* PWM level detect (short detection) selection config for timer4 */
|
||||
en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx,
|
||||
const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv);
|
||||
/* Software brake */
|
||||
en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn);
|
||||
|
||||
//@} // EMBGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EMB_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EMB_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,176 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file hc32f460_event_port.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link EventPortGroup EventPort description @endlink
|
||||
**
|
||||
** - 2018-12-07 CDT First version for Device Driver Library of EventPort.
|
||||
**
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HC32F460_EVENT_PORT_H__
|
||||
#define __HC32F460_EVENT_PORT_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup EventPortGroup Event Port (EventPort)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port Index enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_port
|
||||
{
|
||||
EventPort1 = 0, ///< Event port 1
|
||||
EventPort2 = 1, ///< Event port 2
|
||||
EventPort3 = 2, ///< Event port 3
|
||||
EventPort4 = 3, ///< Event port 4
|
||||
}en_event_port_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port Pin enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_pin
|
||||
{
|
||||
EventPin00 = 1u << 0, ///< Event port Pin 00
|
||||
EventPin01 = 1u << 1, ///< Event port Pin 01
|
||||
EventPin02 = 1u << 2, ///< Event port Pin 02
|
||||
EventPin03 = 1u << 3, ///< Event port Pin 03
|
||||
EventPin04 = 1u << 4, ///< Event port Pin 04
|
||||
EventPin05 = 1u << 5, ///< Event port Pin 05
|
||||
EventPin06 = 1u << 6, ///< Event port Pin 06
|
||||
EventPin07 = 1u << 7, ///< Event port Pin 07
|
||||
EventPin08 = 1u << 8, ///< Event port Pin 08
|
||||
EventPin09 = 1u << 9, ///< Event port Pin 09
|
||||
EventPin10 = 1u << 10, ///< Event port Pin 10
|
||||
EventPin11 = 1u << 11, ///< Event port Pin 11
|
||||
EventPin12 = 1u << 12, ///< Event port Pin 12
|
||||
EventPin13 = 1u << 13, ///< Event port Pin 13
|
||||
EventPin14 = 1u << 14, ///< Event port Pin 14
|
||||
EventPin15 = 1u << 15, ///< Event port Pin 15
|
||||
EventPinAll= 0xFFFF, ///< All event pins are selected
|
||||
}en_event_pin_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port common trigger source select
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_port_com_trigger
|
||||
{
|
||||
EpComTrigger_1 = 0x1, ///< Select common trigger 1.
|
||||
EpComTrigger_2 = 0x2, ///< Select common trigger 2.
|
||||
EpComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
|
||||
} en_event_port_com_trigger_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event Port direction enumeration
|
||||
**
|
||||
******************************************************************************/
|
||||
typedef enum en_event_port_dir
|
||||
{
|
||||
EventPortIn = 0, ///< Event Port direction 'IN'
|
||||
EventPortOut = 1, ///< Event Port direction 'OUT'
|
||||
}en_event_port_dir_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Enumeration to filter clock setting for Event port detect
|
||||
**
|
||||
** \note
|
||||
******************************************************************************/
|
||||
typedef enum en_ep_flt_clk
|
||||
{
|
||||
Pclk1Div1 = 0u, ///< PCLK1 as EP filter clock source
|
||||
Pclk1Div8 = 1u, ///< PCLK1 div8 as EP filter clock source
|
||||
Pclk1Div32 = 2u, ///< PCLK1 div32 as EP filter clock source
|
||||
Pclk1Div64 = 3u, ///< PCLK1 div64 as EP filter clock source
|
||||
}en_ep_flt_clk_t;
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief Event port init structure definition
|
||||
******************************************************************************/
|
||||
typedef struct stc_event_port_init
|
||||
{
|
||||
en_event_port_dir_t enDirection; ///< Input/Output setting
|
||||
en_functional_state_t enReset; ///< Corresponding pin reset after triggered
|
||||
en_functional_state_t enSet; ///< Corresponding pin set after triggered
|
||||
en_functional_state_t enRisingDetect; ///< Rising edge detect enable
|
||||
en_functional_state_t enFallingDetect;///< Falling edge detect enable
|
||||
en_functional_state_t enFilter; ///< Filter clock source select
|
||||
en_ep_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_ep_flt_clk_t for details
|
||||
}stc_event_port_init_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort, \
|
||||
uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit);
|
||||
extern en_result_t EVENTPORT_DeInit(void);
|
||||
extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \
|
||||
en_event_src_t enTriggerSrc);
|
||||
void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \
|
||||
en_event_port_com_trigger_t enComTrigger, \
|
||||
en_functional_state_t enState);
|
||||
extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort);
|
||||
extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, \
|
||||
en_event_pin_t enEventPin);
|
||||
extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, \
|
||||
en_event_pin_t u16EventPin);
|
||||
extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, \
|
||||
en_event_pin_t u16EventPin);
|
||||
|
||||
//@} // EventPortGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DDL_EVENT_PORT_ENABLE */
|
||||
|
||||
#endif /* __HC32F460_EVENT_PORT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
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Reference in New Issue
Block a user