mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-03-27 17:45:13 +08:00
first commit ra6m3-ek
This commit is contained in:
Rbb666
committed by
Man, Jianting (Meco)
Man, Jianting (Meco)
parent
5ff358fec6
commit
622062aaec
@@ -53,6 +53,9 @@ if GetDepend(['BSP_USING_CAN']):
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if GetDepend(['BSP_USING_SDHI']):
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src += ['drv_sdhi.c']
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if GetDepend(['BSP_USING_LCD']):
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src += ['drv_lcd.c']
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path = [cwd]
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path += [cwd + '/config']
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@@ -39,7 +39,7 @@ extern "C"
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#endif
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#endif /* SOC_SERIES_R7FA6M5 */
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#ifdef SOC_SERIES_R7FA6M5
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#if (defined(SOC_SERIES_R7FA6M3)) || (defined(SOC_SERIES_R7FA6M4))
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#include "ra6m4/uart_config.h"
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#ifdef BSP_USING_ADC
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274
bsp/renesas/libraries/HAL_Drivers/drv_lcd.c
Normal file
274
bsp/renesas/libraries/HAL_Drivers/drv_lcd.c
Normal file
@@ -0,0 +1,274 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-24 Rbb666 the first version
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*/
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#include <rtthread.h>
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#if (defined(BSP_USING_LCD)) || (defined(SOC_SERIES_R7FA6M3))
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#include <lcd_port.h>
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#include "r_display_api.h"
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#include "hal_data.h"
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//#define DRV_DEBUG
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//#define LOG_TAG "drv.lcd"
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//#include <drv_log.h>
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struct drv_lcd_device
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{
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struct rt_device parent;
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struct rt_device_graphic_info lcd_info;
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void *framebuffer;
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};
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struct drv_lcd_device _lcd;
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uint16_t screen_rotation;
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uint16_t *lcd_current_working_buffer = (uint16_t *)&fb_background[0];
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void turn_on_lcd_backlight(void)
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{
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rt_pin_mode(LCD_BL_PIN, PIN_MODE_OUTPUT); /* LCD_BL */
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rt_pin_write(LCD_BL_PIN, PIN_HIGH);
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}
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void ra_bsp_lcd_init(void)
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{
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fsp_err_t error;
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// Set screen rotation to default view
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screen_rotation = ROTATION_ZERO;
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/** Display driver open */
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error = R_GLCDC_Open(&g_display0_ctrl, &g_display0_cfg);
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if (FSP_SUCCESS == error)
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{
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/** Display driver start */
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error = R_GLCDC_Start(&g_display0_ctrl);
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}
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}
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void ra_bsp_lcd_set_display_buffer(uint8_t index)
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{
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R_GLCDC_BufferChange(&g_display0_ctrl, fb_background[index - 1], DISPLAY_FRAME_LAYER_1);
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}
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void ra_bsp_lcd_set_working_buffer(uint8_t index)
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{
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if (index >= 1 && index <= 2)
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{
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lcd_current_working_buffer = (uint16_t *)fb_background[index - 1];
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}
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}
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void ra_bsp_lcd_enable_double_buffer(void)
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{
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ra_bsp_lcd_set_display_buffer(1);
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ra_bsp_lcd_set_working_buffer(2);
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}
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void ra_bsp_lcd_clear(uint16_t color)
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{
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for (uint32_t i = 0; i < (LCD_WIDTH * LCD_HEIGHT); i++)
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{
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lcd_current_working_buffer[i] = color;
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}
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}
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void ra_bsp_lcd_swap_buffer(void)
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{
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if (lcd_current_working_buffer == (uint16_t *)fb_background[0])
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{
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ra_bsp_lcd_set_display_buffer(1);
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ra_bsp_lcd_set_working_buffer(2);
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}
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else
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{
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ra_bsp_lcd_set_display_buffer(2);
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ra_bsp_lcd_set_working_buffer(1);
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}
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}
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void bsp_lcd_draw_pixel(uint32_t x, uint32_t y, uint16_t color)
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{
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// Verify pixel is within LCD range
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if ((x < LCD_WIDTH) && (y < LCD_HEIGHT))
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{
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switch (screen_rotation)
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{
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case ROTATION_ZERO:
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{
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lcd_current_working_buffer[(y * LCD_WIDTH) + x] = color;
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break;
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}
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case ROTATION_180:
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{
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lcd_current_working_buffer[((LCD_HEIGHT - y) * LCD_WIDTH) + (LCD_WIDTH - x)] = color;
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break;
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}
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default:
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{
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lcd_current_working_buffer[(y * LCD_WIDTH) + x] = color;
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break;
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}
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}
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}
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else
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{
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rt_kprintf("draw pixel outof range:%d,%d\n", x, y);
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}
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}
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void lcd_fill_array(uint16_t x_start, uint16_t y_start, uint16_t x_end, uint16_t y_end, void *pcolor)
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{
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uint16_t *pixel = RT_NULL;
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uint16_t cycle_y, x_offset = 0;
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pixel = (uint16_t *)pcolor;
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for (cycle_y = y_start; cycle_y <= y_end;)
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{
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for (x_offset = 0; x_start + x_offset <= x_end; x_offset++)
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{
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bsp_lcd_draw_pixel(x_start + x_offset, cycle_y, *pixel++);
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}
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cycle_y++;
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}
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}
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static rt_err_t ra_lcd_init(rt_device_t device)
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{
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RT_ASSERT(device != RT_NULL);
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ra_bsp_lcd_init();
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return RT_EOK;
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}
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static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args)
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{
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struct drv_lcd_device *lcd = (struct drv_lcd_device *)device;
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switch (cmd)
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{
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case RTGRAPHIC_CTRL_RECT_UPDATE:
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{
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struct rt_device_rect_info *info = (struct rt_device_rect_info *)args;
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(void)info; /* nothing, right now */
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rt_kprintf("update screen...\n");
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}
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break;
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case RTGRAPHIC_CTRL_POWERON:
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rt_pin_write(LCD_BL_PIN, PIN_HIGH);
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break;
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case RTGRAPHIC_CTRL_POWEROFF:
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rt_pin_write(LCD_BL_PIN, PIN_LOW);
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break;
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case RTGRAPHIC_CTRL_GET_INFO:
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{
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struct rt_device_graphic_info *info = (struct rt_device_graphic_info *)args;
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RT_ASSERT(info != RT_NULL);
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info->pixel_format = lcd->lcd_info.pixel_format;
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info->bits_per_pixel = 16;
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info->width = lcd->lcd_info.width;
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info->height = lcd->lcd_info.height;
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info->framebuffer = lcd->lcd_info.framebuffer;
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}
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break;
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case RTGRAPHIC_CTRL_SET_MODE:
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break;
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}
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return RT_EOK;
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}
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int rt_hw_lcd_init(void)
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{
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rt_err_t result = RT_EOK;
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struct rt_device *device = &_lcd.parent;
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/* memset _lcd to zero */
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memset(&_lcd, 0x00, sizeof(_lcd));
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/* config LCD dev info */
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_lcd.lcd_info.height = LCD_HEIGHT;
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_lcd.lcd_info.width = LCD_WIDTH;
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_lcd.lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
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_lcd.lcd_info.pixel_format = LCD_PIXEL_FORMAT;
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_lcd.lcd_info.framebuffer = (uint8_t *)&fb_background[0];
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device->type = RT_Device_Class_Graphic;
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#ifdef RT_USING_DEVICE_OPS
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device->ops = &lcd_ops;
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#else
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device->init = ra_lcd_init;
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device->control = ra_lcd_control;
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#endif
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/* register lcd device */
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rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR);
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turn_on_lcd_backlight();
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// Initialize lcd controller
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ra_lcd_init(device);
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ra_bsp_lcd_set_display_buffer(1);
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screen_rotation = ROTATION_ZERO;
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return result;
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}
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INIT_DEVICE_EXPORT(rt_hw_lcd_init);
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int lcd_test()
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{
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struct drv_lcd_device *lcd;
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lcd = (struct drv_lcd_device *)rt_device_find("lcd");
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while (1)
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{
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/* red */
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for (int i = 0; i < LCD_BUF_SIZE / 2; i++)
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{
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lcd->lcd_info.framebuffer[2 * i] = 0x00;
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lcd->lcd_info.framebuffer[2 * i + 1] = 0xF8;
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}
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lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
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rt_thread_mdelay(1000);
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/* green */
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for (int i = 0; i < LCD_BUF_SIZE / 2; i++)
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{
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lcd->lcd_info.framebuffer[2 * i] = 0xE0;
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lcd->lcd_info.framebuffer[2 * i + 1] = 0x07;
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}
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lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
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rt_thread_mdelay(1000);
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/* blue */
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for (int i = 0; i < LCD_BUF_SIZE / 2; i++)
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{
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lcd->lcd_info.framebuffer[2 * i] = 0x1F;
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lcd->lcd_info.framebuffer[2 * i + 1] = 0x00;
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}
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lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
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rt_thread_mdelay(1000);
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}
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}
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MSH_CMD_EXPORT(lcd_test, lcd_test);
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#endif /* BSP_USING_LCD */
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@@ -3,6 +3,12 @@ config SOC_FAMILY_RENESAS
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bool
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default n
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config SOC_SERIES_R7FA6M3
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bool
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select ARCH_ARM_CORTEX_M4
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select SOC_FAMILY_RENESAS
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default n
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config SOC_SERIES_R7FA6M4
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bool
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select ARCH_ARM_CORTEX_M4
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724
bsp/renesas/ra6m3-ek/.config
Normal file
724
bsp/renesas/ra6m3-ek/.config
Normal file
File diff suppressed because it is too large
Load Diff
5
bsp/renesas/ra6m3-ek/.gitignore
vendored
Normal file
5
bsp/renesas/ra6m3-ek/.gitignore
vendored
Normal file
@@ -0,0 +1,5 @@
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/RTE
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/Listings
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/Objects
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ra_cfg.txt
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9
bsp/renesas/ra6m3-ek/.ignore_format.yml
Normal file
9
bsp/renesas/ra6m3-ek/.ignore_format.yml
Normal file
@@ -0,0 +1,9 @@
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# files format check exclude path, please follow the instructions below to modify;
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# If you need to exclude an entire folder, add the folder path in dir_path;
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# If you need to exclude a file, add the path to the file in file_path.
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dir_path:
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- ra
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- ra_gen
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- ra_cfg
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- RTE
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19
bsp/renesas/ra6m3-ek/.settings/standalone.prefs
Normal file
19
bsp/renesas/ra6m3-ek/.settings/standalone.prefs
Normal file
@@ -0,0 +1,19 @@
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#Fri Nov 18 18:05:07 CST 2022
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
|
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|546480625,ra/fsp/inc/fsp_common_api.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1728953905,ra/fsp/inc/fsp_features.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2425160085,ra/fsp/inc/api/bsp_api.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2208590403,ra/fsp/inc/instances/r_ioport.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3297195641,ra/fsp/inc/fsp_version.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1939984091,ra/fsp/inc/api/r_ioport_api.h
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c
|
||||
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.136564520=false
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries=
|
||||
29
bsp/renesas/ra6m3-ek/Kconfig
Normal file
29
bsp/renesas/ra6m3-ek/Kconfig
Normal file
@@ -0,0 +1,29 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
# you can change the RTT_ROOT default "../.." to your rtthread_root,
|
||||
# example : default "F:/git_repositories/rt-thread"
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
config ENV_DIR
|
||||
string
|
||||
option env="ENV_ROOT"
|
||||
default "/"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../libraries/Kconfig"
|
||||
source "$BSP_DIR/board/Kconfig"
|
||||
36
bsp/renesas/ra6m3-ek/R7FA6M3AH3CFC.pincfg
Normal file
36
bsp/renesas/ra6m3-ek/R7FA6M3AH3CFC.pincfg
Normal file
@@ -0,0 +1,36 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
|
||||
<v1:pinMappingsRef version="2.03" file="" />
|
||||
<v1:deviceSetting id="renesas.ra6m3_fc" pattern="R7FA6M3****FC">
|
||||
<v1:packageSetting id="renesas.176lqfp" />
|
||||
</v1:deviceSetting>
|
||||
<v1:configSetting configurationId="debug0.mode" altId="debug0.mode.jtag" />
|
||||
<v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
|
||||
<v1:configSetting configurationId="p300" altId="p300.debug0.tck">
|
||||
<v1:connectionSetting altId="debug0.tck.p300" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="debug0.tck" altId="debug0.tck.p300">
|
||||
<v1:connectionSetting altId="p300.debug0.tck" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
|
||||
<v1:configSetting configurationId="p108" altId="p108.debug0.tms">
|
||||
<v1:connectionSetting altId="debug0.tms.p108" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="debug0.tms" altId="debug0.tms.p108">
|
||||
<v1:connectionSetting altId="p108.debug0.tms" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="p109.gpio_mode" altId="p109.gpio_mode.gpio_mode_peripheral" />
|
||||
<v1:configSetting configurationId="p109" altId="p109.debug0.tdo">
|
||||
<v1:connectionSetting altId="debug0.tdo.p109" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="debug0.tdo" altId="debug0.tdo.p109">
|
||||
<v1:connectionSetting altId="p109.debug0.tdo" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="p110.gpio_mode" altId="p110.gpio_mode.gpio_mode_peripheral" />
|
||||
<v1:configSetting configurationId="p110" altId="p110.debug0.tdi">
|
||||
<v1:connectionSetting altId="debug0.tdi.p110" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="debug0.tdi" altId="debug0.tdi.p110">
|
||||
<v1:connectionSetting altId="p110.debug0.tdi" />
|
||||
</v1:configSetting>
|
||||
</v1:pinSettings>
|
||||
27
bsp/renesas/ra6m3-ek/SConscript
Normal file
27
bsp/renesas/ra6m3-ek/SConscript
Normal file
@@ -0,0 +1,27 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = []
|
||||
CPPPATH = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
print("\nThe current project does not support IAR build\n")
|
||||
Return('group')
|
||||
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
if GetOption('target') != 'mdk5':
|
||||
CPPPATH = [cwd]
|
||||
src = Glob('./src/*.c')
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
54
bsp/renesas/ra6m3-ek/SConstruct
Normal file
54
bsp/renesas/ra6m3-ek/SConstruct
Normal file
@@ -0,0 +1,54 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
77
bsp/renesas/ra6m3-ek/board/Kconfig
Normal file
77
bsp/renesas/ra6m3-ek/board/Kconfig
Normal file
@@ -0,0 +1,77 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_R7FA6M4AF
|
||||
bool
|
||||
select SOC_SERIES_R7FA6M3
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
source "../libraries/HAL_Drivers/Kconfig"
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
select RT_USING_SERIAL_V2
|
||||
if BSP_USING_UART
|
||||
|
||||
menuconfig BSP_USING_UART7
|
||||
bool "Enable UART7"
|
||||
default n
|
||||
if BSP_USING_UART7
|
||||
config BSP_UART7_RX_USING_DMA
|
||||
bool "Enable UART7 RX DMA"
|
||||
depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART7_TX_USING_DMA
|
||||
bool "Enable UART7 TX DMA"
|
||||
depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART7_RX_BUFSIZE
|
||||
int "Set UART7 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART7_TX_BUFSIZE
|
||||
int "Set UART7 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
endif
|
||||
|
||||
config BSP_USING_LCD
|
||||
bool "Enable LCD"
|
||||
select BSP_USING_GPIO
|
||||
select BSP_USING_LCD
|
||||
default n
|
||||
|
||||
config BSP_USING_LVGL
|
||||
bool "Enable LVGL for LCD"
|
||||
select PKG_USING_LVGL
|
||||
select BSP_USING_TOUCH
|
||||
default n
|
||||
|
||||
if BSP_USING_LVGL
|
||||
config BSP_USING_LVGL_DEMO
|
||||
bool "Enable LVGL demo"
|
||||
select PKG_USING_LV_MUSIC_DEMO
|
||||
default y
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
endmenu
|
||||
16
bsp/renesas/ra6m3-ek/board/SConscript
Normal file
16
bsp/renesas/ra6m3-ek/board/SConscript
Normal file
@@ -0,0 +1,16 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
list = os.listdir(cwd)
|
||||
CPPPATH = [cwd]
|
||||
src = Glob('*.c')
|
||||
|
||||
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
38
bsp/renesas/ra6m3-ek/board/board.h
Normal file
38
bsp/renesas/ra6m3-ek/board/board.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-10 Sherman first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RA_SRAM_SIZE 640 /* The SRAM size of the chip needs to be modified */
|
||||
#define RA_SRAM_END (0x20000000 + RA_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RAM_END$$ZI$$Base;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
|
||||
#elif __ICCARM__
|
||||
#pragma section="CSTACK"
|
||||
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||
#else
|
||||
extern int __RAM_segment_used_end__;
|
||||
#define HEAP_BEGIN (&__RAM_segment_used_end__)
|
||||
#endif
|
||||
|
||||
#define HEAP_END RA_SRAM_END
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
16
bsp/renesas/ra6m3-ek/board/lvgl/SConscript
Normal file
16
bsp/renesas/ra6m3-ek/board/lvgl/SConscript
Normal file
@@ -0,0 +1,16 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
group = []
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
group = group + DefineGroup('LVGL-port', src, depend = ['BSP_USING_LVGL'], CPPPATH = CPPPATH)
|
||||
Return('group')
|
||||
17
bsp/renesas/ra6m3-ek/board/lvgl/demo/SConscript
Normal file
17
bsp/renesas/ra6m3-ek/board/lvgl/demo/SConscript
Normal file
@@ -0,0 +1,17 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
group = []
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
group = group + DefineGroup('LVGL-demo', src, depend = ['BSP_USING_LVGL', 'BSP_USING_LVGL_DEMO'], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
17
bsp/renesas/ra6m3-ek/board/lvgl/demo/lv_demo.c
Normal file
17
bsp/renesas/ra6m3-ek/board/lvgl/demo/lv_demo.c
Normal file
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-17 Meco Man First version
|
||||
* 2022-05-10 Meco Man improve rt-thread initialization process
|
||||
*/
|
||||
|
||||
void lv_user_gui_init(void)
|
||||
{
|
||||
/* display demo; you may replace with your LVGL application at here */
|
||||
extern void lv_demo_music(void);
|
||||
lv_demo_music();
|
||||
}
|
||||
37
bsp/renesas/ra6m3-ek/board/lvgl/lv_conf.h
Normal file
37
bsp/renesas/ra6m3-ek/board/lvgl/lv_conf.h
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-18 Meco Man First version
|
||||
*/
|
||||
|
||||
#ifndef LV_CONF_H
|
||||
#define LV_CONF_H
|
||||
|
||||
/* Enable additional color format support */
|
||||
#define DLG_LVGL_CF 1
|
||||
|
||||
/* Enable sub byte color formats to be swapped. If disabled, which is recommended for
|
||||
* performance, bitmaps need to be in correct order */
|
||||
#define DLG_LVGL_CF_SUB_BYTE_SWAP 0
|
||||
|
||||
#define LV_USE_PERF_MONITOR 1
|
||||
#define LV_COLOR_DEPTH 16
|
||||
#define LV_HOR_RES_MAX 480
|
||||
#define LV_VER_RES_MAX 272
|
||||
|
||||
#define DLG_LVGL_USE_GPU_RA6M3 0
|
||||
|
||||
#ifdef PKG_USING_LV_MUSIC_DEMO
|
||||
/* music player demo */
|
||||
#define LV_USE_DEMO_RTT_MUSIC 1
|
||||
#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
|
||||
#define LV_FONT_MONTSERRAT_12 1
|
||||
#define LV_FONT_MONTSERRAT_16 1
|
||||
#define LV_COLOR_SCREEN_TRANSP 0
|
||||
#endif /* PKG_USING_LV_MUSIC_DEMO */
|
||||
|
||||
#endif
|
||||
168
bsp/renesas/ra6m3-ek/board/lvgl/lv_port_disp.c
Normal file
168
bsp/renesas/ra6m3-ek/board/lvgl/lv_port_disp.c
Normal file
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-11-24 Rbb666 The first version
|
||||
*/
|
||||
#include <lvgl.h>
|
||||
#include "lcd_port.h"
|
||||
#include "hal_data.h"
|
||||
|
||||
#if DLG_LVGL_USE_GPU_RA6M3
|
||||
#include "lv_port_gpu.h"
|
||||
#endif
|
||||
|
||||
#define COLOR_BUFFER (LV_HOR_RES_MAX * LV_VER_RES_MAX / 4)
|
||||
|
||||
/*A static or global variable to store the buffers*/
|
||||
static lv_disp_draw_buf_t disp_buf;
|
||||
|
||||
/*Descriptor of a display driver*/
|
||||
static lv_disp_drv_t disp_drv;
|
||||
|
||||
/*Static or global buffer(s). The second buffer is optional*/
|
||||
// 0x1FFE0000 0x20040000
|
||||
__attribute__((section(".ARM.__at_0x1FFE0000"))) lv_color_t buf_1[COLOR_BUFFER];
|
||||
|
||||
static uint8_t lvgl_ready_done = RT_EBUSY;
|
||||
|
||||
static rt_device_t device;
|
||||
static struct rt_device_graphic_info info;
|
||||
static rt_sem_t trans_done_semphr = RT_NULL;
|
||||
|
||||
void _rm_guix_port_display_callback(display_callback_args_t *p_args)
|
||||
{
|
||||
if (lvgl_ready_done != RT_EOK)
|
||||
return;
|
||||
|
||||
if (DISPLAY_EVENT_LINE_DETECTION == p_args->event)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
lv_disp_flush_ready((lv_disp_drv_t *)&disp_drv);
|
||||
|
||||
rt_sem_release(trans_done_semphr);
|
||||
|
||||
/* exit interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
}
|
||||
|
||||
// Wait until Vsync is triggered through callback function
|
||||
void vsync_wait(void)
|
||||
{
|
||||
rt_sem_take(trans_done_semphr, RT_WAITING_FOREVER);
|
||||
}
|
||||
|
||||
static void color_to16_maybe(lv_color16_t *dst, lv_color_t *src)
|
||||
{
|
||||
#if (LV_COLOR_DEPTH == 16)
|
||||
dst->full = src->full;
|
||||
#else
|
||||
dst->ch.blue = src->ch.blue;
|
||||
dst->ch.green = src->ch.green;
|
||||
dst->ch.red = src->ch.red;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disp_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
|
||||
{
|
||||
int x1, x2, y1, y2;
|
||||
|
||||
x1 = area->x1;
|
||||
x2 = area->x2;
|
||||
y1 = area->y1;
|
||||
y2 = area->y2;
|
||||
|
||||
/*Return if the area is out the screen*/
|
||||
if (x2 < 0)
|
||||
return;
|
||||
if (y2 < 0)
|
||||
return;
|
||||
if (x1 > info.width - 1)
|
||||
return;
|
||||
if (y1 > info.height - 1)
|
||||
return;
|
||||
|
||||
/*Truncate the area to the screen*/
|
||||
int32_t act_x1 = x1 < 0 ? 0 : x1;
|
||||
int32_t act_y1 = y1 < 0 ? 0 : y1;
|
||||
int32_t act_x2 = x2 > info.width - 1 ? info.width - 1 : x2;
|
||||
int32_t act_y2 = y2 > info.height - 1 ? info.height - 1 : y2;
|
||||
|
||||
uint32_t x;
|
||||
uint32_t y;
|
||||
long int location = 0;
|
||||
|
||||
#if DLG_LVGL_USE_GPU_RA6M3
|
||||
lv_port_gpu_flush();
|
||||
#endif
|
||||
|
||||
/* color_p is a buffer pointer; the buffer is provided by LVGL */
|
||||
lv_color16_t *fbp16 = (lv_color16_t *)info.framebuffer;
|
||||
|
||||
for (y = act_y1; y <= act_y2; y++)
|
||||
{
|
||||
for (x = act_x1; x <= act_x2; x++)
|
||||
{
|
||||
location = (x) + (y) * info.width;
|
||||
color_to16_maybe(&fbp16[location], color_p);
|
||||
color_p++;
|
||||
}
|
||||
|
||||
color_p += x2 - act_x2;
|
||||
}
|
||||
|
||||
vsync_wait();
|
||||
}
|
||||
|
||||
void lv_port_disp_init(void)
|
||||
{
|
||||
/* LCD Device Init */
|
||||
device = rt_device_find("lcd");
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
if (rt_device_open(device, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
|
||||
{
|
||||
rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info);
|
||||
}
|
||||
|
||||
RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
|
||||
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
|
||||
|
||||
trans_done_semphr = rt_sem_create("lvgl_sem", 1, RT_IPC_FLAG_PRIO);
|
||||
if (trans_done_semphr == RT_NULL)
|
||||
{
|
||||
rt_kprintf("create transform done semphr failed.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*Initialize `disp_buf` with the buffer(s). With only one buffer use NULL instead buf_2 */
|
||||
lv_disp_draw_buf_init(&disp_buf, buf_1, NULL, COLOR_BUFFER);
|
||||
|
||||
lv_disp_drv_init(&disp_drv); /*Basic initialization*/
|
||||
|
||||
/*Set the resolution of the display*/
|
||||
disp_drv.hor_res = LCD_WIDTH;
|
||||
disp_drv.ver_res = LCD_HEIGHT;
|
||||
|
||||
/*Set a display buffer*/
|
||||
disp_drv.draw_buf = &disp_buf;
|
||||
|
||||
/*Used to copy the buffer's content to the display*/
|
||||
disp_drv.flush_cb = disp_flush;
|
||||
|
||||
#if DLG_LVGL_USE_GPU_RA6M3
|
||||
/* Initialize GPU module */
|
||||
lv_port_gpu_init();
|
||||
#endif /* LV_PORT_DISP_GPU_EN */
|
||||
|
||||
/*Finally register the driver*/
|
||||
lv_disp_drv_register(&disp_drv);
|
||||
|
||||
lvgl_ready_done = RT_EOK;
|
||||
}
|
||||
16
bsp/renesas/ra6m3-ek/board/lvgl/lv_port_indev.c
Normal file
16
bsp/renesas/ra6m3-ek/board/lvgl/lv_port_indev.c
Normal file
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-18 Meco Man The first version
|
||||
*/
|
||||
#include <lvgl.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
void lv_port_indev_init(void)
|
||||
{
|
||||
static lv_indev_drv_t indev_drv;
|
||||
}
|
||||
22
bsp/renesas/ra6m3-ek/board/ports/SConscript
Normal file
22
bsp/renesas/ra6m3-ek/board/ports/SConscript
Normal file
@@ -0,0 +1,22 @@
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = []
|
||||
|
||||
if GetDepend(['BSP_USING_RW007']):
|
||||
src += Glob('drv_rw007.c')
|
||||
|
||||
CPPPATH = [cwd]
|
||||
LOCAL_CFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
LOCAL_CFLAGS += ' -std=c99'
|
||||
elif rtconfig.PLATFORM in ['armcc']:
|
||||
LOCAL_CFLAGS += ' --c99'
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
||||
|
||||
Return('group')
|
||||
82
bsp/renesas/ra6m3-ek/board/ports/gpio_cfg.h
Normal file
82
bsp/renesas/ra6m3-ek/board/ports/gpio_cfg.h
Normal file
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-01-19 Sherman first version
|
||||
*/
|
||||
|
||||
/* Number of IRQ channels on the device */
|
||||
#define RA_IRQ_MAX 16
|
||||
|
||||
/* PIN to IRQx table */
|
||||
#define PIN2IRQX_TABLE \
|
||||
{ \
|
||||
switch (pin) \
|
||||
{ \
|
||||
case BSP_IO_PORT_04_PIN_00: \
|
||||
case BSP_IO_PORT_02_PIN_06: \
|
||||
case BSP_IO_PORT_01_PIN_05: \
|
||||
return 0; \
|
||||
case BSP_IO_PORT_02_PIN_05: \
|
||||
case BSP_IO_PORT_01_PIN_01: \
|
||||
case BSP_IO_PORT_01_PIN_04: \
|
||||
return 1; \
|
||||
case BSP_IO_PORT_02_PIN_03: \
|
||||
case BSP_IO_PORT_01_PIN_00: \
|
||||
case BSP_IO_PORT_02_PIN_13: \
|
||||
return 2; \
|
||||
case BSP_IO_PORT_02_PIN_02: \
|
||||
case BSP_IO_PORT_01_PIN_10: \
|
||||
case BSP_IO_PORT_02_PIN_12: \
|
||||
return 3; \
|
||||
case BSP_IO_PORT_04_PIN_02: \
|
||||
case BSP_IO_PORT_01_PIN_11: \
|
||||
case BSP_IO_PORT_04_PIN_11: \
|
||||
return 4; \
|
||||
case BSP_IO_PORT_04_PIN_01: \
|
||||
case BSP_IO_PORT_03_PIN_02: \
|
||||
case BSP_IO_PORT_04_PIN_10: \
|
||||
return 5; \
|
||||
case BSP_IO_PORT_03_PIN_01: \
|
||||
case BSP_IO_PORT_00_PIN_00: \
|
||||
case BSP_IO_PORT_04_PIN_09: \
|
||||
return 6; \
|
||||
case BSP_IO_PORT_00_PIN_01: \
|
||||
case BSP_IO_PORT_04_PIN_08: \
|
||||
return 7; \
|
||||
case BSP_IO_PORT_00_PIN_02: \
|
||||
case BSP_IO_PORT_03_PIN_05: \
|
||||
case BSP_IO_PORT_04_PIN_15: \
|
||||
return 8; \
|
||||
case BSP_IO_PORT_00_PIN_04: \
|
||||
case BSP_IO_PORT_03_PIN_04: \
|
||||
case BSP_IO_PORT_04_PIN_14: \
|
||||
return 9; \
|
||||
case BSP_IO_PORT_00_PIN_05: \
|
||||
case BSP_IO_PORT_07_PIN_09: \
|
||||
return 10; \
|
||||
case BSP_IO_PORT_05_PIN_01: \
|
||||
case BSP_IO_PORT_00_PIN_06: \
|
||||
case BSP_IO_PORT_07_PIN_08: \
|
||||
return 11; \
|
||||
case BSP_IO_PORT_05_PIN_02: \
|
||||
case BSP_IO_PORT_00_PIN_08: \
|
||||
return 12; \
|
||||
case BSP_IO_PORT_00_PIN_15: \
|
||||
case BSP_IO_PORT_00_PIN_09: \
|
||||
return 13; \
|
||||
case BSP_IO_PORT_04_PIN_03: \
|
||||
case BSP_IO_PORT_05_PIN_12: \
|
||||
case BSP_IO_PORT_05_PIN_05: \
|
||||
return 14; \
|
||||
case BSP_IO_PORT_04_PIN_04: \
|
||||
case BSP_IO_PORT_05_PIN_11: \
|
||||
case BSP_IO_PORT_05_PIN_06: \
|
||||
return 15; \
|
||||
default : \
|
||||
return -1; \
|
||||
} \
|
||||
}
|
||||
34
bsp/renesas/ra6m3-ek/board/ports/lcd_port.h
Normal file
34
bsp/renesas/ra6m3-ek/board/ports/lcd_port.h
Normal file
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-07-28 liu2guang the first version for STM32F469NI-Discovery.
|
||||
*/
|
||||
|
||||
#ifndef __DRV_LCD_H_
|
||||
#define __DRV_LCD_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ROTATION_ZERO = 0,
|
||||
ROTATION_090 = 90,
|
||||
ROTATION_180 = 180,
|
||||
ROTATION_270 = 270,
|
||||
} bsp_rotation;
|
||||
|
||||
#define LCD_WIDTH DISPLAY_HSIZE_INPUT0
|
||||
#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0
|
||||
#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1
|
||||
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
|
||||
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
|
||||
|
||||
#define LCD_BL_PIN BSP_IO_PORT_06_PIN_03
|
||||
|
||||
#endif
|
||||
244
bsp/renesas/ra6m3-ek/configuration.xml
Normal file
244
bsp/renesas/ra6m3-ek/configuration.xml
Normal file
@@ -0,0 +1,244 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="7">
|
||||
<generalSettings>
|
||||
<option key="#Board#" value="board.custom"/>
|
||||
<option key="CPU" value="RA6M3"/>
|
||||
<option key="#TargetName#" value="R7FA6M3AH3CFC"/>
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m4"/>
|
||||
<option key="#DeviceCommand#" value="R7FA6M3AH"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA6M3AH3CFC.pincfg"/>
|
||||
<option key="#FSPVersion#" value="3.5.0"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra6m3.R7FA6M3AH3CFC">
|
||||
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||
<property id="config.bsp.rom_size_bytes_hidden" value="2097152"/>
|
||||
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
|
||||
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra6m3">
|
||||
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra6m3.fsp">
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
|
||||
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_start" value="0xFFFFFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_end" value="0xFFFFFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_start" value="0xFFFFFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_end" value="0xFFFFFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
|
||||
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="20000000"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/>
|
||||
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="30000000"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
|
||||
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
|
||||
<property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
|
||||
<property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
|
||||
<property id="config.bsp.common.id1" value=""/>
|
||||
<property id="config.bsp.common.id2" value=""/>
|
||||
<property id="config.bsp.common.id3" value=""/>
|
||||
<property id="config.bsp.common.id4" value=""/>
|
||||
<property id="config.bsp.common.id_fixed" value=""/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x400"/>
|
||||
<property id="config.bsp.common.heap" value="0"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
|
||||
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
|
||||
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
|
||||
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
|
||||
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
|
||||
</config>
|
||||
</raBspConfiguration>
|
||||
<raClockConfiguration>
|
||||
<node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
|
||||
<node id="board.clock.usbmclk.freq" option="board.clock.usbmclk.freq"/>
|
||||
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
|
||||
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
|
||||
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
|
||||
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
|
||||
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
|
||||
<node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
|
||||
<node id="board.clock.pll.mul" option="board.clock.pll.mul.200"/>
|
||||
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
|
||||
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
|
||||
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
|
||||
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
|
||||
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
|
||||
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
|
||||
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
|
||||
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
|
||||
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
|
||||
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
|
||||
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
|
||||
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
|
||||
<node id="board.clock.sdclkout.div" option="board.clock.sdclkout.div.1"/>
|
||||
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
|
||||
<node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
|
||||
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
|
||||
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
|
||||
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
|
||||
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
|
||||
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
|
||||
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
|
||||
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
|
||||
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
|
||||
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
|
||||
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
|
||||
</raClockConfiguration>
|
||||
<raComponentSelection>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Board Support Package Common Files</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>I/O Port</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.8.0+renesas.0.fsp.3.5.0">
|
||||
<description>Arm CMSIS Version 5 - Core (M)</description>
|
||||
<originalPack>Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m3" subgroup="device" variant="R7FA6M3AH3CFC" vendor="Renesas" version="3.5.0">
|
||||
<description>Board support package for R7FA6M3AH3CFC</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m3.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m3" subgroup="device" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Board support package for RA6M3</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m3.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m3" subgroup="fsp" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Board support package for RA6M3 - FSP Data</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m3.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Custom Board Support Files</description>
|
||||
<originalPack>Renesas.RA_board_custom.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>SCI UART</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioportb" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioportc" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioportd" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioporte" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<module id="module.driver.uart_on_sci_uart.136564520">
|
||||
<property id="module.driver.uart.name" value="g_uart7"/>
|
||||
<property id="module.driver.uart.channel" value="7"/>
|
||||
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
|
||||
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
|
||||
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
|
||||
<property id="module.driver.uart.baud" value="115200"/>
|
||||
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
|
||||
<property id="module.driver.uart.baudrate_max_err" value="5"/>
|
||||
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
|
||||
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
|
||||
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
|
||||
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
|
||||
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
|
||||
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
|
||||
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
|
||||
<property id="module.driver.uart.callback" value="user_uart7_callback"/>
|
||||
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
<stack module="module.driver.uart_on_sci_uart.136564520"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
<config id="config.driver.sci_uart">
|
||||
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
|
||||
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
|
||||
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
|
||||
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<pincfg active="true" name="R7FA6M3AH3CFC.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
|
||||
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
|
||||
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
|
||||
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
|
||||
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p401.sci7.txd" configurationId="p401"/>
|
||||
<configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
|
||||
<configSetting altId="p402.sci7.rxd" configurationId="p402"/>
|
||||
<configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/>
|
||||
<configSetting altId="sci7.mode.asynchronous.free" configurationId="sci7.mode"/>
|
||||
<configSetting altId="sci7.rxd.p402" configurationId="sci7.rxd"/>
|
||||
<configSetting altId="sci7.txd.p401" configurationId="sci7.txd"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
765
bsp/renesas/ra6m3-ek/project.uvoptx
Normal file
765
bsp/renesas/ra6m3-ek/project.uvoptx
Normal file
File diff suppressed because it is too large
Load Diff
808
bsp/renesas/ra6m3-ek/project.uvprojx
Normal file
808
bsp/renesas/ra6m3-ek/project.uvprojx
Normal file
File diff suppressed because it is too large
Load Diff
25
bsp/renesas/ra6m3-ek/ra/SConscript
Normal file
25
bsp/renesas/ra6m3-ek/ra/SConscript
Normal file
@@ -0,0 +1,25 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = []
|
||||
group = []
|
||||
CPPPATH = []
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
print("\nThe current project does not support IAR build\n")
|
||||
Return('group')
|
||||
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
if GetOption('target') != 'mdk5':
|
||||
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
|
||||
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
|
||||
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
|
||||
src += Glob(cwd + '/fsp/src/r_*/*.c')
|
||||
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
|
||||
cwd + '/fsp/inc',
|
||||
cwd + '/fsp/inc/api',
|
||||
cwd + '/fsp/inc/instances',]
|
||||
|
||||
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
|
||||
Return('group')
|
||||
@@ -0,0 +1,411 @@
|
||||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.1
|
||||
* @date 19. April 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,283 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
2211
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
Normal file
2211
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2297
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
Normal file
2297
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1943
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
Normal file
1943
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
3265
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
Normal file
3265
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
3265
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
Normal file
3265
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
Normal file
File diff suppressed because it is too large
Load Diff
2129
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
Normal file
2129
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
4278
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
Normal file
4278
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
Normal file
File diff suppressed because it is too large
Load Diff
2366
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
Normal file
2366
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
1030
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
Normal file
1030
bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user