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https://github.com/RT-Thread/rt-thread.git
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新增对MDK5的编译支持
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FuChao
@@ -0,0 +1,35 @@
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/**
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******************************************************************************
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* @file lib_CodeRAM.c
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* @author Application Team
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* @version V4.4.0
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* @date 2019-01-18
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* @brief Codes executed in SRAM.
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******************************************************************************
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* @attention
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "lib_CodeRAM.h"
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#ifndef __GNUC__
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/**
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* @brief Flash deep standby, enter idle mode.
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* @note This function is executed in RAM.
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* @param None
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* @retval None
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*/
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__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void)
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{
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/* Flash deep standby */
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FLASH->PASS = 0x55AAAA55;
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FLASH->DSTB = 0xAA5555AA;
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/* Enter Idle mode */
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SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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__WFI();
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}
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#endif
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/*********************************** END OF FILE ******************************/
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648
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c
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648
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c
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File diff suppressed because it is too large
Load Diff
175
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c
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175
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c
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@@ -0,0 +1,175 @@
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/**
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******************************************************************************
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* @file lib_cortex.c
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* @author Application Team
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* @version V4.4.0
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* @date 2018-09-27
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* @brief Cortex module driver.
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******************************************************************************
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* @attention
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "lib_cortex.h"
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#include "core_cm0.h"
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/**
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* @brief 1. Clears Pending of a device specific External Interrupt.
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* 2. Sets Priority of a device specific External Interrupt.
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* 3. Enables a device specific External Interrupt.
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* @param IRQn: External interrupt number .
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to target.h file)
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* @param Priority: The preemption priority for the IRQn channel.
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* This parameter can be a value between 0 and 3.
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* A lower priority value indicates a higher priority
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* @retval None
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*/
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void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
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assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
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/* Clear Pending Interrupt */
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NVIC_ClearPendingIRQ(IRQn);
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/* Set Interrupt Priority */
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NVIC_SetPriority(IRQn, Priority);
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/* Enable Interrupt in NVIC */
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NVIC_EnableIRQ(IRQn);
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}
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/**
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* @brief Enables a device specific interrupt in the NVIC interrupt controller.
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* @note To configure interrupts priority correctly before calling it.
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* @param IRQn External interrupt number.
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
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* @retval None
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*/
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void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
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/* Enable interrupt in NVIC */
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NVIC_EnableIRQ(IRQn);
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}
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/**
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* @brief Disables a device specific interrupt in the NVIC interrupt controller.
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* @param IRQn External interrupt number.
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
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* @retval None
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*/
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void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
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/* Disable interrupt in NVIC */
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NVIC_DisableIRQ(IRQn);
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}
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/**
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* @brief Initiates a system reset request to reset the MCU.
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* @retval None
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*/
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void CORTEX_NVIC_SystemReset(void)
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{
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/* System Reset */
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NVIC_SystemReset();
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}
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/**
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* @brief Gets the Pending bit of an interrupt.
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* @param IRQn: External interrupt number.
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
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* @retval 0 Interrupt status is not pending.
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1 Interrupt status is pending.
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*/
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uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
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/* Get priority for Cortex-M0 system or device specific interrupts */
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return NVIC_GetPendingIRQ(IRQn);
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}
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/**
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* @brief Sets Pending bit of an external interrupt.
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* @param IRQn External interrupt number
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
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* @retval None
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*/
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void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
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/* Set interrupt pending */
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NVIC_SetPendingIRQ(IRQn);
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}
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/**
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* @brief Clears the pending bit of an external interrupt.
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* @param IRQn External interrupt number.
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
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* @retval None
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*/
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void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
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/* Clear interrupt pending */
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NVIC_ClearPendingIRQ(IRQn);
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}
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/**
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* @brief Gets the priority of an interrupt.
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* @param IRQn: External interrupt number.
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
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* @retval Interrupt Priority. Value is aligned automatically to the implemented
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* priority bits of the microcontroller.
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*/
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uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
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{
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/* Get priority for Cortex-M0 system or device specific interrupts */
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return NVIC_GetPriority(IRQn);
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}
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/**
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* @brief Sets the priority of an interrupt.
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* @param IRQn: External interrupt number .
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* This parameter can be an enumerator of IRQn_Type enumeration
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* (For the complete target Devices IRQ Channels list, please refer to target.h file)
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* @param Priority: The preemption priority for the IRQn channel.
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* This parameter can be a value between 0 and 3.
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* A lower priority value indicates a higher priority
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* @retval None
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*/
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void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
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{
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/* Check parameters */
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assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
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/* Get priority for Cortex-M0 system or device specific interrupts */
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NVIC_SetPriority(IRQn, Priority);
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}
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/**
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* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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* Counter is in free running mode to generate periodic interrupts.
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* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
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* @retval status: - 0 Function succeeded.
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* - 1 Function failed.
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*/
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uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
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{
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return SysTick_Config(TicksNum);
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}
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/*********************************** END OF FILE ******************************/
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894
bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h
Normal file
894
bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h
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File diff suppressed because it is too large
Load Diff
@@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2021-01-04 iysheng first version
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* 2021-09-07 FuC Suit for Vango V85xx
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*/
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#ifndef __BOARD_H__
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@@ -15,11 +16,21 @@
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#include "drv_gpio.h"
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#define V85XX_SRAM_SIZE 48
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/* Internal SRAM memory size[Kbytes] <8-64>, Default: 32*/
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#define V85XX_SRAM_SIZE 32
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#define V85XX_SRAM_END (0x20000000 + V85XX_SRAM_SIZE * 1024)
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END V85XX_SRAM_END
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