mirror of
https://github.com/RT-Thread/rt-thread.git
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add t-head smart-evb bsp, and risc-v cpu e906
This commit is contained in:
chenzx
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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# you can change the RTT_ROOT default "../.." to your rtthread_root,
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# example : default "F:/git_repositories/rt-thread"
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_THEAD_SMART
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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if RT_USING_SERIAL
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config RT_USING_UART1
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bool "Using uart1"
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default y
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endif
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@@ -0,0 +1,45 @@
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# T-HEAD SMART-EVB Introduction
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SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide implementation, integrating T-HEAD's RISC-V CPU (eg. E902/E906/C906) and C-SKY CPU (eg. E805/E804/E803/E802 ), integrates basic peripheral resources such as GPIO/TIMER/UART/RAM.
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##The main resources on board are as follows:
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1. SMART-EVB for E906/E906F/E906FD
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| res | description |
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| -- | -- |
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|ISA | RISCV |
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|CPU | E906 |
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|FREQ| 20MHz |
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|SRAM| 768KB |
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2. SMART-EVB for E804/E804F/E804D
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| res | description |
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| -- | -- |
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|ISA | C-SKY |
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|CPU | E804 |
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|FREQ| 20MHz |
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|SRAM| 768KB |
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# Compile T-HEAD BSP
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SMART-EVB BSP supports GCC compiler, the version information is:
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1. SMART-EVB for E906/E906F/E906FD
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| IDE/Compiler| version|
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| - | - |
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| GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) |
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# run smart-evb bsp
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1. Connect JTAG
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2. Connect the serial port
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3. riscv64-unknown-elf-gdb rtthread-e906f.elf
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run log as follows:
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 4.0.3 build Sep 2 2020
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2006 - 2020 Copyright by rt-thread team
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msh >
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```
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@@ -0,0 +1,14 @@
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,33 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-' + rtconfig.CPU + '.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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# add --start-group and --end-group for GNU GCC
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env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# make a building
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DoBuilding(TARGET, objs)
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@@ -0,0 +1,13 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = GetCurrentDir()
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CCFLAGS = ' -c -ffunction-sections'
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS)
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Return('group')
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@@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen first version
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*/
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#include <rtthread.h>
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int main(void)
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{
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return 0;
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}
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/*@}*/
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@@ -0,0 +1,13 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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# add the general drivers.
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src = Glob("*.c") + Glob("*.cpp") + Glob("*.S")
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen add T-HEAD header file csi_core.h
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "csi_core.h"
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#include "drv_usart.h"
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extern int __bss_end__;
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#define SYS_HEAP_BEGIN (&__bss_end__)
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#include "core_rv32.h"
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extern usart_handle_t console_handle;
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extern void ioreuse_initial(void);
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/**
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* This function will initial smartl-evb(e906) board.
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*/
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void rt_hw_board_init(void)
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{
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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/* initialize hardware usart */
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rt_hw_usart_init();
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)E906FD_IRAM_END);
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#endif
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}
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/*@}*/
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@@ -0,0 +1,18 @@
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen add E906 ram size
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#define APB_DEFAULT_FREQ 20000000 /* Hz */
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#define E906FD_IRAM_SIZE 128
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#define E906FD_IRAM_END (0x20000000 + E906FD_IRAM_SIZE * 1024)
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#endif /* __BOARD_H__ */
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@@ -0,0 +1,88 @@
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen CSI Source File for IRQ Driver
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*/
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#include <stdint.h>
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#include <soc.h>
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#include <csi_core.h>
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#include <csi_config.h>
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extern void Default_Handler(void);
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extern void (*g_irqvector[])(void);
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extern void (*g_nmivector)(void);
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/**
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\brief enable irq.
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\param[in] irq_num Number of IRQ.
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\return None.
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*/
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void drv_irq_enable(uint32_t irq_num)
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{
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if (NMI_EXPn != irq_num)
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{
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#ifdef CONFIG_SYSTEM_SECURE
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csi_vic_enable_sirq(irq_num);
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#else
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csi_vic_enable_irq(irq_num);
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#endif
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}
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}
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/**
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\brief disable irq.
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\param[in] irq_num Number of IRQ.
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\return None.
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*/
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void drv_irq_disable(uint32_t irq_num)
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{
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if (NMI_EXPn != irq_num)
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{
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#ifdef CONFIG_SYSTEM_SECURE
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csi_vic_disable_sirq(irq_num);
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#else
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csi_vic_disable_irq(irq_num);
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#endif
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}
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}
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/**
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\brief register irq handler.
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\param[in] irq_num Number of IRQ.
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\param[in] irq_handler IRQ Handler.
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\return None.
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*/
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void drv_irq_register(uint32_t irq_num, void *irq_handler)
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{
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if (NMI_EXPn != irq_num)
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{
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g_irqvector[irq_num] = irq_handler;
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}
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else
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{
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g_nmivector = irq_handler;
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}
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}
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/**
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\brief unregister irq handler.
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\param[in] irq_num Number of IRQ.
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\return None.
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*/
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void drv_irq_unregister(uint32_t irq_num)
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{
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if (NMI_EXPn != irq_num)
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{
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g_irqvector[irq_num] = (void *)Default_Handler;
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}
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else
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{
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g_nmivector = (void *)Default_Handler;
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}
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,92 @@
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen header file for usart driver
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*/
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#ifndef __CK_USART_H
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#define __CK_USART_H
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#include <stdio.h>
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#include "errno.h"
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define BAUDRATE_DEFAULT 19200
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#define UART_BUSY_TIMEOUT 1000000
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#define UART_RECEIVE_TIMEOUT 1000
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#define UART_TRANSMIT_TIMEOUT 1000
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#define UART_MAX_FIFO 0x10
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/* UART register bit definitions */
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#define USR_UART_BUSY 0x01
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#define USR_UART_TFE 0x04
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#define USR_UART_RFNE 0x08
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#define LSR_DATA_READY 0x01
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#define LSR_THR_EMPTY 0x20
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#define IER_RDA_INT_ENABLE 0x01
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#define IER_THRE_INT_ENABLE 0x02
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#define IIR_RECV_LINE_ENABLE 0x04
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#define IIR_NO_ISQ_PEND 0x01
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#define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */
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#define LCR_PARITY_ENABLE 0x08 /* parity enabled */
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#define LCR_PARITY_EVEN 0x10 /* Even parity enabled */
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#define LCR_PARITY_ODD 0xef /* Odd parity enabled */
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#define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */
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#define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */
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#define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */
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#define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */
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#define LCR_STOP_BIT1 0xfb /* 1 stop bit */
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#define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */
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#define DW_LSR_PFE 0x80
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#define DW_LSR_TEMT 0x40
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#define DW_LSR_THRE 0x40
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#define DW_LSR_BI 0x10
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#define DW_LSR_FE 0x08
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#define DW_LSR_PE 0x04
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#define DW_LSR_OE 0x02
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#define DW_LSR_DR 0x01
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#define DW_LSR_TRANS_EMPTY 0x20
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#define DW_IIR_THR_EMPTY 0x02 /* threshold empty */
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#define DW_IIR_RECV_DATA 0x04 /* received data available */
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#define DW_IIR_RECV_LINE 0x06 /* receiver line status */
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#define DW_IIR_CHAR_TIMEOUT 0x0c /* character timeout */
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typedef struct
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{
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union
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{
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__IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
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__OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
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__IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */
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};
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union
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{
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__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */
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__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */
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};
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__IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */
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__IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */
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uint32_t RESERVED0;
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__IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */
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__IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */
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uint32_t RESERVED1[24];
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__IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */
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} ck_usart_reg_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CK_USART_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
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||||
* SPDX-License-Identifier: Apache-2.0
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||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen config file
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||||
*/
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/* csi_config.h -- Autogenerated! Do not edit. */
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#ifndef __CSI_CONFIG_H
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#define __CSI_CONFIG_H
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#define CONFIG_ARCH_RV32 1
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#define CONFIG_CPU_E906FD 1
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#define CONFIG_RV32_CORETIM 1
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#define CONFIG_CHIP_SMARTL_RV32 1
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#define CONFIG_BOARD_SMARTL_E906_EVB 1
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#define CONFIG_BOARD_NAME_STR "smartl_e906_evb"
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#define CONFIG_SUPPORT_TSPEND 1
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#define CONFIG_ARCH_INTERRUPTSTACK 4096
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#define CONFIG_NEWLIB_WRAP 1
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#define CONFIG_USER_DEFINED_LD_DIR_STR ""
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||||
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||||
#define CONFIG_KERNEL_RTTHREAD 1
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||||
#endif /* __CONFIG_H */
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||||
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@@ -0,0 +1,53 @@
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||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
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||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen CSI Core Layer Header File
|
||||
*/
|
||||
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||||
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||||
#ifndef _CORE_H_
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#define _CORE_H_
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||||
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||||
#include <stdint.h>
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||||
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||||
#if defined(__CK801__) || defined(__E801__)
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||||
#include <core_801.h>
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||||
#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
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||||
#include <core_802.h>
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||||
#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
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||||
#include <core_804.h>
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||||
#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
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||||
#include <core_803.h>
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||||
#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
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||||
#include <core_805.h>
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||||
#elif defined(__CK610__)
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||||
#include <core_ck610.h>
|
||||
#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
|
||||
#include <core_810.h>
|
||||
#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
|
||||
#include <core_807.h>
|
||||
#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
|
||||
#include <core_rv32_old.h>
|
||||
#elif defined(__riscv)
|
||||
#include <core_rv32.h>
|
||||
#endif
|
||||
|
||||
#ifdef __riscv
|
||||
#include <csi_rv32_gcc.h>
|
||||
#else
|
||||
#include <csi_gcc.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CORE_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen Header File for Common Driver
|
||||
*/
|
||||
|
||||
#ifndef _DRV_COMMON_H_
|
||||
#define _DRV_COMMON_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_errno.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/// \details driver handle
|
||||
typedef void *drv_handle_t;
|
||||
|
||||
#ifndef CONFIG_PARAM_NOT_CHECK
|
||||
#define HANDLE_PARAM_CHK(para, err) \
|
||||
do { \
|
||||
if ((int32_t)para == (int32_t)NULL) { \
|
||||
return (err); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define HANDLE_PARAM_CHK_NORETVAL(para, err) \
|
||||
do { \
|
||||
if ((int32_t)para == (int32_t)NULL) { \
|
||||
return; \
|
||||
} \
|
||||
} while (0)
|
||||
#else
|
||||
#define HANDLE_PARAM_CHK(para, err)
|
||||
#define HANDLE_PARAM_CHK_NORETVAL(para, err)
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief General power states
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DRV_POWER_OFF, ///< Power off: no operation possible
|
||||
DRV_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
|
||||
DRV_POWER_FULL, ///< Power on: full operation at maximum performance
|
||||
DRV_POWER_SUSPEND, ///< Power suspend: power saving operation
|
||||
} csi_power_stat_e;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRV_COMMON_H */
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header file for error num
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DRV_ERRNO_H_
|
||||
#define _DRV_ERRNO_H_
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ERRNO_DRV_START 0X80
|
||||
|
||||
/* driver General error codes */
|
||||
typedef enum
|
||||
{
|
||||
DRV_ERROR = ERRNO_DRV_START, ///< Unspecified error
|
||||
DRV_ERROR_BUSY, ///< Driver is busy
|
||||
DRV_ERROR_TIMEOUT, ///< Timeout occurred
|
||||
DRV_ERROR_UNSUPPORTED, ///< Operation not supported
|
||||
DRV_ERROR_PARAMETER, ///< Parameter error
|
||||
DRV_ERROR_SPECIFIC ///< Start of driver specific errors
|
||||
} drv_err_e;
|
||||
|
||||
|
||||
/** Get error type */
|
||||
#define GET_ERROR_TYPE(errno) \
|
||||
(error & 0xFF000000 >> 24)
|
||||
/** Get error module */
|
||||
#define GET_ERROR_MODULE(error) \
|
||||
(error & 0x00FF0000 >> 16)
|
||||
/** Get error API */
|
||||
#define GET_ERROR_API(error) \
|
||||
(error & 0x0000FF00 >> 8)
|
||||
/** Get errno */
|
||||
#define GET_ERROR_NUM(error) \
|
||||
(error & 0x000000FF)
|
||||
|
||||
#ifndef CSI_DRV_ERRNO_BASE
|
||||
#define CSI_DRV_ERRNO_BASE 0x81000000
|
||||
#endif
|
||||
|
||||
/** driver module id definition*/
|
||||
#define CSI_DRV_ERRNO_GPIO_BASE 0x81010000
|
||||
#define CSI_DRV_ERRNO_USART_BASE 0x81020000
|
||||
#define CSI_DRV_ERRNO_SPI_BASE 0x81030000
|
||||
#define CSI_DRV_ERRNO_IIC_BASE 0x81040000
|
||||
#define CSI_DRV_ERRNO_PWM_BASE 0x81050000
|
||||
#define CSI_DRV_ERRNO_RTC_BASE 0x81060000
|
||||
#define CSI_DRV_ERRNO_TIMER_BASE 0x81070000
|
||||
#define CSI_DRV_ERRNO_WDT_BASE 0x81080000
|
||||
#define CSI_DRV_ERRNO_AES_BASE 0x81090000
|
||||
#define CSI_DRV_ERRNO_CRC_BASE 0x810A0000
|
||||
#define CSI_DRV_ERRNO_RSA_BASE 0x810B0000
|
||||
#define CSI_DRV_ERRNO_SHA_BASE 0x810C0000
|
||||
#define CSI_DRV_ERRNO_TRNG_BASE 0x810D0000
|
||||
#define CSI_DRV_ERRNO_EFLASH_BASE 0x810E0000
|
||||
#define CSI_DRV_ERRNO_DMA_BASE 0x810F0000
|
||||
#define CSI_DRV_ERRNO_NORFLASH_BASE 0x81100000
|
||||
#define CSI_DRV_ERRNO_INTC_BASE 0x81110000
|
||||
#define CSI_DRV_ERRNO_SPU_BASE 0x81120000
|
||||
#define CSI_DRV_ERRNO_ADC_BASE 0x81130000
|
||||
#define CSI_DRV_ERRNO_PMU_BASE 0x81140000
|
||||
#define CSI_DRV_ERRNO_BMU_BASE 0x81150000
|
||||
#define CSI_DRV_ERRNO_ETB_BASE 0x81160000
|
||||
#define CSI_DRV_ERRNO_I2S_BASE 0x81170000
|
||||
#define CSI_DRV_ERRNO_USI_BASE 0x81180000
|
||||
#define CSI_DRV_ERRNO_SPIFLASH_BASE 0x81190000
|
||||
#define CSI_DRV_ERRNO_ACMP_BASE 0x811A0000
|
||||
#define CSI_DRV_ERRNO_MAILBOX_BASE 0x811B0000
|
||||
#define CSI_DRV_ERRNO_EFUSEC_BASE 0x811C0000
|
||||
#define CSI_DRV_ERRNO_CODEC_BASE 0x811D0000
|
||||
#define CSI_DRV_ERRNO_DPU_BASE 0x811E0000
|
||||
#define CSI_DRV_ERRNO_VPU_BASE 0x811F0000
|
||||
#define CSI_DRV_ERRNO_CAMERA_BASE 0x81200000
|
||||
#define CSI_DRV_ERRNO_MIPI_CSI_BASE 0x81210000
|
||||
#define CSI_DRV_ERRNO_MIPI_CSI_READER_BASE 0x81220000
|
||||
#define CSI_DRV_ERRNO_GMAC_BASE 0x81230000
|
||||
#define CSI_DRV_ERRNO_ETHPHY_BASE 0x81240000
|
||||
#define CSI_DRV_ERRNO_QW_EFUSE_BASE 0x81250000
|
||||
#define CSI_DRV_ERRNO_RESET_BASE 0x81260000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CSI_DRV_ERRNO_H */
|
||||
@@ -0,0 +1,144 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header file for gpio driver
|
||||
*/
|
||||
|
||||
#ifndef _CSI_GPIO_H_
|
||||
#define _CSI_GPIO_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/// definition for gpio pin handle.
|
||||
typedef void *gpio_pin_handle_t;
|
||||
|
||||
/****** GPIO specific error codes *****/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
|
||||
GPIO_ERROR_DIRECTION, ///< Specified direction not supported
|
||||
GPIO_ERROR_IRQ_MODE, ///< Specified irq mode not supported
|
||||
} gpio_error_e;
|
||||
|
||||
/*----- GPIO Control Codes: Mode -----*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MODE_PULLNONE = 0, ///< pull none for input
|
||||
GPIO_MODE_PULLUP, ///< pull up for input
|
||||
GPIO_MODE_PULLDOWN, ///< pull down for input
|
||||
GPIO_MODE_OPEN_DRAIN, ///< open drain mode for output
|
||||
GPIO_MODE_PUSH_PULL, ///< push-pull mode for output
|
||||
} gpio_mode_e;
|
||||
|
||||
/*----- GPIO Control Codes: Mode Parameters: Data Bits -----*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DIRECTION_INPUT = 0, ///< gpio as input
|
||||
GPIO_DIRECTION_OUTPUT, ///< gpio as output
|
||||
} gpio_direction_e;
|
||||
|
||||
/*----- GPIO Control Codes: Mode Parameters: Parity -----*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_IRQ_MODE_RISING_EDGE = 0, ///< interrupt mode for rising edge
|
||||
GPIO_IRQ_MODE_FALLING_EDGE, ///< interrupt mode for falling edge
|
||||
GPIO_IRQ_MODE_DOUBLE_EDGE, ///< interrupt mode for double edge
|
||||
GPIO_IRQ_MODE_LOW_LEVEL, ///< interrupt mode for low level
|
||||
GPIO_IRQ_MODE_HIGH_LEVEL, ///< interrupt mode for high level
|
||||
} gpio_irq_mode_e;
|
||||
|
||||
typedef void (*gpio_event_cb_t)(int32_t idx); ///< gpio Event call back.
|
||||
|
||||
/**
|
||||
\brief Initialize GPIO handle.
|
||||
\param[in] gpio_pin gpio pin idx.
|
||||
\param[in] cb_event event callback function \ref gpio_event_cb_t
|
||||
\return gpio_pin_handle
|
||||
*/
|
||||
gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize GPIO pin handle.stops operation and releases the software resources used by the handle.
|
||||
\param[in] handle gpio pin handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief control gpio power.
|
||||
\param[in] handle gpio handle to operate.
|
||||
\param[in] state power state.\ref csi_power_stat_e.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state);
|
||||
|
||||
/**
|
||||
\brief config pin mode
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] mode \ref gpio_mode_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
|
||||
gpio_mode_e mode);
|
||||
|
||||
/**
|
||||
\brief config pin direction
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] dir \ref gpio_direction_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
|
||||
gpio_direction_e dir);
|
||||
|
||||
/**
|
||||
\brief config pin
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] mode \ref gpio_mode_e
|
||||
\param[in] dir \ref gpio_direction_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
|
||||
gpio_mode_e mode,
|
||||
gpio_direction_e dir);
|
||||
|
||||
/**
|
||||
\brief Set one or zero to the selected GPIO pin.
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] value value to be set
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value);
|
||||
|
||||
/**
|
||||
\brief Get the value of selected GPIO pin.
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[out] value buffer to store the pin value
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value);
|
||||
|
||||
/**
|
||||
\brief set GPIO interrupt mode.
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] mode irq mode to be set
|
||||
\param[in] enable enable flag
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_GPIO_H_ */
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header File for IRQ Driver
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
\brief enable irq.
|
||||
\param[in] irq_num Number of IRQ.
|
||||
\return None.
|
||||
*/
|
||||
void drv_irq_enable(uint32_t irq_num);
|
||||
|
||||
/**
|
||||
\brief disable irq.
|
||||
\param[in] irq_num Number of IRQ.
|
||||
\return None.
|
||||
*/
|
||||
void drv_irq_disable(uint32_t irq_num);
|
||||
|
||||
/**
|
||||
\brief register irq handler.
|
||||
\param[in] irq_num Number of IRQ.
|
||||
\param[in] irq_handler IRQ Handler.
|
||||
\return None.
|
||||
*/
|
||||
void drv_irq_register(uint32_t irq_num, void *irq_handler);
|
||||
|
||||
/**
|
||||
\brief unregister irq handler.
|
||||
\param[in] irq_num Number of IRQ.
|
||||
\param[in] irq_handler IRQ Handler.
|
||||
\return None.
|
||||
*/
|
||||
void drv_irq_unregister(uint32_t irq_num);
|
||||
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen timer driver header file
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file drv_timer.h
|
||||
* @brief header file for timer driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
* @model timer
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_TIMER_H_
|
||||
#define _CSI_TIMER_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/// definition for timer handle.
|
||||
typedef void *timer_handle_t;
|
||||
|
||||
/*----- TIMER Control Codes: Mode -----*/
|
||||
typedef enum
|
||||
{
|
||||
TIMER_MODE_FREE_RUNNING = 0, ///< free running mode
|
||||
TIMER_MODE_RELOAD ///< reload mode
|
||||
} timer_mode_e;
|
||||
|
||||
/**
|
||||
\brief TIMER Status
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t active : 1; ///< timer active flag
|
||||
uint32_t timeout : 1; ///< timeout flag
|
||||
} timer_status_t;
|
||||
|
||||
/**
|
||||
\brief TIMER Event
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIMER_EVENT_TIMEOUT = 0 ///< time out event
|
||||
} timer_event_e;
|
||||
|
||||
typedef void (*timer_event_cb_t)(int32_t idx, timer_event_e event); ///< Pointer to \ref timer_event_cb_t : TIMER Event call back.
|
||||
|
||||
/**
|
||||
\brief Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
|
||||
\param[in] idx timer index
|
||||
\param[in] cb_event event call back function \ref timer_event_cb_t
|
||||
\param[in] cb_arg arguments of cb_event
|
||||
\return pointer to timer instance
|
||||
*/
|
||||
timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_uninitialize(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief control timer power.
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] state power state.\ref csi_power_stat_e.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state);
|
||||
|
||||
/**
|
||||
\brief config timer mode.
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] mode \ref timer_mode_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode);
|
||||
|
||||
/**
|
||||
\brief Set timeout just for the reload mode.
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] timeout the timeout value in microseconds(us).
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout);
|
||||
|
||||
/**
|
||||
\brief Start timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_start(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Stop timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_stop(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief suspend timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_suspend(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief resume timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_resume(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief get timer current value
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[out] value timer current value
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value);
|
||||
|
||||
/**
|
||||
\brief Get TIMER status.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return TIMER status \ref timer_status_t
|
||||
*/
|
||||
timer_status_t csi_timer_get_status(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief get timer reload value
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[out] value timer reload value
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_TIMER_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header file for GPIO Driver
|
||||
*/
|
||||
|
||||
#ifndef _DW_GPIO_H_
|
||||
#define _DW_GPIO_H_
|
||||
|
||||
#include "drv_gpio.h"
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */
|
||||
__IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */
|
||||
__IOM uint32_t PORT_CTL; /* Offset: 0x008 (W/R) PortA source register */
|
||||
|
||||
} dw_gpio_reg_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t INTEN; /* Offset: 0x000 (W/R) Interrupt enable register */
|
||||
__IOM uint32_t INTMASK; /* Offset: 0x004 (W/R) Interrupt mask register */
|
||||
__IOM uint32_t INTTYPE_LEVEL; /* Offset: 0x008 (W/R) Interrupt level register */
|
||||
__IOM uint32_t INT_POLARITY; /* Offset: 0x00c (W/R) Interrupt polarity register */
|
||||
__IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */
|
||||
__IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port */
|
||||
__IOM uint32_t revreg1; /* Offset: 0x018 (W/R) Reserve register */
|
||||
__OM uint32_t PORTA_EOI; /* Offset: 0x01c (W/R) Port clear interrupt register */
|
||||
__IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register */
|
||||
__IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register */
|
||||
__IOM uint32_t revreg2[2]; /* Offset: 0x028 (W/R) Reserve register */
|
||||
__IOM uint32_t LS_SYNC; /* Offset: 0x030 (W/R) Level-sensitive synchronization enable register */
|
||||
|
||||
} dw_gpio_control_reg_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header file for timer driver
|
||||
*/
|
||||
|
||||
#ifndef __DW_TIMER_H
|
||||
#define __DW_TIMER_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* define the bits for TxControl
|
||||
*/
|
||||
#define DW_TIMER_TXCONTROL_ENABLE (1UL << 0)
|
||||
#define DW_TIMER_TXCONTROL_MODE (1UL << 1)
|
||||
#define DW_TIMER_TXCONTROL_INTMASK (1UL << 2)
|
||||
#define DW_TIMER_TXCONTROL_TRIGGER (1UL << 4)
|
||||
|
||||
#define DW_TIMER_INIT_DEFAULT_VALUE (0xffffffff / drv_get_timer_freq(0) * 1000000)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */
|
||||
__IM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */
|
||||
__IOM uint8_t TxControl: 5; /* Offset: 0x008 (R/W) Clock frequency division low section register */
|
||||
uint8_t RESERVED0[3];
|
||||
__IM uint8_t TxEOI: 1; /* Offset: 0x00c (R) Clock frequency division high section register */
|
||||
uint8_t RESERVED1[3];
|
||||
__IM uint8_t TxIntStatus: 1; /* Offset: 0x010 (R) Interrupt enable register */
|
||||
uint8_t RESERVED2[3];
|
||||
} dw_timer_reg_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DW_TIMER_H */
|
||||
|
||||
@@ -0,0 +1,195 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen source file for the interrupt server route
|
||||
*/
|
||||
|
||||
#include <drv_common.h>
|
||||
#include <csi_config.h>
|
||||
#include "soc.h"
|
||||
|
||||
#ifndef CONFIG_SYSTICK_HZ
|
||||
#define CONFIG_SYSTICK_HZ 100
|
||||
#endif
|
||||
|
||||
extern volatile uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
extern void ck_usart_irqhandler(int32_t idx);
|
||||
extern void dw_timer_irqhandler(int32_t idx);
|
||||
extern void dw_gpio_irqhandler(int32_t idx);
|
||||
extern void systick_handler(void);
|
||||
extern void xPortSysTickHandler(void);
|
||||
extern void OSTimeTick(void);
|
||||
|
||||
#define ATTRIBUTE_ISR
|
||||
|
||||
#define readl(addr) \
|
||||
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
|
||||
|
||||
|
||||
#if(CONFIG_KERNEL_RTTHREAD == 1)
|
||||
#define CSI_INTRPT_ENTER() rt_interrupt_enter()
|
||||
#define CSI_INTRPT_EXIT() rt_interrupt_leave()
|
||||
#endif
|
||||
|
||||
|
||||
void __attribute__((isr)) SysTick_Handler(void)
|
||||
{
|
||||
#if(CONFIG_KERNEL_RTTHREAD == 1)
|
||||
CSI_INTRPT_ENTER();
|
||||
#endif
|
||||
|
||||
csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn);
|
||||
|
||||
#if defined(CONFIG_KERNEL_RHINO)
|
||||
systick_handler();
|
||||
#elif defined(CONFIG_KERNEL_FREERTOS)
|
||||
xPortSysTickHandler();
|
||||
#elif defined(CONFIG_KERNEL_RTTHREAD)
|
||||
rt_tick_increase();
|
||||
#elif defined(CONFIG_KERNEL_UCOS)
|
||||
OSTimeTick();
|
||||
#endif
|
||||
|
||||
#if(CONFIG_KERNEL_RTTHREAD == 1)
|
||||
CSI_INTRPT_EXIT();
|
||||
#endif
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void USART_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
ck_usart0_irqhandler();
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM0_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(0);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM1_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(1);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
ATTRIBUTE_ISR void TIM2_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(2);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM3_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(3);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM4_NMIHandler(void)
|
||||
{
|
||||
dw_timer_irqhandler(4);
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM6_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(6);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM7_IRQHandler(void)
|
||||
{
|
||||
dw_timer_irqhandler(7);
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM8_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(8);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM9_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(9);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
ATTRIBUTE_ISR void TIM10_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(10);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void TIM11_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_timer_irqhandler(11);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO0_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(0);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO1_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(1);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO2_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(2);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO3_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(3);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO4_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(4);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO5_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(5);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO6_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(6);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
|
||||
ATTRIBUTE_ISR void GPIO7_IRQHandler(void)
|
||||
{
|
||||
CSI_INTRPT_ENTER();
|
||||
dw_gpio_irqhandler(7);
|
||||
CSI_INTRPT_EXIT();
|
||||
}
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen novic table init
|
||||
*/
|
||||
|
||||
#include <csi_config.h>
|
||||
#include <soc.h>
|
||||
|
||||
extern void Default_Handler(void);
|
||||
extern void SysTick_Handler(void);
|
||||
extern void TIM4_NMIHandler(void);
|
||||
|
||||
void (*g_irqvector[48])(void);
|
||||
void (*g_nmivector)(void);
|
||||
|
||||
void irq_vectors_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 48; i++)
|
||||
{
|
||||
g_irqvector[i] = Default_Handler;
|
||||
}
|
||||
|
||||
g_irqvector[CORET_IRQn] = SysTick_Handler;
|
||||
g_nmivector = TIM4_NMIHandler;
|
||||
}
|
||||
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header file for the pin_name
|
||||
*/
|
||||
|
||||
#ifndef _PINNAMES_H
|
||||
#define _PINNAMES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PA0 = 0,
|
||||
PA1,
|
||||
PA2,
|
||||
PA3,
|
||||
PA4,
|
||||
PA5,
|
||||
PA6,
|
||||
PA7,
|
||||
PAD_UART0_SIN,
|
||||
PAD_UART0_SOUT
|
||||
}
|
||||
pin_name_e;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PORTA = 0,
|
||||
PORTB = 1,
|
||||
PORTC = 2,
|
||||
PORTD = 3,
|
||||
PORTE = 4,
|
||||
PORTF = 5,
|
||||
PORTG = 6,
|
||||
PORTH = 7
|
||||
} port_name_e;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NONE = 0
|
||||
} pin_func_e;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen CSI Core Peripheral Access Layer Header File for
|
||||
* CSKYSOC Device Series
|
||||
*/
|
||||
|
||||
#ifndef _SOC_H_
|
||||
#define _SOC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <csi_core.h>
|
||||
#include <sys_freq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef IHS_VALUE
|
||||
#define IHS_VALUE (20000000)
|
||||
#endif
|
||||
|
||||
#ifndef EHS_VALUE
|
||||
#define EHS_VALUE (20000000)
|
||||
#endif
|
||||
|
||||
|
||||
/* ------------------------- Interrupt Number Definition ------------------------ */
|
||||
typedef enum IRQn {
|
||||
NMI_EXPn = -2, /* NMI Exception */
|
||||
/* ---------------------- SmartL Specific Interrupt Numbers --------------------- */
|
||||
Machine_Software_IRQn = 3, /* Machine software interrupt */
|
||||
User_Timer_IRQn = 4, /* User timer interrupt */
|
||||
Supervisor_Timer_IRQn = 5, /* Supervisor timer interrupt */
|
||||
CORET_IRQn = 7, /* core Timer Interrupt */
|
||||
Machine_External_IRQn = 11, /* Machine external interrupt */
|
||||
UART_IRQn = 16, /* uart Interrupt */
|
||||
TIM0_IRQn = 18, /* timer0 Interrupt */
|
||||
TIM1_IRQn = 19, /* timer1 Interrupt */
|
||||
TIM2_IRQn = 20, /* timer2 Interrupt */
|
||||
TIM3_IRQn = 21, /* timer3 Interrupt */
|
||||
GPIO0_IRQn = 23, /* gpio0 Interrupt */
|
||||
GPIO1_IRQn = 24, /* gpio1 Interrupt */
|
||||
GPIO2_IRQn = 25, /* gpio2 Interrupt */
|
||||
GPIO3_IRQn = 26, /* gpio3 Interrupt */
|
||||
GPIO4_IRQn = 27, /* gpio4 Interrupt */
|
||||
GPIO5_IRQn = 28, /* gpio5 Interrupt */
|
||||
GPIO6_IRQn = 29, /* gpio6 Interrupt */
|
||||
GPIO7_IRQn = 30, /* gpio7 Interrupt */
|
||||
STIM0_IRQn = 31, /* stimer0 Interrupt */
|
||||
STIM1_IRQn = 32, /* stimer1 Interrupt */
|
||||
STIM2_IRQn = 33, /* stimer2 Interrupt */
|
||||
STIM3_IRQn = 34, /* stimer3 Interrupt */
|
||||
PAD_IRQn = 35, /* pad Interrupt */
|
||||
TIM6_IRQn = 36, /* timer6 Interrupt */
|
||||
TIM7_IRQn = 37, /* timer7 Interrupt */
|
||||
TIM8_IRQn = 38, /* timer8 Interrupt */
|
||||
TIM9_IRQn = 39, /* timer9 Interrupt */
|
||||
TIM10_IRQn = 40, /* timer10 Interrupt */
|
||||
TIM11_IRQn = 41, /* timer11 Interrupt */
|
||||
}
|
||||
IRQn_Type;
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Device Specific Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
#define CONFIG_TIMER_NUM 12
|
||||
#define CONFIG_USART_NUM 1
|
||||
#define CONFIG_GPIO_NUM 8
|
||||
#define CONFIG_GPIO_PIN_NUM 8
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral memory map ================ */
|
||||
/* ================================================================================ */
|
||||
/* -------------------------- CPU FPGA memory map ------------------------------- */
|
||||
#define CSKY_SRAM_BASE (0x20000000UL)
|
||||
|
||||
#define CSKY_UART_BASE (0x40015000UL)
|
||||
#define CSKY_PMU_BASE (0x40016000UL)
|
||||
#define CSKY_TIMER0_BASE (0x40011000UL)
|
||||
#define CSKY_TIMER1_BASE (0x40011014UL)
|
||||
#define CSKY_TIMER2_BASE (0x40011028UL)
|
||||
#define CSKY_TIMER3_BASE (0x4001103cUL)
|
||||
#define CSKY_TIMER4_BASE (0x40021000UL)
|
||||
#define CSKY_TIMER5_BASE (0x40021014UL)
|
||||
#define CSKY_TIMER6_BASE (0x40021028UL)
|
||||
#define CSKY_TIMER7_BASE (0x4002103cUL)
|
||||
#define CSKY_TIMER8_BASE (0x40031000UL)
|
||||
#define CSKY_TIMER9_BASE (0x40031014UL)
|
||||
#define CSKY_TIMER10_BASE (0x40031028UL)
|
||||
#define CSKY_TIMER11_BASE (0x4003103cUL)
|
||||
|
||||
#define CSKY_TIMER_CONTROL_BASE (0x400110a0UL)
|
||||
#define CSKY_CLK_GEN_BASE (0x40017000UL)
|
||||
#define CSKY_STIMER0_BASE (0x40018000UL)
|
||||
#define CSKY_STIMER1_BASE (0x40018014UL)
|
||||
#define CSKY_STIMER2_BASE (0x40018028UL)
|
||||
#define CSKY_STIMER3_BASE (0x4001803cUL)
|
||||
#define CSKY_STIMER_CONTROL_BASE (0x400110a0UL)
|
||||
|
||||
#define CSKY_GPIOA_BASE (0x40019000UL)
|
||||
#define CSKY_GPIOA_CONTROL_BASE (0x40019030UL)
|
||||
#define CSKY_SMPU_BASE (0x4001a000UL)
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* ================================================================================ */
|
||||
#define CSKY_UART (( CSKY_UART_TypeDef *) CSKY_UART_BASE)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_H_ */
|
||||
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen startup file. Should use with
|
||||
* GCC for T-HEAD Embedded Processors
|
||||
*/
|
||||
|
||||
#include <csi_config.h>
|
||||
|
||||
|
||||
.section .vectors, "aw", @progbits
|
||||
.align 6
|
||||
.globl __Vectors
|
||||
.type __Vectors, @object
|
||||
__Vectors:
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long PendSV_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_IRQHandler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
.long Default_Handler
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
.long Default_IRQHandler
|
||||
|
||||
.text
|
||||
.align 2
|
||||
_start:
|
||||
.text
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
la a0, Default_Handler
|
||||
ori a0, a0, 3
|
||||
csrw mtvec, a0
|
||||
la a0, __Vectors
|
||||
csrw mtvt, a0
|
||||
la sp, __StackTop
|
||||
csrw mscratch, sp
|
||||
|
||||
/* Load data section */
|
||||
la a0, __erodata
|
||||
la a1, __data_start__
|
||||
la a2, __data_end__
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
|
||||
/* Clear bss section */
|
||||
la a0, __bss_start__
|
||||
la a1, __bss_end__
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
jal SystemInit
|
||||
#endif
|
||||
|
||||
jal entry
|
||||
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
__exit:
|
||||
j __exit
|
||||
|
||||
.section .bss
|
||||
|
||||
.align 3
|
||||
.global g_base_irqstack
|
||||
.global g_top_irqstack
|
||||
g_base_irqstack:
|
||||
.space CONFIG_ARCH_INTERRUPTSTACK
|
||||
g_top_irqstack:
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen setting system frequency
|
||||
*/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc.h>
|
||||
#include <sys_freq.h>
|
||||
|
||||
extern int g_system_clock;
|
||||
|
||||
int32_t drv_get_cpu_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_usi_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_usart_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_pwm_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_i2s_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_sys_freq(void)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_rtc_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_apb_freq(void)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
|
||||
int32_t drv_get_timer_freq(int32_t idx)
|
||||
{
|
||||
return g_system_clock;
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen header file for setting system frequency
|
||||
*/
|
||||
|
||||
#ifndef _SYS_FREQ_H_
|
||||
#define _SYS_FREQ_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int32_t drv_get_i2s_freq(int32_t idx);
|
||||
int32_t drv_get_pwm_freq(int32_t idx);
|
||||
int32_t drv_get_usart_freq(int32_t idx);
|
||||
int32_t drv_get_usi_freq(int32_t idx);
|
||||
int32_t drv_get_sys_freq(void);
|
||||
int32_t drv_get_apb_freq(void);
|
||||
int32_t drv_get_rtc_freq(int32_t idx);
|
||||
int32_t drv_get_timer_freq(int32_t idx);
|
||||
|
||||
int32_t drv_get_cpu_freq(int32_t idx);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYS_FREQ_H_ */
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen CSI Device System Source File
|
||||
*/
|
||||
|
||||
#include <csi_config.h>
|
||||
#include <soc.h>
|
||||
#include <csi_core.h>
|
||||
#include <drv_irq.h>
|
||||
|
||||
#ifndef CONFIG_SYSTICK_HZ
|
||||
#define CONFIG_SYSTICK_HZ 100
|
||||
#endif
|
||||
|
||||
int g_system_clock = IHS_VALUE;
|
||||
extern int32_t g_top_irqstack;
|
||||
extern void irq_vectors_init(void);
|
||||
extern void mm_heap_initialize(void);
|
||||
|
||||
int SystemCoreClock = IHS_VALUE; /* System Core Clock Frequency */
|
||||
extern int __Vectors;
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = IHS_VALUE;
|
||||
}
|
||||
|
||||
|
||||
static void _system_init_for_kernel(void)
|
||||
{
|
||||
irq_vectors_init();
|
||||
|
||||
csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn); //10ms
|
||||
drv_irq_enable(CORET_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize the system
|
||||
* Initialize the psr and vbr.
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
int i;
|
||||
/* enable mstatus FS */
|
||||
#if ((CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
|
||||
uint32_t mstatus = __get_MSTATUS();
|
||||
mstatus |= (1 << 13);
|
||||
__set_MSTATUS(mstatus);
|
||||
#endif
|
||||
|
||||
/* enable mxstatus THEADISAEE */
|
||||
uint32_t mxstatus = __get_MXSTATUS();
|
||||
mxstatus |= (1 << 22);
|
||||
/* enable mxstatus MM */
|
||||
#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
|
||||
mxstatus |= (1 << 15);
|
||||
#endif
|
||||
__set_MXSTATUS(mxstatus);
|
||||
|
||||
|
||||
/* get interrupt level from info */
|
||||
CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
|
||||
|
||||
for (i = 0; i < 64; i++)
|
||||
{
|
||||
CLIC->CLICINT[i].IP = 0;
|
||||
CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
|
||||
}
|
||||
|
||||
/* tspend use positive interrupt */
|
||||
CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
|
||||
|
||||
csi_dcache_enable();
|
||||
csi_icache_enable();
|
||||
drv_irq_enable(Machine_Software_IRQn);
|
||||
|
||||
_system_init_for_kernel();
|
||||
}
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen source file for the trap process
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <csi_config.h>
|
||||
#include <csi_core.h>
|
||||
|
||||
void (*trap_c_callback)(void);
|
||||
|
||||
void trap_c(uint32_t *regs)
|
||||
{
|
||||
int i;
|
||||
uint32_t vec = 0;
|
||||
|
||||
vec = __get_MCAUSE() & 0x3FF;
|
||||
|
||||
printf("CPU Exception: NO.%d", vec);
|
||||
printf("\n");
|
||||
|
||||
for (i = 0; i < 31; i++)
|
||||
{
|
||||
printf("x%d: %08x\t", i + 1, regs[i]);
|
||||
|
||||
if ((i % 4) == 3)
|
||||
{
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
printf("mepc : %08x\n", regs[31]);
|
||||
printf("mstatus: %08x\n", regs[32]);
|
||||
|
||||
if (trap_c_callback)
|
||||
{
|
||||
trap_c_callback();
|
||||
}
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file gcc_csky.h
|
||||
* @brief csky linker file for PHOBOS
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
MEMORY
|
||||
{
|
||||
I-SRAM : ORIGIN = 0x0 , LENGTH = 0x40000 /* I-SRAM 256KB */
|
||||
D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0xc0000 /* D-SRAM 768KB */
|
||||
O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000 /* off-chip SRAM 8MB */
|
||||
SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* on-chip SRAM 128KB */
|
||||
}
|
||||
|
||||
PROVIDE (__StackTop = 0x200c0000 - 0x8);
|
||||
PROVIDE (Stack_Size = 0x1000);
|
||||
|
||||
REGION_ALIAS("REGION_TEXT", I-SRAM);
|
||||
REGION_ALIAS("REGION_RODATA", I-SRAM);
|
||||
REGION_ALIAS("REGION_CUSTOM1", D-SRAM);
|
||||
REGION_ALIAS("REGION_CUSTOM2", D-SRAM);
|
||||
REGION_ALIAS("REGION_DATA", D-SRAM);
|
||||
REGION_ALIAS("REGION_BSS", D-SRAM);
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text : AT(ADDR(.text)){
|
||||
. = ALIGN(0x4) ;
|
||||
__stext = . ;
|
||||
KEEP(*startup.o(*.text*))
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.text.*)
|
||||
*(.gnu.warning)
|
||||
*(.stub)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.jcr)
|
||||
*(.init)
|
||||
*(.fini)
|
||||
. = ALIGN (4) ;
|
||||
PROVIDE(__ctbp = .);
|
||||
*(.call_table_data)
|
||||
*(.call_table_text)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
. = ALIGN(0x10) ;
|
||||
__etext = . ;
|
||||
} > REGION_TEXT
|
||||
.eh_frame_hdr : {
|
||||
*(.eh_frame_hdr)
|
||||
} > REGION_TEXT
|
||||
.eh_frame : ONLY_IF_RO {
|
||||
KEEP (*(.eh_frame))
|
||||
} > REGION_TEXT
|
||||
.gcc_except_table : ONLY_IF_RO {
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
} > REGION_TEXT
|
||||
.rodata :{
|
||||
. = ALIGN(0x4) ;
|
||||
__srodata = .;
|
||||
*(.rdata)
|
||||
*(.rdata*)
|
||||
*(.rdata1)
|
||||
*(.rdata.*)
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata*)
|
||||
*(.rodata.*)
|
||||
*(.rodata.str1.4)
|
||||
. = ALIGN(0x4) ;
|
||||
__ctor_start__ = .;
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__ctor_end__ = .;
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__dtor_end__ = .;
|
||||
. = ALIGN(0x4) ;
|
||||
__erodata = .;
|
||||
__rodata_end__ = .;
|
||||
} > REGION_RODATA
|
||||
.data : {
|
||||
. = ALIGN(0x4) ;
|
||||
__sdata = . ;
|
||||
__data_start__ = . ;
|
||||
data_start = . ;
|
||||
KEEP(*startup.o(*.vectors*))
|
||||
*(.got.plt)
|
||||
*(.got)
|
||||
*(.gnu.linkonce.r*)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.data1)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.data1)
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table*)
|
||||
__start_init_call = .;
|
||||
*(.initcall.init)
|
||||
__stop_init_call = .;
|
||||
__start_cmd = .;
|
||||
*(.bootloaddata.cmd)
|
||||
. = ALIGN(4) ;
|
||||
__stop_cmd = .;
|
||||
__global_pointer$ = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(__libc_atexit)
|
||||
*(__libc_subinit)
|
||||
*(__libc_subfreeres)
|
||||
*(.note.ABI-tag)
|
||||
__edata = .;
|
||||
__data_end__ = .;
|
||||
. = ALIGN(0x4) ;
|
||||
|
||||
} > REGION_DATA AT > REGION_RODATA
|
||||
.eh_frame : ONLY_IF_RW {
|
||||
KEEP (*(.eh_frame))
|
||||
} > REGION_DATA AT > REGION_RODATA
|
||||
.gcc_except_table : ONLY_IF_RW {
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
__edata = .;
|
||||
__data_end__ = .;
|
||||
} > REGION_DATA AT > REGION_RODATA
|
||||
|
||||
|
||||
.bss : {
|
||||
. = ALIGN(0x4) ;
|
||||
__sbss = ALIGN(0x4) ;
|
||||
__bss_start__ = . ;
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(0x4) ;
|
||||
__ebss = . ;
|
||||
__end = . ;
|
||||
end = . ;
|
||||
__bss_end__ = .;
|
||||
} > REGION_BSS
|
||||
/* End of uninitalized data segement */
|
||||
PROVIDE(end = .);
|
||||
}
|
||||
@@ -0,0 +1,158 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 512
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40003
|
||||
|
||||
/* RT-Thread CPU arch and features */
|
||||
|
||||
|
||||
/* risc-v arch */
|
||||
|
||||
#define ARCH_RISCV
|
||||
#define ARCH_RISCV_32
|
||||
#define ARCH_RISCV_FPU
|
||||
#define ARCH_RISCV_FPU_S
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 1
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 2048
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_USING_MSH_ONLY
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* AT commands */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
#define SOC_THEAD_SMART
|
||||
#define RT_USING_UART1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,68 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH ='risc-v'
|
||||
CPU ='e906'
|
||||
CPUNAME ='e906f'
|
||||
VENDOR ='t-head'
|
||||
CROSS_TOOL ='gcc'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/home/xinge/tools/riscv64-elf-x86_64-20200616-1.9.6/bin'
|
||||
else:
|
||||
print 'Please make sure your toolchains is GNU GCC!'
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
# BUILD = 'debug'
|
||||
BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'riscv64-unknown-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'g++'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
if CPUNAME == 'e906fd':
|
||||
DEVICE = ' -march=rv32imafdcxthead -mabi=ilp32d'
|
||||
if CPUNAME == 'e906f':
|
||||
DEVICE = ' -march=rv32imafcxthead -mabi=ilp32f'
|
||||
if CPUNAME == 'e906':
|
||||
DEVICE = ' -march=rv32imacxthead -mabi=ilp32'
|
||||
|
||||
CFLAGS = DEVICE + ' -c -g -ffunction-sections -fdata-sections -Wall -mcmodel=medlow'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-whole-archive -T gcc_csky.ld -lm -lc -lgcc -Wl,-gc-sections -Wl,-zmax-page-size=1024'
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2 -g2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
# M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic '
|
||||
# M_CXXFLAGS = M_CFLAGS
|
||||
# M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\
|
||||
# ' -nostartfiles -static-libgcc'
|
||||
# M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
@@ -10,10 +10,17 @@ group = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
# add common code files
|
||||
if rtconfig.CPU != "nuclei":
|
||||
group = group + SConscript(os.path.join('common', 'SConscript'))
|
||||
if rtconfig.VENDOR == "t-head" :
|
||||
group = group
|
||||
elif rtconfig.CPU == "nuclei" :
|
||||
group = group
|
||||
else :
|
||||
group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
|
||||
|
||||
# cpu porting code files
|
||||
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
|
||||
if rtconfig.VENDOR == "t-head" :
|
||||
group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
|
||||
else :
|
||||
group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
|
||||
CPPPATH = [cwd]
|
||||
ASFLAGS = ''
|
||||
|
||||
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,170 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code.
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "cpuport.h"
|
||||
|
||||
#ifndef RT_USING_SMP
|
||||
volatile rt_ubase_t rt_interrupt_from_thread = 0;
|
||||
volatile rt_ubase_t rt_interrupt_to_thread = 0;
|
||||
volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
|
||||
#endif
|
||||
|
||||
struct rt_hw_stack_frame
|
||||
{
|
||||
rt_ubase_t epc; /* epc - epc - program counter */
|
||||
rt_ubase_t ra; /* x1 - ra - return address for jumps */
|
||||
rt_ubase_t mstatus; /* - machine status register */
|
||||
rt_ubase_t gp; /* x3 - gp - global pointer */
|
||||
rt_ubase_t tp; /* x4 - tp - thread pointer */
|
||||
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
|
||||
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
|
||||
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
|
||||
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
|
||||
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
|
||||
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
|
||||
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
|
||||
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
|
||||
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
|
||||
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
|
||||
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
|
||||
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
|
||||
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
|
||||
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
|
||||
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
|
||||
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
|
||||
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
|
||||
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
|
||||
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
|
||||
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
|
||||
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
|
||||
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
|
||||
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
|
||||
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
|
||||
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
|
||||
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
|
||||
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
|
||||
#ifdef ARCH_RISCV_FPU
|
||||
rv_floatreg_t f0; /* f0 */
|
||||
rv_floatreg_t f1; /* f1 */
|
||||
rv_floatreg_t f2; /* f2 */
|
||||
rv_floatreg_t f3; /* f3 */
|
||||
rv_floatreg_t f4; /* f4 */
|
||||
rv_floatreg_t f5; /* f5 */
|
||||
rv_floatreg_t f6; /* f6 */
|
||||
rv_floatreg_t f7; /* f7 */
|
||||
rv_floatreg_t f8; /* f8 */
|
||||
rv_floatreg_t f9; /* f9 */
|
||||
rv_floatreg_t f10; /* f10 */
|
||||
rv_floatreg_t f11; /* f11 */
|
||||
rv_floatreg_t f12; /* f12 */
|
||||
rv_floatreg_t f13; /* f13 */
|
||||
rv_floatreg_t f14; /* f14 */
|
||||
rv_floatreg_t f15; /* f15 */
|
||||
rv_floatreg_t f16; /* f16 */
|
||||
rv_floatreg_t f17; /* f17 */
|
||||
rv_floatreg_t f18; /* f18 */
|
||||
rv_floatreg_t f19; /* f19 */
|
||||
rv_floatreg_t f20; /* f20 */
|
||||
rv_floatreg_t f21; /* f21 */
|
||||
rv_floatreg_t f22; /* f22 */
|
||||
rv_floatreg_t f23; /* f23 */
|
||||
rv_floatreg_t f24; /* f24 */
|
||||
rv_floatreg_t f25; /* f25 */
|
||||
rv_floatreg_t f26; /* f26 */
|
||||
rv_floatreg_t f27; /* f27 */
|
||||
rv_floatreg_t f28; /* f28 */
|
||||
rv_floatreg_t f29; /* f29 */
|
||||
rv_floatreg_t f30; /* f30 */
|
||||
rv_floatreg_t f31; /* f31 */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
void *parameter,
|
||||
rt_uint8_t *stack_addr,
|
||||
void *texit)
|
||||
{
|
||||
struct rt_hw_stack_frame *frame;
|
||||
rt_uint8_t *stk;
|
||||
int i;
|
||||
|
||||
stk = stack_addr + sizeof(rt_ubase_t);
|
||||
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
|
||||
stk -= sizeof(struct rt_hw_stack_frame);
|
||||
|
||||
frame = (struct rt_hw_stack_frame *)stk;
|
||||
|
||||
for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
|
||||
{
|
||||
((rt_ubase_t *)frame)[i] = 0xdeadbeef;
|
||||
}
|
||||
|
||||
frame->ra = (rt_ubase_t)texit;
|
||||
frame->a0 = (rt_ubase_t)parameter;
|
||||
frame->epc = (rt_ubase_t)tentry;
|
||||
|
||||
/* force to machine mode(MPP=11) and set MPIE to 1 */
|
||||
frame->mstatus = 0x00007880;
|
||||
|
||||
return stk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* This function will disable global interrupt
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return zero
|
||||
*/
|
||||
|
||||
rt_base_t rt_hw_interrupt_disable(void)
|
||||
{
|
||||
__asm volatile("csrc mstatus, 8");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will ennable global interrupt
|
||||
*
|
||||
* @param level not used
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void rt_hw_interrupt_enable(rt_base_t level)
|
||||
{
|
||||
__asm volatile("csrs mstatus, 8");
|
||||
}
|
||||
|
||||
/** shutdown CPU */
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_uint32_t level;
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
while (level)
|
||||
{
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 zx.chen The first version
|
||||
*/
|
||||
|
||||
#ifndef CPUPORT_H__
|
||||
#define CPUPORT_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* bytes of register width */
|
||||
#ifdef ARCH_RISCV_64
|
||||
#define DFSTORE fsd
|
||||
#define DFLOAD fld
|
||||
#define SFSTORE fsw
|
||||
#define SFLOAD flw
|
||||
#define STORE sd
|
||||
#define LOAD ld
|
||||
#define REGBYTES 8
|
||||
#define SFREGBYTES 4
|
||||
#define DFREGBYTES 8
|
||||
#else
|
||||
#define DFSTORE fsd
|
||||
#define DFLOAD fld
|
||||
#define SFSTORE fsw
|
||||
#define SFLOAD flw
|
||||
#define STORE sw
|
||||
#define LOAD lw
|
||||
|
||||
#define REGBYTES 4
|
||||
#define SFREGBYTES 4
|
||||
#define DFREGBYTES 8
|
||||
#endif
|
||||
|
||||
#ifdef ARCH_RISCV_FPU
|
||||
#ifdef ARCH_RISCV_FPU_D
|
||||
#define FSTORE fsd
|
||||
#define FLOAD fld
|
||||
#define FREGBYTES 8
|
||||
#define rv_floatreg_t rt_int64_t
|
||||
#endif
|
||||
#ifdef ARCH_RISCV_FPU_S
|
||||
#define FSTORE fsw
|
||||
#define FLOAD flw
|
||||
#define FREGBYTES 4
|
||||
#define rv_floatreg_t rt_int32_t
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user