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Merge pull request #4907 from YJ98/stm32f302

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Add stm32f3 series bsp.
This commit is contained in:
guo authored and GitHub committed 2021-08-10 14:33:23 +08:00
2 parents ce1734fb31 53a4074f0b
commit 5e277b0325
347 files changed
+464721 -25
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.github/workflows/action.yml
+1
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@@ -79,6 +79,7 @@ jobs:
- {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f207-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f302-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
bsp/stm32/libraries/HAL_Drivers/config/f3/dma_config.h
+41
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@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-01-02 zylx first version
* 2019-01-08 SummerGift clean up the code
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Channel5
#define UART2_RX_DMA_CHANNEL DMA1_Channel5_BASE
#define UART2_RX_DMA_IRQ DMA1_Channel5_IRQn
#endif
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_TX_DMA_INSTANCE DMA1_Channel6
#define UART2_TX_DMA_CHANNEL DMA1_Channel6_BASE
#define UART2_TX_DMA_IRQ DMA1_Channel6_IRQn
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f3/pwm_config.h
+35
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@@ -0,0 +1,35 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-13 zylx first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.tim_handle.Instance = TIM1, \
.name = "pwm1", \
.channel = 0 \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f3/tim_config.h
+45
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@@ -0,0 +1,45 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-11 zylx first version
*/
#ifndef __TIM_CONFIG_H__
#define __TIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM1
#ifndef TIM1_CONFIG
#define TIM1_CONFIG \
{ \
.tim_handle.Instance = TIM1, \
.tim_irqn = TIM1_IRQn, \
.name = "timer1", \
}
#endif /* TIM1_CONFIG */
#endif /* BSP_USING_TIM1 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f3/uart_config.h
+130
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@@ -0,0 +1,130 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.dma_rcc = UART1_TX_DMA_RCC, \
.dma_irq = UART1_TX_DMA_IRQ, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif /* UART2_CONFIG */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.dma_rcc = UART2_TX_DMA_RCC, \
.dma_irq = UART2_TX_DMA_IRQ, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif /* UART3_CONFIG */
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.dma_rcc = UART3_RX_DMA_RCC, \
.dma_irq = UART3_RX_DMA_IRQ, \
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.channel = UART3_TX_DMA_CHANNEL, \
.dma_rcc = UART3_TX_DMA_RCC, \
.dma_irq = UART3_TX_DMA_IRQ, \
}
#endif /* UART3_DMA_TX_CONFIG */
#endif /* BSP_UART3_TX_USING_DMA */
#endif /* BSP_USING_UART3 */
#ifdef __cplusplus
}
#endif
#endif
bsp/stm32/libraries/HAL_Drivers/drv_can.c
+10 -10
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@@ -325,13 +325,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
* STD ID | STID[10:3] | STDID[2:0] |<- 21bit ->|
* EXT ID | EXTID[28:21] | EXTID[20:13] | EXTID[12:5] | EXTID[4:0] IDE RTR 0|
* @note the 32bit STD ID must << 21 to fill CAN_FxR1[31:21] and EXT ID must << 3,
* -> but the id bit of struct rt_can_filter_item is 29,
* -> but the id bit of struct rt_can_filter_item is 29,
* -> so STD id << 18 and EXT id Don't need << 3, when get the high 16bit.
* -> FilterIdHigh : (((STDid << 18) or (EXT id)) >> 13) & 0xFFFF,
* -> FilterIdLow: ((STDid << 18) or (EXT id << 3)) & 0xFFFF.
* @note the mask bit of struct rt_can_filter_item is 32,
* -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF
* -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF
* -> FilterIdLow: ((STDid << 18) or (EXT id << 3)) & 0xFFFF.
* @note the mask bit of struct rt_can_filter_item is 32,
* -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF
* -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF
*/
if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDMASK)
{
@@ -341,14 +341,14 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
else if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDLIST)
{
/* same as CAN_FxR1 */
mask_l_tail = (filter_cfg->items[i].ide << 2) |
mask_l_tail = (filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1);
}
if (filter_cfg->items[i].ide == RT_CAN_STDID)
{
id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF;
id_l = ((filter_cfg->items[i].id << 18) |
(filter_cfg->items[i].ide << 2) |
id_l = ((filter_cfg->items[i].id << 18) |
(filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF;
mask_l = ((filter_cfg->items[i].mask << 21) | mask_l_tail) & 0xFFFF;
@@ -356,8 +356,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
else if (filter_cfg->items[i].ide == RT_CAN_EXTID)
{
id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF;
id_l = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
id_l = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF;
mask_l = ((filter_cfg->items[i].mask << 3) | mask_l_tail) & 0xFFFF;
bsp/stm32/libraries/HAL_Drivers/drv_config.h
+5
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@@ -44,6 +44,11 @@ extern "C" {
#include "f2/tim_config.h"
#include "f2/sdio_config.h"
#include "f2/pwm_config.h"
#elif defined(SOC_SERIES_STM32F3)
#include "f3/uart_config.h"
#include "f3/tim_config.h"
#include "f3/pwm_config.h"
#include "f3/dma_config.h"
#elif defined(SOC_SERIES_STM32F4)
#include "f4/dma_config.h"
#include "f4/uart_config.h"
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
+2 -2
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@@ -20,7 +20,7 @@ extern "C" {
#endif
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
@@ -32,7 +32,7 @@ struct dma_config {
rt_uint32_t dma_rcc;
IRQn_Type dma_irq;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)|| defined(SOC_SERIES_STM32F3)
rt_uint32_t channel;
#endif
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c
+3 -3
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@@ -78,7 +78,7 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
if(addr % 32 != 0)
{
LOG_E("write addr must be 32-byte alignment");
@@ -171,7 +171,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
size_bank1 = 0;
addr_bank2 = addr;
size_bank2 = size;
size_bank2 = size;
}
else
{
@@ -188,7 +188,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
SCB_DisableDCache();
if(size_bank1)
{
EraseInitStruct.Sector = (addr_bank1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE;
bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
+17
View File
@@ -101,6 +101,23 @@ static const struct pin_irq_map pin_irq_map[] =
{GPIO_PIN_13, EXTI13_IRQn},
{GPIO_PIN_14, EXTI14_IRQn},
{GPIO_PIN_15, EXTI15_IRQn},
#elif defined(SOC_SERIES_STM32F3)
{GPIO_PIN_0, EXTI0_IRQn},
{GPIO_PIN_1, EXTI1_IRQn},
{GPIO_PIN_2, EXTI2_TSC_IRQn},
{GPIO_PIN_3, EXTI3_IRQn},
{GPIO_PIN_4, EXTI4_IRQn},
{GPIO_PIN_5, EXTI9_5_IRQn},
{GPIO_PIN_6, EXTI9_5_IRQn},
{GPIO_PIN_7, EXTI9_5_IRQn},
{GPIO_PIN_8, EXTI9_5_IRQn},
{GPIO_PIN_9, EXTI9_5_IRQn},
{GPIO_PIN_10, EXTI15_10_IRQn},
{GPIO_PIN_11, EXTI15_10_IRQn},
{GPIO_PIN_12, EXTI15_10_IRQn},
{GPIO_PIN_13, EXTI15_10_IRQn},
{GPIO_PIN_14, EXTI15_10_IRQn},
{GPIO_PIN_15, EXTI15_10_IRQn},
#else
{GPIO_PIN_0, EXTI0_IRQn},
{GPIO_PIN_1, EXTI1_IRQn},
bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
+1 -1
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@@ -290,7 +290,7 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)|| defined(SOC_SERIES_STM32F3)
if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
#elif defined(SOC_SERIES_STM32MP1)
if (htim->Instance == TIM4)
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
+1 -1
View File
@@ -263,7 +263,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
}
if(spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG || spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
HAL_NVIC_SetPriority(spi_drv->config->irq_type, 2, 0);
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+11 -4
View File
@@ -248,7 +248,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)
uart->handle.Instance->TDR = c;
#else
uart->handle.Instance->DR = c;
@@ -269,7 +269,7 @@ static int stm32_getc(struct rt_serial_device *serial)
{
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
ch = uart->handle.Instance->RDR & 0xff;
#else
ch = uart->handle.Instance->DR & 0xff;
@@ -373,10 +373,17 @@ static void uart_isr(struct rt_serial_device *serial)
#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
&& !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
&& !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
#ifdef SOC_SERIES_STM32F3
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
}
#else
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
}
#endif
#endif
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
{
@@ -866,7 +873,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32L0)
|| defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
@@ -900,7 +907,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
__HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
}
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3)
DMA_Handle->Instance = dma_config->Instance;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
DMA_Handle->Instance = dma_config->Instance;
bsp/stm32/libraries/HAL_Drivers/drv_usart.h
+2 -2
View File
@@ -22,7 +22,7 @@
int rt_hw_usart_init(void);
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
@@ -31,7 +31,7 @@ int rt_hw_usart_init(void);
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F2) \
|| defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32MP1)
bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/stm32/libraries/Kconfig
+5
View File
@@ -16,6 +16,11 @@ config SOC_SERIES_STM32F2
select ARCH_ARM_CORTEX_M3
select SOC_FAMILY_STM32
config SOC_SERIES_STM32F3
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_STM32
config SOC_SERIES_STM32F4
bool
select ARCH_ARM_CORTEX_M4
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h
+8610
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h
+12383
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h
+12726
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h
+14470
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h
+12137
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h
+13475
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h
+15331
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h
+8597
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h
+12107
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h
+15104
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h
+13242
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h
+12021
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h
+11797
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h
+15085
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h
+232
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h
+106
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@@ -0,0 +1,106 @@
/**
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f3xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F3XX_H
#define __SYSTEM_STM32F3XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F3xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
3) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) by calling HAL API function HAL_RCC_ClockConfig()
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F3XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f301x8.s
+346
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302x8.s
+362
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xc.s
+378
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xe.s
+397
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303x8.s
+348
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xc.s
+394
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xe.s
+413
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f318xx.s
+344
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f328xx.s
+346
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f334x8.s
+362
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f358xx.s
+385
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f373xc.s
+390
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f378xx.s
+382
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f398xx.s
+404
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f301x8.s
+390
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302x8.s
+414
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xc.s
+438
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xe.s
+465
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303x8.s
+393
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xc.s
+462
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xe.s
+489
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f318xx.s
+387
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f328xx.s
+390
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f334x8.s
+414
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f358xx.s
+447
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f373xc.s
+456
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f378xx.s
+444
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f398xx.s
+474
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bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf
+31
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@@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf
+31
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@@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf
+31
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@@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf
+31
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@@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf
+34
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@@ -0,0 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf
+34
View File
@@ -0,0 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10001FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf
+34
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@@ -0,0 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10001FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
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