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[bsp/renesas]add ek-ra8d1 bsp

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This commit is contained in:
Rbb666
2023-12-17 21:19:16 +08:00
committed by guo
parent 6d1fdde1ff
commit 5dd87bc7bb
161 changed files with 125123 additions and 2 deletions
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1
.github/workflows/bsp_buildings.yml vendored
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@@ -202,6 +202,7 @@ jobs:
- "renesas/ra4m2-eco"
- "renesas/ra2l1-cpk"
- "renesas/ra8m1-ek"
- "renesas/ra8d1-ek"
- RTT_BSP: "gd32_n32_apm32"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:

1
bsp/renesas/README.md
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@@ -17,6 +17,7 @@ RA 系列 BSP 目前支持情况如下表所示：
| [ra2l1-cpk](ra2l1-cpk) | Renesas 官方 CPK-RA2L1 开发板 |
| **RA8 系列** | |
| [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 |
| [ra8d1-ek](ra8d1-ek) | Renesas 官方 EK-RA8D1 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

2
bsp/renesas/libraries/HAL_Drivers/drv_gpio.c
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@@ -173,7 +173,7 @@ static rt_int8_t ra_pin_read(rt_device_t dev, rt_base_t pin)
if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
{
LOG_E("GPIO pin value is illegal");
return -RT_ERROR;
return -1;
}
return R_BSP_PinRead(pin);
}

27
bsp/renesas/libraries/HAL_Drivers/drv_log.h Normal file
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@@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

1050
bsp/renesas/ra8d1-ek/.config Normal file
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222
bsp/renesas/ra8d1-ek/.cproject Normal file
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5
bsp/renesas/ra8d1-ek/.gitignore vendored Normal file
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@@ -0,0 +1,5 @@
/RTE
/Listings
/Objects
ra_cfg.txt

9
bsp/renesas/ra8d1-ek/.ignore_format.yml Normal file
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@@ -0,0 +1,9 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- ra
- ra_gen
- ra_cfg
- RTE

28
bsp/renesas/ra8d1-ek/.project Normal file
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@@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ra6m3-temp</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.rt-thread.studio.rttnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources />
</projectDescription>

184
bsp/renesas/ra8d1-ek/.secure_azone Normal file
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@@ -0,0 +1,184 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
<rzone name="R7FA8D1BHECBD.rzone"/>
<partition>
<peripheral name="PORT0" group="PORT">
<slot name="P002" secure="true"/>
<slot name="P003" secure="true"/>
<slot name="P004" secure="true"/>
<slot name="P005" secure="true"/>
<slot name="P007" secure="true"/>
<slot name="P011" secure="true"/>
<slot name="P014" secure="true"/>
<slot name="P015" secure="true"/>
</peripheral>
<peripheral name="PORT1" group="PORT">
<slot name="P100" secure="true"/>
<slot name="P101" secure="true"/>
<slot name="P102" secure="true"/>
<slot name="P103" secure="true"/>
<slot name="P104" secure="true"/>
<slot name="P105" secure="true"/>
<slot name="P106" secure="true"/>
<slot name="P107" secure="true"/>
<slot name="P112" secure="true"/>
<slot name="P113" secure="true"/>
<slot name="P114" secure="true"/>
<slot name="P115" secure="true"/>
</peripheral>
<peripheral name="PORT2" group="PORT">
<slot name="P206" secure="true"/>
<slot name="P207" secure="true"/>
<slot name="P208" secure="true"/>
<slot name="P209" secure="true"/>
<slot name="P210" secure="true"/>
<slot name="P211" secure="true"/>
</peripheral>
<peripheral name="PORT3" group="PORT">
<slot name="P300" secure="true"/>
<slot name="P301" secure="true"/>
<slot name="P302" secure="true"/>
<slot name="P303" secure="true"/>
<slot name="P304" secure="true"/>
<slot name="P305" secure="true"/>
<slot name="P306" secure="true"/>
<slot name="P307" secure="true"/>
<slot name="P308" secure="true"/>
<slot name="P309" secure="true"/>
<slot name="P310" secure="true"/>
<slot name="P311" secure="true"/>
<slot name="P312" secure="true"/>
</peripheral>
<peripheral name="PORT4" group="PORT">
<slot name="P400" secure="true"/>
<slot name="P401" secure="true"/>
<slot name="P402" secure="true"/>
<slot name="P403" secure="true"/>
<slot name="P405" secure="true"/>
<slot name="P406" secure="true"/>
<slot name="P407" secure="true"/>
<slot name="P408" secure="true"/>
<slot name="P409" secure="true"/>
<slot name="P410" secure="true"/>
<slot name="P411" secure="true"/>
<slot name="P412" secure="true"/>
<slot name="P413" secure="true"/>
<slot name="P414" secure="true"/>
<slot name="P415" secure="true"/>
</peripheral>
<peripheral name="PORT5" group="PORT">
<slot name="P500" secure="true"/>
<slot name="P501" secure="true"/>
<slot name="P504" secure="true"/>
<slot name="P505" secure="true"/>
<slot name="P506" secure="true"/>
<slot name="P507" secure="true"/>
<slot name="P511" secure="true"/>
<slot name="P512" secure="true"/>
<slot name="P513" secure="true"/>
<slot name="P514" secure="true"/>
<slot name="P515" secure="true"/>
</peripheral>
<peripheral name="PORT6" group="PORT">
<slot name="P600" secure="true"/>
<slot name="P601" secure="true"/>
<slot name="P602" secure="true"/>
<slot name="P603" secure="true"/>
<slot name="P604" secure="true"/>
<slot name="P605" secure="true"/>
<slot name="P606" secure="true"/>
<slot name="P607" secure="true"/>
<slot name="P609" secure="true"/>
<slot name="P610" secure="true"/>
<slot name="P611" secure="true"/>
<slot name="P612" secure="true"/>
<slot name="P613" secure="true"/>
<slot name="P614" secure="true"/>
<slot name="P615" secure="true"/>
</peripheral>
<peripheral name="PORT7" group="PORT">
<slot name="P700" secure="true"/>
<slot name="P701" secure="true"/>
<slot name="P702" secure="true"/>
<slot name="P703" secure="true"/>
<slot name="P704" secure="true"/>
<slot name="P705" secure="true"/>
<slot name="P706" secure="true"/>
<slot name="P707" secure="true"/>
<slot name="P708" secure="true"/>
<slot name="P709" secure="true"/>
<slot name="P710" secure="true"/>
<slot name="P711" secure="true"/>
<slot name="P712" secure="true"/>
<slot name="P713" secure="true"/>
<slot name="P714" secure="true"/>
<slot name="P715" secure="true"/>
</peripheral>
<peripheral name="PORT8" group="PORT">
<slot name="P800" secure="true"/>
<slot name="P801" secure="true"/>
<slot name="P802" secure="true"/>
<slot name="P803" secure="true"/>
<slot name="P804" secure="true"/>
<slot name="P805" secure="true"/>
<slot name="P806" secure="true"/>
<slot name="P807" secure="true"/>
<slot name="P808" secure="true"/>
<slot name="P809" secure="true"/>
<slot name="P810" secure="true"/>
<slot name="P811" secure="true"/>
<slot name="P813" secure="true"/>
<slot name="P814" secure="true"/>
<slot name="P815" secure="true"/>
</peripheral>
<peripheral name="PORT9" group="PORT">
<slot name="P902" secure="true"/>
<slot name="P903" secure="true"/>
<slot name="P904" secure="true"/>
<slot name="P905" secure="true"/>
<slot name="P906" secure="true"/>
<slot name="P907" secure="true"/>
<slot name="P908" secure="true"/>
<slot name="P909" secure="true"/>
<slot name="P910" secure="true"/>
<slot name="P911" secure="true"/>
<slot name="P912" secure="true"/>
<slot name="P913" secure="true"/>
<slot name="P914" secure="true"/>
<slot name="P915" secure="true"/>
</peripheral>
<peripheral name="PORTA" group="PORT">
<slot name="PA00" secure="true"/>
<slot name="PA01" secure="true"/>
<slot name="PA02" secure="true"/>
<slot name="PA03" secure="true"/>
<slot name="PA04" secure="true"/>
<slot name="PA05" secure="true"/>
<slot name="PA06" secure="true"/>
<slot name="PA07" secure="true"/>
<slot name="PA08" secure="true"/>
<slot name="PA09" secure="true"/>
<slot name="PA10" secure="true"/>
<slot name="PA11" secure="true"/>
<slot name="PA13" secure="true"/>
<slot name="PA14" secure="true"/>
<slot name="PA15" secure="true"/>
</peripheral>
<peripheral name="PORTB" group="PORT">
<slot name="PB00" secure="true"/>
<slot name="PB01" secure="true"/>
<slot name="PB02" secure="true"/>
<slot name="PB03" secure="true"/>
<slot name="PB04" secure="true"/>
<slot name="PB05" secure="true"/>
<slot name="PB06" secure="true"/>
<slot name="PB07" secure="true"/>
</peripheral>
<peripheral name="ICU">
<slot name="IRQ0" secure="true"/>
<slot name="IRQ1" secure="true"/>
<slot name="IRQ2" secure="true"/>
<slot name="IRQ3" secure="true"/>
</peripheral>
</partition>
</azone>

246
bsp/renesas/ra8d1-ek/.secure_xml Normal file
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@@ -0,0 +1,246 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="8">
<generalSettings>
<option key="#Board#" value="board.ra8d1ek"/>
<option key="CPU" value="RA8D1"/>
<option key="Core" value="CM85"/>
<option key="#TargetName#" value="R7FA8D1BHECBD"/>
<option key="#TargetARCHITECTURE#" value="cortex-m85"/>
<option key="#DeviceCommand#" value="R7FA8D1BH"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/>
<option key="#FSPVersion#" value="5.1.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##|Renesas##BSP##Board##ra8d1_ek##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration/>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.1"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.48_00"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/>
<node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/>
<node id="board.clock.pll1q.div" option="board.clock.pll1q.div.4"/>
<node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/>
<node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/>
<node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.1"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.48_00"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/>
<node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/>
<node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/>
<node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/>
<node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/>
<node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.sciclk.source" option="board.clock.sciclk.source.pll1p"/>
<node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.lcdclk.source" option="board.clock.lcdclk.source.pll1p"/>
<node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
<node id="board.clock.uck.source" option="board.clock.uck.source.pll1q"/>
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/>
<node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/>
<node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/>
<node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/>
<node id="board.clock.lcdclk.div" option="board.clock.lcdclk.div.2"/>
<node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/>
<node id="board.clock.uck.div" option="board.clock.uck.div.5"/>
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.5"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/>
<node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/>
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/>
<node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.lcdclk.display" option="board.clock.lcdclk.display.value"/>
<node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
<node id="board.clock.uck.display" option="board.clock.uck.display.value"/>
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raPinConfiguration>
<pincfg active="true" name="" symbol="">
<configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/>
<configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/>
<configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/>
<configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/>
<configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/>
<configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/>
<configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/>
<configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/>
<configSetting altId="ceu.vio_clk.p708" configurationId="ceu.vio_clk"/>
<configSetting altId="ceu.vio_d0.p400" configurationId="ceu.vio_d0"/>
<configSetting altId="ceu.vio_d12.p415" configurationId="ceu.vio_d12"/>
<configSetting altId="ceu.vio_hd.p709" configurationId="ceu.vio_hd"/>
<configSetting altId="ceu.vio_vd.p710" configurationId="ceu.vio_vd"/>
<configSetting altId="ether_rmii.et0_linksta.p403" configurationId="ether_rmii.et0_linksta"/>
<configSetting altId="ether_rmii.et0_mdc.p401" configurationId="ether_rmii.et0_mdc"/>
<configSetting altId="ether_rmii.et0_mdio.p402" configurationId="ether_rmii.et0_mdio"/>
<configSetting altId="ether_rmii.ref50ck0.p701" configurationId="ether_rmii.ref50ck0"/>
<configSetting altId="ether_rmii.rmii0_crs_dv.p705" configurationId="ether_rmii.rmii0_crs_dv"/>
<configSetting altId="ether_rmii.rmii0_rx_er.p704" configurationId="ether_rmii.rmii0_rx_er"/>
<configSetting altId="ether_rmii.rmii0_rxd0.p702" configurationId="ether_rmii.rmii0_rxd0"/>
<configSetting altId="ether_rmii.rmii0_rxd1.p703" configurationId="ether_rmii.rmii0_rxd1"/>
<configSetting altId="ether_rmii.rmii0_txd0.p700" configurationId="ether_rmii.rmii0_txd0"/>
<configSetting altId="ether_rmii.rmii0_txd1.p406" configurationId="ether_rmii.rmii0_txd1"/>
<configSetting altId="ether_rmii.rmii0_txd_en.p405" configurationId="ether_rmii.rmii0_txd_en"/>
<configSetting altId="glcd.lcd_clk.p806" configurationId="glcd.lcd_clk"/>
<configSetting altId="glcd.lcd_data0.p914" configurationId="glcd.lcd_data0"/>
<configSetting altId="glcd.lcd_data1.p915" configurationId="glcd.lcd_data1"/>
<configSetting altId="glcd.lcd_data10.p711" configurationId="glcd.lcd_data10"/>
<configSetting altId="glcd.lcd_data11.p712" configurationId="glcd.lcd_data11"/>
<configSetting altId="glcd.lcd_data12.p713" configurationId="glcd.lcd_data12"/>
<configSetting altId="glcd.lcd_data13.p714" configurationId="glcd.lcd_data13"/>
<configSetting altId="glcd.lcd_data14.p715" configurationId="glcd.lcd_data14"/>
<configSetting altId="glcd.lcd_data15.pb07" configurationId="glcd.lcd_data15"/>
<configSetting altId="glcd.lcd_data16.pb06" configurationId="glcd.lcd_data16"/>
<configSetting altId="glcd.lcd_data17.pb05" configurationId="glcd.lcd_data17"/>
<configSetting altId="glcd.lcd_data18.pb01" configurationId="glcd.lcd_data18"/>
<configSetting altId="glcd.lcd_data19.pb04" configurationId="glcd.lcd_data19"/>
<configSetting altId="glcd.lcd_data2.p910" configurationId="glcd.lcd_data2"/>
<configSetting altId="glcd.lcd_data20.pb03" configurationId="glcd.lcd_data20"/>
<configSetting altId="glcd.lcd_data21.pb02" configurationId="glcd.lcd_data21"/>
<configSetting altId="glcd.lcd_data22.pb00" configurationId="glcd.lcd_data22"/>
<configSetting altId="glcd.lcd_data23.p707" configurationId="glcd.lcd_data23"/>
<configSetting altId="glcd.lcd_data3.p911" configurationId="glcd.lcd_data3"/>
<configSetting altId="glcd.lcd_data4.p912" configurationId="glcd.lcd_data4"/>
<configSetting altId="glcd.lcd_data5.p913" configurationId="glcd.lcd_data5"/>
<configSetting altId="glcd.lcd_data6.p904" configurationId="glcd.lcd_data6"/>
<configSetting altId="glcd.lcd_data7.p903" configurationId="glcd.lcd_data7"/>
<configSetting altId="glcd.lcd_data8.p902" configurationId="glcd.lcd_data8"/>
<configSetting altId="glcd.lcd_data9.p207" configurationId="glcd.lcd_data9"/>
<configSetting altId="glcd.lcd_extclk.p514" configurationId="glcd.lcd_extclk"/>
<configSetting altId="glcd.lcd_tcon0.p805" configurationId="glcd.lcd_tcon0"/>
<configSetting altId="glcd.lcd_tcon1.p807" configurationId="glcd.lcd_tcon1"/>
<configSetting altId="glcd.lcd_tcon2.p513" configurationId="glcd.lcd_tcon2"/>
<configSetting altId="glcd.lcd_tcon3.p515" configurationId="glcd.lcd_tcon3"/>
<configSetting altId="iic1.scl1.p512" configurationId="iic1.scl1"/>
<configSetting altId="iic1.sda1.p511" configurationId="iic1.sda1"/>
<configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/>
<configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/>
<configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/>
<configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/>
<configSetting altId="mipi.dsi_te.p206" configurationId="mipi.dsi_te"/>
<configSetting altId="ospi.om_cs1.p104" configurationId="ospi.om_cs1"/>
<configSetting altId="ospi.om_dqs.p801" configurationId="ospi.om_dqs"/>
<configSetting altId="ospi.om_ecsint1.p105" configurationId="ospi.om_ecsint1"/>
<configSetting altId="ospi.om_reset.p106" configurationId="ospi.om_reset"/>
<configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/>
<configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/>
<configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/>
<configSetting altId="ospi.om_sio2.p103" configurationId="ospi.om_sio2"/>
<configSetting altId="ospi.om_sio3.p101" configurationId="ospi.om_sio3"/>
<configSetting altId="ospi.om_sio4.p102" configurationId="ospi.om_sio4"/>
<configSetting altId="ospi.om_sio5.p800" configurationId="ospi.om_sio5"/>
<configSetting altId="ospi.om_sio6.p802" configurationId="ospi.om_sio6"/>
<configSetting altId="ospi.om_sio7.p804" configurationId="ospi.om_sio7"/>
<configSetting altId="p107.output.low" configurationId="p107"/>
<configSetting altId="p414.output.low" configurationId="p414"/>
<configSetting altId="p504.input" configurationId="p504"/>
<configSetting altId="p505.input" configurationId="p505"/>
<configSetting altId="p506.input" configurationId="p506"/>
<configSetting altId="p507.output.low" configurationId="p507"/>
<configSetting altId="p600.output.low" configurationId="p600"/>
<configSetting altId="p706.output.low" configurationId="p706"/>
<configSetting altId="p809.output.low" configurationId="p809"/>
<configSetting altId="p810.input" configurationId="p810"/>
<configSetting altId="p811.input" configurationId="p811"/>
<configSetting altId="p813.output.low" configurationId="p813"/>
<configSetting altId="p907.input" configurationId="p907"/>
<configSetting altId="pa01.input" configurationId="pa01"/>
<configSetting altId="pa06.input" configurationId="pa06"/>
<configSetting altId="pa07.input" configurationId="pa07"/>
<configSetting altId="pa11.input" configurationId="pa11"/>
<configSetting altId="pa13.output.low" configurationId="pa13"/>
<configSetting altId="sci2.cts_rts2.pa05" configurationId="sci2.cts_rts2"/>
<configSetting altId="sci2.rxd2.pa02" configurationId="sci2.rxd2"/>
<configSetting altId="sci2.sck2.pa04" configurationId="sci2.sck2"/>
<configSetting altId="sci2.txd2.pa03" configurationId="sci2.txd2"/>
<configSetting altId="sci3.rxd3.p408" configurationId="sci3.rxd3"/>
<configSetting altId="sci3.txd3.p409" configurationId="sci3.txd3"/>
<configSetting altId="sci9.rxd9.pa15" configurationId="sci9.rxd9" isUsedByDriver="true"/>
<configSetting altId="sci9.txd9.pa14" configurationId="sci9.txd9" isUsedByDriver="true"/>
<configSetting altId="sdram.a1.p300" configurationId="sdram.a1"/>
<configSetting altId="sdram.a10.p309" configurationId="sdram.a10"/>
<configSetting altId="sdram.a11.p310" configurationId="sdram.a11"/>
<configSetting altId="sdram.a12.p311" configurationId="sdram.a12"/>
<configSetting altId="sdram.a13.p312" configurationId="sdram.a13"/>
<configSetting altId="sdram.a14.p905" configurationId="sdram.a14"/>
<configSetting altId="sdram.a15.p906" configurationId="sdram.a15"/>
<configSetting altId="sdram.a2.p301" configurationId="sdram.a2"/>
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<configSetting altId="sdram.a4.p303" configurationId="sdram.a4"/>
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<configSetting altId="sdram.a6.p305" configurationId="sdram.a6"/>
<configSetting altId="sdram.a7.p306" configurationId="sdram.a7"/>
<configSetting altId="sdram.a8.p307" configurationId="sdram.a8"/>
<configSetting altId="sdram.a9.p308" configurationId="sdram.a9"/>
<configSetting altId="sdram.cas.p909" configurationId="sdram.cas"/>
<configSetting altId="sdram.cke.p113" configurationId="sdram.cke"/>
<configSetting altId="sdram.dq0.p601" configurationId="sdram.dq0"/>
<configSetting altId="sdram.dq1.p602" configurationId="sdram.dq1"/>
<configSetting altId="sdram.dq10.p611" configurationId="sdram.dq10"/>
<configSetting altId="sdram.dq11.p612" configurationId="sdram.dq11"/>
<configSetting altId="sdram.dq12.p613" configurationId="sdram.dq12"/>
<configSetting altId="sdram.dq13.p614" configurationId="sdram.dq13"/>
<configSetting altId="sdram.dq14.p615" configurationId="sdram.dq14"/>
<configSetting altId="sdram.dq15.pa08" configurationId="sdram.dq15"/>
<configSetting altId="sdram.dq2.p603" configurationId="sdram.dq2"/>
<configSetting altId="sdram.dq3.p604" configurationId="sdram.dq3"/>
<configSetting altId="sdram.dq4.p605" configurationId="sdram.dq4"/>
<configSetting altId="sdram.dq5.p606" configurationId="sdram.dq5"/>
<configSetting altId="sdram.dq6.p607" configurationId="sdram.dq6"/>
<configSetting altId="sdram.dq7.pa00" configurationId="sdram.dq7"/>
<configSetting altId="sdram.dq8.p609" configurationId="sdram.dq8"/>
<configSetting altId="sdram.dq9.p610" configurationId="sdram.dq9"/>
<configSetting altId="sdram.dqm0.pa10" configurationId="sdram.dqm0"/>
<configSetting altId="sdram.dqm1.p112" configurationId="sdram.dqm1"/>
<configSetting altId="sdram.ras.p908" configurationId="sdram.ras"/>
<configSetting altId="sdram.sdclk.pa09" configurationId="sdram.sdclk"/>
<configSetting altId="sdram.sdcs.p115" configurationId="sdram.sdcs"/>
<configSetting altId="sdram.we.p114" configurationId="sdram.we"/>
<configSetting altId="spi1.miso1.p410" configurationId="spi1.miso1"/>
<configSetting altId="spi1.mosi1.p411" configurationId="spi1.mosi1"/>
<configSetting altId="spi1.rspck1.p412" configurationId="spi1.rspck1"/>
<configSetting altId="spi1.sslb0.p413" configurationId="spi1.sslb0"/>
<configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/>
<configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/>
<configSetting altId="usbfs.usb_ovrcura.p501" configurationId="usbfs.usb_ovrcura"/>
<configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/>
<configSetting altId="usbfs.usb_vbusen.p500" configurationId="usbfs.usb_vbusen"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

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bsp/renesas/ra8d1-ek/.settings/.rtmenus Normal file
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bsp/renesas/ra8d1-ek/.settings/language.settings.xml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1208902908258079360" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

3
bsp/renesas/ra8d1-ek/.settings/org.eclipse.core.runtime.prefs Normal file
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content-types/enabled=true
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
eclipse.preferences.version=1

19
bsp/renesas/ra8d1-ek/.settings/projcfg.ini Normal file
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#RT-Thread Studio Project Configuration
#Tue Jan 10 14:37:39 CST 2023
cfg_version=v3.0
board_name=ra6m3-ek
example_name=
hardware_adapter=J-Link
board_base_nano_proj=false
project_type=rt-thread
chip_name=R7FA6M3AH\n
selected_rtt_version=latest
bsp_version=
os_branch=master
project_base_rtt_bsp=true
output_project_path=E\:softwareRT-ThreadStudioworkspace\ra6m3-temp
is_base_example_project=false
is_use_scons_build=true
project_name=ra6m3-temp
os_version=latest
bsp_path=

90
bsp/renesas/ra8d1-ek/.settings/ra6m3-temp.JLink.Debug.rttlaunch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDownloadHex" value="true"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
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<listEntry value="4"/>
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</launchConfiguration>

21
bsp/renesas/ra8d1-ek/.settings/standalone.prefs Normal file
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@@ -0,0 +1,21 @@
#Sun Dec 17 21:02:40 CST 2023
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra8d1_ek\#\#\#\#5.1.0/all=3509892698,ra/board/ra8d1_ek/board_leds.h|3819758545,ra/board/ra8d1_ek/board_sdram.c|2603656871,ra/board/ra8d1_ek/board_leds.c|3640013112,ra/board/ra8d1_ek/board_sdram.h|105041966,ra/board/ra8d1_ek/board_init.h|95488157,ra/board/ra8d1_ek/board.h|1628416776,ra/board/ra8d1_ek/board_ethernet_phy.h|777474786,ra/board/ra8d1_ek/board_init.c
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.1.0/all=3058606325,ra/fsp/inc/instances/r_ioport.h|1896254027,ra/fsp/inc/api/r_ioport_api.h|3002446768,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#R7FA8D1BHECBD\#\#5.1.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#\#\#5.1.0/all=3387474234,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#fsp\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_b_uart\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#fsp\#\#\#\#5.1.0/all=4143092756,script/fsp.scat|346195372,script/ac6/fsp_keep.via|934437302,ra/fsp/inc/fsp_features.h|3058606325,ra/fsp/inc/instances/r_ioport.h|543620856,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1171232788,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|296810838,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1632728582,ra/fsp/src/bsp/mcu/all/bsp_common.h|2702335218,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3171976222,ra/fsp/src/bsp/mcu/all/bsp_security.c|429234293,ra/fsp/src/bsp/mcu/all/bsp_common.c|2365965045,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1835725510,ra/fsp/src/bsp/mcu/all/bsp_io.c|271204625,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3610800851,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3569788004,ra/fsp/src/bsp/mcu/all/bsp_io.h|3085135894,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1246740431,ra/fsp/src/bsp/mcu/all/bsp_delay.h|248082807,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1884526901,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2942105346,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1331691689,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|4116718951,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1668386995,ra/fsp/src/bsp/mcu/all/bsp_security.h|2551036977,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3324174567,ra/fsp/src/bsp/mcu/all/bsp_exceptions.h|3881030941,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1437525339,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|4092753007,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2550773705,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|690210506,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2190391198,ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h|944400528,ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h|3051997639,ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h|4150320773,ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.5.1.0/all=1441545198,ra/arm/CMSIS_5/LICENSE.txt|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_b_uart\#\#\#\#5.1.0/all=419014891,ra/fsp/inc/instances/r_sci_b_uart.h|3115705082,ra/fsp/inc/api/r_transfer_api.h|1476071459,ra/fsp/inc/api/r_uart_api.h|3063216256,ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#R7FA8D1BHECBD\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.1.0/all=3217525171,ra/fsp/inc/fsp_version.h|1896254027,ra/fsp/inc/api/r_ioport_api.h|2560512765,ra/fsp/inc/api/bsp_api.h|1037141086,ra/fsp/inc/api/fsp_common_api.h|4290340792,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3088407548,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra8d1_ek\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_b_uart.1514241209=false
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.5.1.0/libraries=

29
bsp/renesas/ra8d1-ek/Kconfig Normal file
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@@ -0,0 +1,29 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "$BSP_DIR/board/Kconfig"

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# 瑞萨 EK-RA8D1 开发板 BSP 说明
中文|[English](README_EN.md)
## 简介
本文档为 EK-RA8D1 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
基于瑞萨 RA8D1 MCU 开发的 EK-RA8D1 评估板，通过灵活配置软件包和 IDE，可帮助用户对 RA8 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。
开发板正面外观如下图：
![](docs/picture/front.png)
该开发板常用 **板载资源** 如下：
- MCU：R7FA8D1BH，480MHz，**Arm®Cortex®-M85** 内核，2MB 代码闪存, 1MB SRAM
- Jlink OB
- OSPI FLASH（64MX8）
- USB-Host
- USB-Device
- CANFD
- 以太网接口
- 2个PMOD+Arduino+micro BUS接口
- 3个用户LED
- 3个按键：2个用户按键，1个复位按键
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------: | :----------------: | :------------: |
| UART | 支持 | UART9 为默认日志输出端口 |
| GPIO | 支持 | |
| USB | 支持 | TinyUSB |
| Camera | 支持 | ov2640、ov7725、ov7670... |
| SDHC | 支持 | 1bit、4bit |
| ADC | 支持 | |
| DAC | 支持 | |
| SPI | 支持 | |
| PWM | 支持 | |
| RTC | 支持 | |
| FLASH | 支持 | 片上flash |
| WDT | 支持 | |
| IIC | 支持 | |
* 注意：仓库刚拉下来是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 支持的编译平台
* armclang（AC6 V6.19）
* LLVM（V16/17）[ARM-software/LLVM-embedded-toolchain-for-Arm (github.com)](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)
## FSP版本说明
本BSP使用的是FSP5.1.0版本，进行外设相关开发需要下载并安装。
* 下载链接：[rasc-5.1.0](https://github.com/renesas/fsp/releases/download/v5.1.0/setup_fsp_v5_1_0_rasc_v2023-10.exe)
* 注意：BSP默认是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
### 快速上手
#### 1、使用 MDK 编译：
本 BSP 目前提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**编译下载**
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
- 下载：点击 MDK 的 Debug 按钮进行下载调试
#### 2、使用 LLVM 编译
使用 env 工具打开当前 bsp，设定要使用的工具链和对应的路径。
```shell
set RTT_CC=llvm-arm
set RTT_EXEC_PATH=D:\Progrem\LLVMEmbeddedToolchainForArm-17.0.1-Windows-x86_64\bin
```
然后运行 scons 命令，执行编译
```shell
scons
```
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
initialize rti_board_start:0 done
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Oct 30 2023 16:14:05
2006 - 2022 Copyright by RT-Thread team
do components initialization.
initialize rti_board_end:0 done
initialize finsh_system_init:0 done
Hello RT-Thread!
msh >
```
**应用入口函数**
应用层的入口函数在 **bsp\renesas\ra8d1-ek\src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### 进阶使用
**资料及文档**
- [开发板官网主页](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8d1-evaluation-kit-ra8d1-mcu-group#overview)
- [开发板用户手册](https://www.renesas.cn/cn/zh/document/mat/ek-ra8d1-v1-users-manual?r=25452351)
- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 UART9 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 EK-RA8D1 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

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# EK-RA8D1 BSP Instruction
中文|[English](README.md)
## Introduction
Prepare for an exhilarating journey into the realm of the EK-RA8D1 development board! This guide is your treasure map, leading you to a trove of knowledge about the Board Support Package (BSP). The Quick Start section is your launchpad, propelling developers into action with the BSP, and getting RT-Thread operational on the development board faster than a speeding bullet.
Here’s a sneak peek of the adventure that awaits:
• A captivating exploration of the development board
• A practical and user-friendly BSP Quick Start Guide
## Hardware
The EK-RA8D1 evaluation board, developed based on the Renesas RA8D1 MCU, is a handy tool that allows users to easily evaluate the features of the RA8 MCU group. With flexible software package and IDE configurations, it’s a breeze to develop embedded system applications.
Here’s a sneak peek of what the front of the development board looks like:
![](docs/picture/front.png)
The board comes with some commonly used **on-board resources**. Let’s dive in and explore!
- MCU：R7FA8D1BH, 480MHz, **Arm®Cortex®-M85**, 2MB Flash, 1MB SRAM
- Jlink OB
- OSPI FLASH（64MX8）
- USB-Host
- USB-Device
- CANFD
- ethernet
- 2个PMOD+Arduino+micro BUS interface
- 3 user LED
- 3 button: 2 user button, 1 reset button
**More Details**
### Peripheral Condition
Each peripheral supporting condition for this BSP is as follows:
| **On-chip Peripheral Drivers** | **Support** | **Remark** |
| :----------------: | :----------------: | :------------- |
| UART | Support | UART9 is the default log output port. |
| GPIO | Support | |
| USB | Support | TinyUSB |
| Camera | Support | ov2640、ov7725、ov7670... |
| SDHC | Support | 1bit、4bit |
| ADC | Support | |
| DAC | Support | |
| SPI | Support | |
| PWM | Support | |
| RTC | Support | |
| FLASH | Support | On board flash |
| WDT | Support | |
| IIC | Support | |
## Instructions for Use
The instructions for use are divided into the following two sections:
• Quick Start
This section is a user guide for newcomers to RT-Thread. By following simple steps, you can run the RT-Thread operating system on this development board and see the experimental results.
• Advanced Use
This section is for developers who want to enable more development board resources on the RT-Thread operating system. By using the ENV tool to configure the BSP, you can enable more on-board resources and achieve more advanced functions.
### Quick Start
This BSP currently only provides an MDK5 project. The following tutorial takes the MDK5 development environment as an example to introduce how to run the system.
**Compile and Download**
• Compile: Double-click the **project.uvprojx** file to open the MDK5 project and compile the program.
• Download: Click the Debug button in MDK to download and debug
**Running results**
After the program is downloaded successfully, the system will automatically run and print system information.
Connect the corresponding serial port of the development board to the PC, open the corresponding serial port (115200-8-1-N) in the terminal tool, reset the device, and you can see RT-Thread’s output information. Enter the help command can view the commands supported by the system.
```bash
initialize rti_board_start:0 done
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Oct 30 2023 16:14:05
2006 - 2022 Copyright by RT-Thread team
do components initialization.
initialize rti_board_end:0 done
initialize finsh_system_init:0 done
Hello RT-Thread!
msh >
```
**Entry function**
The entry function of the application layer is in **bsp\renesas\ra8d1-ek\src\hal_entry.c** in `void hal_entry(void)`. Source files that you created can be placed directly in the src directory.
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### Advanced Features
**Resources & Documents**
- [Development Board Overview](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8d1-evaluation-kit-ra8d1-mcu-group#documents)
- [User Guide](https://www.renesas.com/us/en/document/mat/ek-ra8d1-v1-users-manual?r=25452351)
- [RA MCU](https://www.renesas.com/us/en/document/gde/1520091)
**ENV Configuration**
• How to use the ENV tool: [RT-Thread env tool user manual](https://www.rt-thread.io/document/site/programming-manual/env/env/).
This BSP only enables the function of UART9 by default. If you're looking for more advanced functions such as components and software packages, ENV tool for configuration is available.
The steps are as follows:
1. Open the env tool under bsp.
2. Enter the `menuconfig` command to configure the project, and save and exit after configuration.
3. Enter the `pkgs --update` command to update the software package.
4. Enter the `scons --target=mdk5` command to regenerate the project.
## Contribute the Code
If you’re interested in the EK-RA8D1 and have some cool projects you’d like to share with everyone, we’d love for you to contribute your code! You can check out [how to contribute to RT-Thread’s code](https://www.rt-thread.io/contribution.html). Let’s make something awesome together!

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bsp/renesas/ra8d1-ek/SConscript Normal file
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@@ -0,0 +1,28 @@
# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
CPPPATH = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')

55
bsp/renesas/ra8d1-ek/SConstruct Normal file
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@@ -0,0 +1,55 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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bsp/renesas/ra8d1-ek/board/Kconfig Normal file
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21
bsp/renesas/ra8d1-ek/board/SConscript Normal file
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@@ -0,0 +1,21 @@
import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
CPPPATH = [cwd]
src = Glob('*.c')
if GetDepend(['BSP_USING_FS']):
src += Glob('ports/mnt.c')
CPPDEFINES = ['BSP_CFG_RTOS = 2']
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

38
bsp/renesas/ra8d1-ek/board/board.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-10 Sherman first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RA_SRAM_SIZE 896 /* The SRAM size of the chip needs to be modified */
#define RA_SRAM_END (0x22000000 + RA_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __RAM_segment_used_end__;
#define HEAP_BEGIN (&__RAM_segment_used_end__)
#endif
#define HEAP_END RA_SRAM_END
#ifdef __cplusplus
}
#endif
#endif

16
bsp/renesas/ra8d1-ek/board/lvgl/SConscript Normal file
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from building import *
import os
cwd = GetCurrentDir()
group = []
src = Glob('*.c')
CPPPATH = [cwd]
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
group = group + DefineGroup('LVGL-port', src, depend = ['BSP_USING_LVGL'], CPPPATH = CPPPATH)
Return('group')

17
bsp/renesas/ra8d1-ek/board/lvgl/demo/SConscript Normal file
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@@ -0,0 +1,17 @@
from building import *
import os
cwd = GetCurrentDir()
group = []
src = Glob('*.c')
CPPPATH = [cwd]
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
group = group + DefineGroup('LVGL-demo', src, depend = ['BSP_USING_LVGL', 'BSP_USING_LVGL_DEMO'], CPPPATH = CPPPATH)
Return('group')

18
bsp/renesas/ra8d1-ek/board/lvgl/demo/lv_demo.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-17 Meco Man First version
* 2022-05-10 Meco Man improve rt-thread initialization process
*/
#include "rtconfig.h"
void lv_user_gui_init(void)
{
/* display demo; you may replace with your LVGL application at here */
extern void lv_demo_music(void);
lv_demo_music();
}

66
bsp/renesas/ra8d1-ek/board/lvgl/lv_conf.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-22 Rbb666 First version
*/
#ifndef LV_CONF_H
#define LV_CONF_H
#include <rtconfig.h>
/* Enable additional color format support */
#define DLG_LVGL_CF 1
/* Enable sub byte color formats to be swapped. If disabled, which is recommended for
* performance, bitmaps need to be in correct order */
#define DLG_LVGL_CF_SUB_BYTE_SWAP 0
#define DLG_LVGL_USE_GPU_RA6M3 0
#define LV_USE_PERF_MONITOR 1
#define LV_COLOR_DEPTH 16
#ifdef PKG_USING_ILI9341
#define LV_HOR_RES_MAX 240
#define LV_VER_RES_MAX 320
#define LV_COLOR_16_SWAP 1
#define LV_DPI_DEF 99
#else
#define LV_HOR_RES_MAX 480
#define LV_VER_RES_MAX 272
#define LV_DPI_DEF 89
#endif
#ifdef BSP_USING_LVGL_VIDEO_DEMO
#define LV_USE_FILE_EXPLORER 1
#if LV_USE_FILE_EXPLORER
/*Maximum length of path*/
#define LV_FILE_EXPLORER_PATH_MAX_LEN (128)
/*Quick access bar, 1:use, 0:not use*/
/*Requires: lv_list*/
#define LV_FILE_EXPLORER_QUICK_ACCESS 0
#endif
#define LV_USE_FS_STDIO 1
#if LV_USE_FS_STDIO
#define LV_FS_STDIO_LETTER '/' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/
#define LV_FS_STDIO_PATH "/" /*Set the working directory. File/directory paths will be appended to it.*/
#define LV_FS_STDIO_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/
#endif
#endif
#ifdef PKG_USING_LV_MUSIC_DEMO
/* music player demo */
#define LV_USE_DEMO_RTT_MUSIC 1
#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
#define LV_FONT_MONTSERRAT_12 1
#define LV_FONT_MONTSERRAT_16 1
#define LV_COLOR_SCREEN_TRANSP 0
#endif /* PKG_USING_LV_MUSIC_DEMO */
#endif

146
bsp/renesas/ra8d1-ek/board/lvgl/lv_port_disp.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-24 Rbb666 The first version
*/
#include <lvgl.h>
#include "hal_data.h"
#if DLG_LVGL_USE_GPU_RA6M3
#include "drv_g2d.h"
#endif
#ifdef PKG_USING_ILI9341
#include "lcd_ili9341.h"
#else
#include "lcd_port.h"
#endif
#define COLOR_BUFFER (LV_HOR_RES_MAX * LV_VER_RES_MAX / 4)
/*A static or global variable to store the buffers*/
static lv_disp_draw_buf_t disp_buf;
/*Descriptor of a display driver*/
static lv_disp_drv_t disp_drv;
static struct rt_device_graphic_info info;
/*Static or global buffer(s). The second buffer is optional*/
// 0x1FFE0000 0x20040000
lv_color_t buf_1[COLOR_BUFFER];
#if !DLG_LVGL_USE_GPU_RA6M3
static void color_to16_maybe(lv_color16_t *dst, lv_color_t *src)
{
#if (LV_COLOR_DEPTH == 16)
dst->full = src->full;
#else
dst->ch.blue = src->ch.blue;
dst->ch.green = src->ch.green;
dst->ch.red = src->ch.red;
#endif
}
#endif
void _ra_port_display_callback(display_callback_args_t *p_args)
{
/* TFT-Callback */
}
static void disp_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
{
#ifdef PKG_USING_ILI9341
lcd_fill_array_spi(area->x1, area->y1, area->x2, area->y2, color_p);
#elif DLG_LVGL_USE_GPU_RA6M3
lv_port_gpu_blit(area->x1, area->y1, color_p, area);
#else
int x1, x2, y1, y2;
x1 = area->x1;
x2 = area->x2;
y1 = area->y1;
y2 = area->y2;
/*Return if the area is out the screen*/
if (x2 < 0)
return;
if (y2 < 0)
return;
if (x1 > info.width - 1)
return;
if (y1 > info.height - 1)
return;
/*Truncate the area to the screen*/
int32_t act_x1 = x1 < 0 ? 0 : x1;
int32_t act_y1 = y1 < 0 ? 0 : y1;
int32_t act_x2 = x2 > info.width - 1 ? info.width - 1 : x2;
int32_t act_y2 = y2 > info.height - 1 ? info.height - 1 : y2;
uint32_t x;
uint32_t y;
long int location = 0;
/* color_p is a buffer pointer; the buffer is provided by LVGL */
lv_color16_t *fbp16 = (lv_color16_t *)info.framebuffer;
for (y = act_y1; y <= act_y2; y++)
{
for (x = act_x1; x <= act_x2; x++)
{
location = (x) + (y) * info.width;
color_to16_maybe(&fbp16[location], color_p);
color_p++;
}
color_p += x2 - act_x2;
}
#endif
lv_disp_flush_ready(disp_drv);
}
void lv_port_disp_init(void)
{
#ifdef PKG_USING_ILI9341
spi_lcd_init(20);
#else
static rt_device_t device;
/* LCD Device Init */
device = rt_device_find("lcd");
RT_ASSERT(device != RT_NULL);
if (rt_device_open(device, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
{
rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info);
}
RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
#endif
/*Initialize `disp_buf` with the buffer(s). With only one buffer use NULL instead buf_2 */
lv_disp_draw_buf_init(&disp_buf, buf_1, NULL, COLOR_BUFFER);
lv_disp_drv_init(&disp_drv); /*Basic initialization*/
/*Set the resolution of the display*/
disp_drv.hor_res = LV_HOR_RES_MAX;
disp_drv.ver_res = LV_VER_RES_MAX;
/*Set a display buffer*/
disp_drv.draw_buf = &disp_buf;
/*Used to copy the buffer's content to the display*/
disp_drv.flush_cb = disp_flush;
#if DLG_LVGL_USE_GPU_RA6M3
/* Initialize GPU module */
G2d_Drv_HWInit();
#endif /* LV_PORT_DISP_GPU_EN */
/*Finally register the driver*/
lv_disp_drv_register(&disp_drv);
}

136
bsp/renesas/ra8d1-ek/board/lvgl/lv_port_indev.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-09 Rbb666 The first version
*/
#include <lvgl.h>
#include <rtdevice.h>
#include "gt911.h"
#define DBG_TAG "lv_port_indev"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#include "hal_data.h"
#define GT911_IRQ_PIN BSP_IO_PORT_00_PIN_04
#define GT911_RST_PIN BSP_IO_PORT_08_PIN_01
static rt_device_t touch_dev;
static lv_indev_t *touch_indev;
struct rt_touch_data *read_data;
volatile static rt_uint8_t touch_detect_flag = 0;
static void touchpad_read(lv_indev_drv_t *indev, lv_indev_data_t *data)
{
if (touch_detect_flag != 1)
return;
rt_device_read(touch_dev, 0, read_data, 1);
if (read_data->event == RT_TOUCH_EVENT_NONE)
return;
data->point.x = read_data->x_coordinate;
data->point.y = read_data->y_coordinate;
if (read_data->event == RT_TOUCH_EVENT_DOWN)
data->state = LV_INDEV_STATE_PR;
if (read_data->event == RT_TOUCH_EVENT_MOVE)
data->state = LV_INDEV_STATE_PR;
if (read_data->event == RT_TOUCH_EVENT_UP)
data->state = LV_INDEV_STATE_REL;
touch_detect_flag = 0;
rt_device_control(touch_dev, RT_TOUCH_CTRL_ENABLE_INT, RT_NULL);
}
static rt_err_t rx_callback(rt_device_t dev, rt_size_t size)
{
touch_detect_flag = 1;
rt_device_control(dev, RT_TOUCH_CTRL_DISABLE_INT, RT_NULL);
return 0;
}
rt_err_t gt911_probe(rt_uint16_t x, rt_uint16_t y)
{
void *id;
touch_dev = rt_device_find("gt911");
if (touch_dev == RT_NULL)
{
rt_kprintf("can't find device gt911\n");
return -1;
}
if (rt_device_open(touch_dev, RT_DEVICE_FLAG_INT_RX) != RT_EOK)
{
rt_kprintf("open device failed!");
return -1;
}
id = rt_malloc(sizeof(rt_uint8_t) * 8);
rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_ID, id);
rt_uint8_t *read_id = (rt_uint8_t *)id;
rt_kprintf("id = GT%d%d%d \n", read_id[0] - '0', read_id[1] - '0', read_id[2] - '0');
rt_device_control(touch_dev, RT_TOUCH_CTRL_SET_X_RANGE, &x); /* if possible you can set your x y coordinate*/
rt_device_control(touch_dev, RT_TOUCH_CTRL_SET_Y_RANGE, &y);
rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_INFO, id);
rt_kprintf("range_x = %d \n", (*(struct rt_touch_info *)id).range_x);
rt_kprintf("range_y = %d \n", (*(struct rt_touch_info *)id).range_y);
rt_kprintf("point_num = %d \n", (*(struct rt_touch_info *)id).point_num);
rt_free(id);
rt_device_set_rx_indicate(touch_dev, rx_callback);
read_data = (struct rt_touch_data *)rt_calloc(1, sizeof(struct rt_touch_data));
if (!read_data)
{
return -RT_ENOMEM;
}
return RT_EOK;
}
#define RST_PIN "p801"
#define INT_PIN "p004"
rt_err_t rt_hw_gt911_register(void)
{
struct rt_touch_config cfg;
rt_base_t int_pin = rt_pin_get(INT_PIN);
rt_base_t rst_pin = rt_pin_get(RST_PIN);
cfg.dev_name = "i2c1";
cfg.irq_pin.pin = int_pin;
cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN;
cfg.user_data = &rst_pin;
rt_hw_gt911_init("gt911", &cfg);
gt911_probe(480, 272);
return RT_EOK;
}
void lv_port_indev_init(void)
{
static lv_indev_drv_t indev_drv; /* Descriptor of a input device driver */
lv_indev_drv_init(&indev_drv); /* Basic initialization */
indev_drv.type = LV_INDEV_TYPE_POINTER; /* Touch pad is a pointer-like device */
indev_drv.read_cb = touchpad_read; /* Set your driver function */
/* Register the driver in LVGL and save the created input device object */
touch_indev = lv_indev_drv_register(&indev_drv);
/* Register touch device */
rt_err_t res = rt_hw_gt911_register();
RT_ASSERT(res == RT_EOK);
}

16
bsp/renesas/ra8d1-ek/board/ports/SConscript Normal file
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@@ -0,0 +1,16 @@
import os
from building import *
src = []
objs = []
cwd = GetCurrentDir()
CPPPATH = [cwd]
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

38
bsp/renesas/ra8d1-ek/board/ports/fal_cfg.h Normal file
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@@ -0,0 +1,38 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-07-20 Sherman the first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include "hal_data.h"
extern const struct fal_flash_dev _onchip_flash_hp0;
extern const struct fal_flash_dev _onchip_flash_hp1;
extern const struct fal_flash_dev _onchip_flash_hp3;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&_onchip_flash_hp0, \
&_onchip_flash_hp1, \
&_onchip_flash_hp3, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/** partition table, The chip flash partition is defined in "\ra\fsp\src\bsp\mcu\ra6m4\bsp_feature.h".
* More details can be found in the RA6M4 Group User Manual: Hardware section 47 Flash memory.*/
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "boot", "onchip_flash_hp0", 0, BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_hp1", 0, (BSP_ROM_SIZE_BYTES - BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE), 0}, \
{FAL_PART_MAGIC_WROD, "disk", "onchip_flash_hp3", 0, (BSP_DATA_FLASH_SIZE_BYTES), 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

82
bsp/renesas/ra8d1-ek/board/ports/gpio_cfg.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-01-19 Sherman first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE(pin) \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_04_PIN_00: \
case BSP_IO_PORT_02_PIN_06: \
case BSP_IO_PORT_01_PIN_05: \
return 0; \
case BSP_IO_PORT_02_PIN_05: \
case BSP_IO_PORT_01_PIN_01: \
case BSP_IO_PORT_01_PIN_04: \
return 1; \
case BSP_IO_PORT_02_PIN_03: \
case BSP_IO_PORT_01_PIN_00: \
case BSP_IO_PORT_02_PIN_13: \
return 2; \
case BSP_IO_PORT_02_PIN_02: \
case BSP_IO_PORT_01_PIN_10: \
case BSP_IO_PORT_02_PIN_12: \
return 3; \
case BSP_IO_PORT_04_PIN_02: \
case BSP_IO_PORT_01_PIN_11: \
case BSP_IO_PORT_04_PIN_11: \
return 4; \
case BSP_IO_PORT_04_PIN_01: \
case BSP_IO_PORT_03_PIN_02: \
case BSP_IO_PORT_04_PIN_10: \
return 5; \
case BSP_IO_PORT_03_PIN_01: \
case BSP_IO_PORT_00_PIN_00: \
case BSP_IO_PORT_04_PIN_09: \
return 6; \
case BSP_IO_PORT_00_PIN_01: \
case BSP_IO_PORT_04_PIN_08: \
return 7; \
case BSP_IO_PORT_00_PIN_02: \
case BSP_IO_PORT_03_PIN_05: \
case BSP_IO_PORT_04_PIN_15: \
return 8; \
case BSP_IO_PORT_00_PIN_04: \
case BSP_IO_PORT_03_PIN_04: \
case BSP_IO_PORT_04_PIN_14: \
return 9; \
case BSP_IO_PORT_00_PIN_05: \
case BSP_IO_PORT_07_PIN_09: \
return 10; \
case BSP_IO_PORT_05_PIN_01: \
case BSP_IO_PORT_00_PIN_06: \
case BSP_IO_PORT_07_PIN_08: \
return 11; \
case BSP_IO_PORT_05_PIN_02: \
case BSP_IO_PORT_00_PIN_08: \
return 12; \
case BSP_IO_PORT_00_PIN_15: \
case BSP_IO_PORT_00_PIN_09: \
return 13; \
case BSP_IO_PORT_04_PIN_03: \
case BSP_IO_PORT_05_PIN_12: \
case BSP_IO_PORT_05_PIN_05: \
return 14; \
case BSP_IO_PORT_04_PIN_04: \
case BSP_IO_PORT_05_PIN_11: \
case BSP_IO_PORT_05_PIN_06: \
return 15; \
default : \
return -1; \
} \
}

36
bsp/renesas/ra8d1-ek/board/ports/lcd_port.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-07-28 liu2guang the first version for STM32F469NI-Discovery.
*/
#ifndef __DRV_LCD_H_
#define __DRV_LCD_H_
#include <rtthread.h>
#include <rtdevice.h>
typedef enum
{
ROTATION_ZERO = 0,
ROTATION_090 = 90,
ROTATION_180 = 180,
ROTATION_270 = 270,
} bsp_rotation;
#define LCD_WIDTH DISPLAY_HSIZE_INPUT0
#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0
#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
#define LCD_XSTRIDE_PHYS (((DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0 * LCD_BITS_PER_PIXEL + 0x1FF) & 0xFFFFFE00) / LCD_BITS_PER_PIXEL)
#define LCD_NUM_FRAMEBUFFERS (2)
#define LCD_BL_PIN BSP_IO_PORT_04_PIN_04
#endif

13
bsp/renesas/ra8d1-ek/board/ports/mipi_lcd/SConscript Normal file
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@@ -0,0 +1,13 @@
import os
from building import *
src = []
objs = []
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Glob('*.c')
objs = DefineGroup('Drivers', src, depend = ['BSP_USING_MIPI_LCD'], CPPPATH = CPPPATH)
Return('objs')

226
bsp/renesas/ra8d1-ek/board/ports/mipi_lcd/mipi_config.c Normal file
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@@ -0,0 +1,226 @@
#include <rtthread.h>
#if (defined(BSP_USING_LCD)) || (defined(SOC_SERIES_R7FA8M85))
#include <lcd_port.h>
#include "hal_data.h"
#define DRV_DEBUG
#define LOG_TAG "mipi_cfg"
#include <drv_log.h>
#define MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG ((mipi_dsi_cmd_id_t) 0xFE)
#define MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE ((mipi_dsi_cmd_id_t) 0xFD)
typedef struct
{
unsigned char size;
unsigned char buffer[10];
mipi_dsi_cmd_id_t cmd_id;
mipi_dsi_cmd_flag_t flags;
} lcd_table_setting_t;
volatile static bool g_message_sent;
volatile static mipi_dsi_phy_status_t g_phy_status;
const lcd_table_setting_t g_lcd_init_focuslcd[] =
{
{6, {0xFF, 0xFF, 0x98, 0x06, 0x04, 0x01}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x08, 0x10}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x21, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x30, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x31, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x40, 0x14}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x41, 0x33}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x42, 0x02}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x43, 0x09}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x44, 0x06}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x50, 0x70}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x51, 0x70}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x52, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x53, 0x48}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x60, 0x07}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x61, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x62, 0x08}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x63, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa0, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa1, 0x03}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa2, 0x09}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa3, 0x0d}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa4, 0x06}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa5, 0x16}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa6, 0x09}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa7, 0x08}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa8, 0x03}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xa9, 0x07}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xaa, 0x06}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xab, 0x05}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xac, 0x0d}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xad, 0x2c}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xae, 0x26}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xaf, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc0, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc1, 0x04}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc2, 0x0b}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc3, 0x0f}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc4, 0x09}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc5, 0x18}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc6, 0x07}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc7, 0x08}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc8, 0x05}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xc9, 0x09}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xca, 0x07}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xcb, 0x05}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xcc, 0x0c}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xcd, 0x2d}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xce, 0x28}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xcf, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0xFF, 0x98, 0x06, 0x04, 0x06}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x00, 0x21}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x01, 0x09}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x02, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x03, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x04, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x05, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x06, 0x80}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x07, 0x05}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x08, 0x02}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x09, 0x80}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x0a, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x0b, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x0c, 0x0a}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x0d, 0x0a}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x0e, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x0f, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x10, 0xe0}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x11, 0xe4}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x12, 0x04}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x13, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x14, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x15, 0xc0}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x16, 0x08}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x17, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x18, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x19, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x1a, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x1b, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x1c, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x1d, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x20, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x21, 0x23}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x22, 0x45}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x23, 0x67}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x24, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x25, 0x23}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x26, 0x45}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x27, 0x67}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x30, 0x01}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x31, 0x11}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x32, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x33, 0xee}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x34, 0xff}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x35, 0xcb}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x36, 0xda}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x37, 0xad}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x38, 0xbc}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x39, 0x76}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3a, 0x67}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3b, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3c, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3d, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3e, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3f, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x40, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x53, 0x10}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x54, 0x10}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0xFF, 0x98, 0x06, 0x04, 0x07}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x18, 0x1d}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x26, 0xb2}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x02, 0x77}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xe1, 0x79}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x17, 0x22}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0xFF, 0x98, 0x06, 0x04, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{120, {0}, MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG, (mipi_dsi_cmd_flag_t)0},
{2, {0x11, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{5, {0}, MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG, (mipi_dsi_cmd_flag_t)0},
{2, {0x29, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3a, 0x70}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{0x00, {0}, MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE, (mipi_dsi_cmd_flag_t)0},
};
void mipi_dsi0_callback(mipi_dsi_callback_args_t *p_args)
{
switch (p_args->event)
{
case MIPI_DSI_EVENT_SEQUENCE_0:
{
if (MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED == p_args->tx_status)
{
g_message_sent = true;
}
break;
}
case MIPI_DSI_EVENT_PHY:
{
g_phy_status |= p_args->phy_status;
break;
}
default:
{
break;
}
}
}
static void mipi_dsi_push_table(const lcd_table_setting_t *table)
{
fsp_err_t err = FSP_SUCCESS;
const lcd_table_setting_t *p_entry = table;
while (MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE != p_entry->cmd_id)
{
mipi_dsi_cmd_t msg =
{
.channel = 0,
.cmd_id = p_entry->cmd_id,
.flags = p_entry->flags,
.tx_len = p_entry->size,
.p_tx_buffer = p_entry->buffer,
};
if (MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG == msg.cmd_id)
{
R_BSP_SoftwareDelay (table->size, BSP_DELAY_UNITS_MILLISECONDS);
}
else
{
g_message_sent = false;
/* Send a command to the peripheral device */
err = R_MIPI_DSI_Command(&g_mipi_dsi0_ctrl, &msg);
if (err != FSP_SUCCESS)
{
LOG_E("R_MIPI_DSI_Command error\n");
}
/* Wait */
while (!g_message_sent);
}
p_entry++;
}
}
void ra8_mipi_lcd_init(void)
{
mipi_dsi_push_table(g_lcd_init_focuslcd);
}
#endif

165
bsp/renesas/ra8d1-ek/board/ports/mnt.c Normal file
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@@ -0,0 +1,165 @@
#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_FS
#include <dfs_fs.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef BSP_USING_ONCHIP_FS
#include "fal.h"
#define FS_PARTITION_NAME "disk"
static void sd_mount(void)
{
struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME);
if (flash_dev == NULL)
{
rt_kprintf("Can't create a block device on '%s' partition.\n", FS_PARTITION_NAME);
}
else
{
rt_kprintf("Create a block device on the %s partition of flash successful.\n", FS_PARTITION_NAME);
}
if(rt_device_find(FS_PARTITION_NAME) != RT_NULL)
{
dfs_mkfs("elm", FS_PARTITION_NAME);
if (dfs_mount(FS_PARTITION_NAME, "/", "elm", 0, 0) == RT_EOK)
{
rt_kprintf("onchip elm filesystem mount to '/'\n");
}
else
{
rt_kprintf("onchip elm filesystem mount to '/' failed!\n");
}
}
else
{
rt_kprintf("find filesystem portion failed\r\n");
}
}
#elif defined(BSP_USING_SDCARD_FS)
#include <drv_sdhi.h>
/* SD Card hot plug detection pin */
#define SD_CHECK_PIN "p405"
static rt_base_t sd_check_pin = 0;
static void _sdcard_mount(void)
{
rt_device_t device;
device = rt_device_find("sd");
rt_kprintf("rt_device_find %x \r\n", device);
if (device == NULL)
{
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
device = rt_device_find("sd");
}
if (device != RT_NULL)
{
if (dfs_mount("sd", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
static void _sdcard_unmount(void)
{
rt_thread_mdelay(200);
dfs_unmount("/sdcard");
LOG_I("Unmount \"/sdcard\"");
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
}
static void sd_auto_mount(void *parameter)
{
rt_uint8_t re_sd_check_pin = 1;
rt_thread_mdelay(20);
if (!rt_pin_read(sd_check_pin))
{
_sdcard_mount();
}
while (1)
{
rt_thread_mdelay(200);
if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) == 0)
{
_sdcard_mount();
}
if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) != 0)
{
_sdcard_unmount();
}
}
}
static void sd_mount(void)
{
rt_thread_t tid;
sd_check_pin = rt_pin_get(SD_CHECK_PIN);
rt_pin_mode(sd_check_pin, PIN_MODE_INPUT_PULLUP);
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
return;
}
}
#else
#include <spi_msd.h>
#include "drv_sci_spi.h"
int sd_mount(void)
{
uint32_t cs_pin = BSP_IO_PORT_10_PIN_05;
rt_hw_sci_spi_device_attach("scpi2", "scpi20", cs_pin);
msd_init("sd0", "scpi20");
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
return 0;
}
#endif /* BSP_USING_SDCARD_FS */
int mount_init(void)
{
sd_mount();
return RT_EOK;
}
// INIT_ENV_EXPORT(mount_init);
#endif

49
bsp/renesas/ra8d1-ek/board/ports/omv_fs/ff.h Normal file
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#ifndef __OMV_FF_H__
#define __OMV_FF_H__
#include "dfs_file.h"
typedef struct dfs_file FIL;
typedef char TCHAR;
typedef unsigned int UINT;
typedef unsigned char BYTE;
typedef int FF_DIR;
typedef struct stat FILINFO;
typedef enum {
FR_OK = 0, /* (0) Succeeded */
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
FR_INT_ERR, /* (2) Assertion failed */
FR_NOT_READY, /* (3) The physical drive cannot work */
FR_NO_FILE, /* (4) Could not find the file */
FR_NO_PATH, /* (5) Could not find the path */
FR_INVALID_NAME, /* (6) The path name format is invalid */
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
FR_EXIST, /* (8) Access denied due to prohibited access */
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
FR_NOT_ENABLED, /* (12) The volume has no work area */
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_LOCK */
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
} FRESULT;
/* File access mode and open method flags (3rd argument of f_open) */
#define FA_READ 0x01
#define FA_WRITE 0x02
#define FA_OPEN_EXISTING 0x00
#define FA_CREATE_NEW 0x04
#define FA_CREATE_ALWAYS 0x08
#define FA_OPEN_ALWAYS 0x10
#define FA_OPEN_APPEND 0x30
#define f_eof(fp) ((int)((fp)->pos == (fp)->vnode->size))
#define f_tell(fp) ((fp)->pos)
#define f_size(fp) ((fp)->vnode->size)
#endif

20
bsp/renesas/ra8d1-ek/board/ra8_it.c Normal file
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#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_SCI_SPI
rt_weak void sci_spi3_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi4_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi6_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi7_callback(spi_callback_args_t *p_args)
{
}
#endif

164
bsp/renesas/ra8d1-ek/buildinfo.gpdsc Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.c"/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/board/ra8d1_ek/board.h" path=""/>
<file category="header" name="ra/board/ra8d1_ek/board_ethernet_phy.h" path=""/>
<file category="source" name="ra/board/ra8d1_ek/board_init.c"/>
<file category="header" name="ra/board/ra8d1_ek/board_init.h" path=""/>
<file category="source" name="ra/board/ra8d1_ek/board_leds.c"/>
<file category="header" name="ra/board/ra8d1_ek/board_leds.h" path=""/>
<file category="source" name="ra/board/ra8d1_ek/board_sdram.c"/>
<file category="header" name="ra/board/ra8d1_ek/board_sdram.h" path=""/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_b_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h" path=""/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
<file category="source" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c"/>
<file category="other" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.o"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="other" name="ra_gen/SConscript"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>

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bsp/renesas/ra8d1-ek/memory_regions.scat Normal file
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/* generated memory regions file - do not edit */
#define RAM_START 0x22000000
#define RAM_LENGTH 0xE0000
#define FLASH_START 0x02000000
#define FLASH_LENGTH 0x1F8000
#define DATA_FLASH_START 0x27000000
#define DATA_FLASH_LENGTH 0x3000
#define OPTION_SETTING_START 0x0300A100
#define OPTION_SETTING_LENGTH 0x100
#define OPTION_SETTING_S_START 0x0300A200
#define OPTION_SETTING_S_LENGTH 0x100
#define OPTION_SETTING_DATA_FLASH_S_START 0x27030080
#define OPTION_SETTING_DATA_FLASH_S_LENGTH 0x800
#define ID_CODE_START 0x00000000
#define ID_CODE_LENGTH 0x0
#define SDRAM_START 0x68000000
#define SDRAM_LENGTH 0x8000000
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x0
#define OSPI_DEVICE_0_START 0x80000000
#define OSPI_DEVICE_0_LENGTH 0x10000000
#define OSPI_DEVICE_1_START 0x90000000
#define OSPI_DEVICE_1_LENGTH 0x10000000
#define ITCM_START 0x00000000
#define ITCM_LENGTH 0x10000
#define DTCM_START 0x20000000
#define DTCM_LENGTH 0x10000
#define NS_OFFSET_START 0x10000000
#define NS_OFFSET_LENGTH 0x0

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bsp/renesas/ra8d1-ek/ra/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
src += Glob(cwd + '/fsp/src/r_*/*.c')
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

411
bsp/renesas/ra8d1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h Normal file
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/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.1
* @date 19. April 2021
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */

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