[bsp][gd32]添加 立创开发板 GD32F470 的 SDRAM驱动，从STM32的drv_sdram.c修改而来

bsp/gd32/arm/gd32470z-lckfb/board/Kconfig

@@ -230,6 +230,11 @@ menu "On-chip Peripheral Drivers"
                 endif
         endif
 
+    config BSP_USING_SDRAM
+        bool "Enable SDRAM"
+        select RT_USING_SDRAM
+        default n
+
     source "../libraries/gd32_drivers/Kconfig"
 
 endmenu

bsp/gd32/arm/gd32470z-lckfb/board/board.c

@@ -75,9 +75,7 @@ void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-#ifdef BSP_USING_SDRAM
-    rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
-#else
+#ifdef RT_USING_HEAP
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 }

bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/SConscript

@@ -48,6 +48,10 @@ if GetDepend(['RT_USING_SDIO']):
     src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c']
     src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c']
 
+if GetDepend(['BSP_USING_SDRAM']):
+    src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c']
+    src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c']
+
 path = [
     cwd + '/CMSIS/GD/GD32F4xx/Include',
     cwd + '/CMSIS',

bsp/gd32/arm/libraries/gd32_drivers/SConscript

@@ -53,6 +53,10 @@ if GetDepend('RT_USING_SDIO'):
 if GetDepend('RT_USING_PWM'):
     src += ['drv_pwm.c']
 
+# add sdram drivers.
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
 path = [cwd]
 
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)

bsp/gd32/arm/libraries/gd32_drivers/sdram_port.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-04     zylx         The first version for STM32F4xx
+ * 2023-08-20     yuanzihao    adapter gd32f4xx
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+#define SDRAM_DEVICE    EXMC_SDRAM_DEVICE0
+/* Bank1 or Bank2 */
+#define SDRAM_TARGET_BANK               1
+/* stm32h7 Bank1:0XC0000000  Bank2:0XD0000000 */
+#define SDRAM_BANK_ADDR                 ((uint32_t)0XC0000000)
+/* data width: 8, 16, 32 */
+#define SDRAM_DATA_WIDTH_IN_NUMBER      16
+#define SDRAM_DATA_WIDTH                EXMC_SDRAM_DATABUS_WIDTH_16B
+/* column bit numbers: 8, 9, 10, 11 */
+#define SDRAM_COLUMN_BITS               EXMC_SDRAM_COW_ADDRESS_9
+/* row bit numbers: 11, 12, 13 */
+#define SDRAM_ROW_BITS                  EXMC_SDRAM_ROW_ADDRESS_13
+/* cas latency clock number: 1, 2, 3 */
+#define SDRAM_CAS_LATENCY               EXMC_CAS_LATENCY_3_SDCLK
+/* read pipe delay: 0, 1, 2 */
+#define SDRAM_RPIPE_DELAY               EXMC_PIPELINE_DELAY_2_HCLK
+/* clock divid: 2, 3 */
+#define SDCLOCK_PERIOD                  EXMC_SDCLK_PERIODS_3_HCLK
+/* refresh rate counter */
+#define SDRAM_REFRESH_COUNT             ((uint32_t)0x02A5)
+#define SDRAM_SIZE                      ((uint32_t)0x2000000)
+#define SDRAM_TIMEOUT                   ((uint32_t)0x0000FFFF)
+
+/* Timing configuration for W9825G6KH-6 */
+/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
+/* TMRD: 2 Clock cycles */
+#define LOADTOACTIVEDELAY               2
+/* TXSR: 8x10ns */
+#define EXITSELFREFRESHDELAY            8
+/* TRAS: 5x10ns */
+#define SELFREFRESHTIME                 7
+/* TRC:  7x10ns */
+#define ROWCYCLEDELAY                   5
+/* TWR:  2 Clock cycles */
+#define WRITERECOVERYTIME               2
+/* TRP:  2x10ns */
+#define RPDELAY                         3
+/* TRCD: 2x10ns */
+#define RCDDELAY                        3
+
+/* memory mode register */
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+#endif