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add bf533 bsp and cpu files.

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2138 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
mok.jingxian@gmail.com
2012-05-30 11:29:34 +00:00
parent 3ad6f43ff3
commit 5684d15916
19 changed files with 3686 additions and 0 deletions
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bsp/bf533/application.c
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian first version
*/
#include "application.h"
#include "board.h"
#include "rtthread.h"
void app_init_entry(void *parg)
{
parg = parg;
rt_hw_core_timer_init();//start system tick in first thread.
rt_hw_isr_install();
}
void rt_application_init(void)
{
rt_thread_t led_thread;
#ifdef RT_USING_HEAP
led_thread = rt_thread_create("init", app_init_entry, RT_NULL, 512, 200, 20);
#endif
if (led_thread != RT_NULL)
{
rt_thread_startup(led_thread);
}
}
bsp/bf533/application.h
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian first version
*/
#ifndef __APPLICATION_H__
#define __APPLICATION_H__
#ifdef __cplusplus
extern "C" {
#endif
void rt_application_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __APPLICATION_H__ */
bsp/bf533/board.c
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bsp/bf533/board.h
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian first version
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#define CLKIN 33333000LL
#define SPEED_MULTIPLE 16
#define BUS_DIVISOR 4
#define CCLKSPEED (CLKIN * SPEED_MULTIPLE)
#define SCLKSPEED (CLKIN * BUS_DIVISOR)
#define CLOCKS_PER_SECD CCLKSPEED
#define SCLOCKS_PER_SEC SCLKSPEED
//SIC_IMASK¼Ä´æÆ÷
#define PLL_WAKEUP_INT_MASK 0x00000001
#define DMA_ERROR_INT_MASK 0x00000002
#define PPI_ERROR_INT_MASK 0x00000004
#define SPORT0_ERROR_INT_MASK 0x00000008
#define SPORT1_ERROR_INT_MASK 0x00000010
#define SPI_ERROR_INT_MASK 0x00000020
#define UART_ERROR_INT_MASK 0x00000040
#define RTC_INT_MASK 0x00000080
#define DMA0_PPI_INT_MASK 0x00000100
#define DMA1_SPORT0_RX_INT_MASK 0x00000200
#define DMA2_SPORT0_TX_INT_MASK 0x00000400
#define DMA3_SPORT1_RX_INT_MASK 0x00000800
#define DMA4_SPORT1_TX_INT_MASK 0x00001000
#define DMA5_SPI_INT_MASK 0x00002000
#define DMA6_UART_RX_INT_MASK 0x00004000
#define DMA7_UART_TX_INT_MASK 0x00008000
#define TIMER0_INT_MASK 0x00010000
#define TIMER1_INT_MASK 0x00020000
#define TIMER2_INT_MASK 0x00040000
#define PF_INTA_MASK 0x00080000
#define PF_INTB_MASK 0x00100000
#define MEM_DMA_STREAM0_MASK 0x00200000
#define MEM_DMA_STREAM1_MASK 0x00400000
#define SOFT_WATCHDOG_TMER_MASK 0x00800000
//SIC_IAR0
#define IAR0_PLL_WAKEUP_INT_IVG 0x00
#define IAR0_DMA_ERROR_INT_IVG 0x01
#define IAR0_PPI_ERROR_INT_IVG 0x02
#define IAR0_SPORT0_ERROR_INT_IVG 0x03
#define IAR0_SPORT1_ERROR_INT_IVG 0x04
#define IAR0_SPI_ERROR_INT_IVG 0x05
#define IAR0_UART_ERROR_INT_IVG 0x06
#define IAR0_RTC_INT_IVG 0x07
//SIC_IAR1
#define IAR1_DMA0_PPI_INT_IVG 0x00
#define IAR1_DMA1_SPORT0RX_IVG 0x01
#define IAR1_DMA2_SPORT0TX_IVG 0x02
#define IAR1_DMA3_SPORT1RX_IVG 0x03
#define IAR1_DMA4_SPORT1TX_IVG 0x04
#define IAR1_DMA5_SPI_INT_IVG 0x05
#define IAR1_DMA6_UARTRX_IVG 0x06
#define IAR1_DMA7_UARTTX_IVG 0x07
//SIC_IAR2
#define IAR2_TIMER0_INT_IVG 0x00
#define IAR2_TIMER1_INT_IVG 0x01
#define IAR2_TIMER2_INT_IVG 0x02
#define IAR2_PF_A_INT_IVG 0x03
#define IAR2_PF_B_INT_IVG 0x04
#define IAR2_MEM_DMA_STREAM0_INT_IVG 0x05
#define IAR2_MEM_DMA_STREAM1_INT_IVG 0x06
#define IAR2_SWATCHDOG_TIMER_INT_IVG 0x07
#ifdef __cplusplus
extern "C" {
#endif
void rt_hw_core_timer_init(void);
void rt_hw_board_init(void);
void rt_hw_isr_install(void);
#ifdef __cplusplus
}
#endif
#endif /* _BSP_H_ */
bsp/bf533/rtconfig.h
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bsp/bf533/startup.c
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/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "application.h"
#include "board.h"
#include "serial.h"
#include "finsh.h"
extern "asm" int rtt_heap_start;
extern "asm" int rtt_heap_end;
extern struct serial_device uart0;
extern struct rt_device uart0_device;
void rtthread_startup(void)
{
/* init hardware interrupt */
rt_hw_interrupt_init();
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&rtt_heap_start, (void*)&rtt_heap_end);
#endif
#ifdef RT_USING_MODULE
/* init module system*/
rt_system_module_init();
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* register uart0 */
rt_hw_serial_register(&uart0_device, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
/* init all device */
rt_device_init_all();
rt_console_set_device("uart0");
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
extern void finsh_system_init(void);
finsh_system_init();
finsh_set_device("uart0");
#endif
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
bsp/bf533/vdsp/bf533.dpj
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bsp/bf533/vdsp/bf533.mak
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bsp/bf533/vdsp/bf533.pcf
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bsp/bf533/vdsp/bf533_basiccrt.s
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bsp/bf533/vdsp/bf533_heaptab.c
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/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 6 */
/* LDF Printer version: 5.6.0.4 */
/* ldfgen.exe version: 5.6.0.4 */
/* VDSG version: 5.6.0.4 */
/*
** User heap source file generated on Feb 23, 2012 at 09:38:46.
**
** Copyright (C) 2000-2008 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
** crt_doj: bf533_basiccrt.doj
** processor: ADSP-BF533
** product_name: VisualDSP++ 5.0 Update 6
** si_revision: 0.5
** default_silicon_revision_from_archdef: 0.5
** cplb_init_cplb_ctrl: 81
** using_cplusplus: true
** mem_init: false
** use_vdk: false
** use_eh: true
** use_argv: false
** running_from_internal_memory: true
** user_heap_src_file: E:\eclipse\tq2440radio\bsp\bf533\vdsp\bf533_heaptab.c
** libraries_use_stdlib: true
** libraries_use_fileio_libs: false
** libraries_use_ieeefp_emulation_libs: false
** libraries_use_eh_enabled_libs: false
** system_heap: L1
** system_heap_min_size: 1k
** system_stack: L1
** system_stack_min_size: 1k
** use_sdram: false
**
*/
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_1_1)
#pragma diag(suppress:misra_rule_2_2)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_8_10)
#pragma diag(suppress:misra_rule_10_1_a)
#pragma diag(suppress:misra_rule_11_3)
#pragma diag(suppress:misra_rule_12_7)
#endif /* _MISRA_RULES */
extern "asm" int ldf_heap_space;
extern "asm" int ldf_heap_length;
struct heap_table_t
{
void *base;
unsigned long length;
long int userid;
};
#pragma file_attr("libData=HeapTable")
#pragma section("constdata")
struct heap_table_t heap_table[2] =
{
{ &ldf_heap_space, (int) &ldf_heap_length, 0 },
{ 0, 0, 0 }
};
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
bsp/bf533/vdsp/bf533_init.dxe
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bsp/bf533/vdsp/bf533_ram.ldf
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bsp/bf533/vdsp/bf533_sdram_64M.ldf
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bsp/bf533/vdsp/mine.dxe
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libcpu/blackfin/bf53x/context_vdsp.S
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/*
* File : context_vdsp.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian First version
*/
.global _rt_hw_interrupt_disable;
.global _rt_hw_interrupt_enable;
.global _interrupt_thread_switch;
.extern _rt_interrupt_from_thread;
.extern _rt_interrupt_to_thread;
.extern _rt_thread_switch_interrupt_flag;
.section/DOUBLE64 program;
/*
* rt_base_t rt_hw_interrupt_disable();
* return value in R0.
*/
_rt_hw_interrupt_disable:
CLI R0;
_rt_hw_interrupt_disable.end:
NOP;
NOP;
NOP;
RTS;
/*
* void rt_hw_interrupt_enable(rt_base_t level);
* R0->level
*/
_rt_hw_interrupt_enable:
STI R0;
_rt_hw_interrupt_enable.end:
NOP;
NOP;
NOP;
RTS;
_interrupt_thread_switch:
/* Save context, interrupts disabled by IPEND[4] bit */
[ -- SP ] = R0;
[ -- SP ] = P1;
[ -- SP ] = RETS;
[ -- SP ] = R1;
[ -- SP ] = R2;
[ -- SP ] = P0;
[ -- SP ] = P2;
[ -- SP ] = ASTAT;
R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */
/* IPEND[4] will stay set when RETI is saved through R1 */
[ -- SP ] = R1;
[ -- SP ] = (R7:3, P5:3);
[ -- SP ] = FP;
[ -- SP ] = I0;
[ -- SP ] = I1;
[ -- SP ] = I2;
[ -- SP ] = I3;
[ -- SP ] = B0;
[ -- SP ] = B1;
[ -- SP ] = B2;
[ -- SP ] = B3;
[ -- SP ] = L0;
[ -- SP ] = L1;
[ -- SP ] = L2;
[ -- SP ] = L3;
[ -- SP ] = M0;
[ -- SP ] = M1;
[ -- SP ] = M2;
[ -- SP ] = M3;
R1.L = A0.x;
[ -- SP ] = R1;
R1 = A0.w;
[ -- SP ] = R1;
R1.L = A1.x;
[ -- SP ] = R1;
R1 = A1.w;
[ -- SP ] = R1;
[ -- SP ] = LC0;
R3 = 0;
LC0 = R3;
[ -- SP ] = LC1;
R3 = 0;
LC1 = R3;
[ -- SP ] = LT0;
[ -- SP ] = LT1;
[ -- SP ] = LB0;
[ -- SP ] = LB1;
/* Context save done so save SP in the TCB */
P1.h = _rt_interrupt_from_thread;
P1.l = _rt_interrupt_from_thread;
P2 = [ P1 ];
[ P2 ] = SP;
/* clear rt_thread_switch_interrupt_flag to 0 */
P1.h = _rt_thread_switch_interrupt_flag;
P1.l = _rt_thread_switch_interrupt_flag;
R0 = 0;
[ P1 ] = R0;
/* Get a pointer to the high ready task's TCB */
P1.h = _rt_interrupt_to_thread;
P1.l = _rt_interrupt_to_thread;
P2 = [ P1 ];
SP = [ P2 ];
/* Restoring CPU context and return to task */
LB1 = [ SP ++ ];
LB0 = [ SP ++ ];
LT1 = [ SP ++ ];
LT0 = [ SP ++ ];
LC1 = [ SP ++ ];
LC0 = [ SP ++ ];
R0 = [ SP ++ ];
A1 = R0;
R0 = [ SP ++ ];
A1.x = R0.L;
R0 = [ SP ++ ];
A0 = R0;
R0 = [ SP ++ ];
A0.x = R0.L;
M3 = [ SP ++ ];
M2 = [ SP ++ ];
M1 = [ SP ++ ];
M0 = [ SP ++ ];
L3 = [ SP ++ ];
L2 = [ SP ++ ];
L1 = [ SP ++ ];
L0 = [ SP ++ ];
B3 = [ SP ++ ];
B2 = [ SP ++ ];
B1 = [ SP ++ ];
B0 = [ SP ++ ];
I3 = [ SP ++ ];
I2 = [ SP ++ ];
I1 = [ SP ++ ];
I0 = [ SP ++ ];
FP = [ SP ++ ];
(R7:3, P5:3) = [ SP ++ ];
RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */
ASTAT = [ SP ++ ];
P2 = [ SP ++ ];
P0 = [ SP ++ ];
R2 = [ SP ++ ];
R1 = [ SP ++ ];
RETS = [ SP ++ ];
P1 = [ SP ++ ];
R0 = [ SP ++ ];
_interrupt_thread_switch.end:
RTI;
libcpu/blackfin/bf53x/cpuport.c
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/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian first version
*/
#include <rtthread.h>
/* flag in interrupt handling */
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
/**
* initializes stack of thread
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
unsigned char i;
unsigned long *stk;
stk = (unsigned long *)stack_addr; /* Load stack pointer */
/* Simulate a function call to the task with an argument */
stk -= 3; /* 3 words assigned for incoming args (R0, R1, R2) */
/* Now simulating vectoring to an ISR */
*--stk = (unsigned long)parameter; /* R0 value - caller's incoming argument #1 */
*--stk = (unsigned long)0; /* P1 value - value irrelevant */
*--stk = (unsigned long)texit; /* RETS value - NO task should return with RTS. */
/* however OS_CPU_Invalid_Task_Return is a safety */
/* catch-allfor tasks that return with an RTS */
*--stk = (unsigned long)parameter; /* R1 value - caller's incoming argument #2 */
/* (not relevant in current test example) */
*--stk = (unsigned long)parameter; /* R2 value - caller's incoming argument #3 */
/* (not relevant in current test example) */
*--stk = (unsigned long)0; /* P0 value - value irrelevant */
*--stk = (unsigned long)0; /* P2 value - value irrelevant */
*--stk = (unsigned long)0; /* ASTAT value - caller's ASTAT value - value */
/* irrelevant */
*--stk = (unsigned long)tentry; /* RETI value- pushing the start address of the task */
for (i = 0; i < 35; i++) /* remaining reg values - R7:3, P5:3, */
{ /* 4 words of A1:0(.W,.X), LT0, LT1, */
*--stk = (unsigned long)0; /* LC0, LC1, LB0, LB1,I3:0, M3:0, L3:0, B3:0, */
} /* All values irrelevant */
return (rt_uint8_t *)stk; /* Return top-of-stack */
}
void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
{
if (rt_thread_switch_interrupt_flag != 1)
{
rt_thread_switch_interrupt_flag = 1;
rt_interrupt_from_thread = from;
}
rt_interrupt_to_thread = to;
asm("raise 14;"); // Raise Interrupt 14 (trap)
}
void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
{
if (rt_thread_switch_interrupt_flag != 1)
{
rt_thread_switch_interrupt_flag = 1;
rt_interrupt_from_thread = from;
}
rt_interrupt_to_thread = to;
asm("raise 14;"); // Raise Interrupt 14 (trap)
}
void rt_hw_context_switch_to(rt_uint32_t to)
{
rt_thread_switch_interrupt_flag = 1;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = to;
asm("raise 14;"); // Raise Interrupt 14 (trap)
}
libcpu/blackfin/bf53x/serial.c
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libcpu/blackfin/bf53x/serial.h
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#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
#define USTAT_RCV_READY 0x01 /* receive data ready */
#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct serial_int_tx
{
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
rt_uint32_t write_index, save_index;
};
typedef struct uartport
{
volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register
volatile rt_uint16_t reserved0;
volatile rt_uint16_t reserved1;
volatile rt_uint16_t reserved2;
volatile rt_uint16_t reserved3;
volatile rt_uint16_t reserved4;
volatile rt_uint16_t reserved5;
volatile rt_uint16_t reserved6;
volatile rt_uint16_t reserved7;
volatile rt_uint16_t reserved8;
volatile rt_uint16_t lsr; //line status register
}uartport;
struct serial_device
{
uartport* uart_device;
/* rx structure */
struct serial_int_rx* int_rx;
/* tx structure */
struct serial_int_tx* int_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
#endif