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first commit, keil test pass

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linyuanbo_breo_server
2021-07-20 09:00:20 +00:00
parent 73bd7a7d66
commit 516d2a3640
114 changed files with 72890 additions and 0 deletions
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539
bsp/n32g452xx/.config Executable file
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bsp/n32g452xx/Kconfig Executable file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_N32G452XX
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config RT_USING_UART1
bool "Using UART1"
select RT_USING_SERIAL
default y
config RT_USING_UART2
bool "Using UART2"
select RT_USING_SERIAL
default n
config RT_USING_UART3
bool "Using UART3"
select RT_USING_SERIAL
default n
config RT_USING_UART4
bool "Using UART4"
select RT_USING_SERIAL
default n

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bsp/n32g452xx/Libraries/CMSIS/core/arm_common_tables.h Executable file
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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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bsp/n32g452xx/Libraries/CMSIS/core/arm_math.h Executable file
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bsp/n32g452xx/Libraries/CMSIS/core/cmsis_armcc.h Executable file
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bsp/n32g452xx/Libraries/CMSIS/core/cmsis_armclang.h Executable file
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bsp/n32g452xx/Libraries/CMSIS/core/cmsis_compiler.h Executable file
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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bsp/n32g452xx/Libraries/CMSIS/device/n32g45x.h Executable file
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bsp/n32g452xx/Libraries/CMSIS/device/n32g45x_conf.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_conf.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_CONF_H__
#define __N32G45X_CONF_H__
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
#include "n32g45x_adc.h"
#include "n32g45x_bkp.h"
#include "n32g45x_can.h"
#include "n32g45x_comp.h"
#include "n32g45x_crc.h"
#include "n32g45x_dac.h"
#include "n32g45x_dbg.h"
#include "n32g45x_dma.h"
#include "n32g45x_dvp.h"
#include "n32g45x_eth.h"
#include "n32g45x_exti.h"
#include "n32g45x_flash.h"
#include "n32g45x_gpio.h"
#include "n32g45x_i2c.h"
#include "n32g45x_iwdg.h"
#include "n32g45x_opamp.h"
#include "n32g45x_pwr.h"
#include "n32g45x_qspi.h"
#include "n32g45x_rcc.h"
#include "n32g45x_rtc.h"
#include "n32g45x_sdio.h"
#include "n32g45x_spi.h"
#include "n32g45x_tim.h"
#include "n32g45x_usart.h"
#include "n32g45x_wwdg.h"
#include "n32g45x_xfmc.h"
#include "n32g45x_tsc.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function which reports
* the name of the source file and the source line number of the call
* that failed. If expr is true, it returns no value.
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((const uint8_t*)#expr, (const uint8_t*)__FILE__, __LINE__))
void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* __N32G45X_CONF_H__ */

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bsp/n32g452xx/Libraries/CMSIS/device/startup/startup_n32g45x.s Executable file
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; ****************************************************************************
; Copyright (c) 2019, Nations Technologies Inc.
;
; All rights reserved.
; ****************************************************************************
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; - Redistributions of source code must retain the above copyright notice,
; this list of conditions and the disclaimer below.
;
; Nations' name may not be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; ****************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_WKUP_IRQHandler ; RTC_WKUP
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_4_IRQHandler ; ADC3 & ADC4
DCD XFMC_IRQHandler ; XFMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet global interrupt
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD QSPI_IRQHandler ; QSPI
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel7
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD UART6_IRQHandler ; UART6
DCD UART7_IRQHandler ; UART7
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel8
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel8
DCD DVP_IRQHandler ; DVP
DCD SAC_IRQHandler ; SAC
DCD MMU_IRQHandler ; MMU
DCD TSC_IRQHandler ; TSC
DCD COMP_1_2_3_IRQHandler ; COMP1 & COMP2 & COMP3
DCD COMP_4_5_6_IRQHandler ; COMP4 & COMP5 & COMP6
DCD COMP7_IRQHandler ; COMP7
DCD RSRAM_IRQHandler ; R-SRAM parity error interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_4_IRQHandler [WEAK]
EXPORT XFMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT UART6_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT DVP_IRQHandler [WEAK]
EXPORT SAC_IRQHandler [WEAK]
EXPORT MMU_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT COMP_1_2_3_IRQHandler [WEAK]
EXPORT COMP_4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT RSRAM_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_4_IRQHandler
XFMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
QSPI_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
DMA1_Channel8_IRQHandler
DMA2_Channel8_IRQHandler
DVP_IRQHandler
SAC_IRQHandler
MMU_IRQHandler
TSC_IRQHandler
COMP_1_2_3_IRQHandler
COMP_4_5_6_IRQHandler
COMP7_IRQHandler
RSRAM_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

643
bsp/n32g452xx/Libraries/CMSIS/device/startup/startup_n32g45x_EWARM.s Executable file
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486
bsp/n32g452xx/Libraries/CMSIS/device/startup/startup_n32g45x_gcc.S Executable file
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@@ -0,0 +1,486 @@
/**
******************************************************************************
* @file startup_n32g45x.S
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMPER_IRQHandler /* Tamper */
.word RTC_WKUP_IRQHandler /* RTC Wakeup */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.word ADC1_2_IRQHandler /* ADC1, ADC2 */
.word USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */
.word USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.word TIM1_BRK_IRQHandler /* TIM1 Break */
.word TIM1_UP_IRQHandler /* TIM1 Update */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.word TIM8_BRK_IRQHandler /* TIM8 Break */
.word TIM8_UP_IRQHandler /* TIM8 Update */
.word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word ADC3_4_IRQHandler /* ADC3 & ADC4 */
.word XFMC_IRQHandler /* XFMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_IRQHandler /* TIM6 */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */
.word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */
.word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */
.word DMA2_Channel4_IRQHandler /* DMA2 Channel4 */
.word DMA2_Channel5_IRQHandler /* DMA2 Channel5 */
.word ETH_IRQHandler /* Ethernet global interrupt */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word QSPI_IRQHandler /* QSPI */
.word DMA2_Channel6_IRQHandler /* DMA2 Channel6 */
.word DMA2_Channel7_IRQHandler /* DMA2 Channel7 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word I2C4_EV_IRQHandler /* I2C4 event */
.word I2C4_ER_IRQHandler /* I2C4 error */
.word UART6_IRQHandler /* UART6 */
.word UART7_IRQHandler /* UART7 */
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
.word DMA2_Channel8_IRQHandler /* DMA2 Channel8 */
.word DVP_IRQHandler /* DVP */
.word SAC_IRQHandler /* SAC */
.word MMU_IRQHandler /* MMU */
.word TSC_IRQHandler /* TSC */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_4_IRQHandler
.thumb_set ADC3_4_IRQHandler,Default_Handler
.weak XFMC_IRQHandler
.thumb_set XFMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak QSPI_IRQHandler
.thumb_set QSPI_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak UART6_IRQHandler
.thumb_set UART6_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak DVP_IRQHandler
.thumb_set DVP_IRQHandler,Default_Handler
.weak SAC_IRQHandler
.thumb_set SAC_IRQHandler,Default_Handler
.weak MMU_IRQHandler
.thumb_set MMU_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

421
bsp/n32g452xx/Libraries/CMSIS/device/system_n32g45x.c Executable file
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@@ -0,0 +1,421 @@
/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file system_n32g45x.c
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#include "n32g45x.h"
/* Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your
device's maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume
that:
- For Low, Medium and High density Value line devices an external 8MHz
crystal is used to drive the System clock.
- For Low, Medium and High density devices an external 8MHz crystal is
used to drive the System clock.
- For Connectivity line devices an external 25MHz crystal is used to
drive the System clock. If you are using different crystal you have to adapt
those functions accordingly.
*/
#define SYSCLK_USE_HSI 0
#define SYSCLK_USE_HSE 1
#define SYSCLK_USE_HSI_PLL 2
#define SYSCLK_USE_HSE_PLL 3
#ifndef SYSCLK_FREQ
#define SYSCLK_FREQ 144000000
#endif
#ifndef SYSCLK_SRC
#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
#endif
#if SYSCLK_SRC == SYSCLK_USE_HSI
#if SYSCLK_FREQ != HSI_VALUE
#error SYSCL_FREQ must be set to HSI_VALUE
#endif
#elif SYSCLK_SRC == SYSCLK_USE_HSE
#ifndef HSE_VALUE
#error HSE_VALUE must be defined!
#endif
#if SYSCLK_FREQ != HSE_VALUE
#error SYSCL_FREQ must be set to HSE_VALUE
#endif
#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
#if (SYSCLK_FREQ % (HSI_VALUE / 2) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
&& (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
#define PLLSRC_DIV 2
#define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
#else
#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
#endif
#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
#ifndef HSE_VALUE
#error HSE_VALUE must be defined!
#endif
#if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
&& (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
#define PLLSRC_DIV 2
#define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
#elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
#define PLLSRC_DIV 1
#define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
#else
#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
#endif
#else
#error wrong value for SYSCLK_SRC
#endif
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
/*******************************************************************************
* Clock Definitions
*******************************************************************************/
uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
*/
void SystemInit(void)
{
/* FPU settings
* ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSIEN bit */
RCC->CTRL |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFG &= (uint32_t)0xF8FFC000;
/* Reset HSEON, CLKSSEN and PLLEN bits */
RCC->CTRL &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CTRL &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */
RCC->CFG &= (uint32_t)0xF700FFFF;
/* Reset CFG2 register */
RCC->CFG2 = 0x00000000;
/* Reset CFG3 register */
RCC->CFG3 = 0x00000000;
/* Disable all interrupts and clear pending bits */
RCC->CLKINT = 0x009F0000;
/* Enable ex mode */
RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
PWR->CTRL3 |= 0x00000001;
RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
/* Enable ICACHE and Prefetch Buffer */
FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or
* configure other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any
* configuration based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the
* HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the
* HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the
* HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in n32g45x.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in N32G45X.h file (default value
* 8 MHz or 25 MHz, depedning on the product used), user has to
* ensure that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
*
* - The result of this function could be not correct when using
* fractional value for HSE crystal.
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
/* Get SYSCLK source
* -------------------------------------------------------*/
tmp = RCC->CFG & RCC_CFG_SCLKSTS;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor
* ----------------------*/
pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
pllsource = RCC->CFG & RCC_CFG_PLLSRC;
if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
{
pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
}
else
{
pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
}
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
/* HSE selected as PLL clock entry */
if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
{ /* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
}
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
* prescalers.
*/
static void SetSysClock(void)
{
uint32_t rcc_cfgr = 0;
bool HSEStatus = 0;
uint32_t StartUpCounter = 0;
#if SYSCLK_SRC == SYSCLK_USE_HSE || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
/* Enable HSE */
RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
StartUpCounter++;
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
if (!HSEStatus)
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error */
SystemCoreClock = HSI_VALUE;
return;
}
#endif
/* Flash wait state
0: HCLK <= 32M
1: HCLK <= 64M
2: HCLK <= 96M
3: HCLK <= 128M
4: HCLK <= 144M
*/
FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
/* PCLK2 max 72M */
if (SYSCLK_FREQ > 72000000)
{
RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
}
else
{
RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
}
/* PCLK1 max 36M */
if (SYSCLK_FREQ > 72000000)
{
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
}
else if (SYSCLK_FREQ > 36000000)
{
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
}
else
{
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
}
#if SYSCLK_SRC == SYSCLK_USE_HSE
/* Select HSE as system clock source */
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
{
}
#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
/* clear bits */
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
/* set PLL source */
rcc_cfgr = RCC->CFG;
rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE);
#if SYSCLK_SRC == SYSCLK_USE_HSE_PLL
rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
#endif
/* set PLL multiply factor */
#if PLL_MUL <= 16
rcc_cfgr |= (PLL_MUL - 2) << 18;
#else
rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27);
#endif
RCC->CFG = rcc_cfgr;
/* Enable PLL */
RCC->CTRL |= RCC_CTRL_PLLEN;
/* Wait till PLL is ready */
while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
{
}
#endif
}

59
bsp/n32g452xx/Libraries/CMSIS/device/system_n32g45x.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file system_n32g45x.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __SYSTEM_N32G45X_H__
#define __SYSTEM_N32G45X_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup N32G45X_System
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_N32G45X_H__ */

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bsp/n32g452xx/Libraries/SConscript Executable file
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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('n32g45x_std_periph_driver/src/*.c')
src += [cwd + '/CMSIS/device/system_n32g45x.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/device/startup/startup_n32g45x_gcc.S']
elif rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/device/startup/startup_n32g45x.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [cwd + '/CMSIS/device/startup/startup_n32g45x_EWARM.s']
path = [
cwd + '/CMSIS/core',
cwd + '/CMSIS/device',
cwd + '/n32g45x_std_periph_driver/inc',]
if GetDepend(['RT_USING_BSP_USB']):
path += [cwd + '/n32g45x_usbfs_driver/inc']
src += [cwd + '/n32g45x_usbfs_driver/src']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'N32G45X']
group = DefineGroup('N32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
#print('CROSS_TOOL=[%s]' %(rtconfig.CROSS_TOOL))
#print('path=[%s]' %(path))
Return('group')

126
bsp/n32g452xx/Libraries/n32g45x_algo_lib/inc/n32g45x_aes.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_aes.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_AES_H__
#define __N32G45X_AES_H__
#include <stdint.h>
/** @addtogroup N32G45X_Algorithm_Library
* @{
*/
/** @addtogroup AES
* @brief AES symmetrical cipher algorithm
* @{
*/
#define AES_ECB (0x11111111)
#define AES_CBC (0x22222222)
#define AES_CTR (0x33333333)
#define AES_ENC (0x44444444)
#define AES_DEC (0x55555555)
enum
{
AES_Crypto_OK = 0x0, //AES opreation success
AES_Init_OK = 0x0, //AES Init opreation success
AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
AES_Crypto_ParaNull, // the part of input(output/iv) Null
AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
//if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
AES_Crypto_UnInitError, //AES uninitialized
};
typedef struct
{
uint32_t *in; // the part of input to be encrypted or decrypted
uint32_t *iv; // the part of initial vector
uint32_t *out; // the part of out
uint32_t *key; // the part of key
uint32_t keyWordLen; // the length(by word) of key
uint32_t inWordLen; // the length(by word) of plaintext or cipher
uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
}AES_PARM;
/**
* @brief AES_Init
* @return AES_Init_OK, AES Init success; othets: AES Init fail
* @note
*/
uint32_t AES_Init(AES_PARM *parm);
/**
* @brief AES crypto
* @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
* @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
* @note 1.Please refer to the demo in user guidance before using this function
* 2.Input and output can be the same buffer
* 3. IV can be NULL when ECB mode
* 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
* if Working mode is CTR,the length of input message cannot be zero;
* 5. If the input is in byte, make sure align by word.
*/
uint32_t AES_Crypto(AES_PARM *parm);
/**
* @brief AES close
* @return none
* @note if you want to close AES algorithm, this function can be recalled.
*/
void AES_Close(void);
/**
* @brief Get AES lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get AES lib information
*/
void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
#endif

154
bsp/n32g452xx/Libraries/n32g45x_algo_lib/inc/n32g45x_algo_common.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_algo_common.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_ALGO_COMMON_H__
#define __N32G45X_ALGO_COMMON_H__
#include <stdint.h>
/** @addtogroup N32G45X_Algorithm_Library
* @{
*/
enum{
Cpy_OK=0,//copy success
SetZero_OK = 0,//set zero success
XOR_OK = 0, //XOR success
Reverse_OK = 0, //Reverse success
Cmp_EQUAL = 0, //Two big number are equal
Cmp_UNEQUAL = 1, //Two big number are not equal
};
/**
* @brief disturb the sequence order
* @param[in] order pointer to the sequence to be disturbed
* @param[in] rand pointer to random number
* @param[in] the length of order
* @return RandomSort_OK: disturb order success; Others: disturb order fail;
* @note
*/
uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
/**
* @brief Copy data by byte
* @param[in] dst pointer to destination data
* @param[in] src pointer to source data
* @param[in] byte length
* @return Cpy_OK: success; others: fail.
* @note 1. dst and src cannot be same
*/
uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen);
/**
* @brief Copy data by word
* @param[in] dst pointer to destination data
* @param[in] src pointer to source data
* @param[in] word length
* @return Cpy_OK: success; others: fail.
* @note 1. dst and src must be aligned by word
*/
uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
/**
* @brief XOR
* @param[in] a pointer to one data to be XORed
* @param[in] b pointer to another data to be XORed
* @param[in] the length of order
* @return XOR_OK: operation success; Others: operation fail;
* @note
*/
uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
/**
* @brief XORed two u32 arrays
* @param[in] a pointer to one data to be XORed
* @param[in] b pointer to another data to be XORed
* @param[in] the length of order
* @return XOR_OK: operation success; Others: operation fail;
* @note
*/
uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
/**
* @brief set zero by byte
* @param[in] dst pointer to the address to be set zero
* @param[in] byte length
* @return SetZero_OK: success; others: fail.
* @note
*/
uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
/**
* @brief set zero by word
* @param[in] dst pointer to the address to be set zero
* @param[in] word length
* @return SetZero_OK: success; others: fail.
* @note
*/
uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
/**
* @brief reverse byte order of every word, the words stay the same
* @param[in] dst pointer to the destination address
* @param[in] src pointer to the source address
* @param[in] word length
* @return Reverse_OK: success; others: fail.
* @note 1.dst and src can be same
*/
uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
/**
* @brief compare two big number
* @param[in] a pointer to one big number
* @param[in] word length of a
* @param[in] b pointer to another big number
* @param[in] word length of b
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
*
*/
int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
/**
* @brief compare two big number
* @param[in] a pointer to one big number
* @param[in] word length of a
* @param[in] b pointer to another big number
* @param[in] word length of b
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
*
*/
int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
#endif

121
bsp/n32g452xx/Libraries/n32g45x_algo_lib/inc/n32g45x_des.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_des.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_DES_H__
#define __N32G45X_DES_H__
#include <stdint.h>
/** @addtogroup N32G45X_Algorithm_Library
* @{
*/
/** @addtogroup DES
* @brief DES symmetrical cipher algorithm
* @{
*/
#define DES_ECB (0x11111111)
#define DES_CBC (0x22222222)
#define DES_ENC (0x33333333)
#define DES_DEC (0x44444444)
#define DES_KEY (0x55555555)
#define TDES_2KEY (0x66666666)
#define TDES_3KEY (0x77777777)
enum DES
{
DES_Crypto_OK = 0x0, // DES/TDES opreation success
DES_Init_OK = 0x0, // DES/TDES Init opreation success
DES_Crypto_ModeError = 0x5a5a5a5a, // Working mode error(Neither ECB nor CBC)
DES_Crypto_EnOrDeError, // En&De error(Neither encryption nor decryption)
DES_Crypto_ParaNull, // the part of input(output/iv) Null
DES_Crypto_LengthError, // the length of input message must be 2 times and cannot be zero
DES_Crypto_KeyError, // keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
DES_Crypto_UnInitError, // DES/TDES uninitialized
};
typedef struct
{
uint32_t* in; // the part of input to be encrypted or decrypted
uint32_t* iv; // the part of initial vector
uint32_t* out; // the part of out
uint32_t* key; // the part of key
uint32_t inWordLen; // the length(by word) of plaintext or cipher
uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
uint32_t keyMode; // TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
} DES_PARM;
/**
* @brief DES_Init
* @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
* @note
*/
uint32_t DES_Init(DES_PARM* parm);
/**
* @brief DES crypto
* @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
* @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
* @note 1.Please refer to the demo in user guidance before using this function
* 2.Input and output can be the same buffer
* 3. IV can be NULL when ECB mode
* 4. The word lengrh of message must be as times as 2.
* 5. If the input is in byte, make sure align by word.
*/
uint32_t DES_Crypto(DES_PARM* parm);
/**
* @brief DES close
* @return none
* @note if you want to close DES algorithm, this function can be recalled.
*/
void DES_Close(void);
/**
* @brief Get DES/TDES lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get DES/TDES lib information
*/
void DES_Version(uint8_t* type, uint8_t* customer, uint8_t date[3], uint8_t* version);
#endif

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_hash.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_HASH_H__
#define __N32G45X_HASH_H__
#include <stdint.h>
/** @addtogroup N32G45X_Algorithm_Library
* @{
*/
/** @addtogroup HASH
* @brief Message digest algorithms
* @{
*/
#define ALG_SHA1 (uint16_t)(0x0004)
#define ALG_SHA224 (uint16_t)(0x000A)
#define ALG_SHA256 (uint16_t)(0x000B)
#define ALG_MD5 (uint16_t)(0x000C)
#define ALG_SM3 (uint16_t)(0x0012)
enum
{
HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
HASH_Init_OK = 0,//hash init success
HASH_Start_OK = 0,//hash update success
HASH_Update_OK = 0,//hash update success
HASH_Complete_OK = 0,//hash complete success
HASH_Close_OK = 0,//hash close success
HASH_ByteLenPlus_OK = 0,//byte length plus success
HASH_PadMsg_OK = 0,//message padding success
HASH_ProcMsgBuf_OK = 0, //message processing success
SHA1_Hash_OK = 0,//sha1 operation success
SM3_Hash_OK = 0,//sm3 operation success
SHA224_Hash_OK = 0,//sha224 operation success
SHA256_Hash_OK = 0,//sha256 operation success
MD5_Hash_OK = 0,//MD5 operation success
HASH_Init_ERROR = 0x01044400,//hash init error
HASH_Start_ERROR, //hash start error
HASH_Update_ERROR, //hash update error
HASH_ByteLenPlus_ERROR,//hash byte plus error
};
typedef struct _HASH_CTX_ HASH_CTX;
typedef struct
{
const uint16_t HashAlgID;//choice hash algorithm
const uint32_t * const K, KLen;//K and word length of K
const uint32_t * const IV, IVLen;//IV and word length of IV
const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
const uint32_t Cycle; //interation times
uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
uint32_t (* const PadMsg)(HASH_CTX *); //function pointer
}HASH_ALG;
typedef struct _HASH_CTX_
{
const HASH_ALG *hashAlg;//pointer to HASH_ALG
uint32_t sequence; // TRUE if the IV should be saved
uint32_t IV[16];
uint32_t msgByteLen[4];
uint8_t msgBuf[128+4];
uint32_t msgIdx;
}HASH_CTX;
extern const HASH_ALG HASH_ALG_SHA1[1];
extern const HASH_ALG HASH_ALG_SHA224[1];
extern const HASH_ALG HASH_ALG_SHA256[1];
extern const HASH_ALG HASH_ALG_MD5[1];
extern const HASH_ALG HASH_ALG_SM3[1];
/**
* @brief Hash init
* @param[in] ctx pointer to HASH_CTX struct
* @return HASH_Init_OK, Hash init success; othets: Hash init fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t HASH_Init(HASH_CTX *ctx);
/**
* @brief Hash start
* @param[in] ctx pointer to HASH_CTX struct
* @return HASH_Start_OK, Hash start success; othets: Hash start fail
* @note 1.Please refer to the demo in user guidance before using this function
* 2.HASH_Init() should be recalled before use this function
*/
uint32_t HASH_Start(HASH_CTX *ctx);
/**
* @brief Hash update
* @param[in] ctx pointer to HASH_CTX struct
* @param[in] in pointer to message
* @param[out] out pointer tohash result,digest
* @return HASH_Update_OK, Hash update success; othets: Hash update fail
* @note 1.Please refer to the demo in user guidance before using this function
* 2.HASH_Init() and HASH_Start() should be recalled before use this function
*/
uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
/**
* @brief Hash complete
* @param[in] ctx pointer to HASH_CTX struct
* @param[out] out pointer tohash result,digest
* @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
* @note 1.Please refer to the demo in user guidance before using this function
* 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
*/
uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
/**
* @brief Hash close
* @return HASH_Close_OK, Hash close success; othets: Hash close fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t HASH_Close(void);
/**
* @brief SM3 Hash for 256bits digest
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief SHA1 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief SHA224 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief SHA256 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief MD5 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[in] out pointer tohash result,digest
* @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief Get HASH lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get RSA lib information
*/
void HASH_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
#endif

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_rng.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_RNG_H__
#define __N32G45X_RNG_H__
#include <stdint.h>
/** @addtogroup N32G45X_Algorithm_Library
* @{
*/
/** @addtogroup RNG
* @brief Random number generator
* @{
*/
enum{
RNG_OK = 0x5a5a5a5a,
LENError = 0x311ECF50, //RNG generation of key length error
ADDRNULL = 0x7A9DB86C, // This address is empty
};
//u32 RNG_init(void);
/**
* @brief Get pseudo random number
* @param[out] rand pointer to random number
* @param[in] the wordlen of random number
* @param[in] the seed, can be NULL
* @return RNG_OK:get random number success; othets: get random number fail
* @note
*/
uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
/**
* @brief Get true random number
* @param[out] rand pointer to random number
* @param[in] the wordlen of random number
* @return RNG_OK:get random number success; othets: get random number fail
* @note
*/
uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
/**
* @brief Get RNG lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get RSA lib information
*/
void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
#endif

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file misc.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __MISC_H__
#define __MISC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @addtogroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete N32G45X Devices IRQ Channels list, please
refer to n32g45x.h file) */
uint8_t
NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitType;
/**
* @}
*/
/** @addtogroup NVIC_Priority_Table
* @{
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
priority | | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
priority | | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
priority | | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
priority | | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
priority | | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
/**
* @}
*/
/** @addtogroup MISC_Exported_Constants
* @{
*/
/** @addtogroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @addtogroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @addtogroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 \
((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
4 bits for subpriority */
#define NVIC_PriorityGroup_1 \
((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
3 bits for subpriority */
#define NVIC_PriorityGroup_2 \
((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
2 bits for subpriority */
#define NVIC_PriorityGroup_3 \
((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
1 bits for subpriority */
#define NVIC_PriorityGroup_4 \
((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) \
(((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
|| ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
*/
/** @addtogroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
(((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_bkp.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_BKP_H__
#define __N32G45X_BKP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup BKP
* @{
*/
/** @addtogroup BKP_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup BKP_Exported_Constants
* @{
*/
/** @addtogroup Tamper_Pin_active_level
* @{
*/
#define BKP_TP_HIGH ((uint16_t)0x0000)
#define BKP_TP_LOW ((uint16_t)0x0001)
#define IS_BKP_TP_LEVEL(LEVEL) (((LEVEL) == BKP_TP_HIGH) || ((LEVEL) == BKP_TP_LOW))
/**
* @}
*/
/** @addtogroup Data_Backup_Register
* @{
*/
#define BKP_DAT1 ((uint16_t)0x0004)
#define BKP_DAT2 ((uint16_t)0x0008)
#define BKP_DAT3 ((uint16_t)0x000C)
#define BKP_DAT4 ((uint16_t)0x0010)
#define BKP_DAT5 ((uint16_t)0x0014)
#define BKP_DAT6 ((uint16_t)0x0018)
#define BKP_DAT7 ((uint16_t)0x001C)
#define BKP_DAT8 ((uint16_t)0x0020)
#define BKP_DAT9 ((uint16_t)0x0024)
#define BKP_DAT10 ((uint16_t)0x0028)
#define BKP_DAT11 ((uint16_t)0x0040)
#define BKP_DAT12 ((uint16_t)0x0044)
#define BKP_DAT13 ((uint16_t)0x0048)
#define BKP_DAT14 ((uint16_t)0x004C)
#define BKP_DAT15 ((uint16_t)0x0050)
#define BKP_DAT16 ((uint16_t)0x0054)
#define BKP_DAT17 ((uint16_t)0x0058)
#define BKP_DAT18 ((uint16_t)0x005C)
#define BKP_DAT19 ((uint16_t)0x0060)
#define BKP_DAT20 ((uint16_t)0x0064)
#define BKP_DAT21 ((uint16_t)0x0068)
#define BKP_DAT22 ((uint16_t)0x006C)
#define BKP_DAT23 ((uint16_t)0x0070)
#define BKP_DAT24 ((uint16_t)0x0074)
#define BKP_DAT25 ((uint16_t)0x0078)
#define BKP_DAT26 ((uint16_t)0x007C)
#define BKP_DAT27 ((uint16_t)0x0080)
#define BKP_DAT28 ((uint16_t)0x0084)
#define BKP_DAT29 ((uint16_t)0x0088)
#define BKP_DAT30 ((uint16_t)0x008C)
#define BKP_DAT31 ((uint16_t)0x0090)
#define BKP_DAT32 ((uint16_t)0x0094)
#define BKP_DAT33 ((uint16_t)0x0098)
#define BKP_DAT34 ((uint16_t)0x009C)
#define BKP_DAT35 ((uint16_t)0x00A0)
#define BKP_DAT36 ((uint16_t)0x00A4)
#define BKP_DAT37 ((uint16_t)0x00A8)
#define BKP_DAT38 ((uint16_t)0x00AC)
#define BKP_DAT39 ((uint16_t)0x00B0)
#define BKP_DAT40 ((uint16_t)0x00B4)
#define BKP_DAT41 ((uint16_t)0x00B8)
#define BKP_DAT42 ((uint16_t)0x00BC)
#define IS_BKP_DAT(DAT) \
(((DAT) == BKP_DAT1) || ((DAT) == BKP_DAT2) || ((DAT) == BKP_DAT3) || ((DAT) == BKP_DAT4) || ((DAT) == BKP_DAT5) \
|| ((DAT) == BKP_DAT6) || ((DAT) == BKP_DAT7) || ((DAT) == BKP_DAT8) || ((DAT) == BKP_DAT9) \
|| ((DAT) == BKP_DAT10) || ((DAT) == BKP_DAT11) || ((DAT) == BKP_DAT12) || ((DAT) == BKP_DAT13) \
|| ((DAT) == BKP_DAT14) || ((DAT) == BKP_DAT15) || ((DAT) == BKP_DAT16) || ((DAT) == BKP_DAT17) \
|| ((DAT) == BKP_DAT18) || ((DAT) == BKP_DAT19) || ((DAT) == BKP_DAT20) || ((DAT) == BKP_DAT21) \
|| ((DAT) == BKP_DAT22) || ((DAT) == BKP_DAT23) || ((DAT) == BKP_DAT24) || ((DAT) == BKP_DAT25) \
|| ((DAT) == BKP_DAT26) || ((DAT) == BKP_DAT27) || ((DAT) == BKP_DAT28) || ((DAT) == BKP_DAT29) \
|| ((DAT) == BKP_DAT30) || ((DAT) == BKP_DAT31) || ((DAT) == BKP_DAT32) || ((DAT) == BKP_DAT33) \
|| ((DAT) == BKP_DAT34) || ((DAT) == BKP_DAT35) || ((DAT) == BKP_DAT36) || ((DAT) == BKP_DAT37) \
|| ((DAT) == BKP_DAT38) || ((DAT) == BKP_DAT39) || ((DAT) == BKP_DAT40) || ((DAT) == BKP_DAT41) \
|| ((DAT) == BKP_DAT42))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup BKP_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup BKP_Exported_Functions
* @{
*/
void BKP_DeInit(void);
void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel);
void BKP_TPEnable(FunctionalState Cmd);
void BKP_TPIntEnable(FunctionalState Cmd);
void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data);
uint16_t BKP_ReadBkpData(uint16_t BKP_DAT);
FlagStatus BKP_GetTEFlag(void);
void BKP_ClrTEFlag(void);
INTStatus BKP_GetTINTFlag(void);
void BKP_ClrTINTFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_BKP_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_comp.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_COMP_H__
#define __N32G45X_COMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
#include <stdbool.h>
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/** @addtogroup COMP_Exported_Constants
* @{
*/
typedef enum
{
COMP1 = 0,
COMP2 = 1,
COMP3 = 2,
COMP4 = 3,
COMP5 = 4,
COMP6 = 5,
COMP7 = 6
} COMPX;
// COMPx_CTRL
#define COMP1_CTRL_INPDAC_MASK (0x01L << 18)
#define COMP_CTRL_OUT_MASK (0x01L << 17)
#define COMP_CTRL_BLKING_MASK (0x07L << 14)
typedef enum
{
COMP_CTRL_BLKING_NO = (0x0L << 14),
COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 14),
COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 14),
} COMP_CTRL_BLKING;
#define COMPx_CTRL_HYST_MASK (0x03L << 12)
typedef enum
{
COMP_CTRL_HYST_NO = (0x0L << 12),
COMP_CTRL_HYST_LOW = (0x1L << 12),
COMP_CTRL_HYST_MID = (0x2L << 12),
COMP_CTRL_HYST_HIGH = (0x3L << 12),
} COMP_CTRL_HYST;
#define COMP_POL_MASK (0x01L << 11)
#define COMP_CTRL_OUTSEL_MASK (0x0FL << 7)
typedef enum
{
COMPX_CTRL_OUTSEL_NC = (0x0L << 7),
// comp1 out trig
COMP1_CTRL_OUTSEL_NC = (0x0L << 7),
COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7),
COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7),
COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 7),
COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7),
COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 7),
COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 7),
COMP1_CTRL_OUTSEL_TIM4_IC1 = (0x8L << 7),
COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x9L << 7),
COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
// comp2 out trig
COMP2_CTRL_OUTSEL_NC = (0x0L << 7),
COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7),
COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7),
COMP2_CTRL_OUTSEL_TIM2_IC2 = (0x4L << 7),
COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7),
COMP2_CTRL_OUTSEL_TIM3_IC2 = (0x6L << 7),
COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 7),
COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 7), ////(0x9L << 7)
COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
// comp3 out trig
COMP3_CTRL_OUTSEL_NC = (0x0L << 7),
COMP3_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP3_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7),
COMP3_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7),
COMP3_CTRL_OUTSEL_TIM2_IC3 = (0x4L << 7),
COMP3_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7),
COMP3_CTRL_OUTSEL_TIM4_IC2 = (0x6L << 7),
COMP3_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 7),
COMP3_CTRL_OUTSEL_TIM5_IC2 = (0x8L << 7), //(0x9L << 7)
COMP3_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP3_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
// comp4 out trig
COMP4_CTRL_OUTSEL_NC = (0x0L << 7),
COMP4_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP4_CTRL_OUTSEL_TIM3_IC3 = (0x2L << 7),
COMP4_CTRL_OUTSEL_TIM3_OCrefclear = (0x3L << 7),
COMP4_CTRL_OUTSEL_TIM4_IC3 = (0x4L << 7),
COMP4_CTRL_OUTSEL_TIM4_OCrefclear = (0x5L << 7),
COMP4_CTRL_OUTSEL_TIM5_IC3 = (0x6L << 7), //(0x7L << 7)
COMP4_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
COMP4_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
COMP4_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP4_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
// comp5 out trig
COMP5_CTRL_OUTSEL_NC = (0x0L << 7),
COMP5_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP5_CTRL_OUTSEL_TIM2_IC4 = (0x2L << 7),
COMP5_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7),
COMP5_CTRL_OUTSEL_TIM3_IC4 = (0x4L << 7),
COMP5_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7),
COMP5_CTRL_OUTSEL_TIM4_IC4 = (0x6L << 7),
COMP5_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 7),
COMP5_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
COMP5_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
COMP5_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP5_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
// comp6 out trig
COMP6_CTRL_OUTSEL_NC = (0x0L << 7),
COMP6_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP6_CTRL_OUTSEL_TIM2_IC1 = (0x2L << 7),
COMP6_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7),
COMP6_CTRL_OUTSEL_TIM3_IC1 = (0x4L << 7),
COMP6_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7),
COMP6_CTRL_OUTSEL_TIM5_IC1 = (0x6L << 7), //(0x7L << 7)
COMP6_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
COMP6_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
COMP6_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP6_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
// comp7 out trig
COMP7_CTRL_OUTSEL_NC = (0x0L << 7),
COMP7_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
COMP7_CTRL_OUTSEL_TIM2_IC1 = (0x2L << 7),
COMP7_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7),
COMP7_CTRL_OUTSEL_TIM3_IC1 = (0x4L << 7),
COMP7_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7),
COMP7_CTRL_OUTSEL_TIM5_IC1 = (0x6L << 7), //(0x7L << 7)
COMP7_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
COMP7_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
COMP7_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
COMP7_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
} COMP_CTRL_OUTTRIG;
#define COMP_CTRL_INPSEL_MASK (0x07L<<4)
typedef enum {
COMPX_CTRL_INPSEL_RES = (0x7L << 4),
//comp1 inp sel
COMP1_CTRL_INPSEL_PA1 = (0x0L << 4),
COMP1_CTRL_INPSEL_PB10 = (0x1L << 4),
//comp2 inp sel, need recheck maybe wrong
COMP2_CTRL_INPSEL_PA1 = (0x0L << 4),
COMP2_CTRL_INPSEL_PB11 = (0x1L << 4),
COMP2_CTRL_INPSEL_PA7 = (0x2L << 4),
//comp3 inp sel
COMP3_CTRL_INPSEL_PB14 = (0x0L << 4),
COMP3_CTRL_INPSEL_PB0 = (0x1L << 4),
//comp4 inp sel, need recheck maybe wrong
COMP4_CTRL_INPSEL_PB14 = (0x0L << 4),
COMP4_CTRL_INPSEL_PB0 = (0x1L << 4),
COMP4_CTRL_INPSEL_PC9 = (0x2L << 4),
COMP4_CTRL_INPSEL_PB15 = (0x3L << 4),
//comp5 inp sel
COMP5_CTRL_INPSEL_PC4 = (0x0L << 4),
COMP5_CTRL_INPSEL_PC3 = (0x1L << 4),
COMP5_CTRL_INPSEL_PA3 = (0x2L << 4),
//comp6 inp sel, need recheck maybe wrong
COMP6_CTRL_INPSEL_PC4 = (0x0L << 4),
COMP6_CTRL_INPSEL_PC3 = (0x1L << 4),
COMP6_CTRL_INPSEL_PC5 = (0x2L << 4),
COMP6_CTRL_INPSEL_PD9 = (0x3L << 4),
//comp7 inp sel
COMP7_CTRL_INPSEL_PC1 = (0x0L << 4),
}COMP_CTRL_INPSEL;
#define COMP_CTRL_INMSEL_MASK (0x07L<<1)
typedef enum {
COMPX_CTRL_INMSEL_RES = (0x7L << 1),
//comp1 inm sel
COMP1_CTRL_INMSEL_PA0 = (0x0L << 1),
COMP1_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
COMP1_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
COMP1_CTRL_INMSEL_VERF1 = (0x3L << 1),
COMP1_CTRL_INMSEL_VERF2 = (0x4L << 1),
//comp2 inm sel
COMP2_CTRL_INMSEL_PB1 = (0x0L << 1),
COMP2_CTRL_INMSEL_PE8 = (0x1L << 1),
COMP2_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP2_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
COMP2_CTRL_INMSEL_VERF1 = (0x4L << 1),
COMP2_CTRL_INMSEL_VERF2 = (0x5L << 1),
//comp3 inm sel
COMP3_CTRL_INMSEL_PB12 = (0x0L << 1),
COMP3_CTRL_INMSEL_PE7 = (0x1L << 1),
COMP3_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP3_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
COMP3_CTRL_INMSEL_VERF1 = (0x4L << 1),
COMP3_CTRL_INMSEL_VERF2 = (0x5L << 1),
//comp4 inm sel
COMP4_CTRL_INMSEL_PC4 = (0x0L << 1),
COMP4_CTRL_INMSEL_PB13 = (0x1L << 1),
COMP4_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP4_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
COMP4_CTRL_INMSEL_VERF1 = (0x4L << 1),
COMP4_CTRL_INMSEL_VERF2 = (0x5L << 1),
//comp5 inm sel
COMP5_CTRL_INMSEL_PB10 = (0x0L << 1),
COMP5_CTRL_INMSEL_PD10 = (0x1L << 1),
COMP5_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP5_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
COMP5_CTRL_INMSEL_VERF1 = (0x4L << 1),
COMP5_CTRL_INMSEL_VERF2 = (0x5L << 1),
//comp6 inm sel
COMP6_CTRL_INMSEL_PA7 = (0x0L << 1),
COMP6_CTRL_INMSEL_PD8 = (0x1L << 1),
COMP6_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP6_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
COMP6_CTRL_INMSEL_VERF1 = (0x4L << 1),
COMP6_CTRL_INMSEL_VERF2 = (0x5L << 1),
//comp7 inm sel
COMP7_CTRL_INMSEL_PC0 = (0x0L << 1),
COMP7_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
COMP7_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
COMP7_CTRL_INMSEL_VERF1 = (0x3L << 1),
COMP7_CTRL_INMSEL_VERF2 = (0x4L << 1),
}COMP_CTRL_INMSEL;
#define COMP_CTRL_EN_MASK (0x01L << 0)
//COMPx_FILC
#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable.
//COMPx_FILCLKCR
#define COMP_FILCLKCR_CLKPSC_MASK (0xFFFFL<<0)//Low filter sample clock prescale. Number of system clocks between samples = CLK_PRE_CYCLE + 1, e.g.
//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
#define COMP_WINMODE_CMPMD_MSK (0x07L <<0)
#define COMP_WINMODE_CMP56MD (0x01L <<2)//1: Comparators 5 and 6 can be used in window mode.
#define COMP_WINMODE_CMP34MD (0x01L <<1)//1: Comparators 3 and 4 can be used in window mode.
#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
//COMPx_LOCK
#define COMP_LOCK_CMPLK_MSK (0x7FL <<0)
#define COMP_LOCK_CMP1LK_MSK (0x01L <<0)//1: COMx Lock bit
#define COMP_LOCK_CMP2LK_MSK (0x01L <<1)//1: COMx Lock bit
#define COMP_LOCK_CMP3LK_MSK (0x01L <<2)//1: COMx Lock bit
#define COMP_LOCK_CMP4LK_MSK (0x01L <<3)//1: COMx Lock bit
#define COMP_LOCK_CMP5LK_MSK (0x01L <<4)//1: COMx Lock bit
#define COMP_LOCK_CMP6LK_MSK (0x01L <<5)//1: COMx Lock bit
#define COMP_LOCK_CMP7LK_MSK (0x01L <<6)//1: COMx Lock bit
// COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
#define COMP_INTEN_CMPIEN_MSK (0x7FL << 0)
#define COMP_INTEN_CMP7IEN (0x01L << 6) // This bit control Interrput enable of COMP.
#define COMP_INTEN_CMP6IEN (0x01L << 5)
#define COMP_INTEN_CMP5IEN (0x01L << 4)
#define COMP_INTEN_CMP4IEN (0x01L << 3)
#define COMP_INTEN_CMP3IEN (0x01L << 2)
#define COMP_INTEN_CMP2IEN (0x01L << 1)
#define COMP_INTEN_CMP1IEN (0x01L << 0)
// COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
#define COMP_INTSTS_INTSTS_MSK (0x7FL << 0)
#define COMP_INTSTS_CMP7IS (0x01L << 6) // This bit control Interrput enable of COMP.
#define COMP_INTSTS_CMP6IS (0x01L << 5)
#define COMP_INTSTS_CMP5IS (0x01L << 4)
#define COMP_INTSTS_CMP4IS (0x01L << 3)
#define COMP_INTSTS_CMP3IS (0x01L << 2)
#define COMP_INTSTS_CMP2IS (0x01L << 1)
#define COMP_INTSTS_CMP1IS (0x01L << 0)
// COMP_VREFSCL @addtogroup COMP_VREFSCL
#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value.
#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7)
#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value.
#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0)
/**
* @}
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
// ctrl
bool InpDacConnect; // only COMP1 have this bit
COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
COMP_CTRL_HYST Hyst;
bool PolRev; // out polarity reverse
COMP_CTRL_OUTTRIG OutSel;
COMP_CTRL_INPSEL InpSel;
COMP_CTRL_INMSEL InmSel;
bool En;
// filter
uint8_t SampWindow; // 5bit
uint8_t Thresh; // 5bit ,need > SampWindow/2
bool FilterEn;
// filter psc
uint16_t ClkPsc;
} COMP_InitType;
/** @addtogroup COMP_Exported_Functions
* @{
*/
void COMP_DeInit(void);
void COMP_StructInit(COMP_InitType* COMP_InitStruct);
void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
void COMP_Enable(COMPX COMPx, FunctionalState en);
void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK
void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN
uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS
void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
FlagStatus COMP_GetOutStatus(COMPX COMPx);
FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal);
void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW);
void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST);
void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__N32G45X_ADC_H */
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_crc.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_CRC_H__
#define __N32G45X_CRC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @addtogroup CRC_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup CRC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup CRC_Exported_Functions
* @{
*/
void CRC32_ResetCrc(void);
uint32_t CRC32_CalcCrc(uint32_t Data);
uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC32_GetCrc(void);
void CRC32_SetIDat(uint8_t IDValue);
uint8_t CRC32_GetIDat(void);
uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
uint16_t CRC16_CalcCRC(uint8_t Data);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_CRC_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_dac.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_DAC_H__
#define __N32G45X_DAC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @addtogroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t
LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
} DAC_InitType;
/**
* @}
*/
/** @addtogroup DAC_Exported_Constants
* @{
*/
/** @addtogroup DAC_trigger_selection
* @{
*/
#define DAC_TRG_NONE \
((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
has been loaded, and not by external trigger */
#define DAC_TRG_T6_TRGO \
((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T8_TRGO \
((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
only in High-density devices*/
#define DAC_TRG_T3_TRGO \
((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
only in Connectivity line, Medium-density and Low-density Value Line devices */
#define DAC_TRG_T7_TRGO \
((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T5_TRGO \
((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T15_TRGO \
((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \
only in Medium-density and Low-density Value Line devices*/
#define DAC_TRG_T2_TRGO \
((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T4_TRGO \
((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_EXT_IT9 \
((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) \
(((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
|| ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
|| ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
/**
* @}
*/
/** @addtogroup DAC_wave_generation
* @{
*/
#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) \
(((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
/**
* @}
*/
/** @addtogroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_UNMASK_LFSRBITS1_0 \
((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS2_0 \
((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS3_0 \
((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS4_0 \
((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS5_0 \
((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS6_0 \
((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS7_0 \
((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS8_0 \
((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS9_0 \
((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS10_0 \
((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_UNMASK_LFSRBITS11_0 \
((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
(((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
|| ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
|| ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
|| ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
|| ((VALUE) == DAC_TRIAMP_4095))
/**
* @}
*/
/** @addtogroup DAC_output_buffer
* @{
*/
#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002)
#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
/**
* @}
*/
/** @addtogroup DAC_Channel_selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || ((CHANNEL) == DAC_CHANNEL_2))
/**
* @}
*/
/** @addtogroup DAC_data_alignment
* @{
*/
#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) \
(((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
/**
* @}
*/
/** @addtogroup DAC_wave_generation
* @{
*/
#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
*/
/** @addtogroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
void DAC_DeInit(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct);
void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd);
void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd);
void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd);
void DAC_DualSoftwareTrgEnable(FunctionalState Cmd);
void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd);
void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel);
#ifdef __cplusplus
}
#endif
#endif /*__N32G45X_DAC_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_dbg.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_DBG_H__
#define __N32G45X_DBG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup DBG
* @{
*/
/** @addtogroup DBGMCU_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup DBGMCU_Exported_Constants
* @{
*/
#define DBG_SLEEP ((uint32_t)0x00000001)
#define DBG_STOP ((uint32_t)0x00000002)
#define DBG_STDBY ((uint32_t)0x00000004)
#define DBG_IWDG_STOP ((uint32_t)0x00000100)
#define DBG_WWDG_STOP ((uint32_t)0x00000200)
#define DBG_TIM1_STOP ((uint32_t)0x00000400)
#define DBG_TIM2_STOP ((uint32_t)0x00000800)
#define DBG_TIM3_STOP ((uint32_t)0x00001000)
#define DBG_TIM4_STOP ((uint32_t)0x00002000)
#define DBG_CAN1_STOP ((uint32_t)0x00004000)
#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define DBG_TIM8_STOP ((uint32_t)0x00020000)
#define DBG_TIM5_STOP ((uint32_t)0x00040000)
#define DBG_TIM6_STOP ((uint32_t)0x00080000)
#define DBG_TIM7_STOP ((uint32_t)0x00100000)
#define DBG_CAN2_STOP ((uint32_t)0x00200000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @addtogroup DBGMCU_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup DBGMCU_Exported_Functions
* @{
*/
void GetUCID(uint8_t *UCIDbuf);
void GetUID(uint8_t *UIDbuf);
void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
uint32_t DBG_GetRevNum(void);
uint32_t DBG_GetDevNum(void);
void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
uint32_t DBG_GetFlashSize(void);
uint32_t DBG_GetSramSize(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_DBG_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_exti.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_EXTI_H__
#define __N32G45X_EXTI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @addtogroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTI_ModeType;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTI_TriggerType;
#define IS_EXTI_TRIGGER(TRIGGER) \
(((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
|| ((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_ModeType */
EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_ModeType */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitType;
/**
* @}
*/
/** @addtogroup EXTI_Exported_Constants
* @{
*/
/** @addtogroup EXTI_Lines
* @{
*/
#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the TSC event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFC00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) \
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
|| ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
|| ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
|| ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
|| ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
|| ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21))
/**
* @}
*/
/** @addtogroup EXTI_TSSEL_Line
* @{
*/
#define IS_EXTI_TSSEL_LINE(LINE) \
(((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
|| ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
|| ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
|| ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
|| ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
|| ((LINE) == EXTI_TSSEL_LINE15))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(void);
void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
void EXTI_TriggerSWInt(uint32_t EXTI_Line);
FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClrITPendBit(uint32_t EXTI_Line);
void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_EXTI_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_flash.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_FLASH_H__
#define __N32G45X_FLASH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Exported_Types
* @{
*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_RESERVED,
FLASH_ERR_PG,
FLASH_ERR_PV,
FLASH_ERR_WRP,
FLASH_COMPL,
FLASH_ERR_EV,
FLASH_ERR_RDP2,
FLASH_ERR_ADD,
FLASH_TIMEOUT
} FLASH_STS;
typedef enum
{
FLASH_SMP1 = 0,
FLASH_SMP2
} FLASH_SMPSEL;
/**
* @}
*/
/** @addtogroup FLASH_Exported_Constants
* @{
*/
/** @addtogroup Flash_Latency
* @{
*/
#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
#define FLASH_LATENCY_4 ((uint32_t)0x00000004) /*!< FLASH Four Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) \
(((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \
|| ((LATENCY) == FLASH_LATENCY_3) || ((LATENCY) == FLASH_LATENCY_4))
/**
* @}
*/
/** @addtogroup Prefetch_Buffer_Enable_Disable
* @{
*/
#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
/**
* @}
*/
/** @addtogroup iCache_Enable_Disable
* @{
*/
#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
/**
* @}
*/
/** @addtogroup SMPSEL_SMP1_SMP2
* @{
*/
#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
/**
* @}
*/
/* Values to be used with N32G45X devices */
#define FLASH_WRP_Pages0to1 \
((uint32_t)0x00000001) /*!< N32G45X devices: \
Write protection of page 0 to 1 */
#define FLASH_WRP_Pages2to3 \
((uint32_t)0x00000002) /*!< N32G45X devices: \
Write protection of page 2 to 3 */
#define FLASH_WRP_Pages4to5 \
((uint32_t)0x00000004) /*!< N32G45X devices: \
Write protection of page 4 to 5 */
#define FLASH_WRP_Pages6to7 \
((uint32_t)0x00000008) /*!< N32G45X devices: \
Write protection of page 6 to 7 */
#define FLASH_WRP_Pages8to9 \
((uint32_t)0x00000010) /*!< N32G45X devices: \
Write protection of page 8 to 9 */
#define FLASH_WRP_Pages10to11 \
((uint32_t)0x00000020) /*!< N32G45X devices: \
Write protection of page 10 to 11 */
#define FLASH_WRP_Pages12to13 \
((uint32_t)0x00000040) /*!< N32G45X devices: \
Write protection of page 12 to 13 */
#define FLASH_WRP_Pages14to15 \
((uint32_t)0x00000080) /*!< N32G45X devices: \
Write protection of page 14 to 15 */
#define FLASH_WRP_Pages16to17 \
((uint32_t)0x00000100) /*!< N32G45X devices: \
Write protection of page 16 to 17 */
#define FLASH_WRP_Pages18to19 \
((uint32_t)0x00000200) /*!< N32G45X devices: \
Write protection of page 18 to 19 */
#define FLASH_WRP_Pages20to21 \
((uint32_t)0x00000400) /*!< N32G45X devices: \
Write protection of page 20 to 21 */
#define FLASH_WRP_Pages22to23 \
((uint32_t)0x00000800) /*!< N32G45X devices: \
Write protection of page 22 to 23 */
#define FLASH_WRP_Pages24to25 \
((uint32_t)0x00001000) /*!< N32G45X devices: \
Write protection of page 24 to 25 */
#define FLASH_WRP_Pages26to27 \
((uint32_t)0x00002000) /*!< N32G45X devices: \
Write protection of page 26 to 27 */
#define FLASH_WRP_Pages28to29 \
((uint32_t)0x00004000) /*!< N32G45X devices: \
Write protection of page 28 to 29 */
#define FLASH_WRP_Pages30to31 \
((uint32_t)0x00008000) /*!< N32G45X devices: \
Write protection of page 30 to 31 */
#define FLASH_WRP_Pages32to33 \
((uint32_t)0x00010000) /*!< N32G45X devices: \
Write protection of page 32 to 33 */
#define FLASH_WRP_Pages34to35 \
((uint32_t)0x00020000) /*!< N32G45X devices: \
Write protection of page 34 to 35 */
#define FLASH_WRP_Pages36to37 \
((uint32_t)0x00040000) /*!< N32G45X devices: \
Write protection of page 36 to 37 */
#define FLASH_WRP_Pages38to39 \
((uint32_t)0x00080000) /*!< N32G45X devices: \
Write protection of page 38 to 39 */
#define FLASH_WRP_Pages40to41 \
((uint32_t)0x00100000) /*!< N32G45X devices: \
Write protection of page 40 to 41 */
#define FLASH_WRP_Pages42to43 \
((uint32_t)0x00200000) /*!< N32G45X devices: \
Write protection of page 42 to 43 */
#define FLASH_WRP_Pages44to45 \
((uint32_t)0x00400000) /*!< N32G45X devices: \
Write protection of page 44 to 45 */
#define FLASH_WRP_Pages46to47 \
((uint32_t)0x00800000) /*!< N32G45X devices: \
Write protection of page 46 to 47 */
#define FLASH_WRP_Pages48to49 \
((uint32_t)0x01000000) /*!< N32G45X devices: \
Write protection of page 48 to 49 */
#define FLASH_WRP_Pages50to51 \
((uint32_t)0x02000000) /*!< N32G45X devices: \
Write protection of page 50 to 51 */
#define FLASH_WRP_Pages52to53 \
((uint32_t)0x04000000) /*!< N32G45X devices: \
Write protection of page 52 to 53 */
#define FLASH_WRP_Pages54to55 \
((uint32_t)0x08000000) /*!< N32G45X devices: \
Write protection of page 54 to 55 */
#define FLASH_WRP_Pages56to57 \
((uint32_t)0x10000000) /*!< N32G45X devices: \
Write protection of page 56 to 57 */
#define FLASH_WRP_Pages58to59 \
((uint32_t)0x20000000) /*!< N32G45X devices: \
Write protection of page 58 to 59 */
#define FLASH_WRP_Pages60to61 \
((uint32_t)0x40000000) /*!< N32G45X devices: \
Write protection of page 60 to 61 */
#define FLASH_WRP_Pages62to127 \
((uint32_t)0x80000000) /*!< N32G45X - 256KB devices: Write protection of page 62 to 127 */
#define FLASH_WRP_Pages62to255 \
((uint32_t)0x80000000) /*!< N32G45X - 512KB devices: Write protection of page 62 to 255 */
#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
#define IS_FLASH_WRP_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
/**
* @}
*/
/** @addtogroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @addtogroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP0_NORST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
#define OB_STOP0_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST))
/**
* @}
*/
/** @addtogroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NORST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
/** @addtogroup FLASH_Interrupts
* @{
*/
#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */
#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */
#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @addtogroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFFFFF83) == 0x00) && (FLAG != 0x00))
#define IS_FLASH_GET_FLAG(FLAG) \
(((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \
|| ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \
|| ((FLAG) == FLASH_FLAG_OBERR))
/**
* @}
*/
/** @addtogroup FLASH_STS_CLRFLAG
* @{
*/
#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR)
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/*------------ Functions used for N32G45X devices -----*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
void FLASH_iCacheRST(void);
void FLASH_iCacheCmd(uint32_t FLASH_iCache);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
FLASH_STS FLASH_MassErase(void);
FLASH_STS FLASH_EraseOB(void);
FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void);
FLASH_STS FLASH_ConfigUserOB(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOB(void);
uint32_t FLASH_GetWriteProtectionOB(void);
FlagStatus FLASH_GetReadOutProtectionSTS(void);
FlagStatus FLASH_GetReadOutProtectionL2STS(void);
FlagStatus FLASH_GetPrefetchBufSTS(void);
void FLASH_SetSMPSELStatus(FLASH_SMPSEL FLASH_smpsel);
FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_STS FLASH_GetSTS(void);
FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_FLASH_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_gpio.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_GPIO_H__
#define __N32G45X_GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @addtogroup GPIO_Exported_Types
* @{
*/
#define IS_GPIO_ALL_PERIPH(PERIPH) \
(((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) \
|| ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG))
/**
* @brief Output Maximum frequency selection
*/
typedef enum
{
GPIO_INPUT = 0,
GPIO_Speed_2MHz = 1,
GPIO_Speed_10MHz,
GPIO_Speed_50MHz
} GPIO_SpeedType;
#define IS_GPIO_SPEED(SPEED) \
(((SPEED) == GPIO_INPUT) || ((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) \
|| ((SPEED) == GPIO_Speed_50MHz))
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
} GPIO_ModeType;
#define IS_GPIO_MODE(MODE) \
(((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) \
|| ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) \
|| ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIO_SpeedType GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_SpeedType */
GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_ModeType */
} GPIO_InitType;
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET
} Bit_OperateType;
#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
/**
* @}
*/
/** @addtogroup GPIO_Exported_Constants
* @{
*/
/** @addtogroup GPIO_pins_define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GET_GPIO_PIN(PIN) \
(((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \
|| ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \
|| ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \
|| ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
/**
* @}
*/
/** @addtogroup GPIO_Remap_define
* @{
*/
#define GPIO_RMP_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
#define GPIO_RMP_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
#define GPIO_RMP_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
#define GPIO_RMP_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
#define GPIO_PART_RMP_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
#define GPIO_ALL_RMP_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
#define GPIO_PART1_RMP_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
#define GPIO_PART2_RMP_TIM1 ((uint32_t)0x00160080) /*!< TIM1 Partial Alternate Function mapping */
#define GPIO_ALL_RMP_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
#define GPIO_PART2_RMP_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
#define GPIO_ALL_RMP_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
#define GPIO_PART1_RMP_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
#define GPIO_ALL_RMP_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
#define GPIO_RMP_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
#define GPIO_RMP1_CAN1 ((uint32_t)0x001D2000) /*!< CAN1 Alternate Function mapping */
#define GPIO_RMP2_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
#define GPIO_RMP3_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
#define GPIO_RMP_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
#define GPIO_RMP_TIM5CH4 ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_RMP_ADC1_ETRI ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
#define GPIO_RMP_ADC1_ETRR ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
#define GPIO_RMP_ADC2_ETRI ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
#define GPIO_RMP_ADC2_ETRR ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
#define GPIO_RMP_MII_RMII_SEL ((uint32_t)0x00200080) /*!< MII_RMII_SEL remapping */
#define GPIO_RMP_SW_JTAG_NO_NJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_RMP_SW_JTAG_SW_ENABLE ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_RMP_SW_JTAG_DISABLE ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
/* AFIO_RMP_CFG2 */
#define GPIO_Remap_XFMC_NADV ((uint32_t)0x80000400) /*!< XFMC_NADV Alternate Function mapping */
/* AFIO_RMP_CFG3 */
#define GPIO_RMP_SDIO ((uint32_t)0x40000001) /*!< SDIO Alternate Function mapping */
#define GPIO_RMP1_CAN2 ((uint32_t)0x40110002) /*!< CAN2 Alternate Function mapping */
#define GPIO_RMP3_CAN2 ((uint32_t)0x40110006) /*!< CAN2 Alternate Function mapping */
#define GPIO_RMP1_QSPI ((uint32_t)0x40140020) /*!< QSPI Alternate Function mapping */
#define GPIO_RMP3_QSPI ((uint32_t)0x40140030) /*!< QSPI Alternate Function mapping */
#define GPIO_RMP1_I2C2 ((uint32_t)0x40160040) /*!< I2C2 Alternate Function mapping */
#define GPIO_RMP3_I2C2 ((uint32_t)0x401600C0) /*!< I2C2 Alternate Function mapping */
#define GPIO_RMP2_I2C3 ((uint32_t)0x40180200) /*!< I2C3 Alternate Function mapping */
#define GPIO_RMP3_I2C3 ((uint32_t)0x40180300) /*!< I2C3 Alternate Function mapping */
#define GPIO_RMP1_I2C4 ((uint32_t)0x401A0400) /*!< I2C4 Alternate Function mapping */
#define GPIO_RMP3_I2C4 ((uint32_t)0x401A0C00) /*!< I2C4 Alternate Function mapping */
#define GPIO_RMP1_SPI2 ((uint32_t)0x401C1000) /*!< SPI2 Alternate Function mapping */
#define GPIO_RMP2_SPI2 ((uint32_t)0x401C3000) /*!< SPI2 Alternate Function mapping */
#define GPIO_RMP1_SPI3 ((uint32_t)0x401E4000) /*!< SPI3 Alternate Function mapping */
#define GPIO_RMP2_SPI3 ((uint32_t)0x401E8000) /*!< SPI3 Alternate Function mapping */
#define GPIO_RMP3_SPI3 ((uint32_t)0x401EC000) /*!< SPI3 Alternate Function mapping */
#define GPIO_RMP1_ETH ((uint32_t)0x40300001) /*!< ETH Alternate Function mapping */
#define GPIO_RMP2_ETH ((uint32_t)0x40300002) /*!< ETH Alternate Function mapping */
#define GPIO_RMP3_ETH ((uint32_t)0x40300003) /*!< ETH Alternate Function mapping */
#define GPIO_RMP1_SPI1 ((uint32_t)0x41200000) /*!< SPI1 Alternate Function mapping */
#define GPIO_RMP2_SPI1 ((uint32_t)0x41200004) /*!< SPI1 Alternate Function mapping */
#define GPIO_RMP3_SPI1 ((uint32_t)0x43200004) /*!< SPI1 Alternate Function mapping */
#define GPIO_RMP1_USART2 ((uint32_t)0x44200000) /*!< USART2 Alternate Function mapping */
#define GPIO_RMP2_USART2 ((uint32_t)0x44200008) /*!< USART2 Alternate Function mapping */
#define GPIO_RMP3_USART2 ((uint32_t)0x46200008) /*!< USART2 Alternate Function mapping */
#define GPIO_RMP1_UART4 ((uint32_t)0x40340010) /*!< UART4 Alternate Function mapping */
#define GPIO_RMP2_UART4 ((uint32_t)0x40340020) /*!< UART4 Alternate Function mapping */
#define GPIO_RMP3_UART4 ((uint32_t)0x40340030) /*!< UART4 Alternate Function mapping */
#define GPIO_RMP1_UART5 ((uint32_t)0x40360040) /*!< UART5 Alternate Function mapping */
#define GPIO_RMP2_UART5 ((uint32_t)0x40360080) /*!< UART5 Alternate Function mapping */
#define GPIO_RMP3_UART5 ((uint32_t)0x403600C0) /*!< UART5 Alternate Function mapping */
#define GPIO_RMP2_UART6 ((uint32_t)0x40380200) /*!< UART6 Alternate Function mapping */
#define GPIO_RMP3_UART6 ((uint32_t)0x40380300) /*!< UART6 Alternate Function mapping */
#define GPIO_RMP1_UART7 ((uint32_t)0x403A0400) /*!< UART7 Alternate Function mapping */
#define GPIO_RMP3_UART7 ((uint32_t)0x403A0C00) /*!< UART7 Alternate Function mapping */
#define GPIO_RMP1_XFMC ((uint32_t)0x403C1000) /*!< XFMC Alternate Function mapping */
#define GPIO_RMP3_XFMC ((uint32_t)0x403C3000) /*!< XFMC Alternate Function mapping */
#define GPIO_RMP1_TIM8 ((uint32_t)0x403E4000) /*!< TIM8 Alternate Function mapping */
#define GPIO_RMP3_TIM8 ((uint32_t)0x403EC000) /*!< TIM8 Alternate Function mapping */
/* AFIO_RMP_CFG4 */
#define GPIO_RMP1_COMP1 ((uint32_t)0x20100001) /*!< COMP1 Alternate Function mapping */
#define GPIO_RMP2_COMP1 ((uint32_t)0x20100002) /*!< COMP1 Alternate Function mapping */
#define GPIO_RMP3_COMP1 ((uint32_t)0x20100003) /*!< COMP1 Alternate Function mapping */
#define GPIO_RMP1_COMP2 ((uint32_t)0x20120004) /*!< COMP2 Alternate Function mapping */
#define GPIO_RMP2_COMP2 ((uint32_t)0x20120008) /*!< COMP2 Alternate Function mapping */
#define GPIO_RMP3_COMP2 ((uint32_t)0x2012000C) /*!< COMP2 Alternate Function mapping */
#define GPIO_RMP1_COMP3 ((uint32_t)0x20140010) /*!< COMP3 Alternate Function mapping */
#define GPIO_RMP3_COMP3 ((uint32_t)0x20140030) /*!< COMP3 Alternate Function mapping */
#define GPIO_RMP1_COMP4 ((uint32_t)0x20160040) /*!< COMP4 Alternate Function mapping */
#define GPIO_RMP3_COMP4 ((uint32_t)0x201600C0) /*!< COMP4 Alternate Function mapping */
#define GPIO_RMP1_COMP5 ((uint32_t)0x20180100) /*!< COMP5 Alternate Function mapping */
#define GPIO_RMP2_COMP5 ((uint32_t)0x20180200) /*!< COMP5 Alternate Function mapping */
#define GPIO_RMP3_COMP5 ((uint32_t)0x20180300) /*!< COMP5 Alternate Function mapping */
#define GPIO_RMP1_COMP6 ((uint32_t)0x201A0400) /*!< COMP6 Alternate Function mapping */
#define GPIO_RMP3_COMP6 ((uint32_t)0x201A0C00) /*!< COMP6 Alternate Function mapping */
#define GPIO_RMP_COMP7 ((uint32_t)0x20001000) /*!< COMP7 Alternate Function mapping */
#define GPIO_RMP_ADC3_ETRI ((uint32_t)0x20004000) /*!< ADC3_ETRGINJ Alternate Function mapping */
#define GPIO_RMP_ADC3_ETRR ((uint32_t)0x20008000) /*!< ADC3_ETRGREG Alternate Function mapping */
#define GPIO_RMP_ADC4_ETRI ((uint32_t)0x20200001) /*!< ADC4_ETRGINJ Alternate Function mapping */
#define GPIO_RMP_ADC4_ETRR ((uint32_t)0x20200002) /*!< ADC4_ETRGREG Alternate Function mapping */
#define GPIO_RMP_TSC_OUT_CTRL ((uint32_t)0x20200004) /*!< TSC_OUT_CTRL Alternate Function mapping */
#define GPIO_RMP_QSPI_XIP_EN ((uint32_t)0x20200008) /*!< QSPI_XIP_EN Alternate Function mapping */
#define GPIO_RMP1_DVP ((uint32_t)0x20340010) /*!< DVP Alternate Function mapping */
#define GPIO_RMP3_DVP ((uint32_t)0x20340030) /*!< DVP Alternate Function mapping */
#define GPIO_Remap_SPI1_NSS ((uint32_t)0x20200040) /*!< SPI1 NSS Alternate Function mapping */
#define GPIO_Remap_SPI2_NSS ((uint32_t)0x20200080) /*!< SPI2 NSS Alternate Function mapping */
#define GPIO_Remap_SPI3_NSS ((uint32_t)0x20200100) /*!< SPI3 NSS Alternate Function mapping */
#define GPIO_Remap_QSPI_MISO ((uint32_t)0x20200200) /*!< QSPI MISO Alternate Function mapping */
/* AFIO_RMP_CFG5 */
#define GPIO_Remap_DET_EN_EGB4 ((uint32_t)0x10200080) /*!< EGB4 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGB3 ((uint32_t)0x10200040) /*!< EGB4 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGB2 ((uint32_t)0x10200020) /*!< EGB4 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGB1 ((uint32_t)0x10200010) /*!< EGB4 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGBN4 ((uint32_t)0x10200008) /*!< EGBN4 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGBN3 ((uint32_t)0x10200004) /*!< EGBN3 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGBN2 ((uint32_t)0x10200002) /*!< EGBN2 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_EGBN1 ((uint32_t)0x10200001) /*!< EGBN1 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_ECLAMP4 ((uint32_t)0x10008000) /*!< ECLAMP4 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_ECLAMP3 ((uint32_t)0x10004000) /*!< ECLAMP3 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_ECLAMP2 ((uint32_t)0x10002000) /*!< ECLAMP2 Detect Alternate Function mapping*/
#define GPIO_Remap_DET_EN_ECLAMP1 ((uint32_t)0x10001000) /*!< ECLAMP1 Detect Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGB4 ((uint32_t)0x10000800) /*!< EGB4 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGB3 ((uint32_t)0x10000400) /*!< EGB3 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGB2 ((uint32_t)0x10000200) /*!< EGB2 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGB1 ((uint32_t)0x10000100) /*!< EGB1 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGBN4 ((uint32_t)0x10000080) /*!< EGBN4 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGBN3 ((uint32_t)0x10000040) /*!< EGBN3 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGBN2 ((uint32_t)0x10000020) /*!< EGBN2 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_EGBN1 ((uint32_t)0x10000010) /*!< EGBN1 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_ECLAMP4 ((uint32_t)0x10000008) /*!< ECLAMP4 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_ECLAMP3 ((uint32_t)0x10000004) /*!< ECLAMP3 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_ECLAMP2 ((uint32_t)0x10000002) /*!< ECLAMP2 Reset Alternate Function mapping*/
#define GPIO_Remap_RST_EN_ECLAMP1 ((uint32_t)0x10000001) /*!< ECLAMP1 Reset Alternate Function mapping*/
#define IS_GPIO_REMAP(REMAP) \
(((REMAP) == GPIO_RMP_SPI1) || ((REMAP) == GPIO_RMP_I2C1) || ((REMAP) == GPIO_RMP_USART1) \
|| ((REMAP) == GPIO_RMP_USART2) || ((REMAP) == GPIO_PART_RMP_USART3) || ((REMAP) == GPIO_ALL_RMP_USART3) \
|| ((REMAP) == GPIO_PART1_RMP_TIM1) || ((REMAP) == GPIO_ALL_RMP_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) \
|| ((REMAP) == GPIO_PART2_RMP_TIM2) || ((REMAP) == GPIO_ALL_RMP_TIM2) || ((REMAP) == GPIO_PART1_RMP_TIM3) \
|| ((REMAP) == GPIO_ALL_RMP_TIM3) || ((REMAP) == GPIO_RMP_TIM4) || ((REMAP) == GPIO_RMP1_CAN1) \
|| ((REMAP) == GPIO_RMP2_CAN1) || ((REMAP) == GPIO_RMP3_CAN1) || ((REMAP) == GPIO_RMP_PD01) || ((REMAP) == GPIO_RMP_TIM5CH4) \
|| ((REMAP) == GPIO_RMP_ADC1_ETRI) || ((REMAP) == GPIO_RMP_ADC1_ETRR) || ((REMAP) == GPIO_RMP_ADC2_ETRI) \
|| ((REMAP) == GPIO_RMP_ADC2_ETRR) || ((REMAP) == GPIO_RMP_SW_JTAG_NO_NJTRST) \
|| ((REMAP) == GPIO_RMP_SW_JTAG_SW_ENABLE) || ((REMAP) == GPIO_RMP_SW_JTAG_DISABLE) \
|| ((REMAP) == GPIO_Remap_XFMC_NADV) || ((REMAP) == GPIO_RMP_SDIO) || ((REMAP) == GPIO_RMP1_CAN2) \
|| ((REMAP) == GPIO_RMP3_CAN2) || ((REMAP) == GPIO_RMP1_QSPI) || ((REMAP) == GPIO_RMP3_QSPI) \
|| ((REMAP) == GPIO_RMP1_I2C2) || ((REMAP) == GPIO_RMP3_I2C2) || ((REMAP) == GPIO_RMP2_I2C3) \
|| ((REMAP) == GPIO_RMP3_I2C3) || ((REMAP) == GPIO_RMP1_I2C4) || ((REMAP) == GPIO_RMP3_I2C4) \
|| ((REMAP) == GPIO_RMP1_SPI2) || ((REMAP) == GPIO_RMP2_SPI2) || ((REMAP) == GPIO_RMP1_SPI3) \
|| ((REMAP) == GPIO_RMP2_SPI3) || ((REMAP) == GPIO_RMP3_SPI3) || ((REMAP) == GPIO_RMP1_ETH) \
|| ((REMAP) == GPIO_RMP2_ETH) || ((REMAP) == GPIO_RMP3_ETH) || ((REMAP) == GPIO_RMP1_SPI1) \
|| ((REMAP) == GPIO_RMP2_SPI1) || ((REMAP) == GPIO_RMP3_SPI1) || ((REMAP) == GPIO_RMP1_USART2) \
|| ((REMAP) == GPIO_RMP2_USART2) || ((REMAP) == GPIO_RMP3_USART2) || ((REMAP) == GPIO_RMP1_UART4) \
|| ((REMAP) == GPIO_RMP2_UART4) || ((REMAP) == GPIO_RMP3_UART4) || ((REMAP) == GPIO_RMP1_UART5) \
|| ((REMAP) == GPIO_RMP2_UART5) || ((REMAP) == GPIO_RMP3_UART5) || ((REMAP) == GPIO_RMP2_UART6) \
|| ((REMAP) == GPIO_RMP3_UART6) || ((REMAP) == GPIO_RMP1_UART7) || ((REMAP) == GPIO_RMP3_UART7) \
|| ((REMAP) == GPIO_RMP1_XFMC) || ((REMAP) == GPIO_RMP3_XFMC) || ((REMAP) == GPIO_RMP1_TIM8) \
|| ((REMAP) == GPIO_RMP3_TIM8) || ((REMAP) == GPIO_RMP1_COMP1) || ((REMAP) == GPIO_RMP2_COMP1) \
|| ((REMAP) == GPIO_RMP3_COMP1) || ((REMAP) == GPIO_RMP1_COMP2) || ((REMAP) == GPIO_RMP2_COMP2) \
|| ((REMAP) == GPIO_RMP3_COMP2) || ((REMAP) == GPIO_RMP1_COMP3) || ((REMAP) == GPIO_RMP3_COMP3) \
|| ((REMAP) == GPIO_RMP1_COMP4) || ((REMAP) == GPIO_RMP3_COMP4) || ((REMAP) == GPIO_RMP1_COMP5) \
|| ((REMAP) == GPIO_RMP2_COMP5) || ((REMAP) == GPIO_RMP3_COMP5) || ((REMAP) == GPIO_RMP1_COMP6) \
|| ((REMAP) == GPIO_RMP3_COMP6) || ((REMAP) == GPIO_RMP_COMP7) || ((REMAP) == GPIO_RMP_ADC3_ETRI) \
|| ((REMAP) == GPIO_RMP_ADC3_ETRR) || ((REMAP) == GPIO_RMP_ADC4_ETRI) || ((REMAP) == GPIO_RMP_ADC4_ETRR) \
|| ((REMAP) == GPIO_RMP_TSC_OUT_CTRL) || ((REMAP) == GPIO_RMP_QSPI_XIP_EN) || ((REMAP) == GPIO_RMP1_DVP) \
|| ((REMAP) == GPIO_RMP3_DVP) || ((REMAP) == GPIO_Remap_SPI1_NSS) || ((REMAP) == GPIO_Remap_SPI2_NSS) \
|| ((REMAP) == GPIO_Remap_SPI3_NSS) || ((REMAP) == GPIO_Remap_QSPI_MISO) || ((REMAP) == GPIO_RMP_MII_RMII_SEL) \
|| ((REMAP) == GPIO_PART2_RMP_TIM1) || ((REMAP) == GPIO_Remap_DET_EN_EGB4) || ((REMAP) == GPIO_Remap_DET_EN_EGB3) \
|| ((REMAP) == GPIO_Remap_DET_EN_EGB2) || ((REMAP) == GPIO_Remap_DET_EN_EGB1) \
|| ((REMAP) == GPIO_Remap_DET_EN_EGBN4) || ((REMAP) == GPIO_Remap_DET_EN_EGBN3) \
|| ((REMAP) == GPIO_Remap_DET_EN_EGBN2) || ((REMAP) == GPIO_Remap_DET_EN_EGBN1) \
|| ((REMAP) == GPIO_Remap_DET_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP3) \
|| ((REMAP) == GPIO_Remap_DET_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP1) \
|| ((REMAP) == GPIO_Remap_RST_EN_EGB4) || ((REMAP) == GPIO_Remap_RST_EN_EGB3) \
|| ((REMAP) == GPIO_Remap_RST_EN_EGB2) || ((REMAP) == GPIO_Remap_RST_EN_EGB1) \
|| ((REMAP) == GPIO_Remap_RST_EN_EGBN4) || ((REMAP) == GPIO_Remap_RST_EN_EGBN3) \
|| ((REMAP) == GPIO_Remap_RST_EN_EGBN2) || ((REMAP) == GPIO_Remap_RST_EN_EGBN1) \
|| ((REMAP) == GPIO_Remap_RST_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP3) \
|| ((REMAP) == GPIO_Remap_RST_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP1))
/**
* @}
*/
/** @addtogroup GPIO_Port_Sources
* @{
*/
#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
#define GPIOE_PORT_SOURCE ((uint8_t)0x04)
#define GPIOF_PORT_SOURCE ((uint8_t)0x05)
#define GPIOG_PORT_SOURCE ((uint8_t)0x06)
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \
(((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
|| ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE))
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \
(((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
|| ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE) \
|| ((PORTSOURCE) == GPIOF_PORT_SOURCE) || ((PORTSOURCE) == GPIOG_PORT_SOURCE))
/**
* @}
*/
/** @addtogroup GPIO_Pin_sources
* @{
*/
#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) \
(((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \
|| ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \
|| ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \
|| ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \
|| ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
|| ((PINSOURCE) == GPIO_PIN_SOURCE15))
/**
* @}
*/
/** @addtogroup Ethernet_Media_Interface
* @{
*/
#define GPIO_ETH_MII_CFG ((uint32_t)0x00000000)
#define GPIO_ETH_RMII_CFG ((uint32_t)0x00800000)
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MII_CFG) || ((INTERFACE) == GPIO_ETH_RMII_CFG))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup GPIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
void GPIO_DeInit(GPIO_Module* GPIOx);
void GPIO_AFIOInitDefault(void);
void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
void GPIO_CtrlEventOutput(FunctionalState Cmd);
void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd);
void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
void GPIO_ETH_ConfigMediaInterface(uint32_t ETH_ConfigSel);
void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_GPIO_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_iwdg.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_IWDG_H__
#define __N32G45X_IWDG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/** @addtogroup IWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup IWDG_Exported_Constants
* @{
*/
/** @addtogroup IWDG_WriteAccess
* @{
*/
#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
/**
* @}
*/
/** @addtogroup IWDG_prescaler
* @{
*/
#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
(((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
|| ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
|| ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
|| ((PRESCALER) == IWDG_PRESCALER_DIV256))
/**
* @}
*/
/** @addtogroup IWDG_Flag
* @{
*/
#define IWDG_PVU_FLAG ((uint16_t)0x0001)
#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup IWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
void IWDG_CntReload(uint16_t Reload);
void IWDG_ReloadKey(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_IWDG_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

213
bsp/n32g452xx/Libraries/n32g45x_std_periph_driver/inc/n32g45x_opamp.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_opamp.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_OPAMPMP_H__
#define __N32G45X_OPAMPMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
#include <stdbool.h>
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/** @addtogroup OPAMP_Exported_Constants
* @{
*/
typedef enum
{
OPAMP1 = 0,
OPAMP2 = 4,
OPAMP3 = 8,
OPAMP4 = 12,
} OPAMPX;
// OPAMP_CS
typedef enum
{
OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19),
OPAMP1_CS_VPSSEL_PA3 = (0x01L << 19),
OPAMP1_CS_VPSSEL_DAC2_PA5 = (0x02L << 19),
OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19),
OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19),
OPAMP2_CS_VPSSEL_PB0 = (0x01L << 19),
OPAMP2_CS_VPSSEL_PE8 = (0x02L << 19),
OPAMP3_CS_VPSSEL_PC9 = (0x00L << 19),
OPAMP3_CS_VPSSEL_PA1 = (0x01L << 19),
OPAMP3_CS_VPSSEL_DAC2_PA5 = (0x02L << 19),
OPAMP3_CS_VPSSEL_PC3 = (0x03L << 19),
OPAMP4_CS_VPSSEL_PC3 = (0x00L << 19),
OPAMP4_CS_VPSSEL_DAC1_PA4 = (0x01L << 19),
OPAMP4_CS_VPSSEL_PC5 = (0x02L << 19),
} OPAMP_CS_VPSSEL;
typedef enum
{
OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17),
OPAMP1_CS_VMSSEL_PA2 = (0x01L << 17),
OPAMPx_CS_VMSSEL_FLOAT = (0x03L << 17),
OPAMP2_CS_VMSSEL_PA2 = (0x00L << 17),
OPAMP2_CS_VMSSEL_PA5 = (0x01L << 17),
OPAMP3_CS_VMSSEL_PC4 = (0x00L << 17),
OPAMP3_CS_VMSSEL_PB10 = (0x01L << 17),
OPAMP4_CS_VMSSEL_PB10 = (0x00L << 17),
OPAMP4_CS_VMSSEL_PC9 = (0x01L << 17),
OPAMP4_CS_VMSSEL_PD8 = (0x02L << 17),
} OPAMP_CS_VMSSEL;
typedef enum
{
OPAMP1_CS_VPSEL_PA1 = (0x00L << 8),
OPAMP1_CS_VPSEL_PA3 = (0x01L << 8),
OPAMP1_CS_VPSEL_DAC2_PA5 = (0x02L << 8),
OPAMP1_CS_VPSEL_PA7 = (0x03L << 8),
OPAMP2_CS_VPSEL_PA7 = (0x00L << 8),
OPAMP2_CS_VPSEL_PB0 = (0x01L << 8),
OPAMP2_CS_VPSEL_PE8 = (0x02L << 8),
OPAMP3_CS_VPSEL_PC9 = (0x00L << 8),
OPAMP3_CS_VPSEL_PA1 = (0x01L << 8),
OPAMP3_CS_VPSEL_DAC2_PA5 = (0x02L << 8),
OPAMP3_CS_VPSEL_PC3 = (0x03L << 8),
OPAMP4_CS_VPSEL_PC3 = (0x00L << 8),
OPAMP4_CS_VPSEL_DAC1_PA4 = (0x01L << 8),
OPAMP4_CS_VPSEL_PC5 = (0x02L << 8),
} OPAMP_CS_VPSEL;
typedef enum
{
OPAMP1_CS_VMSEL_PA3 = (0x00L << 6),
OPAMP1_CS_VMSEL_PA2 = (0x01L << 6),
OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6),
OPAMP2_CS_VMSEL_PA2 = (0x00L << 6),
OPAMP2_CS_VMSEL_PA5 = (0x01L << 6),
OPAMP3_CS_VMSEL_PC4 = (0x00L << 6),
OPAMP3_CS_VMSEL_PB10 = (0x01L << 6),
OPAMP4_CS_VMSEL_PB10 = (0x00L << 6),
OPAMP4_CS_VMSEL_PC9 = (0x01L << 6),
OPAMP4_CS_VMSEL_PD8 = (0x02L << 6),
} OPAMP_CS_VMSEL;
typedef enum
{
OPAMP_CS_PGA_GAIN_2 = (0x00 << 3),
OPAMP_CS_PGA_GAIN_4 = (0x01 << 3),
OPAMP_CS_PGA_GAIN_8 = (0x02 << 3),
OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
} OPAMP_CS_PGA_GAIN;
typedef enum
{
OPAMP_CS_EXT_OPAMP = (0x00 << 1),
OPAMP_CS_PGA_EN = (0x02 << 1),
OPAMP_CS_FOLLOW = (0x03 << 1),
} OPAMP_CS_MOD;
// bit mask
#define OPAMP_CS_EN_MASK (0x01L << 0)
#define OPAMP_CS_MOD_MASK (0x03L << 1)
#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3)
#define OPAMP_CS_VMSEL_MASK (0x03L << 6)
#define OPAMP_CS_VPSEL_MASK (0x07L << 8)
#define OPAMP_CS_CALON_MASK (0x01L << 11)
#define OPAMP_CS_TSTREF_MASK (0x01L << 13)
#define OPAMP_CS_CALOUT_MASK (0x01L << 14)
#define OPAMP_CS_RANGE_MASK (0x01L << 15)
#define OPAMP_CS_TCMEN_MASK (0x01L << 16)
#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
/** @addtogroup OPAMP_LOCK
* @{
*/
#define OPAMP_LOCK_1 0x01L
#define OPAMP_LOCK_2 0x02L
#define OPAMP_LOCK_3 0x04L
#define OPAMP_LOCK_4 0x08L
/**
* @}
*/
/**
* @}
*/
/**
* @brief OPAMP Init structure definition
*/
typedef struct
{
FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
} OPAMP_InitType;
/** @addtogroup OPAMP_Exported_Functions
* @{
*/
void OPAMP_DeInit(void);
void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__N32G45X_ADC_H */
/**
* @}
*/
/**
* @}
*/

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bsp/n32g452xx/Libraries/n32g45x_std_periph_driver/inc/n32g45x_pwr.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_pwr.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_PWR_H__
#define __N32G45X_PWR_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @addtogroup PWR_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup PWR_Exported_Constants
* @{
*/
/** @addtogroup PVD_detection_level
* @{
*/
#define PWR_PVDRANGRE_2V2 ((uint32_t)0x00000000)
#define PWR_PVDRANGRE_2V3 ((uint32_t)0x00000020)
#define PWR_PVDRANGRE_2V4 ((uint32_t)0x00000040)
#define PWR_PVDRANGRE_2V5 ((uint32_t)0x00000060)
#define PWR_PVDRANGRE_2V6 ((uint32_t)0x00000080)
#define PWR_PVDRANGRE_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDRANGRE_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDRANGRE_2V9 ((uint32_t)0x000000E0)
#define PWR_PVDRANGE_1V78 ((uint32_t)0x00000200)
#define PWR_PVDRANGE_1V88 ((uint32_t)0x00000220)
#define PWR_PVDRANGE_1V98 ((uint32_t)0x00000240)
#define PWR_PVDRANGE_2V08 ((uint32_t)0x00000260)
#define PWR_PVDRANGE_3V06 ((uint32_t)0x00000280)
#define PWR_PVDRANGE_3V24 ((uint32_t)0x000002A0)
#define PWR_PVDRANGE_3V42 ((uint32_t)0x000002C0)
#define PWR_PVDRANGE_3V60 ((uint32_t)0x000002E0)
#define IS_PWR_PVD_LEVEL(LEVEL) \
(((LEVEL) == PWR_PVDRANGRE_2V2) || ((LEVEL) == PWR_PVDRANGRE_2V3) || ((LEVEL) == PWR_PVDRANGRE_2V4) \
|| ((LEVEL) == PWR_PVDRANGRE_2V5) || ((LEVEL) == PWR_PVDRANGRE_2V6) || ((LEVEL) == PWR_PVDRANGRE_2V7) \
|| ((LEVEL) == PWR_PVDRANGRE_2V8) || ((LEVEL) == PWR_PVDRANGRE_2V9) || ((LEVEL) == PWR_PVDRANGE_1V78) \
|| ((LEVEL) == PWR_PVDRANGE_1V88) || ((LEVEL) == PWR_PVDRANGE_1V98) || ((LEVEL) == PWR_PVDRANGE_2V08) \
|| ((LEVEL) == PWR_PVDRANGE_3V06) || ((LEVEL) == PWR_PVDRANGE_3V24) || ((LEVEL) == PWR_PVDRANGE_3V42) \
|| ((LEVEL) == PWR_PVDRANGE_3V60))
/**
* @}
*/
/** @addtogroup Regulator_state_is_STOP_mode
* @{
*/
#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
/**
* @}
*/
/** @addtogroup STOP_mode_entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
/** @addtogroup PWR_Flag
* @{
*/
#define PWR_WU_FLAG ((uint32_t)0x00000001)
#define PWR_SB_FLAG ((uint32_t)0x00000002)
#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
#define PWR_VBATF_FLAG ((uint32_t)0x00000008)
#define IS_PWR_GET_FLAG(FLAG) \
(((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_PVDO_FLAG) || ((FLAG) == PWR_VBATF_FLAG))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_VBATF_FLAG))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccessEnable(FunctionalState Cmd);
void PWR_PvdEnable(FunctionalState Cmd);
void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinEnable(FunctionalState Cmd);
void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry);
void PWR_EnterStandbyState(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_PWR_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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bsp/n32g452xx/Libraries/n32g45x_std_periph_driver/inc/n32g45x_qspi.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_qspi.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_QSPI_H__
#define __N32G45X_QSPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
#include <stdbool.h>
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup QSPI
* @brief QSPI driver modules
* @{
*/
////////////////////////////////////////////////////////////////////////////////////////////////////
typedef enum
{
STANDARD_SPI_FORMAT_SEL = 0,
DUAL_SPI_FORMAT_SEL,
QUAD_SPI_FORMAT_SEL,
XIP_SPI_FORMAT_SEL
} QSPI_FORMAT_SEL;
typedef enum
{
TX_AND_RX = 0,
TX_ONLY,
RX_ONLY
} QSPI_DATA_DIR;
typedef enum
{
QSPI_NSS_PORTA_SEL,
QSPI_NSS_PORTC_SEL,
QSPI_NSS_PORTF_SEL
} QSPI_NSS_PORT_SEL;
typedef enum
{
QSPI_NULL = 0,
QSPI_SUCCESS,
} QSPI_STATUS;
////////////////////////////////////////////////////////////////////////////////////////////////////
typedef struct
{
/*QSPI_CTRL0*/
uint32_t DFS;
uint32_t FRF;
uint32_t SCPH;
uint32_t SCPOL;
uint32_t TMOD;
uint32_t SSTE;
uint32_t CFS;
uint32_t SPI_FRF;
/*QSPI_CTRL1*/
uint32_t NDF;
/*QSPI_MW_CTRL*/
uint32_t MWMOD;
uint32_t MC_DIR;
uint32_t MHS_EN;
/*QSPI_BAUD*/
uint32_t CLK_DIV;
/*QSPI_TXFT*/
uint32_t TXFT;
/*QSPI_RXFT*/
uint32_t RXFT;
/*QSPI_TXFN*/
uint32_t TXFN;
/*QSPI_RXFN*/
uint32_t RXFN;
/*QSPI_RS_DELAY*/
uint32_t SDCN;
uint32_t SES;
/*QSPI_ENH_CTRL0*/
uint32_t ENHANCED_TRANS_TYPE;
uint32_t ENHANCED_ADDR_LEN;
uint32_t ENHANCED_MD_BIT_EN;
uint32_t ENHANCED_INST_L;
uint32_t ENHANCED_WAIT_CYCLES;
uint32_t ENHANCED_SPI_DDR_EN;
uint32_t ENHANCED_INST_DDR_EN;
uint32_t ENHANCED_XIP_DFS_HC;
uint32_t ENHANCED_XIP_INST_EN;
uint32_t ENHANCED_XIP_CT_EN;
uint32_t ENHANCED_XIP_MBL;
uint32_t ENHANCED_CLK_STRETCH_EN;
/*QSPI_DDR_TXDE*/
uint32_t TXDE;
/*QSPI_XIP_MODE*/
uint32_t XIP_MD_BITS;
/*QSPI_XIP_INCR_TOC*/
uint32_t ITOC;
/*QSPI_XIP_WRAP_TOC*/
uint32_t WTOC;
/*QSPI_XIP_CTRL*/
uint32_t XIP_FRF;
uint32_t XIP_TRANS_TYPE;
uint32_t XIP_ADDR_LEN;
uint32_t XIP_INST_L;
uint32_t XIP_MD_BITS_EN;
uint32_t XIP_WAIT_CYCLES;
uint32_t XIP_DFS_HC;
uint32_t XIP_DDR_EN;
uint32_t XIP_INST_DDR_EN;
uint32_t XIP_INST_EN;
uint32_t XIP_CT_EN;
uint32_t XIP_MBL;
/*QSPI_XIP_TOUT*/
uint32_t XTOUT;
} QSPI_InitType;
////////////////////////////////////////////////////////////////////////////////////////////////////
#define QSPI_TIME_OUT_CNT 200
#define IS_QSPI_SPI_FRF(SPI_FRF) \
(((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
#define IS_QSPI_CFS(CFS) ((((CFS) >= QSPI_CTRL0_CFS_2_BIT) && ((CFS) <= QSPI_CTRL0_CFS_16_BIT)) || ((CFS) == QSPI_CTRL0_CFS_1_BIT))
#define IS_QSPI_SSTE(SSTE) (((SSTE) == QSPI_CTRL0_SSTE_EN) || ((SSTE) == 0))
#define IS_QSPI_TMOD(TMOD) \
(((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ))
#define IS_QSPI_SCPOL(SCPOL) (((SCPOL) == QSPI_CTRL0_SCPOL_LOW) || ((SCPOL) == QSPI_CTRL0_SCPOL_HIGH))
#define IS_QSPI_SCPH(SCPH) (((SCPH) == QSPI_CTRL0_SCPH_FIRST_EDGE) || ((SCPH) == QSPI_CTRL0_SCPH_SECOND_EDGE))
#define IS_QSPI_FRF(FRF) (((FRF) == QSPI_CTRL0_FRF_MOTOROLA) || ((FRF) == QSPI_CTRL0_FRF_TI) || ((FRF) == QSPI_CTRL0_FRF_MICROWIRE))
#define IS_QSPI_DFS(DFS) (((DFS) >= QSPI_CTRL0_DFS_4_BIT) && ((DFS) <= QSPI_CTRL0_DFS_32_BIT))
#define IS_QSPI_NDF(NDF) (((NDF) <= 0xFFFF))
#define IS_QSPI_MWMOD(MWMOD) (((MWMOD) == QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL) || ((MWMOD) == QSPI_MW_CTRL_MWMOD_SEQUENTIAL))
#define IS_QSPI_MC_DIR(MC_DIR) (((MC_DIR) == QSPI_MW_CTRL_MC_DIR_RX) || ((MC_DIR) == QSPI_MW_CTRL_MC_DIR_TX))
#define IS_QSPI_MHS_EN(MHS_EN) (((MHS_EN) == QSPI_MW_CTRL_MHS_EN) || ((MHS_EN) == 0))
#define IS_QSPI_CLK_DIV(CLK_DIV) (((CLK_DIV) <= 0xFFFF))
#define IS_QSPI_TXFT(TXFT) (((TXFT) <= 0x1FFFFF))
#define IS_QSPI_RXFT(RXFT) (((RXFT) <= 0x1F))
#define IS_QSPI_TXFN(TXFN) (((TXFN) <= 0x3F))
#define IS_QSPI_RXFN(RXFN) (((RXFN) <= 0x3F))
#define IS_QSPI_DMA_CTRL(DMA_CTRL) (((DMA_CTRL) == QSPI_DMA_CTRL_TX_DMA_EN) || ((DMA_CTRL) == QSPI_DMA_CTRL_RX_DMA_EN))
#define IS_QSPI_DMATDL_CTRL(DMATDL_CTRL) (((DMATDL_CTRL) <= 0x3F))
#define IS_QSPI_DMARDL_CTRL(DMARDL_CTRL) (((DMARDL_CTRL) <= 0x3F))
#define IS_QSPI_SES(SES) (((SES) == QSPI_RS_DELAY_SES_RISING_EDGE) || ((SES) == QSPI_RS_DELAY_SES_FALLING_EDGE))
#define IS_QSPI_SDCN(SDCN) (((SDCN) <= 0xFF))
#define IS_QSPI_ENH_CLK_STRETCH_EN(ENH_CLK_STRETCH_EN) (((ENH_CLK_STRETCH_EN) == QSPI_ENH_CTRL0_CLK_STRETCH_EN) || ((ENH_CLK_STRETCH_EN) == 0))
#define IS_QSPI_ENH_XIP_MBL(ENH_XIP_MBL) \
(((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_2_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_4_BIT) || \
((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_8_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_16_BIT))
#define IS_QSPI_ENH_XIP_CT_EN(ENH_XIP_CT_EN) (((ENH_XIP_CT_EN) == QSPI_ENH_CTRL0_XIP_CT_EN) || ((ENH_XIP_CT_EN) == 0))
#define IS_QSPI_ENH_XIP_INST_EN(ENH_XIP_INST_EN) (((ENH_XIP_INST_EN) == QSPI_ENH_CTRL0_XIP_INST_EN) || ((ENH_XIP_INST_EN) == 0))
#define IS_QSPI_ENH_XIP_DFS_HC(ENH_XIP_DFS_HC) (((ENH_XIP_DFS_HC) == QSPI_ENH_CTRL0_XIP_DFS_HC) || ((ENH_XIP_DFS_HC) == 0))
#define IS_QSPI_ENH_INST_DDR_EN(ENH_INST_DDR_EN) (((ENH_INST_DDR_EN) == QSPI_ENH_CTRL0_INST_DDR_EN) || ((ENH_INST_DDR_EN) == 0))
#define IS_QSPI_ENH_SPI_DDR_EN(ENH_SPI_DDR_EN) (((ENH_SPI_DDR_EN) == QSPI_ENH_CTRL0_SPI_DDR_EN) || ((ENH_SPI_DDR_EN) == 0))
#define IS_QSPI_ENH_WAIT_CYCLES(ENH_WAIT_CYCLES) ((((ENH_WAIT_CYCLES) >= QSPI_ENH_CTRL0_WAIT_1CYCLES) && ((ENH_WAIT_CYCLES) <= QSPI_ENH_CTRL0_WAIT_31CYCLES)) || \
((ENH_WAIT_CYCLES) == 0))
#define IS_QSPI_ENH_INST_L(ENH_INST_L) \
(((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || \
((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE))
#define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0))
#define IS_QSPI_ENH_ADDR_LEN(ENH_ADDR_LEN) ((((ENH_ADDR_LEN) >= QSPI_ENH_CTRL0_ADDR_LEN_4_BIT) && ((ENH_ADDR_LEN) <= QSPI_ENH_CTRL0_ADDR_LEN_60_BIT)) || \
((ENH_ADDR_LEN) == 0))
#define IS_QSPI_ENH_TRANS_TYPE(ENH_TRANS_TYPE) (((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD) || \
((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF) || \
((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF))
#define IS_QSPI_DDR_TXDE(DDR_TXDE) (((DDR_TXDE) <= 0xFF))
#define IS_QSPI_XIP_MODE(XIP_MODE) (((XIP_MODE) <= 0xFFFF))
#define IS_QSPI_XIP_INCR_TOC(XIP_INCR_TOC) (((XIP_INCR_TOC) <= 0xFFFF))
#define IS_QSPI_XIP_WRAP_TOC(XIP_WRAP_TOC) (((XIP_WRAP_TOC) <= 0xFFFF))
#define IS_QSPI_XIP_TOUT(XIP_TOUT) (((XIP_TOUT) <= 0xFF))
#define IS_QSPI_XIP_MBL(XIP_MBL) \
(((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_2_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_4_BIT) || \
((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_8_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_16_BIT))
#define IS_QSPI_XIP_CT_EN(XIP_CT_EN) (((XIP_CT_EN) == QSPI_XIP_CTRL_XIP_CT_EN) || ((XIP_CT_EN) == 0))
#define IS_QSPI_XIP_INST_EN(XIP_INST_EN) (((XIP_INST_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((XIP_INST_EN) == 0))
#define IS_QSPI_INST_DDR_EN(INST_DDR_EN) (((INST_DDR_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((INST_DDR_EN) == 0))
#define IS_QSPI_DDR_EN(DDR_EN) (((DDR_EN) == QSPI_XIP_CTRL_DDR_EN) || ((DDR_EN) == 0))
#define IS_QSPI_XIP_DFS_HC(XIP_DFS_HC) (((XIP_DFS_HC) == QSPI_XIP_CTRL_DFS_HC) || ((XIP_DFS_HC) == 0))
#define IS_QSPI_XIP_WAIT_CYCLES(XIP_WAIT_CYCLES) ((((XIP_WAIT_CYCLES) >= QSPI_XIP_CTRL_WAIT_1CYCLES) && ((XIP_WAIT_CYCLES) <= QSPI_XIP_CTRL_WAIT_31CYCLES)) || \
((XIP_WAIT_CYCLES) == 0))
#define IS_QSPI_XIP_MD_BIT_EN(XIP_MD_BIT_EN) (((XIP_MD_BIT_EN) == QSPI_XIP_CTRL_MD_BIT_EN) || ((XIP_MD_BIT_EN) == 0))
#define IS_QSPI_XIP_INST_L(XIP_INST_L) \
(((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_0_LINE) || ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_4_LINE) || \
((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_8_LINE) || ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_16_LINE))
#define IS_QSPI_XIP_ADDR_LEN(XIP_ADDR_LEN) ((((XIP_ADDR_LEN) >= QSPI_XIP_CTRL_ADDR_4BIT) && ((XIP_ADDR_LEN) <= QSPI_XIP_CTRL_ADDR_60BIT)) || \
((XIP_ADDR_LEN) == 0))
#define IS_QSPI_XIP_TRANS_TYPE(XIP_TRANS_TYPE) (((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI) || \
((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF) || \
((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF))
#define IS_QSPI_XIP_FRF(XIP_FRF) (((XIP_FRF) == QSPI_XIP_CTRL_FRF_2_LINE) || ((XIP_FRF) == QSPI_XIP_CTRL_FRF_4_LINE) || ((XIP_FRF) == 0))
////////////////////////////////////////////////////////////////////////////////////////////////////
void QSPI_Cmd(bool cmd);
void QSPI_XIP_Cmd(bool cmd);
void QSPI_DeInit(void);
void QspiInitConfig(QSPI_InitType* QSPI_InitStruct);
void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output);
void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel);
uint16_t QSPI_GetITStatus(uint16_t FLAG);
void QSPI_ClearITFLAG(uint16_t FLAG);
void QSPI_XIP_ClearITFLAG(uint16_t FLAG);
bool GetQspiBusyStatus(void);
bool GetQspiTxDataBusyStatus(void);
bool GetQspiTxDataEmptyStatus(void);
bool GetQspiRxHaveDataStatus(void);
bool GetQspiRxDataFullStatus(void);
bool GetQspiTransmitErrorStatus(void);
bool GetQspiDataConflictErrorStatus(void);
void QspiSendWord(uint32_t SendData);
uint32_t QspiReadWord(void);
uint32_t QspiGetDataPointer(void);
uint32_t QspiReadRxFifoNum(void);
void ClrFifo(void);
uint32_t GetFifoData(uint32_t* pData, uint32_t Len);
void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt);
uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t LastRd);
#ifdef __cplusplus
}
#endif
#endif /*__N32G45X_QSPI_H__ */
/**
* @}
*/
/**
* @}
*/

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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_sdio.h
* @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_SDIO_H__
#define __N32G45X_SDIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @addtogroup SDIO_Exported_Types
* @{
*/
typedef struct
{
uint32_t ClkEdge; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge */
uint32_t ClkBypass; /*!< Specifies whether the SDIO Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDIO_Clock_Bypass */
uint32_t ClkPwrSave; /*!< Specifies whether SDIO Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t BusWidth; /*!< Specifies the SDIO bus width.
This parameter can be a value of @ref SDIO_Bus_Wide */
uint32_t HardwareClkCtrl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
uint8_t ClkDiv; /*!< Specifies the clock frequency of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitType;
typedef struct
{
uint32_t CmdArgument; /*!< Specifies the SDIO command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register */
uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
uint32_t ResponseType; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t WaitType; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t CPSMConfig; /*!< Specifies whether SDIO Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitType;
typedef struct
{
uint32_t DatTimeout; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t DatLen; /*!< Specifies the number of data bytes to be transferred. */
uint32_t DatBlkSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t TransferDirection; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Type */
uint32_t DPSMConfig; /*!< Specifies whether SDIO Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitType;
/**
* @}
*/
/** @addtogroup SDIO_Exported_Constants
* @{
*/
/** @addtogroup SDIO_Clock_Edge
* @{
*/
#define SDIO_CLKEDGE_RISING ((uint32_t)0x00000000)
#define SDIO_CLKEDGE_FALLING ((uint32_t)0x00002000)
#define IS_SDIO_CLK_EDGE(EDGE) (((EDGE) == SDIO_CLKEDGE_RISING) || ((EDGE) == SDIO_CLKEDGE_FALLING))
/**
* @}
*/
/** @addtogroup SDIO_Clock_Bypass
* @{
*/
#define SDIO_ClkBYPASS_DISABLE ((uint32_t)0x00000000)
#define SDIO_ClkBYPASS_ENABLE ((uint32_t)0x00000400)
#define IS_SDIO_CLK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClkBYPASS_DISABLE) || ((BYPASS) == SDIO_ClkBYPASS_ENABLE))
/**
* @}
*/
/** @addtogroup SDIO_Clock_Power_Save
* @{
*/
#define SDIO_CLKPOWERSAVE_DISABLE ((uint32_t)0x00000000)
#define SDIO_CLKPOWERSAVE_ENABLE ((uint32_t)0x00000200)
#define IS_SDIO_CLK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLKPOWERSAVE_DISABLE) || ((SAVE) == SDIO_CLKPOWERSAVE_ENABLE))
/**
* @}
*/
/** @addtogroup SDIO_Bus_Wide
* @{
*/
#define SDIO_BUSWIDTH_1B ((uint32_t)0x00000000)
#define SDIO_BUSWIDTH_4B ((uint32_t)0x00000800)
#define SDIO_BUSWIDTH_8B ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDTH(WIDE) \
(((WIDE) == SDIO_BUSWIDTH_1B) || ((WIDE) == SDIO_BUSWIDTH_4B) || ((WIDE) == SDIO_BUSWIDTH_8B))
/**
* @}
*/
/** @addtogroup SDIO_Hardware_Flow_Control
* @{
*/
#define SDIO_HARDWARE_CLKCTRL_DISABLE ((uint32_t)0x00000000)
#define SDIO_HARDWARE_CLKCTRL_ENABLE ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_CLKCTRL(CONTROL) \
(((CONTROL) == SDIO_HARDWARE_CLKCTRL_DISABLE) || ((CONTROL) == SDIO_HARDWARE_CLKCTRL_ENABLE))
/**
* @}
*/
/** @addtogroup SDIO_Power_State
* @{
*/
#define SDIO_POWER_CTRL_OFF ((uint32_t)0x00000000)
#define SDIO_POWER_CTRL_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_CTRL(STATE) (((STATE) == SDIO_POWER_CTRL_OFF) || ((STATE) == SDIO_POWER_CTRL_ON))
/**
* @}
*/
/** @addtogroup SDIO_Interrupt_sources
* @{
*/
#define SDIO_INT_CCRCERR ((uint32_t)0x00000001)
#define SDIO_INT_DCRCERR ((uint32_t)0x00000002)
#define SDIO_INT_CMDTIMEOUT ((uint32_t)0x00000004)
#define SDIO_INT_DATTIMEOUT ((uint32_t)0x00000008)
#define SDIO_INT_TXURERR ((uint32_t)0x00000010)
#define SDIO_INT_RXORERR ((uint32_t)0x00000020)
#define SDIO_INT_CMDRESPRECV ((uint32_t)0x00000040)
#define SDIO_INT_CMDSEND ((uint32_t)0x00000080)
#define SDIO_INT_DATEND ((uint32_t)0x00000100)
#define SDIO_INT_SBERR ((uint32_t)0x00000200)
#define SDIO_INT_DATBLKEND ((uint32_t)0x00000400)
#define SDIO_INT_CMDRUN ((uint32_t)0x00000800)
#define SDIO_INT_TXRUN ((uint32_t)0x00001000)
#define SDIO_INT_RXRUN ((uint32_t)0x00002000)
#define SDIO_INT_TFIFOHE ((uint32_t)0x00004000)
#define SDIO_INT_RFIFOHF ((uint32_t)0x00008000)
#define SDIO_INT_TFIFOF ((uint32_t)0x00010000)
#define SDIO_INT_RFIFOF ((uint32_t)0x00020000)
#define SDIO_INT_TFIFOE ((uint32_t)0x00040000)
#define SDIO_INT_RFIFOE ((uint32_t)0x00080000)
#define SDIO_INT_TDATVALID ((uint32_t)0x00100000)
#define SDIO_INT_RDATVALID ((uint32_t)0x00200000)
#define SDIO_INT_SDIOINT ((uint32_t)0x00400000)
#define SDIO_INT_CEATAF ((uint32_t)0x00800000)
#define IS_SDIO_INT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @addtogroup SDIO_Command_Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/**
* @}
*/
/** @addtogroup SDIO_Response_Type
* @{
*/
#define SDIO_RESP_NO ((uint32_t)0x00000000)
#define SDIO_RESP_SHORT ((uint32_t)0x00000040)
#define SDIO_RESP_LONG ((uint32_t)0x000000C0)
#define IS_SDIO_RESP(RESPONSE) \
(((RESPONSE) == SDIO_RESP_NO) || ((RESPONSE) == SDIO_RESP_SHORT) || ((RESPONSE) == SDIO_RESP_LONG))
/**
* @}
*/
/** @addtogroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_WAIT_NO ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
#define SDIO_WAIT_INT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
#define SDIO_WAIT_PEND ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || ((WAIT) == SDIO_WAIT_INT) || ((WAIT) == SDIO_WAIT_PEND))
/**
* @}
*/
/** @addtogroup SDIO_CPSM_State
* @{
*/
#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_ENABLE) || ((CPSM) == SDIO_CPSM_DISABLE))
/**
* @}
*/
/** @addtogroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESPONSE_1 ((uint32_t)0x00000000)
#define SDIO_RESPONSE_2 ((uint32_t)0x00000004)
#define SDIO_RESPONSE_3 ((uint32_t)0x00000008)
#define SDIO_RESPONSE_4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESPONSE(RESP) \
(((RESP) == SDIO_RESPONSE_1) || ((RESP) == SDIO_RESPONSE_2) || ((RESP) == SDIO_RESPONSE_3) \
|| ((RESP) == SDIO_RESPONSE_4))
/**
* @}
*/
/** @addtogroup SDIO_Data_Length
* @{
*/
#define IS_SDIO_DAT_LEN(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/**
* @}
*/
/** @addtogroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DATBLK_SIZE_1B ((uint32_t)0x00000000)
#define SDIO_DATBLK_SIZE_2B ((uint32_t)0x00000010)
#define SDIO_DATBLK_SIZE_4B ((uint32_t)0x00000020)
#define SDIO_DATBLK_SIZE_8B ((uint32_t)0x00000030)
#define SDIO_DATBLK_SIZE_16B ((uint32_t)0x00000040)
#define SDIO_DATBLK_SIZE_32B ((uint32_t)0x00000050)
#define SDIO_DATBLK_SIZE_64B ((uint32_t)0x00000060)
#define SDIO_DATBLK_SIZE_128B ((uint32_t)0x00000070)
#define SDIO_DATBLK_SIZE_256B ((uint32_t)0x00000080)
#define SDIO_DATBLK_SIZE_512B ((uint32_t)0x00000090)
#define SDIO_DATBLK_SIZE_1024B ((uint32_t)0x000000A0)
#define SDIO_DATBLK_SIZE_2048B ((uint32_t)0x000000B0)
#define SDIO_DATBLK_SIZE_4096B ((uint32_t)0x000000C0)
#define SDIO_DATBLK_SIZE_8192B ((uint32_t)0x000000D0)
#define SDIO_DATBLK_SIZE_16384B ((uint32_t)0x000000E0)
#define IS_SDIO_BLK_SIZE(SIZE) \
(((SIZE) == SDIO_DATBLK_SIZE_1B) || ((SIZE) == SDIO_DATBLK_SIZE_2B) || ((SIZE) == SDIO_DATBLK_SIZE_4B) \
|| ((SIZE) == SDIO_DATBLK_SIZE_8B) || ((SIZE) == SDIO_DATBLK_SIZE_16B) || ((SIZE) == SDIO_DATBLK_SIZE_32B) \
|| ((SIZE) == SDIO_DATBLK_SIZE_64B) || ((SIZE) == SDIO_DATBLK_SIZE_128B) || ((SIZE) == SDIO_DATBLK_SIZE_256B) \
|| ((SIZE) == SDIO_DATBLK_SIZE_512B) || ((SIZE) == SDIO_DATBLK_SIZE_1024B) || ((SIZE) == SDIO_DATBLK_SIZE_2048B) \
|| ((SIZE) == SDIO_DATBLK_SIZE_4096B) || ((SIZE) == SDIO_DATBLK_SIZE_8192B) \
|| ((SIZE) == SDIO_DATBLK_SIZE_16384B))
/**
* @}
*/
/** @addtogroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TRANSDIR_TOCARD ((uint32_t)0x00000000)
#define SDIO_TRANSDIR_TOSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIRECTION(DIR) (((DIR) == SDIO_TRANSDIR_TOCARD) || ((DIR) == SDIO_TRANSDIR_TOSDIO))
/**
* @}
*/
/** @addtogroup SDIO_Transfer_Type
* @{
*/
#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000)
#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004)
#define IS_SDIO_TRANS_MODE(MODE) (((MODE) == SDIO_TRANSMODE_STREAM) || ((MODE) == SDIO_TRANSMODE_BLOCK))
/**
* @}
*/
/** @addtogroup SDIO_DPSM_State
* @{
*/
#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_ENABLE) || ((DPSM) == SDIO_DPSM_DISABLE))
/**
* @}
*/
/** @addtogroup SDIO_Flags
* @{
*/
#define SDIO_FLAG_CCRCERR ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCERR ((uint32_t)0x00000002)
#define SDIO_FLAG_CMDTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DATTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXURERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXORERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDRESPRECV ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSEND ((uint32_t)0x00000080)
#define SDIO_FLAG_DATEND ((uint32_t)0x00000100)
#define SDIO_FLAG_SBERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DATBLKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800)
#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000)
#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000)
#define SDIO_FLAG_TFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TDATVALID ((uint32_t)0x00100000)
#define SDIO_FLAG_RDATVALID ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAF ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) \
(((FLAG) == SDIO_FLAG_CCRCERR) || ((FLAG) == SDIO_FLAG_DCRCERR) || ((FLAG) == SDIO_FLAG_CMDTIMEOUT) \
|| ((FLAG) == SDIO_FLAG_DATTIMEOUT) || ((FLAG) == SDIO_FLAG_TXURERR) || ((FLAG) == SDIO_FLAG_RXORERR) \
|| ((FLAG) == SDIO_FLAG_CMDRESPRECV) || ((FLAG) == SDIO_FLAG_CMDSEND) || ((FLAG) == SDIO_FLAG_DATEND) \
|| ((FLAG) == SDIO_FLAG_SBERR) || ((FLAG) == SDIO_FLAG_DATBLKEND) || ((FLAG) == SDIO_FLAG_CMDRUN) \
|| ((FLAG) == SDIO_FLAG_TXRUN) || ((FLAG) == SDIO_FLAG_RXRUN) || ((FLAG) == SDIO_FLAG_TFIFOHE) \
|| ((FLAG) == SDIO_FLAG_RFIFOHF) || ((FLAG) == SDIO_FLAG_TFIFOF) || ((FLAG) == SDIO_FLAG_RFIFOF) \
|| ((FLAG) == SDIO_FLAG_TFIFOE) || ((FLAG) == SDIO_FLAG_RFIFOE) || ((FLAG) == SDIO_FLAG_TDATVALID) \
|| ((FLAG) == SDIO_FLAG_RDATVALID) || ((FLAG) == SDIO_FLAG_SDIOINT) || ((FLAG) == SDIO_FLAG_CEATAF))
#define IS_SDIO_CLR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_INT(IT) \
(((IT) == SDIO_INT_CCRCERR) || ((IT) == SDIO_INT_DCRCERR) || ((IT) == SDIO_INT_CMDTIMEOUT) \
|| ((IT) == SDIO_INT_DATTIMEOUT) || ((IT) == SDIO_INT_TXURERR) || ((IT) == SDIO_INT_RXORERR) \
|| ((IT) == SDIO_INT_CMDRESPRECV) || ((IT) == SDIO_INT_CMDSEND) || ((IT) == SDIO_INT_DATEND) \
|| ((IT) == SDIO_INT_SBERR) || ((IT) == SDIO_INT_DATBLKEND) || ((IT) == SDIO_INT_CMDRUN) \
|| ((IT) == SDIO_INT_TXRUN) || ((IT) == SDIO_INT_RXRUN) || ((IT) == SDIO_INT_TFIFOHE) \
|| ((IT) == SDIO_INT_RFIFOHF) || ((IT) == SDIO_INT_TFIFOF) || ((IT) == SDIO_INT_RFIFOF) \
|| ((IT) == SDIO_INT_TFIFOE) || ((IT) == SDIO_INT_RFIFOE) || ((IT) == SDIO_INT_TDATVALID) \
|| ((IT) == SDIO_INT_RDATVALID) || ((IT) == SDIO_INT_SDIOINT) || ((IT) == SDIO_INT_CEATAF))
#define IS_SDIO_CLR_INT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @addtogroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_RDWAIT_MODE_CLK ((uint32_t)0x00000001)
#define SDIO_RDWAIT_MODE_DAT2 ((uint32_t)0x00000000)
#define IS_SDIO_RDWAIT_MODE(MODE) (((MODE) == SDIO_RDWAIT_MODE_CLK) || ((MODE) == SDIO_RDWAIT_MODE_DAT2))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup SDIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup SDIO_Exported_Functions
* @{
*/
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitType* SDIO_InitStruct);
void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct);
void SDIO_EnableClock(FunctionalState Cmd);
void SDIO_SetPower(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPower(void);
void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd);
void SDIO_DMACmd(FunctionalState Cmd);
void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct);
void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct);
uint8_t SDIO_GetCmdResp(void);
uint32_t SDIO_GetResp(uint32_t SDIO_RESP);
void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct);
void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct);
uint32_t SDIO_GetDataCountValue(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFifoCounter(void);
void SDIO_EnableReadWait(FunctionalState Cmd);
void SDIO_DisableReadWait(FunctionalState Cmd);
void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_EnableSdioOperation(FunctionalState Cmd);
void SDIO_EnableSendSdioSuspend(FunctionalState Cmd);
void SDIO_EnableCommandCompletion(FunctionalState Cmd);
void SDIO_EnableCEATAInt(FunctionalState Cmd);
void SDIO_EnableSendCEATA(FunctionalState Cmd);
FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG);
void SDIO_ClrFlag(uint32_t SDIO_FLAG);
INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT);
void SDIO_ClrIntPendingBit(uint32_t SDIO_IT);
#ifdef __cplusplus
}
#endif
#endif /* __N32G45X_SDIO_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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bsp/n32g452xx/Libraries/n32g45x_std_periph_driver/inc/n32g45x_spi.h Executable file
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/*****************************************************************************
* Copyright (c) 2019, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g45x_spi.h
* @author Nations
* @version v1.0.0
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G45X_SPI_H__
#define __N32G45X_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g45x.h"
/** @addtogroup N32G45X_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @addtogroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SpiMode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t DataLen; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
} SPI_InitType;
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint16_t I2sMode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2sMode */
uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref Standard */
uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitType;
/**
* @}
*/
/** @addtogroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3))
#define IS_SPI_2OR3_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3))
/** @addtogroup SPI_data_direction
* @{
*/
#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
#define IS_SPI_DIR_MODE(MODE) \
(((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
|| ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
/**
* @}
*/
/** @addtogroup SPI_mode
* @{
*/
#define SPI_MODE_MASTER ((uint16_t)0x0104)
#define SPI_MODE_SLAVE ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
/**
* @}
*/
/** @addtogroup SPI_data_size
* @{
*/
#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
/**
* @}
*/
/** @addtogroup SPI_Clock_Polarity
* @{
*/
#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
/**
* @}
*/
/** @addtogroup SPI_Clock_Phase
* @{
*/
#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
/**
* @}
*/
/** @addtogroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_SOFT ((uint16_t)0x0200)
#define SPI_NSS_HARD ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
/**
* @}
*/
/** @addtogroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
#define IS_SPI_BR_PRESCALER(PRESCALER) \
(((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
|| ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
|| ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
|| ((PRESCALER) == SPI_BR_PRESCALER_256))
/**
* @}
*/
/** @addtogroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FB_MSB ((uint16_t)0x0000)
#define SPI_FB_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
/**
* @}
*/
/** @addtogroup I2sMode
* @{
*/
#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) \
(((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
|| ((MODE) == I2S_MODE_MASTER_RX))
/**
* @}
*/
/** @addtogroup Standard
* @{
*/
#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) \
(((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
|| ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
/**
* @}
*/
/** @addtogroup I2S_Data_Format
* @{
*/
#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
#define IS_I2S_DATA_FMT(FORMAT) \
(((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
|| ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
/**
* @}
*/
/** @addtogroup I2S_MCLK_Output
* @{
*/
#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
/**
* @}
*/
/** @addtogroup I2S_Audio_Frequency
* @{
*/
#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) \
((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
/**
* @}
*/
/** @addtogroup I2S_Clock_Polarity
* @{
*/
#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
/**
* @}
*/
/** @addtogroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @}
*/
/** @addtogroup SPI_NSS_internal_software_management
* @{
*/
#define SPI_NSS_HIGH ((uint16_t)0x0100)
#define SPI_NSS_LOW ((uint16_t)0xFEFF)
#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
/**
* @}
*/
/** @addtogroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_TX ((uint8_t)0x00)
#define SPI_CRC_RX ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
/**
* @}
*/
/** @addtogroup SPI_direction_transmit_receive
* @{
*/
#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
/**
* @}
*/
/** @addtogroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_INT_TE ((uint8_t)0x71)
#define SPI_I2S_INT_RNE ((uint8_t)0x60)
#define SPI_I2S_INT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
#define SPI_I2S_INT_OVER ((uint8_t)0x56)
#define SPI_INT_MODERR ((uint8_t)0x55)
#define SPI_INT_CRCERR ((uint8_t)0x54)
#define I2S_INT_UNDER ((uint8_t)0x53)
#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
#define IS_SPI_I2S_GET_INT(IT) \
(((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
|| ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
/**
* @}
*/
/** @addtogroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
#define I2S_UNDER_FLAG ((uint16_t)0x0008)
#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
#define SPI_MODERR_FLAG ((uint16_t)0x0020)
#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
#define IS_SPI_I2S_GET_FLAG(FLAG) \
(((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
|| ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
|| ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
/**
* @}
*/
/** @addtogroup SPI_CRC_polynomial
* @{
*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup SPI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
void SPI_I2S_DeInit(SPI_Module* SPIx);
void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
void SPI_TransmitCrcNext(SPI_Module* SPIx);
void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__N32G45X_SPI_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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bsp/n32g452xx/Libraries/n32g45x_std_periph_driver/inc/n32g45x_tim.h Executable file
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