add gd32303e-eval BSP

bsp/gd32303e-eval/Kconfig

@@ -0,0 +1,72 @@
+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config RT_USING_USART0
+    bool "Using USART0"
+    select RT_USING_SERIAL
+    default y
+    
+config RT_USING_USART1
+    bool "Using USART1"
+    select RT_USING_SERIAL
+    default n
+
+config RT_USING_USART2
+    bool "Using USART2"
+    select RT_USING_SERIAL
+    default n
+
+config RT_USING_UART3
+    bool "Using UART3"
+    select RT_USING_SERIAL
+    default n
+    
+config RT_USING_UART4
+    bool "Using UART4"
+    select RT_USING_SERIAL
+    default n
+
+config RT_USING_SPI0
+    bool "Using SPI0"
+    select RT_USING_SPI
+    default y 
+
+config RT_USING_SPI1
+    bool "Using SPI1"
+    select RT_USING_SPI
+    default n  
+
+config RT_USING_SPI2
+    bool "Using SPI2"
+    select RT_USING_SPI
+    default n 
+
+config RT_USING_I2C0
+    bool "Using I2C0"
+    select RT_USING_I2C
+    default n 
+
+config RT_USING_I2C1
+    bool "Using I2C1"
+    select RT_USING_I2C
+    default n  
+
+
+

bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h

@@ -0,0 +1,58 @@
+/*!
+    \file  system_gd32f30x.h
+    \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
+           GD32F30x Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32F30X_H
+#define SYSTEM_GD32F30X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit (void);
+/* update the SystemCoreClock with current core clock retrieved from cpu registers */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32F30X_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h

@@ -0,0 +1,55 @@
+/*!
+    \file  gd32f30x_crc.h
+    \brief definitions for the CRC
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_CRC_H
+#define GD32F30X_CRC_H
+
+#include "gd32f30x.h"
+
+/* CRC definitions */
+#define CRC                            CRC_BASE
+
+/* registers definitions */
+#define CRC_DATA                       REG32(CRC + 0x00U)              /*!< CRC data register */
+#define CRC_FDATA                      REG32(CRC + 0x04U)              /*!< CRC free data register */
+#define CRC_CTL                        REG32(CRC + 0x08U)              /*!< CRC control register */
+
+/* bits definitions */
+/* CRC_DATA */
+#define CRC_DATA_DATA                  BITS(0,31)                      /*!< CRC calculation result bits */
+
+/* CRC_FDATA */
+#define CRC_FDATA_FDATA                BITS(0,7)                       /*!< CRC free data bits */
+
+/* CRC_CTL */
+#define CRC_CTL_RST                    BIT(0)                          /*!< CRC reset CRC_DATA register bit */
+
+
+/* function declarations */
+/* deinit CRC calculation unit */
+void crc_deinit(void);
+
+/* reset data register to the value of initializaiton data register */
+void crc_data_register_reset(void);
+/* read the data register */
+uint32_t crc_data_register_read(void);
+
+/* read the free data register */
+uint8_t crc_free_data_register_read(void);
+/* write the free data register */
+void crc_free_data_register_write(uint8_t free_data);
+
+/* CRC calculate a 32-bit data */
+uint32_t crc_single_data_calculate(uint32_t sdata);
+/* CRC calculate a 32-bit data array */
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
+
+#endif /* GD32F30X_CRC_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h

@@ -0,0 +1,161 @@
+/*!
+    \file  gd32f30x_ctc.h
+    \brief definitions for the CTC
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.1, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_CTC_H
+#define GD32F30X_CTC_H
+
+#include "gd32f30x.h"
+
+/* CTC definitions */
+#define CTC                          CTC_BASE
+
+/* registers definitions */
+#define CTC_CTL0                     REG32((CTC) + 0x00U)      /*!< CTC control register 0 */
+#define CTC_CTL1                     REG32((CTC) + 0x04U)      /*!< CTC control register 1 */
+#define CTC_STAT                     REG32((CTC) + 0x08U)      /*!< CTC status register */
+#define CTC_INTC                     REG32((CTC) + 0x0CU)      /*!< CTC interrupt clear register */
+
+/* bits definitions */
+/* CTC_CTL0 */
+#define CTC_CTL0_CKOKIE              BIT(0)                    /*!< clock trim OK(CKOKIF) interrupt enable */ 
+#define CTC_CTL0_CKWARNIE            BIT(1)                    /*!< clock trim warning(CKWARNIF) interrupt enable */
+#define CTC_CTL0_ERRIE               BIT(2)                    /*!< error(ERRIF) interrupt enable */
+#define CTC_CTL0_EREFIE              BIT(3)                    /*!< EREFIF interrupt enable */
+#define CTC_CTL0_CNTEN               BIT(5)                    /*!< CTC counter enable */
+#define CTC_CTL0_AUTOTRIM            BIT(6)                    /*!< hardware automatically trim mode */
+#define CTC_CTL0_SWREFPUL            BIT(7)                    /*!< software reference source sync pulse */
+#define CTC_CTL0_TRIMVALUE           BITS(8,13)                /*!< IRC48M trim value */
+
+/* CTC_CTL1 */
+#define CTC_CTL1_RLVALUE             BITS(0,15)                /*!< CTC counter reload value */
+#define CTC_CTL1_CKLIM               BITS(16,23)               /*!< clock trim base limit value */
+#define CTC_CTL1_REFPSC              BITS(24,26)               /*!< reference signal source prescaler */
+#define CTC_CTL1_REFSEL              BITS(28,29)               /*!< reference signal source selection */
+#define CTC_CTL1_REFPOL              BIT(31)                   /*!< reference signal source polarity */
+
+/* CTC_STAT */
+#define CTC_STAT_CKOKIF              BIT(0)                    /*!< clock trim OK interrupt flag */
+#define CTC_STAT_CKWARNIF            BIT(1)                    /*!< clock trim warning interrupt flag */
+#define CTC_STAT_ERRIF               BIT(2)                    /*!< error interrupt flag */
+#define CTC_STAT_EREFIF              BIT(3)                    /*!< expect reference interrupt flag */
+#define CTC_STAT_CKERR               BIT(8)                    /*!< clock trim error bit */
+#define CTC_STAT_REFMISS             BIT(9)                    /*!< reference sync pulse miss */
+#define CTC_STAT_TRIMERR             BIT(10)                   /*!< trim value error bit */
+#define CTC_STAT_REFDIR              BIT(15)                   /*!< CTC trim counter direction when reference sync pulse occurred */
+#define CTC_STAT_REFCAP              BITS(16,31)               /*!< CTC counter capture when reference sync pulse occurred */
+
+/* CTC_INTC */
+#define CTC_INTC_CKOKIC              BIT(0)                    /*!< CKOKIF interrupt clear bit */
+#define CTC_INTC_CKWARNIC            BIT(1)                    /*!< CKWARNIF interrupt clear bit */
+#define CTC_INTC_ERRIC               BIT(2)                    /*!< ERRIF interrupt clear bit */
+#define CTC_INTC_EREFIC              BIT(3)                    /*!< EREFIF interrupt clear bit */
+
+/* constants definitions */
+/* hardware automatically trim mode definitions */
+#define CTC_HARDWARE_TRIM_MODE_ENABLE                    CTC_CTL0_AUTOTRIM            /*!< hardware automatically trim mode enable*/
+#define CTC_HARDWARE_TRIM_MODE_DISABLE                   ((uint32_t)0x00000000U)      /*!< hardware automatically trim mode disable*/
+
+/* reference signal source polarity definitions */
+#define CTC_REFSOURCE_POLARITY_FALLING                   CTC_CTL1_REFPOL              /*!< reference signal source polarity is falling edge*/
+#define CTC_REFSOURCE_POLARITY_RISING                    ((uint32_t)0x00000000U)      /*!< reference signal source polarity is rising edge*/
+
+/* reference signal source selection definitions */
+#define CTL1_REFSEL(regval)                              (BITS(28,29) & ((uint32_t)(regval) << 28))
+#define CTC_REFSOURCE_GPIO                               CTL1_REFSEL(0)               /*!< GPIO is selected */
+#define CTC_REFSOURCE_LXTAL                              CTL1_REFSEL(1)               /*!< LXTAL is clock selected */
+#define CTC_REFSOURCE_USBSOF                             CTL1_REFSEL(2)               /*!< USBDSOF or USBFSSOF selected */
+
+/* reference signal source prescaler definitions */
+#define CTL1_REFPSC(regval)                              (BITS(24,26) & ((uint32_t)(regval) << 24))
+#define CTC_REFSOURCE_PSC_OFF                            CTL1_REFPSC(0)               /*!< reference signal not divided */
+#define CTC_REFSOURCE_PSC_DIV2                           CTL1_REFPSC(1)               /*!< reference signal divided by 2 */
+#define CTC_REFSOURCE_PSC_DIV4                           CTL1_REFPSC(2)               /*!< reference signal divided by 4 */
+#define CTC_REFSOURCE_PSC_DIV8                           CTL1_REFPSC(3)               /*!< reference signal divided by 8 */
+#define CTC_REFSOURCE_PSC_DIV16                          CTL1_REFPSC(4)               /*!< reference signal divided by 16 */
+#define CTC_REFSOURCE_PSC_DIV32                          CTL1_REFPSC(5)               /*!< reference signal divided by 32 */
+#define CTC_REFSOURCE_PSC_DIV64                          CTL1_REFPSC(6)               /*!< reference signal divided by 64 */
+#define CTC_REFSOURCE_PSC_DIV128                         CTL1_REFPSC(7)               /*!< reference signal divided by 128 */
+
+/* CTC interrupt enable definitions */
+#define CTC_INT_CKOK                                     CTC_CTL0_CKOKIE             /*!< clock trim OK interrupt enable */
+#define CTC_INT_CKWARN                                   CTC_CTL0_CKWARNIE           /*!< clock trim warning interrupt enable */
+#define CTC_INT_ERR                                      CTC_CTL0_ERRIE              /*!< error interrupt enable */
+#define CTC_INT_EREF                                     CTC_CTL0_EREFIE             /*!< expect reference interrupt enable */
+
+/* CTC interrupt source definitions */
+#define CTC_INT_FLAG_CKOK                                CTC_STAT_CKOKIF             /*!< clock trim OK interrupt flag */
+#define CTC_INT_FLAG_CKWARN                              CTC_STAT_CKWARNIF           /*!< clock trim warning interrupt flag */
+#define CTC_INT_FLAG_ERR                                 CTC_STAT_ERRIF              /*!< error interrupt flag */
+#define CTC_INT_FLAG_EREF                                CTC_STAT_EREFIF             /*!< expect reference interrupt flag */
+#define CTC_INT_FLAG_CKERR                               CTC_STAT_CKERR              /*!< clock trim error bit */
+#define CTC_INT_FLAG_REFMISS                             CTC_STAT_REFMISS            /*!< reference sync pulse miss */
+#define CTC_INT_FLAG_TRIMERR                             CTC_STAT_TRIMERR            /*!< trim value error */
+
+/* CTC flag definitions */
+#define CTC_FLAG_CKOK                                    CTC_STAT_CKOKIF             /*!< clock trim OK flag */
+#define CTC_FLAG_CKWARN                                  CTC_STAT_CKWARNIF           /*!< clock trim warning flag */
+#define CTC_FLAG_ERR                                     CTC_STAT_ERRIF              /*!< error flag */
+#define CTC_FLAG_EREF                                    CTC_STAT_EREFIF             /*!< expect reference flag */
+#define CTC_FLAG_CKERR                                   CTC_STAT_CKERR              /*!< clock trim error bit */
+#define CTC_FLAG_REFMISS                                 CTC_STAT_REFMISS            /*!< reference sync pulse miss */
+#define CTC_FLAG_TRIMERR                                 CTC_STAT_TRIMERR            /*!< trim value error bit */
+
+/* function declarations */
+/* reset ctc clock trim controller */
+void ctc_deinit(void);
+
+/* enable the CTC interrupt */
+void ctc_interrupt_enable(uint32_t ctc_interrupt);
+/* disable the CTC interrupt */
+void ctc_interrupt_disable(uint32_t ctc_interrupt);
+/* get CTC interrupt flag */
+FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt); 
+/* clear CTC interrupt flag */
+void ctc_interrupt_flag_clear(uint32_t ctc_interrupt);
+
+/* get CTC flag */
+FlagStatus ctc_flag_get(uint32_t ctc_flag);
+/* clear CTC flag */
+void ctc_flag_clear(uint32_t ctc_flag);
+
+/* configure the IRC48M trim value */
+void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value);
+/* generate software reference source sync pulse */
+void ctc_software_refsource_pulse_generate(void);
+/* configure hardware automatically trim mode */
+void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode);
+
+/* enable CTC trim counter */
+void ctc_counter_enable(void);
+/* disable CTC trim counter */
+void ctc_counter_disable(void);
+
+/* configure reference signal source polarity */
+void ctc_refsource_polarity_config(uint32_t ctc_polarity);
+/* select reference signal source */
+void ctc_refsource_signal_select(uint32_t ctc_refs);
+/* configure reference signal source prescaler */
+void ctc_refsource_prescaler_config(uint32_t ctc_prescaler);
+/* configure clock trim base limit value */
+void ctc_clock_limit_value_config(uint8_t ctc_limit_value);
+/* configure CTC counter reload value */
+void ctc_counter_reload_value_config(uint16_t ctc_reload_value);
+
+/* read CTC counter capture value when reference sync pulse occurred */
+uint16_t ctc_counter_capture_value_read(void);
+/* read CTC trim counter direction when reference sync pulse occurred */
+FlagStatus ctc_counter_direction_read(void);
+/* read CTC counter reload value */
+uint16_t ctc_counter_reload_value_read(void);
+/* read the IRC48M trim value */
+uint8_t ctc_irc48m_trim_value_read(void);
+
+#endif /* GD32F30X_CTC_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h

@@ -0,0 +1,119 @@
+/*!
+    \file  gd32f30x_dbg.h
+    \brief definitions for the DBG
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_DBG_H
+#define GD32F30X_DBG_H
+
+#include "gd32f30x.h"
+
+/* DBG definitions */
+#define DBG                      DBG_BASE
+
+/* registers definitions */
+#define DBG_ID                   REG32(DBG + 0x00U)         /*!< DBG_ID code register */
+#define DBG_CTL0                 REG32(DBG + 0x04U)         /*!< DBG control register 0 */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE           BITS(0,31)                 /*!< DBG ID code values */
+
+/* DBG_CTL0 */
+#define DBG_CTL0_SLP_HOLD        BIT(0)                     /*!< keep debugger connection during sleep mode */
+#define DBG_CTL0_DSLP_HOLD       BIT(1)                     /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL0_STB_HOLD        BIT(2)                     /*!< keep debugger connection during standby mode */
+#define DBG_CTL0_TRACE_IOEN      BIT(5)                     /*!< enable trace pin assignment */
+#define DBG_CTL0_TRACE_MODE      BITS(6,7)                  /*!< trace pin mode selection */
+#define DBG_CTL0_FWDGT_HOLD      BIT(8)                     /*!< debug FWDGT kept when core is halted */
+#define DBG_CTL0_WWDGT_HOLD      BIT(9)                     /*!< debug WWDGT kept when core is halted */
+#define DBG_CTL0_TIMER0_HOLD     BIT(10)                    /*!< hold TIMER0 counter when core is halted */
+#define DBG_CTL0_TIMER1_HOLD     BIT(11)                    /*!< hold TIMER1 counter when core is halted */
+#define DBG_CTL0_TIMER2_HOLD     BIT(12)                    /*!< hold TIMER2 counter when core is halted */
+#define DBG_CTL0_TIMER3_HOLD     BIT(13)                    /*!< hold TIMER3 counter when core is halted */
+#define DBG_CTL0_CAN0_HOLD       BIT(14)                    /*!< debug CAN0 kept when core is halted */
+#define DBG_CTL0_I2C0_HOLD       BIT(15)                    /*!< hold I2C0 smbus when core is halted */
+#define DBG_CTL0_I2C1_HOLD       BIT(16)                    /*!< hold I2C1 smbus when core is halted */
+#define DBG_CTL0_TIMER4_HOLD     BIT(17)                    /*!< hold TIMER4 counter when core is halted */
+#define DBG_CTL0_TIMER5_HOLD     BIT(18)                    /*!< hold TIMER5 counter when core is halted */
+#define DBG_CTL0_TIMER6_HOLD     BIT(19)                    /*!< hold TIMER6 counter when core is halted */
+#define DBG_CTL0_TIMER7_HOLD     BIT(20)                    /*!< hold TIMER7 counter when core is halted */
+#ifdef GD32F30X_CL
+#define DBG_CTL0_CAN1_HOLD       BIT(21)                    /*!< debug CAN1 kept when core is halted */
+#endif /* GD32F30X_CL */
+#ifndef GD32F30X_HD
+#define DBG_CTL0_TIMER11_HOLD    BIT(25)                    /*!< hold TIMER11 counter when core is halted */
+#define DBG_CTL0_TIMER12_HOLD    BIT(26)                    /*!< hold TIMER12 counter when core is halted */
+#define DBG_CTL0_TIMER13_HOLD    BIT(27)                    /*!< hold TIMER13 counter when core is halted */
+#define DBG_CTL0_TIMER8_HOLD     BIT(28)                    /*!< hold TIMER8 counter when core is halted */
+#define DBG_CTL0_TIMER9_HOLD     BIT(29)                    /*!< hold TIMER9 counter when core is halted */
+#define DBG_CTL0_TIMER10_HOLD    BIT(30)                    /*!< hold TIMER10 counter when core is halted */
+#endif /* GD32F30X_HD */
+
+/* constants definitions */
+#define DBG_LOW_POWER_SLEEP      DBG_CTL0_SLP_HOLD          /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP  DBG_CTL0_DSLP_HOLD         /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY    DBG_CTL0_STB_HOLD          /*!< keep debugger connection during standby mode */
+
+typedef enum
+{
+    DBG_FWDGT_HOLD             = BIT(8),                    /*!< debug FWDGT kept when core is halted */
+    DBG_WWDGT_HOLD             = BIT(9),                    /*!< debug WWDGT kept when core is halted */
+    DBG_TIMER0_HOLD            = BIT(10),                   /*!< hold TIMER0 counter when core is halted */
+    DBG_TIMER1_HOLD            = BIT(11),                   /*!< hold TIMER1 counter when core is halted */
+    DBG_TIMER2_HOLD            = BIT(12),                   /*!< hold TIMER2 counter when core is halted */
+    DBG_TIMER3_HOLD            = BIT(13),                   /*!< hold TIMER3 counter when core is halted */
+    DBG_CAN0_HOLD              = BIT(14),                   /*!< debug CAN0 kept when core is halted */
+    DBG_I2C0_HOLD              = BIT(15),                   /*!< hold I2C0 smbus when core is halted */
+    DBG_I2C1_HOLD              = BIT(16),                   /*!< hold I2C1 smbus when core is halted */
+    DBG_TIMER4_HOLD            = BIT(17),                   /*!< hold TIMER4 counter when core is halted */
+    DBG_TIMER5_HOLD            = BIT(18),                   /*!< hold TIMER5 counter when core is halted */
+    DBG_TIMER6_HOLD            = BIT(19),                   /*!< hold TIMER6 counter when core is halted */
+    DBG_TIMER7_HOLD            = BIT(20),                   /*!< hold TIMER7 counter when core is halted */
+#ifdef GD32F30X_CL
+    DBG_CAN1_HOLD              = BIT(21),                   /*!< debug CAN1 kept when core is halted */
+#endif /* GD32F30X_CL */
+#ifndef GD32F30X_HD
+    DBG_TIMER11_HOLD           = BIT(25),                   /*!< hold TIMER11 counter when core is halted */
+    DBG_TIMER12_HOLD           = BIT(26),                   /*!< hold TIMER12 counter when core is halted */
+    DBG_TIMER13_HOLD           = BIT(27),                   /*!< hold TIMER13 counter when core is halted */
+    DBG_TIMER8_HOLD            = BIT(28),                   /*!< hold TIMER8 counter when core is halted */
+    DBG_TIMER9_HOLD            = BIT(29),                   /*!< hold TIMER9 counter when core is halted */
+    DBG_TIMER10_HOLD           = BIT(30),                   /*!< hold TIMER10 counter when core is halted */
+#endif /* GD32F30X_HD */
+}dbg_periph_enum;
+
+#define CTL0_TRACE_MODE(regval)       (BITS(6,7)&((uint32_t)(regval)<<6))
+#define TRACE_MODE_ASYNC              CTL0_TRACE_MODE(0)    /*!< trace pin used for async mode */
+#define TRACE_MODE_SYNC_DATASIZE_1    CTL0_TRACE_MODE(1)    /*!< trace pin used for sync mode and data size is 1 */
+#define TRACE_MODE_SYNC_DATASIZE_2    CTL0_TRACE_MODE(2)    /*!< trace pin used for sync mode and data size is 2 */
+#define TRACE_MODE_SYNC_DATASIZE_4    CTL0_TRACE_MODE(3)    /*!< trace pin used for sync mode and data size is 4 */
+
+/* function declarations */
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+/* enable trace pin assignment */
+void dbg_trace_pin_enable(void);
+/* disable trace pin assignment */
+void dbg_trace_pin_disable(void);
+/* set trace pin mode */
+void dbg_trace_pin_mode_set(uint32_t trace_mode);
+
+#endif /* GD32F30X_DBG_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h

@@ -0,0 +1,79 @@
+/*!
+    \file  gd32f30x_fwdgt.h
+    \brief definitions for the FWDGT
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.1, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_FWDGT_H
+#define GD32F30X_FWDGT_H
+
+#include "gd32f30x.h"
+
+/* FWDGT definitions */
+#define FWDGT                       FWDGT_BASE
+
+/* registers definitions */
+#define FWDGT_CTL                   REG32((FWDGT) + 0x00U)                    /*!< FWDGT control register */
+#define FWDGT_PSC                   REG32((FWDGT) + 0x04U)                    /*!< FWDGT prescaler register */
+#define FWDGT_RLD                   REG32((FWDGT) + 0x08U)                    /*!< FWDGT reload register */
+#define FWDGT_STAT                  REG32((FWDGT) + 0x0CU)                    /*!< FWDGT status register */
+
+/* bits definitions */
+/* FWDGT_CTL */
+#define FWDGT_CTL_CMD               BITS(0,15)                                /*!< FWDGT command value */
+
+/* FWDGT_PSC */
+#define FWDGT_PSC_PSC               BITS(0,2)                                 /*!< FWDGT prescaler divider value */
+
+/* FWDGT_RLD */
+#define FWDGT_RLD_RLD               BITS(0,11)                                /*!< FWDGT counter reload value */
+
+/* FWDGT_STAT */
+#define FWDGT_STAT_PUD              BIT(0)                                    /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD              BIT(1)                                    /*!< FWDGT counter reload value update */
+
+/* constants definitions */
+/* psc register value */
+#define PSC_PSC(regval)             (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))                     /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))                     /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))                     /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))                     /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))                     /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))                     /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))                     /*!< FWDGT prescaler set to 256 */
+
+/* control value */
+#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x5555U)                       /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x0000U)                       /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD            ((uint16_t)0xAAAAU)                       /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE            ((uint16_t)0xCCCCU)                       /*!< FWDGT_CTL bits fwdgt counter enable value */
+
+/* FWDGT timeout value */
+#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_RLD register write operation state flag timeout */
+
+/* FWDGT flag definitions */
+#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                            /*!< FWDGT prescaler divider value update flag */
+#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                            /*!< FWDGT counter reload value update flag */
+
+/* function declarations */
+/* disable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_disable(void);
+/* start the free watchdog timer counter */
+void fwdgt_enable(void);
+
+/* reload the counter of FWDGT */
+void fwdgt_counter_reload(void);
+/* configure counter reload value, and prescaler divider value */
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
+
+/* get flag state of FWDGT */
+FlagStatus fwdgt_flag_get(uint16_t flag);
+
+#endif /* GD32F30X_FWDGT_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h

@@ -0,0 +1,68 @@
+/*!
+    \file  gd32f30x_misc.h
+    \brief definitions for the MISC
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_MISC_H
+#define GD32F30X_MISC_H
+
+#include "gd32f30x.h"
+
+/* constants definitions */
+/* set the RAM and FLASH base address */
+#define NVIC_VECTTAB_RAM            ((uint32_t)0x20000000) /*!< RAM base address */
+#define NVIC_VECTTAB_FLASH          ((uint32_t)0x08000000) /*!< Flash base address */
+
+/* set the NVIC vector table offset mask */
+#define NVIC_VECTTAB_OFFSET_MASK    ((uint32_t)0x1FFFFF80)
+
+/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
+#define NVIC_AIRCR_VECTKEY_MASK     ((uint32_t)0x05FA0000)
+
+/* priority group - define the pre-emption priority and the subpriority */
+#define NVIC_PRIGROUP_PRE0_SUB4     ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
+#define NVIC_PRIGROUP_PRE1_SUB3     ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
+#define NVIC_PRIGROUP_PRE2_SUB2     ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
+#define NVIC_PRIGROUP_PRE3_SUB1     ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
+#define NVIC_PRIGROUP_PRE4_SUB0     ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
+
+/* choose the method to enter or exit the lowpower mode */
+#define SCB_SCR_SLEEPONEXIT         ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
+#define SCB_SCR_SLEEPDEEP           ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
+#define SCB_SCR_SEVONPEND           ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
+
+#define SCB_LPM_SLEEP_EXIT_ISR      SCB_SCR_SLEEPONEXIT
+#define SCB_LPM_DEEPSLEEP           SCB_SCR_SLEEPDEEP
+#define SCB_LPM_WAKE_BY_ALL_INT     SCB_SCR_SEVONPEND
+
+/* choose the systick clock source */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
+#define SYSTICK_CLKSOURCE_HCLK      ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
+
+/* function declarations */
+/* set the priority group */
+void nvic_priority_group_set(uint32_t nvic_prigroup);
+
+/* enable NVIC request */
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
+/* disable NVIC request */
+void nvic_irq_disable(uint8_t nvic_irq);
+
+/* set the NVIC vector table base address */
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
+
+/* set the state of the low power mode */
+void system_lowpower_set(uint8_t lowpower_mode);
+/* reset the state of the low power mode */
+void system_lowpower_reset(uint8_t lowpower_mode);
+
+/* set the systick clock source */
+void systick_clksource_set(uint32_t systick_clksource);
+
+#endif /* GD32F30X_MISC_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h

@@ -0,0 +1,160 @@
+/*!
+    \file  gd32f30x_pmu.h
+    \brief definitions for the PMU
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_PMU_H
+#define GD32F30X_PMU_H
+
+#include "gd32f30x.h"
+
+/* PMU definitions */
+#define PMU                           PMU_BASE                 /*!< PMU base address */
+
+/* registers definitions */
+#define PMU_CTL                       REG32((PMU) + 0x00U)     /*!< PMU control register */
+#define PMU_CS                        REG32((PMU) + 0x04U)     /*!< PMU control and status register */
+
+/* bits definitions */
+/* PMU_CTL */
+#define PMU_CTL_LDOLP                 BIT(0)                   /*!< LDO low power mode */
+#define PMU_CTL_STBMOD                BIT(1)                   /*!< standby mode */
+#define PMU_CTL_WURST                 BIT(2)                   /*!< wakeup flag reset */
+#define PMU_CTL_STBRST                BIT(3)                   /*!< standby flag reset */
+#define PMU_CTL_LVDEN                 BIT(4)                   /*!< low voltage detector enable */
+#define PMU_CTL_LVDT                  BITS(5,7)                /*!< low voltage detector threshold */
+#define PMU_CTL_BKPWEN                BIT(8)                   /*!< backup domain write enable */
+#define PMU_CTL_LDLP                  BIT(10)                  /*!< low-driver mode when use low power LDO */
+#define PMU_CTL_LDNP                  BIT(11)                  /*!< low-driver mode when use normal power LDO */
+#define PMU_CTL_LDOVS                 BITS(14,15)              /*!< LDO output voltage select */
+#define PMU_CTL_HDEN                  BIT(16)                  /*!< high-driver mode enable */
+#define PMU_CTL_HDS                   BIT(17)                  /*!< high-driver mode switch */
+#define PMU_CTL_LDEN                  BITS(18,19)              /*!< low-driver mode enable in deep-sleep mode */
+
+/* PMU_CS */
+#define PMU_CS_WUF                    BIT(0)                   /*!< wakeup flag */
+#define PMU_CS_STBF                   BIT(1)                   /*!< standby flag */
+#define PMU_CS_LVDF                   BIT(2)                   /*!< low voltage detector status flag */
+#define PMU_CS_WUPEN                  BIT(8)                   /*!< wakeup pin enable */
+#define PMU_CS_LDOVSRF                BIT(14)                  /*!< LDO voltage select ready flag */
+#define PMU_CS_HDRF                   BIT(16)                  /*!< high-driver ready flag */
+#define PMU_CS_HDSRF                  BIT(17)                  /*!< high-driver switch ready flag */
+#define PMU_CS_LDRF                   BITS(18,19)              /*!< Low-driver mode ready flag */
+
+/* constants definitions */
+/* PMU low voltage detector threshold definitions */
+#define CTL_LVDT(regval)              (BITS(5,7)&((uint32_t)(regval)<<5))
+#define PMU_LVDT_0                    CTL_LVDT(0)              /*!< voltage threshold is 2.1V */
+#define PMU_LVDT_1                    CTL_LVDT(1)              /*!< voltage threshold is 2.3V */
+#define PMU_LVDT_2                    CTL_LVDT(2)              /*!< voltage threshold is 2.4V */
+#define PMU_LVDT_3                    CTL_LVDT(3)              /*!< voltage threshold is 2.6V */
+#define PMU_LVDT_4                    CTL_LVDT(4)              /*!< voltage threshold is 2.7V */
+#define PMU_LVDT_5                    CTL_LVDT(5)              /*!< voltage threshold is 2.9V */
+#define PMU_LVDT_6                    CTL_LVDT(6)              /*!< voltage threshold is 3.0V */
+#define PMU_LVDT_7                    CTL_LVDT(7)              /*!< voltage threshold is 3.1V */
+
+/* PMU LDO output voltage select definitions */
+#define CTL_LDOVS(regval)             (BITS(14,15)&((uint32_t)(regval)<<14))
+#define PMU_LDOVS_LOW                 CTL_LDOVS(1)             /*!< LDO output voltage low mode */
+#define PMU_LDOVS_MID                 CTL_LDOVS(2)             /*!< LDO output voltage mid mode */
+#define PMU_LDOVS_HIGH                CTL_LDOVS(3)             /*!< LDO output voltage high mode */
+
+/* PMU high-driver mode switch */
+#define CTL_HDS(regval)               (BIT(17)&((uint32_t)(regval)<<17))
+#define PMU_HIGHDR_SWITCH_NONE        CTL_HDS(0)               /*!< no high-driver mode switch */
+#define PMU_HIGHDR_SWITCH_EN          CTL_HDS(1)               /*!< high-driver mode switch */
+
+/* PMU low-driver mode when use low power LDO */
+#define CTL_LDLP(regval)              (BIT(10)&((uint32_t)(regval)<<10))
+#define PMU_NORMALDR_LOWPWR           CTL_LDLP(0)              /*!< normal driver when use low power LDO */
+#define PMU_LOWDR_LOWPWR              CTL_LDLP(1)              /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
+
+/* PMU low-driver mode when use normal power LDO */
+#define CTL_LDNP(regval)              (BIT(11)&((uint32_t)(regval)<<11))
+#define PMU_NORMALDR_NORMALPWR        CTL_LDNP(0)              /*!< normal driver when use normal power LDO */
+#define PMU_LOWDR_NORMALPWR           CTL_LDNP(1)              /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
+
+/* PMU low power mode ready flag definitions */
+#define CS_LDRF(regval)               (BITS(18,19)&((uint32_t)(regval)<<18))
+#define PMU_LDRF_NORMAL               CS_LDRF(0)               /*!< normal driver in deep-sleep mode */
+#define PMU_LDRF_LOWDRIVER            CS_LDRF(3)               /*!< low-driver mode in deep-sleep mode */
+
+/* PMU flag definitions */
+#define PMU_FLAG_WAKEUP               PMU_CS_WUF               /*!< wakeup flag status */
+#define PMU_FLAG_STANDBY              PMU_CS_STBF              /*!< standby flag status */
+#define PMU_FLAG_LVD                  PMU_CS_LVDF              /*!< lvd flag status */
+#define PMU_FLAG_LDOVSRF              PMU_CS_LDOVSRF           /*!< LDO voltage select ready flag */
+#define PMU_FLAG_HDRF                 PMU_CS_HDRF              /*!< high-driver ready flag */
+#define PMU_FLAG_HDSRF                PMU_CS_HDSRF             /*!< high-driver switch ready flag */
+#define PMU_FLAG_LDRF                 PMU_CS_LDRF              /*!< low-driver mode ready flag */
+
+/* PMU ldo definitions */
+#define PMU_LDO_NORMAL                ((uint32_t)0x00000000U)  /*!< LDO normal work when PMU enter deepsleep mode */
+#define PMU_LDO_LOWPOWER              PMU_CTL_LDOLP            /*!< LDO work at low power status when PMU enter deepsleep mode */
+
+/* PMU flag reset definitions */
+#define PMU_FLAG_RESET_WAKEUP         ((uint8_t)0x00U)         /*!< wakeup flag reset */
+#define PMU_FLAG_RESET_STANDBY        ((uint8_t)0x01U)         /*!< standby flag reset */
+
+/* PMU command constants definitions */
+#define WFI_CMD                       ((uint8_t)0x00U)         /*!< use WFI command */
+#define WFE_CMD                       ((uint8_t)0x01U)         /*!< use WFE command */
+
+/* function declarations */
+/* reset PMU registers */
+void pmu_deinit(void);
+
+/* select low voltage detector threshold */
+void pmu_lvd_select(uint32_t lvdt_n);
+/* select LDO output voltage */
+void pmu_ldo_output_select(uint32_t ldo_output);
+/* disable PMU lvd */
+void pmu_lvd_disable(void);
+
+/* functions of low-driver mode and high-driver mode in deep-sleep mode */
+/* switch high-driver mode */
+void pmu_highdriver_switch_select(uint32_t highdr_switch);
+/* enable high-driver mode */
+void pmu_highdriver_mode_enable(void);
+/* disable high-driver mode */
+void pmu_highdriver_mode_disable(void);
+/* enable low-driver mode in deep-sleep mode */
+void pmu_lowdriver_mode_enable(void);
+/* disable low-driver mode in deep-sleep mode */
+void pmu_lowdriver_mode_disable(void);
+/* in deep-sleep mode, driver mode when use low power LDO */
+void pmu_lowpower_driver_config(uint32_t mode);
+/* in deep-sleep mode, driver mode when use normal power LDO */
+void pmu_normalpower_driver_config(uint32_t mode);
+
+/* set PMU mode */
+/* PMU work at sleep mode */
+void pmu_to_sleepmode(uint8_t sleepmodecmd);
+/* PMU work at deepsleep mode */
+void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
+/* PMU work at standby mode */
+void pmu_to_standbymode(uint8_t standbymodecmd);
+/* enable PMU wakeup pin */
+void pmu_wakeup_pin_enable(void);
+/* disable PMU wakeup pin */
+void pmu_wakeup_pin_disable(void);
+
+/* backup related functions */
+/* enable backup domain write */
+void pmu_backup_write_enable(void);
+/* disable backup domain write */
+void pmu_backup_write_disable(void);
+
+/* flag functions */
+/* clear flag bit */
+void pmu_flag_clear(uint32_t flag_reset);
+/* get flag state */
+FlagStatus pmu_flag_get(uint32_t flag);
+
+#endif /* GD32F30X_PMU_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h

@@ -0,0 +1,111 @@
+/*!
+    \file  gd32f30x_rtc.h
+    \brief definitions for the RTC
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.1, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_RTC_H
+#define GD32F30X_RTC_H
+
+#include "gd32f30x.h"
+
+/* RTC definitions */
+#define RTC                          RTC_BASE
+
+/* registers definitions */
+#define RTC_INTEN                    REG32(RTC + 0x00U)      /*!< interrupt enable register */
+#define RTC_CTL                      REG32(RTC + 0x04U)      /*!< control register */
+#define RTC_PSCH                     REG32(RTC + 0x08U)      /*!< prescaler high register */
+#define RTC_PSCL                     REG32(RTC + 0x0CU)      /*!< prescaler low register */
+#define RTC_DIVH                     REG32(RTC + 0x10U)      /*!< divider high register */
+#define RTC_DIVL                     REG32(RTC + 0x14U)      /*!< divider low register */
+#define RTC_CNTH                     REG32(RTC + 0x18U)      /*!< counter high register */
+#define RTC_CNTL                     REG32(RTC + 0x1CU)      /*!< counter low register */
+#define RTC_ALRMH                    REG32(RTC + 0x20U)      /*!< alarm high register */
+#define RTC_ALRML                    REG32(RTC + 0x24U)      /*!< alarm low register */
+
+/* bits definitions */
+/* RTC_INTEN */
+#define RTC_INTEN_SCIE               BIT(0)                   /*!< second interrupt enable */
+#define RTC_INTEN_ALRMIE             BIT(1)                   /*!< alarm interrupt enable */
+#define RTC_INTEN_OVIE               BIT(2)                   /*!< overflow interrupt enable */
+
+/* RTC_CTL */
+#define RTC_CTL_SCIF                 BIT(0)                   /*!< second interrupt flag */
+#define RTC_CTL_ALRMIF               BIT(1)                   /*!< alarm interrupt flag */
+#define RTC_CTL_OVIF                 BIT(2)                   /*!< overflow interrupt flag */
+#define RTC_CTL_RSYNF                BIT(3)                   /*!< registers synchronized flag */
+#define RTC_CTL_CMF                  BIT(4)                   /*!< configuration mode flag */
+#define RTC_CTL_LWOFF                BIT(5)                   /*!< last write operation finished flag */
+
+/* RTC_PSC */
+#define RTC_PSCH_PSC                 BITS(0, 3)               /*!< prescaler high value */
+#define RTC_PSCL_PSC                 BITS(0, 15)              /*!< prescaler low value */
+
+/* RTC_DIV */
+#define RTC_DIVH_DIV                 BITS(0, 3)               /*!< divider high value */
+#define RTC_DIVL_DIV                 BITS(0, 15)              /*!< divider low value */
+
+/* RTC_CNT */
+#define RTC_CNTH_CNT                 BITS(0, 15)              /*!< counter high value */
+#define RTC_CNTL_CNT                 BITS(0, 15)              /*!< counter low value */
+
+/* RTC_ALRM */
+#define RTC_ALRMH_ALRM               BITS(0, 15)              /*!< alarm high value */
+#define RTC_ALRML_ALRM               BITS(0, 15)              /*!< alarm low value */
+
+/* constants definitions */
+#define RTC_HIGH_VALUE               0x000F0000U              /*!< RTC high value */
+#define RTC_LOW_VALUE                0x0000FFFFU              /*!< RTC low value */
+
+/* RTC interrupt enable or disable definitions */
+#define RTC_INT_SECOND               RTC_INTEN_SCIE           /*!< second interrupt enable */
+#define RTC_INT_ALARM                RTC_INTEN_ALRMIE         /*!< alarm interrupt enable */
+#define RTC_INT_OVERFLOW             RTC_INTEN_OVIE           /*!< overflow interrupt enable */
+
+/* RTC flag definitions */
+#define RTC_FLAG_SECOND              RTC_CTL_SCIF             /*!< second interrupt flag */
+#define RTC_FLAG_ALARM               RTC_CTL_ALRMIF           /*!< alarm interrupt flag */
+#define RTC_FLAG_OVERFLOW            RTC_CTL_OVIF             /*!< overflow interrupt flag */
+#define RTC_FLAG_RSYN                RTC_CTL_RSYNF            /*!< registers synchronized flag */
+#define RTC_FLAG_LWOF                RTC_CTL_LWOFF            /*!< last write operation finished flag */
+
+/* function declarations */
+/* enable RTC interrupt */
+void rtc_interrupt_enable(uint32_t interrupt);
+/* disable RTC interrupt */
+void rtc_interrupt_disable(uint32_t interrupt);
+
+/* enter RTC configuration mode */
+void rtc_configuration_mode_enter(void);
+/* exit RTC configuration mode */
+void rtc_configuration_mode_exit(void);
+
+/* wait RTC last write operation finished flag set */
+void rtc_lwoff_wait(void);
+/* wait RTC registers synchronized flag set */
+void rtc_register_sync_wait(void);
+
+/* get RTC counter value */
+uint32_t rtc_counter_get(void);
+/* set RTC counter value */
+void rtc_counter_set(uint32_t cnt);
+
+/* set RTC prescaler value */
+void rtc_prescaler_set(uint32_t psc);
+/* set RTC alarm value */
+void rtc_alarm_config(uint32_t alarm);
+/* get RTC divider value */
+uint32_t rtc_divider_get(void);
+
+/* get RTC flag status */
+FlagStatus rtc_flag_get(uint32_t flag);
+/* clear RTC flag status */
+void rtc_flag_clear(uint32_t flag);
+
+#endif /* GD32F30X_RTC_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h

@@ -0,0 +1,63 @@
+/*!
+    \file  gd32f30x_wwdgt.h
+    \brief definitions for the WWDGT 
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef GD32F30X_WWDGT_H
+#define GD32F30X_WWDGT_H
+
+#include "gd32f30x.h"
+
+/* WWDGT definitions */
+#define WWDGT                       WWDGT_BASE
+
+/* registers definitions */
+#define WWDGT_CTL                   REG32((WWDGT) + 0x00U)                    /*!< WWDGT control register */
+#define WWDGT_CFG                   REG32((WWDGT) + 0x04U)                    /*!< WWDGT configuration register */
+#define WWDGT_STAT                  REG32((WWDGT) + 0x08U)                    /*!< WWDGT status register */
+
+/* bits definitions */
+/* WWDGT_CTL */
+#define WWDGT_CTL_CNT               BITS(0,6)                                 /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN            BIT(7)                                    /*!< WWDGT counter enable */
+
+/* WWDGT_CFG */
+#define WWDGT_CFG_WIN               BITS(0,6)                                 /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC               BITS(7,8)                                 /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE              BIT(9)                                    /*!< early wakeup interrupt enable */
+
+/* WWDGT_STAT */
+#define WWDGT_STAT_EWIF             BIT(0)                                    /*!< early wakeup interrupt flag */
+
+/* constants definitions */
+#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7))   /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1          CFG_PSC(0)                                /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2          CFG_PSC(1)                                /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4          CFG_PSC(2)                                /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8          CFG_PSC(3)                                /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+
+/* function declarations */
+/* reset the window watchdog timer configuration */
+void wwdgt_deinit(void);
+/* start the window watchdog timer counter */
+void wwdgt_enable(void);
+
+/* configure the window watchdog timer counter value */
+void wwdgt_counter_update(uint16_t counter_value);
+/* configure counter value, window value, and prescaler divider value */
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
+
+/* enable early wakeup interrupt of WWDGT */
+void wwdgt_interrupt_enable(void);
+/* check early wakeup interrupt state of WWDGT */
+FlagStatus wwdgt_flag_get(void);
+/* clear early wakeup interrupt state of WWDGT */
+void wwdgt_flag_clear(void);
+
+#endif /* GD32F30X_WWDGT_H */

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c

@@ -0,0 +1,101 @@
+/*!
+    \file  gd32f30x_crc.c
+    \brief CRC driver
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#include "gd32f30x_crc.h"
+
+/*!
+    \brief      deinit CRC calculation unit
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_deinit(void)
+{
+    CRC_DATA  = (uint32_t)0xFFFFFFFFU;
+    CRC_FDATA = (uint32_t)0x00000000U;
+    CRC_CTL   = (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+    \brief      reset data register to the value of initializaiton data register
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_data_register_reset(void)
+{
+    CRC_CTL |= (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+    \brief      read the data register 
+    \param[in]  none
+    \param[out] none
+    \retval     32-bit value of the data register
+*/
+uint32_t crc_data_register_read(void)
+{
+    uint32_t data;
+    data = CRC_DATA;
+    return (data);
+}
+
+/*!
+    \brief      read the free data register
+    \param[in]  none
+    \param[out] none
+    \retval     8-bit value of the free data register
+*/
+uint8_t crc_free_data_register_read(void)
+{
+    uint8_t fdata;
+    fdata = (uint8_t)CRC_FDATA;
+    return (fdata);
+}
+
+/*!
+    \brief      write the free data register
+    \param[in]  free_data: specify 8-bit data
+    \param[out] none
+    \retval     none
+*/
+void crc_free_data_register_write(uint8_t free_data)
+{
+    CRC_FDATA = (uint32_t)free_data;
+}
+
+/*!
+    \brief      CRC calculate a 32-bit data
+    \param[in]  sdata: specify 32-bit data
+    \param[out] none
+    \retval     32-bit CRC calculate value
+*/
+uint32_t crc_single_data_calculate(uint32_t sdata)
+{
+    CRC_DATA = sdata;
+    return (CRC_DATA);
+}
+
+/*!
+    \brief      CRC calculate a 32-bit data array
+    \param[in]  array: pointer to an array of 32 bit data words
+    \param[in]  size: size of the array
+    \param[out] none
+    \retval     32-bit CRC calculate value
+*/
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
+{
+    uint32_t index;
+    for(index = 0U; index < size; index++){
+        CRC_DATA = array[index];
+    }
+    return (CRC_DATA);
+}

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c

@@ -0,0 +1,125 @@
+/*!
+    \file  gd32f30x_dbg.c
+    \brief DBG driver
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#include "gd32f30x_dbg.h"
+
+/*!
+    \brief      read DBG_ID code register
+    \param[in]  none
+    \param[out] none
+    \retval     DBG_ID code
+*/
+uint32_t dbg_id_get(void)
+{
+    return DBG_ID;
+}
+
+/*!
+    \brief      enable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                this parameter can be any combination of the following values:
+      \arg        DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_enable(uint32_t dbg_low_power)
+{
+    DBG_CTL0 |= dbg_low_power;
+}
+
+/*!
+    \brief      disable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                this parameter can be any combination of the following values:
+      \arg        DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_disable(uint32_t dbg_low_power)
+{
+    DBG_CTL0 &= ~dbg_low_power;
+}
+
+/*!
+    \brief      enable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: refer to dbg_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+      \arg        DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_enable(dbg_periph_enum dbg_periph)
+{
+    DBG_CTL0 |= (uint32_t)dbg_periph;
+}
+
+/*!
+    \brief      disable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: refer to dbg_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+      \arg        DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_disable(dbg_periph_enum dbg_periph)
+{
+    DBG_CTL0 &= ~(uint32_t)dbg_periph;
+}
+
+/*!
+    \brief      enable trace pin assignment
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dbg_trace_pin_enable(void)
+{
+    DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
+}
+
+/*!
+    \brief      disable trace pin assignment
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dbg_trace_pin_disable(void)
+{
+    DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
+}
+
+/*!
+    \brief      trace pin mode selection 
+    \param[in]  trace_mode:
+      \arg        TRACE_MODE_ASYNC: trace pin used for async mode 
+      \arg        TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
+      \arg        TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
+      \arg        TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
+    \param[out] none
+    \retval     none
+*/
+void dbg_trace_pin_mode_set(uint32_t trace_mode)
+{
+    DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
+    DBG_CTL0 |= trace_mode;
+}

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c

@@ -0,0 +1,120 @@
+/*!
+    \file  gd32f30x_fwdgt.c
+    \brief FWDGT driver
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.1, firmware for GD32F30x
+*/
+
+#include "gd32f30x_fwdgt.h"
+
+/* write value to FWDGT_CTL_CMD bit field */
+#define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0))
+/* write value to FWDGT_RLD_RLD bit field */
+#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/*!
+    \brief      disable write access to FWDGT_PSC and FWDGT_RLD
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_write_disable(void)
+{
+    FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
+}
+
+/*!
+    \brief      reload the counter of FWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_counter_reload(void)
+{
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+}
+
+/*!
+    \brief      start the free watchdog timer counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_enable(void)
+{
+    FWDGT_CTL = FWDGT_KEY_ENABLE;
+}
+
+
+/*!
+    \brief      configure counter reload value, and prescaler divider value
+    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
+    \param[in]  prescaler_div: FWDGT prescaler value
+      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
+{
+    uint32_t timeout = FWDGT_PSC_TIMEOUT;
+    uint32_t flag_status = RESET;
+  
+    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+  
+    /* wait until the PUD flag to be reset */
+    do{
+       flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+    
+    if ((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+
+    /* configure FWDGT */
+    FWDGT_PSC = (uint32_t)prescaler_div;
+
+    timeout = FWDGT_RLD_TIMEOUT;
+    /* wait until the RUD flag to be reset */
+    do{
+       flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+   
+    if ((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    
+    FWDGT_RLD = RLD_RLD(reload_value);
+    
+    /* reload the counter */
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+
+    return SUCCESS;
+}
+
+/*!
+    \brief      get flag state of FWDGT
+    \param[in]  flag: flag to get 
+      \arg        FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
+      \arg        FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus fwdgt_flag_get(uint16_t flag)
+{
+  if(FWDGT_STAT & flag){
+        return SET;
+  }
+
+    return RESET;
+}

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c

@@ -0,0 +1,146 @@
+/*!
+    \file  gd32f30x_misc.c
+    \brief MISC driver
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#include "gd32f30x_misc.h"
+
+/*!
+    \brief      set the priority group
+    \param[in]  nvic_prigroup: the NVIC priority group
+      \arg        NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
+      \arg        NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
+      \arg        NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
+      \arg        NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
+      \arg        NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
+    \param[out] none
+    \retval     none
+*/
+void nvic_priority_group_set(uint32_t nvic_prigroup)
+{
+    /* set the priority group value */
+    SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
+}
+
+/*!
+    \brief      enable NVIC request
+    \param[in]  nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+    \param[in]  nvic_irq_pre_priority: the pre-emption priority needed to set
+    \param[in]  nvic_irq_sub_priority: the subpriority needed to set
+    \param[out] none
+    \retval     none
+*/
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, 
+                     uint8_t nvic_irq_sub_priority)
+{
+    uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
+    /* use the priority group value to get the temp_pre and the temp_sub */
+    if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
+        temp_pre=0U;
+        temp_sub=0x4U;
+    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
+        temp_pre=1U;
+        temp_sub=0x3U;
+    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
+        temp_pre=2U;
+        temp_sub=0x2U;
+    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
+        temp_pre=3U;
+        temp_sub=0x1U;
+    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
+        temp_pre=4U;
+        temp_sub=0x0U;
+    }else{
+    }
+    /* get the temp_priority to fill the NVIC->IP register */
+    temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
+    temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
+    temp_priority = temp_priority << 0x04U;
+    NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+    /* enable the selected IRQ */
+    NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
+}
+
+/*!
+    \brief      disable NVIC request
+    \param[in]  nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+    \param[out] none
+    \retval     none
+*/
+void nvic_irq_disable(uint8_t nvic_irq)
+{
+    /* disable the selected IRQ.*/
+    NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
+}
+
+/*!
+    \brief      set the NVIC vector table base address
+    \param[in]  nvic_vict_tab: the RAM or FLASH base address
+      \arg        NVIC_VECTTAB_RAM: RAM base address
+      \are        NVIC_VECTTAB_FLASH: Flash base address
+    \param[in]  offset: Vector Table offset
+    \param[out] none
+    \retval     none
+*/
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
+{
+    SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
+}
+
+/*!
+    \brief      set the state of the low power mode
+    \param[in]  lowpower_mode: the low power mode state
+      \arg        SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power 
+                    mode by exiting from ISR
+      \arg        SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
+      \arg        SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up 
+                    by all the enable and disable interrupts
+    \param[out] none
+    \retval     none
+*/
+void system_lowpower_set(uint8_t lowpower_mode)
+{
+    SCB->SCR |= (uint32_t)lowpower_mode;
+}
+
+/*!
+    \brief      reset the state of the low power mode
+    \param[in]  lowpower_mode: the low power mode state
+      \arg        SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power 
+                    mode by exiting from ISR
+      \arg        SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
+      \arg        SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be 
+                    woke up by the enable interrupts
+    \param[out] none
+    \retval     none
+*/
+void system_lowpower_reset(uint8_t lowpower_mode)
+{
+    SCB->SCR &= (~(uint32_t)lowpower_mode);
+}
+
+/*!
+    \brief      set the systick clock source
+    \param[in]  systick_clksource: the systick clock source needed to choose
+      \arg        SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
+      \arg        SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
+    \param[out] none
+    \retval     none
+*/
+
+void systick_clksource_set(uint32_t systick_clksource)
+{
+    if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
+        /* set the systick clock source from HCLK */
+        SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+    }else{
+        /* set the systick clock source from HCLK/8 */
+        SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
+    }
+}

bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c

@@ -0,0 +1,122 @@
+/*!
+    \file  gd32f30x_wwdgt.c
+    \brief WWDGT driver
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#include "gd32f30x_wwdgt.h"
+
+/* write value to WWDGT_CTL_CNT bit field */
+#define CTL_CNT(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0))
+/* write value to WWDGT_CFG_WIN bit field */
+#define CFG_WIN(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0))
+
+/*!
+    \brief      reset the window watchdog timer configuration
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_WWDGTRST);
+    rcu_periph_reset_disable(RCU_WWDGTRST);
+}
+
+/*!
+    \brief      configure the window watchdog timer counter value
+    \param[in]  counter_value: 0x00 - 0x7F
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_counter_update(uint16_t counter_value)
+{
+    uint32_t reg = 0U;
+    
+    reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
+    reg |= CTL_CNT(counter_value);
+    
+    WWDGT_CTL = reg;
+}
+
+/*!
+    \brief      start the window watchdog timer counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_enable(void)
+{
+    WWDGT_CTL |= WWDGT_CTL_WDGTEN;
+}
+
+/*!
+    \brief      configure counter value, window value, and prescaler divider value  
+    \param[in]  counter: 0x00 - 0x7F   
+    \param[in]  window: 0x00 - 0x7F
+    \param[in]  prescaler: wwdgt prescaler value
+      \arg        WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
+      \arg        WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
+      \arg        WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
+      \arg        WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
+{
+    uint32_t reg_cfg = 0U, reg_ctl = 0U;
+
+    /* clear WIN and PSC bits, clear CNT bit */
+    reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
+    reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
+  
+    /* configure WIN and PSC bits, configure CNT bit */
+    reg_cfg |= CFG_WIN(window);
+    reg_cfg |= prescaler;
+    reg_ctl |= CTL_CNT(counter);
+    
+    WWDGT_CTL = reg_ctl;
+    WWDGT_CFG = reg_cfg;
+}
+
+/*!
+    \brief      enable early wakeup interrupt of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_interrupt_enable(void)
+{
+    WWDGT_CFG |= WWDGT_CFG_EWIE;
+}
+
+/*!
+    \brief      check early wakeup interrupt state of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus wwdgt_flag_get(void)
+{
+    if(WWDGT_STAT & WWDGT_STAT_EWIF){
+        return SET;
+    }
+
+    return RESET;
+}
+
+/*!
+    \brief      clear early wakeup interrupt state of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_flag_clear(void)
+{
+    WWDGT_STAT &= (~WWDGT_STAT_EWIF);
+}

bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_core.h

@@ -0,0 +1,191 @@
+/*!
+    \file  usbd_core.h
+    \brief USB device driver core
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBD_CORE_H
+#define USBD_CORE_H
+
+#include "usbd_conf.h"
+#include "usbd_regs.h"
+
+/* interrupt flag mask which decide what event should be handled by application */
+#define IER_MASK          (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \
+                            | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE)
+
+#ifdef LPM_ENABLED
+#undef IER_MASK
+
+#define IER_MASK          (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \
+                            | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE)
+#endif /* LPM_ENABLED */
+
+/* USB device endpoint0 max packet size */
+#define USBD_EP0_MAX_SIZE     64U
+
+#define USBD_CONTRL_STATUS_TX() do \
+{ \
+    pbuf_reg->tx_count = 0U; \
+    USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \
+} while(0)
+
+#define USBD_CONTRL_STATUS_RX() do \
+{ \
+    USBD_STATUS_OUT_SET(EP0); \
+    USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \
+} while(0)
+
+#define ENDP_BUF_ADDR         (sizeof(usbd_ep_buf_struct) * EP_COUNT)
+
+/* USB device endpoint type */
+typedef enum
+{
+    ENDP_CONTROL = 0, /*!< control endpoint type value */
+    ENDP_ISOC,        /*!< isochronous endpoint type value */
+    ENDP_BULK,        /*!< bulk endpoint type value */
+    ENDP_INT          /*!< interupt endpoint type value */
+}usbd_eptype_enum;
+
+/* USB device endpoint kind */
+typedef enum
+{
+    ENDP_SNG_BUF = 0, /*!< single buffer endpoint type value */
+    ENDP_DBL_BUF      /*!< double buffer endpoint type value */
+}usbd_epkind_enum;
+
+/* transfer direction */
+typedef enum
+{
+    USBD_RX = 0,      /*!< receive direction type value */
+    USBD_TX           /*!< transmit direction type value */
+}usbd_dir_enum;
+
+/* USB device status */
+typedef enum
+{
+    USBD_UNCONNECTED = 0, /*!< USB device unconnected status */
+    USBD_DEFAULT,         /*!< USB device default status */
+    USBD_ADDRESSED,       /*!< USB device addressed status */
+    USBD_CONFIGURED,      /*!< USB device configured status */
+    USBD_SUSPENDED,       /*!< USB device suspended status */
+    USBD_CONNECTED        /*!< USB device connected status */
+}usbd_run_status_enum;
+
+/* USB device operation state */
+typedef enum
+{
+    USBD_OK = 0,          /*!< USB device ok */
+    USBD_BUSY,            /*!< USB device busy */
+    USBD_FAIL             /*!< USB device fail */
+}usbd_status_enum;
+
+typedef struct
+{
+    uint16_t tx_addr;    /*!< transmission address */
+    uint16_t reserved0;
+    uint16_t tx_count;   /*!< transmission count */
+    uint16_t reserved1;
+    uint16_t rx_addr;    /*!< reception address */
+    uint16_t reserved2;
+    uint16_t rx_count;   /*!< reception count */
+    uint16_t reserved3;
+}usbd_ep_buf_struct;
+
+/* USB endpoint structure */
+typedef struct
+{
+    /* basic parameters */
+    uint8_t        stall;            /*!< endpoint stall status */
+    uint32_t       maxpacket;        /*!< the maxpacket of the endpoint */
+
+    /* transaction level parameters */
+    uint8_t       *trs_buf;          /*!< transaction buffer address */
+    uint32_t       trs_len;          /*!< transaction buffer length */
+    uint32_t       trs_count;        /*!< transaction data counts */
+}usb_ep_struct;
+
+/* USB standard device request structure */
+typedef struct
+{
+    uint8_t    bmRequestType; /*!< the property of the request */
+    uint8_t    bRequest;      /*!< the code of the request */
+    uint16_t   wValue;        /*!< the value of the request which used to choose the different request in the same code request */
+    uint16_t   wIndex;        /*!< USB standard device request index */
+    uint16_t   wLength;       /*!< the return datas length that the host wants to get */
+}usb_device_req_struct;
+
+/* USB core driver struct */
+typedef struct
+{
+    /* basic parameters */
+    uint8_t  config_num;      /*!< the number of the USB device configuration */
+    uint8_t  status;          /*!< USB device status */
+    uint8_t  prev_status;     /*!< the previous USB device status */
+    uint8_t  remote_wakeup;   /*!< the flag that point out the device whether support the 
+                                   remte wakeup function */
+
+    /* the parameters which needs in control transfer */
+    uint8_t  setup_packet[8];      /*!< the buffer used to store the setup packet */
+    uint32_t ctl_count;            /*!< the datas length of control transfer request */
+
+    /* device endpoints */
+    usb_ep_struct in_ep[EP_COUNT];      /*!< the IN direction endpoints */
+    usb_ep_struct out_ep[EP_COUNT];     /*!< the OUT direction endpoints */
+
+#ifdef LPM_ENABLED
+    uint8_t *bos_desc;                  /*!< BOS descriptor */
+#endif /* LPM_ENABLED */
+
+    uint8_t *dev_desc;                  /*!< device descriptor */
+    uint8_t *config_desc;               /*!< configuration descriptor */
+    void* const *strings;               /*!< configuration strings */
+
+    /* device class handler */
+    usbd_status_enum (*class_init)         (void *pudev, uint8_t config_index);
+    usbd_status_enum (*class_deinit)       (void *pudev, uint8_t config_index);
+    usbd_status_enum (*class_req_handler)  (void *pudev, usb_device_req_struct *req);
+    usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num);
+}usbd_core_handle_struct;
+
+extern uint32_t g_free_buf_addr;
+extern usbd_ep_buf_struct *pbuf_reg;
+
+/* function declarations */
+/* device core register initialization */
+void  usbd_core_init (usbd_core_handle_struct *pudev);
+/* device core register configure when stop device */
+void  usbd_core_deinit (void);
+
+/* free buffer used from application by toggling the SW_BUF byte */
+void  user_buffer_free (uint8_t ep_num, uint8_t dir);
+
+/* endpoint initialization */
+void  usbd_ep_init (usbd_core_handle_struct *pudev, void *pep_desc);
+/* configure the endpoint when it is disabled */
+void  usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr);
+/* endpoint prepare to transmit data */
+void  usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
+/* endpoint prepare to receive data */
+void  usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
+/* set an endpoint to STALL status */
+void  usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr);
+/* clear endpoint stalled status */
+void  usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr);
+/* write datas from user fifo to USBRAM */
+void  usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes);
+/* read datas from USBRAM to user fifo */
+void  usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes);
+
+/* get the endpoint status */
+uint8_t  usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr);
+
+/* get the received data length */
+uint16_t  usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num);
+
+#endif /* USBD_CORE_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_int.h

@@ -0,0 +1,32 @@
+/*!
+    \file  usbd_int.h
+    \brief USB device interrupt handler header file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBD_INT_H
+#define USBD_INT_H
+
+#include "usbd_core.h"
+#include "usbd_std.h"
+#include "usbd_pwr.h"
+
+extern usbd_core_handle_struct usb_device_dev;
+
+typedef struct
+{
+    uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */
+}usbd_int_cb_struct;
+
+extern usbd_int_cb_struct *usbd_int_fops;
+
+/* function declarations */
+/* USB device interrupt service routine */
+void  usbd_isr (void);
+
+#endif /* USBD_INT_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_pwr.h

@@ -0,0 +1,25 @@
+/*!
+    \file  usbd_pwr.h
+    \brief USB device power management functions prototype
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBD_PWR_H
+#define USBD_PWR_H
+
+#include "usbd_core.h"
+
+/* function declarations */
+/* USB wakeup first operation is to wakeup mcu */
+void  resume_mcu (void);
+/* set USB device to suspend mode */
+void  usbd_suspend (void);
+/* start to remote wakeup */
+void  usbd_remote_wakeup_active (void);
+
+#endif /* USBD_PWR_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_std.h

@@ -0,0 +1,194 @@
+/*!
+    \file  usbd_std.h
+    \brief USB standard definitions 
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBD_STD_H
+#define USBD_STD_H
+
+#include "usbd_core.h"
+#include <wchar.h>
+
+#ifndef NULL
+#define NULL                                           0U
+#endif
+
+/* constants definitions */
+#define USB_DEV_QUALIFIER_DESC_LEN                     0x0AU  /* device qualifier descriptor length */
+#define USB_CFG_DESC_LEN                               0x09U  /* configuration descriptor length */
+
+#define USBD_LANGID_STR_IDX                            0x00U  /* language ID string index */
+#define USBD_MFC_STR_IDX                               0x01U  /* manufacturer string index */
+#define USBD_PRODUCT_STR_IDX                           0x02U  /* product string index */
+#define USBD_SERIAL_STR_IDX                            0x03U  /* serial string index */
+#define USBD_CONFIG_STR_IDX                            0x04U  /* configuration string index */
+#define USBD_INTERFACE_STR_IDX                         0x05U  /* interface string index */
+
+#define USB_STANDARD_REQ                               0x00U  /* standard request */
+#define USB_CLASS_REQ                                  0x20U  /* device class request */
+#define USB_VENDOR_REQ                                 0x40U  /* vendor request */
+#define USB_REQ_MASK                                   0x60U  /* request type mask */
+
+#define USB_REQTYPE_DEVICE                             0x00U  /* request recipient is device */
+#define USB_REQTYPE_INTERFACE                          0x01U  /* request recipient is interface */
+#define USB_REQTYPE_ENDPOINT                           0x02U  /* request recipient is endpoint */
+#define USB_REQ_RECIPIENT_MASK                         0x1fU  /* request recipient mask */
+
+#define USBREQ_GET_STATUS                              0x00U  /* Get_Status standard requeset */
+#define USBREQ_CLEAR_FEATURE                           0x01U  /* Clear_Feature standard requeset */
+#define USBREQ_SET_FEATURE                             0x03U  /* Set_Feature standard requeset */
+#define USBREQ_SET_ADDRESS                             0x05U  /* Set_Address standard requeset */
+#define USBREQ_GET_DESCRIPTOR                          0x06U  /* Get_Descriptor standard requeset */
+#define USBREQ_GET_CONFIGURATION                       0x08U  /* Get_Configuration standard requeset */
+#define USBREQ_SET_CONFIGURATION                       0x09U  /* Set_Configuration standard requeset */
+#define USBREQ_GET_INTERFACE                           0x0AU  /* Get_Interface standard requeset */
+#define USBREQ_SET_INTERFACE                           0x0BU  /* Set_Interface standard requeset */
+
+#define USB_DESCTYPE_DEVICE                            0x01U  /* device descriptor type */
+#define USB_DESCTYPE_CONFIGURATION                     0x02U  /* configuration descriptor type */
+#define USB_DESCTYPE_STRING                            0x03U  /* string descriptor type */
+#define USB_DESCTYPE_INTERFACE                         0x04U  /* interface descriptor type */
+#define USB_DESCTYPE_ENDPOINT                          0x05U  /* endpoint descriptor type */
+#define USB_DESCTYPE_DEVICE_QUALIFIER                  0x06U  /* device qualifier descriptor type */
+#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION         0x07U  /* other speed configuration descriptor type */
+#define USB_DESCTYPE_BOS                               0x0FU  /* BOS descriptor type */
+
+#define USB_STATUS_REMOTE_WAKEUP                       2U     /* USB is in remote wakeup status */
+#define USB_STATUS_SELF_POWERED                        1U     /* USB is in self powered status */
+
+#define USB_FEATURE_ENDP_HALT                          0U     /* USB has endpoint halt feature */
+#define USB_FEATURE_REMOTE_WAKEUP                      1U     /* USB has endpoint remote wakeup feature */
+#define USB_FEATURE_TEST_MODE                          2U     /* USB has endpoint test mode feature */
+
+#define ENG_LANGID                                     0x0409U  /* english language ID */
+#define CHN_LANGID                                     0x0804U  /* chinese language ID */
+
+#define USB_EPTYPE_MASK                                0x03U
+
+#define USB_DEVICE_DESC_SIZE                           0x12U
+
+/* USB device exported macros */
+#define SWAPBYTE(addr)       (((uint16_t)(*((uint8_t *)(addr)))) + \
+                             (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
+
+#define LOWBYTE(x)           ((uint8_t)((x) & 0x00FFU))
+#define HIGHBYTE(x)          ((uint8_t)(((x) & 0xFF00U) >> 8U))
+
+#define MIN(a, b)            (((a) < (b)) ? (a) : (b))
+
+#define IS_NOT_EP0(ep_addr)  (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
+
+#define WIDE_STRING(string)  _WIDE_STRING(string)
+#define _WIDE_STRING(string) L##string
+
+#define USBD_STRING_DESC(string) \
+    (void *)&(const struct { \
+        uint8_t _len; \
+        uint8_t _type; \
+        wchar_t _data[sizeof(string)]; \
+    }) { \
+        sizeof(WIDE_STRING(string)) + 2U - 2U, \
+        USB_DESCTYPE_STRING, \
+        WIDE_STRING(string) \
+    }
+
+typedef struct
+{
+    uint8_t bLength;                      /*!< size of the descriptor */
+    uint8_t bDescriptorType;              /*!< type of the descriptor */
+} usb_descriptor_header_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size */
+
+    uint16_t bcdUSB;                      /*!< BCD of the supported USB specification */
+    uint8_t  bDeviceClass;                /*!< USB device class */
+    uint8_t  bDeviceSubClass;             /*!< USB device subclass */
+    uint8_t  bDeviceProtocol;             /*!< USB device protocol */
+    uint8_t  bMaxPacketSize0;             /*!< size of the control (address 0) endpoint's bank in bytes */
+    uint16_t idVendor;                    /*!< vendor ID for the USB product */
+    uint16_t idProduct;                   /*!< unique product ID for the USB product */
+    uint16_t bcdDevice;                   /*!< product release (version) number */
+    uint8_t  iManufacturer;               /*!< string index for the manufacturer's name */
+    uint8_t  iProduct;                    /*!< string index for the product name/details */
+    uint8_t  iSerialNumber;               /*!< string index for the product's globally unique hexadecimal serial number */
+    uint8_t  bNumberConfigurations;       /*!< total number of configurations supported by the device */
+} usb_descriptor_device_struct;
+
+#pragma pack(1)
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size */
+
+    uint16_t wTotalLength;                /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */
+    uint8_t  bNumInterfaces;              /*!< total number of interfaces in the configuration */
+    uint8_t  bConfigurationValue;         /*!< configuration index of the current configuration */
+    uint8_t  iConfiguration;              /*!< index of a string descriptor describing the configuration */
+    uint8_t  bmAttributes;                /*!< configuration attributes */
+    uint8_t  bMaxPower;                   /*!< maximum power consumption of the device while in the current configuration */
+} usb_descriptor_configuration_struct;
+
+#pragma pack()
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size */
+
+    uint8_t bInterfaceNumber;             /*!< index of the interface in the current configuration */
+    uint8_t bAlternateSetting;            /*!< alternate setting for the interface number */
+    uint8_t bNumEndpoints;                /*!< total number of endpoints in the interface */
+    uint8_t bInterfaceClass;              /*!< interface class ID */
+    uint8_t bInterfaceSubClass;           /*!< interface subclass ID */
+    uint8_t bInterfaceProtocol;           /*!< interface protocol ID */
+    uint8_t iInterface;                   /*!< index of the string descriptor describing the interface */
+} usb_descriptor_interface_struct;
+
+#pragma pack(1)
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size. */
+
+    uint8_t  bEndpointAddress;            /*!< logical address of the endpoint */
+    uint8_t  bmAttributes;                /*!< endpoint attributes */
+    uint16_t wMaxPacketSize;              /*!< size of the endpoint bank, in bytes */
+    uint8_t  bInterval;                   /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */
+} usb_descriptor_endpoint_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size. */
+    uint16_t wLANGID;                     /*!< LANGID code */
+}usb_descriptor_language_id_struct;
+
+#pragma pack()
+
+/* function declarations */
+/* USB SETUP transaction processing */
+uint8_t  usbd_setup_transaction (usbd_core_handle_struct *pudev);
+/* USB OUT transaction processing */
+uint8_t  usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num);
+/* USB IN transaction processing */
+uint8_t  usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num);
+
+/* handle USB standard device request */
+uint8_t  usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
+/* handle device class request */
+uint8_t  usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
+/* handle USB vendor request */
+uint8_t  usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
+
+/* decode setup data packet */
+void  usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
+/* handle USB enumeration error event */
+void  usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
+
+#endif /* USBD_STD_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_pwr.c

@@ -0,0 +1,132 @@
+/*!
+    \file  usbd_pwr.c
+    \brief USB device power management driver
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#include "usbd_pwr.h"
+
+#ifdef USBD_LOWPWR_MODE_ENABLE
+static void  lowpower_mode_exit (void);
+#endif /* USBD_LOWPWR_MODE_ENABLE */
+
+__IO uint8_t g_ESOF_count = 0U;
+__IO uint8_t g_suspend_enabled = 1U;
+__IO uint8_t g_remote_wakeup_on = 0U;
+
+#ifdef LPM_ENABLED
+extern __IO uint32_t L1_resume;
+#endif /* LPM_ENABLED */
+
+/*!
+    \brief      USB wakeup first operation is to wakeup mcu
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void  resume_mcu (void)
+{
+    /* clear low_power mode bit in USBD_CTL */
+    USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM));
+
+#ifdef USBD_LOWPWR_MODE_ENABLE
+
+    /* restore normal operations */
+    lowpower_mode_exit();
+
+#endif /* USBD_LOWPWR_MODE_ENABLE */
+
+    /* clear SETSPS bit */
+    USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS));
+}
+
+#ifdef USBD_LOWPWR_MODE_ENABLE
+
+/*!
+    \brief      restore system clocks and power while exiting suspend mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void  lowpower_mode_exit (void)
+{
+    /* restore system clock */
+
+    /* enable HSE */
+    rcu_osci_on(RCU_HXTAL);
+
+    /* wait till HSE is ready */
+    while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB));
+
+    /* enable PLL */
+    rcu_osci_on(RCU_PLL_CK);
+
+    /* wait till PLL is ready */
+    while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB));
+
+    /* select PLL as system clock source */
+    rcu_system_clock_source_config(RCU_CKSYSSRC_PLL);
+
+    /* wait till PLL is used as system clock source */
+    while(0x08 != rcu_system_clock_source_get());
+
+    /* low power sleep on exit disabled */
+    system_lowpower_reset(SCB_LPM_DEEPSLEEP);
+}
+
+#endif /* USBD_LOWPWR_MODE_ENABLE */
+
+/*!
+    \brief      set USB device to suspend mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void  usbd_suspend (void)
+{
+    /* set usb module to suspend and low-power mode */
+    USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM);
+
+#ifdef USBD_LOWPWR_MODE_ENABLE
+
+    /* check wakeup flag is set */
+    if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) {
+        /* enter DEEP_SLEEP mode with LDO in low power mode */
+        pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
+    } else {
+        /* clear wakeup interrupt flag */
+        USBD_REG_SET(USBD_INTF, CLR_WKUPIF);
+
+        /* clear set_suspend flag */
+        USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS);
+    }
+
+#endif /* USBD_LOWPWR_MODE_ENABLE */
+}
+
+/*!
+    \brief      start to remote wakeup
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void  usbd_remote_wakeup_active(void)
+{
+    resume_mcu();
+
+#ifdef LPM_ENABLED
+    USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ);
+
+    L1_resume = 1U;
+#else
+    g_remote_wakeup_on = 1U;
+
+    g_ESOF_count = 15U;
+    USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ);
+#endif /* LPM_ENABLED */
+}

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_defines.h

@@ -0,0 +1,100 @@
+/*!
+    \file  usb_defines.h
+    \brief USB core defines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USB_DEFINES_H
+#define USB_DEFINES_H
+
+#include  "usb_conf.h"
+
+#ifndef NULL
+    #define NULL                                (void *)0   /*!< USB null marco value*/
+#endif /* NULL */
+
+#define USB_CORE_SPEED_HIGH                     0U    /* USB core speed is high-speed */
+#define USB_CORE_SPEED_FULL                     1U    /* USB core speed is full-speed */
+
+#define USBFS_MAX_PACKET_SIZE                   64U   /* USBFS max packet size */
+#define USBFS_MAX_HOST_CHANNELCOUNT             8U    /* USBFS host channel count */
+#define USBFS_MAX_DEV_EPCOUNT                   4U    /* USBFS device endpoint count */
+#define USBFS_MAX_FIFO_WORDLEN                  320U  /* USBFS max fifo size in words */
+
+#define USBHS_MAX_PACKET_SIZE                   512U  /* USBHS max packet size */
+#define USBHS_MAX_HOST_CHANNELCOUNT             12U   /* USBHS host channel count */
+#define USBHS_MAX_DEV_EPCOUNT                   6U    /* USBHS device endpoint count */
+#define USBHS_MAX_FIFO_WORDLEN                  1280U /* USBHS max fifo size in words */
+
+#define USB_CORE_ULPI_PHY                       1U    /* USB core use external ULPI PHY */
+#define USB_CORE_EMBEDDED_PHY                   2U    /* USB core use embedded PHY */
+
+#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     0U    /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
+#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     1U    /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
+#define DSTAT_ENUMSPD_LS_PHY_6MHZ               2U    /* USB enumerate speed use low-speed PHY clock in 6MHz */
+#define DSTAT_ENUMSPD_FS_PHY_48MHZ              3U    /* USB enumerate speed use full-speed PHY clock in 48MHz */
+
+#define GRSTATR_RPCKST_IN                       2U    /* IN data packet received */
+#define GRSTATR_RPCKST_IN_XFER_COMP             3U    /* IN transfer completed (generates an interrupt if poped) */
+#define GRSTATR_RPCKST_DATA_TOGGLE_ERR          5U    /* data toggle error (generates an interrupt if poped) */
+#define GRSTATR_RPCKST_CH_HALTED                7U    /* channel halted (generates an interrupt if poped) */
+
+#define DEVICE_MODE                             0U    /* USB core in device mode */
+#define HOST_MODE                               1U    /* USB core in host mode */
+#define OTG_MODE                                2U    /* USB core in OTG mode */
+
+#define USB_EPTYPE_CTRL                         0U    /* USB control endpoint type */
+#define USB_EPTYPE_ISOC                         1U    /* USB synchronous endpoint type */
+#define USB_EPTYPE_BULK                         2U    /* USB bulk endpoint type */
+#define USB_EPTYPE_INTR                         3U    /* USB interrupt endpoint type */
+#define USB_EPTYPE_MASK                         3U    /* USB endpoint type mask */
+
+#define RXSTAT_GOUT_NAK                         1U    /* global OUT NAK (triggers an interrupt) */
+#define RXSTAT_DATA_UPDT                        2U    /* OUT data packet received */
+#define RXSTAT_XFER_COMP                        3U    /* OUT transfer completed (triggers an interrupt) */
+#define RXSTAT_SETUP_COMP                       4U    /* SETUP transaction completed (triggers an interrupt) */
+#define RXSTAT_SETUP_UPDT                       6U    /* SETUP data packet received */
+
+#define DPID_DATA0                              0U    /* device endpoint data PID is DATA0 */
+#define DPID_DATA1                              2U    /* device endpoint data PID is DATA1 */
+#define DPID_DATA2                              1U    /* device endpoint data PID is DATA2 */
+#define DPID_MDATA                              3U    /* device endpoint data PID is MDATA */
+
+#define HC_PID_DATA0                            0U    /* host channel data PID is DATA0 */
+#define HC_PID_DATA2                            1U    /* host channel data PID is DATA2 */
+#define HC_PID_DATA1                            2U    /* host channel data PID is DATA1 */
+#define HC_PID_SETUP                            3U    /* host channel data PID is SETUP */
+
+#define HPRT_PRTSPD_HIGH_SPEED                  0U    /* host port speed use high speed */
+#define HPRT_PRTSPD_FULL_SPEED                  1U    /* host port speed use full speed */
+#define HPRT_PRTSPD_LOW_SPEED                   2U    /* host port speed use low speed */
+
+#define HCTLR_30_60_MHZ                         0U    /* USB PHY(ULPI) clock is 60MHz */
+#define HCTLR_48_MHZ                            1U    /* USB PHY(embedded full-speed) clock is 48MHz */
+#define HCTLR_6_MHZ                             2U    /* USB PHY(embedded low-speed) clock is 6MHz */
+
+#define HCCHAR_CTRL                             0U    /* control channel type */
+#define HCCHAR_ISOC                             1U    /* synchronous channel type */
+#define HCCHAR_BULK                             2U    /* bulk channel type */
+#define HCCHAR_INTR                             3U    /* interrupt channel type */
+
+typedef enum
+{
+    USB_HS_CORE_ID = 0,
+    USB_FS_CORE_ID = 1
+}usb_core_id_enum;
+
+typedef enum
+{
+    USB_SPEED_UNKNOWN = 0,
+    USB_SPEED_LOW,
+    USB_SPEED_FULL,
+    USB_SPEED_HIGH
+}usb_speed_enum;
+
+#endif /* USB_DEFINES_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_std.h

@@ -0,0 +1,188 @@
+/*!
+    \file  usb_std.h
+    \brief USB 2.0 standard defines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USB_STD_H
+#define USB_STD_H
+
+#include "usb_conf.h"
+
+#define USB_DEV_QUALIFIER_DESC_LEN                     0x0AU       /*!< USB device qualifier descriptor length */
+#define USB_DEV_DESC_LEN                               0x12U       /*!< USB device descriptor length */
+#define USB_CFG_DESC_LEN                               0x09U       /*!< USB device configuration descriptor length */
+#define USB_IF_DESC_LEN                                0x09U       /*!< USB device interface descriptor length */
+#define USB_EP_DESC_LEN                                0x07U       /*!< USB device endpoint descriptor length */
+#define USB_OTG_DESC_LEN                               0x03U       /*!< USB device OTG descriptor length */
+
+/* bit 7 of bmRequestType: data phase transfer direction */
+#define USB_DIR_MASK                                   0x80U       /*!< USB transfer direction mask */
+#define USB_DIR_OUT                                    0x00U       /*!< USB transfer OUT direction */
+#define USB_DIR_IN                                     0x80U       /*!< USB transfer IN direction */
+
+/* bit 6..5 of bmRequestType: request type */
+#define USB_STANDARD_REQ                               0x00U       /*!< USB standard request */
+#define USB_CLASS_REQ                                  0x20U       /*!< USB class request */
+#define USB_VENDOR_REQ                                 0x40U       /*!< USB vebdor request */
+#define USB_REQ_MASK                                   0x60U       /*!< USB request mask */
+
+/* bit 4..0 of bmRequestType: recipient type */
+#define USB_REQTYPE_DEVICE                             0x00U       /*!< USB device request type */
+#define USB_REQTYPE_INTERFACE                          0x01U       /*!< USB interface request type*/
+#define USB_REQTYPE_ENDPOINT                           0x02U       /*!< USB endpoint request type*/
+#define USB_REQTYPE_MASK                               0x03U       /*!< USB request type mask*/
+
+/* bRequest value */
+#define USBREQ_GET_STATUS                              0x00U       /*!< USB get status request*/
+#define USBREQ_CLEAR_FEATURE                           0x01U       /*!< USB clear feature request*/
+#define USBREQ_SET_FEATURE                             0x03U       /*!< USB set feature request*/
+#define USBREQ_SET_ADDRESS                             0x05U       /*!< USB set address request*/
+#define USBREQ_GET_DESCRIPTOR                          0x06U       /*!< USB get descriptor request*/
+#define USBREQ_SET_DESCRIPTOR                          0x07U       /*!< USB set descriptor request*/
+#define USBREQ_GET_CONFIGURATION                       0x08U       /*!< USB get configuration request*/
+#define USBREQ_SET_CONFIGURATION                       0x09U       /*!< USB set configuration request*/
+#define USBREQ_GET_INTERFACE                           0x0AU       /*!< USB get interface request*/
+#define USBREQ_SET_INTERFACE                           0x0BU       /*!< USB set interface request*/
+#define USBREQ_SYNCH_FRAME                             0x0CU       /*!< USB synchronize frame request*/
+
+/* descriptor types of usb specifications */
+#define USB_DESCTYPE_DEVICE                            0x01U       /*!< USB device descriptor type*/
+#define USB_DESCTYPE_CONFIGURATION                     0x02U       /*!< USB configuration descriptor type*/
+#define USB_DESCTYPE_STRING                            0x03U       /*!< USB string descriptor type*/
+#define USB_DESCTYPE_INTERFACE                         0x04U       /*!< USB interface descriptor type*/
+#define USB_DESCTYPE_ENDPOINT                          0x05U       /*!< USB endpoint descriptor type*/
+#define USB_DESCTYPE_DEVICE_QUALIFIER                  0x06U       /*!< USB device qualtfier descriptor type*/
+#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION         0x07U       /*!< USB other speed configuration descriptor type*/
+#define USB_DESCTYPE_INTERFACE_POWER                   0x08U       /*!< USB interface power descriptor type*/
+
+#define USB_DESCTYPE_HID                               0x21U       /*!< USB HID descriptor type*/
+#define USB_DESCTYPE_HID_REPORT                        0x22U       /*!< USB HID report descriptor type*/
+
+#define USB_DEVDESC_SIZE                               18U         /*!< USB device descriptor size*/
+#define USB_CFGDESC_SIZE                               9U          /*!< USB configure descriptor size*/
+#define USB_INTDESC_SIZE                               9U          /*!< USB interface descriptor size*/
+#define USB_EPDESC_SIZE                                7U          /*!< USB endpoint descriptor size*/
+
+/* descriptor type and descriptor index  */
+/* use the following values when USB host need to get descriptor  */
+#define  USB_DEVDESC                    ((USB_DESCTYPE_DEVICE                    << 8U) & 0xFF00U)  /*!< USB device operation marco */
+#define  USB_CFGDESC                    ((USB_DESCTYPE_CONFIGURATION             << 8U) & 0xFF00U)  /*!< USB configuration operation marco */
+#define  USB_STRDESC                    ((USB_DESCTYPE_STRING                    << 8U) & 0xFF00U)  /*!< USB string operation marco */
+#define  USB_INTDESC                    ((USB_DESCTYPE_INTERFACE                 << 8U) & 0xFF00U)  /*!< USB interface operation marco */
+#define  USB_EPDESC                     ((USB_DESCTYPE_INTERFACE                 << 8U) & 0xFF00U)  /*!< USB endpoint operation marco */
+#define  USB_DEVQUADESC                 ((USB_DESCTYPE_DEVICE_QUALIFIER          << 8U) & 0xFF00U)  /*!< USB device qualifier operation marco */
+#define  USB_OSPCFGDESC                 ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)  /*!< USB other speed configuration operation marco */
+#define  USB_INTPWRDESC                 ((USB_DESCTYPE_INTERFACE_POWER           << 8U) & 0xFF00U)  /*!< USB interface power operation marco */
+#define  USB_HIDREPDESC                 ((USB_DESCTYPE_HID_REPORT                << 8U) & 0xFF00U)  /*!< USB HID report operation marco */
+#define  USB_HIDDESC                    ((USB_DESCTYPE_HID                       << 8U) & 0xFF00U)  /*!< USB HID operation marco */
+
+#define SWAPBYTE(addr)       (((uint16_t)(*((uint8_t *)(addr)))) + \
+                             (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
+
+/* supported classes */
+#define USB_MSC_CLASS                                   0x08U     /*!< USB MSC class*/
+#define USB_HID_CLASS                                   0x03U     /*!< USB HID class*/
+
+/* interface descriptor field values for hid boot protocol */
+#define HID_BOOT_CODE                                   0x01U     /*!< USB HID boot code*/
+#define HID_KEYBRD_BOOT_CODE                            0x01U     /*!< USB HID keyboard boot code*/
+#define HID_MOUSE_BOOT_CODE                             0x02U     /*!< USB HID mouse boot code*/
+
+/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec
+   standard request with no data stage timeout : 50ms */
+#define DATA_STAGE_TIMEOUT                              5000U     /*!< USB data stage timeout*/
+#define NODATA_STAGE_TIMEOUT                            50U       /*!< USB no data stage timeout*/
+
+#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \
+                                + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE))    /*!< USB host set configuration descriptor size */
+
+#pragma pack(1)
+
+typedef union
+{
+    uint8_t data[8];
+
+    struct _setup_packet_struct
+    {
+        uint8_t           bmRequestType;  /*!< type of request */
+        uint8_t           bRequest;       /*!< request of setup packet */
+        uint16_t          wValue;         /*!< value of setup packet */
+        uint16_t          wIndex;         /*!< index of setup packet */
+        uint16_t          wLength;        /*!< length of setup packet */
+    } b;
+}usb_setup_union;
+
+typedef struct
+{
+    uint8_t bLength;                      /*!< size of the descriptor */
+    uint8_t bDescriptorType;              /*!< type of the descriptor */
+} usb_descriptor_header_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size */
+
+    uint16_t bcdUSB;                      /*!< BCD of the supported USB specification */
+    uint8_t  bDeviceClass;                /*!< USB device class */
+    uint8_t  bDeviceSubClass;             /*!< USB device subclass */
+    uint8_t  bDeviceProtocol;             /*!< USB device protocol */
+    uint8_t  bMaxPacketSize0;             /*!< size of the control (address 0) endpoint's bank in bytes */
+    uint16_t idVendor;                    /*!< vendor ID for the USB product */
+    uint16_t idProduct;                   /*!< unique product ID for the USB product */
+    uint16_t bcdDevice;                   /*!< product release (version) number */
+    uint8_t  iManufacturer;               /*!< string index for the manufacturer's name */
+    uint8_t  iProduct;                    /*!< string index for the product name/details */
+    uint8_t  iSerialNumber;               /*!< string index for the product's globally unique hexadecimal serial number */
+    uint8_t  bNumberConfigurations;       /*!< total number of configurations supported by the device */
+} usb_descriptor_device_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size */
+
+    uint16_t wTotalLength;                /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */
+    uint8_t  bNumInterfaces;              /*!< total number of interfaces in the configuration */
+    uint8_t  bConfigurationValue;         /*!< configuration index of the current configuration */
+    uint8_t  iConfiguration;              /*!< index of a string descriptor describing the configuration */
+    uint8_t  bmAttributes;                /*!< configuration attributes */
+    uint8_t  bMaxPower;                   /*!< maximum power consumption of the device while in the current configuration */
+} usb_descriptor_configuration_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size */
+
+    uint8_t bInterfaceNumber;             /*!< index of the interface in the current configuration */
+    uint8_t bAlternateSetting;            /*!< alternate setting for the interface number */
+    uint8_t bNumEndpoints;                /*!< total number of endpoints in the interface */
+    uint8_t bInterfaceClass;              /*!< interface class ID */
+    uint8_t bInterfaceSubClass;           /*!< interface subclass ID */
+    uint8_t bInterfaceProtocol;           /*!< interface protocol ID */
+    uint8_t iInterface;                   /*!< index of the string descriptor describing the interface */
+} usb_descriptor_interface_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size. */
+
+    uint8_t  bEndpointAddress;            /*!< logical address of the endpoint */
+    uint8_t  bmAttributes;                /*!< endpoint attributes */
+    uint16_t wMaxPacketSize;              /*!< size of the endpoint bank, in bytes */
+    uint8_t  bInterval;                   /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */
+} usb_descriptor_endpoint_struct;
+
+typedef struct
+{
+    usb_descriptor_header_struct Header;  /*!< descriptor header, including type and size. */
+    uint16_t wLANGID;                     /*!< LANGID code */
+}usb_descriptor_language_id_struct;
+
+#pragma pack()
+
+#endif /* USB_STD_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_core.h

@@ -0,0 +1,54 @@
+/*!
+    \file  usbd_core.h
+    \brief USB device mode core driver header file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+
+#ifndef USBD_CORE_H
+#define USBD_CORE_H
+
+#include "usbd_conf.h"
+#include "usb_core.h"
+#include "usbd_std.h"
+
+/* device status */
+#define USB_STATUS_DEFAULT                          1U     /* default status */
+#define USB_STATUS_ADDRESSED                        2U     /* addressed status */
+#define USB_STATUS_CONFIGURED                       3U     /* configured status */
+#define USB_STATUS_SUSPENDED                        4U     /* suspended status */
+
+/* function declarations */
+/* initailizes the USB device-mode handler stack */
+void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
+/* endpoint initialization */
+void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc);
+/* endpoint deinitialize */
+void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr);
+/* endpoint prepare to receive data */
+void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
+/* endpoint prepare to transmit data */
+void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
+/* transmit data on the control channel */
+usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
+/* receive data on the control channel */
+usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
+/* transmit status on the control channel */
+usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev);
+/* receive status on the control channel */
+usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev);
+/* set an endpoint to STALL status */
+void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
+/* clear endpoint stalled status */
+void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
+/* flushes the FIFOs */
+void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr);
+/* get the received data length */
+uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num);
+
+#endif /* USBD_CORE_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_int.h

@@ -0,0 +1,29 @@
+/*!
+    \file  usbd_int.h
+    \brief USB device mode interrupt handler header file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBD_INT_H
+#define USBD_INT_H
+
+#include "usbd_core.h"
+
+typedef struct
+{
+    uint8_t (*SOF) (usb_core_handle_struct *pudev);
+}usbd_int_cb_struct;
+
+extern usbd_int_cb_struct *usbd_int_fops;
+
+/* function declarations */
+/* USB device-mode interrupts global service routine handler */
+uint32_t usbd_isr (usb_core_handle_struct *pudev);
+
+#endif /* USBD_INT_H */
+

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_std.h

@@ -0,0 +1,70 @@
+/*!
+    \file  usbd_std.h
+    \brief USB 2.0 standard defines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBD_STD_H
+#define USBD_STD_H
+
+#include "usb_std.h"
+#include "usbd_core.h"
+#include "usbd_conf.h"
+#include <wchar.h>
+
+#define USBD_LANGID_STR_IDX                            0x00U     /*!< USB language ID string index*/
+#define USBD_MFC_STR_IDX                               0x01U     /*!< USB manufacturer string index*/
+#define USBD_PRODUCT_STR_IDX                           0x02U     /*!< USB product string index*/
+#define USBD_SERIAL_STR_IDX                            0x03U     /*!< USB serial string index*/
+#define USBD_CONFIG_STR_IDX                            0x04U     /*!< USB configuration string index*/
+#define USBD_INTERFACE_STR_IDX                         0x05U     /*!< USB interface string index*/
+
+#define USB_STATUS_REMOTE_WAKEUP                       0x02U     /*!< USB remote wakeup status*/
+#define USB_STATUS_SELF_POWERED                        0x01U     /*!< USB self power status*/
+
+#define USB_FEATURE_ENDP_HALT                          0x00U     /*!< USB halt endpoint feature*/
+#define USB_FEATURE_REMOTE_WAKEUP                      0x01U     /*!< USB remote wakeup feature*/
+#define USB_FEATURE_TEST_MODE                          0x02U     /*!< USB test mode feature*/
+
+#define ENG_LANGID                                     0x0409U   /*!< USB english language id*/
+#define CHN_LANGID                                     0x0804U   /*!< USB chinese language id*/
+
+#define USB_DEVICE_DESC_SIZE                           0x12U     /*!< USB device descriptor size*/
+
+#define LOWBYTE(x)           ((uint8_t)((x) & 0x00FFU))          /*!< USB lowbyte operation marco*/
+#define HIGHBYTE(x)          ((uint8_t)(((x) & 0xFF00U) >> 8U))  /*!< USB highbyte operation marco*/
+
+#define USB_MIN(a, b)        (((a) < (b)) ? (a) : (b))           /*!< USB minimum operation marco*/
+
+#define WIDE_STRING(string)  _WIDE_STRING(string)
+#define _WIDE_STRING(string) L##string
+
+#define USBD_STRING_DESC(string) \
+    (uint8_t *)&(struct { \
+        uint8_t _len; \
+        uint8_t _type; \
+        wchar_t _data[sizeof(string)]; \
+    }) { \
+        sizeof(WIDE_STRING(string)) + 2U - 2U, \
+        USB_DESCTYPE_STRING, \
+        WIDE_STRING(string) \
+    }
+
+#define IS_NOT_EP0(ep_addr)   (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
+
+/* function declarations */
+/* USB device setup transaction*/
+usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev);
+/* USB device out transaction*/
+usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
+/* USB device in transaction*/
+usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
+/* USB device enum error handle*/
+void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req);
+
+#endif /* USBD_STD_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_ctrl.h

@@ -0,0 +1,45 @@
+/*!
+    \file  usbh_ctrl.h
+    \brief header file for usbh_ctrl.c
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBH_CTRL_H
+#define USBH_CTRL_H
+
+#include "usbh_core.h"
+#include "usbh_usr.h"
+
+#define CTRL_HANDLE_TABLE_SIZE   13U    /*!< the ctrl handle table size define */
+
+extern state_table_struct        ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE];
+extern uint8_t                   ctrl_polling_handle_flag;
+
+/* the enum of CTRL event */
+typedef enum 
+{
+    CTRL_EVENT_IDLE = 0,   /* the ctrl idle event */
+    CTRL_EVENT_SETUP,      /* the ctrl setup event */
+    CTRL_EVENT_DATA,       /* the ctrl data event */
+    CTRL_EVENT_STATUS,     /* the ctrl status event */
+    CTRL_EVENT_COMPLETE,   /* the ctrl complete event */
+    CTRL_EVENT_ERROR,      /* the ctrl error event */
+    CTRL_EVENT_STALLED,    /* the ctrl stalled event */
+}ctrl_event_enum;
+
+/* function declarations */
+/* the polling function of control transfer state handle */
+usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
+/* send datas from the host channel */
+usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t  hc_num, uint16_t len);
+/* send the setup packet to the device */
+usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t  hc_num);
+/* this function prepare a hc and start a transfer */
+uint32_t  hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num);
+
+#endif /* USBH_CTRL_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_hcs.h

@@ -0,0 +1,46 @@
+/*!
+    \file  usbh_hcs.h
+    \brief header file for usbh_hcs.c
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBH_HCS_H
+#define USBH_HCS_H
+
+#include "usbh_core.h"
+
+#define HC_MAX                  8U
+
+#define HC_OK                   0x0000U
+#define HC_USED                 0x8000U
+#define HC_ERROR                0xFFFFU
+#define HC_USED_MASK            0x7FFFU
+
+/* function declarations */
+/* allocate a new channel for the pipe */
+uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr);
+/* free all usb host channel */
+uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev);
+/* free the usb host channel */
+uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index);
+/* open a channel */
+uint8_t usbh_channel_open (usb_core_handle_struct *pudev, 
+                           uint8_t  channel_num,
+                           uint8_t  dev_addr,
+                           uint8_t  dev_speed,
+                           uint8_t  ep_type,
+                           uint16_t ep_mps);
+/* modify a channel */
+uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
+                             uint8_t  channel_num,
+                             uint8_t  dev_addr,
+                             uint8_t  dev_speed,
+                             uint8_t  ep_type,
+                             uint16_t ep_mps);
+
+#endif /* USBH_HCS_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_int.h

@@ -0,0 +1,30 @@
+/*!
+    \file  usbh_int.h
+    \brief USB host mode interrupt handler header file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBH_INT_H
+#define USBH_INT_H
+
+#include "usb_core.h"
+
+typedef struct
+{
+    uint8_t (*sof)                  (usb_core_handle_struct *pudev);
+    uint8_t (*device_connected)     (usb_core_handle_struct *pudev);
+    uint8_t (*device_disconnected)  (usb_core_handle_struct *pudev);
+}usbh_hcd_int_cb_struct;
+
+extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops;
+
+/* function declarations */
+/* handle global host interrupt */
+uint32_t usbh_isr (usb_core_handle_struct *pudev);
+
+#endif /* USBH_INT_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_std.h

@@ -0,0 +1,74 @@
+/*!
+    \file  usbh_std.h
+    \brief header file for usbh_std.c
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#ifndef USBH_STD_H
+#define USBH_STD_H
+
+#include "usbh_core.h"
+#include "usbh_usr.h"
+
+/* standard feature selector for clear feature command */
+#define FEATURE_SELECTOR_ENDPOINT      0x00U
+#define FEATURE_SELECTOR_DEVICE        0x01U
+
+#define USBH_SETUP_PACKET_SIZE         8U      /* setup packet size */
+#define ENUM_HANDLE_TABLE_SIZE         10U     /* enumerate handle table size */
+
+extern uint8_t                         usbh_cfg_desc[512];
+extern uint8_t                         enum_polling_handle_flag;
+extern state_table_struct              enum_handle_table[ENUM_HANDLE_TABLE_SIZE];
+
+typedef enum 
+{
+    ENUN_EVENT_IDLE = 0,                   /* the enum idle event */
+    ENUM_EVENT_SET_ADDR,                   /* the enum set address event */
+    ENUN_EVENT_GET_FULL_DEV_DESC,          /* the enum get full device descripter event */
+    ENUN_EVENT_GET_CFG_DESC,               /* the enum get congiguration descripter event */
+    ENUN_EVENT_GET_FULL_CFG_DESC,          /* the enum get full configuration descripter event */
+    ENUN_EVENT_GET_MFC_STRING_DESC,        /* the enum get MFC string descripter event */
+    ENUN_EVENT_GET_PRODUCT_STRING_DESC,    /* the enum get product string event */
+    ENUN_EVENT_GET_SERIALNUM_STRING_DESC,  /* the enum get serialnum string event */
+    ENUN_EVENT_SET_CONFIGURATION,          /* the enum set configuration event */
+    ENUN_EVENT_DEV_CONFIGURED              /* the enum device configured event */
+}enum_event_enum;
+
+/* function declarations */
+/* the polling function of enumeration state */
+usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
+/* get descriptor in usb host enumeration stage */
+void usbh_enum_desc_get (usb_core_handle_struct *pudev, 
+                         usbh_host_struct *puhost, 
+                         uint8_t *buf, 
+                         uint8_t  req_type, 
+                         uint16_t value_idx, 
+                         uint16_t len);
+/* set address in usb host enumeration stage */
+void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address);
+/* set configuration in usb host enumeration stage */
+void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx);
+/* parse the device descriptor */
+void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len);
+/* parse the configuration descriptor */
+void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
+                          usb_descriptor_interface_struct *itf_desc,
+                          usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
+                          uint8_t *buf,
+                          uint16_t len);
+/* parse the interface descriptor */
+void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf);
+/* parse the endpoint descriptor */
+void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf);
+/* parse the string descriptor */
+void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
+/* get the next descriptor header */
+usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr);
+
+#endif /* USBH_STD_H */

bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_hcs.c

@@ -0,0 +1,158 @@
+/*!
+    \file  usbh_hcs.c
+    \brief this file implements functions for opening and closing host channels
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2017-02-10, V1.0.0, firmware for GD32F30x
+*/
+
+#include "usbh_hcs.h"
+
+static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev);
+
+/*!
+    \brief      open a channel
+    \param[in]  pudev: pointer to usb device
+    \param[in]  channel_num: host channel number which is in (0..7)
+    \param[in]  dev_addr: USB device address allocated to attached device
+    \param[in]  dev_speed: USB device speed (Full speed/Low speed)
+    \param[in]  ep_type: endpoint type (bulk/int/ctl)
+    \param[in]  ep_mps: max packet size
+    \param[out] none
+    \retval     operation status
+*/
+uint8_t usbh_channel_open (usb_core_handle_struct *pudev, 
+                           uint8_t  channel_num,
+                           uint8_t  dev_addr,
+                           uint8_t  dev_speed,
+                           uint8_t  ep_type,
+                           uint16_t ep_mps)
+{
+    usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
+    uint16_t channel_info = puhc->info;
+
+    puhc->endp_id   = (uint8_t)channel_info & 0x7FU;
+    puhc->endp_in   = (uint8_t)(channel_info & 0x80U) >> 7;
+    puhc->endp_type = ep_type;
+    puhc->endp_mps  = ep_mps;
+    puhc->dev_addr  = dev_addr;
+    puhc->dev_speed = dev_speed;
+
+    puhc->data_tg_in  = 0U;
+    puhc->data_tg_out = 0U;
+
+    usb_hostchannel_init(pudev, channel_num);
+
+    return (uint8_t)HC_OK;
+}
+
+/*!
+    \brief      modify a channel
+    \param[in]  pudev: pointer to usb device
+    \param[in]  channel_num: host channel number which is in (0..7)
+    \param[in]  dev_addr: USB Device address allocated to attached device
+    \param[in]  dev_speed: USB device speed (Full speed/Low speed)
+    \param[in]  ep_type: endpoint type (bulk/int/ctl)
+    \param[in]  ep_mps: max packet size
+    \param[out] none
+    \retval     operation status
+*/
+uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
+                             uint8_t  channel_num,
+                             uint8_t  dev_addr,
+                             uint8_t  dev_speed,
+                             uint8_t  ep_type,
+                             uint16_t ep_mps)
+{
+    usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
+
+    if (0U != dev_addr) {
+        puhc->dev_addr = dev_addr;
+    }
+
+    if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
+        puhc->endp_mps = ep_mps; 
+    }
+
+    if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
+        puhc->dev_speed = dev_speed;
+    }
+
+    usb_hostchannel_init(pudev, channel_num);
+
+    return (uint8_t)HC_OK;
+}
+
+/*!
+    \brief      allocate a new channel for the pipe
+    \param[in]  pudev: pointer to usb device
+    \param[in]  ep_addr: endpoint for which the channel to be allocated
+    \param[out] none
+    \retval     host channel number
+*/
+uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
+{
+    uint16_t hc_num = usbh_freechannel_get(pudev);
+
+    if ((uint16_t)HC_ERROR != hc_num) {
+        pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
+    }
+
+    return (uint8_t)hc_num;
+}
+
+/*!
+    \brief      free the usb host channel
+    \param[in]  pudev: pointer to usb device
+    \param[in]  index: channel number to be freed  which is in (0..7)
+    \param[out] none
+    \retval     host operation status
+*/
+uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
+{
+    if (index < HC_MAX) {
+        pudev->host.host_channel[index].info &= HC_USED_MASK;
+    }
+
+    return USBH_OK;
+}
+
+/*!
+    \brief      free all usb host channel
+    \param[in]  pudev: pointer to usb device
+    \param[out] none
+    \retval     host operation status
+*/
+uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
+{
+    uint8_t index;
+
+    for (index = 2U; index < HC_MAX; index ++) {
+        pudev->host.host_channel[index].info = 0U;
+    }
+
+    return USBH_OK;
+}
+
+/*!
+    \brief      get a free channel number for allocation to a device endpoint
+    \param[in]  pudev: pointer to usb device
+    \param[out] none
+    \retval     free channel number
+*/
+static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev)
+{
+    uint8_t index = 0U;
+
+    for (index = 0U; index < HC_MAX; index++) {
+        if (0U == (pudev->host.host_channel[index].info & HC_USED)) {
+            return (uint16_t)index;
+        }
+    }
+
+    return HC_ERROR;
+}
+

bsp/gd32303e-eval/Libraries/SConscript

@@ -0,0 +1,36 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('GD32F30x_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    print('=================================================')
+    print('Not support gcc yet !')
+    print('=================================================')
+    exit(0)
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s']
+
+path = [
+    cwd + '/CMSIS/GD/GD32F30x/Include',
+    cwd + '/CMSIS',
+    cwd + '/GD32F30x_standard_peripheral/Include',]
+    
+if GetDepend(['RT_USING_BSP_USB']):
+    path += [cwd + '/GD32F30x_usb_driver/Include']
+    src  += [cwd + '/GD32F30x_usb_driver/Source']
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F30X_HD']
+
+group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/gd32303e-eval/README.md

@@ -0,0 +1,93 @@
+# GD32303E-EVAL #
+
+## 1. 简介
+
+[GD32303E-EVAL](http://gd32mcu.21ic.com/site)是兆易科技提供的开发板，使用 GD32F303ZET6 作为主控制器。提供包括扩展引脚在内的及 SWD, Reset, Boot, User button key, LED, CAN, I2C, I2S, USART, RTC, LCD, SPI, ADC, DAC, EXMC, CTC, SDIO,USBD, GD-Link 等外设资源。
+
+板载主要资源如下：
+
+| 硬件 | 描述 |
+| -- | -- |
+|CPU| Cortex-M4|
+|主频| 120MHz |
+|SRAM| 64KB |
+|Flash| 512KB |
+
+## 2. 编译说明
+
+GD32303E-EVAL板级包支持MDK5和IAR。
+| IDE/编译器 | 已测试版本                   |
+| ---------- | ---------------------------- |
+| MDK5       | MDK5.25                      |
+| IAR        | IAR8.20             |
+
+## 3. 烧写及执行
+
+供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。
+
+下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。
+
+串口连接：可使用USB转串口线连接开发板串口0的PA9和PA10引脚。
+
+解决IDE "Missing Device(s)"问题"
+* MDK5: 安装GigaDevice.GD32F30x_AddOn.1.0.1.exe，在 Folder Selection 中的 Destination Folder 那一栏选择 Keil uVision5 软件的安装目录，如 C:\Keil_v5，然后在 Option for Target 的 Device 选择对应的器件，同时在 Option forTarget 的 C/C++中添加路径 C:\Keil_v5\ARM\Pack\ARM\CMSIS\4.2.0\CMSIS\Include。
+
+* IAR：安装 IAR_GD32F30x_ADDON.1.0.0.exe
+
+### 3.1 配置和仿真
+
+工程已经默认使能了RT-Thread UART驱动、GPIO驱动、SPI驱动、I2C驱动。若想进一步配置工程请
+使用ENV工具。
+
+### 3.2 运行结果
+
+打开MDK或者IAR工程，进入仿真后全速运行，将会在终端设备putty上看到RT-Thread的启动logo信息：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.0.3 build Apr 26 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh />
+
+```
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0/1/2/3/4 |
+| GPIO | 支持 |  |
+| SPI | 支持 | SPI0/1/2 |
+| I2C | 支持 | I2C0/1|
+
+### 4.1 IO在板级支持包中的映射情况
+
+| IO号 | 板级包中的定义 |
+| -- | -- |
+| PA9 | USART0 TX |
+| PA10 | USART0 RX |
+| PA2 | USART1 TX |
+| PA3 | USART1 RX |
+| PA5| SPI0 SCK |
+| PA6 | SPI0 MISO |
+| PA6 | SPI0 MOSI |
+| PB13| SPI1 SCK |
+| PB14 | SPI1 MISO |
+| PB15 | SPI1 MOSI |
+| PB6| I2C0 SCL |
+| PB7 | I2C0 SDA |
+| PB10| I2C1 SCL |
+| PB11 | I2C1 SDA |
+
+## 5. 联系人信息
+
+维护人：
+
+- [misonyo](https://github.com/misonyo)
+
+## 6. 参考
+
+* [GD32303E-EVAL](http://gd32mcu.21ic.com/site)
+
+

bsp/gd32303e-eval/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/gd32303e-eval/SConstruct

@@ -0,0 +1,39 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/gd32303e-eval/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/gd32303e-eval/applications/main.c

@@ -0,0 +1,27 @@
+/*
+ * File      : main.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-07-29     Arda.Fu      first implementation
+ */
+#include <rtthread.h>
+#include <board.h>
+
+int main(void)
+{
+  /* user app entry */
+
+  return 0;
+}
+
+
+
+
+

bsp/gd32303e-eval/drivers/SConscript

@@ -0,0 +1,33 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drivers.
+src = Split("""
+board.c
+drv_usart.c
+""")
+
+CPPPATH = [cwd]
+
+# add spi drivers.
+if GetDepend('RT_USING_SPI'):
+    src += ['drv_spi.c']
+    
+# add i2c drivers.
+if GetDepend('RT_USING_I2C'):
+    src += ['drv_i2c.c']
+
+# add pin drivers.
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add spi flash drivers.
+if GetDepend('RT_USING_SFUD'):
+    src += ['drv_spi_flash.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')