mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-08-18 20:48:41 +08:00
Merge pull request #4702 from OpenNuvoton/nuvoton
[nuvoton] Support M031 Series.
This commit is contained in:
Bernard Xiong
@@ -9,3 +9,4 @@ Current supported BSP shown in below table:
|
||||
| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
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| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
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| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |
|
||||
| [numaker-m032ki](numaker-m032ki) | Nuvoton NuMaker-M032KI |
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|
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@@ -0,0 +1,136 @@
|
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/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. October 2015
|
||||
* $Revision: V.1.4.5 a
|
||||
*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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||||
*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
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||||
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||||
#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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/* extern const q31_t realCoefAQ31[1024]; */
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/* extern const q31_t realCoefBQ31[1024]; */
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extern const float32_t twiddleCoef_16[32];
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extern const float32_t twiddleCoef_32[64];
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extern const float32_t twiddleCoef_64[128];
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extern const float32_t twiddleCoef_128[256];
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extern const float32_t twiddleCoef_256[512];
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extern const float32_t twiddleCoef_512[1024];
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extern const float32_t twiddleCoef_1024[2048];
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extern const float32_t twiddleCoef_2048[4096];
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extern const float32_t twiddleCoef_4096[8192];
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#define twiddleCoef twiddleCoef_4096
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extern const q31_t twiddleCoef_16_q31[24];
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extern const q31_t twiddleCoef_32_q31[48];
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extern const q31_t twiddleCoef_64_q31[96];
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extern const q31_t twiddleCoef_128_q31[192];
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extern const q31_t twiddleCoef_256_q31[384];
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extern const q31_t twiddleCoef_512_q31[768];
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extern const q31_t twiddleCoef_1024_q31[1536];
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extern const q31_t twiddleCoef_2048_q31[3072];
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extern const q31_t twiddleCoef_4096_q31[6144];
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extern const q15_t twiddleCoef_16_q15[24];
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extern const q15_t twiddleCoef_32_q15[48];
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extern const q15_t twiddleCoef_64_q15[96];
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extern const q15_t twiddleCoef_128_q15[192];
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extern const q15_t twiddleCoef_256_q15[384];
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extern const q15_t twiddleCoef_512_q15[768];
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extern const q15_t twiddleCoef_1024_q15[1536];
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extern const q15_t twiddleCoef_2048_q15[3072];
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extern const q15_t twiddleCoef_4096_q15[6144];
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extern const float32_t twiddleCoef_rfft_32[32];
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extern const float32_t twiddleCoef_rfft_64[64];
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extern const float32_t twiddleCoef_rfft_128[128];
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extern const float32_t twiddleCoef_rfft_256[256];
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extern const float32_t twiddleCoef_rfft_512[512];
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extern const float32_t twiddleCoef_rfft_1024[1024];
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extern const float32_t twiddleCoef_rfft_2048[2048];
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extern const float32_t twiddleCoef_rfft_4096[4096];
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||||
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||||
/* floating-point bit reversal tables */
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#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
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#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
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||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
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||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
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#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
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||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
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||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
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||||
|
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extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
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||||
|
||||
/* fixed-point bit reversal tables */
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||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
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||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
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||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
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||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
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||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
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#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
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||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
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#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
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||||
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||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
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||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
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|
||||
/* Tables for Fast Math Sine and Cosine */
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extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
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||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
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||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@@ -0,0 +1,79 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. March 2015
|
||||
* $Revision: V.1.4.5
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
*
|
||||
* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
||||
* arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
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||||
#define _ARM_CONST_STRUCTS_H
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||||
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||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
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||||
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||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
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||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
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||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
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||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
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||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
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||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
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||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
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||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
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||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
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@@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
@@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
""")
|
||||
|
||||
path = [cwd + '/Include',]
|
||||
|
||||
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,17 @@
|
||||
/**************************************************************************//**
|
||||
* @file NuMicro.h
|
||||
* @version V1.00
|
||||
* @brief NuMicro peripheral access layer header file.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NUMICRO_H__
|
||||
#define __NUMICRO_H__
|
||||
|
||||
#include "nutool_clkcfg.h"
|
||||
#include "M031Series.h"
|
||||
|
||||
#endif /* __NUMICRO_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,255 @@
|
||||
/**************************************************************************//**
|
||||
* @file acmp_reg.h
|
||||
* @version V1.00
|
||||
* @brief ACMP register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ACMP_REG_H__
|
||||
#define __ACMP_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup ACMP Analog Comparator Controller (ACMP)
|
||||
Memory Mapped Structure for ACMP Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var ACMP_T::CTL
|
||||
* Offset: 0x00/0x04 Analog Comparator 0/1 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACMPEN |Comparator Enable Bit
|
||||
* | | |0 = Comparator 0 Disabled.
|
||||
* | | |1 = Comparator 0 Enabled.
|
||||
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
|
||||
* | | |0 = Comparator 0 interrupt Disabled.
|
||||
* | | |1 = Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
|
||||
* |[3] |ACMPOINV |Comparator Output Inverse
|
||||
* | | |0 = Comparator 0 output inverse Disabled.
|
||||
* | | |1 = Comparator 0 output inverse Enabled.
|
||||
* |[5:4] |NEGSEL |Comparator Negative Input Selection
|
||||
* | | |00 = ACMP0_N pin.
|
||||
* | | |01 = Internal comparator reference voltage (CRV).
|
||||
* | | |10 = Band-gap voltage.
|
||||
* | | |11 = Reserved.
|
||||
* |[7:6] |POSSEL |Comparator Positive Input Selection
|
||||
* | | |00 = Input from ACMP0_P0.
|
||||
* | | |01 = Input from ACMP0_P1.
|
||||
* | | |10 = Input from ACMP0_P2.
|
||||
* | | |11 = Input from ACMP0_P3.
|
||||
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
|
||||
* | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
|
||||
* | | |00 = Rising edge or falling edge.
|
||||
* | | |01 = Rising edge.
|
||||
* | | |10 = Falling edge.
|
||||
* | | |11 = Reserved.
|
||||
* |[12] |OUTSEL |Comparator Output Select
|
||||
* | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
|
||||
* | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
|
||||
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
|
||||
* | | |000 = Filter function is Disabled.
|
||||
* | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
|
||||
* | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
|
||||
* | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
|
||||
* | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
|
||||
* | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
|
||||
* | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
|
||||
* | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
|
||||
* |[16] |WKEN |Power-down Wake-up Enable Bit
|
||||
* | | |0 = Wake-up function Disabled.
|
||||
* | | |1 = Wake-up function Enabled.
|
||||
* |[17] |WLATEN |Window Latch Mode Enable Bit
|
||||
* | | |0 = Window Latch Mode Disabled.
|
||||
* | | |1 = Window Latch Mode Enabled.
|
||||
* |[18] |WCMPSEL |Window Compare Mode Selection
|
||||
* | | |0 = Window Compare Mode Disabled.
|
||||
* | | |1 = Window Compare Mode is Selected.
|
||||
* @var ACMP_T::STATUS
|
||||
* Offset: 0x08 Analog Comparator Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
|
||||
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
|
||||
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
|
||||
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[4] |ACMPO0 |Comparator 0 Output
|
||||
* | | |Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
|
||||
* |[5] |ACMPO1 |Comparator 1 Output
|
||||
* | | |Synchronized to the PCLK to allow reading by software
|
||||
* | | |Cleared when the comparator 1 is disabled, i.e
|
||||
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
|
||||
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
|
||||
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
|
||||
* | | |0 = No power-down wake-up occurred.
|
||||
* | | |1 = Power-down wake-up occurred.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
|
||||
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
|
||||
* | | |0 = No power-down wake-up occurred.
|
||||
* | | |1 = Power-down wake-up occurred.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[12] |ACMPS0 |Comparator 0 Status
|
||||
* | | |Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
|
||||
* |[13] |ACMPS1 |Comparator 1 Status
|
||||
* | | |Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
|
||||
* |[16] |ACMPWO |Comparator Window Output
|
||||
* | | |This bit shows the output status of window compare mode.
|
||||
* | | |0 = The positive input voltage is outside the window.
|
||||
* | | |1 = The positive input voltage is in the window.
|
||||
* @var ACMP_T::VREF
|
||||
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
|
||||
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
|
||||
* |[6] |CRVSSEL |CRV Source Voltage Selection
|
||||
* | | |0 = AVDD is selected as CRV source voltage.
|
||||
* | | |1 = VREF is selected as as CRV source voltage.
|
||||
*/
|
||||
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
|
||||
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
|
||||
__IO uint32_t CALCTL; /*!< [0x0010] Analog Comparator Calibration Control Register */
|
||||
__I uint32_t CALSR; /*!< [0x0014] Analog Comparator Calibration Status Register */
|
||||
|
||||
} ACMP_T;
|
||||
|
||||
/**
|
||||
@addtogroup ACMP_CONST ACMP Bit Field Definition
|
||||
Constant Definitions for ACMP Controller
|
||||
@{ */
|
||||
|
||||
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
|
||||
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
|
||||
|
||||
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
|
||||
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
|
||||
|
||||
#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
|
||||
#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
|
||||
|
||||
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
|
||||
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
|
||||
|
||||
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
|
||||
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
|
||||
|
||||
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
|
||||
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
|
||||
|
||||
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
|
||||
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
|
||||
|
||||
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
|
||||
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
|
||||
|
||||
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
|
||||
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
|
||||
|
||||
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
|
||||
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
|
||||
|
||||
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
|
||||
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
|
||||
|
||||
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
|
||||
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
|
||||
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
|
||||
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
|
||||
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
|
||||
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
|
||||
|
||||
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
|
||||
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
|
||||
|
||||
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
|
||||
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
|
||||
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
|
||||
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
|
||||
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
|
||||
|
||||
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
|
||||
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
|
||||
|
||||
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
|
||||
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALTRG0_Pos (0) /*!< ACMP_T::CALCTL: CALTRG0 Position */
|
||||
#define ACMP_CALCTL_CALTRG0_Msk (0x1ul << ACMP_CALCTL_CALTRG0_Pos) /*!< ACMP_T::CALCTL: CALTRG0 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALTRG1_Pos (1) /*!< ACMP_T::CALCTL: CALTRG1 Position */
|
||||
#define ACMP_CALCTL_CALTRG1_Msk (0x1ul << ACMP_CALCTL_CALTRG1_Pos) /*!< ACMP_T::CALCTL: CALTRG1 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALCLK0_Pos (4) /*!< ACMP_T::CALCTL: CALCLK0 Position */
|
||||
#define ACMP_CALCTL_CALCLK0_Msk (0x3ul << ACMP_CALCTL_CALCLK0_Pos) /*!< ACMP_T::CALCTL: CALCLK0 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALCLK1_Pos (6) /*!< ACMP_T::CALCTL: CALCLK1 Position */
|
||||
#define ACMP_CALCTL_CALCLK1_Msk (0x3ul << ACMP_CALCTL_CALCLK1_Pos) /*!< ACMP_T::CALCTL: CALCLK1 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALRVS0_Pos (16) /*!< ACMP_T::CALCTL: CALRVS0 Position */
|
||||
#define ACMP_CALCTL_CALRVS0_Msk (0x1ul << ACMP_CALCTL_CALRVS0_Pos) /*!< ACMP_T::CALCTL: CALRVS0 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALRVS1_Pos (17) /*!< ACMP_T::CALCTL: CALRVS1 Position */
|
||||
#define ACMP_CALCTL_CALRVS1_Msk (0x1ul << ACMP_CALCTL_CALRVS1_Pos) /*!< ACMP_T::CALCTL: CALRVS1 Mask */
|
||||
|
||||
#define ACMP_CALSR_DONE0_Pos (0) /*!< ACMP_T::CALSR: DONE0 Position */
|
||||
#define ACMP_CALSR_DONE0_Msk (0x1ul << ACMP_CALSR_DONE0_Pos) /*!< ACMP_T::CALSR: DONE0 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALNS0_Pos (1) /*!< ACMP_T::CALSR: CALNS0 Position */
|
||||
#define ACMP_CALSR_CALNS0_Msk (0x1ul << ACMP_CALSR_CALNS0_Pos) /*!< ACMP_T::CALSR: CALNS0 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALPS0_Pos (2) /*!< ACMP_T::CALSR: CALPS0 Position */
|
||||
#define ACMP_CALSR_CALPS0_Msk (0x1ul << ACMP_CALSR_CALPS0_Pos) /*!< ACMP_T::CALSR: CALPS0 Mask */
|
||||
|
||||
#define ACMP_CALSR_DONE1_Pos (4) /*!< ACMP_T::CALSR: DONE1 Position */
|
||||
#define ACMP_CALSR_DONE1_Msk (0x1ul << ACMP_CALSR_DONE1_Pos) /*!< ACMP_T::CALSR: DONE1 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALNS1_Pos (5) /*!< ACMP_T::CALSR: CALNS1 Position */
|
||||
#define ACMP_CALSR_CALNS1_Msk (0x1ul << ACMP_CALSR_CALNS1_Pos) /*!< ACMP_T::CALSR: CALNS1 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALPS1_Pos (6) /*!< ACMP_T::CALSR: CALPS1 Position */
|
||||
#define ACMP_CALSR_CALPS1_Msk (0x1ul << ACMP_CALSR_CALPS1_Pos) /*!< ACMP_T::CALSR: CALPS1 Mask */
|
||||
|
||||
/**@}*/ /* ACMP_CONST */
|
||||
/**@}*/ /* end of ACMP register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __ACMP_REG_H__ */
|
||||
@@ -0,0 +1,400 @@
|
||||
/**************************************************************************//**
|
||||
* @file adc_reg.h
|
||||
* @version V1.00
|
||||
* @brief ADC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ADC_REG_H__
|
||||
#define __ADC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup ADC Analog to Digital Converter (ADC)
|
||||
Memory Mapped Structure for ADC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var ADC_T::ADDR
|
||||
* Offset: 0x00-0x74 ADC Data Register 0-29
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |RSLT |A/D Conversion Result (Read Only)
|
||||
* | | |This field contains conversion result of ADC.
|
||||
* |[16] |OVERRUN |Overrun Flag (Read Only)
|
||||
* | | |If converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read.
|
||||
* | | |0 = Data in RSLT bits is not overwrote.
|
||||
* | | |1 = Data in RSLT bits is overwrote.
|
||||
* |[17] |VALID |Valid Flag (Read Only)
|
||||
* | | |This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.
|
||||
* | | |0 = Data in RSLT bits is not valid.
|
||||
* | | |1 = Data in RSLT bits is valid.
|
||||
* @var ADC_T::ADCR
|
||||
* Offset: 0x80 ADC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ADEN |A/D Converter Enable Bit
|
||||
* | | |0 = A/D converter Disabled.
|
||||
* | | |1 = A/D converter Enabled.
|
||||
* | | |Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
|
||||
* |[1] |ADIE |A/D Interrupt Enable Bit
|
||||
* | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1.
|
||||
* | | |0 = A/D interrupt function Disabled.
|
||||
* | | |1 = A/D interrupt function Enabled.
|
||||
* |[3:2] |ADMD |A/D Converter Operation Mode Control
|
||||
* | | |00 = Single conversion.
|
||||
* | | |01 = Burst conversion.
|
||||
* | | |10 = Single-cycle Scan.
|
||||
* | | |11 = Continuous Scan.
|
||||
* | | |Note1: When changing the operation mode, software should clear ADST bit first.
|
||||
* | | |Note2: In Burst mode, the A/D result data is always at ADC Data Register 0.
|
||||
* |[5:4] |TRGS |Hardware Trigger Source
|
||||
* | | |00 = A/D conversion is started by external STADC pin.
|
||||
* | | |01 = Timer0 ~ Timer3 overflow pulse trigger.
|
||||
* | | |10 = Reserved.
|
||||
* | | |11 = A/D conversion is started by PWM trigger.
|
||||
* | | |Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
|
||||
* |[7:6] |TRGCOND |External Trigger Condition
|
||||
* | | |These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.
|
||||
* | | |00 = Low level.
|
||||
* | | |01 = High level.
|
||||
* | | |10 = Falling edge.
|
||||
* | | |11 = Rising edge.
|
||||
* |[8] |TRGEN |External Trigger Enable Bit
|
||||
* | | |Enable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.
|
||||
* | | |0 = External trigger Disabled.
|
||||
* | | |1 = External trigger Enabled.
|
||||
* | | |Note: The ADC external trigger function is only supported in Single-cycle Scan mode.
|
||||
* |[9] |PTEN |PDMA Transfer Enable Bit
|
||||
* | | |When A/D conversion is completed, the converted data is loaded into ADDR0~15, ADDR29. Software can enable this bit to generate a PDMA data transfer request.
|
||||
* | | |0 = PDMA data transfer Disabled.
|
||||
* | | |1 = PDMA data transfer in ADDR0~15, ADDR29 Enabled.
|
||||
* | | |Note: When PTEN=1, software must set ADIE=0 to disable interrupt.
|
||||
* |[10] |DIFFEN |Differential Input Mode Control
|
||||
* | | |Differential input voltage (Vdiff) = Vplus - Vminus.
|
||||
* | | |The relation between Vplus and Vminus is Vplus + Vminus = Vref.
|
||||
* | | |The Vplus of differential input paired channel x is from ADC0_CHy pin; Vminus is from ADC0_CHz pin, x=0,1..7, y=2*x, z=y+1.
|
||||
* | | |0 = Single-end analog input mode.
|
||||
* | | |1 = Differential analog input mode.
|
||||
* | | |Note: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
|
||||
* |[11] |ADST |A/D Conversion Start or Calibration Start
|
||||
* | | |ADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode, Single-cycle Scan mode and Calibration mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
|
||||
* | | |0 = Conversion stops and A/D converter enters idle state.
|
||||
* | | |1 = Conversion starts or Calibration Start.
|
||||
* | | |Note1: When ADST become from 1 to 0, ADC macro will reset to initial state. After macro reset to initial state, user should wait at most 2 ADC clock and set this bit to start next conversion.
|
||||
* | | |Note2: Calibration Start only if CALEN (ADC_ADCALR[0]) = 1.
|
||||
* |[12] |RESET |ADC RESET (Write Protect)
|
||||
* | | |If user writes this bit, the ADC analog macro will reset
|
||||
* | | |Calibration data in macro will be deleted, but registers in ADC controller will keep.
|
||||
* | | |Note: This bit is cleared by hardware.
|
||||
* |[31] |DMOF |Differential Input Mode Output Format
|
||||
* | | |If user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
|
||||
* | | |0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format).
|
||||
* | | |1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format.
|
||||
* @var ADC_T::ADCHER
|
||||
* Offset: 0x84 ADC Channel Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CHEN |Analog Input Channel Enable Control
|
||||
* | | |Set ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0
|
||||
* | | |If DIFFEN bit is set to 1, only the even number channel needs to be enabled.
|
||||
* | | |Besides, set ADCHER[29] bit will enable internal channel for band-gap voltage respectively
|
||||
* | | |Other bits are reserved.
|
||||
* | | |0 = Channel Disabled.
|
||||
* | | |1 = Channel Enabled.
|
||||
* | | |Note1: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 1M SPS.
|
||||
* @var ADC_T::ADCMPR
|
||||
* Offset: 0x88/0x8C ADC Compare Register 0/1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CMPEN |Compare Enable Bit
|
||||
* | | |Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
|
||||
* | | |0 = Compare function Disabled.
|
||||
* | | |1 = Compare function Enabled.
|
||||
* |[1] |CMPIE |Compare Interrupt Enable Bit
|
||||
* | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated.
|
||||
* | | |0 = Compare function interrupt Disabled.
|
||||
* | | |1 = Compare function interrupt Enabled.
|
||||
* |[2] |CMPCOND |Compare Condition
|
||||
* | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one.
|
||||
* | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one.
|
||||
* | | |Note: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
|
||||
* |[7:3] |CMPCH |Compare Channel Selection
|
||||
* | | |00000 = Channel 0 conversion result is selected to be compared.
|
||||
* | | |00001 = Channel 1 conversion result is selected to be compared.
|
||||
* | | |00010 = Channel 2 conversion result is selected to be compared.
|
||||
* | | |00011 = Channel 3 conversion result is selected to be compared.
|
||||
* | | |00100 = Channel 4 conversion result is selected to be compared.
|
||||
* | | |00101 = Channel 5 conversion result is selected to be compared.
|
||||
* | | |00110 = Channel 6 conversion result is selected to be compared.
|
||||
* | | |00111 = Channel 7 conversion result is selected to be compared.
|
||||
* | | |01000 = Channel 8 conversion result is selected to be compared.
|
||||
* | | |01001 = Channel 9 conversion result is selected to be compared.
|
||||
* | | |01010 = Channel 10 conversion result is selected to be compared.
|
||||
* | | |01011 = Channel 11 conversion result is selected to be compared.
|
||||
* | | |01100 = Channel 12 conversion result is selected to be compared.
|
||||
* | | |01101 = Channel 13 conversion result is selected to be compared.
|
||||
* | | |01110 = Channel 14 conversion result is selected to be compared.
|
||||
* | | |01111 = Channel 15 conversion result is selected to be compared.
|
||||
* | | |11101 = Band-gap voltage conversion result is selected to be compared.
|
||||
* | | |Others = Reserved.
|
||||
* |[11:8] |CMPMATCNT |Compare Match Count
|
||||
* | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
|
||||
* |[15] |CMPWEN |Compare Window Mode Enable Bit
|
||||
* | | |0 = Compare Window Mode Disabled.
|
||||
* | | |1 = Compare Window Mode Enabled.
|
||||
* | | |Note: This bit is only presented in ADCMPR0 register.
|
||||
* |[27:16] |CMPD |Comparison Data
|
||||
* | | |The 12-bit data is used to compare with conversion result of specified channel.
|
||||
* | | |Note: CMPD bits should be filled in unsigned format (straight binary format).
|
||||
* @var ADC_T::ADSR0
|
||||
* Offset: 0x90 ADC Status Register0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ADF |A/D Conversion End Flag
|
||||
* | | |A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.
|
||||
* | | |ADF bit is set to 1 at the following three conditions:
|
||||
* | | |1. When A/D conversion ends in Single mode.
|
||||
* | | |2. When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.
|
||||
* | | |3. When more than or equal to 8 samples in FIFO in Burst mode.
|
||||
* |[1] |CMPF0 |Compare Flag 0
|
||||
* | | |When the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
|
||||
* | | |0 = Conversion result in ADDR does not meet ADCMPR0 setting.
|
||||
* | | |1 = Conversion result in ADDR meets ADCMPR0 setting.
|
||||
* |[2] |CMPF1 |Compare Flag 1
|
||||
* | | |When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1; it is cleared by writing 1 to it.
|
||||
* | | |0 = Conversion result in ADDR does not meet ADCMPR1 setting.
|
||||
* | | |1 = Conversion result in ADDR meets ADCMPR1 setting.
|
||||
* |[7] |BUSY |BUSY/IDLE (Read Only)
|
||||
* | | |This bit is a mirror of ADST bit in ADCR register.
|
||||
* | | |0 = A/D converter is in idle state.
|
||||
* | | |1 = A/D converter is busy at conversion.
|
||||
* |[8] |VALIDF |Data Valid Flag (Read Only)
|
||||
* | | |If any one of VALID (ADDRx[17]) is set, this flag will be set to 1.
|
||||
* | | |Note: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
|
||||
* |[16] |OVERRUNF |Overrun Flag (Read Only)
|
||||
* | | |If any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.
|
||||
* | | |Note: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
|
||||
* |[31:27] |CHANNEL |Current Conversion Channel (Read Only)
|
||||
* | | |When BUSY=1, this filed reflects current conversion channel. When BUSY=0, it shows the number of the next converted channel.
|
||||
* @var ADC_T::ADSR1
|
||||
* Offset: 0x94 ADC Status Register1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |VALID |Data Valid Flag (Read Only)
|
||||
* | | |VALID[29, 15:0] are the mirror of the VALID bits in ADDR29[17], ADDR15[17]~ ADDR0[17]. The other bits are reserved.
|
||||
* | | |Note: When ADC is in burst mode and any conversion result is valid, VALID[29, 15:0] will be set to 1.
|
||||
* @var ADC_T::ADSR2
|
||||
* Offset: 0x98 ADC Status Register2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |OVERRUN |Overrun Flag (Read Only)
|
||||
* | | |OVERRUN[29, 15:0] are the mirror of the OVERRUN bit in ADDR29[16], ADDR15[16] ~ ADDR0[16]. The other bits are reserved.
|
||||
* | | |Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[29, 15:0] will be set to 1.
|
||||
* @var ADC_T::ESMPCTL
|
||||
* Offset: 0xA0 ADC Extend Sample Time Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |EXTSMPT |ADC Sampling Time Extend
|
||||
* | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
|
||||
* | | |The range of start delay time is from 0~255 ADC clock.
|
||||
* @var ADC_T::ADPDMA
|
||||
* Offset: 0x100 ADC PDMA Current Transfer Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register (Read Only)
|
||||
* | | |When PDMA transferring, read this register can monitor current PDMA transfer data.
|
||||
* | | |Current PDMA transfer data could be the content of ADDR0 ~ ADDR15 and ADDR29 registers.
|
||||
* @var ADC_T::ADCALR
|
||||
* Offset: 0x180 ADC Calibration Mode Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CALEN |Calibration Function Enable Bit
|
||||
* | | |0 = Calibration function Disable.
|
||||
* | | |1 = Calibration function Enable.
|
||||
* | | |Note: If chip power off, calibration function should be executed again.
|
||||
* |[1] |CALIE |Calibration Interrupt Enable
|
||||
* | | |If calibration function is enabled and the calibration finish, CALIF bit will be asserted, in the meanwhile, if CALIE bit is set to 1, a calibration interrupt request is generated.
|
||||
* | | |0 = Calibration function Interrupt Disable.
|
||||
* | | |1 = Calibration function Interrupt Enable.
|
||||
* @var ADC_T::ADCALSTSR
|
||||
* Offset: 0x184 ADC Calibration Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CALIF |Calibration Finish Interrupt Flag
|
||||
* | | |If calibration finish, this flag will be set to 1. It is cleared by writing 1 to it.
|
||||
*/
|
||||
__I uint32_t ADDR[30]; /*!< [0x0000-0x0074] ADC Data Register 0 ~ 29 */
|
||||
__I uint32_t RESERVE1[2];
|
||||
__IO uint32_t ADCR; /*!< [0x0080] ADC Control Register */
|
||||
__IO uint32_t ADCHER; /*!< [0x0084] ADC Channel Enable Register */
|
||||
__IO uint32_t ADCMPR[2]; /*!< [0x0088-0x008c] ADC Compare Register 0/1 */
|
||||
__IO uint32_t ADSR0; /*!< [0x0090] ADC Status Register0 */
|
||||
__I uint32_t ADSR1; /*!< [0x0094] ADC Status Register1 */
|
||||
__I uint32_t ADSR2; /*!< [0x0098] ADC Status Register2 */
|
||||
__I uint32_t RESERVE2[1];
|
||||
__IO uint32_t ESMPCTL; /*!< [0x00a0] ADC Extend Sample Time Control Register */
|
||||
__IO uint32_t CFDCTL; /*!< [0x00a4] ADC Channel Floating Detect Control Register */
|
||||
__I uint32_t RESERVE3[22];
|
||||
__I uint32_t ADPDMA; /*!< [0x0100] ADC PDMA Current Transfer Data Register */
|
||||
__I uint32_t RESERVE4[31];
|
||||
__IO uint32_t ADCALR; /*!< [0x0180] ADC Calibration Mode Register */
|
||||
__IO uint32_t ADCALSTSR; /*!< [0x0184] ADC Calibration Status Register */
|
||||
__IO uint32_t ADCALDBR; /*!< [0x0188] ADC Calibration Debug Mode Register */
|
||||
} ADC_T;
|
||||
|
||||
/**
|
||||
@addtogroup ADC_CONST ADC Bit Field Definition
|
||||
Constant Definitions for ADC Controller
|
||||
@{ */
|
||||
|
||||
#define ADC_ADDR_RSLT_Pos (0) /*!< ADC_T::ADDR: RSLT Position */
|
||||
#define ADC_ADDR_RSLT_Msk (0xfffful << ADC_ADDR_RSLT_Pos) /*!< ADC_T::ADDR: RSLT Mask */
|
||||
|
||||
#define ADC_ADDR_OVERRUN_Pos (16) /*!< ADC_T::ADDR: OVERRUN Position */
|
||||
#define ADC_ADDR_OVERRUN_Msk (0x1ul << ADC_ADDR_OVERRUN_Pos) /*!< ADC_T::ADDR: OVERRUN Mask */
|
||||
|
||||
#define ADC_ADDR_VALID_Pos (17) /*!< ADC_T::ADDR: VALID Position */
|
||||
#define ADC_ADDR_VALID_Msk (0x1ul << ADC_ADDR_VALID_Pos) /*!< ADC_T::ADDR: VALID Mask */
|
||||
|
||||
#define ADC_ADCR_ADEN_Pos (0) /*!< ADC_T::ADCR: ADEN Position */
|
||||
#define ADC_ADCR_ADEN_Msk (0x1ul << ADC_ADCR_ADEN_Pos) /*!< ADC_T::ADCR: ADEN Mask */
|
||||
|
||||
#define ADC_ADCR_ADIE_Pos (1) /*!< ADC_T::ADCR: ADIE Position */
|
||||
#define ADC_ADCR_ADIE_Msk (0x1ul << ADC_ADCR_ADIE_Pos) /*!< ADC_T::ADCR: ADIE Mask */
|
||||
|
||||
#define ADC_ADCR_ADMD_Pos (2) /*!< ADC_T::ADCR: ADMD Position */
|
||||
#define ADC_ADCR_ADMD_Msk (0x3ul << ADC_ADCR_ADMD_Pos) /*!< ADC_T::ADCR: ADMD Mask */
|
||||
|
||||
#define ADC_ADCR_TRGS_Pos (4) /*!< ADC_T::ADCR: TRGS Position */
|
||||
#define ADC_ADCR_TRGS_Msk (0x3ul << ADC_ADCR_TRGS_Pos) /*!< ADC_T::ADCR: TRGS Mask */
|
||||
|
||||
#define ADC_ADCR_TRGCOND_Pos (6) /*!< ADC_T::ADCR: TRGCOND Position */
|
||||
#define ADC_ADCR_TRGCOND_Msk (0x3ul << ADC_ADCR_TRGCOND_Pos) /*!< ADC_T::ADCR: TRGCOND Mask */
|
||||
|
||||
#define ADC_ADCR_TRGEN_Pos (8) /*!< ADC_T::ADCR: TRGEN Position */
|
||||
#define ADC_ADCR_TRGEN_Msk (0x1ul << ADC_ADCR_TRGEN_Pos) /*!< ADC_T::ADCR: TRGEN Mask */
|
||||
|
||||
#define ADC_ADCR_PTEN_Pos (9) /*!< ADC_T::ADCR: PTEN Position */
|
||||
#define ADC_ADCR_PTEN_Msk (0x1ul << ADC_ADCR_PTEN_Pos) /*!< ADC_T::ADCR: PTEN Mask */
|
||||
|
||||
#define ADC_ADCR_DIFFEN_Pos (10) /*!< ADC_T::ADCR: DIFFEN Position */
|
||||
#define ADC_ADCR_DIFFEN_Msk (0x1ul << ADC_ADCR_DIFFEN_Pos) /*!< ADC_T::ADCR: DIFFEN Mask */
|
||||
|
||||
#define ADC_ADCR_ADST_Pos (11) /*!< ADC_T::ADCR: ADST Position */
|
||||
#define ADC_ADCR_ADST_Msk (0x1ul << ADC_ADCR_ADST_Pos) /*!< ADC_T::ADCR: ADST Mask */
|
||||
|
||||
#define ADC_ADCR_RESET_Pos (12) /*!< ADC_T::ADCR: RESET Position */
|
||||
#define ADC_ADCR_RESET_Msk (0x1ul << ADC_ADCR_RESET_Pos) /*!< ADC_T::ADCR: RESET Mask */
|
||||
|
||||
#define ADC_ADCR_DMOF_Pos (31) /*!< ADC_T::ADCR: DMOF Position */
|
||||
#define ADC_ADCR_DMOF_Msk (0x1ul << ADC_ADCR_DMOF_Pos) /*!< ADC_T::ADCR: DMOF Mask */
|
||||
|
||||
#define ADC_ADCHER_CHEN_Pos (0) /*!< ADC_T::ADCHER: CHEN Position */
|
||||
#define ADC_ADCHER_CHEN_Msk (0xfffffffful << ADC_ADCHER_CHEN_Pos) /*!< ADC_T::ADCHER: CHEN Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPEN_Pos (0) /*!< ADC_T::ADCMPR: CMPEN Position */
|
||||
#define ADC_ADCMPR_CMPEN_Msk (0x1ul << ADC_ADCMPR_CMPEN_Pos) /*!< ADC_T::ADCMPR: CMPEN Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPIE_Pos (1) /*!< ADC_T::ADCMPR: CMPIE Position */
|
||||
#define ADC_ADCMPR_CMPIE_Msk (0x1ul << ADC_ADCMPR_CMPIE_Pos) /*!< ADC_T::ADCMPR: CMPIE Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPCOND_Pos (2) /*!< ADC_T::ADCMPR: CMPCOND Position */
|
||||
#define ADC_ADCMPR_CMPCOND_Msk (0x1ul << ADC_ADCMPR_CMPCOND_Pos) /*!< ADC_T::ADCMPR: CMPCOND Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPCH_Pos (3) /*!< ADC_T::ADCMPR: CMPCH Position */
|
||||
#define ADC_ADCMPR_CMPCH_Msk (0x1ful << ADC_ADCMPR_CMPCH_Pos) /*!< ADC_T::ADCMPR: CMPCH Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPMATCNT_Pos (8) /*!< ADC_T::ADCMPR: CMPMATCNT Position */
|
||||
#define ADC_ADCMPR_CMPMATCNT_Msk (0xful << ADC_ADCMPR_CMPMATCNT_Pos) /*!< ADC_T::ADCMPR: CMPMATCNT Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPWEN_Pos (15) /*!< ADC_T::ADCMPR: CMPWEN Position */
|
||||
#define ADC_ADCMPR_CMPWEN_Msk (0x1ul << ADC_ADCMPR_CMPWEN_Pos) /*!< ADC_T::ADCMPR: CMPWEN Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPD_Pos (16) /*!< ADC_T::ADCMPR: CMPD Position */
|
||||
#define ADC_ADCMPR_CMPD_Msk (0xffful << ADC_ADCMPR_CMPD_Pos) /*!< ADC_T::ADCMPR: CMPD Mask */
|
||||
|
||||
#define ADC_ADSR0_ADF_Pos (0) /*!< ADC_T::ADSR0: ADF Position */
|
||||
#define ADC_ADSR0_ADF_Msk (0x1ul << ADC_ADSR0_ADF_Pos) /*!< ADC_T::ADSR0: ADF Mask */
|
||||
|
||||
#define ADC_ADSR0_CMPF0_Pos (1) /*!< ADC_T::ADSR0: CMPF0 Position */
|
||||
#define ADC_ADSR0_CMPF0_Msk (0x1ul << ADC_ADSR0_CMPF0_Pos) /*!< ADC_T::ADSR0: CMPF0 Mask */
|
||||
|
||||
#define ADC_ADSR0_CMPF1_Pos (2) /*!< ADC_T::ADSR0: CMPF1 Position */
|
||||
#define ADC_ADSR0_CMPF1_Msk (0x1ul << ADC_ADSR0_CMPF1_Pos) /*!< ADC_T::ADSR0: CMPF1 Mask */
|
||||
|
||||
#define ADC_ADSR0_BUSY_Pos (7) /*!< ADC_T::ADSR0: BUSY Position */
|
||||
#define ADC_ADSR0_BUSY_Msk (0x1ul << ADC_ADSR0_BUSY_Pos) /*!< ADC_T::ADSR0: BUSY Mask */
|
||||
|
||||
#define ADC_ADSR0_VALIDF_Pos (8) /*!< ADC_T::ADSR0: VALIDF Position */
|
||||
#define ADC_ADSR0_VALIDF_Msk (0x1ul << ADC_ADSR0_VALIDF_Pos) /*!< ADC_T::ADSR0: VALIDF Mask */
|
||||
|
||||
#define ADC_ADSR0_OVERRUNF_Pos (16) /*!< ADC_T::ADSR0: OVERRUNF Position */
|
||||
#define ADC_ADSR0_OVERRUNF_Msk (0x1ul << ADC_ADSR0_OVERRUNF_Pos) /*!< ADC_T::ADSR0: OVERRUNF Mask */
|
||||
|
||||
#define ADC_ADSR0_CHANNEL_Pos (27) /*!< ADC_T::ADSR0: CHANNEL Position */
|
||||
#define ADC_ADSR0_CHANNEL_Msk (0x1ful << ADC_ADSR0_CHANNEL_Pos) /*!< ADC_T::ADSR0: CHANNEL Mask */
|
||||
|
||||
#define ADC_ADSR1_VALID_Pos (0) /*!< ADC_T::ADSR1: VALID Position */
|
||||
#define ADC_ADSR1_VALID_Msk (0xfffffffful << ADC_ADSR1_VALID_Pos) /*!< ADC_T::ADSR1: VALID Mask */
|
||||
|
||||
#define ADC_ADSR2_OVERRUN_Pos (0) /*!< ADC_T::ADSR2: OVERRUN Position */
|
||||
#define ADC_ADSR2_OVERRUN_Msk (0xfffffffful << ADC_ADSR2_OVERRUN_Pos) /*!< ADC_T::ADSR2: OVERRUN Mask */
|
||||
|
||||
#define ADC_ESMPCTL_EXTSMPT_Pos (0) /*!< ADC_T::ESMPCTL: EXTSMPT Position */
|
||||
#define ADC_ESMPCTL_EXTSMPT_Msk (0xfful << ADC_ESMPCTL_EXTSMPT_Pos) /*!< ADC_T::ESMPCTL: EXTSMPT Mask */
|
||||
|
||||
#define ADC_CFDCTL_PRECHEN_Pos (0) /*!< ADC_T::CFDCTL: PRECHEN Position */
|
||||
#define ADC_CFDCTL_PRECHEN_Msk (0x1ul << ADC_CFDCTL_PRECHEN_Pos) /*!< ADC_T::CFDCTL: PRECHEN Mask */
|
||||
|
||||
#define ADC_CFDCTL_DISCHEN_Pos (1) /*!< ADC_T::CFDCTL: DISCHEN Position */
|
||||
#define ADC_CFDCTL_DISCHEN_Msk (0x1ul << ADC_CFDCTL_DISCHEN_Pos) /*!< ADC_T::CFDCTL: DISCHEN Mask */
|
||||
|
||||
#define ADC_CFDCTL_FDETCHEN_Pos (8) /*!< ADC_T::CFDCTL: FDETCHEN Position */
|
||||
#define ADC_CFDCTL_FDETCHEN_Msk (0x1ul << ADC_CFDCTL_FDETCHEN_Pos) /*!< ADC_T::CFDCTL: FDETCHEN Mask */
|
||||
|
||||
#define ADC_ADPDMA_CURDAT_Pos (0) /*!< ADC_T::ADPDMA: CURDAT Position */
|
||||
#define ADC_ADPDMA_CURDAT_Msk (0x3fffful << ADC_ADPDMA_CURDAT_Pos) /*!< ADC_T::ADPDMA: CURDAT Mask */
|
||||
|
||||
#define ADC_ADCALR_CALEN_Pos (0) /*!< ADC_T::ADCALR: CALEN Position */
|
||||
#define ADC_ADCALR_CALEN_Msk (0x1ul << ADC_ADCALR_CALEN_Pos) /*!< ADC_T::ADCALR: CALEN Mask */
|
||||
|
||||
#define ADC_ADCALR_CALIE_Pos (1) /*!< ADC_T::ADCALR: CALIE Position */
|
||||
#define ADC_ADCALR_CALIE_Msk (0x1ul << ADC_ADCALR_CALIE_Pos) /*!< ADC_T::ADCALR: CALIE Mask */
|
||||
|
||||
#define ADC_ADCALSTSR_CALIF_Pos (0) /*!< ADC_T::ADCALSTSR: CALIF Position */
|
||||
#define ADC_ADCALSTSR_CALIF_Msk (0x1ul << ADC_ADCALSTSR_CALIF_Pos) /*!< ADC_T::ADCALSTSR: CALIF Mask */
|
||||
|
||||
/**@}*/ /* ADC_CONST */
|
||||
/**@}*/ /* end of ADC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,151 @@
|
||||
/**************************************************************************//**
|
||||
* @file crc_reg.h
|
||||
* @version V1.00
|
||||
* @brief CRC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CRC_REG_H__
|
||||
#define __CRC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
|
||||
Memory Mapped Structure for CRC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var CRC_T::CTL
|
||||
* Offset: 0x00 CRC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CRCEN |CRC Channel Enable Bit
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = CRC operation Enabled.
|
||||
* |[1] |CHKSINIT |Checksum Initialization
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
|
||||
* | | |Note: This bit will be cleared automatically.
|
||||
* |[24] |DATREV |Write Data Bit Order Reverse
|
||||
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
|
||||
* | | |0 = Bit order reversed for CRC write data in Disabled.
|
||||
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
|
||||
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
|
||||
* |[25] |CHKSREV |Checksum Bit Order Reverse
|
||||
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
|
||||
* | | |0 = Bit order reverse for CRC checksum Disabled.
|
||||
* | | |1 = Bit order reverse for CRC checksum Enabled.
|
||||
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
|
||||
* |[26] |DATFMT |Write Data 1's Complement
|
||||
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
|
||||
* | | |0 = 1's complement for CRC writes data in Disabled.
|
||||
* | | |1 = 1's complement for CRC writes data in Enabled.
|
||||
* |[27] |CHKSFMT |Checksum 1's Complement
|
||||
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
|
||||
* | | |0 = 1's complement for CRC checksum Disabled.
|
||||
* | | |1 = 1's complement for CRC checksum Enabled.
|
||||
* |[29:28] |DATLEN |CPU Write Data Length
|
||||
* | | |This field indicates the write data length.
|
||||
* | | |00 = Data length is 8-bit mode.
|
||||
* | | |01 = Data length is 16-bit mode.
|
||||
* | | |1x = Data length is 32-bit mode.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* |[31:30] |CRCMODE |CRC Polynomial Mode
|
||||
* | | |This field indicates the CRC operation polynomial mode.
|
||||
* | | |00 = CRC-CCITT Polynomial mode.
|
||||
* | | |01 = CRC-8 Polynomial mode.
|
||||
* | | |10 = CRC-16 Polynomial mode.
|
||||
* | | |11 = CRC-32 Polynomial mode.
|
||||
* @var CRC_T::DAT
|
||||
* Offset: 0x04 CRC Write Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DATA |CRC Write Data Bits
|
||||
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* @var CRC_T::SEED
|
||||
* Offset: 0x08 CRC Seed Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |SEED |CRC Seed Value
|
||||
* | | |This field indicates the CRC seed value.
|
||||
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
|
||||
* @var CRC_T::CHECKSUM
|
||||
* Offset: 0x0C CRC Checksum Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CHECKSUM |CRC Checksum Results
|
||||
* | | |This field indicates the CRC checksum result.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
|
||||
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
|
||||
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
|
||||
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
|
||||
|
||||
} CRC_T;
|
||||
|
||||
/**
|
||||
@addtogroup CRC_CONST CRC Bit Field Definition
|
||||
Constant Definitions for CRC Controller
|
||||
@{ */
|
||||
|
||||
|
||||
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
|
||||
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
|
||||
|
||||
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
|
||||
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
|
||||
|
||||
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
|
||||
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
|
||||
|
||||
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
|
||||
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
|
||||
|
||||
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
|
||||
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
|
||||
|
||||
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
|
||||
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
|
||||
|
||||
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
|
||||
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
|
||||
|
||||
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
|
||||
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
|
||||
|
||||
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
|
||||
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
|
||||
|
||||
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
|
||||
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
|
||||
|
||||
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
|
||||
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
|
||||
|
||||
/**@}*/ /* CRC_CONST */
|
||||
/**@}*/ /* end of CRC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __CRC_REG_H__ */
|
||||
@@ -0,0 +1,224 @@
|
||||
/**************************************************************************//**
|
||||
* @file ebi_reg.h
|
||||
* @version V1.00
|
||||
* @brief EBI register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __EBI_REG_H__
|
||||
#define __EBI_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup EBI External Bus Interface Controller(EBI)
|
||||
Memory Mapped Structure for EBI Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var EBI_T::CTL0
|
||||
* Offset: 0x00 External Bus Interface Bank0 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |EN |EBI Enable Bit
|
||||
* | | |This bit is the functional enable bit for EBI.
|
||||
* | | |0 = EBI function Disabled.
|
||||
* | | |1 = EBI function Enabled.
|
||||
* |[1] |DW16 |EBI Data Width 16-bit Select
|
||||
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
|
||||
* | | |0 = EBI data width is 8-bit.
|
||||
* | | |1 = EBI data width is 16-bit.
|
||||
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
|
||||
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
|
||||
* | | |0 = Chip select pin (EBI_nCS) is active low.
|
||||
* | | |1 = Chip select pin (EBI_nCS) is active high.
|
||||
* |[4] |CACCESS |Continuous Data Access Mode
|
||||
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
|
||||
* | | |0 = Continuous data access mode Disabled.
|
||||
* | | |1 = Continuous data access mode Enabled.
|
||||
* |[10:8] |MCLKDIV |External Output Clock Divider
|
||||
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
|
||||
* | | |000 = HCLK/1.
|
||||
* | | |001 = HCLK/2.
|
||||
* | | |010 = HCLK/4.
|
||||
* | | |011 = HCLK/8.
|
||||
* | | |100 = HCLK/16.
|
||||
* | | |101 = HCLK/32.
|
||||
* | | |110 = HCLK/64.
|
||||
* | | |111 = HCLK/128.
|
||||
* |[18:16] |TALE |Extend Time Of of ALE
|
||||
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
|
||||
* | | |tALE = (TALE + 1)*EBI_MCLK.
|
||||
* | | |Note: This field only available in EBI_CTL0 register.
|
||||
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
|
||||
* | | |0 = EBI write buffer Disabled.
|
||||
* | | |1 = EBI write buffer Enabled.
|
||||
* | | |Note: This bit only available in EBI_CTL0 register.
|
||||
* @var EBI_T::TCTL0
|
||||
* Offset: 0x04 External Bus Interface Bank0 Timing Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:3] |TACC |EBI Data Access Time
|
||||
* | | |TACC define data access time (tACC).
|
||||
* | | |tACC = (TACC + 1) * EBI_MCLK.
|
||||
* |[10:8] |TAHD |EBI Data Access Hold Time
|
||||
* | | |TAHD define data access hold time (tAHD).
|
||||
* | | |tAHD = (TAHD + 1) * EBI_MCLK.
|
||||
* |[15:12] |W2X |Idle Cycle After Write
|
||||
* | | |This field defines the number of W2X idle cycle.
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |W2X idle cycle = (W2X * EBI_MCLK).
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
|
||||
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
|
||||
* |[27:24] |R2R |Idle Cycle Between Read-to-read
|
||||
* | | |This field defines the number of R2R idle cycle.
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |R2R idle cycle = (R2R * EBI_MCLK).
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* @var EBI_T::CTL1
|
||||
* Offset: 0x10 External Bus Interface Bank1 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |EN |EBI Enable Bit
|
||||
* | | |This bit is the functional enable bit for EBI.
|
||||
* | | |0 = EBI function Disabled.
|
||||
* | | |1 = EBI function Enabled.
|
||||
* |[1] |DW16 |EBI Data Width 16-bit Select
|
||||
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
|
||||
* | | |0 = EBI data width is 8-bit.
|
||||
* | | |1 = EBI data width is 16-bit.
|
||||
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
|
||||
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
|
||||
* | | |0 = Chip select pin (EBI_nCS) is active low.
|
||||
* | | |1 = Chip select pin (EBI_nCS) is active high.
|
||||
* |[4] |CACCESS |Continuous Data Access Mode
|
||||
* | | |When con ttinuousenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
|
||||
* | | |0 = Continuous data access mode Disabled.
|
||||
* | | |1 = Continuous data access mode Enabled.
|
||||
* |[10:8] |MCLKDIV |External Output Clock Divider
|
||||
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
|
||||
* | | |000 = HCLK/1.
|
||||
* | | |001 = HCLK/2.
|
||||
* | | |010 = HCLK/4.
|
||||
* | | |011 = HCLK/8.
|
||||
* | | |100 = HCLK/16.
|
||||
* | | |101 = HCLK/32.
|
||||
* | | |110 = HCLK/64.
|
||||
* | | |111 = HCLK/128.
|
||||
* |[18:16] |TALE |Extend Time Of of ALE
|
||||
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
|
||||
* | | |tALE = (TALE + 1)*EBI_MCLK.
|
||||
* | | |Note: This field only available in EBI_CTL0 register.
|
||||
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
|
||||
* | | |0 = EBI write buffer Disabled.
|
||||
* | | |1 = EBI write buffer Enabled.
|
||||
* | | |Note: This bit only available in EBI_CTL0 register.
|
||||
* @var EBI_T::TCTL1
|
||||
* Offset: 0x14 External Bus Interface Bank1 Timing Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:3] |TACC |EBI Data Access Time
|
||||
* | | |TACC define data access time (tACC).
|
||||
* | | |tACC = (TACC + 1) * EBI_MCLK.
|
||||
* |[10:8] |TAHD |EBI Data Access Hold Time
|
||||
* | | |TAHD define data access hold time (tAHD).
|
||||
* | | |tAHD = (TAHD + 1) * EBI_MCLK.
|
||||
* |[15:12] |W2X |Idle Cycle After Write
|
||||
* | | |This field defines the number of W2X idle cycle.
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |W2X idle cycle = (W2X * EBI_MCLK).
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
|
||||
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
|
||||
* |[27:24] |R2R |Idle Cycle Between Read-to-read
|
||||
* | | |This field defines the number of R2R idle cycle.
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |R2R idle cycle = (R2R * EBI_MCLK).
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
*/
|
||||
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
|
||||
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
|
||||
__I uint32_t RESERVE0[2];
|
||||
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
|
||||
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
|
||||
|
||||
} EBI_T;
|
||||
|
||||
/**
|
||||
@addtogroup EBI_CONST EBI Bit Field Definition
|
||||
Constant Definitions for EBI Controller
|
||||
@{ */
|
||||
|
||||
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
|
||||
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
|
||||
|
||||
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
|
||||
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
|
||||
|
||||
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
|
||||
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
|
||||
|
||||
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
|
||||
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
|
||||
|
||||
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
|
||||
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
|
||||
|
||||
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
|
||||
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
|
||||
|
||||
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
|
||||
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
|
||||
|
||||
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
|
||||
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
|
||||
|
||||
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
|
||||
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
|
||||
|
||||
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
|
||||
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
|
||||
|
||||
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
|
||||
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
|
||||
|
||||
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
|
||||
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
|
||||
|
||||
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
|
||||
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
|
||||
|
||||
/**@}*/ /* EBI_CONST */
|
||||
/**@}*/ /* end of EBI register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __EBI_REG_H__ */
|
||||
@@ -0,0 +1,317 @@
|
||||
/**************************************************************************//**
|
||||
* @file fmc_reg.h
|
||||
* @version V1.00
|
||||
* @brief FMC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __FMC_REG_H__
|
||||
#define __FMC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup FMC Flash Memory Controller(FMC)
|
||||
Memory Mapped Structure for FMC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var FMC_T::ISPCTL
|
||||
* Offset: 0x00 ISP Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ISPEN |ISP Enable Bit (Write Protection)
|
||||
* | | |ISP function enable bit. Set this bit to enable ISP function.
|
||||
* | | |0 = ISP function Disabled.
|
||||
* | | |1 = ISP function Enabled.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[1] |BS |Boot Select (Write Protection)
|
||||
* | | |Set/clear this bit to select next booting from LDROM/APROM, respectively.
|
||||
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
|
||||
* | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
|
||||
* | | |0 = Booting from APROM.
|
||||
* | | |1 = Booting from LDROM.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[2] |SPUEN |SPROM Update Enable Bit (Write Protection)
|
||||
* | | |0 = SPROM cannot be updated.
|
||||
* | | |1 = SPROM can be updated.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[3] |APUEN |APROM Update Enable Bit (Write Protection)
|
||||
* | | |0 = APROM cannot be updated when the chip runs in APROM.
|
||||
* | | |1 = APROM can be updated when the chip runs in APROM.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protection)
|
||||
* | | |0 = CONFIG cannot be updated.
|
||||
* | | |1 = CONFIG can be updated.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protection)
|
||||
* | | |LDROM update enable bit.
|
||||
* | | |0 = LDROM cannot be updated.
|
||||
* | | |1 = LDROM can be updated.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[6] |ISPFF |ISP Fail Flag (Write Protection)
|
||||
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
|
||||
* | | |This bit needs to be cleared by writing 1 to it.
|
||||
* | | |(1) APROM writes to itself if APUEN is set to 0.
|
||||
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
|
||||
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
|
||||
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0.
|
||||
* | | |(5) SPROM is programmed at SPROM secured mode.
|
||||
* | | |(6) Page Erase command at LOCK mode with ICE connection.
|
||||
* | | |(7) Erase or Program command at brown-out detected.
|
||||
* | | |(8) Destination address is illegal, such as over an available range.
|
||||
* | | |(9) Invalid ISP commands.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* @var FMC_T::ISPADDR
|
||||
* Offset: 0x04 ISP Address Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |ISPADDR |ISP Address
|
||||
* | | |The NuMicro M031 series is equipped with embedded flash.
|
||||
* | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.
|
||||
* | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
|
||||
* @var FMC_T::ISPDAT
|
||||
* Offset: 0x08 ISP Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |ISPDAT |ISP Data
|
||||
* | | |Write data to this register before ISP program operation.
|
||||
* | | |Read data from this register after ISP read operation.
|
||||
* | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment.
|
||||
* | | |For ISP Read Checksum command, ISPDAT is the checksum result.
|
||||
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect.
|
||||
* @var FMC_T::ISPCMD
|
||||
* Offset: 0x0C ISP Command Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6:0] |CMD |ISP CMD
|
||||
* | | |ISP command table is shown below:
|
||||
* | | |0x00 = FLASH Read.
|
||||
* | | |0x04 = Read Unique ID..
|
||||
* | | |0x0B = Read Company ID.
|
||||
* | | |0x0C = Read Device ID.
|
||||
* | | |0x0D = Read CRC32 Checksum.
|
||||
* | | |0x21 = FLASH 32-bit Program.
|
||||
* | | |0x22 = FLASH Page Erase..
|
||||
* | | |0x2D = Run CRC32 Checksum Calculation.
|
||||
* | | |0x2E = Vector Remap.
|
||||
* | | |The other commands are invalid.
|
||||
* @var FMC_T::ISPTRG
|
||||
* Offset: 0x10 ISP Trigger Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ISPGO |ISP Start Trigger (Write Protection)
|
||||
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
|
||||
* | | |0 = ISP operation is finished.
|
||||
* | | |1 = ISP is progressed.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* @var FMC_T::DFBA
|
||||
* Offset: 0x14 Data Flash Base Address
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DFBA |Data Flash Base Address
|
||||
* | | |This register indicates Data Flash start address. It is a read only register.
|
||||
* | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1.
|
||||
* | | |This register is valid when DFEN (CONFIG0[0]) =0.
|
||||
* @var FMC_T::FTCTL
|
||||
* Offset: 0x18 Flash Access Time Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
|
||||
* | | |The NuMicro Mini58TM series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
|
||||
* | | |0x1 = Frequency <= 24MHz..
|
||||
* | | |Others = Frequency <= 50MHz.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* @var FMC_T::ISPSTS
|
||||
* Offset: 0x40 ISP Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ISPBUSY |ISP BUSY (Read Only)
|
||||
* | | |0 = ISP operation is finished.
|
||||
* | | |1 = ISP operation is busy.
|
||||
* |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
|
||||
* | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
|
||||
* | | |00 = LDROM with IAP mode.
|
||||
* | | |01 = LDROM without IAP mode.
|
||||
* | | |10 = APROM with IAP mode.
|
||||
* | | |11 = APROM without IAP mode.
|
||||
* |[6] |ISPFF |ISP Fail Flag (Write Protection)
|
||||
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
|
||||
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
|
||||
* | | |(1) APROM writes to itself if APUEN is set to 0.
|
||||
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
|
||||
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
|
||||
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0.
|
||||
* | | |(5) SPROM is programmed at SPROM secured mode.
|
||||
* | | |(6) Page Erase command at LOCK mode with ICE connection.
|
||||
* | | |(7) Erase or Program command at brown-out detected.
|
||||
* | | |(8) Destination address is illegal, such as over an available range.
|
||||
* | | |(9) Invalid ISP commands.
|
||||
* |[29:9] |VECMAP |Vector Page Mapping Address (Read Only)
|
||||
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.
|
||||
* | | |VECMAP [20:19] = 00 system vector address is mapped to Flash memory.
|
||||
* | | |VECMAP [20:19] = 10 system vector address is mapped to SRAM memory.
|
||||
* | | |VECMAP [18:12] should be 0.All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
|
||||
* |[31] |SCODE |Security Code Active Flag
|
||||
* | | |This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation.
|
||||
* | | |0 = SPROM secured code is inactive.
|
||||
* | | |1 = SPROM secured code is active.
|
||||
*/
|
||||
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
|
||||
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
|
||||
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
|
||||
__IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
|
||||
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
|
||||
__I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */
|
||||
__IO uint32_t FTCTL; /*!< [0x0018] Flash Access Time Control Register */
|
||||
__IO uint32_t ICPCTL; /*!< [0x001C] Flash ICP Enable Control Register */
|
||||
__I uint32_t RESERVE0[8];
|
||||
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
|
||||
__I uint32_t RESERVE1[15];
|
||||
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
|
||||
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
|
||||
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
|
||||
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
|
||||
__I uint32_t RESERVE2[12];
|
||||
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
|
||||
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
|
||||
__I uint32_t RESERVE3[0x3CD];
|
||||
__I uint32_t VERSION; /*!< [0x0FFC] FMC Version Register */
|
||||
} FMC_T;
|
||||
|
||||
/**
|
||||
@addtogroup FMC_CONST FMC Bit Field Definition
|
||||
Constant Definitions for FMC Controller
|
||||
@{ */
|
||||
|
||||
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
|
||||
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
|
||||
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
|
||||
|
||||
#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */
|
||||
#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
|
||||
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
|
||||
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
|
||||
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
|
||||
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
|
||||
|
||||
#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */
|
||||
#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */
|
||||
|
||||
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
|
||||
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
|
||||
|
||||
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
|
||||
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
|
||||
|
||||
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
|
||||
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
|
||||
|
||||
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
|
||||
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
|
||||
|
||||
#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
|
||||
#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
|
||||
|
||||
#define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
|
||||
#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
|
||||
|
||||
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
|
||||
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
|
||||
|
||||
#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
|
||||
#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
|
||||
|
||||
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
|
||||
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
|
||||
|
||||
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
|
||||
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
|
||||
|
||||
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ISPFF Position */
|
||||
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos)
|
||||
|
||||
#define FMC_ISPSTS_INTFLAG_Pos (8) /*!< FMC_T::ISPSTS: INTFLAG Position */
|
||||
#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */
|
||||
|
||||
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
|
||||
#define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
|
||||
|
||||
#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */
|
||||
#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */
|
||||
|
||||
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
|
||||
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
|
||||
|
||||
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
|
||||
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
|
||||
|
||||
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
|
||||
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
|
||||
|
||||
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
|
||||
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
|
||||
|
||||
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
|
||||
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
|
||||
|
||||
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
|
||||
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
|
||||
|
||||
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
|
||||
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
|
||||
|
||||
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
|
||||
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
|
||||
|
||||
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
|
||||
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
|
||||
|
||||
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
|
||||
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
|
||||
|
||||
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
|
||||
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
|
||||
|
||||
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
|
||||
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
|
||||
|
||||
/**@}*/ /* FMC_CONST */
|
||||
/**@}*/ /* end of FMC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __FMC_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,130 @@
|
||||
/**************************************************************************//**
|
||||
* @file hdiv_reg.h
|
||||
* @version V1.00
|
||||
* @brief HDIV register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __HDIV_REG_H__
|
||||
#define __HDIV_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup HDIV Hardware Divider (HDIV)
|
||||
Memory Mapped Structure for HDIV Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* DIVIDEND
|
||||
* ===================================================================================================
|
||||
* Offset: 0x00 Dividend Source Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DIVIDEND |Dividend Source
|
||||
* | | |This register is given the dividend of divider before calculation starting.
|
||||
*/
|
||||
__IO uint32_t DIVIDEND;
|
||||
|
||||
/**
|
||||
* DIVISOR
|
||||
* ===================================================================================================
|
||||
* Offset: 0x04 Divisor Source Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |DIVISOR |Divisor Source
|
||||
* | | |This register is given the divisor of divider before calculation starts.
|
||||
* | | |Note: When this register is written, hardware divider will start calculate.
|
||||
*/
|
||||
__IO uint32_t DIVISOR;
|
||||
|
||||
/**
|
||||
* QUOTIENT
|
||||
* ===================================================================================================
|
||||
* Offset: 0x08 Quotient Result Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |QUOTIENT |Quotient Result
|
||||
* | | |This register holds the quotient result of divider after calculation complete.
|
||||
*/
|
||||
__IO uint32_t QUOTIENT;
|
||||
|
||||
/**
|
||||
* REM
|
||||
* ===================================================================================================
|
||||
* Offset: 0x0C Remainder Result Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |REM |Remainder Result
|
||||
* | | |The remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension
|
||||
* | | |(REM[31:16]) to 32-bit integer.
|
||||
*/
|
||||
__IO uint32_t REM;
|
||||
|
||||
/**
|
||||
* STATUS
|
||||
* ===================================================================================================
|
||||
* Offset: 0x10 Divider Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |DIVBYZERO |Divisor Zero Warning
|
||||
* | | |0 = The divisor is not 0.
|
||||
* | | |1 = The divisor is 0.
|
||||
* | | |Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever
|
||||
* | | |HDIV_DIVISOR is written.
|
||||
* | | |This register is read only.
|
||||
*/
|
||||
__I uint32_t STATUS;
|
||||
|
||||
} HDIV_T;
|
||||
|
||||
/**
|
||||
@addtogroup HDIV_CONST HDIV Bit Field Definition
|
||||
Constant Definitions for HDIV Controller
|
||||
@{ */
|
||||
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
|
||||
|
||||
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
|
||||
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
|
||||
|
||||
#define HDIV_QUOTIENT_QUOTIENT_Pos (0) /*!< HDIV_T::QUOTIENT: QUOTIENT Position */
|
||||
#define HDIV_QUOTIENT_QUOTIENT_Msk (0xfffffffful << HDIV_QUOTIENT_QUOTIENT_Pos) /*!< HDIV_T::QUOTIENT: QUOTIENT Mask */
|
||||
|
||||
#define HDIV_REM_REM_Pos (0) /*!< HDIV_T::REM: REM Position */
|
||||
#define HDIV_REM_REM_Msk (0xfffffffful << HDIV_REM_REM_Pos) /*!< HDIV_T::REM: REM Mask */
|
||||
|
||||
#define HDIV_STATUS_DIVBYZERO_Pos (1) /*!< HDIV_T::STATUS: DIVBYZERO Position */
|
||||
#define HDIV_STATUS_DIVBYZERO_Msk (0x1ul << HDIV_STATUS_DIVBYZERO_Pos) /*!< HDIV_T::STATUS: DIVBYZERO Mask */
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __HDIV_REG_H__ */
|
||||
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,419 @@
|
||||
/**************************************************************************//**
|
||||
* @file rtc_reg.h
|
||||
* @version V1.00
|
||||
* @brief RTC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __RTC_REG_H__
|
||||
#define __RTC_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------- Real Time Clock Controller -------------------------*/
|
||||
/**
|
||||
@addtogroup RTC Real Time Clock Controller(RTC)
|
||||
Memory Mapped Structure for RTC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var RTC_T::INIT
|
||||
* Offset: 0x00 RTC Initiation Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
|
||||
* | | |0 = RTC is at reset state.
|
||||
* | | |1 = RTC is at normal active state.
|
||||
* |[31:1] |INIT |RTC Initiation
|
||||
* | | |When RTC block is powered on, RTC is at reset state
|
||||
* | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state
|
||||
* | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
|
||||
* | | |The INIT is a write-only field and read value will be always 0.
|
||||
* @var RTC_T::FREQADJ
|
||||
* Offset: 0x08 RTC Frequency Compensation Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |FRACTION |Fraction Part
|
||||
* | | |Formula: FRACTION = (fraction part of detected value) X 64.
|
||||
* | | |Note: Digit in FCR must be expressed as hexadecimal number.
|
||||
* |[12:8] |INTEGER |Integer Part
|
||||
* | | |00000 = Integer part of detected value is 32752.
|
||||
* | | |00001 = Integer part of detected value is 32753.
|
||||
* | | |00010 = Integer part of detected value is 32754.
|
||||
* | | |00011 = Integer part of detected value is 32755.
|
||||
* | | |00100 = Integer part of detected value is 32756.
|
||||
* | | |00101 = Integer part of detected value is 32757.
|
||||
* | | |00110 = Integer part of detected value is 32758.
|
||||
* | | |00111 = Integer part of detected value is 32759.
|
||||
* | | |01000 = Integer part of detected value is 32760.
|
||||
* | | |01001 = Integer part of detected value is 32761.
|
||||
* | | |01010 = Integer part of detected value is 32762.
|
||||
* | | |01011 = Integer part of detected value is 32763.
|
||||
* | | |01100 = Integer part of detected value is 32764.
|
||||
* | | |01101 = Integer part of detected value is 32765.
|
||||
* | | |01110 = Integer part of detected value is 32766.
|
||||
* | | |01111 = Integer part of detected value is 32767.
|
||||
* | | |10000 = Integer part of detected value is 32768.
|
||||
* | | |10001 = Integer part of detected value is 32769.
|
||||
* | | |10010 = Integer part of detected value is 32770.
|
||||
* | | |10011 = Integer part of detected value is 32771.
|
||||
* | | |10100 = Integer part of detected value is 32772.
|
||||
* | | |10101 = Integer part of detected value is 32773.
|
||||
* | | |10110 = Integer part of detected value is 32774.
|
||||
* | | |10111 = Integer part of detected value is 32775.
|
||||
* | | |11000 = Integer part of detected value is 32776.
|
||||
* | | |11001 = Integer part of detected value is 32777.
|
||||
* | | |11010 = Integer part of detected value is 32778.
|
||||
* | | |11011 = Integer part of detected value is 32779.
|
||||
* | | |11100 = Integer part of detected value is 32780.
|
||||
* | | |11101 = Integer part of detected value is 32781.
|
||||
* | | |11110 = Integer part of detected value is 32782.
|
||||
* | | |11111 = Integer part of detected value is 32783.
|
||||
* @var RTC_T::TIME
|
||||
* Offset: 0x0C RTC Time Loading Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |SEC |1-Sec Time Digit (0~9)
|
||||
* |[6:4] |TENSEC |10-Sec Time Digit (0~5)
|
||||
* |[11:8] |MIN |1-Min Time Digit (0~9)
|
||||
* |[14:12] |TENMIN |10-Min Time Digit (0~5)
|
||||
* |[19:16] |HR |1-Hour Time Digit (0~9)
|
||||
* |[21:20] |TENHR |10-Hour Time Digit (0~2)
|
||||
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
|
||||
* |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
|
||||
* @var RTC_T::CAL
|
||||
* Offset: 0x10 RTC Calendar Loading Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |DAY |1-Day Calendar Digit (0~9)
|
||||
* |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
|
||||
* |[11:8] |MON |1-Month Calendar Digit (0~9)
|
||||
* |[12] |TENMON |10-Month Calendar Digit (0~1)
|
||||
* |[19:16] |YEAR |1-Year Calendar Digit (0~9)
|
||||
* |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
|
||||
* @var RTC_T::CLKFMT
|
||||
* Offset: 0x14 RTC Time Scale Selection Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |24HEN |24-hour / 12-hour Time Scale Selection
|
||||
* | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
|
||||
* | | |0 = 12-hour time scale with AM and PM indication selected.
|
||||
* | | |1 = 24-hour time scale selected.
|
||||
* |[8] |HZCNTEN |Sub-second Counter Enable Bit
|
||||
* | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM.
|
||||
* | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM .
|
||||
* @var RTC_T::WEEKDAY
|
||||
* Offset: 0x18 RTC Day of the Week Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |WEEKDAY |Day of the Week Register
|
||||
* | | |000 = Sunday.
|
||||
* | | |001 = Monday.
|
||||
* | | |010 = Tuesday.
|
||||
* | | |011 = Wednesday.
|
||||
* | | |100 = Thursday.
|
||||
* | | |101 = Friday.
|
||||
* | | |110 = Saturday.
|
||||
* | | |111 = Reserved.
|
||||
* @var RTC_T::TALM
|
||||
* Offset: 0x1C RTC Time Alarm Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
|
||||
* |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
|
||||
* |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
|
||||
* |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
|
||||
* |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
|
||||
* |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
|
||||
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
|
||||
* |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
|
||||
* @var RTC_T::CALM
|
||||
* Offset: 0x20 RTC Calendar Alarm Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
|
||||
* |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
|
||||
* |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
|
||||
* |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
|
||||
* |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* @var RTC_T::LEAPYEAR
|
||||
* Offset: 0x24 RTC Leap Year Indicator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
|
||||
* | | |0 = This year is not a leap year.
|
||||
* | | |1 = This year is leap year.
|
||||
* @var RTC_T::INTEN
|
||||
* Offset: 0x28 RTC Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ALMIEN |Alarm Interrupt Enable Bit
|
||||
* | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
|
||||
* | | |0 = RTC Alarm interrupt Disabled.
|
||||
* | | |1 = RTC Alarm interrupt Enabled.
|
||||
* |[1] |TICKIEN |Time Tick Interrupt Enable Bit
|
||||
* @var RTC_T::INTSTS
|
||||
* Offset: 0x2C RTC Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ALMIF |RTC Alarm Interrupt Flag
|
||||
* | | |0 = Alarm condition is not matched.
|
||||
* | | |1 = Alarm condition is matched.
|
||||
* | | |Note: Write 1 to clear this bit.
|
||||
* |[1] |TICKIF |RTC Time Tick Interrupt Flag
|
||||
* @var RTC_T::TICK
|
||||
* Offset: 0x30 RTC Time Tick Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |TICK |Time Tick Register
|
||||
* | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
|
||||
* | | |000 = Time tick is 1 second.
|
||||
* | | |001 = Time tick is 1/2 second.
|
||||
* | | |010 = Time tick is 1/4 second.
|
||||
* | | |011 = Time tick is 1/8 second.
|
||||
* | | |100 = Time tick is 1/16 second.
|
||||
* | | |101 = Time tick is 1/32 second.
|
||||
* | | |110 = Time tick is 1/64 second.
|
||||
* | | |111 = Time tick is 1/128 second.
|
||||
* | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
|
||||
* @var RTC_T::TAMSK
|
||||
* Offset: 0x34 RTC Time Alarm Mask Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
|
||||
* |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
|
||||
* |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
|
||||
* |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
|
||||
* |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
|
||||
* | | |Note: MHR function is only for 24-hour time scale mode.
|
||||
* |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
|
||||
* | | |Note: MTENHR function is only for 24-hour time scale mode.
|
||||
* @var RTC_T::CAMSK
|
||||
* Offset: 0x38 RTC Calendar Alarm Mask Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
|
||||
* |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
|
||||
* |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
|
||||
* |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
|
||||
* |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* @var RTC_T::LXTCTL
|
||||
* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7] |C32KS |Clock 32K Source Selection:
|
||||
* | | |0 = Internal 32K clock is from 32K crystal .
|
||||
* | | |1 = Internal 32K clock is from LIRC32K.
|
||||
*/
|
||||
__IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
|
||||
__I uint32_t RESERVE0[1];
|
||||
__IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
|
||||
__IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
|
||||
__IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
|
||||
__IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
|
||||
__IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
|
||||
__IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
|
||||
__IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
|
||||
__I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
|
||||
__IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
|
||||
__IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
|
||||
__IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
|
||||
__IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
|
||||
__I uint32_t RESERVE1[49]; /* 0x3C ~ 0xFC */
|
||||
__IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */
|
||||
|
||||
} RTC_T;
|
||||
|
||||
/**
|
||||
@addtogroup RTC_CONST RTC Bit Field Definition
|
||||
Constant Definitions for RTC Controller
|
||||
@{ */
|
||||
|
||||
#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
|
||||
#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
|
||||
|
||||
#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */
|
||||
#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
|
||||
|
||||
#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
|
||||
#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
|
||||
|
||||
#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
|
||||
#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
|
||||
|
||||
#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
|
||||
#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
|
||||
|
||||
#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
|
||||
#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
|
||||
|
||||
#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
|
||||
#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
|
||||
|
||||
#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
|
||||
#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
|
||||
|
||||
#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
|
||||
#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
|
||||
|
||||
#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
|
||||
#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
|
||||
|
||||
#define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */
|
||||
#define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */
|
||||
|
||||
#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
|
||||
#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
|
||||
|
||||
#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
|
||||
#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
|
||||
|
||||
#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
|
||||
#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
|
||||
|
||||
#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
|
||||
#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
|
||||
|
||||
#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
|
||||
#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
|
||||
|
||||
#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
|
||||
#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
|
||||
|
||||
#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
|
||||
#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
|
||||
|
||||
#define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */
|
||||
#define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */
|
||||
|
||||
#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
|
||||
#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
|
||||
|
||||
#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
|
||||
#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
|
||||
|
||||
#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
|
||||
#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
|
||||
|
||||
#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
|
||||
#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
|
||||
|
||||
#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
|
||||
#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
|
||||
|
||||
#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
|
||||
#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
|
||||
|
||||
#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
|
||||
#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
|
||||
|
||||
#define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */
|
||||
#define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */
|
||||
|
||||
#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
|
||||
#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
|
||||
|
||||
#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
|
||||
#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
|
||||
|
||||
#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
|
||||
#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
|
||||
|
||||
#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
|
||||
#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
|
||||
|
||||
#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
|
||||
#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
|
||||
|
||||
#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
|
||||
#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
|
||||
|
||||
#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
|
||||
#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
|
||||
|
||||
#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
|
||||
#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
|
||||
|
||||
#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
|
||||
#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
|
||||
|
||||
#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
|
||||
#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
|
||||
|
||||
#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
|
||||
#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
|
||||
|
||||
#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
|
||||
#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
|
||||
|
||||
#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
|
||||
#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
|
||||
|
||||
#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
|
||||
#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
|
||||
|
||||
#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
|
||||
#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
|
||||
|
||||
#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
|
||||
#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
|
||||
|
||||
#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
|
||||
#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
|
||||
|
||||
#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
|
||||
#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
|
||||
|
||||
#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
|
||||
#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
|
||||
|
||||
#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
|
||||
#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
|
||||
|
||||
#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
|
||||
#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
|
||||
|
||||
#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
|
||||
#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
|
||||
|
||||
#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
|
||||
#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
|
||||
|
||||
#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
|
||||
#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
|
||||
|
||||
#define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */
|
||||
#define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */
|
||||
|
||||
/**@}*/ /* RTC_CONST */
|
||||
/**@}*/ /* end of RTC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#endif /* __RTC_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,105 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_M031Series.h
|
||||
* @version V3.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/05/29 5:31p $
|
||||
* @brief M031 Series System Setting Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __SYSTEM_M031_H__
|
||||
#define __SYSTEM_M031_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macro Definition */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#ifndef DEBUG_PORT
|
||||
#define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
|
||||
#endif
|
||||
|
||||
/**
|
||||
*
|
||||
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
|
||||
* default clock source (External crystal or internal 22.1184MHz IRC).
|
||||
* Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to
|
||||
* user configuration setting in CONFIG0
|
||||
*
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define SYSCLK
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __HXT
|
||||
#define __HXT (32000000UL) /*!< External Crystal Clock Frequency */
|
||||
#endif /*!defined(__HXT) */
|
||||
|
||||
#ifndef __LXT
|
||||
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
|
||||
#endif /*!defined(__LXT) */
|
||||
|
||||
#define __LIRC (38400UL) /*!< Internal 38.4KHz RC Oscillator Frequency */
|
||||
#define __HIRC (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
|
||||
#define __HSI (96000000UL) /*!< PLL default output is 96MHz from HIRC */
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
||||
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
||||
|
||||
#if USE_ASSERT
|
||||
/**
|
||||
* @brief Assert Function
|
||||
*
|
||||
* @param[in] expr Expression to be evaluated
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If the expression is false, an error message will be printed out
|
||||
* from debug port (UART0 or UART1).
|
||||
*/
|
||||
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
|
||||
|
||||
void AssertError(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define ASSERT_PARAM(expr)
|
||||
#endif
|
||||
|
||||
#define assert_param(expr) ASSERT_PARAM(expr)
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */
|
||||
@@ -0,0 +1,336 @@
|
||||
/**************************************************************************//**
|
||||
* @file timer_reg.h
|
||||
* @version V1.00
|
||||
* @brief TIMER register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __TIMER_REG_H__
|
||||
#define __TIMER_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup TIMER Timer Controller (TIMER)
|
||||
Memory Mapped Structure for TIMER Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var TIMER_T::CTL
|
||||
* Offset: 0x00/0x20 Timer0~3 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |PSC |Prescale Counter
|
||||
* | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter. If this field is 0 (PSC = 0), then there is no scaling.
|
||||
* | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
|
||||
* |[8] |TRGPDMA |Trigger PDMA Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
|
||||
* | | |0 = Timer interrupt trigger PDMA Disabled.
|
||||
* | | |1 = Timer interrupt trigger PDMA Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PDMA. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PDMA.
|
||||
* |[9] |TRGBPWM |Trigger BPWM Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
|
||||
* | | |0 = Timer interrupt trigger BPWM Disabled.
|
||||
* | | |1 = Timer interrupt trigger BPWM Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger BPWM. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger BPWM.
|
||||
* |[10] |INTRGEN |Inter-timer Trigger Mode Enable Bit
|
||||
* | | |Setting this bit will enable the inter-timer trigger capture function.
|
||||
* | | |The Timer0/2 will be in event counter mode and counting with external clock source or event. Also, Timer1/3 will be in trigger-counting mode of capture function.
|
||||
* | | |0 = Inter-Timer Trigger mode Disabled.
|
||||
* | | |1 = Inter-Timer Trigger mode Enabled.
|
||||
* | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
|
||||
* |[16] |CAPSRC |Capture Pin Source Selection
|
||||
* | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
|
||||
* | | |1 = Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC as timer capture source.
|
||||
* |[18] |TRGSSEL |Trigger Source Select Bit
|
||||
* | | |This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
|
||||
* | | |0 = Timer time-out interrupt signal is used to trigger PWM, ADC and PDMA.
|
||||
* | | |1 = Capture interrupt signal is used to trigger PWM, ADC and PDMA.
|
||||
* |[19] |TRGPWM |Trigger PWM Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
|
||||
* | | |0 = Timer interrupt trigger PWM Disabled.
|
||||
* | | |1 = Timer interrupt trigger PWM Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
|
||||
* |[21] |TRGADC |Trigger ADC Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
|
||||
* | | |0 = Timer interrupt trigger ADC Disabled.
|
||||
* | | |1 = Timer interrupt trigger ADC Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger ADC. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger ADC.
|
||||
* |[22] |TGLPINSEL |Toggle-output Pin Select
|
||||
* | | |0 = Toggle mode output to Tx (Timer Event Counter Pin).
|
||||
* | | |1 = Toggle mode output to Tx_EXT (Timer External Capture Pin).
|
||||
* |[23] |WKEN |Wake-up Function Enable Bit
|
||||
* | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
|
||||
* | | |0 = Wake-up function Disabled if timer interrupt signal generated.
|
||||
* | | |1 = Wake-up function Enabled if timer interrupt signal generated.
|
||||
* |[24] |EXTCNTEN |Event Counter Mode Enable Bit
|
||||
* | | |This bit is for external counting pin function enabled.
|
||||
* | | |0 = Event counter mode Disabled.
|
||||
* | | |1 = Event counter mode Enabled.
|
||||
* | | |Note1: When timer is used as an event counter, this bit should be set to 1 and select PCLKx (x=0~1) as timer clock source.
|
||||
* | | |Note2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
|
||||
* |[25] |ACTSTS |Timer Active Status Bit (Read Only)
|
||||
* | | |This bit indicates the 24-bit up counter status.
|
||||
* | | |0 = 24-bit up counter is not active.
|
||||
* | | |1 = 24-bit up counter is active.
|
||||
* | | |Note: This bit may active when CNT 0 transition to CNT 1.
|
||||
* |[26] |RSTCNT |Timer Counter Reset Bit
|
||||
* | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
|
||||
* | | |Note: This bit will be auto cleared.
|
||||
* |[28:27] |OPMODE |Timer Counting Mode Select
|
||||
* | | |00 = The timer controller is operated in One-shot mode.
|
||||
* | | |01 = The timer controller is operated in Periodic mode.
|
||||
* | | |10 = The timer controller is operated in Toggle-output mode.
|
||||
* | | |11 = The timer controller is operated in Continuous Counting mode.
|
||||
* |[29] |INTEN |Timer Interrupt Enable Bit
|
||||
* | | |0 = Timer time-out interrupt Disabled.
|
||||
* | | |1 = Timer time-out interrupt Enabled.
|
||||
* | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
|
||||
* |[30] |CNTEN |Timer Counting Enable Bit
|
||||
* | | |0 = Stops/Suspends counting.
|
||||
* | | |1 = Starts counting.
|
||||
* | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
|
||||
* | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
|
||||
* | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
|
||||
* | | |0 = ICE debug mode acknowledgement effects TIMER counting.
|
||||
* | | |TIMER counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |TIMER counter will keep going no matter CPU is held by ICE or not.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var TIMER_T::CMP
|
||||
* Offset: 0x04/0x24 Timer0~3 Comparator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CMPDAT |Timer Comparator Value
|
||||
* | | |CMPDAT is a 24-bit compared value register
|
||||
* | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
|
||||
* | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
|
||||
* | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
|
||||
* | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
|
||||
* @var TIMER_T::INTSTS
|
||||
* Offset: 0x08/0x28 Timer0~3 Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TIF |Timer Interrupt Flag
|
||||
* | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = CNT value matches the CMPDAT value.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[1] |TWKF |Timer Wake-up Flag
|
||||
* | | |This bit indicates the interrupt wake-up flag status of timer.
|
||||
* | | |0 = Timer does not cause CPU wake-up.
|
||||
* | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* @var TIMER_T::CNT
|
||||
* Offset: 0x0C/0x2C Timer0~3 Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CNT |Timer Data Register
|
||||
* | | |Read this register to get CNT value. For example:
|
||||
* | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
|
||||
* | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
|
||||
* @var TIMER_T::CAP
|
||||
* Offset: 0x10/0x30 Timer0~3 Capture Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CAPDAT |Timer Capture Data Register
|
||||
* | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
|
||||
* @var TIMER_T::EXTCTL
|
||||
* Offset: 0x14/0x34 Timer0~3 External Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CNTPHASE |Timer External Count Phase
|
||||
* | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
|
||||
* | | |0 = A falling edge of external counting pin will be counted.
|
||||
* | | |1 = A rising edge of external counting pin will be counted.
|
||||
* |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
|
||||
* | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected.
|
||||
* | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected.
|
||||
* | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected.
|
||||
* | | |11 = Reserved.
|
||||
* |[3] |CAPEN |Timer Capture Enable Bit
|
||||
* | | |This bit enables the capture input function.
|
||||
* | | |0 =Capture source Disabled.
|
||||
* | | |1 =Capture source Enabled.
|
||||
* | | |Note: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled.
|
||||
* |[4] |CAPFUNCS |Capture Function Selection
|
||||
* | | |0 = External Capture Mode Enabled.
|
||||
* | | |1 = External Reset Mode Enabled.
|
||||
* | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
|
||||
* | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
|
||||
* |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit
|
||||
* | | |0 = TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled.
|
||||
* | | |1 = TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled.
|
||||
* | | |Note: CAPIEN is used to enable timer external interrupt
|
||||
* | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
|
||||
* | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT (x= 0~3) pin, or ACMP will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
|
||||
* |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit
|
||||
* | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
|
||||
* | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
|
||||
* | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
|
||||
* |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit
|
||||
* | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
|
||||
* | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
|
||||
* | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
|
||||
* |[10:8] |INTERCAPSEL|Internal Capture Source Selection to Trigger Capture Function
|
||||
* | | |000 = Capture Function source is from internal ACMP0 output signal.
|
||||
* | | |001 = Capture Function source is from internal ACMP1 output signal.
|
||||
* | | |101 = Capture Function source is from LIRC.
|
||||
* | | |Others = Reserved.
|
||||
* | | |Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
|
||||
* |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function
|
||||
* | | |0 = Event Counter input source is from TMx (x= 0~3) pin.
|
||||
* | | |1 = Event Counter input source is from USB internal SOF output signal.
|
||||
* @var TIMER_T::EINTSTS
|
||||
* Offset: 0x18/0x38 Timer0~3 External Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CAPIF |Timer External Capture Interrupt Flag
|
||||
* | | |This bit indicates the timer external capture interrupt flag status.
|
||||
* | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
|
||||
* | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
|
||||
* | | |Note1: This bit is cleared by writing 1 to it.
|
||||
* | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
|
||||
* | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] Timer0 Control Register */
|
||||
__IO uint32_t CMP; /*!< [0x0004] Timer0 Comparator Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x0008] Timer0 Interrupt Status Register */
|
||||
__I uint32_t CNT; /*!< [0x000c] Timer0 Data Register */
|
||||
__I uint32_t CAP; /*!< [0x0010] Timer0 Capture Data Register */
|
||||
__IO uint32_t EXTCTL; /*!< [0x0014] Timer0 External Control Register */
|
||||
__IO uint32_t EINTSTS; /*!< [0x0018] Timer0 External Interrupt Status Register */
|
||||
} TIMER_T;
|
||||
|
||||
/**
|
||||
@addtogroup TIMER_CONST TIMER Bit Field Definition
|
||||
Constant Definitions for TIMER Controller
|
||||
@{ */
|
||||
|
||||
#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
|
||||
#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
|
||||
|
||||
#define TIMER_CTL_TRGPDMA_Pos (8) /*!< TIMER_T::CTL: TRGPDMA Position */
|
||||
#define TIMER_CTL_TRGPDMA_Msk (0x1ul << TIMER_CTL_TRGPDMA_Pos) /*!< TIMER_T::CTL: TRGPDMA Mask */
|
||||
|
||||
#define TIMER_CTL_TRGBPWM_Pos (9) /*!< TIMER_T::CTL: TRGBPWM Position */
|
||||
#define TIMER_CTL_TRGBPWM_Msk (0x1ul << TIMER_CTL_TRGBPWM_Pos) /*!< TIMER_T::CTL: TRGBPWM Mask */
|
||||
|
||||
#define TIMER_CTL_INTRGEN_Pos (10) /*!< TIMER_T::CTL: INTRGEN Position */
|
||||
#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */
|
||||
|
||||
#define TIMER_CTL_CAPSRC_Pos (16) /*!< TIMER_T::CTL: CAPSRC Position */
|
||||
#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */
|
||||
|
||||
#define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
|
||||
#define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
|
||||
|
||||
#define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
|
||||
#define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
|
||||
|
||||
#define TIMER_CTL_TRGADC_Pos (21) /*!< TIMER_T::CTL: TRGADC Position */
|
||||
#define TIMER_CTL_TRGADC_Msk (0x1ul << TIMER_CTL_TRGADC_Pos) /*!< TIMER_T::CTL: TRGADC Mask */
|
||||
|
||||
#define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
|
||||
#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
|
||||
|
||||
#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
|
||||
#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
|
||||
|
||||
#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
|
||||
#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
|
||||
|
||||
#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
|
||||
#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
|
||||
|
||||
#define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
|
||||
#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
|
||||
|
||||
#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
|
||||
#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
|
||||
|
||||
#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
|
||||
#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
|
||||
|
||||
#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
|
||||
#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
|
||||
|
||||
#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
|
||||
#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
|
||||
#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
|
||||
|
||||
#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
|
||||
#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
|
||||
|
||||
#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
|
||||
#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
|
||||
|
||||
#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
|
||||
#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
|
||||
|
||||
#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
|
||||
#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
|
||||
#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
|
||||
#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
|
||||
#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
|
||||
#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
|
||||
#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
|
||||
#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
|
||||
#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */
|
||||
#define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */
|
||||
|
||||
#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */
|
||||
#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */
|
||||
|
||||
#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
|
||||
#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
|
||||
|
||||
/**@}*/ /* TIMER_CONST */
|
||||
/**@}*/ /* end of TIMER register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __TIMER_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,174 @@
|
||||
/**************************************************************************//**
|
||||
* @file wdt_reg.h
|
||||
* @version V1.00
|
||||
* @brief WDT register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WDT_REG_H__
|
||||
#define __WDT_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup WDT Watch Dog Timer Controller(WDT)
|
||||
Memory Mapped Structure for WDT Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @var WDT_T::CTL
|
||||
* Offset: 0x00 WDT Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect)
|
||||
* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
|
||||
* | | |0 = WDT time-out reset function Disabled.
|
||||
* | | |1 = WDT time-out reset function Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[2] |RSTF |WDT Time-out Reset Flag
|
||||
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
|
||||
* | | |0 = WDT time-out reset did not occur.
|
||||
* | | |1 = WDT time-out reset occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[3] |IF |WDT Time-out Interrupt Flag
|
||||
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.
|
||||
* | | |0 = WDT time-out interrupt did not occur.
|
||||
* | | |1 = WDT time-out interrupt occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
|
||||
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
|
||||
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
|
||||
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
|
||||
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
|
||||
* | | |This bit indicates the interrupt wake-up flag status of WDT.
|
||||
* | | |0 = WDT does not cause chip wake-up.
|
||||
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: This bit is cleared by writing 1 to it.
|
||||
* |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect)
|
||||
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
|
||||
* | | |0 = WDT time-out interrupt Disabled.
|
||||
* | | |1 = WDT time-out interrupt Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[7] |WDTEN |WDT Enable Bit (Write Protect)
|
||||
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
|
||||
* | | |1 = WDT Enabled.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
|
||||
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
|
||||
* | | |These four bits select the time-out interval period for the WDT.
|
||||
* | | |0000 = 24 * WDT_CLK.
|
||||
* | | |0001 = 26 * WDT_CLK.
|
||||
* | | |0010 = 28 * WDT_CLK.
|
||||
* | | |0011 = 210 * WDT_CLK.
|
||||
* | | |0100 = 212 * WDT_CLK.
|
||||
* | | |0101 = 214 * WDT_CLK.
|
||||
* | | |0110 = 216 * WDT_CLK.
|
||||
* | | |0111 = 218 * WDT_CLK.
|
||||
* | | |1000 = 220 * WDT_CLK.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
|
||||
* | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
|
||||
* | | |0 = Set WDTEN bit is completed.
|
||||
* | | |1 = Set WDTEN bit is synchronizing and not become active yet.
|
||||
* | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
|
||||
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
|
||||
* | | |WDT up counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var WDT_T::ALTCTL
|
||||
* Offset: 0x04 WDT Alternative Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect).
|
||||
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.
|
||||
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
|
||||
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
|
||||
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
|
||||
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
|
||||
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
|
||||
* @var WDT_T::RSTCNT
|
||||
* Offset: 0x08 WDT Reset Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RSTCNT |WDT Reset Counter Register
|
||||
* | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
|
||||
* | | |Note1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
|
||||
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
|
||||
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
|
||||
|
||||
} WDT_T;
|
||||
|
||||
/**
|
||||
@addtogroup WDT_CONST WDT Bit Field Definition
|
||||
Constant Definitions for WDT Controller
|
||||
@{ */
|
||||
|
||||
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
|
||||
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
|
||||
|
||||
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
|
||||
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
|
||||
|
||||
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
|
||||
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
|
||||
|
||||
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
|
||||
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
|
||||
|
||||
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
|
||||
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
|
||||
|
||||
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
|
||||
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
|
||||
|
||||
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
|
||||
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
|
||||
|
||||
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
|
||||
#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
|
||||
|
||||
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
|
||||
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
|
||||
|
||||
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
|
||||
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
|
||||
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
|
||||
|
||||
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
|
||||
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
|
||||
|
||||
/**@}*/ /* WDT_CONST */
|
||||
/**@}*/ /* end of WDT register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __WDT_REG_H__ */
|
||||
|
||||
@@ -0,0 +1,148 @@
|
||||
/**************************************************************************//**
|
||||
* @file wwdt_reg.h
|
||||
* @version V1.00
|
||||
* @brief WWDT register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WWDT_REG_H__
|
||||
#define __WWDT_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup WWDT Window Watchdog Timer(WWDT)
|
||||
Memory Mapped Structure for WWDT Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var WWDT_T::RLDCNT
|
||||
* Offset: 0x00 WWDT Reload Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RLDCNT |WWDT Reload Counter Register
|
||||
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
|
||||
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
|
||||
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
|
||||
* @var WWDT_T::CTL
|
||||
* Offset: 0x04 WWDT Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WWDTEN |WWDT Enable Bit
|
||||
* | | |0 = WWDT counter is stopped.
|
||||
* | | |1 = WWDT counter starts counting.
|
||||
* |[1] |INTEN |WWDT Interrupt Enable Bit
|
||||
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
|
||||
* | | |0 = WWDT counter compare match interrupt Disabled.
|
||||
* | | |1 = WWDT counter compare match interrupt Enabled.
|
||||
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
|
||||
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
|
||||
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
|
||||
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
|
||||
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
|
||||
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
|
||||
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
|
||||
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
|
||||
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
|
||||
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
|
||||
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
|
||||
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
|
||||
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
|
||||
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
|
||||
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
|
||||
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
|
||||
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
|
||||
* |[21:16] |CMPDAT |WWDT Window Compare Register
|
||||
* | | |Set this register to adjust the valid reload window.
|
||||
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
|
||||
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit
|
||||
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
|
||||
* | | |WWDT down counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
|
||||
* @var WWDT_T::STATUS
|
||||
* Offset: 0x08 WWDT Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
|
||||
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = WWDT counter value matches CMPDAT.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
|
||||
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
|
||||
* | | |0 = WWDT time-out reset did not occur.
|
||||
* | | |1 = WWDT time-out reset occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* @var WWDT_T::CNT
|
||||
* Offset: 0x0C WWDT Counter Value Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |CNTDAT |WWDT Counter Value
|
||||
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
|
||||
*/
|
||||
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
|
||||
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
|
||||
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
|
||||
|
||||
} WWDT_T;
|
||||
|
||||
/**
|
||||
@addtogroup WWDT_CONST WWDT Bit Field Definition
|
||||
Constant Definitions for WWDT Controller
|
||||
@{ */
|
||||
|
||||
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
|
||||
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
|
||||
|
||||
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
|
||||
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
|
||||
|
||||
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
|
||||
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
|
||||
|
||||
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
|
||||
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
|
||||
|
||||
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
|
||||
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
|
||||
|
||||
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
|
||||
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
|
||||
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
|
||||
|
||||
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
|
||||
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
|
||||
|
||||
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
|
||||
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
|
||||
|
||||
/**@}*/ /* WWDT_CONST */
|
||||
/**@}*/ /* end of WWDT register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __WWDT_REG_H__ */
|
||||
@@ -0,0 +1,259 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_m031series.s
|
||||
; * @version V2.00
|
||||
; * $Revision: 4 $
|
||||
; * $Date: 18/04/02 4:02p $
|
||||
; * @brief M031 Series Startup Source File
|
||||
; *
|
||||
; * @note
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
IF :LNOT: :DEF: Stack_Size
|
||||
Stack_Size EQU 0x00002000
|
||||
ENDIF
|
||||
|
||||
AREA |.STACK|, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
IF :LNOT: :DEF: Heap_Size
|
||||
Heap_Size EQU 0x00000000
|
||||
ENDIF
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT g_pfnVectors
|
||||
|
||||
g_pfnVectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; maximum of 32 External Interrupts are possible
|
||||
DCD BOD_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD EINT024_IRQHandler
|
||||
DCD EINT135_IRQHandler
|
||||
DCD GPABGH_IRQHandler
|
||||
DCD GPCDEF_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD TMR0_IRQHandler
|
||||
DCD TMR1_IRQHandler
|
||||
DCD TMR2_IRQHandler
|
||||
DCD TMR3_IRQHandler
|
||||
DCD UART02_IRQHandler
|
||||
DCD UART13_IRQHandler
|
||||
DCD SPI0_IRQHandler
|
||||
DCD QSPI0_IRQHandler
|
||||
DCD ISP_IRQHandler
|
||||
DCD UART57_IRQHandler
|
||||
DCD I2C0_IRQHandler
|
||||
DCD I2C1_IRQHandler
|
||||
DCD BPWM0_IRQHandler
|
||||
DCD BPWM1_IRQHandler
|
||||
DCD USCI01_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD Default_Handler
|
||||
DCD ACMP01_IRQHandler
|
||||
DCD PDMA_IRQHandler
|
||||
DCD UART46_IRQHandler
|
||||
DCD PWRWU_IRQHandler
|
||||
DCD ADC_IRQHandler
|
||||
DCD CKFAIL_IRQHandler
|
||||
DCD RTC_IRQHandler
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Init LDO_RDY
|
||||
LDR R2, =0x40000280
|
||||
LDR R1, =0x00000001
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT EINT024_IRQHandler [WEAK]
|
||||
EXPORT EINT135_IRQHandler [WEAK]
|
||||
EXPORT GPABGH_IRQHandler [WEAK]
|
||||
EXPORT GPCDEF_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT TMR0_IRQHandler [WEAK]
|
||||
EXPORT TMR1_IRQHandler [WEAK]
|
||||
EXPORT TMR2_IRQHandler [WEAK]
|
||||
EXPORT TMR3_IRQHandler [WEAK]
|
||||
EXPORT UART02_IRQHandler [WEAK]
|
||||
EXPORT UART13_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT QSPI0_IRQHandler [WEAK]
|
||||
EXPORT ISP_IRQHandler [WEAK]
|
||||
EXPORT UART57_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT BPWM0_IRQHandler [WEAK]
|
||||
EXPORT BPWM1_IRQHandler [WEAK]
|
||||
EXPORT USCI01_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT ACMP01_IRQHandler [WEAK]
|
||||
EXPORT PDMA_IRQHandler [WEAK]
|
||||
EXPORT UART46_IRQHandler [WEAK]
|
||||
EXPORT PWRWU_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CKFAIL_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
|
||||
BOD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
EINT024_IRQHandler
|
||||
EINT135_IRQHandler
|
||||
GPABGH_IRQHandler
|
||||
GPCDEF_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART02_IRQHandler
|
||||
UART13_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
QSPI0_IRQHandler
|
||||
ISP_IRQHandler
|
||||
UART57_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
BPWM0_IRQHandler
|
||||
BPWM1_IRQHandler
|
||||
USCI01_IRQHandler
|
||||
USBD_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
UART46_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,229 @@
|
||||
/**************************************************************************//**
|
||||
* @file startup_m031series.s
|
||||
* @version V2.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 18/04/12 4:44p $
|
||||
* @brief CMSIS Cortex-M0 Core Device Startup File for M031
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Unlock Register */
|
||||
ldr r0, =0x40000100
|
||||
ldr r1, =0x59
|
||||
str r1, [r0]
|
||||
ldr r1, =0x16
|
||||
str r1, [r0]
|
||||
ldr r1, =0x88
|
||||
str r1, [r0]
|
||||
|
||||
#if 1
|
||||
/* Init POR */
|
||||
ldr r0, =0x40000024
|
||||
ldr r1, =0x00005AA5
|
||||
str r1, [r0]
|
||||
|
||||
/* Init LDO_RDY */
|
||||
ldr r0, =0x40000280
|
||||
ldr r1, =0x00000001
|
||||
str r1, [r0]
|
||||
#endif
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2, #4]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Lock register */
|
||||
ldr r0, =0x40000100
|
||||
ldr r1, =0
|
||||
str r1, [r0]
|
||||
|
||||
/* Call the application entry point.*/
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/*******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.long _estack /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long BOD_IRQHandler /* 0: BOD */
|
||||
.long WDT_IRQHandler /* 1: WDT */
|
||||
.long EINT024_IRQHandler /* 2: EINT0 */
|
||||
.long EINT135_IRQHandler /* 3: EINT1 */
|
||||
.long GPABGH_IRQHandler /* 4: GPAB */
|
||||
.long GPCDEF_IRQHandler /* 5: GPCDEF */
|
||||
.long PWM0_IRQHandler /* 6: PWM0 */
|
||||
.long PWM1_IRQHandler /* 7: PWM1 */
|
||||
.long TMR0_IRQHandler /* 8: TIMER0 */
|
||||
.long TMR1_IRQHandler /* 9: TIMER1 */
|
||||
.long TMR2_IRQHandler /* 10: TIMER2 */
|
||||
.long TMR3_IRQHandler /* 11: TIMER3 */
|
||||
.long UART02_IRQHandler /* 12: UART02 */
|
||||
.long UART13_IRQHandler /* 13: UART13 */
|
||||
.long SPI0_IRQHandler /* 14: SPI0 */
|
||||
.long QSPI0_IRQHandler /* 15: QSPI0 */
|
||||
.long ISP_IRQHandler /* 16: Reserved */
|
||||
.long UART57_IRQHandler /* 17: UART57 */
|
||||
.long I2C0_IRQHandler /* 18: I2C0 */
|
||||
.long I2C1_IRQHandler /* 19: I2C1 */
|
||||
.long BPWM0_IRQHandler /* 20: BPWM0 */
|
||||
.long BPWM1_IRQHandler /* 21: BPWM1 */
|
||||
.long USCI01_IRQHandler /* 22: USCI01 */
|
||||
.long USBD_IRQHandler /* 23: USBD */
|
||||
.long Default_Handler /* 24: Reserved */
|
||||
.long ACMP01_IRQHandler /* 25: ACMP01 */
|
||||
.long PDMA_IRQHandler /* 26: PDMA */
|
||||
.long UART46_IRQHandler /* 27: UART46 */
|
||||
.long PWRWU_IRQHandler /* 28: PWRWU */
|
||||
.long ADC_IRQHandler /* 29: ADC */
|
||||
.long CKFAIL_IRQHandler /* 30: CLK Fail Detect */
|
||||
.long RTC_IRQHandler /* 31: RTC */
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler BOD_IRQHandler
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler EINT024_IRQHandler
|
||||
def_irq_handler EINT135_IRQHandler
|
||||
def_irq_handler GPABGH_IRQHandler
|
||||
def_irq_handler GPCDEF_IRQHandler
|
||||
def_irq_handler PWM0_IRQHandler
|
||||
def_irq_handler PWM1_IRQHandler
|
||||
def_irq_handler TMR0_IRQHandler
|
||||
def_irq_handler TMR1_IRQHandler
|
||||
def_irq_handler TMR2_IRQHandler
|
||||
def_irq_handler TMR3_IRQHandler
|
||||
def_irq_handler UART02_IRQHandler
|
||||
def_irq_handler UART13_IRQHandler
|
||||
def_irq_handler SPI0_IRQHandler
|
||||
def_irq_handler QSPI0_IRQHandler
|
||||
def_irq_handler ISP_IRQHandler
|
||||
def_irq_handler UART57_IRQHandler
|
||||
def_irq_handler I2C0_IRQHandler
|
||||
def_irq_handler I2C1_IRQHandler
|
||||
def_irq_handler BPWM0_IRQHandler
|
||||
def_irq_handler BPWM1_IRQHandler
|
||||
def_irq_handler USCI01_IRQHandler
|
||||
def_irq_handler USBD_IRQHandler
|
||||
def_irq_handler ACMP01_IRQHandler
|
||||
def_irq_handler PDMA_IRQHandler
|
||||
def_irq_handler UART46_IRQHandler
|
||||
def_irq_handler PWRWU_IRQHandler
|
||||
def_irq_handler ADC_IRQHandler
|
||||
def_irq_handler CKFAIL_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
|
||||
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,202 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_M031Series.s
|
||||
; * @version V3.00
|
||||
; * $Revision: 5 $
|
||||
; * $Date: 18/04/02 4:02p $
|
||||
; * @brief M031 Series Startup Source File for IAR Platform
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
|
||||
|
||||
EXTERN SystemInit
|
||||
EXTERN __iar_program_start
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD BOD_IRQHandler ; Brownout low voltage detected interrupt
|
||||
DCD WDT_IRQHandler ; Watch Dog Timer interrupt
|
||||
DCD EINT024_IRQHandler
|
||||
DCD EINT135_IRQHandler
|
||||
DCD GPABGH_IRQHandler
|
||||
DCD GPCDEF_IRQHandler
|
||||
DCD PWM0_IRQHandler ; PWM0 or PWM2 interrupt
|
||||
DCD PWM1_IRQHandler ; PWM1 or PWM3 interrupt
|
||||
DCD TMR0_IRQHandler ; Timer 0 interrupt
|
||||
DCD TMR1_IRQHandler ; Timer 1 interrupt
|
||||
DCD TMR2_IRQHandler ; Timer 2 interrupt
|
||||
DCD TMR3_IRQHandler ; Timer 3 interrupt
|
||||
DCD UART02_IRQHandler
|
||||
DCD UART13_IRQHandler
|
||||
DCD SPI0_IRQHandler
|
||||
DCD QSPI0_IRQHandler
|
||||
DCD ISP_IRQHandler
|
||||
DCD UART57_IRQHandler
|
||||
DCD I2C0_IRQHandler
|
||||
DCD I2C1_IRQHandler
|
||||
DCD BPWM0_IRQHandler
|
||||
DCD BPWM1_IRQHandler
|
||||
DCD USCI01_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD Default_Handler
|
||||
DCD ACMP01_IRQHandler
|
||||
DCD PDMA_IRQHandler
|
||||
DCD UART46_IRQHandler
|
||||
DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power-down
|
||||
DCD ADC_IRQHandler ; ADC interrupt
|
||||
DCD CKFAIL_IRQHandler ; Clock fail detect and IRC TRIM interrupt
|
||||
DCD RTC_IRQHandler
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2) ; 4 bytes alignment
|
||||
Reset_Handler
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Init LDO_RDY
|
||||
LDR R2, =0x40000280
|
||||
LDR R1, =0x00000001
|
||||
STR R1, [R2]
|
||||
|
||||
; Disable NMI (Assign to reserved IRQ)
|
||||
LDR R2, =0x40000380
|
||||
LDR R1, =0x0000001F
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK BOD_IRQHandler
|
||||
PUBWEAK WDT_IRQHandler
|
||||
PUBWEAK EINT024_IRQHandler
|
||||
PUBWEAK EINT135_IRQHandler
|
||||
PUBWEAK GPABGH_IRQHandler
|
||||
PUBWEAK GPCDEF_IRQHandler
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
PUBWEAK TMR0_IRQHandler
|
||||
PUBWEAK TMR1_IRQHandler
|
||||
PUBWEAK TMR2_IRQHandler
|
||||
PUBWEAK TMR3_IRQHandler
|
||||
PUBWEAK UART02_IRQHandler
|
||||
PUBWEAK UART13_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK QSPI0_IRQHandler
|
||||
PUBWEAK ISP_IRQHandler
|
||||
PUBWEAK UART57_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK BPWM0_IRQHandler
|
||||
PUBWEAK BPWM1_IRQHandler
|
||||
PUBWEAK USCI01_IRQHandler
|
||||
PUBWEAK USBD_IRQHandler
|
||||
PUBWEAK ACMP01_IRQHandler
|
||||
PUBWEAK PDMA_IRQHandler
|
||||
PUBWEAK UART46_IRQHandler
|
||||
PUBWEAK PWRWU_IRQHandler
|
||||
PUBWEAK ADC_IRQHandler
|
||||
PUBWEAK CKFAIL_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
|
||||
HardFault_Handler
|
||||
NMI_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BOD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
EINT024_IRQHandler
|
||||
EINT135_IRQHandler
|
||||
GPABGH_IRQHandler
|
||||
GPCDEF_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART02_IRQHandler
|
||||
UART13_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
QSPI0_IRQHandler
|
||||
ISP_IRQHandler
|
||||
UART57_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
BPWM0_IRQHandler
|
||||
BPWM1_IRQHandler
|
||||
USCI01_IRQHandler
|
||||
USBD_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
UART46_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
|
||||
|
||||
END
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_M031Series.c
|
||||
* @version V2.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/07/19 1:44p $
|
||||
* @brief M031 Series System Setting Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
const uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, __HSI, __LIRC, __HIRC, 0UL, 0UL, __HIRC};
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system. Global variables are forbidden here.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Unlock protected registers */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Set HXTGain Level dependend on HXT Frequency */
|
||||
CLK->PWRCTL = CLK->PWRCTL & ~CLK_PWRCTL_HXTGAIN_Msk;
|
||||
if ((__HXT >= FREQ_4MHZ) && (__HXT < FREQ_8MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (1 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_8MHZ) && (__HXT < FREQ_12MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (2 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_12MHZ) && (__HXT < FREQ_16MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (3 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_16MHZ) && (__HXT < FREQ_24MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (4 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLK->PWRCTL |= (7 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
|
||||
/* Lock protected registers */
|
||||
SYS_LockReg();
|
||||
}
|
||||
|
||||
#if USE_ASSERT
|
||||
|
||||
/**
|
||||
* @brief Assert Error Message
|
||||
*
|
||||
* @param[in] file the source file name
|
||||
* @param[in] line line number
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function prints the source file name and line number where
|
||||
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
|
||||
*/
|
||||
void AssertError(uint8_t * file, uint32_t line)
|
||||
{
|
||||
|
||||
printf("[%s] line %d : wrong parameters.\r\n", file, line);
|
||||
|
||||
/* Infinite loop */
|
||||
while(1) ;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
Nuvoton/M031/Source/system_M031Series.c
|
||||
""")
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src = src + ['Nuvoton/M031/Source/GCC/startup_M031Series.S']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src = src + ['Nuvoton/M031/Source/ARM/startup_M031Series.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src = src + ['Nuvoton/M031/Source/IAR/startup_M031Series.s']
|
||||
|
||||
path = [cwd + '/Nuvoton/M031/Include',]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user