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[bsp\fm33lc026] *增加gpio支持 *更新libraries\FM33LC0xx_FL_Driver FL库到V2.3.1 (#6175)

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* [bsp\fm33lc026] *增加gpio支持 *更新libraries\FM33LC0xx_FL_Driver到2021年新版本
This commit is contained in:
wudiyidashi
2022-07-26 10:11:12 +08:00
committed by GitHub
parent 32ed7dcfd2
commit 48d43678ed
97 changed files with 3043 additions and 2010 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/fm33lc026/.config
+88 -120
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File diff suppressed because it is too large Load Diff
bsp/fm33lc026/applications/main.c
+13 -14
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@@ -1,31 +1,30 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-27 Jiao first version
* Date Author Notes
* 2021-08-27 Jiao first version
* 2022-07-20 wudiyidashi support gpio
*/
#include <rtthread.h>
#include "board.h"
int main(void)
{
FL_GPIO_InitTypeDef GPIO_InitStruct = {0};
#define LED1 GET_PIN(D, 4)
int main(void)
{
rt_pin_mode(LED1, PIN_MODE_OUTPUT);
rt_pin_write(LED1, PIN_HIGH);
FL_GPIO_SetOutputPin(GPIOD, FL_GPIO_PIN_4);
GPIO_InitStruct.pin = FL_GPIO_PIN_4;
GPIO_InitStruct.mode = FL_GPIO_MODE_OUTPUT;
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct.pull = FL_DISABLE;
FL_GPIO_Init(GPIOD, &GPIO_InitStruct);
while (1)
{
FL_GPIO_SetOutputPin(GPIOD, FL_GPIO_PIN_4);
rt_pin_write(LED1, PIN_HIGH);
rt_thread_mdelay(500);
FL_GPIO_ResetOutputPin(GPIOD, FL_GPIO_PIN_4);
rt_pin_write(LED1, PIN_LOW);
rt_thread_mdelay(500);
}
bsp/fm33lc026/board/Kconfig
+9 -3
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@@ -9,6 +9,11 @@ config SOC_FM33LC0XX
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
@@ -29,10 +34,11 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_UART5
bool "Enable UART5"
default y
endif
source "../libraries/HAL_Drivers/Kconfig"
endmenu
endmenu
endmenu
bsp/fm33lc026/board/board.c
+27 -1
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -71,7 +71,33 @@ FL_ErrorStatus FL_UART_GPIO_Init(UART_Type *UARTx)
return status;
}
FL_ErrorStatus FL_SPI_GPIO_Init(SPI_Type *SPIx)
{
FL_ErrorStatus status = FL_FAIL;
FL_GPIO_InitTypeDef GPIO_InitStruct;
if (SPIx == SPI1)
{
GPIO_InitStruct.pin = FL_GPIO_PIN_11 | FL_GPIO_PIN_10 | FL_GPIO_PIN_9;
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct.pull = FL_DISABLE;
GPIO_InitStruct.remapPin = FL_DISABLE;
status=FL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
else if (SPIx == SPI2)
{
GPIO_InitStruct.pin = FL_GPIO_PIN_8 | FL_GPIO_PIN_10 | FL_GPIO_PIN_9;
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct.pull = FL_DISABLE;
GPIO_InitStruct.remapPin = FL_DISABLE;
status=FL_GPIO_Init(GPIOC, &GPIO_InitStruct);
}
return status;
}
static void RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLL_R, uint32_t PLL_DB, uint32_t PLL_O)
{
bsp/fm33lc026/board/board.h
+2 -1
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -13,6 +13,7 @@
#include <rtthread.h>
#include "fm33lc0xx_fl.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cm0plus.h
+1 -1
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@@ -22,7 +22,7 @@
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmFunc.h
+1 -1
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@@ -552,7 +552,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
/** \brief Set Base Priority with condition
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33_assert.h
+2 -2
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@@ -24,8 +24,8 @@
#ifdef __cplusplus
extern "C" {
#endif
#ifdef USE_FULL_ASSERT
#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0)
#else
bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lc0xx.h
+61 -61
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@@ -8,19 +8,19 @@
* @version V0.0.1
* @date 13. august 2019
*
* @note Generated with SVDConv V2.87e
* @note Generated with SVDConv V2.87e
* from CMSIS SVD File 'FM33LC0XX.SVD' Version 1.0,
*
* @par ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontroller, but can be equally used for other
* suitable processor architectures. This file can be freely distributed.
* Modifications to this file shall be clearly marked.
*
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*******************************************************************************************************/
@@ -41,7 +41,7 @@ extern "C" {
#endif /* __cplusplus */
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 0U /*!< MPU present or not */
@@ -51,8 +51,8 @@ extern "C" {
/**
* @brief FM33LC0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
* @brief FM33LC0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum {
/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
@@ -66,7 +66,7 @@ typedef enum {
WWDT_IRQn = 0, /*!< 0 Window WatchDog Interrupt */
SVD_IRQn = 1, /*!< 1 SVD Interrupt */
RTC_IRQn = 2, /*!< 2 RTC Interrupt */
FLASH_IRQn = 3, /*!< 3 FLASH global Interrupt */
FLASH_IRQn = 3, /*!< 3 FLASH global Interrupt */
LFDET_IRQn = 4, /*!< 4 LFDET Interrupt */
ADC_IRQn = 5, /*!< 5 ADC Interrupt */
IWDT_IRQn = 6, /*!< 6 IWDT Interrupt */
@@ -76,13 +76,13 @@ typedef enum {
UART0_IRQn = 10, /*!< 10 UART0 global Interrupt */
UART1_IRQn = 11, /*!< 11 UART1 global Interrupt */
UART4_IRQn = 12, /*!< 12 UART4 global Interrupt */
UART5_IRQn = 13, /*!< 13 UART5 global Interrupt */
UART5_IRQn = 13, /*!< 13 UART5 global Interrupt */
HFDET_IRQn = 14, /*!< 14 HFDET Interrupt */
U7816_IRQn = 15, /*!< 15 U7816 Interrupt */
LPUART1_IRQn = 16, /*!< 16 LPUART1 Interrupt */
I2C_IRQn = 17, /*!< 17 I2C global Interrupt */
USB_IRQn = 18, /*!< 18 USB Interrupt */
AES_IRQn = 19, /*!< 19 AES Interrupt */
AES_IRQn = 19, /*!< 19 AES Interrupt */
LPTIM_IRQn = 20, /*!< 20 LPTIM Interrupt */
DMA_IRQn = 21, /*!< 21 DMA Interrupt */
WKUP_IRQn = 22, /*!< 22 WKUP Interrupt */
@@ -114,10 +114,10 @@ typedef enum {
/** @addtogroup Peripheral_registers_structures
* @{
*/
*/
/**
* @brief Analog to Digital Converter
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
@@ -142,9 +142,9 @@ typedef struct
__IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */
__IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */
__IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */
__IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */
__IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */
__IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */
__IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */
__IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */
__IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */
__IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */
__IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */
__IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */
@@ -227,7 +227,7 @@ typedef struct
__IO uint32_t RSV;
__IO uint32_t CR; /*!< Debug Configuration Register */
__IO uint32_t HDFR; /*!< HardFault Flag Register*/
} DBG_Type;
typedef struct
@@ -236,7 +236,7 @@ typedef struct
__IO uint32_t CH0CR; /*!< Channel 0 Control Register , Address offset: 0x04 */
__IO uint32_t CH0MAD; /*!< Channel 0 Memory Address Register , Address offset: 0x08 */
__IO uint32_t CH1CR; /*!< Channel 1 Control Register , Address offset: 0x0C */
__IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register , Address offset: 0x10 */
__IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register , Address offset: 0x10 */
__IO uint32_t CH2CR; /*!< Channel 2 Control Register , Address offset: 0x14 */
__IO uint32_t CH2MAD; /*!< Channel 2 Memory Address Register , Address offset: 0x18 */
__IO uint32_t CH3CR; /*!< Channel 3 Control Register , Address offset: 0x1C */
@@ -270,7 +270,7 @@ typedef struct
__IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */
__IO uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */
__IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */
__IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */
__IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */
} FLASH_Type;
typedef struct
@@ -279,7 +279,7 @@ typedef struct
__IO uint32_t PUEN; /*!< Pull-Up Enable Register */
__IO uint32_t ODEN; /*!< Open-Drain Enable Register */
__IO uint32_t FCR; /*!< Function Control Register */
__IO uint32_t DO; /*!< Data Output Register */
__IO uint32_t DO; /*!< Data Output Register */
__O uint32_t DSET; /*!< Data Set Register */
__O uint32_t DRST; /*!< Data Reset Register */
__I uint32_t DIN; /*!< Data Input RegisterR */
@@ -294,7 +294,7 @@ typedef struct
__IO uint32_t EXTIEDS; /*!< External Interrupt Edge Select and Enable Register */
__IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register */
__IO uint32_t EXTIISR; /*!< External Interrupt and Status Register */
__IO uint32_t EXTIDI; /*!< External Interrupt Data Input Register */
__IO uint32_t EXTIDI; /*!< External Interrupt Data Input Register */
__IO uint32_t RSV0[59]; /*!< RESERVED REGISTER */
__IO uint32_t FOUTSEL; /*!< Frequency Output Select Register */
__IO uint32_t RSV1[63]; /*!< RESERVED REGISTER */
@@ -336,7 +336,7 @@ typedef struct
__IO uint32_t SOR; /*!< Divisor Regsiter, Address offset: 0x04 */
__IO uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */
__IO uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */
__IO uint32_t SR; /*!< Status Register, Address offset: 0x10 */
__IO uint32_t SR; /*!< Status Register, Address offset: 0x10 */
} DIV_Type;
@@ -349,14 +349,14 @@ typedef struct
__IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */
__IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */
__IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */
__IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */
__IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */
__IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */
__IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */
__IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */
__IO uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */
__IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */
__IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */
__IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */
__IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */
__IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */
__IO uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */
__IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */
__IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */
__IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */
} I2C_Type;
typedef struct
@@ -374,13 +374,13 @@ typedef struct
__IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */
__IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */
__IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */
__IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */
__IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */
__IO uint32_t RSV0; /*!< NULL, Address offset: 0x10 */
__IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */
__IO uint32_t RSV1; /*!< NULL, Address offset: 0x1C */
__IO uint32_t RSV2; /*!< NULL, Address offset: 0x20 */
__IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */
__IO uint32_t RSV1; /*!< NULL, Address offset: 0x1C */
__IO uint32_t RSV2; /*!< NULL, Address offset: 0x20 */
__IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */
__IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */
__IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */
__IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */
@@ -403,7 +403,7 @@ typedef struct
__IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */
__IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */
__IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */
__IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */
__IO uint32_t RSV; /*!< RESERVED REGISTER, Address offset: 0x1C */
__IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */
__IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */
@@ -417,7 +417,7 @@ typedef struct
__IO uint32_t BMR; /*!< LPUART Baud rate Modulation Register, Address offset: 0x0C */
__IO uint32_t RXBUF; /*!< LPUART Receive Buffer Register, Address offset: 0x10 */
__IO uint32_t TXBUF; /*!< LPUART Transmit Buffer Register, Address offset: 0x14 */
__IO uint32_t DMR; /*!< LPUART data Matching Register, Address offset: 0x18 */
__IO uint32_t DMR; /*!< LPUART data Matching Register, Address offset: 0x18 */
} LPUART_Type;
@@ -466,8 +466,8 @@ typedef struct
__IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Control Register2 , Address offset: 0x5C */
__IO uint32_t XTHFCR; /*!< XTHF Control Register , Address offset: 0x60 */
__IO uint32_t RCMFCR; /*!< RCMF Control Register , Address offset: 0x64 */
__IO uint32_t RCMFTR; /*!< RCHF Trim Register , Address offset: 0x68 */
__IO uint32_t OPCCR1; /*!< Peripheral Operation Clock Control Register1, Address offset: 0x6C */
__IO uint32_t RCMFTR; /*!< RCHF Trim Register , Address offset: 0x68 */
__IO uint32_t OPCCR1; /*!< Peripheral Operation Clock Control Register1, Address offset: 0x6C */
__IO uint32_t OPCCR2; /*!< Peripheral Operation Clock Control Register2, Address offset: 0x70 */
__IO uint32_t PHYCR; /*!< PHY Control Register , Address offset: 0x74 */
__IO uint32_t PHYBCKCR; /*!< PHY BCK Control Register , Address offset: 0x78 */
@@ -491,10 +491,10 @@ typedef struct
__IO uint32_t DOR; /*!< RNG OUTPUT REGISTER, Address offset: 0x04 */
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */
__IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x0C */
__IO uint32_t SR; /*!< RNG FLAG REGISTER, Address offset: 0x10 */
__IO uint32_t CRCCR; /*!< RNG CRC CONTROL REGISTER, Address offset: 0x14 */
__IO uint32_t CRCDIR; /*!< RNG CRC INPUT REGISTER, Address offset: 0x18 */
__IO uint32_t CRCSR; /*!< RNG CRC FLAG REGISTER, Address offset: 0x1C */
__IO uint32_t SR; /*!< RNG FLAG REGISTER, Address offset: 0x10 */
__IO uint32_t CRCCR; /*!< RNG CRC CONTROL REGISTER, Address offset: 0x14 */
__IO uint32_t CRCDIR; /*!< RNG CRC INPUT REGISTER, Address offset: 0x18 */
__IO uint32_t CRCSR; /*!< RNG CRC FLAG REGISTER, Address offset: 0x1C */
} RNG_Type;
typedef struct
@@ -506,9 +506,9 @@ typedef struct
__IO uint32_t BCDMIN; /*!< RTC MINITE IN BCD REGISTER, Address offset: 0x10 */
__IO uint32_t BCDHOUR; /*!< RTC HOUR IN BCD REGISTER, Address offset: 0x14 */
__IO uint32_t BCDDAY; /*!< RTC DAY IN BCD REGISTER, Address offset: 0x18 */
__IO uint32_t BCDWEEK; /*!< RTC WEEK IN BCD REGISTER, Address offset: 0x1C */
__IO uint32_t BCDMONTH; /*!< RTC MONTH IN BCD REGISTER, Address offset: 0x20 */
__IO uint32_t BCDYEAR; /*!< RTC YEAR IN BCD REGISTER, Address offset: 0x24 */
__IO uint32_t BCDWEEK; /*!< RTC WEEK IN BCD REGISTER, Address offset: 0x1C */
__IO uint32_t BCDMONTH; /*!< RTC MONTH IN BCD REGISTER, Address offset: 0x20 */
__IO uint32_t BCDYEAR; /*!< RTC YEAR IN BCD REGISTER, Address offset: 0x24 */
__IO uint32_t ALARM; /*!< RTC Alarm Register, Address offset: 0x28 */
__IO uint32_t TMSEL; /*!< RTC Time Mark Select, Address offset: 0x2C */
__IO uint32_t ADJUST; /*!< RTC time Adjust Register, Address offset: 0x30 */
@@ -532,7 +532,7 @@ typedef struct
__IO uint32_t CR2; /*!< SPI1 Control Register2 */
__IO uint32_t CR3; /*!< SPI1 Control Register3 */
__IO uint32_t IER; /*!< SPI1 Interrupt Enable Register */
__IO uint32_t ISR; /*!< SPI1 Status Register */
__IO uint32_t ISR; /*!< SPI1 Status Register */
__IO uint32_t TXBUF; /*!< SPI1 Transmit Buffer */
__IO uint32_t RXBUF; /*!< SPI1 Receive Buffer */
} SPI_Type;
@@ -571,10 +571,10 @@ typedef struct
__IO uint32_t GINTMSK; /*!< USB Global Interrupt Mask Register, Address offset: 0x18 */
__IO uint32_t GRXSTSR; /*!< USB Receive Status Debug Read Register, Address offset: 0x1C */
__IO uint32_t GRXSTSP; /*!< USB Receive Status and Pop Register, Address offset: 0x20 */
__IO uint32_t GRXFSIZ; /*!< USB Receive FIFO size Register, Address offset: 0x24 */
__IO uint32_t GNPTXFSIZ; /*!< USB Non-Periodic Transmit FIFO size Register, Address offset: 0x28 */
__IO uint32_t GRXFSIZ; /*!< USB Receive FIFO size Register, Address offset: 0x24 */
__IO uint32_t GNPTXFSIZ; /*!< USB Non-Periodic Transmit FIFO size Register, Address offset: 0x28 */
__IO uint32_t RSV2[10]; /*!< Reserved */
__IO uint32_t GLPMCFG; /*!< USB Low-Power-Mode config Register, Address offset: 0x54 */
__IO uint32_t GLPMCFG; /*!< USB Low-Power-Mode config Register, Address offset: 0x54 */
__IO uint32_t RSV3[490]; /*!< Reserved */
__IO uint32_t DCFG; /*!< USB Device Config Register, Address offset: 0x800*/
__IO uint32_t DCTL; /*!< USB Device Control Register, Address offset: 0x804*/
@@ -635,12 +635,12 @@ typedef struct
__IO uint32_t PCGCCTL; /*!< USB Power Control Global Control Register, Address offset: 0xE00*/
} USB_Type;
typedef struct
typedef struct
{
__IO uint32_t IRCR; /*!< Infrared modulation Control Register */
__IO uint32_t IRCR; /*!< Infrared modulation Control Register */
} UART_COMMON_Type;
typedef struct
typedef struct
{
__IO uint32_t CSR; /*!< UART Control Status Register */
__IO uint32_t IER; /*!< UART Interrupt Enable Register */
@@ -649,7 +649,7 @@ typedef struct
__IO uint32_t RXBUF; /*!< UART Receive Buffer */
__IO uint32_t TXBUF; /*!< UART Transmit Buffer */
__IO uint32_t BGR; /*!< UART Baud rate Generator Register */
} UART_Type;
} UART_Type;
typedef struct
@@ -667,15 +667,15 @@ typedef struct
__IO uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */
__IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */
__IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */
__IO uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */
__IO uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */
} WWDT_Type;
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE 0x00000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
*/
#define FLASH_BASE 0x00000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
#define SRAM_BASE 0x20000000UL
#define PERIPH_BASE 0x40000000UL
@@ -697,9 +697,9 @@ typedef struct
#define U7816_BASE (PERIPH_BASE + 0x00010000UL)
#define LPUART0_BASE (PERIPH_BASE + 0x00010400UL)
#define SPI2_BASE (PERIPH_BASE + 0x00010800UL)
#define LCD_BASE (PERIPH_BASE + 0x00010C00UL)
#define LCD_BASE (PERIPH_BASE + 0x00010C00UL)
#define RTC_BASE (PERIPH_BASE + 0x00011000UL)
#define IWDT_BASE (PERIPH_BASE + 0x00011400UL)
#define IWDT_BASE (PERIPH_BASE + 0x00011400UL)
#define WWDT_BASE (PERIPH_BASE + 0x00011800UL)
#define UART0_BASE (PERIPH_BASE + 0x00011C00UL)
#define UART1_BASE (PERIPH_BASE + 0x00012000UL)
@@ -707,13 +707,13 @@ typedef struct
#define LPTIM32_BASE (PERIPH_BASE + 0x00013400UL)
#define GPTIM0_BASE (PERIPH_BASE + 0x00013800UL)
#define GPTIM1_BASE (PERIPH_BASE + 0x00013C00UL)
#define CRC_BASE (PERIPH_BASE + 0x00018000UL)
#define CRC_BASE (PERIPH_BASE + 0x00018000UL)
#define LPUART1_BASE (PERIPH_BASE + 0x00018400UL)
#define SPI1_BASE (PERIPH_BASE + 0x00018C00UL)
#define DIVAS_BASE (PERIPH_BASE + 0x00019000UL)
#define UART_COMMON_BASE (PERIPH_BASE + 0x00019C00UL)
#define UART4_BASE (PERIPH_BASE + 0x0001A000UL)
#define UART5_BASE (PERIPH_BASE + 0x0001A400UL)
#define UART_COMMON_BASE (PERIPH_BASE + 0x00019C00UL)
#define UART4_BASE (PERIPH_BASE + 0x0001A000UL)
#define UART5_BASE (PERIPH_BASE + 0x0001A400UL)
#define RMU_BASE (PERIPH_BASE + 0x0001A800UL)
#define VREF_BASE (PERIPH_BASE + 0x0001A80CUL)
#define SVD_BASE (PERIPH_BASE + 0x0001A824UL)
bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lg0xx.h
+7 -7
View File
@@ -6,7 +6,7 @@
* @version V0.0.1
* @date 14 july 2020
*
* @note Generated with SVDConv V2.87e
* @note Generated with SVDConv V2.87e
* from CMSIS SVD File 'FM33LG0XX.SVD' Version 1.0,
*
* @par ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -45,7 +45,7 @@ extern "C" {
#define __XTLF_CLOCK (32768) /* Value of the EXTERNAL oscillator in Hz */
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 1U /*!< MPU present or not */
@@ -55,10 +55,10 @@ extern "C" {
/* ------------------------- Interrupt Number Definition ------------------------ */
/**
* @brief FM33LG0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
* @brief FM33LG0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum {
/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
Reset_IRQn = -15, /*!< 1 复位向量 */
@@ -71,7 +71,7 @@ typedef enum {
/* -------------------- FM33LG0XX specific Interrupt Numbers --------------------*/
WWDT_IRQn = 0, /*!< 0 窗口看门狗或独立看门狗中断 */
SVD_IRQn = 1, /*!< 1 电源监测报警中断 */
RTCx_IRQn = 2, /*!< 2 实时时钟中断 */
RTCx_IRQn = 2, /*!< 2 实时时钟中断 */
FLASH_IRQn = 3, /*!< 3 NVMIF中断 */
FDET_IRQn = 4, /*!< 4 XTLF或XTHF停振检测中断、系统时钟选择错误中断 */
ADC_IRQn = 5, /*!< 5 ADC转换完成中断 */
@@ -769,7 +769,7 @@ typedef struct
__IO uint32_t TMSEL; /*!< RTCA Time Mark Select, Address offset: 0x2C */
__IO uint32_t ADJUST; /*!< RTCA time Adjust Register, Address offset: 0x30 */
__IO uint32_t ADSIGN; /*!< RTCA time Adjust Sign Register, Address offset: 0x34 */
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */
__IO uint32_t SBSCNT; /*!< RTCA Sub-Second Counter, Address offset: 0x3C */
__IO uint32_t CR; /*!< RTCA Control Register, Address offset: 0x40 */
}RTCA_Type;
bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33xx.h
+7 -7
View File
@@ -17,24 +17,24 @@
* See the Mulan PSL v1 for more details.
*
****************************************************************************************************
*/
*/
/** @addtogroup CMSIS
* @{
*/
#ifndef __FM33xx_H
#define __FM33xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief FM33 Family
*/
@@ -52,7 +52,7 @@
|(__FM33x0xx_CMSIS_VERSION_SUB1 << 16)\
|(__FM33x0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__FM33x0xx_CMSIS_VERSION_RC))
/**
* @}
*/
@@ -105,6 +105,6 @@
/**
* @}
*/
/************************ (C) COPYRIGHT Fudan Microelectronics *****END OF FILE****/
bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lc0xx.h
+14 -14
View File
@@ -46,7 +46,7 @@ extern "C" {
#include <stdint.h>
#include <stdio.h>
#include "fm33lc0xx.h"
#define USE_LSCLK_CLOCK_SRC_XTLF
//#define SYSCLK_SRC_RC4M
@@ -54,8 +54,8 @@ extern "C" {
#define SYSCLK_SRC_RCHF
//#define SYSCLK_SRC_PLL
//#define USE_PLL_CLOCK_SRC_RCHF
//#define USE_PLL_CLOCK_SRC_XTHF
@@ -77,11 +77,11 @@ extern "C" {
#if !defined (XTHF_VALUE)
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* XTHF_VALUE */
#endif /* XTHF_VALUE */
#if !defined (XTLF_VALUE)
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
#endif /* XTLF_VALUE */
#endif /* XTLF_VALUE */
#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
@@ -89,9 +89,9 @@ extern "C" {
((~_N_VALUE_) & 0xffff)) ? _N_VALUE_ : _T_VALUE_)
#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20) // LPOSC 常温校准值
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值
#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44) // RCMF 常温校准值
#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xff)
@@ -99,7 +99,7 @@ extern "C" {
#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7f)
#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7f)
#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7f)
#define __SYSTEM_CLOCK (8000000)
@@ -111,7 +111,7 @@ typedef struct
{
/* 中断抢占优先级 */
uint32_t preemptPriority;
}NVIC_ConfigTypeDef;
@@ -138,13 +138,13 @@ void SystemInit (void);
extern uint32_t SystemCoreClock;
void SystemCoreClockUpdate (void);
/**
* @brief NVIC_Init config NVIC
* @brief NVIC_Init config NVIC
*
* @param NVIC_configStruct configParams
* @param NVIC_configStruct configParams
*
* @param IRQn Interrupt number
* @param IRQn Interrupt number
*
* @retval None
* @retval None
*/
void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn);
bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lg0xx.h
+8 -8
View File
@@ -46,17 +46,17 @@ extern "C" {
#include <stdint.h>
#include <stdio.h>
#include "fm33lg0xx.h"
#if !defined (XTHF_VALUE)
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* XTHF_VALUE */
#endif /* XTHF_VALUE */
#if !defined (XTLF_VALUE)
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
#endif /* XTLF_VALUE */
#endif /* XTLF_VALUE */
#define __SYSTEM_CLOCK (8000000)
#define DELAY_US (__SYSTEM_CLOCK/1000000)
#define DELAY_MS (__SYSTEM_CLOCK/1000)
@@ -64,12 +64,12 @@ extern "C" {
#define Do_DelayStart() { \
uint32_t LastTick = SysTick->VAL; do {
#define While_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); \
}
#define While_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); \
}
}
/**
* Initialize the system
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cm0plus.h
+1 -1
View File
@@ -22,7 +22,7 @@
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmFunc.h
+1 -1
View File
@@ -552,7 +552,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
/** \brief Set Base Priority with condition
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33_assert.h
+2 -2
View File
@@ -24,8 +24,8 @@
#ifdef __cplusplus
extern "C" {
#endif
#ifdef USE_FULL_ASSERT
#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0)
#else
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lc0xx.h
+65 -64
View File
@@ -8,24 +8,24 @@
* @version V0.0.1
* @date 13. august 2019
*
* @note Generated with SVDConv V2.87e
* @note Generated with SVDConv V2.87e
* from CMSIS SVD File 'FM33LC0XX.SVD' Version 1.0,
*
* @par ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontroller, but can be equally used for other
* suitable processor architectures. This file can be freely distributed.
* Modifications to this file shall be clearly marked.
*
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*******************************************************************************************************/
/** @addtogroup Keil
/** @addtogroup CMSIS
* @{
*/
@@ -41,7 +41,7 @@ extern "C" {
#endif /* __cplusplus */
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 0U /*!< MPU present or not */
@@ -51,8 +51,8 @@ extern "C" {
/**
* @brief FM33LC0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
* @brief FM33LC0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum {
/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
@@ -66,7 +66,7 @@ typedef enum {
WWDT_IRQn = 0, /*!< 0 Window WatchDog Interrupt */
SVD_IRQn = 1, /*!< 1 SVD Interrupt */
RTC_IRQn = 2, /*!< 2 RTC Interrupt */
FLASH_IRQn = 3, /*!< 3 FLASH global Interrupt */
FLASH_IRQn = 3, /*!< 3 FLASH global Interrupt */
LFDET_IRQn = 4, /*!< 4 LFDET Interrupt */
ADC_IRQn = 5, /*!< 5 ADC Interrupt */
IWDT_IRQn = 6, /*!< 6 IWDT Interrupt */
@@ -76,13 +76,13 @@ typedef enum {
UART0_IRQn = 10, /*!< 10 UART0 global Interrupt */
UART1_IRQn = 11, /*!< 11 UART1 global Interrupt */
UART4_IRQn = 12, /*!< 12 UART4 global Interrupt */
UART5_IRQn = 13, /*!< 13 UART5 global Interrupt */
UART5_IRQn = 13, /*!< 13 UART5 global Interrupt */
HFDET_IRQn = 14, /*!< 14 HFDET Interrupt */
U7816_IRQn = 15, /*!< 15 U7816 Interrupt */
LPUART1_IRQn = 16, /*!< 16 LPUART1 Interrupt */
I2C_IRQn = 17, /*!< 17 I2C global Interrupt */
USB_IRQn = 18, /*!< 18 USB Interrupt */
AES_IRQn = 19, /*!< 19 AES Interrupt */
AES_IRQn = 19, /*!< 19 AES Interrupt */
LPTIM_IRQn = 20, /*!< 20 LPTIM Interrupt */
DMA_IRQn = 21, /*!< 21 DMA Interrupt */
WKUP_IRQn = 22, /*!< 22 WKUP Interrupt */
@@ -108,16 +108,16 @@ typedef enum {
/* ================================================================================ */
#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */
#include "system_fm33lc0xx.h" /*!< FM33LC0XX System */
#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */
#include "system_fm33lc0xx.h" /*!< FM33LC0XX System */
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
*/
/**
* @brief Analog to Digital Converter
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
@@ -142,9 +142,9 @@ typedef struct
__IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */
__IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */
__IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */
__IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */
__IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */
__IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */
__IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */
__IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */
__IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */
__IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */
__IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */
__IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */
@@ -227,7 +227,7 @@ typedef struct
__IO uint32_t RSV;
__IO uint32_t CR; /*!< Debug Configuration Register */
__IO uint32_t HDFR; /*!< HardFault Flag Register*/
} DBG_Type;
typedef struct
@@ -236,7 +236,7 @@ typedef struct
__IO uint32_t CH0CR; /*!< Channel 0 Control Register , Address offset: 0x04 */
__IO uint32_t CH0MAD; /*!< Channel 0 Memory Address Register , Address offset: 0x08 */
__IO uint32_t CH1CR; /*!< Channel 1 Control Register , Address offset: 0x0C */
__IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register , Address offset: 0x10 */
__IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register , Address offset: 0x10 */
__IO uint32_t CH2CR; /*!< Channel 2 Control Register , Address offset: 0x14 */
__IO uint32_t CH2MAD; /*!< Channel 2 Memory Address Register , Address offset: 0x18 */
__IO uint32_t CH3CR; /*!< Channel 3 Control Register , Address offset: 0x1C */
@@ -270,7 +270,7 @@ typedef struct
__IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */
__IO uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */
__IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */
__IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */
__IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */
} FLASH_Type;
typedef struct
@@ -279,7 +279,7 @@ typedef struct
__IO uint32_t PUEN; /*!< Pull-Up Enable Register */
__IO uint32_t ODEN; /*!< Open-Drain Enable Register */
__IO uint32_t FCR; /*!< Function Control Register */
__IO uint32_t DO; /*!< Data Output Register */
__IO uint32_t DO; /*!< Data Output Register */
__O uint32_t DSET; /*!< Data Set Register */
__O uint32_t DRST; /*!< Data Reset Register */
__I uint32_t DIN; /*!< Data Input RegisterR */
@@ -294,7 +294,7 @@ typedef struct
__IO uint32_t EXTIEDS; /*!< External Interrupt Edge Select and Enable Register */
__IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register */
__IO uint32_t EXTIISR; /*!< External Interrupt and Status Register */
__IO uint32_t EXTIDI; /*!< External Interrupt Data Input Register */
__IO uint32_t EXTIDI; /*!< External Interrupt Data Input Register */
__IO uint32_t RSV0[59]; /*!< RESERVED REGISTER */
__IO uint32_t FOUTSEL; /*!< Frequency Output Select Register */
__IO uint32_t RSV1[63]; /*!< RESERVED REGISTER */
@@ -336,7 +336,7 @@ typedef struct
__IO uint32_t SOR; /*!< Divisor Regsiter, Address offset: 0x04 */
__IO uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */
__IO uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */
__IO uint32_t SR; /*!< Status Register, Address offset: 0x10 */
__IO uint32_t SR; /*!< Status Register, Address offset: 0x10 */
} DIV_Type;
@@ -349,14 +349,14 @@ typedef struct
__IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */
__IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */
__IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */
__IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */
__IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */
__IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */
__IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */
__IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */
__IO uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */
__IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */
__IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */
__IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */
__IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */
__IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */
__IO uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */
__IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */
__IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */
__IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */
} I2C_Type;
typedef struct
@@ -374,13 +374,13 @@ typedef struct
__IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */
__IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */
__IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */
__IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */
__IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */
__IO uint32_t RSV0; /*!< NULL, Address offset: 0x10 */
__IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */
__IO uint32_t RSV1; /*!< NULL, Address offset: 0x1C */
__IO uint32_t RSV2; /*!< NULL, Address offset: 0x20 */
__IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */
__IO uint32_t RSV1; /*!< NULL, Address offset: 0x1C */
__IO uint32_t RSV2; /*!< NULL, Address offset: 0x20 */
__IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */
__IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */
__IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */
__IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */
@@ -403,7 +403,7 @@ typedef struct
__IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */
__IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */
__IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */
__IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */
__IO uint32_t RSV; /*!< RESERVED REGISTER, Address offset: 0x1C */
__IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */
__IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */
@@ -417,7 +417,7 @@ typedef struct
__IO uint32_t BMR; /*!< LPUART Baud rate Modulation Register, Address offset: 0x0C */
__IO uint32_t RXBUF; /*!< LPUART Receive Buffer Register, Address offset: 0x10 */
__IO uint32_t TXBUF; /*!< LPUART Transmit Buffer Register, Address offset: 0x14 */
__IO uint32_t DMR; /*!< LPUART data Matching Register, Address offset: 0x18 */
__IO uint32_t DMR; /*!< LPUART data Matching Register, Address offset: 0x18 */
} LPUART_Type;
@@ -466,8 +466,8 @@ typedef struct
__IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Control Register2 , Address offset: 0x5C */
__IO uint32_t XTHFCR; /*!< XTHF Control Register , Address offset: 0x60 */
__IO uint32_t RCMFCR; /*!< RCMF Control Register , Address offset: 0x64 */
__IO uint32_t RCMFTR; /*!< RCHF Trim Register , Address offset: 0x68 */
__IO uint32_t OPCCR1; /*!< Peripheral Operation Clock Control Register1, Address offset: 0x6C */
__IO uint32_t RCMFTR; /*!< RCHF Trim Register , Address offset: 0x68 */
__IO uint32_t OPCCR1; /*!< Peripheral Operation Clock Control Register1, Address offset: 0x6C */
__IO uint32_t OPCCR2; /*!< Peripheral Operation Clock Control Register2, Address offset: 0x70 */
__IO uint32_t PHYCR; /*!< PHY Control Register , Address offset: 0x74 */
__IO uint32_t PHYBCKCR; /*!< PHY BCK Control Register , Address offset: 0x78 */
@@ -491,10 +491,10 @@ typedef struct
__IO uint32_t DOR; /*!< RNG OUTPUT REGISTER, Address offset: 0x04 */
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */
__IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x0C */
__IO uint32_t SR; /*!< RNG FLAG REGISTER, Address offset: 0x10 */
__IO uint32_t CRCCR; /*!< RNG CRC CONTROL REGISTER, Address offset: 0x14 */
__IO uint32_t CRCDIR; /*!< RNG CRC INPUT REGISTER, Address offset: 0x18 */
__IO uint32_t CRCSR; /*!< RNG CRC FLAG REGISTER, Address offset: 0x1C */
__IO uint32_t SR; /*!< RNG FLAG REGISTER, Address offset: 0x10 */
__IO uint32_t CRCCR; /*!< RNG CRC CONTROL REGISTER, Address offset: 0x14 */
__IO uint32_t CRCDIR; /*!< RNG CRC INPUT REGISTER, Address offset: 0x18 */
__IO uint32_t CRCSR; /*!< RNG CRC FLAG REGISTER, Address offset: 0x1C */
} RNG_Type;
typedef struct
@@ -506,9 +506,9 @@ typedef struct
__IO uint32_t BCDMIN; /*!< RTC MINITE IN BCD REGISTER, Address offset: 0x10 */
__IO uint32_t BCDHOUR; /*!< RTC HOUR IN BCD REGISTER, Address offset: 0x14 */
__IO uint32_t BCDDAY; /*!< RTC DAY IN BCD REGISTER, Address offset: 0x18 */
__IO uint32_t BCDWEEK; /*!< RTC WEEK IN BCD REGISTER, Address offset: 0x1C */
__IO uint32_t BCDMONTH; /*!< RTC MONTH IN BCD REGISTER, Address offset: 0x20 */
__IO uint32_t BCDYEAR; /*!< RTC YEAR IN BCD REGISTER, Address offset: 0x24 */
__IO uint32_t BCDWEEK; /*!< RTC WEEK IN BCD REGISTER, Address offset: 0x1C */
__IO uint32_t BCDMONTH; /*!< RTC MONTH IN BCD REGISTER, Address offset: 0x20 */
__IO uint32_t BCDYEAR; /*!< RTC YEAR IN BCD REGISTER, Address offset: 0x24 */
__IO uint32_t ALARM; /*!< RTC Alarm Register, Address offset: 0x28 */
__IO uint32_t TMSEL; /*!< RTC Time Mark Select, Address offset: 0x2C */
__IO uint32_t ADJUST; /*!< RTC time Adjust Register, Address offset: 0x30 */
@@ -532,7 +532,7 @@ typedef struct
__IO uint32_t CR2; /*!< SPI1 Control Register2 */
__IO uint32_t CR3; /*!< SPI1 Control Register3 */
__IO uint32_t IER; /*!< SPI1 Interrupt Enable Register */
__IO uint32_t ISR; /*!< SPI1 Status Register */
__IO uint32_t ISR; /*!< SPI1 Status Register */
__IO uint32_t TXBUF; /*!< SPI1 Transmit Buffer */
__IO uint32_t RXBUF; /*!< SPI1 Receive Buffer */
} SPI_Type;
@@ -571,14 +571,15 @@ typedef struct
__IO uint32_t GINTMSK; /*!< USB Global Interrupt Mask Register, Address offset: 0x18 */
__IO uint32_t GRXSTSR; /*!< USB Receive Status Debug Read Register, Address offset: 0x1C */
__IO uint32_t GRXSTSP; /*!< USB Receive Status and Pop Register, Address offset: 0x20 */
__IO uint32_t GRXFSIZ; /*!< USB Receive FIFO size Register, Address offset: 0x24 */
__IO uint32_t GNPTXFSIZ; /*!< USB Non-Periodic Transmit FIFO size Register, Address offset: 0x28 */
__IO uint32_t GRXFSIZ; /*!< USB Receive FIFO size Register, Address offset: 0x24 */
__IO uint32_t GNPTXFSIZ; /*!< USB Non-Periodic Transmit FIFO size Register, Address offset: 0x28 */
__IO uint32_t RSV2[10]; /*!< Reserved */
__IO uint32_t GLPMCFG; /*!< USB Low-Power-Mode config Register, Address offset: 0x54 */
__IO uint32_t GLPMCFG; /*!< USB Low-Power-Mode config Register, Address offset: 0x54 */
__IO uint32_t RSV3[490]; /*!< Reserved */
__IO uint32_t DCFG; /*!< USB Device Config Register, Address offset: 0x800*/
__IO uint32_t DCTL; /*!< USB Device Control Register, Address offset: 0x804*/
__IO uint32_t DSTS; /*!< USB Device Status Register, Address offset: 0x808*/
__IO uint32_t RSV31; /*!< Reserved , Address offset: 0x80C*/
__IO uint32_t DIEPMSK; /*!< USB Device In Endpoint Interrupt Mask Register, Address offset: 0x810*/
__IO uint32_t DOEPMSK; /*!< USB Device OUT Endpoint Interrupt Mask Registe, Address offset: 0x814*/
__IO uint32_t DAINT; /*!< USB Device All Endpoint Interrupt Register, Address offset: 0x818*/
@@ -635,12 +636,12 @@ typedef struct
__IO uint32_t PCGCCTL; /*!< USB Power Control Global Control Register, Address offset: 0xE00*/
} USB_Type;
typedef struct
typedef struct
{
__IO uint32_t IRCR; /*!< Infrared modulation Control Register */
__IO uint32_t IRCR; /*!< Infrared modulation Control Register */
} UART_COMMON_Type;
typedef struct
typedef struct
{
__IO uint32_t CSR; /*!< UART Control Status Register */
__IO uint32_t IER; /*!< UART Interrupt Enable Register */
@@ -649,7 +650,7 @@ typedef struct
__IO uint32_t RXBUF; /*!< UART Receive Buffer */
__IO uint32_t TXBUF; /*!< UART Transmit Buffer */
__IO uint32_t BGR; /*!< UART Baud rate Generator Register */
} UART_Type;
} UART_Type;
typedef struct
@@ -667,15 +668,15 @@ typedef struct
__IO uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */
__IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */
__IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */
__IO uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */
__IO uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */
} WWDT_Type;
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE 0x00000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
*/
#define FLASH_BASE 0x00000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
#define SRAM_BASE 0x20000000UL
#define PERIPH_BASE 0x40000000UL
@@ -697,9 +698,9 @@ typedef struct
#define U7816_BASE (PERIPH_BASE + 0x00010000UL)
#define LPUART0_BASE (PERIPH_BASE + 0x00010400UL)
#define SPI2_BASE (PERIPH_BASE + 0x00010800UL)
#define LCD_BASE (PERIPH_BASE + 0x00010C00UL)
#define LCD_BASE (PERIPH_BASE + 0x00010C00UL)
#define RTC_BASE (PERIPH_BASE + 0x00011000UL)
#define IWDT_BASE (PERIPH_BASE + 0x00011400UL)
#define IWDT_BASE (PERIPH_BASE + 0x00011400UL)
#define WWDT_BASE (PERIPH_BASE + 0x00011800UL)
#define UART0_BASE (PERIPH_BASE + 0x00011C00UL)
#define UART1_BASE (PERIPH_BASE + 0x00012000UL)
@@ -707,13 +708,13 @@ typedef struct
#define LPTIM32_BASE (PERIPH_BASE + 0x00013400UL)
#define GPTIM0_BASE (PERIPH_BASE + 0x00013800UL)
#define GPTIM1_BASE (PERIPH_BASE + 0x00013C00UL)
#define CRC_BASE (PERIPH_BASE + 0x00018000UL)
#define CRC_BASE (PERIPH_BASE + 0x00018000UL)
#define LPUART1_BASE (PERIPH_BASE + 0x00018400UL)
#define SPI1_BASE (PERIPH_BASE + 0x00018C00UL)
#define DIVAS_BASE (PERIPH_BASE + 0x00019000UL)
#define UART_COMMON_BASE (PERIPH_BASE + 0x00019C00UL)
#define UART4_BASE (PERIPH_BASE + 0x0001A000UL)
#define UART5_BASE (PERIPH_BASE + 0x0001A400UL)
#define UART_COMMON_BASE (PERIPH_BASE + 0x00019C00UL)
#define UART4_BASE (PERIPH_BASE + 0x0001A000UL)
#define UART5_BASE (PERIPH_BASE + 0x0001A400UL)
#define RMU_BASE (PERIPH_BASE + 0x0001A800UL)
#define VREF_BASE (PERIPH_BASE + 0x0001A80CUL)
#define SVD_BASE (PERIPH_BASE + 0x0001A824UL)
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lg0xx.h
+7 -7
View File
@@ -6,7 +6,7 @@
* @version V0.0.1
* @date 14 july 2020
*
* @note Generated with SVDConv V2.87e
* @note Generated with SVDConv V2.87e
* from CMSIS SVD File 'FM33LG0XX.SVD' Version 1.0,
*
* @par ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -45,7 +45,7 @@ extern "C" {
#define __XTLF_CLOCK (32768) /* Value of the EXTERNAL oscillator in Hz */
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 1U /*!< MPU present or not */
@@ -55,10 +55,10 @@ extern "C" {
/* ------------------------- Interrupt Number Definition ------------------------ */
/**
* @brief FM33LG0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
* @brief FM33LG0XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum {
/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
Reset_IRQn = -15, /*!< 1 复位向量 */
@@ -71,7 +71,7 @@ typedef enum {
/* -------------------- FM33LG0XX specific Interrupt Numbers --------------------*/
WWDT_IRQn = 0, /*!< 0 窗口看门狗或独立看门狗中断 */
SVD_IRQn = 1, /*!< 1 电源监测报警中断 */
RTCx_IRQn = 2, /*!< 2 实时时钟中断 */
RTCx_IRQn = 2, /*!< 2 实时时钟中断 */
FLASH_IRQn = 3, /*!< 3 NVMIF中断 */
FDET_IRQn = 4, /*!< 4 XTLF或XTHF停振检测中断、系统时钟选择错误中断 */
ADC_IRQn = 5, /*!< 5 ADC转换完成中断 */
@@ -769,7 +769,7 @@ typedef struct
__IO uint32_t TMSEL; /*!< RTCA Time Mark Select, Address offset: 0x2C */
__IO uint32_t ADJUST; /*!< RTCA time Adjust Register, Address offset: 0x30 */
__IO uint32_t ADSIGN; /*!< RTCA time Adjust Sign Register, Address offset: 0x34 */
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */
__IO uint32_t SBSCNT; /*!< RTCA Sub-Second Counter, Address offset: 0x3C */
__IO uint32_t CR; /*!< RTCA Control Register, Address offset: 0x40 */
}RTCA_Type;
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33xx.h
+7 -7
View File
@@ -17,24 +17,24 @@
* See the Mulan PSL v1 for more details.
*
****************************************************************************************************
*/
*/
/** @addtogroup CMSIS
* @{
*/
#ifndef __FM33xx_H
#define __FM33xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief FM33 Family
*/
@@ -52,7 +52,7 @@
|(__FM33x0xx_CMSIS_VERSION_SUB1 << 16)\
|(__FM33x0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__FM33x0xx_CMSIS_VERSION_RC))
/**
* @}
*/
@@ -105,6 +105,6 @@
/**
* @}
*/
/************************ (C) COPYRIGHT Fudan Microelectronics *****END OF FILE****/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lc0xx.h
+105 -97
View File
@@ -2,8 +2,8 @@
* @file system_fm33lc0xx.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
* Device FM33LC0XX
* @version V2.00
* @date 15. March 2021
* @version V2.0.0
* @date 15. Mar 2021
*
* @note
*
@@ -35,7 +35,6 @@
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_FM33LC0XX_H
#define SYSTEM_FM33LC0XX_H
@@ -43,110 +42,119 @@
extern "C" {
#endif
#include <stdint.h>
#include <stdio.h>
#include "fm33lc0xx.h"
#define USE_LSCLK_CLOCK_SRC_XTLF
//#define SYSCLK_SRC_RC4M
//#define SYSCLK_SRC_XTHF
#define SYSCLK_SRC_RCHF
//#define SYSCLK_SRC_PLL
//#define USE_PLL_CLOCK_SRC_RCHF
//#define USE_PLL_CLOCK_SRC_XTHF
#if ((!defined(SYSCLK_SRC_RC4M)) && (!defined(SYSCLK_SRC_XTHF))&&(!defined(SYSCLK_SRC_PLL))&&(!defined(SYSCLK_SRC_RCHF)))
#error "Must select a clock source form the SYSCLK_SRC_RC4M or SYSCLK_SRC_XTHF or SYSCLK_SRC_PLL or SYSCLK_SRC_RCHF as the master clock."
#elif (((defined(SYSCLK_SRC_RC4M)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\
((defined(SYSCLK_SRC_XTHF)) && ((defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\
((defined(SYSCLK_SRC_PLL)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_RCHF))))||\
((defined(SYSCLK_SRC_RCHF)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RC4M)))))
#error "Only one clock source can be selected as the master clock."
#endif
#if defined(SYSCLK_SRC_PLL) && !defined(USE_PLL_CLOCK_SRC_RCHF) && !defined(USE_PLL_CLOCK_SRC_XTHF)
#error "You have chosen to enable the PLL, so you need to specify the clock source for the PLL.."
#elif defined(SYSCLK_SRC_PLL) && (defined(USE_PLL_CLOCK_SRC_RCHF) && defined(USE_PLL_CLOCK_SRC_XTHF))
#error "Please select one of the USE_PLL_CLOCK_SRC_RCHF and USE_PLL_CLOCK_SRC_XTHF in your application"
#endif
#if !defined (XTHF_VALUE)
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* XTHF_VALUE */
#if !defined (XTLF_VALUE)
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
#endif /* XTLF_VALUE */
#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
((((_N_VALUE_ >> 16) & 0xffff) == \
((~_N_VALUE_) & 0xffff)) ? _N_VALUE_ : _T_VALUE_)
#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20) // LPOSC 常温校准值
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值
#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44) // RCMF 常温校准值
#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xff)
#define RCMF4M_TRIM (LDT_CHECK(RCMF4M_LDT_TRIM, 0x40) & 0x7f)
#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7f)
#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7f)
#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7f)
#define __SYSTEM_CLOCK (8000000)
/**
* @brief FL NVIC Init Sturcture definition
* @brief CMSIS Device version number
*/
typedef struct
{
/* 中断抢占优先级 */
uint32_t preemptPriority;
}NVIC_ConfigTypeDef;
#define __FM33LC0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __FM33LC0xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __FM33LC0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:0] sub2 version */
#define __FM33LC0xx_CMSIS_VERSION ((__FM33LC0xx_CMSIS_VERSION_MAIN << 24)\
|(__FM33LC0xx_CMSIS_VERSION_SUB1 << 16)\
|(__FM33LC0xx_CMSIS_VERSION_SUB2))
/* Configurations ------------------------------------------------------------*/
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
* @brief LSCLK source
* @note Comment the following line to use only LPOSC as LSCLK source, and also
* disable LSCLK auto switch function.
*/
void SystemInit (void);
#define USE_LSCLK_CLOCK_SRC_XTLF
#ifdef USE_LSCLK_CLOCK_SRC_XTLF
/**
* @brief LSCLK source
* @note Comment the following line to disable LSCLK auto switch function.
*/
#define USE_LSCLK_AUTO_SWITCH
#endif /* USE_LSCLK_CLOCK_SRC_XTLF */
/**
* @brief Open IWDT on program startup
* @note Uncomment the following line to use IWDT on startup. User can modify
* the IWDT_OVERFLOW_PERIOD to change the IDWT overflow period.
*/
/* #define USE_IWDT_ON_STARTUP */
#ifdef USE_IWDT_ON_STARTUP
/*
Valid value of IWDT_OVERFLOW_PERIOD:
- 0x0: 125ms
- 0x1: 250ms
- 0x2: 500ms
- 0x3: 1s
- 0x4: 2s
- 0x5: 4s
- 0x6: 8s
- 0x7: 16s
*/
#define IWDT_OVERFLOW_PERIOD 0x7
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/* Device Includes -----------------------------------------------------------*/
#include "fm33lc0xx.h"
/* Trim Values ---------------------------------------------------------------*/
/* Validate Function */
#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
((((_N_VALUE_ >> 16) & 0xFFFFU) == \
(~(_N_VALUE_) & 0xFFFFU)) ? (_N_VALUE_) : (_T_VALUE_))
/* Trim Values Address */
#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20U) /* LPOSC trim value */
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40U) /* RC8M trim value */
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3CU) /* RC16M trim value */
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38U) /* RC24M trim value */
#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44U) /* RCMF trim value */
/* Trim Values */
#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xFFU)
#define RCMF4M_TRIM (LDT_CHECK(RCMF4M_LDT_TRIM, 0x40) & 0x7FU)
#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7FU)
#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7FU)
#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7FU)
/* Default Clock Frequency Values --------------------------------------------*/
#define XTHF_DEFAULT_VALUE ((uint32_t)8000000U) /*!< Default value of XTHF in Hz */
#define XTLF_DEFAULT_VALUE ((uint32_t)32768U) /*!< Default value of XTLF in Hz */
/* Default system core clock value */
#define HCLK_DEFAULT_VALUE ((uint32_t)8000000U)
/* Exported Clock Frequency Variables --------------------------------------- */
/*
- [SystemCoreClock] holds the value of CPU operation clock freqency, and is initialized
to HCLK_DEFAULT_VALUE;
- [XTLFClock] holds the value of external low-frequency oscillator(XTLF),
and is initialized to XTLF_DEFAULT_VALUE;
- [XTHFClock] holds the value of external high_frequency oscillator(XTHF),
and is initialized to XTHF_DEFAULT_VALUE;
NOTE: If users are using these two external oscillators, they should modify the
value of XTLFClock and XTHFClock to the correct value, and call the SystemCoreClockUpdate()
to update the SystemCoreClock variable, otherwise those codes which rely on
the SystemCoreClock variable will fail to run.
*/
extern uint32_t XTLFClock; /*!< External Low-freq Osc Clock Frequency (XTLF) */
extern uint32_t XTHFClock; /*!< External High-freq Osc Clock Frequency (XTHF) */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern uint32_t SystemCoreClock;
void SystemCoreClockUpdate (void);
/**
* @brief NVIC_Init config NVIC
*
* @param NVIC_configStruct configParams
*
* @param IRQn Interrupt number
*
* @retval None
*/
void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn);
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lg0xx.h
+8 -8
View File
@@ -46,17 +46,17 @@ extern "C" {
#include <stdint.h>
#include <stdio.h>
#include "fm33lg0xx.h"
#if !defined (XTHF_VALUE)
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* XTHF_VALUE */
#endif /* XTHF_VALUE */
#if !defined (XTLF_VALUE)
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
#endif /* XTLF_VALUE */
#endif /* XTLF_VALUE */
#define __SYSTEM_CLOCK (8000000)
#define DELAY_US (__SYSTEM_CLOCK/1000000)
#define DELAY_MS (__SYSTEM_CLOCK/1000)
@@ -64,12 +64,12 @@ extern "C" {
#define Do_DelayStart() { \
uint32_t LastTick = SysTick->VAL; do {
#define While_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); \
}
#define While_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); \
}
}
/**
* Initialize the system
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/system_fm33lc0xx.c
+167 -151
View File
@@ -2,8 +2,8 @@
* @file system_fm33lc0xx.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
* Device FM33LC0XX
* @version V2.00
* @date 15. March 2021
* @version V2.0.0
* @date 15. Mar 2021
*
* @note
*
@@ -35,170 +35,171 @@
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "system_fm33lc0xx.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
/* Clock Variable definitions ------------------------------------------------*/
uint32_t XTLFClock = XTLF_DEFAULT_VALUE; /*!< External Low-freq Osc Clock Frequency (XTLF) */
uint32_t XTHFClock = XTHF_DEFAULT_VALUE; /*!< External High-freq Osc Clock Frequency (XTHF) */
uint32_t SystemCoreClock = HCLK_DEFAULT_VALUE; /*!< System Clock Frequency (Core Clock) */
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/* Clock functions -----------------------------------------------------------*/
/**
* @brief Retrieve the PLL clock frequency
*
* @retval PLL clock frequency
*/
static uint32_t SystemPLLClockUpdate(void)
{
uint32_t clock = 0;
// 时钟源
/* Acquire PLL clock source */
switch ((RCC->PLLCR >> 1) & 0x1)
{
case 0:
switch ((RCC->RCHFCR >> 16) & 0xf)
switch ((RCC->RCHFCR >> 16) & 0xFU)
{
case 1: // 16M
case 1: /* 16MHz */
clock = 16000000;
break;
case 2: // 24M
case 2: /* 24MHz */
clock = 24000000;
break;
case 0: // 8M
case 0: /* 8MHz */
default:
clock = 8000000;
break;
}
break;
case 1:
clock = XTHF_VALUE;
clock = XTHFClock;
break;
}
// 分频
/* Acquire PLL prescaler */
switch ((RCC->PLLCR >> 0x4) & 0x7)
{
case 0: // 不分频
case 0: /* input divided by 1 */
clock /= 1;
break;
case 1: // 2分频
clock /= 2;
case 1: /* input divided by 2 */
clock /= 2;
break;
case 2: // 4分频
case 2: /* input divided by 4 */
clock /= 4;
break;
case 3: // 8分频
case 3: /* input divided by 8 */
clock /= 8;
break;
case 4: // 12分频
case 4: /* input divided by 12 */
clock /= 12;
break;
case 5: // 16分频
case 5: /* input divided by 16 */
clock /= 16;
break;
case 6: // 24分频
case 6: /* input divided by 24 */
clock /= 24;
break;
case 7: // 32分频
case 7: /* input divided by 32 */
clock /= 32;
break;
}
// 倍频比
clock = clock * (((RCC->PLLCR >> 16) & 0x7f) + 1);
// 输出选择
/* Acquire PLL multiplier and calculate PLL frequency */
clock = clock * (((RCC->PLLCR >> 16) & 0x7F) + 1);
/* Acquire PLL output channel(PLLx1 or PLLx2) */
if ((RCC->PLLCR >> 3) & 0x1)
{
clock *= 2;
}
return clock;
}
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
/**
* @brief Update the core clock frequency variable: SystemCoreClock
*
*/
void SystemCoreClockUpdate(void)
{
switch ((RCC->SYSCLKCR >> 0) & 0x7)
{
case 1: // XTHF
SystemCoreClock = XTHF_VALUE;
{
case 1: /* XTHF */
SystemCoreClock = XTHFClock;
break;
case 2: // PLL
case 2: /* PLL */
SystemCoreClock = SystemPLLClockUpdate();
break;
case 4: // RCMF
case 4: /* RCMF */
switch ((RCC->RCMFCR >> 16) & 0x3)
{
case 0: // 不分频
case 0: /* output divided by 1 */
SystemCoreClock = 4000000;
break;
case 1: // 4分频
case 1: /* output divided by 4 */
SystemCoreClock = 1000000;
break;
case 2: // 8分频
case 2: /* output divided by 8 */
SystemCoreClock = 500000;
break;
case 3: // 16分频
case 3: /* output divided by 16 */
SystemCoreClock = 250000;
break;
}
break;
case 5: // LSCLK
case 6: // LPOSC
SystemCoreClock = 32768;
case 5: /* LSCLK */
#ifdef USE_LSCLK_CLOCK_SRC_LPOSC
SystemCoreClock = 32000;
#else
SystemCoreClock = XTLFClock;
#endif
break;
case 7: // USBBCK
case 6: /* LPOSC */
SystemCoreClock = 32000;
break;
case 7: /* USBBCK */
switch ((RCC->SYSCLKCR >> 3) & 0x1)
{
case 0: // USBBCK 48M
case 0: /* USBBCK 48MHz */
SystemCoreClock = 48000000;
break;
case 1: // USBBCK 120M 2分频
case 1: /* USBBCK 120MHz/2 */
SystemCoreClock = 60000000;
break;
}
break;
default:
switch ((RCC->RCHFCR >> 16) & 0xf)
{
case 1: // 16M
case 1: /* 16MHz */
SystemCoreClock = 16000000;
break;
case 2: // 24M
case 2: /* 24MHz */
SystemCoreClock = 24000000;
break;
case 0: // 8M
case 0: /* 8MHz */
default:
SystemCoreClock = 8000000;
break;
@@ -208,79 +209,94 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
}
/**
* @brief NVIC_Init config NVIC
*
* @param NVIC_configStruct configParams
*
* @param IRQn Interrupt number
*
* @retval None
*/
void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn)
{
/* Params Check */
if(NVIC_configStruct->preemptPriority>3)
{
NVIC_configStruct->preemptPriority = 3;
}
NVIC_DisableIRQ(IRQn);
NVIC_SetPriority(IRQn,NVIC_configStruct->preemptPriority);
NVIC_EnableIRQ(IRQn);
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
void SystemInit(void)
{
#if !defined(MFANG) && defined(USE_LSCLK_CLOCK_SRC_XTLF)
uint32_t temp;
/* */
RCC->PLLCR = (uint32_t)0x00000000U;
RCC->SYSCLKCR = (uint32_t)0x0A000000U;
/* PAD RCC*/
RCC->PCLKCR1 |= (0x1U << 7U);
#ifdef USE_LSCLK_CLOCK_SRC_XTLF
GPIOD->FCR |= 0x3C0000;
/* XTLF*/
RCC->XTLFCR = (uint32_t)(0x00000000U);
/* XTLF*/
RCC->XTLFCR |= (uint32_t)(0x00000005U<<8);
for(temp = 2000;temp>0;temp--);
/* LSCLKXTLF*/
RCC->LSCLKSEL = 0xAA;
/* LSCXTLF*/
RCC->SYSCLKCR |= 0x8000000U;
#else
RCC->SYSCLKCR &= 0x7FFFFFFU;
RCC->LSCLKSEL = 0x55;
#endif
/*PDR*/
RMU->PDRCR |=0x01;
/*BOR*/
RMU->BORCR &=0xFE;
/* DEBUG IWDT WWDT */
DBG->CR =0x03;
RCC->RCHFTR = RCHF24M_TRIM;
#if defined(USE_IWDT_ON_STARTUP)
RCC->PCLKCR1 |= 0x20U; /* Enable IWDT Operation Clock */
IWDT->CR = IWDT_OVERFLOW_PERIOD; /* Configure IWDT overflow period */
IWDT->SERV = 0x12345A5AU; /* Enable IWDT */
#endif
/* Reset PLL & SYSCLK selection */
RCC->PLLCR = 0x00000000U;
RCC->SYSCLKCR = 0x0A000000U;
/* Enable PAD Operation Clock */
RCC->PCLKCR1 |= (0x1U << 7);
#ifndef MFANG /* MFANG handles clock configurations by itself */
#ifdef USE_LSCLK_CLOCK_SRC_XTLF
/* XTLF IO configuration */
GPIOD->FCR |= 0x003C0000U;
/* Enable XTLF */
RCC->XTLFCR = 0x00000000U;
RCC->XTLFCR |= (uint32_t)(0x5U << 8);
for(temp = 2000U; temp > 0U; temp--);
#ifdef USE_LSCLK_AUTO_SWITCH
/* Enable LSCLK auto switch */
RCC->SYSCLKCR |= 0x8000000U;
/* LSCLK from XTLF */
RCC->LSCLKSEL = 0xAAU;
#else
/* Disable LSCLK auto switch */
CMU->SYSCLKCR &= 0x7FFFFFFU;
/* LSCLK from XTLF */
CMU->LSCLKSEL = 0xAAU;
#endif /* USE_LSCLK_AUTO_SWITCH */
#else
/* Disable LSCLK auto switch */
RCC->SYSCLKCR &= 0x7FFFFFFU;
/* LSCLK from LPOSC */
RCC->LSCLKSEL = 0x55U;
#endif /* USE_LSCLK_CLOCK_SRC_XTLF */
#endif /* MFANG */
/* PDR & BOR Configuration */
RMU->PDRCR = 0x1U;
RMU->BORCR = 0xEU;
/* Disable IWDT & WWDT, enable other peripherals(e.g. timers) under Debug Mode */
DBG->CR = 0x3U;
/* Load clock trim value */
RCC->RCHFTR = RCHF8M_TRIM;
RCC->RCMFTR = RCMF4M_TRIM;
RCC->LPOSCTR = LPOSC_TRIM;
GPIOD->PUEN |= 0x3 << 7;
/* Enable SWD port pull up */
GPIOD->PUEN |= (0x3U << 7U);
/* DMA Flash Channel: Flash->RAM */
RCC->PCLKCR2 |= 0x1 << 4;
DMA->CH7CR |= 0x1 << 10;
RCC->PCLKCR2 &= ~(0x1 << 4);
}
RCC->PCLKCR2 |= (0x1U << 4U);
DMA->CH7CR |= (0x1U << 10U);
RCC->PCLKCR2 &= ~(0x1U << 4U);
/* Update System Core Clock */
SystemCoreClockUpdate();
#if defined(USE_IWDT_ON_STARTUP)
IWDT->SERV = 0x12345A5AU; /* Feed IWDT */
#endif
}
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/system_fm33lg0xx.c
+3 -3
View File
@@ -61,7 +61,7 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Cl
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
}
/**
* Initialize the system
@@ -74,8 +74,8 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
*/
void SystemInit (void)
{
}
}
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33_assert.h
+40
View File
@@ -0,0 +1,40 @@
/**
****************************************************************************************************
* @file fm33_assert.h
* @author FMSH Application Team
* @brief Assert function define
****************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
*
****************************************************************************************************
*/
#ifndef __FM33_ASSERT_H
#define __FM33_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef USE_FULL_ASSERT
#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0)
#else
#define assert_param(expr) ((void)0U)
#endif
#ifdef __cplusplus
}
#endif
#endif
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl.h
+36 -208
View File
@@ -6,20 +6,20 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------------------------------*/
/* Define to prevent recursive inclusion --------------------------------------------------------------*/
#ifndef __FM33LC0XX_FL_H
#define __FM33LC0XX_FL_H
@@ -27,64 +27,12 @@
extern "C" {
#endif
/**
* @brief Select FM33LC0XX Device
*/
#if !defined (FM33LC0XX)
#define FM33LC0XX
#endif /* FM33LC0XX */
/* Defines -------------------------------------------------------------------------------------------*/
/**
* @brief List of drivers to be used.
*
* @note Uncomment following lines to disable specified driver.
*/
#ifndef MFANG
#define FL_ADC_DRIVER_ENABLED
#define FL_AES_DRIVER_ENABLED
#define FL_ATIM_DRIVER_ENABLED
#define FL_BSTIM32_DRIVER_ENABLED
#define FL_COMP_DRIVER_ENABLED
#define FL_CRC_DRIVER_ENABLED
#define FL_DIVAS_DRIVER_ENABLED
#define FL_DMA_DRIVER_ENABLED
#define FL_EXTI_DRIVER_ENABLED
#define FL_FLASH_DRIVER_ENABLED
#define FL_GPIO_DRIVER_ENABLED
#define FL_GPTIM_DRIVER_ENABLED
#define FL_I2C_DRIVER_ENABLED
#define FL_IWDT_DRIVER_ENABLED
#define FL_LCD_DRIVER_ENABLED
#define FL_LPTIM32_DRIVER_ENABLED
#define FL_LPUART_DRIVER_ENABLED
#define FL_OPA_DRIVER_ENABLED
#define FL_PMU_DRIVER_ENABLED
#define FL_RCC_DRIVER_ENABLED
#define FL_RMU_DRIVER_ENABLED
#define FL_RNG_DRIVER_ENABLED
#define FL_RTC_DRIVER_ENABLED
#define FL_SPI_DRIVER_ENABLED
#define FL_SVD_DRIVER_ENABLED
#define FL_U7816_DRIVER_ENABLED
#define FL_UART_DRIVER_ENABLED
#define FL_VREF_DRIVER_ENABLED
#define FL_WWDT_DRIVER_ENABLED
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33xx.h"
#include "fm33_assert.h"
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "fm33lc0xx_fl_conf.h"
#include "fm33lc0xx_fl_def.h"
/* Macros ---------------------------------------------------------------------------------------------*/
/** @defgroup FL_Private_Macros FL Driver Library Private Macros
/** @defgroup FL_Exported_Macros FL Driver Library Exported Macros
* @{
*/
@@ -92,7 +40,7 @@ extern "C" {
* @brief FM33LC0xx FL Driver Library version number
*/
#define __FM33LC0xx_FL_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __FM33LC0xx_FL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __FM33LC0xx_FL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __FM33LC0xx_FL_VERSION_SUB2 (0x01) /*!< [15:0] sub2 version */
#define __FM33LC0xx_FL_VERSION ((__FM33LC0xx_FL_VERSION_MAIN << 24)\
|(__FM33LC0xx_FL_VERSION_SUB1 << 16)\
@@ -108,44 +56,39 @@ extern "C" {
* @}
*/
/* Types ----------------------------------------------------------------------------------------------*/
/** @defgroup FL_ET_Return FL Exported Return Type Defines
/* Struct Defines -------------------------------------------------------------------------------------*/
/** @defgroup FL_ET_NVIC FL Driver Library NVIC Init Sturcture Defines
* @{
*/
typedef enum
typedef struct
{
FL_RESET = 0U,
FL_SET = !FL_RESET
} FL_FlagStatus, FL_ITStatus;
/** 中断抢占优先级 */
uint32_t preemptPriority;
typedef enum
{
FL_DISABLE = 0U,
FL_ENABLE = !FL_DISABLE
} FL_FunState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == FL_DISABLE) || ((STATE) == FL_ENABLE))
typedef enum
{
FL_FAIL = 0U,
FL_PASS = !FL_FAIL
} FL_ErrorStatus;
} FL_NVIC_ConfigTypeDef;
/**
* @}
*/
/* Exported Functions ---------------------------------------------------------------------------------*/
/** @defgroup FL_EF_DELAY Exported FL Driver Library Delay Support Functions
/** @defgroup FL_EF_DELAY FL Driver Library Exported Delay Support Functions
* @{
*/
void FL_DelayInit(void);
void FL_DelayUs(uint32_t count);
void FL_DelayMs(uint32_t count);
void FL_DelayUsStart(uint32_t count);
void FL_DelayMsStart(uint32_t count);
bool FL_DelayEnd(void);
/**
* @}
*/
/** @defgroup FL_EF_INIT Exported FL Driver Library Init Functions
/** @defgroup FL_EF_INIT FL Driver Library Exported Init Functions
* @{
*/
@@ -155,130 +98,15 @@ void FL_Init(void);
* @}
*/
/* Post Includes --------------------------------------------------------------------------------------*/
/**
* @brief Include peripheral's header file
/** @defgroup FL_EF_NVIC FL Driver Library Exported NVIC Configuration Functions
* @{
*/
#if defined(USE_FULL_ASSERT)
#include "fm33_assert.h"
#endif /* USE_FULL_ASSERT */
void FL_NVIC_Init(FL_NVIC_ConfigTypeDef *configStruct, IRQn_Type irq);
#if defined(FL_ADC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_adc.h"
#endif /* FL_ADC_DRIVER_ENABLED */
#if defined(FL_AES_DRIVER_ENABLED)
#include "fm33lc0xx_fl_aes.h"
#endif /* FL_AES_DRIVER_ENABLED */
#if defined(FL_ATIM_DRIVER_ENABLED)
#include "fm33lc0xx_fl_atim.h"
#endif /* FL_ATIM_DRIVER_ENABLED */
#if defined(FL_BSTIM32_DRIVER_ENABLED)
#include "fm33lc0xx_fl_bstim32.h"
#endif /* FL_BSTIM32_DRIVER_ENABLED */
#if defined(FL_COMP_DRIVER_ENABLED)
#include "fm33lc0xx_fl_comp.h"
#endif /* FL_COMP_DRIVER_ENABLED */
#if defined(FL_CRC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_crc.h"
#endif /* FL_CRC_DRIVER_ENABLED */
#if defined(FL_DIVAS_DRIVER_ENABLED)
#include "fm33lc0xx_fl_divas.h"
#endif /* FL_DIVAS_DRIVER_ENABLED */
#if defined(FL_DMA_DRIVER_ENABLED)
#include "fm33lc0xx_fl_dma.h"
#endif /* FL_DMA_DRIVER_ENABLED */
#if defined(FL_EXTI_DRIVER_ENABLED)
#include "fm33lc0xx_fl_exti.h"
#endif /* FL_EXTI_DRIVER_ENABLED */
#if defined(FL_FLASH_DRIVER_ENABLED)
#include "fm33lc0xx_fl_flash.h"
#endif /* FL_FLASH_DRIVER_ENABLED */
#if defined(FL_GPIO_DRIVER_ENABLED)
#include "fm33lc0xx_fl_gpio.h"
#endif /* FL_GPIO_DRIVER_ENABLED */
#if defined(FL_GPTIM_DRIVER_ENABLED)
#include "fm33lc0xx_fl_gptim.h"
#endif /* FL_GPTIM_DRIVER_ENABLED */
#if defined(FL_I2C_DRIVER_ENABLED)
#include "fm33lc0xx_fl_i2c.h"
#endif /* FL_I2C_DRIVER_ENABLED */
#if defined(FL_IWDT_DRIVER_ENABLED)
#include "fm33lc0xx_fl_iwdt.h"
#endif /* FL_IWDT_DRIVER_ENABLED */
#if defined(FL_LCD_DRIVER_ENABLED)
#include "fm33lc0xx_fl_lcd.h"
#endif /* FL_LCD_DRIVER_ENABLED */
#if defined(FL_LPTIM32_DRIVER_ENABLED)
#include "fm33lc0xx_fl_lptim32.h"
#endif /* FL_LPTIM32_DRIVER_ENABLED */
#if defined(FL_LPUART_DRIVER_ENABLED)
#include "fm33lc0xx_fl_lpuart.h"
#endif /* FL_LPUART_DRIVER_ENABLED */
#if defined(FL_OPA_DRIVER_ENABLED)
#include "fm33lc0xx_fl_opa.h"
#endif /* FL_OPA_DRIVER_ENABLED */
#if defined(FL_PMU_DRIVER_ENABLED)
#include "fm33lc0xx_fl_pmu.h"
#endif /* FL_PMU_DRIVER_ENABLED */
#if defined(FL_RCC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rcc.h"
#endif /* FL_RCC_DRIVER_ENABLED */
#if defined(FL_RMU_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rmu.h"
#endif /* FL_RMU_DRIVER_ENABLED */
#if defined(FL_RNG_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rng.h"
#endif /* FL_RNG_DRIVER_ENABLED */
#if defined(FL_RTC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rtc.h"
#endif /* FL_RTC_DRIVER_ENABLED */
#if defined(FL_SPI_DRIVER_ENABLED)
#include "fm33lc0xx_fl_spi.h"
#endif /* FL_SPI_DRIVER_ENABLED */
#if defined(FL_SVD_DRIVER_ENABLED)
#include "fm33lc0xx_fl_svd.h"
#endif /* FL_SVD_DRIVER_ENABLED */
#if defined(FL_U7816_DRIVER_ENABLED)
#include "fm33lc0xx_fl_u7816.h"
#endif /* FL_U7816_DRIVER_ENABLED */
#if defined(FL_UART_DRIVER_ENABLED)
#include "fm33lc0xx_fl_uart.h"
#endif /* FL_UART_DRIVER_ENABLED */
#if defined(FL_VREF_DRIVER_ENABLED)
#include "fm33lc0xx_fl_vref.h"
#endif /* FL_VREF_DRIVER_ENABLED */
#if defined(FL_WWDT_DRIVER_ENABLED)
#include "fm33lc0xx_fl_wwdt.h"
#endif /* FL_WWDT_DRIVER_ENABLED */
/**
* @}
*/
#ifdef __cplusplus
}
@@ -286,4 +114,4 @@ void FL_Init(void);
#endif /* __FM33LC0XX_FL_H */
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_adc.h
+16 -13
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -271,6 +271,7 @@ typedef struct
#define FL_ADC_INTERNAL_VREF1P2 (0x1U << 17U)
#define FL_ADC_INTERNAL_OPA1 (0x1U << 18U)
#define FL_ADC_INTERNAL_OPA2 (0x1U << 19U)
#define FL_ADC_ALL_CHANNEL (0xfffffU << 0U)
@@ -1488,6 +1489,7 @@ __STATIC_INLINE uint32_t FL_ADC_GetSamplingInterval(ADC_Type *ADCx)
* @arg @ref FL_ADC_INTERNAL_VREF1P2
* @arg @ref FL_ADC_INTERNAL_OPA1
* @arg @ref FL_ADC_INTERNAL_OPA2
* @arg @ref FL_ADC_ALL_CHANNEL
* @retval None
*/
__STATIC_INLINE void FL_ADC_EnableSequencerChannel(ADC_Type *ADCx, uint32_t channel)
@@ -1516,6 +1518,7 @@ __STATIC_INLINE void FL_ADC_EnableSequencerChannel(ADC_Type *ADCx, uint32_t chan
* @arg @ref FL_ADC_INTERNAL_VREF1P2
* @arg @ref FL_ADC_INTERNAL_OPA1
* @arg @ref FL_ADC_INTERNAL_OPA2
* @arg @ref FL_ADC_ALL_CHANNEL
* @retval None
*/
__STATIC_INLINE void FL_ADC_DisableSequencerChannel(ADC_Type *ADCx, uint32_t channel)
@@ -1616,14 +1619,14 @@ __STATIC_INLINE void FL_ADC_WriteAnalogWDGHighThreshold(ADC_Type *ADCx, uint32_t
*/
__STATIC_INLINE uint32_t FL_ADC_ReadAnalogWDGHighThreshold(ADC_Type *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->HLTR, 0xfffU) >> 16U);
return (uint32_t)(READ_BIT(ADCx->HLTR, (0xfffU << 16U)) >> 16U);
}
/**
* @}
*/
/** @defgroup ADC_FL_EF_Init Initialization and de-initialization functions
/** @defgroup ADC_FL_EF_Init ADC Initialization and de-initialization Functions
* @{
*/
FL_ErrorStatus FL_ADC_CommonDeInit(void);
@@ -1652,4 +1655,4 @@ FL_ErrorStatus FL_ADC_CommonInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
#endif /* __FM33LC0XX_FL_ADC_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_aes.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -698,4 +698,4 @@ FL_ErrorStatus FL_AES_Init(AES_Type *AESx, FL_AES_InitTypeDef *AES_InitStructer)
#endif /* __FM33LC0XX_FL_AES_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_atim.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -3787,4 +3787,4 @@ FL_ErrorStatus FL_ATIM_BDTR_Init(ATIM_Type *TIMx, FL_ATIM_BDTR_InitTypeDef *TIM_
#endif /* __FM33LC0XX_FL_ATIM_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_bstim32.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -480,4 +480,4 @@ void FL_BSTIM32_StructInit(FL_BSTIM32_InitTypeDef *initStruct);
#endif /* __FM33LC0XX_FL_BSTIM32_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_comp.h
+12 -12
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -64,7 +64,7 @@ typedef struct
uint32_t digitalFilter;
/** 数字滤波器长度 */
uint32_t digitalFilterLen; //此芯片不可设
uint32_t digitalFilterLen; /* 此芯片不可设 */
} FL_COMP_InitTypeDef;
@@ -569,4 +569,4 @@ FL_ErrorStatus FL_COMP_Init(COMP_Type *COMPx, FL_COMP_InitTypeDef *initStruct);
#endif /* __FM33LC0XX_FL_COMP_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_conf.h
+195
View File
@@ -0,0 +1,195 @@
/**
*******************************************************************************************************
* @file fm33lc0xx_fl_conf.h
* @author FMSH Application Team
* @brief Header file of FL Driver Library Configurations
*******************************************************************************************************
* @attention
*
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
/* Define to prevent recursive inclusion --------------------------------------------------------------*/
#ifndef __FM33LC0XX_FL_CONF_H
#define __FM33LC0XX_FL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Defines --------------------------------------------------------------------------------------------*/
/**
* @brief List of drivers to be used.
*
* @note Uncomment following lines to disable specified driver.
*/
#define FL_ADC_DRIVER_ENABLED
#define FL_AES_DRIVER_ENABLED
#define FL_ATIM_DRIVER_ENABLED
#define FL_BSTIM32_DRIVER_ENABLED
#define FL_COMP_DRIVER_ENABLED
#define FL_CRC_DRIVER_ENABLED
#define FL_DIVAS_DRIVER_ENABLED
#define FL_DMA_DRIVER_ENABLED
#define FL_EXTI_DRIVER_ENABLED
#define FL_FLASH_DRIVER_ENABLED
#define FL_GPIO_DRIVER_ENABLED
#define FL_GPTIM_DRIVER_ENABLED
#define FL_I2C_DRIVER_ENABLED
#define FL_IWDT_DRIVER_ENABLED
#define FL_LCD_DRIVER_ENABLED
#define FL_LPTIM32_DRIVER_ENABLED
#define FL_LPUART_DRIVER_ENABLED
#define FL_OPA_DRIVER_ENABLED
#define FL_PMU_DRIVER_ENABLED
#define FL_RCC_DRIVER_ENABLED
#define FL_RMU_DRIVER_ENABLED
#define FL_RNG_DRIVER_ENABLED
#define FL_RTC_DRIVER_ENABLED
#define FL_SPI_DRIVER_ENABLED
#define FL_SVD_DRIVER_ENABLED
#define FL_U7816_DRIVER_ENABLED
#define FL_UART_DRIVER_ENABLED
#define FL_VREF_DRIVER_ENABLED
#define FL_WWDT_DRIVER_ENABLED
/* Device Includes ------------------------------------------------------------------------------------*/
/**
* @brief Include peripheral's header file
*/
#if defined(FL_ADC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_adc.h"
#endif /* FL_ADC_DRIVER_ENABLED */
#if defined(FL_AES_DRIVER_ENABLED)
#include "fm33lc0xx_fl_aes.h"
#endif /* FL_AES_DRIVER_ENABLED */
#if defined(FL_ATIM_DRIVER_ENABLED)
#include "fm33lc0xx_fl_atim.h"
#endif /* FL_ATIM_DRIVER_ENABLED */
#if defined(FL_BSTIM32_DRIVER_ENABLED)
#include "fm33lc0xx_fl_bstim32.h"
#endif /* FL_BSTIM32_DRIVER_ENABLED */
#if defined(FL_COMP_DRIVER_ENABLED)
#include "fm33lc0xx_fl_comp.h"
#endif /* FL_COMP_DRIVER_ENABLED */
#if defined(FL_CRC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_crc.h"
#endif /* FL_CRC_DRIVER_ENABLED */
#if defined(FL_DIVAS_DRIVER_ENABLED)
#include "fm33lc0xx_fl_divas.h"
#endif /* FL_DIVAS_DRIVER_ENABLED */
#if defined(FL_DMA_DRIVER_ENABLED)
#include "fm33lc0xx_fl_dma.h"
#endif /* FL_DMA_DRIVER_ENABLED */
#if defined(FL_EXTI_DRIVER_ENABLED)
#include "fm33lc0xx_fl_exti.h"
#endif /* FL_EXTI_DRIVER_ENABLED */
#if defined(FL_FLASH_DRIVER_ENABLED)
#include "fm33lc0xx_fl_flash.h"
#endif /* FL_FLASH_DRIVER_ENABLED */
#if defined(FL_GPIO_DRIVER_ENABLED)
#include "fm33lc0xx_fl_gpio.h"
#endif /* FL_GPIO_DRIVER_ENABLED */
#if defined(FL_GPTIM_DRIVER_ENABLED)
#include "fm33lc0xx_fl_gptim.h"
#endif /* FL_GPTIM_DRIVER_ENABLED */
#if defined(FL_I2C_DRIVER_ENABLED)
#include "fm33lc0xx_fl_i2c.h"
#endif /* FL_I2C_DRIVER_ENABLED */
#if defined(FL_IWDT_DRIVER_ENABLED)
#include "fm33lc0xx_fl_iwdt.h"
#endif /* FL_IWDT_DRIVER_ENABLED */
#if defined(FL_LCD_DRIVER_ENABLED)
#include "fm33lc0xx_fl_lcd.h"
#endif /* FL_LCD_DRIVER_ENABLED */
#if defined(FL_LPTIM32_DRIVER_ENABLED)
#include "fm33lc0xx_fl_lptim32.h"
#endif /* FL_LPTIM32_DRIVER_ENABLED */
#if defined(FL_LPUART_DRIVER_ENABLED)
#include "fm33lc0xx_fl_lpuart.h"
#endif /* FL_LPUART_DRIVER_ENABLED */
#if defined(FL_OPA_DRIVER_ENABLED)
#include "fm33lc0xx_fl_opa.h"
#endif /* FL_OPA_DRIVER_ENABLED */
#if defined(FL_PMU_DRIVER_ENABLED)
#include "fm33lc0xx_fl_pmu.h"
#endif /* FL_PMU_DRIVER_ENABLED */
#if defined(FL_RCC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rcc.h"
#endif /* FL_RCC_DRIVER_ENABLED */
#if defined(FL_RMU_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rmu.h"
#endif /* FL_RMU_DRIVER_ENABLED */
#if defined(FL_RNG_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rng.h"
#endif /* FL_RNG_DRIVER_ENABLED */
#if defined(FL_RTC_DRIVER_ENABLED)
#include "fm33lc0xx_fl_rtc.h"
#endif /* FL_RTC_DRIVER_ENABLED */
#if defined(FL_SPI_DRIVER_ENABLED)
#include "fm33lc0xx_fl_spi.h"
#endif /* FL_SPI_DRIVER_ENABLED */
#if defined(FL_SVD_DRIVER_ENABLED)
#include "fm33lc0xx_fl_svd.h"
#endif /* FL_SVD_DRIVER_ENABLED */
#if defined(FL_U7816_DRIVER_ENABLED)
#include "fm33lc0xx_fl_u7816.h"
#endif /* FL_U7816_DRIVER_ENABLED */
#if defined(FL_UART_DRIVER_ENABLED)
#include "fm33lc0xx_fl_uart.h"
#endif /* FL_UART_DRIVER_ENABLED */
#if defined(FL_VREF_DRIVER_ENABLED)
#include "fm33lc0xx_fl_vref.h"
#endif /* FL_VREF_DRIVER_ENABLED */
#if defined(FL_WWDT_DRIVER_ENABLED)
#include "fm33lc0xx_fl_wwdt.h"
#endif /* FL_WWDT_DRIVER_ENABLED */
#ifdef __cplusplus
}
#endif
#endif /* __FM33LC0XX_FL_CONF_H */
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_crc.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -471,4 +471,4 @@ FL_ErrorStatus FL_CRC_Init(CRC_Type *CRCx, FL_CRC_InitTypeDef *CRC_InitStruct);
#endif /* __FM33LC0XX_FL_CRC_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_def.h
+92
View File
@@ -0,0 +1,92 @@
/**
*******************************************************************************************************
* @file fm33lc0xx_fl_def.h
* @author FMSH Application Team
* @brief Header file of FL Driver Library Defines
*******************************************************************************************************
* @attention
*
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
/* Define to prevent recursive inclusion --------------------------------------------------------------*/
#ifndef __FM33LC0XX_FL_DEF_H
#define __FM33LC0XX_FL_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx.h"
#include "fm33_assert.h"
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
/* Macros ---------------------------------------------------------------------------------------------*/
/** @defgroup FL_Exported_Macros FL Driver Library Private Macros
* @{
*/
/**
* @brief Bit-wise operation macros used by FL driver library functions
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @}
*/
/* Types ----------------------------------------------------------------------------------------------*/
/** @defgroup FL_PT_Return FL Driver Library Private Return Type Defines
* @{
*/
typedef enum
{
FL_RESET = 0U,
FL_SET = !FL_RESET
} FL_FlagStatus, FL_ITStatus;
typedef enum
{
FL_DISABLE = 0U,
FL_ENABLE = !FL_DISABLE
} FL_FunState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == FL_DISABLE) || ((STATE) == FL_ENABLE))
typedef enum
{
FL_FAIL = 0U,
FL_PASS = !FL_FAIL
} FL_ErrorStatus;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __FM33LC0XX_FL_DEF_H */
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_divas.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -203,4 +203,4 @@ uint32_t FL_DIVAS_Hdiv_Calculation(DIV_Type *DIVx, int32_t DivisorEnd, int16_t D
#endif /* __FM33LC0XX_FL_DIVAS_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_dma.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -50,7 +50,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -1284,4 +1284,4 @@ FL_ErrorStatus FL_DMA_StartTransmission(DMA_Type *DMAx, FL_DMA_ConfigTypeDef *co
#endif /* __FM33LC0XX_FL_DMA_H*/
/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2020-10-20*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_exti.h
+20 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,10 +28,16 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI FL driver
* @{
*/
/* Exported types -------------------------------------------------------------------------------------*/
/** @defgroup EXTI_FL_ES_INIT EXTI Exported Init structures
* @{
@@ -108,6 +114,9 @@ void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *init);
* @}
*/
/**
* @}
*/
/**
* @}
@@ -120,4 +129,4 @@ void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *init);
#endif /* __FM33LC0XX_FL_EXTI_H */
/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2021-03-16*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_flash.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -978,4 +978,4 @@ FL_ErrorStatus FL_FLASH_Program_Sector(FLASH_Type *FLASHx, uint32_t sectorNum, u
#endif /* __FM33LC0XX_FL_FLASH_H*/
/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2020-12-15*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gpio.h
+44 -37
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -289,37 +289,37 @@ typedef struct
#define FL_GPIO_FOUT0_SELECT_XTLF (0x0U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RCLP (0x1U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_LPOSC (0x1U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RCHF_DIV64 (0x2U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_LSCLK (0x3U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_AHBCLK_DIV64 (0x4U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RTCTM (0x5U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_PLLOUTPUT_DIV64 (0x6U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_APBCLK_DIV64 (0x8U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_APB1CLK_DIV64 (0x8U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_PLLOUTPUT (0x9U << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RC4M_PSC (0xaU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RCMF_PSC (0xaU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_RCHF (0xbU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_XTHF_DIV64 (0xcU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_ADCCLK_DIV64 (0xdU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_COMP1_OUTPUT (0xdU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_CLK_8K (0xeU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT0_SELECT_ADC_CLK (0xfU << GPIO_FOUTSEL_FOUT0_Pos)
#define FL_GPIO_FOUT1_SELECT_XTLF (0x0U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RCLP (0x1U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_LPOSC (0x1U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RCHF_DIV64 (0x2U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_LSCLK (0x3U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_AHBCLK_DIV64 (0x4U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RTCTM (0x5U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_PLLOUTPUT_DIV64 (0x6U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_APBCLK_DIV64 (0x8U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_APB1CLK_DIV64 (0x8U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_PLLOUTPUT (0x9U << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RC4M_PSC (0xaU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RCMF_PSC (0xaU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_RCHF (0xbU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_XTHF_DIV64 (0xcU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_COMP1_OUTPUT (0xdU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_ADCCLK_DIV64 (0xdU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_CLK_8K (0xeU << GPIO_FOUTSEL_FOUT1_Pos)
#define FL_GPIO_FOUT1_SELECT_COMP2_OUTPUT (0xfU << GPIO_FOUTSEL_FOUT1_Pos)
@@ -921,7 +921,14 @@ __STATIC_INLINE uint32_t FL_GPIO_GetOutputPin(GPIO_Type *GPIOx, uint32_t pin)
*/
__STATIC_INLINE void FL_GPIO_ToggleOutputPin(GPIO_Type *GPIOx, uint32_t pin)
{
WRITE_REG(GPIOx->DO, READ_REG(GPIOx->DO) ^ pin);
if(pin&GPIOx->DO)
{
WRITE_REG(GPIOx->DRST, pin);
}
else
{
WRITE_REG(GPIOx->DSET, pin);
}
}
/**
@@ -1274,19 +1281,19 @@ __STATIC_INLINE uint32_t FL_GPIO_ReadEXTILines(GPIO_COMMON_Type *GPIOx)
* @param GPIOx GPIO Port
* @param select This parameter can be one of the following values:
* @arg @ref FL_GPIO_FOUT0_SELECT_XTLF
* @arg @ref FL_GPIO_FOUT0_SELECT_RCLP
* @arg @ref FL_GPIO_FOUT0_SELECT_LPOSC
* @arg @ref FL_GPIO_FOUT0_SELECT_RCHF_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_LSCLK
* @arg @ref FL_GPIO_FOUT0_SELECT_AHBCLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_RTCTM
* @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_RTCCLK64Hz
* @arg @ref FL_GPIO_FOUT0_SELECT_APBCLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_APB1CLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT
* @arg @ref FL_GPIO_FOUT0_SELECT_RC4M_PSC
* @arg @ref FL_GPIO_FOUT0_SELECT_RCMF_PSC
* @arg @ref FL_GPIO_FOUT0_SELECT_RCHF
* @arg @ref FL_GPIO_FOUT0_SELECT_XTHF_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_ADCCLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_COMP1_OUTPUT
* @arg @ref FL_GPIO_FOUT0_SELECT_CLK_8K
* @arg @ref FL_GPIO_FOUT0_SELECT_ADC_CLK
* @retval None
@@ -1302,19 +1309,19 @@ __STATIC_INLINE void FL_GPIO_SetFOUT0(GPIO_COMMON_Type *GPIOx, uint32_t select)
* @param GPIOx GPIO Port
* @retval Returned value can be one of the following values:
* @arg @ref FL_GPIO_FOUT0_SELECT_XTLF
* @arg @ref FL_GPIO_FOUT0_SELECT_RCLP
* @arg @ref FL_GPIO_FOUT0_SELECT_LPOSC
* @arg @ref FL_GPIO_FOUT0_SELECT_RCHF_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_LSCLK
* @arg @ref FL_GPIO_FOUT0_SELECT_AHBCLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_RTCTM
* @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_RTCCLK64Hz
* @arg @ref FL_GPIO_FOUT0_SELECT_APBCLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_APB1CLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT
* @arg @ref FL_GPIO_FOUT0_SELECT_RC4M_PSC
* @arg @ref FL_GPIO_FOUT0_SELECT_RCMF_PSC
* @arg @ref FL_GPIO_FOUT0_SELECT_RCHF
* @arg @ref FL_GPIO_FOUT0_SELECT_XTHF_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_ADCCLK_DIV64
* @arg @ref FL_GPIO_FOUT0_SELECT_COMP1_OUTPUT
* @arg @ref FL_GPIO_FOUT0_SELECT_CLK_8K
* @arg @ref FL_GPIO_FOUT0_SELECT_ADC_CLK
*/
@@ -1329,19 +1336,19 @@ __STATIC_INLINE uint32_t FL_GPIO_GetFOUT0(GPIO_COMMON_Type *GPIOx)
* @param GPIOx GPIO Port
* @param select This parameter can be one of the following values:
* @arg @ref FL_GPIO_FOUT1_SELECT_XTLF
* @arg @ref FL_GPIO_FOUT1_SELECT_RCLP
* @arg @ref FL_GPIO_FOUT1_SELECT_LPOSC
* @arg @ref FL_GPIO_FOUT1_SELECT_RCHF_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_LSCLK
* @arg @ref FL_GPIO_FOUT1_SELECT_AHBCLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_RTCTM
* @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_RTCCLK64Hz
* @arg @ref FL_GPIO_FOUT1_SELECT_APBCLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_APB1CLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT
* @arg @ref FL_GPIO_FOUT1_SELECT_RC4M_PSC
* @arg @ref FL_GPIO_FOUT1_SELECT_RCMF_PSC
* @arg @ref FL_GPIO_FOUT1_SELECT_RCHF
* @arg @ref FL_GPIO_FOUT1_SELECT_XTHF_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_COMP1_OUTPUT
* @arg @ref FL_GPIO_FOUT1_SELECT_ADCCLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_CLK_8K
* @arg @ref FL_GPIO_FOUT1_SELECT_COMP2_OUTPUT
* @retval None
@@ -1357,19 +1364,19 @@ __STATIC_INLINE void FL_GPIO_SetFOUT1(GPIO_COMMON_Type *GPIOx, uint32_t select)
* @param GPIOx GPIO Port
* @retval Returned value can be one of the following values:
* @arg @ref FL_GPIO_FOUT1_SELECT_XTLF
* @arg @ref FL_GPIO_FOUT1_SELECT_RCLP
* @arg @ref FL_GPIO_FOUT1_SELECT_LPOSC
* @arg @ref FL_GPIO_FOUT1_SELECT_RCHF_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_LSCLK
* @arg @ref FL_GPIO_FOUT1_SELECT_AHBCLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_RTCTM
* @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_RTCCLK64Hz
* @arg @ref FL_GPIO_FOUT1_SELECT_APBCLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_APB1CLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT
* @arg @ref FL_GPIO_FOUT1_SELECT_RC4M_PSC
* @arg @ref FL_GPIO_FOUT1_SELECT_RCMF_PSC
* @arg @ref FL_GPIO_FOUT1_SELECT_RCHF
* @arg @ref FL_GPIO_FOUT1_SELECT_XTHF_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_COMP1_OUTPUT
* @arg @ref FL_GPIO_FOUT1_SELECT_ADCCLK_DIV64
* @arg @ref FL_GPIO_FOUT1_SELECT_CLK_8K
* @arg @ref FL_GPIO_FOUT1_SELECT_COMP2_OUTPUT
*/
@@ -1955,5 +1962,5 @@ void FL_GPIO_ALLPIN_LPM_MODE(void);
#endif /* __FM33LC0XX_FL_GPIO_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2021-08-19*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gptim.h
+13 -13
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -173,7 +173,7 @@ typedef struct
* ---------------------------------------------------
* ITR2 | 0 | BSTIM32_TRGO | 计数触发
* | 1 | LPUART2_RX | 宽度捕捉
* | 2 | RCLP | 周期捕捉
* | 2 | LPOSC | 周期捕捉
* | 3 | XTLF | 周期捕捉
* ---------------------------------------------------
* ITR3 | 0 | COMP1_TRGO | 计数触发
@@ -198,7 +198,7 @@ typedef struct
* ---------------------------------------------------
* ITR2 | 0 | BSTIM32_TRGO | 计数触发
* | 1 | LSCLK | 周期捕捉
* | 2 | RCLP | 周期捕捉
* | 2 | LPOSC | 周期捕捉
* | 3 | XTLF | 周期捕捉
* ---------------------------------------------------
* ITR3 | 0 | COMP1_TRGO | 计数触发
@@ -2955,4 +2955,4 @@ FL_ErrorStatus FL_GPTIM_ETR_Init(GPTIM_Type *TIMx, FL_GPTIM_ETR_InitTypeDef *etr
#endif /* __FM33LC0XX_FL_GPTIM_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_i2c.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -1862,4 +1862,4 @@ FL_ErrorStatus FL_I2C_MasterMode_Init(I2C_Type *I2Cx, FL_I2C_MasterMode_InitType
#endif /* __FM33LC0XX_FL_I2C_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_iwdt.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -306,4 +306,4 @@ FL_ErrorStatus FL_IWDT_Init(IWDT_Type *IWDTx, FL_IWDT_InitTypeDef *IWDT_InitStru
#endif /* __FM33LC0XX_FL_IWDT_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-27*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lcd.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -1012,4 +1012,4 @@ void FL_LCD_8COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t sta
#endif /* __FM33LC0XX_FL_LCD_H*/
/*************************Py_Code_Generator Version: 0.1-0.14-0.1 @ 2021-02-02*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lptim32.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -1170,4 +1170,4 @@ void FL_LPTIM32_OC_StructInit(FL_LPTIM32_OC_InitTypeDef *initStruct_OC);
#endif /* __FM33LC0XX_FL_LPTIM32_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lpuart.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -1089,4 +1089,4 @@ FL_ErrorStatus FL_LPUART_Init(LPUART_Type *LPUARTx, FL_LPUART_InitTypeDef *initS
#endif /* __FM33LC0XX_FL_LPUART_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_opa.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -782,4 +782,4 @@ FL_ErrorStatus FL_OPA_Init(OPA_Type *OPAx, FL_OPA_InitTypeDef *initStruct);
#endif /* __FM33LC0XX_FL_OPA_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_pmu.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -953,4 +953,4 @@ void FL_PMU_StructInit(FL_PMU_SleepInitTypeDef *LPM_InitStruct);
#endif /* __FM33LC0XX_FL_PMU_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rcc.h
+325 -53
View File
File diff suppressed because it is too large Load Diff
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rmu.h
+12 -12
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -59,7 +59,7 @@ extern "C" {
#define RMU_PDRCR_EN_Msk (0x1U << RMU_PDRCR_EN_Pos)
#define RMU_PDRCR_EN RMU_PDRCR_EN_Msk
#define RMU_BORCR_CFG_Pos (1U)
#define RMU_BORCR_CFG_Pos (2U)
#define RMU_BORCR_CFG_Msk (0x3U << RMU_BORCR_CFG_Pos)
#define RMU_BORCR_CFG RMU_BORCR_CFG_Msk
@@ -284,4 +284,4 @@ __STATIC_INLINE void FL_RMU_BORPowerUp_Enable(RMU_Type *RMUx)
#endif /* __FM33LC0XX_FL_RMU_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rng.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -261,4 +261,4 @@ uint32_t GetCrc32(uint32_t dataIn);
#endif /* __FM33LC0XX_FL_RNG_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rtc.h
+11 -11
View File
@@ -6,15 +6,15 @@
*******************************************************************************************************
* @attention
*
* Copyright (c) [2019] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under the Mulan PSL v1.
* can use this software according to the terms and conditions of the Mulan PSL v1.
* You may obtain a copy of Mulan PSL v1 at:
* http://license.coscl.org.cn/MulanPSL
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
* PURPOSE.
* See the Mulan PSL v1 for more details.
* Copyright (c) [2021] [Fudan Microelectronics]
* THIS SOFTWARE is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*
*******************************************************************************************************
*/
@@ -28,7 +28,7 @@
extern "C" {
#endif
/* Includes -------------------------------------------------------------------------------------------*/
#include "fm33lc0xx_fl.h"
#include "fm33lc0xx_fl_def.h"
/** @addtogroup FM33LC0XX_FL_Driver
* @{
*/
@@ -1386,4 +1386,4 @@ FL_ErrorStatus FL_RTC_ConfigTime(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct)
#endif /* __FM33LC0XX_FL_RTC_H*/
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/

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