mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-02 14:23:19 +08:00
[hc32] Add some bsp drivers. (#8480)
This commit is contained in:
Jamie
+1
-1
@@ -17,7 +17,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
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| **BSP 使用教程** | **简介** |
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|:-------------------- |:------------------------------------------------- |
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| [外设驱动使用教程](docs/HC32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
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| [外设驱动介绍与应用](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
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| [外设驱动介绍](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
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| **BSP 制作与提交** | **简介** |
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| [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 |
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@@ -1 +1,11 @@
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# HC32系列BSP外设驱动使用教程
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## 简介
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本文档是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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主要包括以下内容：
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1. 如何使用开发板上更多的板载资源
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2. 如何使用更多的片上资源
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3. 如何添加更多片上资源选项
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@@ -0,0 +1,2 @@
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# HC32系列驱动介绍
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@@ -1,2 +1,64 @@
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# HC32系列驱动介绍
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在 RT-Thread 实时操作系统中，各种各样的设备驱动是通过一套 I/O 设备管理框架来管理的。设备管理框架给上层应用提供了一套标准的设备操作 API，开发者通过调用这些标准设备操作 API，可以高效地完成和底层硬件外设的交互。设备管理框架的结构如下图所示：
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使用 I/O 设备管理框架开发应用程序，有如下优点：
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- 使用同一套标准的 API 开发应用程序，使应用程序具有更好的移植性
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- 底层驱动的升级和修改不会影响到上层代码
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- 驱动和应用程序相互独立，方便多个开发者协同开发
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## 1. 驱动分类介绍
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本小节介绍 BSP 提供的不同类别驱动的概念，对一个 BSP 而言，有如下三类驱动：
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- **片上外设驱动**：指 MCU 芯片上的外设，例如硬件定时器、ADC等
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- **板载外设驱动**：指 MCU 之外，开发板上外设，例如 TF 卡、以太网等
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- **扩展模块驱动**：指可以通过扩展接口或者杜邦线连接的开发板的模块
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这三种外设的示意图如下所示：
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## 2. 外设驱动的使用方法
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当前 RT-Thread 提供的驱动库已经支持 HC32 多个系列的 BSP。点击下表中的驱动名称，即可跳转到对应驱动框架的介绍文档。开发者可以通过阅读相关资料，了解如何在应用开发中通过设备驱动框架来使用这些外设驱动。
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### 2.1 片上外设
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| 序号 | 驱动 | 简介 |
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| ---- | ------------------------------------------------------------ | ------------------------------ |
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| 1 | [GPIO](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pin/pin) | 操作 GPIO 管脚 |
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| 2 | [UART](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/uart/uart_v1/uart) | 通过串口收发数据 |
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| 3 | [UART V2](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/uart/uart_v2/uart) | 通过串口收发数据 |
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| 4 | [SOFT I2C](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/i2c/i2c) | 通过软件 I2C 收发数据 |
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| 5 | [I2C](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/i2c/i2c) | 通过硬件 I2C 收发数据 |
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| 6 | [SPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi) | 通过 SPI 收发数据 |
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| 7 | [QSPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi?id=配置-qspi-设备) | 通过 SPI（1、2、4线） 收发数据 |
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| 8 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量 |
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| 9 | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量 |
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| 10 | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据 |
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| 11 | [HWTIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | 通过硬件定时器计时 |
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| 12 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形 |
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| 13 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间 |
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| 14 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动 |
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| 15 | [CRYPTO](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/crypto/crypto) | 对数据进行加解密操作 |
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| 16 | [PULSE ENCODER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pulse_encoder/pulse_encoder) | 脉冲编码器驱动 |
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### 2.2 板载外设
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| 序号 | 驱动 | 简介 |
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| ---- | ------- | --------------------------------------- |
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| 1 | SD | 适用于 SDIO 接口的 SD(TF) 卡 |
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| 2 | ETH | 以太网 |
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| 3 | USB | USB |
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| 4 | NAND | NAND |
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| 4 | SDRAM | SDRAM |
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### 2.3 扩展模块
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### 2.4 驱动示例代码
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在 RT-Thread 的 `examples\test` 目录下，有 RT-Thread 提供的基于不同外设驱动的示例代码。在 env 工具中开启 BSP 中要测试的驱动，并将 `examples\test` 中对应的驱动框架测试文件加入工程，即可快速测试 BSP 中提供的驱动。
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@@ -0,0 +1,68 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>project</name>
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<comment />
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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<triggers>clean,full,incremental,</triggers>
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||||
<arguments>
|
||||
</arguments>
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||||
</buildCommand>
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||||
<buildCommand>
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||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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||||
<triggers>full,incremental,</triggers>
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||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
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||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
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||||
<name>rt-thread</name>
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||||
<type>2</type>
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||||
<locationURI>virtual:/virtual</locationURI>
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</link>
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||||
<link>
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||||
<name>rt-thread/bsp</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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||||
<link>
|
||||
<name>rt-thread/components</name>
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||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
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||||
</link>
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||||
<link>
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||||
<name>rt-thread/include</name>
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||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
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</link>
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||||
<link>
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||||
<name>rt-thread/libcpu</name>
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<type>2</type>
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||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
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||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
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||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/libraries</name>
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<type>2</type>
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<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
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</link>
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</linkedResources>
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</projectDescription>
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@@ -39,12 +39,13 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下：
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| :------------ | :-----------: | :-----------------------------------: |
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| USB 转串口 | 支持 | 使用 UART4 |
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| LED | 支持 | LED |
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| **片上外设** | **支持情况** | **备注** |
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| **片上外设** | **支持情况** | **备注** |
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| :------------ | :-----------: | :-----------------------------------: |
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| ADC | 支持 | ADC1: CH10, CH11, CH12,<br>ADC2: CH7 |
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| CAN | 支持 | CAN1 |
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| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
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| I2C | 支持 | 软件 |
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| ADC | 支持 | ADC1~2 |
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| CAN | 支持 | CAN1 |
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| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
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| I2C | 支持 | 软件 |
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| UART | 支持 | UART1~4 |
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@@ -107,4 +108,4 @@ msh >
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维护人:
|
||||
|
||||
- [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
|
||||
@@ -56,5 +56,7 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
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objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
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|
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# make a building
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DoBuilding(TARGET, objs)
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|
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@@ -1,6 +1,5 @@
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||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -13,7 +12,6 @@
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#include <rtdevice.h>
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||||
#include <board.h>
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|
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|
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/* defined the LED_GREEN pin: PD4 */
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#define LED_GREEN_PIN GET_PIN(D, 4)
|
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|
||||
|
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@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-27 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -12,9 +12,13 @@ board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/drv_spi_flash.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
path += [cwd + '/config/usb_config']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
@@ -25,7 +29,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s']
|
||||
|
||||
CPPDEFINES = ['HC32F460']
|
||||
CPPDEFINES = ['HC32F460', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -20,12 +19,18 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_SIZE (512 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (188)
|
||||
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
@@ -36,6 +41,11 @@ extern int __bss_end;
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,13 +1,11 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (c) 2022, xiaoxiaolisunny
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-06-07 xiaoxiaolisunny first version
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
@@ -25,6 +23,7 @@ extern "C" {
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
@@ -47,6 +46,7 @@ extern "C" {
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
|
||||
@@ -1,13 +1,11 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (c) 2022, xiaoxiaolisunny
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-06-07 xiaoxiaolisunny first version
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
@@ -21,10 +19,16 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "can1", \
|
||||
.name = CAN1_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
@@ -34,80 +38,80 @@ extern "C" {
|
||||
|
||||
Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
|
||||
TQ = u32Prescaler / CANClock.
|
||||
Bit time = (u32TimeSeg1 + u32TimeSeg2) x TQ.
|
||||
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
|
||||
The following bit time configures are based on CAN Clock 8M
|
||||
The following bit time configures are based on CAN Clock 40M
|
||||
*/
|
||||
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 1, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 1, \
|
||||
.u32TimeSeg1 = 6, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 20, \
|
||||
.u32TimeSeg2 = 5, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 16, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 10, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 50, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 5, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
.u32Prescaler = 200, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -115,5 +119,3 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
||||
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_CONFIG_H__
|
||||
#define __I2C_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#ifndef I2C1_CONFIG
|
||||
#define I2C1_CONFIG \
|
||||
{ \
|
||||
.name = "i2c1", \
|
||||
.Instance = CM_I2C1, \
|
||||
.clock = FCG1_PERIPH_I2C1, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C1_CONFIG */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_I2C1_USING_DMA)
|
||||
#ifndef I2C1_TX_DMA_CONFIG
|
||||
#define I2C1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_TX_DMA_INSTANCE, \
|
||||
.channel = I2C1_TX_DMA_CHANNEL, \
|
||||
.clock = I2C1_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C1_TEI, \
|
||||
.flag = I2C1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C1_RX_DMA_CONFIG
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
||||
.channel = I2C1_RX_DMA_CHANNEL, \
|
||||
.clock = I2C1_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C1_RXI, \
|
||||
.flag = I2C1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C1_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_I2C2)
|
||||
#ifndef I2C2_CONFIG
|
||||
#define I2C2_CONFIG \
|
||||
{ \
|
||||
.name = "i2c2", \
|
||||
.Instance = CM_I2C2, \
|
||||
.clock = FCG1_PERIPH_I2C2, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C2_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C2_USING_DMA)
|
||||
#ifndef I2C2_TX_DMA_CONFIG
|
||||
#define I2C2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2_TX_DMA_INSTANCE, \
|
||||
.channel = I2C2_TX_DMA_CHANNEL, \
|
||||
.clock = I2C2_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C2_TEI, \
|
||||
.flag = I2C2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C2_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C2_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C2_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C2_RX_DMA_CONFIG
|
||||
#define I2C2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2_RX_DMA_INSTANCE, \
|
||||
.channel = I2C2_RX_DMA_CHANNEL, \
|
||||
.clock = I2C2_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C2_RXI, \
|
||||
.flag = I2C2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C2_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C2_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C2_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C3)
|
||||
#ifndef I2C3_CONFIG
|
||||
#define I2C3_CONFIG \
|
||||
{ \
|
||||
.name = "i2c3", \
|
||||
.Instance = CM_I2C3, \
|
||||
.clock = FCG1_PERIPH_I2C3, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C3_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C3_USING_DMA)
|
||||
#ifndef I2C3_TX_DMA_CONFIG
|
||||
#define I2C3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3_TX_DMA_INSTANCE, \
|
||||
.channel = I2C3_TX_DMA_CHANNEL, \
|
||||
.clock = I2C3_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C3_TEI, \
|
||||
.flag = I2C3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C3_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C3_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C3_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C3_RX_DMA_CONFIG
|
||||
#define I2C3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3_RX_DMA_INSTANCE, \
|
||||
.channel = I2C3_RX_DMA_CHANNEL, \
|
||||
.clock = I2C3_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C3_RXI, \
|
||||
.flag = I2C3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C3_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C3_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C3_USING_DMA */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-05-12 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PM_CONFIG_H__
|
||||
#define __PM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PM
|
||||
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
|
||||
|
||||
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
|
||||
#define PM_TICKLESS_TIMER_ENABLE_MASK \
|
||||
( (1UL << PM_SLEEP_MODE_IDLE) | \
|
||||
(1UL << PM_SLEEP_MODE_DEEP))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief run mode config @ref pm_run_mode_config structure
|
||||
*/
|
||||
#ifndef PM_RUN_MODE_CFG
|
||||
#define PM_RUN_MODE_CFG \
|
||||
{ \
|
||||
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
|
||||
}
|
||||
#endif /* PM_RUN_MODE_CFG */
|
||||
|
||||
/**
|
||||
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_IDLE_CFG
|
||||
#define PM_SLEEP_IDLE_CFG \
|
||||
{ \
|
||||
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_IDLE_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_DEEP_CFG
|
||||
#define PM_SLEEP_DEEP_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u16Clock = PWC_STOP_CLK_KEEP, \
|
||||
.u8StopDrv = PWC_STOP_DRV_HIGH, \
|
||||
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
|
||||
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
|
||||
}, \
|
||||
.pwc_stop_type = PWC_STOP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_DEEP_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_STANDBY_CFG
|
||||
#define PM_SLEEP_STANDBY_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD1, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_STANDBY_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_SHUTDOWN_CFG
|
||||
#define PM_SLEEP_SHUTDOWN_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD3, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
|
||||
|
||||
#endif /* BSP_USING_PM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PM_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-06-15 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_QSPI, \
|
||||
.clock = FCG1_PERIPH_QSPI, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_QSPI_INTR, \
|
||||
}, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
|
||||
#ifndef QSPI_INIT_PARAMS
|
||||
#define QSPI_INIT_PARAMS \
|
||||
{ \
|
||||
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
|
||||
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
|
||||
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
|
||||
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
|
||||
}
|
||||
#endif /* QSPI_INIT_PARAMS */
|
||||
|
||||
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = QSPI_DMA_INSTANCE, \
|
||||
.channel = QSPI_DMA_CHANNEL, \
|
||||
.clock = QSPI_DMA_CLOCK, \
|
||||
.trigger_select = QSPI_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_AOS_STRG, \
|
||||
.flag = QSPI_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = QSPI_DMA_IRQn, \
|
||||
.irq_prio = QSPI_DMA_INT_PRIO, \
|
||||
.int_src = QSPI_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__QSPI_CONFIG_H__ */
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_SDIO1)
|
||||
#ifndef SDIO1_BUS_CONFIG
|
||||
#define SDIO1_BUS_CONFIG \
|
||||
{ \
|
||||
.name = "sdio1", \
|
||||
.instance = CM_SDIOC1, \
|
||||
.clock = FCG1_PERIPH_SDIOC1, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SDIO1_IRQ_NUM, \
|
||||
.irq_prio = BSP_SDIO1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SDIOC1_SD, \
|
||||
}, \
|
||||
.dma_rx = \
|
||||
{ \
|
||||
.Instance = SDIO1_RX_DMA_INSTANCE, \
|
||||
.channel = SDIO1_RX_DMA_CHANNEL, \
|
||||
.clock = SDIO1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC1_DMAR, \
|
||||
}, \
|
||||
.dma_tx = \
|
||||
{ \
|
||||
.Instance = SDIO1_TX_DMA_INSTANCE, \
|
||||
.channel = SDIO1_TX_DMA_CHANNEL, \
|
||||
.clock = SDIO1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC1_DMAW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SDIO1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SDIO1 */
|
||||
|
||||
#if defined(BSP_USING_SDIO2)
|
||||
#ifndef SDIO2_BUS_CONFIG
|
||||
#define SDIO2_BUS_CONFIG \
|
||||
{ \
|
||||
.name = "sdio2", \
|
||||
.instance = CM_SDIOC2, \
|
||||
.clock = FCG1_PERIPH_SDIOC2, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SDIO2_IRQ_NUM, \
|
||||
.irq_prio = BSP_SDIO2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SDIOC2_SD, \
|
||||
}, \
|
||||
.dma_rx = \
|
||||
{ \
|
||||
.Instance = SDIO2_RX_DMA_INSTANCE, \
|
||||
.channel = SDIO2_RX_DMA_CHANNEL, \
|
||||
.clock = SDIO2_RX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC2_DMAR, \
|
||||
}, \
|
||||
.dma_tx = \
|
||||
{ \
|
||||
.Instance = SDIO2_TX_DMA_INSTANCE, \
|
||||
.channel = SDIO2_TX_DMA_CHANNEL, \
|
||||
.clock = SDIO2_TX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC2_DMAW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SDIO2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SDIO2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-06-21 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TMR_CONFIG_H__
|
||||
#define __TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TMRA_1
|
||||
#ifndef TMRA_1_CONFIG
|
||||
#define TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_1, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_1, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_1" \
|
||||
}
|
||||
#endif /* TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_2
|
||||
#ifndef TMRA_2_CONFIG
|
||||
#define TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_2, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_2, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_2" \
|
||||
}
|
||||
#endif /* TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_3
|
||||
#ifndef TMRA_3_CONFIG
|
||||
#define TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_3, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_3, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_3" \
|
||||
}
|
||||
#endif /* TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_4
|
||||
#ifndef TMRA_4_CONFIG
|
||||
#define TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_4, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_4, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_4" \
|
||||
}
|
||||
#endif /* TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_5
|
||||
#ifndef TMRA_5_CONFIG
|
||||
#define TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_5, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_5, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_5" \
|
||||
}
|
||||
#endif /* TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_5 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_6
|
||||
#ifndef TMRA_6_CONFIG
|
||||
#define TMRA_6_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_6, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_6, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_6_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_6" \
|
||||
}
|
||||
#endif /* TMRA_6_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_6 */
|
||||
|
||||
#endif /* __TMR_CONFIG_H__ */
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -57,6 +56,7 @@ extern "C" {
|
||||
.clock = UART1_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART1_RI, \
|
||||
.flag = UART1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART1_RX_DMA_IRQn, \
|
||||
@@ -83,7 +83,7 @@ extern "C" {
|
||||
#endif /* UART1_RXTO_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_TX_CPLT_CONFIG
|
||||
#define UART1_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
@@ -94,8 +94,22 @@ extern "C" {
|
||||
.int_src = INT_SRC_USART1_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART1_TX_CPLT_CONFIG
|
||||
#define UART1_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART1_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART1_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
@@ -104,6 +118,7 @@ extern "C" {
|
||||
.clock = UART1_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART1_TI, \
|
||||
.flag = UART1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART1_TX_DMA_IRQn, \
|
||||
@@ -152,6 +167,7 @@ extern "C" {
|
||||
.clock = UART2_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART2_RI, \
|
||||
.flag = UART2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART2_RX_DMA_IRQn, \
|
||||
@@ -178,7 +194,7 @@ extern "C" {
|
||||
#endif /* UART2_RXTO_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_TX_CPLT_CONFIG
|
||||
#define UART2_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
@@ -189,8 +205,22 @@ extern "C" {
|
||||
.int_src = INT_SRC_USART2_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART2_TX_CPLT_CONFIG
|
||||
#define UART2_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART2_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART2_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
@@ -199,6 +229,7 @@ extern "C" {
|
||||
.clock = UART2_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART2_TI, \
|
||||
.flag = UART2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART2_TX_DMA_IRQn, \
|
||||
@@ -247,6 +278,7 @@ extern "C" {
|
||||
.clock = UART3_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART3_RI, \
|
||||
.flag = UART3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART3_RX_DMA_IRQn, \
|
||||
@@ -273,7 +305,7 @@ extern "C" {
|
||||
#endif /* UART3_RXTO_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_TX_CPLT_CONFIG
|
||||
#define UART3_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
@@ -284,8 +316,22 @@ extern "C" {
|
||||
.int_src = INT_SRC_USART3_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART3_TX_CPLT_CONFIG
|
||||
#define UART3_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART3_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART3_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_DMA_TX_CONFIG
|
||||
#define UART3_DMA_TX_CONFIG \
|
||||
{ \
|
||||
@@ -294,6 +340,7 @@ extern "C" {
|
||||
.clock = UART3_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART3_TI, \
|
||||
.flag = UART3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART3_TX_DMA_IRQn, \
|
||||
@@ -342,6 +389,7 @@ extern "C" {
|
||||
.clock = UART4_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART4_RI, \
|
||||
.flag = UART4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART4_RX_DMA_IRQn, \
|
||||
@@ -368,7 +416,7 @@ extern "C" {
|
||||
#endif /* UART4_RXTO_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_TX_CPLT_CONFIG
|
||||
#define UART4_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
@@ -379,8 +427,22 @@ extern "C" {
|
||||
.int_src = INT_SRC_USART4_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART4_TX_CPLT_CONFIG
|
||||
#define UART4_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART4_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART4_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_DMA_TX_CONFIG
|
||||
#define UART4_DMA_TX_CONFIG \
|
||||
{ \
|
||||
@@ -389,6 +451,7 @@ extern "C" {
|
||||
.clock = UART4_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART4_TI, \
|
||||
.flag = UART1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART4_TX_DMA_IRQn, \
|
||||
|
||||
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __USB_APP_CONF_H__
|
||||
#define __USB_APP_CONF_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "rtconfig.h"
|
||||
|
||||
/* USB MODE CONFIGURATION */
|
||||
|
||||
|
||||
#if defined(BSP_USING_USBFS)
|
||||
#define USB_FS_MODE
|
||||
#else
|
||||
#define USB_FS_MODE
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD)
|
||||
#define USE_DEVICE_MODE
|
||||
#elif defined(BSP_USING_USBH)
|
||||
#define USE_HOST_MODE
|
||||
#else
|
||||
#define USE_DEVICE_MODE
|
||||
#endif
|
||||
|
||||
#ifndef USB_FS_MODE
|
||||
#error "USB_FS_MODE should be defined"
|
||||
#endif
|
||||
|
||||
#ifndef USE_DEVICE_MODE
|
||||
#ifndef USE_HOST_MODE
|
||||
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD)
|
||||
/* USB DEVICE FIFO CONFIGURATION */
|
||||
#ifdef USB_FS_MODE
|
||||
#define RX_FIFO_FS_SIZE (128U)
|
||||
#define TX0_FIFO_FS_SIZE (32U)
|
||||
#define TX1_FIFO_FS_SIZE (32U)
|
||||
#define TX2_FIFO_FS_SIZE (32U)
|
||||
#define TX3_FIFO_FS_SIZE (32U)
|
||||
#define TX4_FIFO_FS_SIZE (32U)
|
||||
#define TX5_FIFO_FS_SIZE (32U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + \
|
||||
TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
|
||||
TX5_FIFO_FS_SIZE) > 320U)
|
||||
#error "The USB max FIFO size is 320 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD_VBUS_SENSING)
|
||||
#define VBUS_SENSING_ENABLED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBH)
|
||||
/* USB HOST FIFO CONFIGURATION */
|
||||
#ifdef USB_FS_MODE
|
||||
#define RX_FIFO_FS_SIZE (128U)
|
||||
#define TXH_NP_FS_FIFOSIZ (64U)
|
||||
#define TXH_P_FS_FIFOSIZ (128U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 320U)
|
||||
#error "The USB max FIFO size is 320 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_APP_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __USB_BSP_H__
|
||||
#define __USB_BSP_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "hc32_ll_utility.h"
|
||||
|
||||
extern void usb_udelay(const uint32_t usec);
|
||||
extern void usb_mdelay(const uint32_t msec);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_BSP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -19,20 +18,18 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Suppress warning messages */
|
||||
#if defined(__CC_ARM)
|
||||
// Suppress warning message: extended constant initialiser used
|
||||
#pragma diag_suppress 1296
|
||||
#elif defined(__ICCARM__)
|
||||
#elif defined(__GNUC__)
|
||||
#endif
|
||||
|
||||
#include "dma_config.h"
|
||||
#include "uart_config.h"
|
||||
#include "spi_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "can_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "pwm_tmra_config.h"
|
||||
#include "sdio_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "qspi_config.h"
|
||||
#include "pulse_encoder_config.h"
|
||||
#include "timer_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -5,10 +5,10 @@
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-04-28 CDT First version
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
@@ -23,6 +23,7 @@
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
@@ -58,64 +59,44 @@ extern "C"
|
||||
#define LL_CLK_ENABLE (DDL_ON)
|
||||
#define LL_CMP_ENABLE (DDL_ON)
|
||||
#define LL_CRC_ENABLE (DDL_ON)
|
||||
#define LL_CTC_ENABLE (DDL_ON)
|
||||
#define LL_DAC_ENABLE (DDL_ON)
|
||||
#define LL_DBGC_ENABLE (DDL_OFF)
|
||||
#define LL_DCU_ENABLE (DDL_ON)
|
||||
#define LL_DMA_ENABLE (DDL_ON)
|
||||
#define LL_DMC_ENABLE (DDL_ON)
|
||||
#define LL_DVP_ENABLE (DDL_ON)
|
||||
#define LL_EFM_ENABLE (DDL_ON)
|
||||
#define LL_EMB_ENABLE (DDL_ON)
|
||||
#define LL_ETH_ENABLE (DDL_ON)
|
||||
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define LL_FCG_ENABLE (DDL_ON)
|
||||
#define LL_FCM_ENABLE (DDL_ON)
|
||||
#define LL_FMAC_ENABLE (DDL_ON)
|
||||
#define LL_GPIO_ENABLE (DDL_ON)
|
||||
#define LL_HASH_ENABLE (DDL_ON)
|
||||
#define LL_HRPWM_ENABLE (DDL_ON)
|
||||
#define LL_I2C_ENABLE (DDL_ON)
|
||||
#define LL_I2S_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON)
|
||||
#define LL_KEYSCAN_ENABLE (DDL_ON)
|
||||
#define LL_MAU_ENABLE (DDL_ON)
|
||||
#define LL_MDIO_ENABLE (DDL_OFF)
|
||||
#define LL_MPU_ENABLE (DDL_ON)
|
||||
#define LL_NFC_ENABLE (DDL_ON)
|
||||
#define LL_OTS_ENABLE (DDL_ON)
|
||||
#define LL_PLA_ENABLE (DDL_OFF)
|
||||
#define LL_PWC_ENABLE (DDL_ON)
|
||||
#define LL_QSPI_ENABLE (DDL_ON)
|
||||
#define LL_RMU_ENABLE (DDL_ON)
|
||||
#define LL_RTC_ENABLE (DDL_ON)
|
||||
#define LL_SDIOC_ENABLE (DDL_ON)
|
||||
#define LL_SMC_ENABLE (DDL_ON)
|
||||
#define LL_SPI_ENABLE (DDL_ON)
|
||||
#define LL_SRAM_ENABLE (DDL_ON)
|
||||
#define LL_SWDT_ENABLE (DDL_ON)
|
||||
#define LL_TMR0_ENABLE (DDL_ON)
|
||||
#define LL_TMR2_ENABLE (DDL_ON)
|
||||
#define LL_TMR4_ENABLE (DDL_ON)
|
||||
#define LL_TMR6_ENABLE (DDL_ON)
|
||||
#define LL_TMRA_ENABLE (DDL_ON)
|
||||
#define LL_TRNG_ENABLE (DDL_ON)
|
||||
#define LL_USART_ENABLE (DDL_ON)
|
||||
#define LL_USB_ENABLE (DDL_OFF)
|
||||
#define LL_VREF_ENABLE (DDL_OFF)
|
||||
#define LL_USB_ENABLE (DDL_ON)
|
||||
#define LL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F4A0_LQFP176 (1U)
|
||||
#define BSP_EV_HC32F4A0_LQFP176_MEM (2U)
|
||||
#define BSP_EV_HC32F460_LQFP100_V1 (3U)
|
||||
#define BSP_EV_HC32F460_LQFP100_V2 (4U)
|
||||
#define BSP_EV_HC32F451_LQFP100 (5U)
|
||||
#define BSP_EV_HC32F452_LQFP100 (6U)
|
||||
#define BSP_EV_HC32F472_LQFP100 (7U)
|
||||
#define BSP_SK_HC32F4A0_LQFP100 (8U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
|
||||
@@ -131,23 +112,9 @@ extern "C"
|
||||
* Select the components you need to use to DDL_ON.
|
||||
*/
|
||||
#define BSP_24CXX_ENABLE (DDL_OFF)
|
||||
#define BSP_CY62167EV30LL_ENABLE (DDL_OFF)
|
||||
#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF)
|
||||
#define BSP_IS62WV51216_ENABLE (DDL_OFF)
|
||||
#define BSP_MT29F2G08AB_ENABLE (DDL_OFF)
|
||||
#define BSP_NT35510_ENABLE (DDL_OFF)
|
||||
#define BSP_OV5640_ENABLE (DDL_OFF)
|
||||
#define BSP_S29GL064N90TFI03_ENABLE (DDL_OFF)
|
||||
#define BSP_TCA9539_ENABLE (DDL_OFF)
|
||||
#define BSP_W25QXX_ENABLE (DDL_OFF)
|
||||
#define BSP_WM8731_ENABLE (DDL_OFF)
|
||||
|
||||
/**
|
||||
* @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0).
|
||||
* @note Set value to non-zero if re-define main function.
|
||||
*/
|
||||
#define RE_DEFINE_MAIN (0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
@@ -1,21 +1,68 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/***************************************************************************//**
|
||||
* \file HC32F460.icf
|
||||
* \version 1.0
|
||||
*
|
||||
* \brief Linker file for the IAR compiler.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*******************************************************************************/
|
||||
/*###ICF### Section handled by ICF editor, don't touch! *****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
// Check that necessary symbols have been passed to linker via command line interface
|
||||
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
|
||||
error "Link location not defined or not supported!";
|
||||
}
|
||||
if((!isdefinedsymbol(_HC32F460_512K_)) && (!isdefinedsymbol(_HC32F460_256K_))) {
|
||||
error "Mcu type or size not defined or not supported!";
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory address and size definitions
|
||||
******************************************************************************/
|
||||
define symbol ram1_base_address = 0x1FFF8000;
|
||||
define symbol ram1_end_address = 0x20026FFF;
|
||||
|
||||
if(isdefinedsymbol(_LINK_RAM_)) {
|
||||
define symbol ram_start_reserve = 0x8000;
|
||||
define symbol rom1_base_address = ram1_base_address;
|
||||
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else {
|
||||
define symbol ram_start_reserve = 0x0;
|
||||
define symbol rom1_base_address = 0x0;
|
||||
define symbol rom2_base_address = 0x03000C00;
|
||||
define symbol rom2_end_address = 0x03000FBF;
|
||||
if (isdefinedsymbol(_HC32F460_512K_)) {
|
||||
define symbol rom1_end_address = 0x0007FFFF;
|
||||
} else if (isdefinedsymbol(_HC32F460_256K_)) {
|
||||
define symbol rom1_end_address = 0x0003FFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
@@ -25,16 +72,18 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC00;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory definitions
|
||||
******************************************************************************/
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
|
||||
define region OTP_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
@@ -47,5 +96,6 @@ do not initialize { section .noinit };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in OTP_region { readonly section .otp_data };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
@@ -11,8 +11,8 @@
|
||||
/* File HC32F460xE.ld */
|
||||
/* Abstract Linker script for HC32F460 Device with */
|
||||
/* 512KByte FLASH, 192KByte RAM */
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-04-28 */
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-03-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
@@ -163,42 +163,6 @@ SECTIONS
|
||||
__data_end__ = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ret_ram_data : AT (__etext_ret_ram)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ret_ram__ = .;
|
||||
*(.ret_ram_data)
|
||||
*(.ret_ram_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
__bss_end = .;
|
||||
|
||||
.ret_ram_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ret_ram__ = .;
|
||||
*(.ret_ram_bss)
|
||||
*(.ret_ram_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
.heap_stack (COPY) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
@@ -215,6 +179,45 @@ SECTIONS
|
||||
__StackTop = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ramb_data : AT (__etext_ret_ram)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ret_ram__ = .;
|
||||
*(.ramb_data)
|
||||
*(.ramb_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
__bss_start = .;
|
||||
.bss __StackTop (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
. = ALIGN(4);
|
||||
*(.noinit*)
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
__bss_end = .;
|
||||
|
||||
.ramb_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ret_ram__ = .;
|
||||
*(.ramb_bss)
|
||||
*(.ramb_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a (*)
|
||||
|
||||
@@ -8,7 +8,14 @@ LR_IROM1 0x00000000 0x00080000 { ; load region size_region
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFF8000 0x0002F000 { ; RW data
|
||||
RW_IRAM1 0x1FFF8000 UNINIT 0x00000008 { ; RW data
|
||||
*(.bss.noinit)
|
||||
}
|
||||
RW_IRAM2 0x1FFF8008 0x0002EFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (RAMCODE)
|
||||
}
|
||||
RW_IRAMB 0x200F0000 0x00001000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <drv_spi.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
#include <finsh.h>
|
||||
#include <dfs_fs.h>
|
||||
#include <fal.h>
|
||||
|
||||
#ifdef BSP_USING_SPI_FLASH
|
||||
|
||||
#include "spi_flash.h"
|
||||
#ifdef RT_USING_SFUD
|
||||
#include "spi_flash_sfud.h"
|
||||
#endif
|
||||
|
||||
#define SPI_BUS_NAME "spi3"
|
||||
#define SPI_FLASH_DEVICE_NAME "spi30"
|
||||
#define SPI_FLASH_CHIP "w25q64"
|
||||
#define SPI_FLASH_SS_PORT GPIO_PORT_C
|
||||
#define SPI_FLASH_SS_PIN GPIO_PIN_07
|
||||
/* Partition Name */
|
||||
#define FS_PARTITION_NAME "filesystem"
|
||||
|
||||
#ifdef RT_USING_SFUD
|
||||
static void rt_hw_spi_flash_reset(char *spi_dev_name)
|
||||
{
|
||||
struct rt_spi_device *spi_dev_w25;
|
||||
rt_uint8_t w25_en_reset = 0x66;
|
||||
rt_uint8_t w25_reset_dev = 0x99;
|
||||
|
||||
spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
|
||||
if (!spi_dev_w25)
|
||||
{
|
||||
rt_kprintf("Can't find %s device!\n", spi_dev_name);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
|
||||
rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
|
||||
DDL_DelayMS(1U);
|
||||
rt_kprintf("Reset ext flash!\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int rt_hw_spi_flash_with_sfud_init(void)
|
||||
{
|
||||
rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
|
||||
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
|
||||
|
||||
static int rt_hw_fs_init(void)
|
||||
{
|
||||
struct rt_device *mtd_dev = RT_NULL;
|
||||
|
||||
/* 初始化 fal */
|
||||
fal_init();
|
||||
/* 生成 mtd 设备 */
|
||||
mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
|
||||
if (!mtd_dev)
|
||||
{
|
||||
LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 格式化文件系统 */
|
||||
if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to initialize filesystem!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to Format fs!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
INIT_APP_EXPORT(rt_hw_fs_init);
|
||||
|
||||
#endif /* RT_USING_SFUD */
|
||||
|
||||
#endif /* BSP_USING_SPI_FLASH */
|
||||
@@ -0,0 +1,20 @@
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = []
|
||||
|
||||
src += Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
LOCAL_CFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
LOCAL_CFLAGS += ' -std=c99'
|
||||
elif rtconfig.PLATFORM in ['armcc']:
|
||||
LOCAL_CFLAGS += ' --c99'
|
||||
|
||||
group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/* enable hc32f4 onchip flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_HC32F4
|
||||
/* enable SFUD flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_SFUD
|
||||
|
||||
extern const struct fal_flash_dev hc32_onchip_flash;
|
||||
extern struct fal_flash_dev ext_nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&hc32_onchip_flash, \
|
||||
&ext_nor_flash0, \
|
||||
}
|
||||
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0}, \
|
||||
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <fal.h>
|
||||
|
||||
#include <sfud.h>
|
||||
#ifdef RT_USING_SFUD
|
||||
#include <spi_flash_sfud.h>
|
||||
#endif
|
||||
|
||||
#ifndef FAL_USING_NOR_FLASH_DEV_NAME
|
||||
#define FAL_USING_NOR_FLASH_DEV_NAME "w25q64"
|
||||
#endif
|
||||
|
||||
static int init(void);
|
||||
static int read(long offset, uint8_t *buf, size_t size);
|
||||
static int write(long offset, const uint8_t *buf, size_t size);
|
||||
static int erase(long offset, size_t size);
|
||||
|
||||
static sfud_flash_t sfud_dev = NULL;
|
||||
struct fal_flash_dev ext_nor_flash0 =
|
||||
{
|
||||
.name = FAL_USING_NOR_FLASH_DEV_NAME,
|
||||
.addr = 0,
|
||||
.len = 8 * 1024 * 1024,
|
||||
.blk_size = 4096,
|
||||
.ops = {init, read, write, erase},
|
||||
.write_gran = 1
|
||||
};
|
||||
|
||||
static int init(void)
|
||||
{
|
||||
/* RT-Thread RTOS platform */
|
||||
sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
|
||||
if (NULL == sfud_dev)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
/* update the flash chip information */
|
||||
ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
|
||||
ext_nor_flash0.len = sfud_dev->chip.capacity;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read(long offset, uint8_t *buf, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int write(long offset, const uint8_t *buf, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int erase(long offset, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 958 KiB After Width: | Height: | Size: 671 KiB |
@@ -0,0 +1,80 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals/> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F460"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F460.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/project"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -179,12 +179,13 @@
|
||||
<debug>0</debug>
|
||||
<option>
|
||||
<name>CCDefines</name>
|
||||
<state>__DEBUG</state>
|
||||
<state />
|
||||
<state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
|
||||
<state>RT_USING_DLIBC</state>
|
||||
<state>RT_USING_LIBC</state>
|
||||
<state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
|
||||
<state>HC32F460</state>
|
||||
<state>__DEBUG</state>
|
||||
<state>__RTTHREAD__</state>
|
||||
<state>USE_DDL_DRIVER</state>
|
||||
</option>
|
||||
@@ -316,27 +317,28 @@
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state />
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\..\..\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\board</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\include</state>
|
||||
<state>$PROJ_DIR$\board\config\usb_config</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
@@ -723,7 +725,8 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkConfigDefines</name>
|
||||
<state />
|
||||
<state>_LINK_FLASH_= 0</state>
|
||||
<state>_HC32F460_512K_= 1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkMapFile</name>
|
||||
@@ -1172,6 +1175,7 @@
|
||||
<state>RT_USING_LIBC</state>
|
||||
<state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
|
||||
<state>HC32F460</state>
|
||||
<state>__DEBUG</state>
|
||||
<state>__RTTHREAD__</state>
|
||||
<state>USE_DDL_DRIVER</state>
|
||||
</option>
|
||||
@@ -1303,27 +1307,28 @@
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state />
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\..\..\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\board</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\include</state>
|
||||
<state>$PROJ_DIR$\board\config\usb_config</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
@@ -1706,7 +1711,8 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkConfigDefines</name>
|
||||
<state />
|
||||
<state>_LINK_FLASH_= 0</state>
|
||||
<state>_HC32F460_512K_= 1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkMapFile</name>
|
||||
@@ -1979,6 +1985,9 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applications\main.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applications\xtal32_fcm.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Compiler</name>
|
||||
@@ -2090,6 +2099,9 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\startup_hc32f460.s</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_common.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_gpio.c</name>
|
||||
</file>
|
||||
|
||||
@@ -10,7 +10,7 @@
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
|
||||
@@ -30,7 +30,7 @@
|
||||
<SLE66CMisc />
|
||||
<SLE66AMisc />
|
||||
<SLE66LinkerMisc />
|
||||
<SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR</SFDFile>
|
||||
<SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath />
|
||||
@@ -46,10 +46,10 @@
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<OutputName>rt-thread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
@@ -182,8 +182,9 @@
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>1</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
@@ -277,7 +278,7 @@
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x03000C00</StartAddress>
|
||||
<Size>0x3FC</Size>
|
||||
<Size>0x3C0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
@@ -333,9 +334,9 @@
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls />
|
||||
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, USE_DDL_DRIVER, __RTTHREAD__</Define>
|
||||
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, USE_DDL_DRIVER, __RTTHREAD__, __DEBUG</Define>
|
||||
<Undefine />
|
||||
<IncludePath>..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;.;..\libraries\hc32f460_ddl\drivers\cmsis\Include;board;..\..\..\components\libc\compilers\common\extension;applications;..\..\..\libcpu\arm\cortex-m4;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board\ports;..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc;..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;..\..\..\components\drivers\include;..\libraries\hc32_drivers;..\..\..\components\libc\posix\ipc;board\config;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\finsh</IncludePath>
|
||||
<IncludePath>..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include;..\..\..\include;..\libraries\hc32_drivers;..\libraries\hc32f460_ddl\drivers\cmsis\Include;board\config;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;board\config\usb_config;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;board\ports;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc;.;board;..\..\..\libcpu\arm\cortex-m4;applications</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
@@ -348,7 +349,7 @@
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls />
|
||||
<Define />
|
||||
@@ -385,6 +386,13 @@
|
||||
<FilePath>applications\main.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>xtal32_fcm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>applications\xtal32_fcm.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Compiler</GroupName>
|
||||
@@ -579,6 +587,13 @@
|
||||
<FilePath>..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\ARM\startup_hc32f460.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>drv_common.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\hc32_drivers\drv_common.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>drv_gpio.c</FileName>
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
@@ -38,14 +39,12 @@
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart4"
|
||||
#define RT_VER_NUM 0x50002
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
@@ -85,6 +84,7 @@
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
@@ -114,6 +114,9 @@
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
@@ -133,6 +136,15 @@
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
@@ -240,8 +252,13 @@
|
||||
|
||||
#define SOC_HC32F460PE
|
||||
|
||||
/* On-chip Drivers */
|
||||
|
||||
#define BSP_USING_ON_CHIP_FLASH_CACHE
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
|
||||
@@ -17,7 +17,10 @@ if os.getenv('RTT_ROOT'):
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
else:
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
@@ -25,9 +28,6 @@ elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
[PlDriver]
|
||||
MemConfigValue=$PROJ_DIR$/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd
|
||||
[PlCacheRanges]
|
||||
CustomRanges0=0 0 524288 1 2048
|
||||
CustomRangesText0=Flash
|
||||
CustomRanges1=0 50334720 1020 1 2048
|
||||
CustomRangesText1=OTP
|
||||
CustomRanges2=0 536838144 192512 0 2048
|
||||
CustomRangesText2=SRAM
|
||||
CustomRanges3=0 537853952 4096 0 2048
|
||||
CustomRangesText3=RET_SRAM
|
||||
CustomRanges4=0 1073741824 536870912 2 0
|
||||
CustomRangesText4=Peripheral
|
||||
CustomRanges5=0 2550136832 67108864 1 2048
|
||||
CustomRangesText5=QSPI
|
||||
CustomRanges6=0 2617245696 67108864 2 67108864
|
||||
CustomRangesText6=QSPI_REG
|
||||
CustomRanges7=0 3758096384 536870912 2 0
|
||||
CustomRangesText7=Private peripheral
|
||||
[Stack]
|
||||
FillEnabled=0
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnLogOnly=1
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[Disassemble mode]
|
||||
mode=0
|
||||
[Breakpoints2]
|
||||
Count=0
|
||||
[Aliases]
|
||||
Count=0
|
||||
SuppressDialog=0
|
||||
[Jet]
|
||||
DisableInterrupts=0
|
||||
LeaveRunning=0
|
||||
MultiCoreRunAll=0
|
||||
[ArmDriver]
|
||||
EnableCache=0
|
||||
@@ -181,7 +181,7 @@
|
||||
<debug>0</debug>
|
||||
<option>
|
||||
<name>CCDefines</name>
|
||||
<state>__DEBUG</state>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPreprocFile</name>
|
||||
@@ -697,7 +697,8 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkConfigDefines</name>
|
||||
<state></state>
|
||||
<state>_LINK_FLASH_= 0</state>
|
||||
<state>_HC32F460_512K_= 1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkMapFile</name>
|
||||
@@ -1652,7 +1653,8 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkConfigDefines</name>
|
||||
<state></state>
|
||||
<state>_LINK_FLASH_= 0</state>
|
||||
<state>_HC32F460_512K_= 1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IlinkMapFile</name>
|
||||
|
||||
@@ -10,7 +10,7 @@
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
|
||||
@@ -33,7 +33,7 @@
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR</SFDFile>
|
||||
<SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
@@ -49,10 +49,10 @@
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<OutputName>rt-thread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
@@ -185,8 +185,9 @@
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>1</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
@@ -280,7 +281,7 @@
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x03000C00</StartAddress>
|
||||
<Size>0x3FC</Size>
|
||||
<Size>0x3C0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
@@ -351,7 +352,7 @@
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,68 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>project</name>
|
||||
<comment />
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>rt-thread</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/libcpu</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/libraries</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
@@ -40,17 +40,31 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下：
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| USB 转串口 | 支持 | 使用 UART1 |
|
||||
| LED | 支持 | LED |
|
||||
| ETH | 支持 | |
|
||||
| ADC | 支持 | |
|
||||
| CAN | 支持 | |
|
||||
| LED | 支持 | LED |
|
||||
| Nand | 支持 | MT29F2G08AB |
|
||||
| SDRAM | 支持 | IS42S16400J |
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| Crypto | 支持 | AES, CRC, HASH, RNG, UID |
|
||||
| DAC | 支持 | |
|
||||
| ADC | 支持 | |
|
||||
| CAN | 支持 | |
|
||||
| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
|
||||
| UART | 支持 | UART1~10 |
|
||||
| PM | 支持 | |
|
||||
| Lptimer | 支持 | |
|
||||
| Hwtimer | 支持 | |
|
||||
| Pulse_encoder | 支持 | |
|
||||
| PWM | 支持 | |
|
||||
| RTC | 支持 | 闹钟精度为1分钟 |
|
||||
| WDT | 支持 | |
|
||||
| I2C | 支持 | 软件、硬件 I2C |
|
||||
| QSPI | 支持 | |
|
||||
| SPI | 支持 | SPI1~6 |
|
||||
| I2C | 支持 | 软件 I2C |
|
||||
|
||||
| SDIO | 支持 | |
|
||||
| UART V1 & V2 | 支持 | UART1~10 |
|
||||
| USB | 支持 | USBFS/HS Core， device/host模式 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
@@ -107,8 +121,19 @@ msh >
|
||||
|
||||
## 注意事项
|
||||
|
||||
| 板载外设 | 模式 | 注意事项 |
|
||||
| :------: | :----: | :----------------------------------------------------------- |
|
||||
| USB | device | 由于RTT抽象层的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） |
|
||||
| USB | device | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 |
|
||||
| USB | host | 由于main()函数中的LED闪烁示例，使用的是USBFS主机口的供电控制管脚，因而当配置为使用USBFS Core的主机模式时，需要将main()函数中的LED示例代码手动屏蔽。 |
|
||||
| USB | host | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 |
|
||||
| USB | host | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 |
|
||||
| USB | host | 目前仅实现并测试了对U盘的支持。 |
|
||||
| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
|
||||
| USB | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 |
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>
|
||||
@@ -56,5 +56,7 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -13,7 +12,6 @@
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
|
||||
/* defined the LED_GREEN pin: PC9 */
|
||||
#define LED_GREEN_PIN GET_PIN(C, 9)
|
||||
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-27 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -15,9 +15,13 @@ board_config.c
|
||||
if GetDepend(['BSP_USING_TCA9539']):
|
||||
src += Glob('ports/tca9539.c')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/drv_spi_flash.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
path += [cwd + '/config/usb_config']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
@@ -28,7 +32,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
|
||||
|
||||
CPPDEFINES = ['HC32F4A0']
|
||||
CPPDEFINES = ['HC32F4A0', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -20,12 +19,18 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_SIZE (2 * 1024 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (512)
|
||||
#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
@@ -36,6 +41,11 @@ extern int __bss_end;
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -24,6 +23,7 @@ extern "C" {
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
@@ -46,6 +46,7 @@ extern "C" {
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
@@ -68,6 +69,7 @@ extern "C" {
|
||||
#define ADC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -20,19 +19,31 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "can1", \
|
||||
.name = CAN1_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "can2", \
|
||||
.name = CAN2_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-05-12 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user