mirror of
https://github.com/RT-Thread/rt-thread.git
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Add ev_hc32f334_lqfp64 board and update package relation. #10522
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This commit is contained in:
Jamie
GitHub
1
.github/ALL_BSP_COMPILE.json
vendored
1
.github/ALL_BSP_COMPILE.json
vendored
@@ -47,6 +47,7 @@
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"at32/at32m416-start",
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"hc32/ev_hc32f4a0_lqfp176",
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"hc32/ev_hc32f4a8_lqfp176",
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"hc32/ev_hc32f334_lqfp64",
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"hc32/ev_hc32f448_lqfp80",
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"hc32/ev_hc32f460_lqfp100_v2",
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"hc32/ev_hc32f472_lqfp100",
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@@ -87,6 +87,10 @@ tag: bsp_gd32e503v-eval
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path: bsp/gd32/arm/gd32e503v-eval
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owners: 蒙蒙plus(meng-plus)<chengmeng_2@outlook.com>
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tag: bsp_hc32
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path: bsp/hc32
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owners: Levi Zhang(levizh)<levizhangxl@gmail.com>
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tag: bsp_k230
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path: bsp/k230
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owners: Chen Wang(unicornx)<unicorn_wang@outlook.com>
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@@ -0,0 +1,7 @@
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devices.gpio:
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kconfig:
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- CONFIG_BSP_USING_GPIO=y
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devices.uart:
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kconfig:
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- CONFIG_BSP_USING_UART=y
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- CONFIG_BSP_USING_UART2=y
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1462
bsp/hc32/ev_hc32f334_lqfp64/.config
Normal file
1462
bsp/hc32/ev_hc32f334_lqfp64/.config
Normal file
File diff suppressed because it is too large
Load Diff
220
bsp/hc32/ev_hc32f334_lqfp64/.cproject
Normal file
220
bsp/hc32/ev_hc32f334_lqfp64/.cproject
Normal file
File diff suppressed because one or more lines are too long
42
bsp/hc32/ev_hc32f334_lqfp64/.gitignore
vendored
Normal file
42
bsp/hc32/ev_hc32f334_lqfp64/.gitignore
vendored
Normal file
@@ -0,0 +1,42 @@
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*.pyc
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*.map
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*.dblite
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*.elf
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*.bin
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*.hex
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*.axf
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*.exe
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*.pdb
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*.idb
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*.ilk
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*.old
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build
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Debug
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documentation/html
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packages/
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*~
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*.o
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*.obj
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*.out
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*.bak
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*.dep
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*.lib
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*.i
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*.d
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.DS_Stor*
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.config 3
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.config 4
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.config 5
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Midea-X1
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*.uimg
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GPATH
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GRTAGS
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GTAGS
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.vscode
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JLinkLog.txt
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JLinkSettings.ini
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DebugConfig/
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RTE/
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settings/
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*.uvguix*
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cconfig.h
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78
bsp/hc32/ev_hc32f334_lqfp64/.project
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78
bsp/hc32/ev_hc32f334_lqfp64/.project
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@@ -0,0 +1,78 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>project</name>
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<comment />
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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<triggers>clean,full,incremental,</triggers>
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<arguments>
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</arguments>
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</buildCommand>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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<triggers>full,incremental,</triggers>
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<arguments>
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</arguments>
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</buildCommand>
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</buildSpec>
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<natures>
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<nature>org.eclipse.cdt.core.cnature</nature>
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<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
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<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
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</natures>
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<linkedResources>
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<link>
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<name>rt-thread</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/components</name>
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<type>2</type>
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||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
|
||||
</link>
|
||||
<link>
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||||
<name>rt-thread/libcpu</name>
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<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
|
||||
</link>
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<link>
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<name>rt-thread/bsp/hc32</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/libraries</name>
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<type>2</type>
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<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/platform</name>
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<type>2</type>
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<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/tests</name>
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||||
<type>2</type>
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||||
<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
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</link>
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||||
</linkedResources>
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</projectDescription>
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12
bsp/hc32/ev_hc32f334_lqfp64/Kconfig
Normal file
12
bsp/hc32/ev_hc32f334_lqfp64/Kconfig
Normal file
@@ -0,0 +1,12 @@
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mainmenu "RT-Thread Configuration"
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BSP_DIR := .
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RTT_DIR := ../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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rsource "../libraries/Kconfig"
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rsource "board/Kconfig"
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140
bsp/hc32/ev_hc32f334_lqfp64/README.md
Normal file
140
bsp/hc32/ev_hc32f334_lqfp64/README.md
Normal file
@@ -0,0 +1,140 @@
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# XHSC EV_F334_LQ64_Rev1.0 开发板 BSP 说明
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## 简介
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本文档为小华半导体为 EV_F334_LQ64_Rev1.0 开发板提供的 BSP (板级支持包) 说明。
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||||
主要内容如下：
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||||
- 开发板资源介绍
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||||
- BSP 快速上手
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||||
- 进阶使用方法
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||||
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||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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||||
## 开发板介绍
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EV_F334_LQ64_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F334MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F334MCTI 的芯片性能。
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开发板外观如下图所示：
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EV_F334_LQ64_Rev1.0 开发板常用 **板载资源** 如下：
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- **MCU**
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- HC32F334MCTI
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- 主频200MHz
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- 256KB FLASH
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- 68KB RAM
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- **外部Memory**
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- BL24C256（EEPROM, 256Kbits）
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- W25Q64（SPI NOR，64MB）
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- IS62WV51216（SRAM， 1MB）
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- **常用外设**
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- LED: 4 个，User LED（LED0，LED1，LED2，LED3）。
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- 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0）
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||||
- **常用接口**
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- USB转串口
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- CAN DB9接口 * 2
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- TFT接口
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||||
- SmartCard接口
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||||
- I2C/USART/SPI接口
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||||
- **调试接口**
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||||
- 板载DAP调试器
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||||
- 标准JTAG/SWD/Trace
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||||
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||||
开发板更多详细信息请参考小华半导体半导体[EV_F334_LQ64_Rev1.0](https://www.xhsc.com.cn)
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## 外设支持
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|
||||
本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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|:-------- |:--------:|:--------:|
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||||
| USB 转串口 | 支持 | 使用 UART2 |
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||||
| LED | 支持 | LED1~4 |
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||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
|:------------- |:--------:|:------------------------------------------:|
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||||
| Crypto | 支持 | AES, CRC, HASH, RNG, UID |
|
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| DAC | 支持 | |
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||||
| ADC | 支持 | ADC1: CH10, CH11, <br>ADC3: CH1 |
|
||||
| CAN | 支持 | CAN1、CAN2 |
|
||||
| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
|
||||
| I2C | 支持 | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
|
||||
| PM | 支持 | |
|
||||
| Lptimer | 支持 | |
|
||||
| Hwtimer | 支持 | Hwtimer1~5 |
|
||||
| Pulse_encoder | 支持 | |
|
||||
| PWM | 支持 | |
|
||||
| RTC | 支持 | 闹钟精度为1分钟 |
|
||||
| WDT | 支持 | |
|
||||
| I2C | 支持 | 软件、硬件 I2C |
|
||||
| QSPI | 支持 | |
|
||||
| SPI | 支持 | SPI1~3<br>SPI1支持W25Q |
|
||||
| UART | 支持 | UART1~6<br>UART2为console使用 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用Type-A to MircoUSB线连接开发板和PC供电。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。
|
||||
|
||||
USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.0.1 build Feb 4 2024 16:44:26
|
||||
2006 - 2022 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
| 板载外设 | 模式 | 注意事项 |
|
||||
| ---- | ---- | ------------------------------------------------------------------------------------------------------ |
|
||||
| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
|
||||
15
bsp/hc32/ev_hc32f334_lqfp64/SConscript
Normal file
15
bsp/hc32/ev_hc32f334_lqfp64/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
83
bsp/hc32/ev_hc32f334_lqfp64/SConstruct
Normal file
83
bsp/hc32/ev_hc32f334_lqfp64/SConstruct
Normal file
@@ -0,0 +1,83 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "hc32-f3-cmsis-latest"),
|
||||
os.path.join("packages", "hc32-f3-series-latest")
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
# include platform
|
||||
platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
|
||||
objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
|
||||
|
||||
# include tests
|
||||
test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
|
||||
objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
15
bsp/hc32/ev_hc32f334_lqfp64/applications/SConscript
Normal file
15
bsp/hc32/ev_hc32f334_lqfp64/applications/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
31
bsp/hc32/ev_hc32f334_lqfp64/applications/main.c
Normal file
31
bsp/hc32/ev_hc32f334_lqfp64/applications/main.c
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-07-10 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED_BLUE pin: PC13 */
|
||||
#define LED_BLUE_PIN GET_PIN(C, 13)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED_BLUE_PIN pin mode to output */
|
||||
rt_pin_mode(LED_BLUE_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_BLUE_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_BLUE_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
99
bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c
Normal file
99
bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
#define XTAL32_FCM_UNIT (CM_FCM)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
619
bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig
Normal file
619
bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig
Normal file
File diff suppressed because it is too large
Load Diff
19
bsp/hc32/ev_hc32f334_lqfp64/board/SConscript
Normal file
19
bsp/hc32/ev_hc32f334_lqfp64/board/SConscript
Normal file
@@ -0,0 +1,19 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
|
||||
CPPDEFINES = ['HC32F334', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
125
bsp/hc32/ev_hc32f334_lqfp64/board/board.c
Normal file
125
bsp/hc32/ev_hc32f334_lqfp64/board/board.c
Normal file
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "board_config.h"
|
||||
|
||||
/* unlock/lock peripheral */
|
||||
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
/** System Base Configuration
|
||||
*/
|
||||
void SystemBase_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
|
||||
EFM_ICacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
|
||||
EFM_DCacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
|
||||
EFM_PrefetchCmd(ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
stc_clock_xtal_init_t stcXtalInit;
|
||||
stc_clock_pll_init_t stcPLLHInit;
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
stc_clock_xtal32_init_t stcXtal32Init;
|
||||
#endif
|
||||
#if defined(BSP_RTC_USING_XTAL_DIV)
|
||||
stc_clock_xtaldiv_init_t stcXtaldivInit;
|
||||
#endif
|
||||
|
||||
/* PCLK0, HCLK Max 120MHz */
|
||||
/* PCLK1, PCLK2, PCLK3, PCLK4 Max 60MHz */
|
||||
CLK_SetClockDiv(CLK_BUS_CLK_ALL,
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV2 |
|
||||
CLK_PCLK3_DIV2 | CLK_PCLK4_DIV2 | CLK_HCLK_DIV1));
|
||||
|
||||
|
||||
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
|
||||
(void)CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||||
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||||
stcXtalInit.u8State = CLK_XTAL_ON;
|
||||
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||||
(void)CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*60 = 480MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 60UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||||
(void)CLK_PLLInit(&stcPLLHInit);
|
||||
|
||||
/* 2 cycles for 100 ~ 120MHz */
|
||||
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE2);
|
||||
/* 2 cycles for 100 ~ 120MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_RD_WAIT2);
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
/* Xtal32 config */
|
||||
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
|
||||
(void)CLK_Xtal32StructInit(&stcXtal32Init);
|
||||
stcXtal32Init.u8State = CLK_XTAL32_ON;
|
||||
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
|
||||
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
|
||||
(void)CLK_Xtal32Init(&stcXtal32Init);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL_DIV)
|
||||
/* Xtal Div config */
|
||||
(void)CLK_XtalDivStructInit(&stcXtaldivInit);
|
||||
/* 8000000Hz / 32768Hz = 0x7A12 / 0x80 */
|
||||
stcXtaldivInit.u32Num = 0x7A12UL;
|
||||
stcXtaldivInit.u32Den = 0x80UL;
|
||||
stcXtaldivInit.u32State = CLK_XTALDIV_ON;
|
||||
(void)CLK_XtalDivInit(&stcXtaldivInit);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Clock Configuration
|
||||
*/
|
||||
void PeripheralClock_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
CLK_SetCANClockSrc(CLK_MCAN1, CLK_MCANCLK_SYSCLK_DIV3);
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
CLK_SetCANClockSrc(CLK_MCAN2, CLK_MCANCLK_SYSCLK_DIV3);
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Registers Unlock
|
||||
*/
|
||||
void PeripheralRegister_Unlock(void)
|
||||
{
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
53
bsp/hc32/ev_hc32f334_lqfp64/board/board.h
Normal file
53
bsp/hc32/ev_hc32f334_lqfp64/board/board.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (128 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (32)
|
||||
#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
388
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c
Normal file
388
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c
Normal file
@@ -0,0 +1,388 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include "board_config.h"
|
||||
|
||||
/**
|
||||
* The below functions will initialize HC32 board.
|
||||
*/
|
||||
|
||||
#if defined RT_USING_SERIAL
|
||||
rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)USARTx)
|
||||
{
|
||||
#if defined(BSP_USING_UART1)
|
||||
case (rt_uint32_t)CM_USART1:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
|
||||
GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_UART2)
|
||||
case (rt_uint32_t)CM_USART2:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC);
|
||||
GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_I2C)
|
||||
rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
|
||||
switch ((rt_uint32_t)I2Cx)
|
||||
{
|
||||
#if defined(BSP_USING_I2C1)
|
||||
case (rt_uint32_t)CM_I2C:
|
||||
/* Configure I2C1 SDA/SCL pin. */
|
||||
GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
|
||||
GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
switch ((rt_uint32_t)ADCx)
|
||||
{
|
||||
#if defined(BSP_USING_ADC1)
|
||||
case (rt_uint32_t)CM_ADC1:
|
||||
(void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_ADC2)
|
||||
case (rt_uint32_t)CM_ADC2:
|
||||
(void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_ADC3)
|
||||
case (rt_uint32_t)CM_ADC3:
|
||||
(void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_DAC)
|
||||
rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
switch ((rt_uint32_t)DACx)
|
||||
{
|
||||
#if defined(BSP_USING_DAC1)
|
||||
case (rt_uint32_t)CM_DAC:
|
||||
(void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CAN)
|
||||
void CanPhyEnable(void)
|
||||
{
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
|
||||
TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
|
||||
TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
|
||||
#endif
|
||||
}
|
||||
rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)MCANx)
|
||||
{
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
case (rt_uint32_t)CM_MCAN1:
|
||||
GPIO_SetFunc(MCAN1_TX_PORT, MCAN1_TX_PIN, MCAN1_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(MCAN1_RX_PORT, MCAN1_RX_PIN, MCAN1_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
case (rt_uint32_t)CM_MCAN2:
|
||||
GPIO_SetFunc(MCAN2_TX_PORT, MCAN2_TX_PIN, MCAN2_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(MCAN2_RX_PORT, MCAN2_RX_PIN, MCAN2_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (RT_USING_SPI)
|
||||
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
#if defined(BSP_USING_SPI1)
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
#endif
|
||||
|
||||
switch ((rt_uint32_t)CM_SPIx)
|
||||
{
|
||||
#if defined(BSP_USING_SPI1)
|
||||
case (rt_uint32_t)CM_SPI1:
|
||||
GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinState = PIN_STAT_SET;
|
||||
stcGpioInit.u16PinDir = PIN_DIR_OUT;
|
||||
GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
|
||||
GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
|
||||
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
|
||||
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
|
||||
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
#if defined(BSP_USING_PWM_TMRA)
|
||||
rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMRAx)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
case (rt_uint32_t)CM_TMRA_1:
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2)
|
||||
case (rt_uint32_t)CM_TMRA_2:
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMR4)
|
||||
rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMR4x)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMR4_1)
|
||||
case (rt_uint32_t)CM_TMR4_1:
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OUH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OUL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OVH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OVL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OWH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OWL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMR6)
|
||||
rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMR6x)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMR6_1)
|
||||
case (rt_uint32_t)CM_TMR6_1:
|
||||
#ifdef BSP_USING_PWM_TMR6_1_A
|
||||
GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR6_1_B
|
||||
GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE)
|
||||
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)tmr_instance)
|
||||
{
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
case (rt_uint32_t)CM_TMR6_1:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
case (rt_uint32_t)CM_TMR6_2:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
case (rt_uint32_t)CM_TMR6_3:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_PM
|
||||
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
{
|
||||
switch (run_mode)
|
||||
{
|
||||
case PM_RUN_MODE_HIGH_SPEED:
|
||||
case PM_RUN_MODE_NORMAL_SPEED:
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
break;
|
||||
|
||||
case PM_RUN_MODE_LOW_SPEED:
|
||||
/* Ensure that system clock less than 8M */
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
|
||||
rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
276
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h
Normal file
276
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h
Normal file
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __BOARD_CONFIG_H__
|
||||
#define __BOARD_CONFIG_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
|
||||
/************************* XTAL port **********************/
|
||||
#define XTAL_PORT (GPIO_PORT_F)
|
||||
#define XTAL_IN_PIN (GPIO_PIN_00)
|
||||
#define XTAL_OUT_PIN (GPIO_PIN_01)
|
||||
|
||||
/************************ USART port **********************/
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define USART1_RX_PORT (GPIO_PORT_B)
|
||||
#define USART1_RX_PIN (GPIO_PIN_06)
|
||||
#define USART1_RX_FUNC (GPIO_FUNC_33)
|
||||
|
||||
#define USART1_TX_PORT (GPIO_PORT_B)
|
||||
#define USART1_TX_PIN (GPIO_PIN_07)
|
||||
#define USART1_TX_FUNC (GPIO_FUNC_32)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#define USART2_RX_PORT (GPIO_PORT_C)
|
||||
#define USART2_RX_PIN (GPIO_PIN_04)
|
||||
#define USART2_RX_FUNC (GPIO_FUNC_37)
|
||||
|
||||
#define USART2_TX_PORT (GPIO_PORT_C)
|
||||
#define USART2_TX_PIN (GPIO_PIN_10)
|
||||
#define USART2_TX_FUNC (GPIO_FUNC_36)
|
||||
#endif
|
||||
|
||||
/************************ I2C port **********************/
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#define I2C1_SDA_PORT (GPIO_PORT_B)
|
||||
#define I2C1_SDA_PIN (GPIO_PIN_06)
|
||||
#define I2C1_SDA_FUNC (GPIO_FUNC_52)
|
||||
|
||||
#define I2C1_SCL_PORT (GPIO_PORT_B)
|
||||
#define I2C1_SCL_PIN (GPIO_PIN_07)
|
||||
#define I2C1_SCL_FUNC (GPIO_FUNC_53)
|
||||
#endif
|
||||
|
||||
/*********** ADC configure *********/
|
||||
#if defined(BSP_USING_ADC1)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
|
||||
#define ADC1_CH_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC2)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
|
||||
#define ADC2_CH_PIN (GPIO_PIN_04)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC3)
|
||||
#define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */
|
||||
#define ADC3_CH_PIN (GPIO_PIN_03)
|
||||
#endif
|
||||
|
||||
/*********** DAC configure *********/
|
||||
#if defined(BSP_USING_DAC1)
|
||||
#define DAC1_CH1_PORT (GPIO_PORT_A)
|
||||
#define DAC1_CH1_PIN (GPIO_PIN_04)
|
||||
#define DAC1_CH2_PORT (GPIO_PORT_A)
|
||||
#define DAC1_CH2_PIN (GPIO_PIN_05)
|
||||
#endif
|
||||
|
||||
/*********** CAN configure *********/
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
#define MCAN1_TX_PORT (GPIO_PORT_C)
|
||||
#define MCAN1_TX_PIN (GPIO_PIN_12)
|
||||
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
|
||||
#define MCAN1_RX_PORT (GPIO_PORT_D)
|
||||
#define MCAN1_RX_PIN (GPIO_PIN_00)
|
||||
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
#define MCAN2_TX_PORT (GPIO_PORT_H)
|
||||
#define MCAN2_TX_PIN (GPIO_PIN_02)
|
||||
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
|
||||
#define MCAN2_RX_PORT (GPIO_PORT_E)
|
||||
#define MCAN2_RX_PIN (GPIO_PIN_04)
|
||||
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#endif
|
||||
|
||||
/************************* SPI port ***********************/
|
||||
#if defined(BSP_USING_SPI1)
|
||||
#define SPI1_CS_PORT (GPIO_PORT_C)
|
||||
#define SPI1_CS_PIN (GPIO_PIN_07)
|
||||
|
||||
#define SPI1_SCK_PORT (GPIO_PORT_B)
|
||||
#define SPI1_SCK_PIN (GPIO_PIN_14)
|
||||
#define SPI1_SCK_FUNC (GPIO_FUNC_47)
|
||||
|
||||
#define SPI1_MOSI_PORT (GPIO_PORT_B)
|
||||
#define SPI1_MOSI_PIN (GPIO_PIN_13)
|
||||
#define SPI1_MOSI_FUNC (GPIO_FUNC_44)
|
||||
|
||||
#define SPI1_MISO_PORT (GPIO_PORT_D)
|
||||
#define SPI1_MISO_PIN (GPIO_PIN_09)
|
||||
#define SPI1_MISO_FUNC (GPIO_FUNC_45)
|
||||
|
||||
#define SPI1_WP_PORT (GPIO_PORT_D)
|
||||
#define SPI1_WP_PIN (GPIO_PIN_10)
|
||||
|
||||
#define SPI1_HOLD_PORT (GPIO_PORT_D)
|
||||
#define SPI1_HOLD_PIN (GPIO_PIN_11)
|
||||
#endif
|
||||
|
||||
/************************ RTC/PM *****************************/
|
||||
#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
#define XTAL32_PORT (GPIO_PORT_C)
|
||||
#define XTAL32_IN_PIN (GPIO_PIN_14)
|
||||
#define XTAL32_OUT_PIN (GPIO_PIN_15)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
/*********** PWM_TMRA configure *********/
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH1)
|
||||
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH2)
|
||||
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH3)
|
||||
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH4)
|
||||
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
|
||||
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMRA_2)
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH1)
|
||||
#define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00)
|
||||
#define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH2)
|
||||
#define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01)
|
||||
#define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH3)
|
||||
#define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02)
|
||||
#define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH4)
|
||||
#define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03)
|
||||
#define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********** PWM_TMR4 configure *********/
|
||||
#if defined(BSP_USING_PWM_TMR4_1)
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OUH)
|
||||
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OUL)
|
||||
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07)
|
||||
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OVH)
|
||||
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OVL)
|
||||
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B)
|
||||
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00)
|
||||
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OWH)
|
||||
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OWL)
|
||||
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
|
||||
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01)
|
||||
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********** PWM_TMR6 configure *********/
|
||||
#if defined(BSP_USING_PWM_TMR6_1)
|
||||
#if defined(BSP_USING_PWM_TMR6_1_A)
|
||||
#define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR6_1_B)
|
||||
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
|
||||
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_INPUT_CAPTURE)
|
||||
#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3)
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B)
|
||||
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09)
|
||||
#endif
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E)
|
||||
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07)
|
||||
#endif
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A)
|
||||
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*********** TMRA_PULSE_ENCODER configure *********/
|
||||
#if defined(RT_USING_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
|
||||
#endif /* RT_USING_PULSE_ENCODER */
|
||||
|
||||
#endif
|
||||
|
||||
154
bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h
Normal file
154
bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h
Normal file
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_INIT_PARAMS
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC1_USING_DMA)
|
||||
#ifndef ADC1_EOCA_DMA_CONFIG
|
||||
#define ADC1_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC1_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC1_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC1_EOCA, \
|
||||
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC1_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC1_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC1_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC1_USING_DMA */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_INIT_PARAMS
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC2_USING_DMA)
|
||||
#ifndef ADC2_EOCA_DMA_CONFIG
|
||||
#define ADC2_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC2_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC2_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC2_EOCA, \
|
||||
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC2_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC2_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC2_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC2_USING_DMA */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_INIT_PARAMS
|
||||
#define ADC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC3_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC3_USING_DMA)
|
||||
#ifndef ADC3_EOCA_DMA_CONFIG
|
||||
#define ADC3_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC3_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC3_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC3_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC3_EOCA, \
|
||||
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC3_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC3_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC3_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC3_USING_DMA */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
42
bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h
Normal file
42
bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
.vref = 3300, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
191
bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h
Normal file
191
bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h
Normal file
@@ -0,0 +1,191 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DMA_CONFIG_H__
|
||||
#define __DMA_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#define UART1_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART1_TX_DMA_CHANNEL DMA_CH0
|
||||
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0
|
||||
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
|
||||
|
||||
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_TX_DMA_INSTANCE CM_DMA
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CH0
|
||||
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0
|
||||
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
|
||||
#endif
|
||||
|
||||
/* DMA1 ch1 */
|
||||
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CH1
|
||||
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1
|
||||
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
|
||||
|
||||
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_RX_DMA_INSTANCE CM_DMA
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CH1
|
||||
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1
|
||||
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
|
||||
#endif
|
||||
|
||||
/* DMA1 ch2 */
|
||||
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
|
||||
#define UART2_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART2_TX_DMA_CHANNEL DMA_CH2
|
||||
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2
|
||||
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2
|
||||
|
||||
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
|
||||
#define I2C1_TX_DMA_INSTANCE CM_DMA
|
||||
#define I2C1_TX_DMA_CHANNEL DMA_CH2
|
||||
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2
|
||||
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2
|
||||
#endif
|
||||
|
||||
/* DMA1 ch3 */
|
||||
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
|
||||
#define UART2_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART2_RX_DMA_CHANNEL DMA_CH3
|
||||
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3
|
||||
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3
|
||||
|
||||
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
|
||||
#define I2C1_RX_DMA_INSTANCE CM_DMA
|
||||
#define I2C1_RX_DMA_CHANNEL DMA_CH3
|
||||
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3
|
||||
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3
|
||||
#endif
|
||||
|
||||
/* DMA1 ch4 */
|
||||
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
|
||||
#define UART3_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART3_TX_DMA_CHANNEL DMA_CH4
|
||||
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4
|
||||
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4
|
||||
|
||||
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
|
||||
#define ADC1_EOCA_DMA_INSTANCE CM_DMA
|
||||
#define ADC1_EOCA_DMA_CHANNEL DMA_CH4
|
||||
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4
|
||||
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4
|
||||
#endif
|
||||
|
||||
/* DMA1 ch5 */
|
||||
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
|
||||
#define UART3_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART3_RX_DMA_CHANNEL DMA_CH5
|
||||
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5
|
||||
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5
|
||||
|
||||
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
|
||||
#define ADC2_EOCA_DMA_INSTANCE CM_DMA
|
||||
#define ADC2_EOCA_DMA_CHANNEL DMA_CH5
|
||||
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5
|
||||
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5
|
||||
#endif
|
||||
|
||||
/* DMA1 ch6 */
|
||||
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
|
||||
#define UART4_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART4_TX_DMA_CHANNEL DMA_CH6
|
||||
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6
|
||||
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6
|
||||
|
||||
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
|
||||
#define ADC3_EOCA_DMA_INSTANCE CM_DMA
|
||||
#define ADC3_EOCA_DMA_CHANNEL DMA_CH6
|
||||
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6
|
||||
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6
|
||||
#endif
|
||||
|
||||
/* DMA1 ch7 */
|
||||
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
||||
#define UART4_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART4_RX_DMA_CHANNEL DMA_CH7
|
||||
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7
|
||||
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
|
||||
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
|
||||
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
175
bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h
Normal file
175
bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h
Normal file
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_CONFIG_H__
|
||||
#define __GPIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#ifndef EXTINT0_IRQ_CONFIG
|
||||
#define EXTINT0_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT0_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ0, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT1_IRQ_CONFIG
|
||||
#define EXTINT1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT1_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ1, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT2_IRQ_CONFIG
|
||||
#define EXTINT2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT2_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ2, \
|
||||
}
|
||||
#endif /* EXTINT2_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT3_IRQ_CONFIG
|
||||
#define EXTINT3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT3_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ3, \
|
||||
}
|
||||
#endif /* EXTINT3_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT4_IRQ_CONFIG
|
||||
#define EXTINT4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT4_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ4, \
|
||||
}
|
||||
#endif /* EXTINT4_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT5_IRQ_CONFIG
|
||||
#define EXTINT5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT5_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ5, \
|
||||
}
|
||||
#endif /* EXTINT5_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT6_IRQ_CONFIG
|
||||
#define EXTINT6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT6_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ6, \
|
||||
}
|
||||
#endif /* EXTINT6_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT7_IRQ_CONFIG
|
||||
#define EXTINT7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT7_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ7, \
|
||||
}
|
||||
#endif /* EXTINT7_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT8_IRQ_CONFIG
|
||||
#define EXTINT8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT8_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ8, \
|
||||
}
|
||||
#endif /* EXTINT8_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT9_IRQ_CONFIG
|
||||
#define EXTINT9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT9_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ9, \
|
||||
}
|
||||
#endif /* EXTINT9_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT10_IRQ_CONFIG
|
||||
#define EXTINT10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT10_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ10, \
|
||||
}
|
||||
#endif /* EXTINT10_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT11_IRQ_CONFIG
|
||||
#define EXTINT11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT11_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ11, \
|
||||
}
|
||||
#endif /* EXTINT11_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT12_IRQ_CONFIG
|
||||
#define EXTINT12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT12_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ12, \
|
||||
}
|
||||
#endif /* EXTINT12_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT13_IRQ_CONFIG
|
||||
#define EXTINT13_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT13_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ13, \
|
||||
}
|
||||
#endif /* EXTINT13_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT14_IRQ_CONFIG
|
||||
#define EXTINT14_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT14_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ14, \
|
||||
}
|
||||
#endif /* EXTINT14_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT15_IRQ_CONFIG
|
||||
#define EXTINT15_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT15_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ15, \
|
||||
}
|
||||
#endif /* EXTINT15_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_CONFIG_H__ */
|
||||
76
bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h
Normal file
76
bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_CONFIG_H__
|
||||
#define __I2C_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#ifndef I2C1_CONFIG
|
||||
#define I2C1_CONFIG \
|
||||
{ \
|
||||
.name = "i2c1", \
|
||||
.Instance = CM_I2C, \
|
||||
.clock = FCG1_PERIPH_I2C, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C1_CONFIG */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_I2C1_USING_DMA)
|
||||
#ifndef I2C1_TX_DMA_CONFIG
|
||||
#define I2C1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_TX_DMA_INSTANCE, \
|
||||
.channel = I2C1_TX_DMA_CHANNEL, \
|
||||
.clock = I2C1_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C_TEI, \
|
||||
.flag = I2C1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C1_RX_DMA_CONFIG
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
||||
.channel = I2C1_RX_DMA_CHANNEL, \
|
||||
.clock = I2C1_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C_RXI, \
|
||||
.flag = I2C1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C1_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
236
bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h
Normal file
236
bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h
Normal file
@@ -0,0 +1,236 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_CONFIG_H__
|
||||
#define __IRQ_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
|
||||
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
|
||||
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
|
||||
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
|
||||
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
|
||||
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
|
||||
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
|
||||
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
|
||||
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
|
||||
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
|
||||
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
|
||||
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
|
||||
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
|
||||
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
|
||||
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
|
||||
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
|
||||
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
|
||||
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch1 */
|
||||
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
|
||||
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch2 */
|
||||
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
|
||||
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch3 */
|
||||
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
|
||||
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch4 */
|
||||
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
|
||||
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch5 */
|
||||
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
|
||||
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch6 */
|
||||
#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn
|
||||
#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch7 */
|
||||
#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn
|
||||
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define BSP_UART1_IRQ_NUM USART1_IRQn
|
||||
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
|
||||
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#define BSP_UART2_IRQ_NUM USART2_IRQn
|
||||
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
|
||||
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#define BSP_UART3_IRQ_NUM USART3_IRQn
|
||||
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn
|
||||
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#define BSP_UART4_IRQ_NUM USART4_IRQn
|
||||
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
|
||||
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_SPI1)
|
||||
#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn
|
||||
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI2)
|
||||
#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn
|
||||
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI3)
|
||||
#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn
|
||||
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_QSPI)
|
||||
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
|
||||
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#if defined(BSP_USING_TMRA_1)
|
||||
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_1 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_2)
|
||||
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_2 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_3)
|
||||
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_3 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_4)
|
||||
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_4 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_5)
|
||||
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_5 */
|
||||
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
|
||||
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#define BSP_MCAN1_INT1_IRQ_NUM MCAN1_INT1_IRQn
|
||||
#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_MCAN1 */
|
||||
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
|
||||
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#define BSP_MCAN2_INT1_IRQ_NUM MCAN2_INT1_IRQn
|
||||
#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_MCAN2 */
|
||||
|
||||
#if defined(RT_USING_ALARM)
|
||||
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
|
||||
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* RT_USING_ALARM */
|
||||
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
|
||||
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IRQ_CONFIG_H__ */
|
||||
363
bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h
Normal file
363
bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h
Normal file
@@ -0,0 +1,363 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __MCAN_CONFIG_H__
|
||||
#define __MCAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
/* The default configuration for MCANs. Users can modify the configurations based on the application.
|
||||
For the message RAM:
|
||||
1. MCAN1 and MCAN2 share 2048 bytes message RAM
|
||||
2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number.
|
||||
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
|
||||
If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64,
|
||||
and pay attention the total size of meesage RAM that to be allocated.
|
||||
*/
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
|
||||
#define MCAN_TOTAL_FILTER_NUM (26U)
|
||||
#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */
|
||||
#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */
|
||||
#define MCAN_TX_FIFO_NUM (6U)
|
||||
#define MCAN_RX_FIFO_NUM (6U)
|
||||
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
|
||||
#else
|
||||
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
|
||||
#define MCAN_TOTAL_FILTER_NUM (32U)
|
||||
#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */
|
||||
#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */
|
||||
#define MCAN_TX_FIFO_NUM (26U)
|
||||
#define MCAN_RX_FIFO_NUM (26U)
|
||||
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_MCAN1
|
||||
#define MCAN1_NAME ("mcan1")
|
||||
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
#define MCAN1_FD_SEL MCAN_FD_SEL
|
||||
|
||||
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
|
||||
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
|
||||
|
||||
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
|
||||
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
|
||||
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
|
||||
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
|
||||
#endif /* BSP_USING_MCAN1 */
|
||||
|
||||
#ifdef BSP_USING_MCAN2
|
||||
#define MCAN2_NAME ("mcan2")
|
||||
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
#define MCAN2_FD_SEL MCAN_FD_SEL
|
||||
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
|
||||
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
|
||||
|
||||
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
|
||||
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
|
||||
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
|
||||
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
|
||||
#endif /* BSP_USING_MCAN2 */
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
|
||||
/*
|
||||
Bit rate configuration examples for CAN FD.
|
||||
Nominal bit rate for CAN FD arbitration phase and data bit rate for CAN FD data phase.
|
||||
BitRate(bps) = MCANClock(Hz) / (Prescaler * (TimeSeg1 + TimeSeg2))
|
||||
SamplePoint(%) = TimeSeg1 / (TimeSeg1 + TimeSeg2)
|
||||
eg.
|
||||
BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps)
|
||||
SamplePoint(%) = 16 / (16 + 4) = 80%
|
||||
The following bit rate configurations are based on the max MCAN Clock(40MHz).
|
||||
NOTE:
|
||||
1. It is better to limit u32NominalPrescaler and u32DataPrescaler between 1 and 2.
|
||||
1. The unit of u32SspOffset is MCANClock.
|
||||
2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF).
|
||||
The u32TdcFilter can be get from PSR.TDCV.
|
||||
*/
|
||||
#define MCAN_FD_CFG_500K_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 32, \
|
||||
.u32DataTimeSeg2 = 8, \
|
||||
.u32DataSyncJumpWidth = 8, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 32, \
|
||||
.u32TdcFilter = 32 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_2M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 16, \
|
||||
.u32DataTimeSeg2 = 4, \
|
||||
.u32DataSyncJumpWidth = 4, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 16, \
|
||||
.u32TdcFilter = 16 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_4M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 8, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 8, \
|
||||
.u32TdcFilter = 8 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_5M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 6, \
|
||||
.u32TdcFilter = 6 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_8M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
.u32DataSyncJumpWidth = 1, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 4, \
|
||||
.u32TdcFilter = 4 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 32, \
|
||||
.u32DataTimeSeg2 = 8, \
|
||||
.u32DataSyncJumpWidth = 8, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 2*32, \
|
||||
.u32TdcFilter = 2*32 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_2M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 16, \
|
||||
.u32DataTimeSeg2 = 4, \
|
||||
.u32DataSyncJumpWidth = 4, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 16, \
|
||||
.u32TdcFilter = 16 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_4M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 8, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 8, \
|
||||
.u32TdcFilter = 8 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_5M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 6, \
|
||||
.u32TdcFilter = 6 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_8M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
.u32DataSyncJumpWidth = 1, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 4, \
|
||||
.u32TdcFilter = 4 + 1, \
|
||||
}
|
||||
|
||||
/*
|
||||
Bit rate configuration examples for classical CAN.
|
||||
BitRate(bps) = MCANClock(Hz) / (u32NominalPrescaler * (u32NominalTimeSeg1 + u32NominalTimeSeg2))
|
||||
SamplePoint(%) = u32NominalTimeSeg1 / (u32NominalTimeSeg1 + u32NominalTimeSeg2)
|
||||
eg.
|
||||
BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps)
|
||||
SamplePoint(%) = 16 / (16 + 4) = 80%
|
||||
The following bit rate configurations are based on the max MCAN Clock(40MHz).
|
||||
*/
|
||||
#define MCAN_CC_CFG_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 2, \
|
||||
.u32NominalTimeSeg1 = 16, \
|
||||
.u32NominalTimeSeg2 = 4, \
|
||||
.u32NominalSyncJumpWidth = 4, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_800K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 2, \
|
||||
.u32NominalTimeSeg1 = 20, \
|
||||
.u32NominalTimeSeg2 = 5, \
|
||||
.u32NominalSyncJumpWidth = 5, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_500K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 4, \
|
||||
.u32NominalTimeSeg1 = 16, \
|
||||
.u32NominalTimeSeg2 = 4, \
|
||||
.u32NominalSyncJumpWidth = 4, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_250K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 4, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_125K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 8, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_100K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 10, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_50K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 20, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_20K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 50, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_10K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 100, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
|
||||
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
|
||||
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
|
||||
|
||||
#else
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
|
||||
#define MCAN1_DATA_BAUD_RATE 0
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
|
||||
#define MCAN2_DATA_BAUD_RATE 0
|
||||
|
||||
#endif /* #ifdef RT_CAN_USING_CANFD */
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MCAN_CONFIG_H__ */
|
||||
|
||||
|
||||
99
bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h
Normal file
99
bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PM_CONFIG_H__
|
||||
#define __PM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PM
|
||||
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
|
||||
|
||||
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
|
||||
#define PM_TICKLESS_TIMER_ENABLE_MASK \
|
||||
( (1UL << PM_SLEEP_MODE_IDLE) | \
|
||||
(1UL << PM_SLEEP_MODE_DEEP))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief run mode config @ref pm_run_mode_config structure
|
||||
*/
|
||||
#ifndef PM_RUN_MODE_CFG
|
||||
#define PM_RUN_MODE_CFG \
|
||||
{ \
|
||||
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
|
||||
}
|
||||
#endif /* PM_RUN_MODE_CFG */
|
||||
|
||||
/**
|
||||
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_IDLE_CFG
|
||||
#define PM_SLEEP_IDLE_CFG \
|
||||
{ \
|
||||
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_IDLE_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_DEEP_CFG
|
||||
#define PM_SLEEP_DEEP_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u16Clock = PWC_STOP_CLK_KEEP, \
|
||||
.u8StopDrv = PWC_STOP_DRV_HIGH, \
|
||||
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
|
||||
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
|
||||
}, \
|
||||
.pwc_stop_type = PWC_STOP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_DEEP_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_STANDBY_CFG
|
||||
#define PM_SLEEP_STANDBY_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD1, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_STANDBY_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_SHUTDOWN_CFG
|
||||
#define PM_SLEEP_SHUTDOWN_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD3, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
|
||||
|
||||
#endif /* BSP_USING_PM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PM_CONFIG_H__ */
|
||||
206
bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h
Normal file
206
bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h
Normal file
@@ -0,0 +1,206 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PULSE_ENCODER_CONFIG_H__
|
||||
#define __PULSE_ENCODER_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PULSE_ENCODER)
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
|
||||
#ifndef PULSE_ENCODER_TMRA_1_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_1, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a1" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
|
||||
#ifndef PULSE_ENCODER_TMRA_2_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_2, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a2" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
|
||||
#ifndef PULSE_ENCODER_TMRA_3_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_3, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a3" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
|
||||
#ifndef PULSE_ENCODER_TMRA_4_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_4, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a4" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
|
||||
#ifndef PULSE_ENCODER_TMRA_5_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_5, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a5" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
|
||||
#ifndef PULSE_ENCODER_TMR6_1_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_1, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_61" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
|
||||
#ifndef PULSE_ENCODER_TMR6_2_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_2, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_62" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
|
||||
|
||||
#endif /* RT_USING_PULSE_ENCODER */
|
||||
|
||||
#endif /* __PULSE_ENCODER_CONFIG_H__ */
|
||||
663
bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h
Normal file
663
bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h
Normal file
File diff suppressed because it is too large
Load Diff
84
bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h
Normal file
84
bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h
Normal file
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI, \
|
||||
.bus_name = "spi1", \
|
||||
.clock = FCG1_PERIPH_SPI, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.channel = SPI1_TX_DMA_CHANNEL, \
|
||||
.clock = SPI1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI_SPTI, \
|
||||
.flag = SPI1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.channel = SPI1_RX_DMA_CHANNEL, \
|
||||
.clock = SPI1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI_SPRI, \
|
||||
.flag = SPI1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
114
bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h
Normal file
114
bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h
Normal file
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TMR_CONFIG_H__
|
||||
#define __TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TMRA_1
|
||||
#ifndef TMRA_1_CONFIG
|
||||
#define TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_1, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_1, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_1" \
|
||||
}
|
||||
#endif /* TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_2
|
||||
#ifndef TMRA_2_CONFIG
|
||||
#define TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_2, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_2, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_2" \
|
||||
}
|
||||
#endif /* TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_3
|
||||
#ifndef TMRA_3_CONFIG
|
||||
#define TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_3, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_3, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_3" \
|
||||
}
|
||||
#endif /* TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_4
|
||||
#ifndef TMRA_4_CONFIG
|
||||
#define TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_4, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_4, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_4" \
|
||||
}
|
||||
#endif /* TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_5
|
||||
#ifndef TMRA_5_CONFIG
|
||||
#define TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_5, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_5, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_5" \
|
||||
}
|
||||
#endif /* TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_5 */
|
||||
#endif /* __TMR_CONFIG_H__ */
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-01-10 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __IC_CONFIG_H__
|
||||
#define __IC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
#define IC1_NAME "ic1"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_1 \
|
||||
{ \
|
||||
.name = IC1_NAME, \
|
||||
.ch = TMR6_CH_A, \
|
||||
.clk_div = TMR6_CLK_DIV32, \
|
||||
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
#define IC2_NAME "ic2"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_2 \
|
||||
{ \
|
||||
.name = IC2_NAME, \
|
||||
.ch = TMR6_CH_A, \
|
||||
.clk_div = TMR6_CLK_DIV32, \
|
||||
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
#define IC3_NAME "ic3"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_3 \
|
||||
{ \
|
||||
.name = IC3_NAME, \
|
||||
.ch = TMR6_CH_B, \
|
||||
.clk_div = TMR6_CLK_DIV16, \
|
||||
.first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IC_CONFIG_H__ */
|
||||
390
bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h
Normal file
390
bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h
Normal file
@@ -0,0 +1,390 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = CM_USART1, \
|
||||
.clock = FCG3_PERIPH_USART1, \
|
||||
.irq_num = BSP_UART1_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART1_EI, \
|
||||
.rx_int_src = INT_SRC_USART1_RI, \
|
||||
.tx_int_src = INT_SRC_USART1_TI, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.channel = UART1_RX_DMA_CHANNEL, \
|
||||
.clock = UART1_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART1_RI, \
|
||||
.flag = UART1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART1_RX_DMA_IRQn, \
|
||||
.irq_prio = UART1_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART1_RXTO_CONFIG
|
||||
#define UART1_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_1, \
|
||||
.channel = TMR0_CH_A, \
|
||||
.clock = FCG2_PERIPH_TMR0_1, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART1_RXTO_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_TX_CPLT_CONFIG
|
||||
#define UART1_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART1_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART1_TX_CPLT_CONFIG
|
||||
#define UART1_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART1_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART1_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||
.channel = UART1_TX_DMA_CHANNEL, \
|
||||
.clock = UART1_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART1_TI, \
|
||||
.flag = UART1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART1_TX_DMA_IRQn, \
|
||||
.irq_prio = UART1_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART1_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = CM_USART2, \
|
||||
.clock = FCG3_PERIPH_USART2, \
|
||||
.irq_num = BSP_UART2_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART2_EI, \
|
||||
.rx_int_src = INT_SRC_USART2_RI, \
|
||||
.tx_int_src = INT_SRC_USART2_TI, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.channel = UART2_RX_DMA_CHANNEL, \
|
||||
.clock = UART2_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART2_RI, \
|
||||
.flag = UART2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART2_RX_DMA_IRQn, \
|
||||
.irq_prio = UART2_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART2_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART2_RXTO_CONFIG
|
||||
#define UART2_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_1, \
|
||||
.channel = TMR0_CH_B, \
|
||||
.clock = FCG2_PERIPH_TMR0_1, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART2_RXTO_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_TX_CPLT_CONFIG
|
||||
#define UART2_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART2_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART2_TX_CPLT_CONFIG
|
||||
#define UART2_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART2_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART2_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||
.channel = UART2_TX_DMA_CHANNEL, \
|
||||
.clock = UART2_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART2_TI, \
|
||||
.flag = UART2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART2_TX_DMA_IRQn, \
|
||||
.irq_prio = UART2_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART2_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART2_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = CM_USART3, \
|
||||
.clock = FCG3_PERIPH_USART3, \
|
||||
.irq_num = BSP_UART3_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART3_EI, \
|
||||
.rx_int_src = INT_SRC_USART3_RI, \
|
||||
.tx_int_src = INT_SRC_USART3_TI, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#ifndef UART3_DMA_RX_CONFIG
|
||||
#define UART3_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||
.channel = UART3_RX_DMA_CHANNEL, \
|
||||
.clock = UART3_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART3_RI, \
|
||||
.flag = UART3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART3_RX_DMA_IRQn, \
|
||||
.irq_prio = UART3_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART3_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART3_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART3_RXTO_CONFIG
|
||||
#define UART3_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_2, \
|
||||
.channel = TMR0_CH_B, \
|
||||
.clock = FCG2_PERIPH_TMR0_2, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART3_RXTO_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_TX_CPLT_CONFIG
|
||||
#define UART3_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART3_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART3_TX_CPLT_CONFIG
|
||||
#define UART3_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART3_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART3_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_DMA_TX_CONFIG
|
||||
#define UART3_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_TX_DMA_INSTANCE, \
|
||||
.channel = UART3_TX_DMA_CHANNEL, \
|
||||
.clock = UART3_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART3_TI, \
|
||||
.flag = UART3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART3_TX_DMA_IRQn, \
|
||||
.irq_prio = UART3_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART3_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART3_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART3_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = CM_USART4, \
|
||||
.clock = FCG3_PERIPH_USART4, \
|
||||
.irq_num = BSP_UART4_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART4_EI, \
|
||||
.rx_int_src = INT_SRC_USART4_RI, \
|
||||
.tx_int_src = INT_SRC_USART4_TI, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#ifndef UART4_DMA_RX_CONFIG
|
||||
#define UART4_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||
.channel = UART4_RX_DMA_CHANNEL, \
|
||||
.clock = UART4_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART4_RI, \
|
||||
.flag = UART4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART4_RX_DMA_IRQn, \
|
||||
.irq_prio = UART4_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART4_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART4_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART4_RXTO_CONFIG
|
||||
#define UART4_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_2, \
|
||||
.channel = TMR0_CH_B, \
|
||||
.clock = FCG2_PERIPH_TMR0_2, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART4_RXTO_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_TX_CPLT_CONFIG
|
||||
#define UART4_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART4_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART4_TX_CPLT_CONFIG
|
||||
#define UART4_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART4_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART4_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_DMA_TX_CONFIG
|
||||
#define UART4_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_TX_DMA_INSTANCE, \
|
||||
.channel = UART4_TX_DMA_CHANNEL, \
|
||||
.clock = UART4_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART4_TI, \
|
||||
.flag = UART4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART4_TX_DMA_IRQn, \
|
||||
.irq_prio = UART4_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART4_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART4_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART4_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
38
bsp/hc32/ev_hc32f334_lqfp64/board/drv_config.h
Normal file
38
bsp/hc32/ev_hc32f334_lqfp64/board/drv_config.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dma_config.h"
|
||||
#include "uart_config.h"
|
||||
#include "spi_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "dac_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "mcan_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "pulse_encoder_config.h"
|
||||
#include "timer_config.h"
|
||||
#include "tmr_capture_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
127
bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h
Normal file
127
bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h
Normal file
@@ -0,0 +1,127 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file template/source/hc32f3xx_conf.h
|
||||
* @brief This file contains HC32 Series Device Driver Library usage management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2024-01-15 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F3XX_CONF_H__
|
||||
#define __HC32F3XX_CONF_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the Device Driver Library.
|
||||
* Select the modules you need to use to DDL_ON.
|
||||
* @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
* properly.
|
||||
* @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
* Library.
|
||||
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
*/
|
||||
#define LL_ICG_ENABLE (DDL_ON)
|
||||
#define LL_UTILITY_ENABLE (DDL_ON)
|
||||
#define LL_PRINT_ENABLE (DDL_OFF)
|
||||
|
||||
#define LL_ADC_ENABLE (DDL_ON)
|
||||
#define LL_AOS_ENABLE (DDL_ON)
|
||||
#define LL_CLK_ENABLE (DDL_ON)
|
||||
#define LL_CMP_ENABLE (DDL_ON)
|
||||
#define LL_CRC_ENABLE (DDL_ON)
|
||||
#define LL_CTC_ENABLE (DDL_ON)
|
||||
#define LL_DAC_ENABLE (DDL_ON)
|
||||
#define LL_DBGC_ENABLE (DDL_OFF)
|
||||
#define LL_DMA_ENABLE (DDL_ON)
|
||||
#define LL_EFM_ENABLE (DDL_ON)
|
||||
#define LL_EMB_ENABLE (DDL_ON)
|
||||
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define LL_FCG_ENABLE (DDL_ON)
|
||||
#define LL_FCM_ENABLE (DDL_ON)
|
||||
#define LL_HRPWM_ENABLE (DDL_ON)
|
||||
#define LL_GPIO_ENABLE (DDL_ON)
|
||||
#define LL_I2C_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define LL_MCAN_ENABLE (DDL_ON)
|
||||
#define LL_MPU_ENABLE (DDL_ON)
|
||||
#define LL_PLA_ENABLE (DDL_ON)
|
||||
#define LL_PWC_ENABLE (DDL_ON)
|
||||
#define LL_RMU_ENABLE (DDL_ON)
|
||||
#define LL_RTC_ENABLE (DDL_ON)
|
||||
#define LL_SPI_ENABLE (DDL_ON)
|
||||
#define LL_SRAM_ENABLE (DDL_ON)
|
||||
#define LL_SWDT_ENABLE (DDL_ON)
|
||||
#define LL_TMR0_ENABLE (DDL_ON)
|
||||
#define LL_TMR4_ENABLE (DDL_ON)
|
||||
#define LL_TMR6_ENABLE (DDL_ON)
|
||||
#define LL_TMRA_ENABLE (DDL_ON)
|
||||
#define LL_USART_ENABLE (DDL_ON)
|
||||
#define LL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F334_LQFP64 (1U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to 0U.
|
||||
*/
|
||||
#define BSP_EV_HC32F3XX (0U)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
* Select the components you need to use to DDL_ON.
|
||||
*/
|
||||
#define BSP_24CXX_ENABLE (DDL_OFF)
|
||||
#define BSP_W25QXX_ENABLE (DDL_OFF)
|
||||
#define BSP_INT_KEY_ENABLE (DDL_OFF)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F3XX_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
111
bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf
Normal file
111
bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf
Normal file
@@ -0,0 +1,111 @@
|
||||
/***************************************************************************//**
|
||||
* \file HC32F334.icf
|
||||
* \version 1.0
|
||||
*
|
||||
* \brief Linker file for the IAR compiler.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*******************************************************************************/
|
||||
/*###ICF### Section handled by ICF editor, don't touch! *****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
|
||||
// Check that necessary symbols have been passed to linker via command line interface
|
||||
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
|
||||
error "Link location not defined or not supported!";
|
||||
}
|
||||
if((!isdefinedsymbol(_HC32F334_128K_)) && (!isdefinedsymbol(_HC32F334_64K_))) {
|
||||
error "Mcu type or size not defined or not supported!";
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory address and size definitions
|
||||
******************************************************************************/
|
||||
define symbol ram1_base_address = 0x1FFFC000;
|
||||
define symbol ram1_end_address = 0x20003FFF;
|
||||
|
||||
if(isdefinedsymbol(_LINK_RAM_)) {
|
||||
define symbol ram_start_reserve = 0x4000;
|
||||
define symbol rom1_base_address = ram1_base_address;
|
||||
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
define symbol rom3_base_address = 0x0;
|
||||
define symbol rom3_end_address = 0x0;
|
||||
} else {
|
||||
define symbol ram_start_reserve = 0x0;
|
||||
define symbol rom1_base_address = 0x0;
|
||||
define symbol rom3_base_address = 0x03000C00;
|
||||
define symbol rom3_end_address = 0x03000FFF;
|
||||
if(isdefinedsymbol(_HC32F334_128K_)) {
|
||||
define symbol rom1_end_address = 0x0001FFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else if (isdefinedsymbol(_HC32F334_64K_)) {
|
||||
define symbol rom1_end_address = 0x0000FFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
|
||||
define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
|
||||
define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory definitions
|
||||
******************************************************************************/
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in OTP_region { readonly section .otp_data };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
288
bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.ld
Normal file
288
bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.ld
Normal file
@@ -0,0 +1,288 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/* File HC32F334xA.ld */
|
||||
/* Abstract Linker script for HC32F334 Device with */
|
||||
/* 128KByte FLASH, 68KByte RAM */
|
||||
/* Version V1.0 */
|
||||
/* Date 2024-01-15 */
|
||||
/*****************************************************************************/
|
||||
/* OTP section(not flash multiplexed region) implementation.
|
||||
You need to pay attention to the size of the specified OTP block.
|
||||
Take two OTP blocks for example. */
|
||||
__OTP_DATA_BASE = 0x03000C00;
|
||||
__OTP_LOCK_BASE = 0x03000A80;
|
||||
/* OTP block 1 */
|
||||
__OTP_DATA_B1_START = 0x03000C00;
|
||||
__OTP_LOCK_B1_START = 0x03000AC0;
|
||||
__OTP_DATA_B1_OFFSET = __OTP_DATA_B1_START - __OTP_DATA_BASE;
|
||||
__OTP_LOCK_B1_OFFSET = __OTP_LOCK_B1_START - __OTP_LOCK_BASE;
|
||||
/* OTP block 2 */
|
||||
__OTP_DATA_B2_START = 0x03000C40;
|
||||
__OTP_LOCK_B2_START = 0x03000AC4;
|
||||
__OTP_DATA_B2_OFFSET = __OTP_DATA_B2_START - __OTP_DATA_BASE;
|
||||
__OTP_LOCK_B2_OFFSET = __OTP_LOCK_B2_START - __OTP_LOCK_BASE;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 128K
|
||||
OTP_DATA (rx): ORIGIN = 0x03000C00, LENGTH = 1K
|
||||
OTP_LOCK (rx): ORIGIN = 0x03000A80, LENGTH = 68
|
||||
RAM (rwx): ORIGIN = 0x1FFFC000, LENGTH = 32K
|
||||
RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.icg_sec 0x00000400 :
|
||||
{
|
||||
KEEP(*(.icg_sec))
|
||||
} >FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} >FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = ORIGIN(OTP_DATA) + __OTP_DATA_B1_OFFSET;
|
||||
KEEP(*(.otp_b1_data*))
|
||||
. = ORIGIN(OTP_DATA) + __OTP_DATA_B2_OFFSET;
|
||||
KEEP(*(.otp_b2_data*))
|
||||
. = ALIGN(4);
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = ORIGIN(OTP_LOCK) + __OTP_LOCK_B1_OFFSET;
|
||||
KEEP(*(.otp_b1_lock*))
|
||||
. = ORIGIN(OTP_LOCK) + __OTP_LOCK_B2_OFFSET;
|
||||
KEEP(*(.otp_b2_lock*))
|
||||
. = ALIGN(4);
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.gnu.linkonce.d*)
|
||||
. = ALIGN(4);
|
||||
*(.ramfunc)
|
||||
*(.ramfunc*)
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .;
|
||||
} >RAM
|
||||
|
||||
.heap_stack (COPY) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
*(.heap*)
|
||||
. = ALIGN(8);
|
||||
__HeapLimit = .;
|
||||
|
||||
__StackLimit = .;
|
||||
*(.stack*)
|
||||
. = ALIGN(8);
|
||||
__StackTop = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ramb_data : AT (__etext_ramb)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ramb__ = .;
|
||||
*(.ramb_data)
|
||||
*(.ramb_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ramb__ = .;
|
||||
} >RAMB
|
||||
|
||||
__bss_start = .;
|
||||
.bss __StackTop (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
. = ALIGN(4);
|
||||
*(.noinit*)
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
__bss_end = .;
|
||||
|
||||
.ramb_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ramb__ = .;
|
||||
*(.ramb_bss)
|
||||
*(.ramb_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ramb__ = .;
|
||||
} >RAMB
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a (*)
|
||||
libm.a (*)
|
||||
libgcc.a (*)
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
PROVIDE(_stack = __StackTop);
|
||||
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
|
||||
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
|
||||
|
||||
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
|
||||
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
22
bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.sct
Normal file
22
bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.sct
Normal file
@@ -0,0 +1,22 @@
|
||||
; ****************************************************************
|
||||
; Scatter-Loading Description File
|
||||
; ****************************************************************
|
||||
LR_IROM1 0x00000000 0x0001FFFF { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x0001FFFF { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFFC000 UNINIT 0x00000008 { ; RW data
|
||||
*(.bss.noinit)
|
||||
}
|
||||
RW_IRAM2 0x1FFFC008 0x00007FF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (RAMCODE)
|
||||
}
|
||||
RW_IRAMB 0x200F0000 0x00001000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
42
bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h
Normal file
42
bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/* enable hc32f3 onchip flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_HC32F3
|
||||
/* enable SFUD flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_SFUD
|
||||
|
||||
extern const struct fal_flash_dev hc32_onchip_flash;
|
||||
extern struct fal_flash_dev ext_nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&hc32_onchip_flash, \
|
||||
&ext_nor_flash0, \
|
||||
}
|
||||
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0}, \
|
||||
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
BIN
bsp/hc32/ev_hc32f334_lqfp64/figures/board.png
Normal file
BIN
bsp/hc32/ev_hc32f334_lqfp64/figures/board.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 7.5 MiB |
@@ -0,0 +1,84 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F334"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="10000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/packages/hc32-f3-cmsis-latest/Device/HDSC/hc32f334/Source/GCC/svd/HC32F334.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/project"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
|
||||
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
|
||||
<stringAttribute key="org.eclipse.embedcdt.debug.gdbjtag.core.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
2974
bsp/hc32/ev_hc32f334_lqfp64/project.ewd
Normal file
2974
bsp/hc32/ev_hc32f334_lqfp64/project.ewd
Normal file
File diff suppressed because it is too large
Load Diff
2303
bsp/hc32/ev_hc32f334_lqfp64/project.ewp
Normal file
2303
bsp/hc32/ev_hc32f334_lqfp64/project.ewp
Normal file
File diff suppressed because it is too large
Load Diff
10
bsp/hc32/ev_hc32f334_lqfp64/project.eww
Normal file
10
bsp/hc32/ev_hc32f334_lqfp64/project.eww
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
179
bsp/hc32/ev_hc32f334_lqfp64/project.uvoptx
Normal file
179
bsp/hc32/ev_hc32f334_lqfp64/project.uvoptx
Normal file
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFFC000 -FC4000 -FN2 -FF0HC32F334_128K -FS00 -FL020000 -FP0($$Device:HC32F334KATI$FlashARM\HC32F334_128K.FLM) -FF1HC32F334_otp -FS13000000 -FL11800 -FP1($$Device:HC32F334KATI$FlashARM\HC32F334_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
1368
bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx
Normal file
1368
bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx
Normal file
File diff suppressed because it is too large
Load Diff
438
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h
Normal file
438
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h
Normal file
@@ -0,0 +1,438 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice options */
|
||||
|
||||
/* end of kservice options */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart2"
|
||||
#define RT_VER_NUM 0x50201
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_M4
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
|
||||
/* WCH HAL & SDK Drivers */
|
||||
|
||||
/* end of WCH HAL & SDK Drivers */
|
||||
|
||||
/* AT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of AT32 HAL & SDK Drivers */
|
||||
|
||||
/* HC32 DDL Drivers */
|
||||
|
||||
#define PKG_USING_HC32F3_CMSIS_DRIVER
|
||||
#define PKG_USING_HC32F3_CMSIS_DRIVER_LATEST_VERSION
|
||||
#define PKG_USING_HC32F3_SERIES_DRIVER
|
||||
#define PKG_USING_HC32F3_SERIES_DRIVER_LATEST_VERSION
|
||||
/* end of HC32 DDL Drivers */
|
||||
|
||||
/* NXP HAL & SDK Drivers */
|
||||
|
||||
/* end of NXP HAL & SDK Drivers */
|
||||
|
||||
/* NUVOTON Drivers */
|
||||
|
||||
/* end of NUVOTON Drivers */
|
||||
|
||||
/* GD32 Drivers */
|
||||
|
||||
/* end of GD32 Drivers */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
#define SOC_FAMILY_HC32
|
||||
#define SOC_SERIES_HC32F3
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_HC32F334KA
|
||||
|
||||
/* On-chip Drivers */
|
||||
|
||||
#define BSP_USING_ON_CHIP_FLASH_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
|
||||
/* end of On-chip Drivers */
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* end of Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART2
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_I2C_HW
|
||||
#define BSP_USING_I2C1
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
150
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py
Normal file
150
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py
Normal file
@@ -0,0 +1,150 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
else:
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
1927
bsp/hc32/ev_hc32f334_lqfp64/template.ewp
Normal file
1927
bsp/hc32/ev_hc32f334_lqfp64/template.ewp
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user