mirror of
https://github.com/RT-Thread/rt-thread.git
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Add ev_hc32f334_lqfp64 board and update package relation. #10522
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This commit is contained in:
Jamie
@@ -47,6 +47,7 @@
|
||||
"at32/at32m416-start",
|
||||
"hc32/ev_hc32f4a0_lqfp176",
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||||
"hc32/ev_hc32f4a8_lqfp176",
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||||
"hc32/ev_hc32f334_lqfp64",
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||||
"hc32/ev_hc32f448_lqfp80",
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||||
"hc32/ev_hc32f460_lqfp100_v2",
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||||
"hc32/ev_hc32f472_lqfp100",
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||||
|
||||
@@ -87,6 +87,10 @@ tag: bsp_gd32e503v-eval
|
||||
path: bsp/gd32/arm/gd32e503v-eval
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||||
owners: 蒙蒙plus(meng-plus)<chengmeng_2@outlook.com>
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|
||||
tag: bsp_hc32
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||||
path: bsp/hc32
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||||
owners: Levi Zhang(levizh)<levizhangxl@gmail.com>
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||||
|
||||
tag: bsp_k230
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||||
path: bsp/k230
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||||
owners: Chen Wang(unicornx)<unicorn_wang@outlook.com>
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||||
|
||||
@@ -0,0 +1,7 @@
|
||||
devices.gpio:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_GPIO=y
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||||
devices.uart:
|
||||
kconfig:
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||||
- CONFIG_BSP_USING_UART=y
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||||
- CONFIG_BSP_USING_UART2=y
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||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,42 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
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||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
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||||
settings/
|
||||
*.uvguix*
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||||
cconfig.h
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||||
@@ -0,0 +1,78 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<projectDescription>
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||||
<name>project</name>
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||||
<comment />
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>rt-thread</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/libcpu</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/libraries</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/platform</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/tests</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,12 @@
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||||
mainmenu "RT-Thread Configuration"
|
||||
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||||
BSP_DIR := .
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||||
|
||||
RTT_DIR := ../../..
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||||
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||||
PKGS_DIR := packages
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||||
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||||
source "$(RTT_DIR)/Kconfig"
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||||
osource "$PKGS_DIR/Kconfig"
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rsource "../libraries/Kconfig"
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rsource "board/Kconfig"
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||||
@@ -0,0 +1,140 @@
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||||
# XHSC EV_F334_LQ64_Rev1.0 开发板 BSP 说明
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||||
|
||||
## 简介
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||||
|
||||
本文档为小华半导体为 EV_F334_LQ64_Rev1.0 开发板提供的 BSP (板级支持包) 说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
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||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
EV_F334_LQ64_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F334MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F334MCTI 的芯片性能。
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
EV_F334_LQ64_Rev1.0 开发板常用 **板载资源** 如下：
|
||||
|
||||
- **MCU**
|
||||
- HC32F334MCTI
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||||
- 主频200MHz
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||||
- 256KB FLASH
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||||
- 68KB RAM
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||||
- **外部Memory**
|
||||
- BL24C256（EEPROM, 256Kbits）
|
||||
- W25Q64（SPI NOR，64MB）
|
||||
- IS62WV51216（SRAM， 1MB）
|
||||
- **常用外设**
|
||||
- LED: 4 个，User LED（LED0，LED1，LED2，LED3）。
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||||
- 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0）
|
||||
- **常用接口**
|
||||
- USB转串口
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||||
- CAN DB9接口 * 2
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||||
- TFT接口
|
||||
- SmartCard接口
|
||||
- I2C/USART/SPI接口
|
||||
- **调试接口**
|
||||
- 板载DAP调试器
|
||||
- 标准JTAG/SWD/Trace
|
||||
|
||||
开发板更多详细信息请参考小华半导体半导体[EV_F334_LQ64_Rev1.0](https://www.xhsc.com.cn)
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
|:-------- |:--------:|:--------:|
|
||||
| USB 转串口 | 支持 | 使用 UART2 |
|
||||
| LED | 支持 | LED1~4 |
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
|:------------- |:--------:|:------------------------------------------:|
|
||||
| Crypto | 支持 | AES, CRC, HASH, RNG, UID |
|
||||
| DAC | 支持 | |
|
||||
| ADC | 支持 | ADC1: CH10, CH11, <br>ADC3: CH1 |
|
||||
| CAN | 支持 | CAN1、CAN2 |
|
||||
| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
|
||||
| I2C | 支持 | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
|
||||
| PM | 支持 | |
|
||||
| Lptimer | 支持 | |
|
||||
| Hwtimer | 支持 | Hwtimer1~5 |
|
||||
| Pulse_encoder | 支持 | |
|
||||
| PWM | 支持 | |
|
||||
| RTC | 支持 | 闹钟精度为1分钟 |
|
||||
| WDT | 支持 | |
|
||||
| I2C | 支持 | 软件、硬件 I2C |
|
||||
| QSPI | 支持 | |
|
||||
| SPI | 支持 | SPI1~3<br>SPI1支持W25Q |
|
||||
| UART | 支持 | UART1~6<br>UART2为console使用 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用Type-A to MircoUSB线连接开发板和PC供电。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。
|
||||
|
||||
USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.0.1 build Feb 4 2024 16:44:26
|
||||
2006 - 2022 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
| 板载外设 | 模式 | 注意事项 |
|
||||
| ---- | ---- | ------------------------------------------------------------------------------------------------------ |
|
||||
| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
|
||||
@@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,83 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "hc32-f3-cmsis-latest"),
|
||||
os.path.join("packages", "hc32-f3-series-latest")
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
# include platform
|
||||
platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
|
||||
objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
|
||||
|
||||
# include tests
|
||||
test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
|
||||
objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-07-10 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED_BLUE pin: PC13 */
|
||||
#define LED_BLUE_PIN GET_PIN(C, 13)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED_BLUE_PIN pin mode to output */
|
||||
rt_pin_mode(LED_BLUE_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_BLUE_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_BLUE_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
#define XTAL32_FCM_UNIT (CM_FCM)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,19 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
|
||||
CPPDEFINES = ['HC32F334', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "board_config.h"
|
||||
|
||||
/* unlock/lock peripheral */
|
||||
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
/** System Base Configuration
|
||||
*/
|
||||
void SystemBase_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
|
||||
EFM_ICacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
|
||||
EFM_DCacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
|
||||
EFM_PrefetchCmd(ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
stc_clock_xtal_init_t stcXtalInit;
|
||||
stc_clock_pll_init_t stcPLLHInit;
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
stc_clock_xtal32_init_t stcXtal32Init;
|
||||
#endif
|
||||
#if defined(BSP_RTC_USING_XTAL_DIV)
|
||||
stc_clock_xtaldiv_init_t stcXtaldivInit;
|
||||
#endif
|
||||
|
||||
/* PCLK0, HCLK Max 120MHz */
|
||||
/* PCLK1, PCLK2, PCLK3, PCLK4 Max 60MHz */
|
||||
CLK_SetClockDiv(CLK_BUS_CLK_ALL,
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV2 |
|
||||
CLK_PCLK3_DIV2 | CLK_PCLK4_DIV2 | CLK_HCLK_DIV1));
|
||||
|
||||
|
||||
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
|
||||
(void)CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||||
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||||
stcXtalInit.u8State = CLK_XTAL_ON;
|
||||
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||||
(void)CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*60 = 480MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 60UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||||
(void)CLK_PLLInit(&stcPLLHInit);
|
||||
|
||||
/* 2 cycles for 100 ~ 120MHz */
|
||||
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE2);
|
||||
/* 2 cycles for 100 ~ 120MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_RD_WAIT2);
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
/* Xtal32 config */
|
||||
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
|
||||
(void)CLK_Xtal32StructInit(&stcXtal32Init);
|
||||
stcXtal32Init.u8State = CLK_XTAL32_ON;
|
||||
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
|
||||
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
|
||||
(void)CLK_Xtal32Init(&stcXtal32Init);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL_DIV)
|
||||
/* Xtal Div config */
|
||||
(void)CLK_XtalDivStructInit(&stcXtaldivInit);
|
||||
/* 8000000Hz / 32768Hz = 0x7A12 / 0x80 */
|
||||
stcXtaldivInit.u32Num = 0x7A12UL;
|
||||
stcXtaldivInit.u32Den = 0x80UL;
|
||||
stcXtaldivInit.u32State = CLK_XTALDIV_ON;
|
||||
(void)CLK_XtalDivInit(&stcXtaldivInit);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Clock Configuration
|
||||
*/
|
||||
void PeripheralClock_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
CLK_SetCANClockSrc(CLK_MCAN1, CLK_MCANCLK_SYSCLK_DIV3);
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
CLK_SetCANClockSrc(CLK_MCAN2, CLK_MCANCLK_SYSCLK_DIV3);
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Registers Unlock
|
||||
*/
|
||||
void PeripheralRegister_Unlock(void)
|
||||
{
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (128 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (32)
|
||||
#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_INIT_PARAMS
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC1_USING_DMA)
|
||||
#ifndef ADC1_EOCA_DMA_CONFIG
|
||||
#define ADC1_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC1_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC1_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC1_EOCA, \
|
||||
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC1_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC1_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC1_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC1_USING_DMA */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_INIT_PARAMS
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC2_USING_DMA)
|
||||
#ifndef ADC2_EOCA_DMA_CONFIG
|
||||
#define ADC2_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC2_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC2_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC2_EOCA, \
|
||||
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC2_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC2_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC2_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC2_USING_DMA */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_INIT_PARAMS
|
||||
#define ADC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC3_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC3_USING_DMA)
|
||||
#ifndef ADC3_EOCA_DMA_CONFIG
|
||||
#define ADC3_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC3_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC3_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC3_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC3_EOCA, \
|
||||
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC3_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC3_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC3_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC3_USING_DMA */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
.vref = 3300, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
@@ -0,0 +1,191 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DMA_CONFIG_H__
|
||||
#define __DMA_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#define UART1_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART1_TX_DMA_CHANNEL DMA_CH0
|
||||
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0
|
||||
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
|
||||
|
||||
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_TX_DMA_INSTANCE CM_DMA
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CH0
|
||||
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0
|
||||
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
|
||||
#endif
|
||||
|
||||
/* DMA1 ch1 */
|
||||
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CH1
|
||||
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1
|
||||
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
|
||||
|
||||
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_RX_DMA_INSTANCE CM_DMA
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CH1
|
||||
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1
|
||||
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
|
||||
#endif
|
||||
|
||||
/* DMA1 ch2 */
|
||||
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
|
||||
#define UART2_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART2_TX_DMA_CHANNEL DMA_CH2
|
||||
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2
|
||||
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2
|
||||
|
||||
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
|
||||
#define I2C1_TX_DMA_INSTANCE CM_DMA
|
||||
#define I2C1_TX_DMA_CHANNEL DMA_CH2
|
||||
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2
|
||||
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2
|
||||
#endif
|
||||
|
||||
/* DMA1 ch3 */
|
||||
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
|
||||
#define UART2_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART2_RX_DMA_CHANNEL DMA_CH3
|
||||
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3
|
||||
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3
|
||||
|
||||
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
|
||||
#define I2C1_RX_DMA_INSTANCE CM_DMA
|
||||
#define I2C1_RX_DMA_CHANNEL DMA_CH3
|
||||
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3
|
||||
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3
|
||||
#endif
|
||||
|
||||
/* DMA1 ch4 */
|
||||
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
|
||||
#define UART3_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART3_TX_DMA_CHANNEL DMA_CH4
|
||||
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4
|
||||
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4
|
||||
|
||||
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
|
||||
#define ADC1_EOCA_DMA_INSTANCE CM_DMA
|
||||
#define ADC1_EOCA_DMA_CHANNEL DMA_CH4
|
||||
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4
|
||||
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4
|
||||
#endif
|
||||
|
||||
/* DMA1 ch5 */
|
||||
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
|
||||
#define UART3_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART3_RX_DMA_CHANNEL DMA_CH5
|
||||
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5
|
||||
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5
|
||||
|
||||
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
|
||||
#define ADC2_EOCA_DMA_INSTANCE CM_DMA
|
||||
#define ADC2_EOCA_DMA_CHANNEL DMA_CH5
|
||||
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5
|
||||
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5
|
||||
#endif
|
||||
|
||||
/* DMA1 ch6 */
|
||||
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
|
||||
#define UART4_TX_DMA_INSTANCE CM_DMA
|
||||
#define UART4_TX_DMA_CHANNEL DMA_CH6
|
||||
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6
|
||||
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6
|
||||
|
||||
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
|
||||
#define ADC3_EOCA_DMA_INSTANCE CM_DMA
|
||||
#define ADC3_EOCA_DMA_CHANNEL DMA_CH6
|
||||
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6
|
||||
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6
|
||||
#endif
|
||||
|
||||
/* DMA1 ch7 */
|
||||
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
||||
#define UART4_RX_DMA_INSTANCE CM_DMA
|
||||
#define UART4_RX_DMA_CHANNEL DMA_CH7
|
||||
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
|
||||
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7
|
||||
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
|
||||
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
|
||||
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_CONFIG_H__
|
||||
#define __GPIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#ifndef EXTINT0_IRQ_CONFIG
|
||||
#define EXTINT0_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT0_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ0, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT1_IRQ_CONFIG
|
||||
#define EXTINT1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT1_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ1, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT2_IRQ_CONFIG
|
||||
#define EXTINT2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT2_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ2, \
|
||||
}
|
||||
#endif /* EXTINT2_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT3_IRQ_CONFIG
|
||||
#define EXTINT3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT3_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ3, \
|
||||
}
|
||||
#endif /* EXTINT3_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT4_IRQ_CONFIG
|
||||
#define EXTINT4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT4_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ4, \
|
||||
}
|
||||
#endif /* EXTINT4_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT5_IRQ_CONFIG
|
||||
#define EXTINT5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT5_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ5, \
|
||||
}
|
||||
#endif /* EXTINT5_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT6_IRQ_CONFIG
|
||||
#define EXTINT6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT6_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ6, \
|
||||
}
|
||||
#endif /* EXTINT6_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT7_IRQ_CONFIG
|
||||
#define EXTINT7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT7_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ7, \
|
||||
}
|
||||
#endif /* EXTINT7_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT8_IRQ_CONFIG
|
||||
#define EXTINT8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT8_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ8, \
|
||||
}
|
||||
#endif /* EXTINT8_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT9_IRQ_CONFIG
|
||||
#define EXTINT9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT9_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ9, \
|
||||
}
|
||||
#endif /* EXTINT9_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT10_IRQ_CONFIG
|
||||
#define EXTINT10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT10_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ10, \
|
||||
}
|
||||
#endif /* EXTINT10_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT11_IRQ_CONFIG
|
||||
#define EXTINT11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT11_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ11, \
|
||||
}
|
||||
#endif /* EXTINT11_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT12_IRQ_CONFIG
|
||||
#define EXTINT12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT12_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ12, \
|
||||
}
|
||||
#endif /* EXTINT12_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT13_IRQ_CONFIG
|
||||
#define EXTINT13_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT13_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ13, \
|
||||
}
|
||||
#endif /* EXTINT13_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT14_IRQ_CONFIG
|
||||
#define EXTINT14_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT14_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ14, \
|
||||
}
|
||||
#endif /* EXTINT14_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT15_IRQ_CONFIG
|
||||
#define EXTINT15_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT15_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ15, \
|
||||
}
|
||||
#endif /* EXTINT15_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_CONFIG_H__ */
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_CONFIG_H__
|
||||
#define __I2C_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#ifndef I2C1_CONFIG
|
||||
#define I2C1_CONFIG \
|
||||
{ \
|
||||
.name = "i2c1", \
|
||||
.Instance = CM_I2C, \
|
||||
.clock = FCG1_PERIPH_I2C, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C1_CONFIG */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_I2C1_USING_DMA)
|
||||
#ifndef I2C1_TX_DMA_CONFIG
|
||||
#define I2C1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_TX_DMA_INSTANCE, \
|
||||
.channel = I2C1_TX_DMA_CHANNEL, \
|
||||
.clock = I2C1_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C_TEI, \
|
||||
.flag = I2C1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C1_RX_DMA_CONFIG
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
||||
.channel = I2C1_RX_DMA_CHANNEL, \
|
||||
.clock = I2C1_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C_RXI, \
|
||||
.flag = I2C1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C1_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PM_CONFIG_H__
|
||||
#define __PM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PM
|
||||
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
|
||||
|
||||
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
|
||||
#define PM_TICKLESS_TIMER_ENABLE_MASK \
|
||||
( (1UL << PM_SLEEP_MODE_IDLE) | \
|
||||
(1UL << PM_SLEEP_MODE_DEEP))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief run mode config @ref pm_run_mode_config structure
|
||||
*/
|
||||
#ifndef PM_RUN_MODE_CFG
|
||||
#define PM_RUN_MODE_CFG \
|
||||
{ \
|
||||
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
|
||||
}
|
||||
#endif /* PM_RUN_MODE_CFG */
|
||||
|
||||
/**
|
||||
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_IDLE_CFG
|
||||
#define PM_SLEEP_IDLE_CFG \
|
||||
{ \
|
||||
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_IDLE_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_DEEP_CFG
|
||||
#define PM_SLEEP_DEEP_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u16Clock = PWC_STOP_CLK_KEEP, \
|
||||
.u8StopDrv = PWC_STOP_DRV_HIGH, \
|
||||
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
|
||||
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
|
||||
}, \
|
||||
.pwc_stop_type = PWC_STOP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_DEEP_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_STANDBY_CFG
|
||||
#define PM_SLEEP_STANDBY_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD1, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_STANDBY_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_SHUTDOWN_CFG
|
||||
#define PM_SLEEP_SHUTDOWN_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD3, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
|
||||
|
||||
#endif /* BSP_USING_PM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PM_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI, \
|
||||
.bus_name = "spi1", \
|
||||
.clock = FCG1_PERIPH_SPI, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.channel = SPI1_TX_DMA_CHANNEL, \
|
||||
.clock = SPI1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI_SPTI, \
|
||||
.flag = SPI1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.channel = SPI1_RX_DMA_CHANNEL, \
|
||||
.clock = SPI1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI_SPRI, \
|
||||
.flag = SPI1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TMR_CONFIG_H__
|
||||
#define __TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TMRA_1
|
||||
#ifndef TMRA_1_CONFIG
|
||||
#define TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_1, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_1, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_1" \
|
||||
}
|
||||
#endif /* TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_2
|
||||
#ifndef TMRA_2_CONFIG
|
||||
#define TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_2, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_2, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_2" \
|
||||
}
|
||||
#endif /* TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_3
|
||||
#ifndef TMRA_3_CONFIG
|
||||
#define TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_3, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_3, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_3" \
|
||||
}
|
||||
#endif /* TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_4
|
||||
#ifndef TMRA_4_CONFIG
|
||||
#define TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_4, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_4, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_4" \
|
||||
}
|
||||
#endif /* TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_5
|
||||
#ifndef TMRA_5_CONFIG
|
||||
#define TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_5, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_5, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_5" \
|
||||
}
|
||||
#endif /* TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_5 */
|
||||
#endif /* __TMR_CONFIG_H__ */
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-01-10 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __IC_CONFIG_H__
|
||||
#define __IC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
#define IC1_NAME "ic1"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_1 \
|
||||
{ \
|
||||
.name = IC1_NAME, \
|
||||
.ch = TMR6_CH_A, \
|
||||
.clk_div = TMR6_CLK_DIV32, \
|
||||
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
#define IC2_NAME "ic2"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_2 \
|
||||
{ \
|
||||
.name = IC2_NAME, \
|
||||
.ch = TMR6_CH_A, \
|
||||
.clk_div = TMR6_CLK_DIV32, \
|
||||
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
#define IC3_NAME "ic3"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_3 \
|
||||
{ \
|
||||
.name = IC3_NAME, \
|
||||
.ch = TMR6_CH_B, \
|
||||
.clk_div = TMR6_CLK_DIV16, \
|
||||
.first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IC_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dma_config.h"
|
||||
#include "uart_config.h"
|
||||
#include "spi_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "dac_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "mcan_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "pulse_encoder_config.h"
|
||||
#include "timer_config.h"
|
||||
#include "tmr_capture_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,127 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file template/source/hc32f3xx_conf.h
|
||||
* @brief This file contains HC32 Series Device Driver Library usage management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2024-01-15 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F3XX_CONF_H__
|
||||
#define __HC32F3XX_CONF_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the Device Driver Library.
|
||||
* Select the modules you need to use to DDL_ON.
|
||||
* @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
* properly.
|
||||
* @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
* Library.
|
||||
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
*/
|
||||
#define LL_ICG_ENABLE (DDL_ON)
|
||||
#define LL_UTILITY_ENABLE (DDL_ON)
|
||||
#define LL_PRINT_ENABLE (DDL_OFF)
|
||||
|
||||
#define LL_ADC_ENABLE (DDL_ON)
|
||||
#define LL_AOS_ENABLE (DDL_ON)
|
||||
#define LL_CLK_ENABLE (DDL_ON)
|
||||
#define LL_CMP_ENABLE (DDL_ON)
|
||||
#define LL_CRC_ENABLE (DDL_ON)
|
||||
#define LL_CTC_ENABLE (DDL_ON)
|
||||
#define LL_DAC_ENABLE (DDL_ON)
|
||||
#define LL_DBGC_ENABLE (DDL_OFF)
|
||||
#define LL_DMA_ENABLE (DDL_ON)
|
||||
#define LL_EFM_ENABLE (DDL_ON)
|
||||
#define LL_EMB_ENABLE (DDL_ON)
|
||||
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define LL_FCG_ENABLE (DDL_ON)
|
||||
#define LL_FCM_ENABLE (DDL_ON)
|
||||
#define LL_HRPWM_ENABLE (DDL_ON)
|
||||
#define LL_GPIO_ENABLE (DDL_ON)
|
||||
#define LL_I2C_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define LL_MCAN_ENABLE (DDL_ON)
|
||||
#define LL_MPU_ENABLE (DDL_ON)
|
||||
#define LL_PLA_ENABLE (DDL_ON)
|
||||
#define LL_PWC_ENABLE (DDL_ON)
|
||||
#define LL_RMU_ENABLE (DDL_ON)
|
||||
#define LL_RTC_ENABLE (DDL_ON)
|
||||
#define LL_SPI_ENABLE (DDL_ON)
|
||||
#define LL_SRAM_ENABLE (DDL_ON)
|
||||
#define LL_SWDT_ENABLE (DDL_ON)
|
||||
#define LL_TMR0_ENABLE (DDL_ON)
|
||||
#define LL_TMR4_ENABLE (DDL_ON)
|
||||
#define LL_TMR6_ENABLE (DDL_ON)
|
||||
#define LL_TMRA_ENABLE (DDL_ON)
|
||||
#define LL_USART_ENABLE (DDL_ON)
|
||||
#define LL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F334_LQFP64 (1U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to 0U.
|
||||
*/
|
||||
#define BSP_EV_HC32F3XX (0U)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
* Select the components you need to use to DDL_ON.
|
||||
*/
|
||||
#define BSP_24CXX_ENABLE (DDL_OFF)
|
||||
#define BSP_W25QXX_ENABLE (DDL_OFF)
|
||||
#define BSP_INT_KEY_ENABLE (DDL_OFF)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F3XX_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,111 @@
|
||||
/***************************************************************************//**
|
||||
* \file HC32F334.icf
|
||||
* \version 1.0
|
||||
*
|
||||
* \brief Linker file for the IAR compiler.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*******************************************************************************/
|
||||
/*###ICF### Section handled by ICF editor, don't touch! *****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
|
||||
// Check that necessary symbols have been passed to linker via command line interface
|
||||
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
|
||||
error "Link location not defined or not supported!";
|
||||
}
|
||||
if((!isdefinedsymbol(_HC32F334_128K_)) && (!isdefinedsymbol(_HC32F334_64K_))) {
|
||||
error "Mcu type or size not defined or not supported!";
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory address and size definitions
|
||||
******************************************************************************/
|
||||
define symbol ram1_base_address = 0x1FFFC000;
|
||||
define symbol ram1_end_address = 0x20003FFF;
|
||||
|
||||
if(isdefinedsymbol(_LINK_RAM_)) {
|
||||
define symbol ram_start_reserve = 0x4000;
|
||||
define symbol rom1_base_address = ram1_base_address;
|
||||
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
define symbol rom3_base_address = 0x0;
|
||||
define symbol rom3_end_address = 0x0;
|
||||
} else {
|
||||
define symbol ram_start_reserve = 0x0;
|
||||
define symbol rom1_base_address = 0x0;
|
||||
define symbol rom3_base_address = 0x03000C00;
|
||||
define symbol rom3_end_address = 0x03000FFF;
|
||||
if(isdefinedsymbol(_HC32F334_128K_)) {
|
||||
define symbol rom1_end_address = 0x0001FFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else if (isdefinedsymbol(_HC32F334_64K_)) {
|
||||
define symbol rom1_end_address = 0x0000FFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
|
||||
define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
|
||||
define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory definitions
|
||||
******************************************************************************/
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in OTP_region { readonly section .otp_data };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,22 @@
|
||||
; ****************************************************************
|
||||
; Scatter-Loading Description File
|
||||
; ****************************************************************
|
||||
LR_IROM1 0x00000000 0x0001FFFF { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x0001FFFF { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFFC000 UNINIT 0x00000008 { ; RW data
|
||||
*(.bss.noinit)
|
||||
}
|
||||
RW_IRAM2 0x1FFFC008 0x00007FF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (RAMCODE)
|
||||
}
|
||||
RW_IRAMB 0x200F0000 0x00001000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/* enable hc32f3 onchip flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_HC32F3
|
||||
/* enable SFUD flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_SFUD
|
||||
|
||||
extern const struct fal_flash_dev hc32_onchip_flash;
|
||||
extern struct fal_flash_dev ext_nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&hc32_onchip_flash, \
|
||||
&ext_nor_flash0, \
|
||||
}
|
||||
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0}, \
|
||||
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 7.5 MiB |
@@ -0,0 +1,84 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
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||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
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<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||
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|
||||
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||||
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|
||||
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|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
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|
||||
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
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|
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|
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F334"/>
|
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="10000"/>
|
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
|
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<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
|
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<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
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<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
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<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
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<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/packages/hc32-f3-cmsis-latest/Device/HDSC/hc32f334/Source/GCC/svd/HC32F334.svd"/>
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<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
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<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
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<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
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||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
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<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
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||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/project"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
|
||||
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
|
||||
<stringAttribute key="org.eclipse.embedcdt.debug.gdbjtag.core.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFFC000 -FC4000 -FN2 -FF0HC32F334_128K -FS00 -FL020000 -FP0($$Device:HC32F334KATI$FlashARM\HC32F334_128K.FLM) -FF1HC32F334_otp -FS13000000 -FL11800 -FP1($$Device:HC32F334KATI$FlashARM\HC32F334_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
else:
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFFC000 -FC4000 -FN2 -FF0HC32F334_128K -FS00 -FL020000 -FP0($$Device:HC32F334KATI$FlashARM\HC32F334_128K.FLM) -FF1HC32F334_otp -FS13000000 -FL11800 -FP1($$Device:HC32F334KATI$FlashARM\HC32F334_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
|
||||
devices.gpio:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_GPIO=y
|
||||
- CONFIG_BSP_USING_I2C=y
|
||||
- CONFIG_BSP_USING_I2C_HW=y
|
||||
- CONFIG_BSP_USING_I2C1=y
|
||||
- CONFIG_BSP_USING_TCA9539=y
|
||||
- CONFIG_BSP_USING_EXT_IO=y
|
||||
devices.uart:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_UART=y
|
||||
- CONFIG_BSP_USING_UART2=y
|
||||
@@ -389,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||
# CONFIG_PKG_USING_NANOPB is not set
|
||||
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
|
||||
# CONFIG_PKG_USING_ESP_HOSTED is not set
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
@@ -633,6 +634,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_ZDEBUG is not set
|
||||
# CONFIG_PKG_USING_RVBACKTRACE is not set
|
||||
# CONFIG_PKG_USING_HPATCHLITE is not set
|
||||
# CONFIG_PKG_USING_THREAD_METRIC is not set
|
||||
# end of tools packages
|
||||
|
||||
#
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -21,7 +21,16 @@ extern "C" {
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
.name = "dac1", \
|
||||
.vref = 3300, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals/> "/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
@@ -41,7 +41,7 @@
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f448/Source/GCC/svd/HC32F448.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f448/Source/IAR/svd/HC32F448.svd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -112,7 +112,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F448xC.board</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f448/Source/IAR/flashloader/FlashHC32F448xC.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
@@ -1529,7 +1529,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f448/Source/IAR/svd/HC32F448.svd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -1597,7 +1597,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F448xC.board</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f448/Source/IAR/flashloader/FlashHC32F448xC.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -33,7 +33,7 @@
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR</SFDFile>
|
||||
<SFDFile>./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f448/Source/ARM/sfr/HC32F448.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
devices.gpio:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_GPIO=y
|
||||
devices.uart:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_UART=y
|
||||
- CONFIG_BSP_USING_UART4=y
|
||||
@@ -389,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||
# CONFIG_PKG_USING_NANOPB is not set
|
||||
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
|
||||
# CONFIG_PKG_USING_ESP_HOSTED is not set
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
@@ -633,6 +634,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_ZDEBUG is not set
|
||||
# CONFIG_PKG_USING_RVBACKTRACE is not set
|
||||
# CONFIG_PKG_USING_HPATCHLITE is not set
|
||||
# CONFIG_PKG_USING_THREAD_METRIC is not set
|
||||
# end of tools packages
|
||||
|
||||
#
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -20,6 +20,7 @@
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
#define XTAL32_FCM_UNIT (CM_FCM)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
@@ -41,24 +42,24 @@ void xtal32_fcm_thread_entry(void *parameter)
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 90UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 110UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
@@ -67,7 +68,7 @@ void xtal32_fcm_thread_entry(void *parameter)
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
@@ -73,9 +73,9 @@ define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC00;
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
@@ -14,20 +14,28 @@
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-03-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
Take OTP sector 0 for example. */
|
||||
__OTP_DATA_START = 0x03000C00;
|
||||
__OTP_DATA_SIZE = 64;
|
||||
__OTP_LOCK_START = 0x03000FC0;
|
||||
__OTP_LOCK_SIZE = 4;
|
||||
/* OTP section implementation.
|
||||
You need to pay attention to the size of the specified OTP block.
|
||||
Take two OTP blocks for example. */
|
||||
__OTP_DATA_BASE = 0x03000C00;
|
||||
__OTP_LOCK_BASE = 0x03000FC0;
|
||||
/* OTP block 0 */
|
||||
__OTP_DATA_B0_START = 0x03000C00;
|
||||
__OTP_LOCK_B0_START = 0x03000FC0;
|
||||
__OTP_DATA_B0_OFFSET = __OTP_DATA_B0_START - __OTP_DATA_BASE;
|
||||
__OTP_LOCK_B0_OFFSET = __OTP_LOCK_B0_START - __OTP_LOCK_BASE;
|
||||
/* OTP block 1 */
|
||||
__OTP_DATA_B1_START = 0x03000C40;
|
||||
__OTP_LOCK_B1_START = 0x03000FC4;
|
||||
__OTP_DATA_B1_OFFSET = __OTP_DATA_B1_START - __OTP_DATA_BASE;
|
||||
__OTP_LOCK_B1_OFFSET = __OTP_LOCK_B1_START - __OTP_LOCK_BASE;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K
|
||||
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
|
||||
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
|
||||
OTP_DATA (rx): ORIGIN = 0x03000C00, LENGTH = 960
|
||||
OTP_LOCK (rx): ORIGIN = 0x03000FC0, LENGTH = 60
|
||||
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
|
||||
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
@@ -138,14 +146,24 @@ SECTIONS
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data_sec :
|
||||
.otp_data :
|
||||
{
|
||||
KEEP(*(.otp_data_sec))
|
||||
. = ALIGN(4);
|
||||
. = ORIGIN(OTP_DATA) + __OTP_DATA_B0_OFFSET;
|
||||
KEEP(*(.otp_b0_data*))
|
||||
. = ORIGIN(OTP_DATA) + __OTP_DATA_B1_OFFSET;
|
||||
KEEP(*(.otp_b1_data*))
|
||||
. = ALIGN(4);
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock_sec :
|
||||
.otp_lock :
|
||||
{
|
||||
KEEP(*(.otp_lock_sec))
|
||||
. = ALIGN(4);
|
||||
. = ORIGIN(OTP_LOCK) + __OTP_LOCK_B0_OFFSET;
|
||||
KEEP(*(.otp_b0_lock*))
|
||||
. = ORIGIN(OTP_LOCK) + __OTP_LOCK_B1_OFFSET;
|
||||
KEEP(*(.otp_b1_lock*))
|
||||
. = ALIGN(4);
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
@@ -180,12 +198,12 @@ SECTIONS
|
||||
} >RAM
|
||||
|
||||
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ramb_data : AT (__etext_ret_ram)
|
||||
.ret_ram_data : AT (__etext_ret_ram)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ret_ram__ = .;
|
||||
*(.ramb_data)
|
||||
*(.ramb_data*)
|
||||
*(.ret_ram_data)
|
||||
*(.ret_ram_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
@@ -208,12 +226,12 @@ SECTIONS
|
||||
} >RAM
|
||||
__bss_end = .;
|
||||
|
||||
.ramb_bss :
|
||||
.ret_ram_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ret_ram__ = .;
|
||||
*(.ramb_bss)
|
||||
*(.ramb_bss*)
|
||||
*(.ret_ram_bss)
|
||||
*(.ret_ram_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
@@ -41,7 +41,7 @@
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F460.svd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f460/Source/GCC/svd/HC32F460.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f460/Source/IAR/debugger/HC32F460xE.ddf</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -88,7 +88,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>OCLastSavedByProductVersion</name>
|
||||
<state>8.50.9.33458</state>
|
||||
<state>8.40.2.22864</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UseFlashLoader</name>
|
||||
@@ -112,7 +112,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460xE.board</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f460/Source/IAR/flashloader/FlashHC32F460xE.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
@@ -1529,7 +1529,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f460/Source/IAR/debugger/HC32F460xE.ddf</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -1597,7 +1597,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460xE.board</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f460/Source/IAR/flashloader/FlashHC32F460xE.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,42 +0,0 @@
|
||||
[PlDriver]
|
||||
MemConfigValue=$PROJ_DIR$/../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd
|
||||
[PlCacheRanges]
|
||||
CustomRanges0=0 0 524288 1 2048
|
||||
CustomRangesText0=Flash
|
||||
CustomRanges1=0 50334720 1020 1 2048
|
||||
CustomRangesText1=OTP
|
||||
CustomRanges2=0 536838144 192512 0 2048
|
||||
CustomRangesText2=SRAM
|
||||
CustomRanges3=0 537853952 4096 0 2048
|
||||
CustomRangesText3=RET_SRAM
|
||||
CustomRanges4=0 1073741824 536870912 2 0
|
||||
CustomRangesText4=Peripheral
|
||||
CustomRanges5=0 2550136832 67108864 1 2048
|
||||
CustomRangesText5=QSPI
|
||||
CustomRanges6=0 2617245696 67108864 2 67108864
|
||||
CustomRangesText6=QSPI_REG
|
||||
CustomRanges7=0 3758096384 536870912 2 0
|
||||
CustomRangesText7=Private peripheral
|
||||
[Stack]
|
||||
FillEnabled=0
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnLogOnly=1
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[Disassemble mode]
|
||||
mode=0
|
||||
[Breakpoints2]
|
||||
Count=0
|
||||
[Aliases]
|
||||
Count=0
|
||||
SuppressDialog=0
|
||||
[Jet]
|
||||
DisableInterrupts=0
|
||||
LeaveRunning=0
|
||||
MultiCoreRunAll=0
|
||||
[ArmDriver]
|
||||
EnableCache=0
|
||||
@@ -33,7 +33,7 @@
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>../libraries/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR</SFDFile>
|
||||
<SFDFile>./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f460/Source/ARM/sfr/HC32F460.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
devices.gpio:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_GPIO=y
|
||||
- CONFIG_BSP_USING_I2C=y
|
||||
- CONFIG_BSP_USING_I2C_HW=y
|
||||
- CONFIG_BSP_USING_I2C1=y
|
||||
- CONFIG_BSP_USING_TCA9539=y
|
||||
- CONFIG_BSP_USING_EXT_IO=y
|
||||
devices.uart:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_UART=y
|
||||
- CONFIG_BSP_USING_UART2=y
|
||||
@@ -389,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||
# CONFIG_PKG_USING_NANOPB is not set
|
||||
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
|
||||
# CONFIG_PKG_USING_ESP_HOSTED is not set
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
@@ -633,6 +634,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_ZDEBUG is not set
|
||||
# CONFIG_PKG_USING_RVBACKTRACE is not set
|
||||
# CONFIG_PKG_USING_HPATCHLITE is not set
|
||||
# CONFIG_PKG_USING_THREAD_METRIC is not set
|
||||
# end of tools packages
|
||||
|
||||
#
|
||||
@@ -1403,7 +1405,7 @@ CONFIG_SOC_SERIES_HC32F4=y
|
||||
#
|
||||
# Hardware Drivers Config
|
||||
#
|
||||
CONFIG_SOC_HC32F472MC=y
|
||||
CONFIG_SOC_HC32F472PE=y
|
||||
|
||||
#
|
||||
# On-chip Drivers
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -1,6 +1,6 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_HC32F472MC
|
||||
config SOC_HC32F472PE
|
||||
bool
|
||||
select SOC_SERIES_HC32F4
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
|
||||
@@ -109,6 +109,27 @@
|
||||
#define DAC1_CH2_PIN (GPIO_PIN_05)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_DAC2)
|
||||
#define DAC2_CH1_PORT (GPIO_PORT_A)
|
||||
#define DAC2_CH1_PIN (GPIO_PIN_06)
|
||||
#define DAC2_CH2_PORT (GPIO_PORT_A)
|
||||
#define DAC2_CH2_PIN (GPIO_PIN_07)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_DAC3)
|
||||
#define DAC3_CH1_PORT (GPIO_PORT_C)
|
||||
#define DAC3_CH1_PIN (GPIO_PIN_04)
|
||||
#define DAC3_CH2_PORT (GPIO_PORT_C)
|
||||
#define DAC3_CH2_PIN (GPIO_PIN_05)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_DAC4)
|
||||
#define DAC4_CH1_PORT (GPIO_PORT_E)
|
||||
#define DAC4_CH1_PIN (GPIO_PIN_07)
|
||||
#define DAC4_CH2_PORT (GPIO_PORT_E)
|
||||
#define DAC4_CH2_PIN (GPIO_PIN_08)
|
||||
#endif
|
||||
|
||||
/*********** CAN configure *********/
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define CAN1_TX_PORT (GPIO_PORT_D)
|
||||
|
||||
@@ -22,7 +22,17 @@ extern "C" {
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
.name = "dac1", \
|
||||
.vref = 3300, \
|
||||
.data_align = DAC_DATA_ALIGN_RIGHT, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
.ch1_amp_gain = DAC_AMP_GAIN_1, \
|
||||
.ch2_amp_gain = DAC_AMP_GAIN_1, \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
@@ -31,7 +41,17 @@ extern "C" {
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
.name = "dac2", \
|
||||
.vref = 3300, \
|
||||
.data_align = DAC_DATA_ALIGN_RIGHT, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
.ch1_amp_gain = DAC_AMP_GAIN_1, \
|
||||
.ch2_amp_gain = DAC_AMP_GAIN_1, \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
@@ -40,7 +60,17 @@ extern "C" {
|
||||
#ifndef DAC3_INIT_PARAMS
|
||||
#define DAC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac3", \
|
||||
.name = "dac3", \
|
||||
.vref = 3300, \
|
||||
.data_align = DAC_DATA_ALIGN_RIGHT, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
.ch1_amp_gain = DAC_AMP_GAIN_1, \
|
||||
.ch2_amp_gain = DAC_AMP_GAIN_1, \
|
||||
}
|
||||
#endif /* DAC3_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC3 */
|
||||
@@ -49,7 +79,17 @@ extern "C" {
|
||||
#ifndef DAC4_INIT_PARAMS
|
||||
#define DAC4_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac4", \
|
||||
.name = "dac4", \
|
||||
.vref = 3300, \
|
||||
.data_align = DAC_DATA_ALIGN_RIGHT, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
.ch1_amp_gain = DAC_AMP_GAIN_1, \
|
||||
.ch2_amp_gain = DAC_AMP_GAIN_1, \
|
||||
}
|
||||
#endif /* DAC4_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC4 */
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals/> "/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
@@ -41,7 +41,7 @@
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F472.svd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f472/Source/GCC/svd/HC32F472.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F472.svd</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f472/Source/IAR/svd/HC32F472.svd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -112,7 +112,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472xE.board</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f472/Source/IAR/flashloader/FlashHC32F472xE.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
@@ -1529,7 +1529,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F472.svd</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f472/Source/IAR/svd/HC32F472.svd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -1597,7 +1597,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472xE.board</state>
|
||||
<state>$PROJ_DIR$/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f472/Source/IAR/flashloader/FlashHC32F472xE.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -407,7 +407,7 @@
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_HC32F472MC
|
||||
#define SOC_HC32F472PE
|
||||
|
||||
/* On-chip Drivers */
|
||||
|
||||
|
||||
@@ -33,7 +33,7 @@
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F472.SFR</SFDFile>
|
||||
<SFDFile>./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f472/Source/ARM/sfr/HC32F472.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
devices.adc:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_ADC=y
|
||||
- CONFIG_BSP_USING_ADC1=y
|
||||
devices.flash:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_ON_CHIP_FLASH=y
|
||||
devices.gpio:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_GPIO=y
|
||||
- CONFIG_BSP_USING_I2C=y
|
||||
- CONFIG_BSP_USING_I2C_HW=y
|
||||
- CONFIG_BSP_USING_I2C1=y
|
||||
- CONFIG_BSP_USING_TCA9539=y
|
||||
- CONFIG_BSP_USING_EXT_IO=y
|
||||
devices.hwtimer:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_HWTIMER=y
|
||||
- CONFIG_BSP_USING_TMRA_1=y
|
||||
devices.i2c:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_I2C=y
|
||||
devices.pwm:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_PWM=y
|
||||
- CONFIG_BSP_USING_PWM_TMRA=y
|
||||
- CONFIG_BSP_USING_PWM_TMRA_1=y
|
||||
- CONFIG_BSP_USING_PWM_TMRA_1_CH1=y
|
||||
- CONFIG_BSP_USING_PWM_TMRA_1_CH2=y
|
||||
devices.rtc:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_RTC=y
|
||||
- CONFIG_BSP_RTC_USING_XTAL32=y
|
||||
devices.spi:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_SPI=y
|
||||
- CONFIG_BSP_USING_SPI1=y
|
||||
devices.uart:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_UART=y
|
||||
- CONFIG_BSP_USING_UART1=y
|
||||
devices.watchdog:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_WDT_TMR=y
|
||||
- CONFIG_BSP_USING_SWDT=y
|
||||
# ------ SEGGER CI ------
|
||||
segger:
|
||||
kconfig:
|
||||
- CONFIG_PKG_USING_SEGGER_RTT=y
|
||||
- CONFIG_RT_USING_SERIAL_V1=y
|
||||
@@ -392,6 +392,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||
# CONFIG_PKG_USING_NANOPB is not set
|
||||
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
|
||||
# CONFIG_PKG_USING_ESP_HOSTED is not set
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
@@ -636,6 +637,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# CONFIG_PKG_USING_ZDEBUG is not set
|
||||
# CONFIG_PKG_USING_RVBACKTRACE is not set
|
||||
# CONFIG_PKG_USING_HPATCHLITE is not set
|
||||
# CONFIG_PKG_USING_THREAD_METRIC is not set
|
||||
# end of tools packages
|
||||
|
||||
#
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -32,7 +32,7 @@ def bsp_pkg_check():
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
#define XTAL32_FCM_UNIT (CM_FCM)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
@@ -42,22 +43,22 @@ void xtal32_fcm_thread_entry(void *parameter)
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
@@ -66,7 +67,7 @@ void xtal32_fcm_thread_entry(void *parameter)
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
(void)FCM_DeInit(XTAL32_FCM_UNIT);
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
|
||||
@@ -105,6 +105,13 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_DAC)
|
||||
#if defined(BSP_USING_DAC2)
|
||||
void EthPhyDisable(void)
|
||||
{
|
||||
TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET);
|
||||
TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT);
|
||||
}
|
||||
#endif
|
||||
rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
@@ -21,7 +21,17 @@ extern "C" {
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
.name = "dac1", \
|
||||
.vref = 3300, \
|
||||
.data_align = DAC_DATA_ALIGN_RIGHT, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
@@ -30,7 +40,17 @@ extern "C" {
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
.name = "dac2", \
|
||||
.vref = 3300, \
|
||||
.data_align = DAC_DATA_ALIGN_RIGHT, \
|
||||
.dac_adp_enable = RT_FALSE, \
|
||||
.dac_adp_sel = DAC_ADP_SEL_ALL, \
|
||||
.ch1_output_enable = RT_TRUE, \
|
||||
.ch2_output_enable = RT_TRUE, \
|
||||
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
|
||||
.ch1_amp_enable = RT_TRUE, \
|
||||
.ch2_amp_enable = RT_TRUE, \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
@@ -14,20 +14,28 @@
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-03-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
Take OTP sector 16 for example. */
|
||||
__OTP_DATA_START = 0x03000000;
|
||||
__OTP_DATA_SIZE = 2048;
|
||||
__OTP_LOCK_START = 0x03001840;
|
||||
__OTP_LOCK_SIZE = 4;
|
||||
/* OTP section(data sections are not flash multiplexed region) implementation.
|
||||
You need to pay attention to the size of the specified OTP block.
|
||||
Take two OTP blocks for example. */
|
||||
__OTP_DATA_BASE = 0x03000000;
|
||||
__OTP_LOCK_BASE = 0x03001800;
|
||||
/* OTP block 16 */
|
||||
__OTP_DATA_B16_START = 0x03000000;
|
||||
__OTP_LOCK_B16_START = 0x03001840;
|
||||
__OTP_DATA_B16_OFFSET = __OTP_DATA_B16_START - __OTP_DATA_BASE;
|
||||
__OTP_LOCK_B16_OFFSET = __OTP_LOCK_B16_START - __OTP_LOCK_BASE;
|
||||
/* OTP block 17 */
|
||||
__OTP_DATA_B17_START = 0x03000800;
|
||||
__OTP_LOCK_B17_START = 0x03001844;
|
||||
__OTP_DATA_B17_OFFSET = __OTP_DATA_B17_START - __OTP_DATA_BASE;
|
||||
__OTP_LOCK_B17_OFFSET = __OTP_LOCK_B17_START - __OTP_LOCK_BASE;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M
|
||||
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
|
||||
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
|
||||
OTP_DATA (rx): ORIGIN = 0x03000000, LENGTH = 6K
|
||||
OTP_LOCK (rx): ORIGIN = 0x03001800, LENGTH = 728
|
||||
RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
|
||||
RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
@@ -138,14 +146,24 @@ SECTIONS
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data_sec :
|
||||
.otp_data :
|
||||
{
|
||||
KEEP(*(.otp_data_sec))
|
||||
. = ALIGN(4);
|
||||
. = ORIGIN(OTP_DATA) + __OTP_DATA_B16_OFFSET;
|
||||
KEEP(*(.otp_b16_data*))
|
||||
. = ORIGIN(OTP_DATA) + __OTP_DATA_B17_OFFSET;
|
||||
KEEP(*(.otp_b17_data*))
|
||||
. = ALIGN(4);
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock_sec :
|
||||
.otp_lock :
|
||||
{
|
||||
KEEP(*(.otp_lock_sec))
|
||||
. = ALIGN(4);
|
||||
. = ORIGIN(OTP_LOCK) + __OTP_LOCK_B16_OFFSET;
|
||||
KEEP(*(.otp_b16_lock*))
|
||||
. = ORIGIN(OTP_LOCK) + __OTP_LOCK_B17_OFFSET;
|
||||
KEEP(*(.otp_b17_lock*))
|
||||
. = ALIGN(4);
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
|
||||
@@ -61,5 +61,13 @@
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define ETH_RST_PORT (TCA9539_IO_PORT1)
|
||||
#define ETH_RST_PIN (EIO_ETH_RST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals/> "/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
@@ -41,7 +41,7 @@
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F4A0.svd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f4a0/Source/GCC/svd/HC32F4A0.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user