Merge pull request #3356 from wangyq2018/es32f369x

[bsp]add bsp essemi/es32f369x.
2026-06-13 04:33:18 +08:00 · 2020-01-23 16:27:02 +08:00
parent 0f781d013c 9a5a66a716
commit 43abbc3ce8
122 changed files with 76673 additions and 0 deletions
@@ -0,0 +1,434 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40002
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_USING_CAN=y
+# CONFIG_RT_CAN_USING_HDR is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_USING_I2C_BITOPS is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_SOC_ES32F3696LT=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# UART Drivers
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+
+#
+# SPI Drivers
+#
+# CONFIG_BSP_USING_SPI0 is not set
+# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_SPI2 is not set
+
+#
+# I2C Drivers
+#
+# CONFIG_BSP_USING_I2C0 is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# CAN Drivers
+#
+# CONFIG_BSP_USING_CAN is not set
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Offboard Peripheral Drivers
+#
@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ES32F3696LT
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "drivers/Kconfig"
@@ -0,0 +1,98 @@
+# ES-PDS-ES32F369x 开发板 BSP 说明
+标签： EastSoft、国产MCU、Cortex-M3、ES32F3696LT
+
+## 1. 简介
+
+本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F369x 开发板提供的 BSP (板级支持包) 说明。
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+主要内容如下：
+ES-PDS-ES32F369x 是东软载波微电子官方推出的一款基于 ARM Cortex-M3 内核的开发板，最高主频为 96MHz，可满足基础功能测试及高端功能扩展等开发需求。
+
+开发板外观如下图所示：
+
+ES-PDS-ES32F369x-V1.2
+
+![ES32F0654](figures/ES-PDS-ES32F369x-V1.2.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：ES32F3696LT，主频 96MHz，96KB SRAM，512KB FLASH，50 GPIOs
+- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
+- 常用外设
+  - 可调电阻：1个(PA05)
+  - LED：2个，(PF00/PF01)
+  - 按键：6个，PB02、PB12、PC10、PC11、PC12、RESET(MRST)
+- 常用接口：GPIO、UART、SPI、I2C、CAN
+- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
+
+外设支持:
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注**         |
+| :----------- | :----------: | :--------------- |
+| SPI FLASH    |     支持     | SPI0             |
+| **片上外设** | **支持情况** | **备注**         |
+| GPIO         |     支持     | 50 GPIOs         |
+| UART         |     支持     | UART0/1/2/3/4/5  |
+| SPI          |     支持     | SPI0/1/2         |
+| I2C          |     支持     | I2C0/1           |
+| CAN          |     支持     | CAN0             |
+
+### 1.2  注意事项
+
+更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
+
+## 2. 快速上手
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+### 硬件连接
+
+使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART0_TX(PB10)、UART0_RX(PB11)、GND 接到串口工具上。
+
+使用ESlinkⅡ(mini)连接开发板如下图所示：
+
+ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.2
+
+![ESLinkII](figures/ESLinkII-mini.jpg)
+
+### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
+
+### 运行结果
+
+下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.2 build Jan 23 2020
+ 2006 - 2019 Copyright by rt-thread team
+msh>
+```
+## 3. 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 uart0 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+## 4. 联系人信息
+
+- [wangyongquan](https://github.com/wangyq2018) 
+
+## 5. 参考
+
+- [ EastSoft 官网](http://www.essemi.com)
+
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+objs = []
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,40 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN 18
+
+int main(void)
+{
+    int count = 1;
+    /* set PF00 pin mode to output */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}
@@ -0,0 +1,93 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menu "UART Drivers"
+            config BSP_USING_UART0
+                bool "Enable UART0 PB10/PB11(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART1
+                bool "Enable UART1 PC10/PC11(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART2
+                bool "Enable UART2 PC12/PD02(T/R)"
+                select RT_USING_SERIAL
+                default y
+                depends on !BSP_USING_HWTIMER1
+
+            config BSP_USING_UART3
+                bool "Enable UART3 PC04/PC05(T/R)"
+                select RT_USING_SERIAL
+                default n
+                depends on !BSP_USING_HWTIMER2
+
+            
+            config BSP_USING_UART4
+                bool "Enable UART4 PB06/PB07(T/R)"
+                select RT_USING_SERIAL
+                default n
+                depends on !BSP_USING_I2C0
+
+            config BSP_USING_UART5
+                bool "Enable UART5 PB09/PB08(T/R)"
+                select RT_USING_SERIAL
+                default n
+        endmenu
+
+        menu "SPI Drivers"
+            config BSP_USING_SPI0
+                bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+
+            config BSP_USING_SPI1
+                bool "Enable SPI1 BUS PC01/PC02/PC03(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+
+            config BSP_USING_SPI2
+                bool "Enable SPI2 BUS PC05/PB00/PB01(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+        endmenu
+
+        menu "I2C Drivers"
+            config BSP_USING_I2C0
+                bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)"
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_I2C1
+                bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)"
+                select RT_USING_I2C
+                default n
+        endmenu
+
+        menu "CAN Drivers"
+            config BSP_USING_CAN
+                bool "Enable CAN BUS PB08/PB09(RX/TX)"
+                select RT_USING_CAN
+                default n
+        endmenu
+    endmenu
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "Offboard Peripheral Drivers"
+
+    endmenu
+
+endmenu
@@ -0,0 +1,34 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split('''
+board.c
+''')
+
+# add gpio code
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \
+    GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'):
+    src += ['drv_uart.c']
+
+# add spi driver code
+if  GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'):
+    src += ['drv_spi.c']
+
+# add i2c driver code
+if  GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
+    src += ['drv_i2c.c']
+
+# add can driver code
+if  GetDepend('BSP_USING_CAN'):
+    src += ['drv_can.c']
+
+CPPPATH = [cwd]
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+#include <ald_cmu.h>
+#include <ald_gpio.h>
+
+/**
+ * @addtogroup es32f3
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+}
+
+/*******************************************************************************
+ * Function Name  : SystemClock_Configuration
+ * Description    : Configures the System Clock.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SystemClock_Config(void)
+{
+    /* hosc 12MHz, from hosc/3 pll to 96MHz */
+    ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_96M);
+    /*  SYSCLK 96MHz */
+    ald_cmu_clock_config(CMU_CLOCK_PLL1, 96000000);
+    ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE);
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    /* ticks = sysclk / RT_TICK_PER_SECOND */
+    SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_tick_increase();
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/*@}*/
+/**
+ * This function will initial ES32F3 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+    /*System Clock Configuration */
+    SystemClock_Config();
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    unsigned int start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = ald_cmu_get_sys_clock() / 1000000UL;
+    do
+    {
+        now = SysTick->VAL;
+        delta = start > now ? start - now : reload + start - now;
+    }
+    while (delta <  us_tick * us);
+}
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <es32f36xx.h>
+
+#define ES32F3_SRAM_SIZE    0x80000
+#define ES32F3_SRAM_END     (0x20000000 + ES32F3_SRAM_SIZE)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+
+#define HEAP_END    ES32F3_SRAM_END
+
+void rt_hw_board_init(void);
+
+#endif
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_CAN_H__
+#define DRV_CAN_H__
+
+#include <board.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#include <ald_can.h>
+#include <ald_gpio.h>
+
+struct es32f3_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t config_data;
+};
+
+/* es32f3 can device */
+struct es32f3_can
+{
+    can_handle_t CanHandle;
+    can_filter_t FilterConfig;
+    struct rt_can_device device;     /* inherit from can device */
+};
+
+int rt_hw_can_init(void);
+
+#endif /*DRV_CAN_H__ */
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_i2c.h"
+#include <ald_i2c.h>
+#include <ald_gpio.h>
+
+#ifdef RT_USING_I2C
+
+#define TIMEOUT 0x0FFF
+
+/* I2C struct definition */
+#ifdef BSP_USING_I2C0
+    static i2c_handle_t _h_i2c0;
+#endif
+
+#ifdef BSP_USING_I2C1
+    static i2c_handle_t _h_i2c1;
+#endif
+
+static void _i2c_init(void)
+{
+    gpio_init_t gpio_instruct;
+
+    /* Initialize I2C Pin */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.pupd = GPIO_PUSH_UP;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+    gpio_instruct.type = GPIO_TYPE_CMOS;
+    gpio_instruct.func = GPIO_FUNC_5;
+
+#ifdef BSP_USING_I2C0
+    /* Initialize I2C Function */
+    _h_i2c0.perh = I2C0;
+    _h_i2c0.init.clk_speed    = 100000;
+    _h_i2c0.init.own_addr1    = 0x0A;
+    _h_i2c0.init.addr_mode    = I2C_ADDR_7BIT;
+    _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE;
+    _h_i2c0.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
+
+    ald_i2c_reset(&_h_i2c0);
+    ald_i2c_init(&_h_i2c0);
+    /* PB8->I2C0_SCL, PB9->I2C0_SDA */
+    ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* Initialize i2c function */
+    _h_i2c1.perh = I2C1;
+    _h_i2c1.init.clk_speed    = 100000;
+    _h_i2c1.init.own_addr1    = 0xA0;
+    _h_i2c1.init.addr_mode    = I2C_ADDR_7BIT;
+    _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE;
+    _h_i2c1.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
+
+    ald_i2c_reset(&_h_i2c1);
+    ald_i2c_init(&_h_i2c1);
+    /* PA05->I2C1_SCL, PA06->I2C1_SDA */
+    ald_gpio_init(GPIOA, GPIO_PIN_5 | GPIO_PIN_6, &gpio_instruct);
+#endif
+}
+
+static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    rt_uint32_t i;
+    rt_err_t ret = RT_ERROR;
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        if (msg->flags & RT_I2C_RD)
+        {
+            if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+        else
+        {
+            if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+    }
+
+    ret = i;
+
+out:
+    i2c_dbg("send stop condition\n");
+
+    return ret;
+}
+
+const struct rt_i2c_bus_device_ops es32f3_i2c_ops =
+{
+    es32f3_master_xfer,
+    RT_NULL,
+    RT_NULL,
+};
+
+int rt_hw_i2c_init(void)
+{
+    int result = RT_EOK;
+
+    _i2c_init();
+
+#ifdef BSP_USING_I2C0
+    /* define i2c Instance */
+    static struct rt_i2c_bus_device _i2c_device0;
+    rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device));
+
+    _i2c_device0.ops = &es32f3_i2c_ops;
+    _i2c_device0.priv = &_h_i2c0;
+    result = rt_i2c_bus_device_register(&_i2c_device0, "i2c0");
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* define i2c Instance */
+    static struct rt_i2c_bus_device _i2c_device1;
+    rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device));
+
+    _i2c_device1.ops = &es32f3_i2c_ops;
+    _i2c_device1.priv = &_h_i2c1;
+    rt_i2c_bus_device_register(&_i2c_device1, "i2c1");
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_I2C_H__
+#define DRV_I2C_H__
+
+int rt_hw_i2c_init(void);
+
+#endif
@@ -0,0 +1,341 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <string.h>
+#include <rthw.h>
+#include "board.h"
+#include "drv_spi.h"
+#include <ald_spi.h>
+#include <ald_gpio.h>
+#include <ald_cmu.h>
+
+#ifdef RT_USING_SPI
+
+#define SPITIMEOUT 0xFFFF
+
+rt_err_t spi_configure(struct rt_spi_device *device,
+                       struct rt_spi_configuration *cfg)
+{
+    spi_handle_t *hspi;
+    hspi = (spi_handle_t *)device->bus->parent.user_data;
+
+    /* config spi mode */
+    if (cfg->mode & RT_SPI_SLAVE)
+    {
+        hspi->init.mode = SPI_MODE_SLAVER;
+    }
+    else
+    {
+        hspi->init.mode = SPI_MODE_MASTER;
+    }
+    if (cfg->mode & RT_SPI_3WIRE)
+    {
+        hspi->init.dir = SPI_DIRECTION_1LINE;
+    }
+    else
+    {
+        hspi->init.dir = SPI_DIRECTION_2LINES;
+    }
+    if (cfg->data_width == 8)
+    {
+        hspi->init.data_size = SPI_DATA_SIZE_8;
+    }
+    else if (cfg->data_width == 16)
+    {
+        hspi->init.data_size = SPI_DATA_SIZE_16;
+    }
+
+    if (cfg->mode & RT_SPI_CPHA)
+    {
+        hspi->init.phase = SPI_CPHA_SECOND;
+    }
+    else
+    {
+        hspi->init.phase = SPI_CPHA_FIRST;
+    }
+    if (cfg->mode & RT_SPI_CPOL)
+    {
+        hspi->init.polarity = SPI_CPOL_HIGH;
+    }
+    else
+    {
+        hspi->init.polarity = SPI_CPOL_LOW;
+    }
+    if (cfg->mode & RT_SPI_NO_CS)
+    {
+        hspi->init.ss_en = DISABLE;
+    }
+    else
+    {
+        hspi->init.ss_en = ENABLE;
+    }
+
+    /* config spi clock */
+    if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
+    {
+        /* pclk1 max speed 48MHz, spi master max speed 10MHz */
+        if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
+        {
+            hspi->init.baud = SPI_BAUD_2;
+        }
+        else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
+        {
+            hspi->init.baud = SPI_BAUD_4;
+        }
+        else
+        {
+            hspi->init.baud = SPI_BAUD_8;
+        }
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
+    {
+        /* pclk1 max speed 48MHz, spi master max speed 10MHz */
+        if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
+        {
+            hspi->init.baud = SPI_BAUD_4;
+        }
+        else
+        {
+            hspi->init.baud = SPI_BAUD_8;
+        }
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
+    {
+        hspi->init.baud = SPI_BAUD_8;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
+    {
+        hspi->init.baud = SPI_BAUD_16;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
+    {
+        hspi->init.baud = SPI_BAUD_32;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
+    {
+        hspi->init.baud = SPI_BAUD_64;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
+    {
+        hspi->init.baud = SPI_BAUD_128;
+    }
+    else
+    {
+        hspi->init.baud = SPI_BAUD_256;
+    }
+    hspi->init.ss_en    = DISABLE;
+    hspi->init.crc_calc = DISABLE;
+    ald_spi_init(hspi);
+    return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    rt_err_t res;
+    spi_handle_t *hspi;
+    struct es32f3_hw_spi_cs *cs;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
+
+    hspi = (spi_handle_t *)device->bus->parent.user_data;
+    cs = device->parent.user_data;
+
+    /* send & receive */
+    if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
+    {
+        if (message->cs_take)
+        {
+            rt_pin_write(cs->pin, 0);
+        }
+        res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                                (rt_int32_t)message->length, SPITIMEOUT);
+        if (message->cs_release)
+        {
+            rt_pin_write(cs->pin, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+    else
+    {
+        /* only send data */
+        if (message->recv_buf == RT_NULL)
+        {
+            if (message->cs_take)
+            {
+                rt_pin_write(cs->pin, 0);
+            }
+            res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+            if (message->cs_release)
+            {
+                rt_pin_write(cs->pin, 1);
+            }
+            if (res != RT_EOK)
+                return RT_ERROR;
+        }
+        /* only receive data */
+        if (message->send_buf == RT_NULL)
+        {
+            if (message->cs_take)
+            {
+                rt_pin_write(cs->pin, 0);
+            }
+            res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
+            if (message->cs_release)
+            {
+                rt_pin_write(cs->pin, 1);
+            }
+            if (res != RT_EOK)
+                return RT_ERROR;
+        }
+    }
+
+    return message->length;
+}
+
+const struct rt_spi_ops es32f3_spi_ops =
+{
+    spi_configure,
+    spixfer,
+};
+
+rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
+{
+    /* define spi Instance */
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+    cs_pin->pin = pin;
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+    rt_pin_write(pin, 1);
+    return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+}
+
+#ifdef BSP_USING_SPI0
+    static struct rt_spi_bus _spi_bus0;
+    static spi_handle_t _spi0;
+#endif
+
+#ifdef BSP_USING_SPI1
+    static struct rt_spi_bus _spi_bus1;
+    static spi_handle_t _spi1;
+#endif
+
+#ifdef BSP_USING_SPI2
+    static struct rt_spi_bus _spi_bus2;
+    static spi_handle_t _spi2;
+#endif
+
+int rt_hw_spi_init(void)
+{
+    int result = RT_EOK;
+
+    struct rt_spi_bus *spi_bus;
+    spi_handle_t *spi;
+    gpio_init_t gpio_instruct;
+
+#ifdef BSP_USING_SPI0
+    _spi0.perh = SPI0;
+    spi_bus = &_spi_bus0;
+    spi = &_spi0;
+
+    /* SPI0 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.func = GPIO_FUNC_4;
+    gpio_instruct.type = GPIO_TYPE_TTL;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+
+    /* PB3->SPI0_SCK, PB5->SPI0_MOSI */
+    ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
+
+    /* PB4->SPI0_MISO */
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_SPI1
+    _spi1.perh = SPI1;
+    spi_bus = &_spi_bus1;
+    spi = &_spi1;
+
+    /* SPI1 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.func = GPIO_FUNC_4;
+    gpio_instruct.type = GPIO_TYPE_TTL;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+
+    /* PC01->SPI1_SCK, PC03->SPI1_MOSI */
+    ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct);
+
+    /* PC02->SPI1_MISO */
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_SPI2
+    _spi1.perh = SPI2;
+    spi_bus = &_spi_bus2;
+    spi = &_spi2;
+
+    /* SPI2 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.func = GPIO_FUNC_5;
+    gpio_instruct.type = GPIO_TYPE_TTL;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+
+    /* PC05->SPI1_SCK, PB01->SPI1_MOSI */
+    ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct);
+
+    /* PB00->SPI1_MISO */
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_SPI_H__
+#define DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+struct es32f3_hw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+/* cannot be used before completion init */
+rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name);
+int rt_hw_spi_init(void);
+
+#endif
@@ -0,0 +1,431 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_uart.h"
+#include <ald_gpio.h>
+#include <ald_uart.h>
+#include <ald_cmu.h>
+
+#ifdef RT_USING_SERIAL
+
+/* es32 uart driver */
+struct es32_uart
+{
+    uart_handle_t huart;
+    IRQn_Type irq;
+};
+
+static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    gpio_init_t gpio_initstructure;
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    /* Initialize tx pin */
+    gpio_initstructure.mode = GPIO_MODE_OUTPUT;
+    gpio_initstructure.odos = GPIO_PUSH_PULL;
+    gpio_initstructure.pupd = GPIO_PUSH_UP;
+    gpio_initstructure.podrv = GPIO_OUT_DRIVE_1;
+    gpio_initstructure.nodrv = GPIO_OUT_DRIVE_0_1;
+    gpio_initstructure.flt  = GPIO_FILTER_DISABLE;
+    gpio_initstructure.type = GPIO_TYPE_TTL;
+
+#ifdef BSP_USING_UART0
+    gpio_initstructure.func = GPIO_FUNC_3;
+    ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE);
+#endif /* uart0 gpio init */
+
+#ifdef BSP_USING_UART1
+    gpio_initstructure.func = GPIO_FUNC_3;
+    ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE);
+#endif /* uart1 gpio init */
+
+#ifdef BSP_USING_UART2
+    gpio_initstructure.func = GPIO_FUNC_5;
+    ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE);
+#endif /* uart2 gpio init */
+
+#ifdef BSP_USING_UART3
+    gpio_initstructure.func = GPIO_FUNC_4;
+    ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE);
+#endif /* uart3 gpio init */
+
+#ifdef BSP_USING_UART4
+    gpio_initstructure.func = GPIO_FUNC_3;
+    ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE);
+#endif /* uart4 gpio init */
+
+#ifdef BSP_USING_UART5
+    gpio_initstructure.func = GPIO_FUNC_4;
+    ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE);
+#endif /* uart5 gpio init */
+
+    ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY, 1);
+    ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE, 1);
+
+    uart->huart.init.mode        = UART_MODE_UART;
+    uart->huart.init.baud        = cfg->baud_rate;
+    uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits);
+    uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
+    uart->huart.init.fctl        = UART_HW_FLOW_CTL_DISABLE;
+    ald_uart_init(&uart->huart);
+
+    if (cfg->bit_order == BIT_ORDER_MSB)
+    {
+        UART_MSB_FIRST_ENABLE(&uart->huart);
+    }
+    else
+    {
+        UART_MSB_FIRST_DISABLE(&uart->huart);
+    }
+
+    if (cfg->invert == NRZ_INVERTED)
+    {
+        UART_DATA_INV_ENABLE(&uart->huart);
+    }
+    else
+    {
+        UART_DATA_INV_DISABLE(&uart->huart);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct es32_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irq);
+        /* disable interrupt */
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irq);
+        /* enable interrupt */
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int es32f3x_putc(struct rt_serial_device *serial, char c)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET)
+        ;
+    WRITE_REG(uart->huart.perh->TXBUF, c);
+
+    return 1;
+}
+
+static int es32f3x_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct es32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH))
+    {
+        ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF);
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops es32f3x_uart_ops =
+{
+    es32f3x_configure,
+    es32f3x_control,
+    es32f3x_putc,
+    es32f3x_getc,
+};
+
+#ifdef BSP_USING_UART0
+/* UART0 device driver structure */
+struct es32_uart uart0 =
+{
+    {UART0},
+    UART0_IRQn
+};
+
+struct rt_serial_device serial0;
+
+void UART0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart0.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart0.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+/* UART1 device driver structure */
+struct es32_uart uart1 =
+{
+    {UART1},
+    UART1_IRQn
+};
+
+struct rt_serial_device serial1;
+
+void UART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart1.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart1.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+/* UART2 device driver structure */
+struct es32_uart uart2 =
+{
+    {UART2},
+    UART2_IRQn
+};
+
+struct rt_serial_device serial2;
+
+void UART2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart2.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart2.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+/* UART3 device driver structure */
+struct es32_uart uart3 =
+{
+    {UART3},
+    UART3_IRQn
+};
+
+struct rt_serial_device serial3;
+
+void UART3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart3.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart3.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+#ifdef BSP_USING_UART4
+/* UART4 device driver structure */
+struct es32_uart uart4 =
+{
+    {UART4},
+    UART4_IRQn
+};
+
+struct rt_serial_device serial4;
+
+void UART4_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart4.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart4.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+#ifdef BSP_USING_UART5
+/* UART5 device driver structure */
+struct es32_uart uart5 =
+{
+    {UART5},
+    UART5_IRQn
+};
+
+struct rt_serial_device serial5;
+
+void UART5_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart5.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart5.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART5 */
+
+int rt_hw_uart_init(void)
+{
+    struct es32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART0
+    uart = &uart0;
+    serial0.ops = &es32f3x_uart_ops;
+    serial0.config = config;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+    uart = &uart1;
+    serial1.ops = &es32f3x_uart_ops;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+    uart = &uart2;
+    serial2.ops = &es32f3x_uart_ops;
+    serial2.config = config;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+    uart = &uart3;
+    serial3.ops = &es32f3x_uart_ops;
+    serial3.config = config;
+
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3, "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART3 */
+
+#ifdef BSP_USING_UART4
+    uart = &uart4;
+    serial4.ops = &es32f3x_uart_ops;
+    serial4.config = config;
+
+    /* register UART4 device */
+    rt_hw_serial_register(&serial4, "uart4",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART4 */
+
+#ifdef BSP_USING_UART5
+    uart = &uart5;
+    serial5.ops = &es32f3x_uart_ops;
+    serial5.config = config;
+
+    /* register UART5 device */
+    rt_hw_serial_register(&serial5, "uart5",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART5 */
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00018000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
@@ -0,0 +1,28 @@
+/**
+  *********************************************************************************
+  *
+  * @file    system_es32f3xx.c
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer
+  *
+  * @version V1.0
+  * @date    24 Dec 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "utils.h"
+
+
+/**
+  * @brief  Configuring system clock before startup.
+  * @note   This function must be used after reset.
+  * @retval None
+  */
+void system_init (void)
+{
+	/* do nothing */
+}
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
@@ -0,0 +1,197 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0U 
+#define ARM_MPU_AP_PRIV 1U
+#define ARM_MPU_AP_URO  2U
+#define ARM_MPU_AP_FULL 3U
+#define ARM_MPU_AP_PRO  5U
+#define ARM_MPU_AP_RO   6U
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((((DisableExec     ) << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+   (((TypeExtField    ) << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+   (((IsShareable     ) << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+   (((IsCacheable     ) << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+   (((IsBufferable    ) << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+   (((Size            ) << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+   (MPU_RASR_ENABLE_Msk))
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Pos) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
@@ -0,0 +1,301 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_acmp.h
+  * @brief   Header file of ACMP module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __ALD_ACMP_H__
+#define __ALD_ACMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup ACMP
+  * @{
+  */
+
+/** @defgroup ACMP_Public_Types ACMP Public Types
+  * @{
+  */
+
+/**
+  * @brief ACMP interrupt
+  */
+typedef enum {
+	ACMP_IT_EDGE   = (1U << 0),	/**< Edge interrupt bit */
+	ACMP_IT_WARMUP = (1U << 1),	/**< Warm up interrupt bit */
+} acmp_it_t;
+
+/**
+  * @brief ACMP interrupt flag
+  */
+typedef enum {
+	ACMP_FLAG_EDGE   = (1U << 0),	/**< Edge interrupt flag */
+	ACMP_FLAG_WARMUP = (1U << 1),	/**< Warm up interrupt flag */	
+} acmp_flag_t;
+
+/**
+  * @brief ACMP status flag
+  */
+typedef enum {
+	ACMP_STATUS_ACT = (1U << 0),	/**< Edge status flag */
+	ACMP_STATUS_OUT = (1U << 1),	/**< Warm up status flag */
+} acmp_status_t;
+
+/**
+  * @brief ACMP positive input
+  */
+typedef enum {
+	ACMP_POS_CH0 = 0x0,	/**< Channel 0 as positive input */
+	ACMP_POS_CH1 = 0x1,	/**< Channel 1 as positive input */
+	ACMP_POS_CH2 = 0x2,	/**< Channel 2 as positive input */
+	ACMP_POS_CH3 = 0x3,	/**< Channel 3 as positive input */
+	ACMP_POS_CH4 = 0x4,	/**< Channel 4 as positive input */
+	ACMP_POS_CH5 = 0x5,	/**< Channel 5 as positive input */
+	ACMP_POS_CH6 = 0x6,	/**< Channel 6 as positive input */
+	ACMP_POS_CH7 = 0x7,	/**< Channel 7 as positive input */
+} acmp_pos_input_t;
+
+/**
+  * @brief ACMP negative input
+  */
+typedef enum {
+	ACMP_NEG_CH0  = 0x0, 	/**< Channel 0 as negative input */
+	ACMP_NEG_CH1  = 0x1, 	/**< Channel 1 as negative input */
+	ACMP_NEG_CH2  = 0x2, 	/**< Channel 2 as negative input */
+	ACMP_NEG_CH3  = 0x3, 	/**< Channel 3 as negative input */
+	ACMP_NEG_CH4  = 0x4, 	/**< Channel 4 as negative input */
+	ACMP_NEG_CH5  = 0x5, 	/**< Channel 5 as negative input */
+	ACMP_NEG_CH6  = 0x6, 	/**< Channel 6 as negative input */
+	ACMP_NEG_CH7  = 0x7, 	/**< Channel 7 as negative input */
+	ACMP_NEG_1V25 = 0x8, 	/**< 1.25v as negative input */
+	ACMP_NEG_2V5  = 0x9, 	/**< 2.5v as negative input */
+	ACMP_NEG_VDD  = 0xA,	/**< VDD as negative input */
+} acmp_neg_input_t;
+
+/**
+  * @brief ACMP mode
+  */
+typedef enum {
+	ACMP_ULTRA_LOW_POWER = 0x0,	/**< Ultra low power mode */
+	ACMP_LOW_POWER       = 0x1,	/**< Low power mode */
+	ACMP_MIDDLE_POWER    = 0x2,	/**< Middle power mode */
+	ACMP_HIGH_POWER      = 0x3,	/**< High power mode */
+} acmp_mode_t;
+
+/**
+  * @brief ACMP warm-up time
+  */
+typedef enum {
+	ACMP_4_PCLK   = 0x0,	/**< 4 hfperclk cycles */
+	ACMP_8_PCLK   = 0x1,	/**< 4 hfperclk cycles */
+	ACMP_16_PCLK  = 0x2,	/**< 4 hfperclk cycles */
+	ACMP_32_PCLK  = 0x3,	/**< 4 hfperclk cycles */
+	ACMP_64_PCLK  = 0x4,	/**< 4 hfperclk cycles */
+	ACMP_128_PCLK = 0x5,	/**< 4 hfperclk cycles */
+	ACMP_256_PCLK = 0x6,	/**< 4 hfperclk cycles */
+	ACMP_512_PCLK = 0x7,	/**< 4 hfperclk cycles */
+} acmp_warm_time_t;
+
+/**
+  * @brief ACMP hysteresis level
+  */
+typedef enum {
+	ACMP_HYST_0  = 0x0,	/**< No hysteresis */
+	ACMP_HYST_15 = 0x1,	/**< 15mV hysteresis */
+	ACMP_HYST_22 = 0x2,	/**< 22mV hysteresis */
+	ACMP_HYST_29 = 0x3,	/**< 29mV hysteresis */
+	ACMP_HYST_36 = 0x4,	/**< 36mV hysteresis */
+	ACMP_HYST_43 = 0x5,	/**< 43mV hysteresis */
+	ACMP_HYST_50 = 0x6,	/**< 50mV hysteresis */
+	ACMP_HYST_57 = 0x7,	/**< 57mV hysteresis */
+} acmp_hystsel_t;
+
+/**
+  * @brief ACMP inactive state
+  */
+typedef enum {
+	ACMP_INACTVAL_LOW  = 0x0,	/**< The inactive value is 0 */
+	ACMP_INACTVAL_HIGH = 0x1,	/**< The inactive value is 1 */
+} acmp_inactval_t;
+
+/**
+  * @brief which edges set up interrupt
+  */
+typedef enum {
+	ACMP_EDGE_NONE = 0x0,	/**< Disable EDGE interrupt */
+	ACMP_EDGE_FALL = 0x1,	/**< Falling edges set EDGE interrupt */
+	ACMP_EDGE_RISE = 0x2,	/**< rise edges set EDGE interrupt */
+	ACMP_EDGE_ALL  = 0x3,	/**< Falling edges and rise edges set EDGE interrupt */
+} acmp_edge_t;
+
+/**
+  * @brief ACMP output function
+  */
+typedef enum {
+	ACMP_OUT_DISABLE = 0x0,	/**< Disable acmp output */
+	ACMP_OUT_ENABLE  = 0x1,	/**< Enable acmp output */
+} acmp_out_func_t;
+
+/**
+  * @brief ACMP init structure definition
+  */
+typedef struct {
+	acmp_mode_t mode;           	/**< ACMP operation mode */
+	acmp_warm_time_t warm_time; 	/**< ACMP warm up time */
+	acmp_hystsel_t hystsel;     	/**< ACMP hysteresis level */
+	acmp_pos_input_t p_port;  	/**< ACMP positive port select */
+	acmp_neg_input_t n_port;  	/**< ACMP negative port select */
+	acmp_inactval_t inactval;   	/**< ACMP inavtive output value */
+	type_func_t out_inv;		/**< ACMP output inverse */
+	acmp_edge_t edge;           	/**< Select edges to set interrupt flag */
+	uint8_t vdd_level;          	/**< Select scaling factor for CDD reference level, MAX is 63 */
+} acmp_init_t;
+
+/**
+  * @brief  ACMP Handle Structure definition
+  */
+typedef struct acmp_handle_s {
+	ACMP_TypeDef *perh;	/**< Register base address */
+	acmp_init_t init;  	/**< ACMP required parameters */
+	lock_state_t lock; 	/**< Locking object */
+
+	void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg);	/**< ACMP warm-up complete callback */
+	void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg);  	/**< ACMP edge trigger callback */
+} acmp_handle_t;
+/**
+  * @}
+  */
+
+/** @defgroup ACMP_Public_Macros ACMP Public Macros
+  * @{
+  */
+#define ACMP_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
+#define ACMP_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
+/**
+  * @}
+  */
+
+/** @defgroup ACMP_Private_Macros   ACMP Private Macros
+  * @{
+  */
+#define IS_ACMP_TYPE(x) 		(((x) == ACMP0) || \
+                                         ((x) == ACMP1) || \
+				         ((x) == ACMP2))
+#define IS_ACMP_MODE_TYPE(x)		(((x) == ACMP_ULTRA_LOW_POWER) || \
+					 ((x) == ACMP_LOW_POWER)       || \
+					 ((x) == ACMP_MIDDLE_POWER)    || \
+					 ((x) == ACMP_HIGH_POWER))
+#define IS_ACMP_IT_TYPE(x) 		(((x) == ACMP_IT_EDGE)  || \
+				         ((x) == ACMP_IT_WARMUP))
+#define IS_ACMP_FLAG_TYPE(x) 		(((x) == ACMP_FLAG_EDGE) || \
+				         ((x) == ACMP_FLAG_WARMUP))
+#define IS_ACMP_STATUS_TYPE(x) 	        (((x) == ACMP_STATUS_ACT) || \
+				         ((x) == ACMP_STATUS_OUT))
+#define IS_ACMP_POS_INPUT_TYPE(x) 	(((x) == ACMP_POS_CH0) || \
+				         ((x) == ACMP_POS_CH1) || \
+				         ((x) == ACMP_POS_CH2) || \
+				         ((x) == ACMP_POS_CH3) || \
+				         ((x) == ACMP_POS_CH4) || \
+				         ((x) == ACMP_POS_CH5) || \
+				         ((x) == ACMP_POS_CH6) || \
+				         ((x) == ACMP_POS_CH7))
+#define IS_ACMP_NEG_INPUT_TYPE(x) 	(((x) == ACMP_NEG_CH0)  || \
+				         ((x) == ACMP_NEG_CH1)  || \
+				         ((x) == ACMP_NEG_CH2)  || \
+				         ((x) == ACMP_NEG_CH3)  || \
+				         ((x) == ACMP_NEG_CH4)  || \
+				         ((x) == ACMP_NEG_CH5)  || \
+				         ((x) == ACMP_NEG_CH6)  || \
+				         ((x) == ACMP_NEG_CH7)  || \
+				         ((x) == ACMP_NEG_1V25) || \
+				         ((x) == ACMP_NEG_2V5)  || \
+				         ((x) == ACMP_NEG_VDD))
+#define IS_ACMP_WARM_UP_TIME_TYPE(x)    (((x) == ACMP_4_PCLK)   || \
+				         ((x) == ACMP_8_PCLK)   || \
+				         ((x) == ACMP_16_PCLK)  || \
+				         ((x) == ACMP_32_PCLK)  || \
+				         ((x) == ACMP_64_PCLK)  || \
+				         ((x) == ACMP_128_PCLK) || \
+				         ((x) == ACMP_256_PCLK) || \
+				         ((x) == ACMP_512_PCLK))
+#define IS_ACMP_HYSTSEL_TYPE(x)         (((x) == ACMP_HYST_0)  || \
+				         ((x) == ACMP_HYST_15) || \
+				         ((x) == ACMP_HYST_22) || \
+				         ((x) == ACMP_HYST_29) || \
+				         ((x) == ACMP_HYST_36) || \
+				         ((x) == ACMP_HYST_43) || \
+				         ((x) == ACMP_HYST_50) || \
+				         ((x) == ACMP_HYST_57))
+#define IS_ACMP_INACTVAL_TYPE(x) 	(((x) == ACMP_INACTVAL_LOW) || \
+				         ((x) == ACMP_INACTVAL_HIGH))
+#define IS_ACMP_EDGE_TYPE(x) 	        (((x) == ACMP_EDGE_NONE) || \
+					 ((x) == ACMP_EDGE_FALL) || \
+				         ((x) == ACMP_EDGE_RISE) || \
+					 ((x) == ACMP_EDGE_ALL))
+/**
+  * @}
+  */
+
+/** @addtogroup ACMP_Public_Functions
+  * @{
+  */
+
+/** @addtogroup ACMP_Public_Functions_Group1
+  * @{
+  */
+ald_status_t ald_acmp_init(acmp_handle_t *hperh);
+/**
+  * @}
+  */
+/** @addtogroup ACMP_Public_Functions_Group2
+  * @{
+  */
+void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
+it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it);
+flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
+flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
+void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
+/**
+  * @}
+  */
+/** @addtogroup ACMP_Public_Functions_Group3
+  * @{
+  */
+void ald_acmp_irq_handler(acmp_handle_t *hperh);
+void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state);
+uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
+flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#ifdef __cplusplus
+extern "C" }
+#endif
+#endif
@@ -0,0 +1,194 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_bkpc.h
+  * @brief   Header file of BKPC module driver.
+  *
+  * @version V1.0
+  * @date    15 Dec 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_BKPC_H__
+#define __ALD_BKPC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup BKPC
+  * @{
+  */
+
+/** @defgroup BKPC_Public_Macros BKPC Public Macros
+  * @{
+  */
+#define BKPC_LOCK()		(WRITE_REG(BKPC->PROT, 0))
+#define BKPC_UNLOCK()		(WRITE_REG(BKPC->PROT, 0x9669AA55))
+#define BKPC_LRC_ENABLE()			\
+do {						\
+	BKPC_UNLOCK();				\
+	SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
+#define BKPC_LRC_DISABLE()			\
+do {						\
+	BKPC_UNLOCK();				\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
+#define BKPC_LOSM_ENABLE()			\
+do {						\
+	BKPC_UNLOCK();				\
+	SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
+#define BKPC_LOSM_DISABLE()			\
+do {						\
+	BKPC_UNLOCK();				\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
+	BKPC_LOCK();				\
+} while (0)
+#define BKPC_LOSC_ENABLE()			\
+do {						\
+	BKPC_UNLOCK();				\
+	SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
+#define BKPC_LOSC_DISABLE()			\
+do {						\
+	BKPC_UNLOCK();				\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
+	BKPC_LOCK();				\
+} while (0)
+
+
+#define BKPC_MRST_WAKEUP_ENABLE()			\
+do {							\
+	BKPC_UNLOCK();					\
+	SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);	\
+	BKPC_LOCK();					\
+} while (0)
+#define BKPC_MRST_WAKEUP_DISABLE()			\
+do {							\
+	BKPC_UNLOCK();					\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);	\
+	BKPC_LOCK();					\
+} while (0)
+
+/**
+  * @}
+  */
+
+/** @defgroup BKPC_Public_Types BKPC Public Types
+  * @{
+  */
+/**
+  * @brief BKPC preipheral clock select.
+  */
+typedef enum {
+	BKPC_PREH_CLK_LOSM    = 0x0,	/**< LOSM */
+	BKPC_PREH_CLK_LRC     = 0x1,	/**< LRC */
+	BKPC_PREH_CLK_HRC_1M  = 0x2,	/**< HRC down to 1MHz */
+	BKPC_PREH_CLK_HOSC_1M = 0x3,	/**< HOSC down to 1MHz */
+} bkpc_preh_clk_t;
+
+/**
+  * @brief Standby wakeup port select
+  */
+typedef enum {
+	PMU_STANDBY_PORT_SEL_PA0 = 0x0,	/**< PA0 */
+	PMU_STANDBY_PORT_SEL_PA1 = 0x1,	/**< PA1 */
+	PMU_STANDBY_PORT_SEL_PA2 = 0x2,	/**< PA2 */
+	PMU_STANDBY_PORT_SEL_PA3 = 0x3,	/**< PA3 */
+	PMU_STANDBY_PORT_SEL_PA4 = 0x4,	/**< PA4 */
+	PMU_STANDBY_PORT_SEL_PA5 = 0x5,	/**< PA5 */
+	PMU_STANDBY_PORT_SEL_PA6 = 0x6,	/**< PA6 */
+	PMU_STANDBY_PORT_SEL_PA7 = 0x7,	/**< PA7 */
+} bkpc_wakeup_port_t;
+
+/**
+  * @brief Standby wakeup level
+  */
+typedef enum {
+	PMU_STANDBY_LEVEL_HIGH = 0x0,	/**< PA0 */
+	PMU_STANDBY_LEVEL_LOW  = 0x1,	/**< PA1 */
+} bkpc_wakeup_level_t;
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup BKPC_Private_Macros BKPC Private Macros
+  * @{
+  */
+#define IS_BKPC_WAKEUP_PORT(x)	(((x) == PMU_STANDBY_PORT_SEL_PA0) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA1) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA2) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA3) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA4) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA5) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA6) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA7))
+#define IS_BKPC_WAKEUP_LEVEL(x)	(((x) == PMU_STANDBY_LEVEL_HIGH) || \
+                                 ((x) == PMU_STANDBY_LEVEL_LOW))
+#define IS_BKPC_PREH_CLOCK(x)	(((x) == BKPC_PREH_CLK_LOSM) || \
+                                 ((x) == BKPC_PREH_CLK_LRC) || \
+                                 ((x) == BKPC_PREH_CLK_HRC_1M) || \
+                                 ((x) == BKPC_PREH_CLK_HOSC_1M))
+#define IS_BKPC_RAM_IDX(x)	((x) < 32)
+/**
+  * @}
+  */
+
+/** @addtogroup BKPC_Public_Functions
+  * @{
+  */
+/** @addtogroup BKPC_Public_Functions_Group1
+  * @{
+  */
+/* control functions */
+extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
+extern void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock);
+extern void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock);
+/**
+  * @}
+  */
+/** @addtogroup BKPC_Public_Functions_Group2
+  * @{
+  */
+/* IO operation functions */
+extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value);
+extern uint32_t ald_bkpc_read_ram(uint8_t idx);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_BKPC_H__ */
@@ -0,0 +1,57 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_calc.h
+  * @brief   Header file of CALC module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_CALC_H__
+#define __ALD_CALC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup CALC
+  * @{
+  */
+
+/** @addtogroup CALC_Public_Functions
+  * @{
+  */
+extern uint32_t ald_calc_sqrt(uint32_t data);
+extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
+extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
+extern flag_status_t ald_calc_get_dz_status(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_CALC_H__ */
@@ -0,0 +1,471 @@
+/**
+  ******************************************************************************
+  * @file    ald_can.h
+  * @brief   Header file of CAN Module driver.
+  *
+  * @version V1.0
+  * @date    16 Apr 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ******************************************************************************
+  */
+
+#ifndef __ALD_CAN_H
+#define __ALD_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/** @defgroup CAN_Public_Types CAN Public Types
+  * @{
+  */
+/**
+  * @brief  ALD State structures definition
+  */
+typedef enum {
+	CAN_STATE_RESET      = 0x00,	/**< CAN not yet initialized or disabled */
+	CAN_STATE_READY      = 0x01,	/**< CAN initialized and ready for use */
+	CAN_STATE_BUSY       = 0x02,	/**< CAN process is ongoing */
+	CAN_STATE_BUSY_TX    = 0x11,	/**< CAN process is ongoing */
+	CAN_STATE_BUSY_RX    = 0x21,	/**< CAN process is ongoing */
+	CAN_STATE_BUSY_TX_RX = 0x31,	/**< CAN process is ongoing */
+	CAN_STATE_TIMEOUT    = 0x03,	/**< CAN in Timeout state */
+	CAN_STATE_ERROR      = 0x04,	/**< CAN error state */
+} can_state_t;
+
+/**
+  * @brief CAN Error Code
+  */
+typedef enum {
+	CAN_ERROR_NONE = 0x00,		/**< No error */
+	CAN_ERROR_EWG  = 0x01,		/**< EWG error */
+	CAN_ERROR_EPV  = 0x02,		/**< EPV error */
+	CAN_ERROR_BOF  = 0x04,		/**< BOF error */
+	CAN_ERROR_STF  = 0x08,		/**< Stuff error */
+	CAN_ERROR_FOR  = 0x10,		/**< Form error */
+	CAN_ERROR_ACK  = 0x20,		/**< Acknowledgment error */
+	CAN_ERROR_BR   = 0x40,		/**< Bit recessive */
+	CAN_ERROR_BD   = 0x80,		/**< LEC dominant */
+	CAN_ERROR_CRC  = 0x100,		/**< LEC transfer error */
+	CAN_ERROR_UNK  = 0x200,		/**< Unknown error */
+} can_error_t;
+
+/**
+  * @brief CAN Operating Mode
+  */
+ typedef enum {
+	CAN_MODE_NORMAL          =  0x00,	/**< Normal mode */
+	CAN_MODE_LOOPBACK        =  0x01,	/**< Loopback mode */
+	CAN_MODE_SILENT          =  0x02,	/**< Silent mode */
+	CAN_MODE_SILENT_LOOPBACK =  0x03,  	/**< Loopback combined with silent mode */
+} can_operate_mode_t;
+
+/**
+  * @brief CAN Synchronization Jump Width
+  */
+typedef enum {
+	CAN_SJW_1 = 0x0,	/**< 1 time quantum */
+	CAN_SJW_2 = 0x1,	/**< 2 time quantum */
+	CAN_SJW_3 = 0x2,	/**< 3 time quantum */
+	CAN_SJW_4 = 0x3,	/**< 4 time quantum */
+} can_sjw_t;
+
+/**
+  * @brief CAN Time Quantum in Bit Segment 1
+  */
+typedef enum {
+	CAN_SEG1_1  = 0x0,	/**< 1 time quantum */
+	CAN_SEG1_2  = 0x1,	/**< 2 time quantum */
+	CAN_SEG1_3  = 0x2,	/**< 3 time quantum */
+	CAN_SEG1_4  = 0x3,	/**< 4 time quantum */
+	CAN_SEG1_5  = 0x4,	/**< 5 time quantum */
+	CAN_SEG1_6  = 0x5,	/**< 6 time quantum */
+	CAN_SEG1_7  = 0x6,	/**< 7 time quantum */
+	CAN_SEG1_8  = 0x7,	/**< 8 time quantum */
+	CAN_SEG1_9  = 0x8,	/**< 9 time quantum */
+	CAN_SEG1_10 = 0x9,	/**< 10 time quantum */
+	CAN_SEG1_11 = 0xA,	/**< 11 time quantum */
+	CAN_SEG1_12 = 0xB,	/**< 12 time quantum */
+	CAN_SEG1_13 = 0xC,	/**< 13 time quantum */
+	CAN_SEG1_14 = 0xD,	/**< 14 time quantum */
+	CAN_SEG1_15 = 0xE,	/**< 15 time quantum */
+	CAN_SEG1_16 = 0xF,	/**< 16 time quantum */
+} can_seg1_t;
+
+/**
+  * @brief CAN Time Quantum in Bit Segment 2
+  */
+typedef enum {
+	CAN_SEG2_1 = 0x0,	/**< 1 time quantum */
+	CAN_SEG2_2 = 0x1,     	/**< 2 time quantum */
+	CAN_SEG2_3 = 0x2,     	/**< 3 time quantum */
+	CAN_SEG2_4 = 0x3,     	/**< 4 time quantum */
+	CAN_SEG2_5 = 0x4,     	/**< 5 time quantum */
+	CAN_SEG2_6 = 0x5,     	/**< 6 time quantum */
+	CAN_SEG2_7 = 0x6,     	/**< 7 time quantum */
+	CAN_SEG2_8 = 0x7,     	/**< 8 time quantum */
+} can_seg2_t;
+
+/**
+  * @brief CAN Filter Mode
+  */
+typedef enum {
+	CAN_FILTER_MODE_MASK = 0x0,	/**< Identifier mask mode */
+	CAN_FILTER_MODE_LIST = 0x1,	/**< Identifier list mode */
+} can_filter_mode_t;
+
+/**
+  * @brief CAN Filter Scale
+  */
+typedef enum {
+	CAN_FILTER_SCALE_16 = 0x0,	/**< Two 16-bit filters */
+	CAN_FILTER_SCALE_32 = 0x1,	/**< One 32-bit filter */
+} can_filter_scale_t;
+
+/**
+  * @brief CAN Filter fifo
+  */
+typedef enum {
+	CAN_FILTER_FIFO0 = 0x0,	/**< FIFO 0 assignment for filter */
+	CAN_FILTER_FIFO1 = 0x1,	/**< FIFO 1 assignment for filter */
+} can_filter_fifo_t;
+
+/**
+  * @brief CAN Identifier Type
+  */
+typedef enum {
+	CAN_ID_STD = 0x0,	/**< Standard Id */
+	CAN_ID_EXT = 0x1,	/**< Extended Id */
+} can_id_type_t;
+
+/**
+  * @brief CAN Remote Transmission Request
+  */
+typedef enum {
+	CAN_RTR_DATA   = 0x0,	/**< Data frame */
+	CAN_RTR_REMOTE = 0x1, 	/**< Remote frame */
+} can_remote_req_t;
+
+/**
+  * @brief CAN Transmit Constants
+  */
+typedef enum {
+	CAN_TX_MAILBOX_0    = 0x0,	/**< TX mailbox index 0 */
+	CAN_TX_MAILBOX_1    = 0x1,	/**< TX mailbox index 1 */
+	CAN_TX_MAILBOX_2    = 0x2,	/**< TX mailbox index 2 */
+	CAN_TX_MAILBOX_NONE = 0x3,	/**< MailBox can't be used */
+} can_tx_mailbox_t;
+
+/**
+  * @brief  CAN Receive fifo Number
+  */
+typedef enum {
+	CAN_RX_FIFO0 = 0x0,	/**< CAN fifo 0 used to receive */
+	CAN_RX_FIFO1 = 0x1,	/**< CAN fifo 1 used to receive */
+} can_rx_fifo_t;
+
+/**
+  * @brief  CAN Flags
+  */
+typedef enum {
+	CAN_FLAG_SLPS   = (1U << 1),			/**< Sleep acknowledge flag */
+	CAN_FLAG_ERR    = (1U << 2),			/**< Error flag*/
+	CAN_FLAG_WK     = (1U << 3),			/**< Wake up flag */
+	CAN_FLAG_SLP    = (1U << 4),			/**< Sleep acknowledge flag */
+	CAN_FLAG_M0REQC = (1U << 20) | (1U << 0),	/**< Request MailBox0 flag */
+	CAN_FLAG_M0TXC  = (1U << 20) | (1U << 1),	/**< Transmission OK MailBox0 flag */
+	CAN_FLAG_M1REQC = (1U << 20) | (1U << 8),	/**< Request MailBox1 flag */
+	CAN_FLAG_M1TXC  = (1U << 20) | (1U << 9),	/**< Transmission OK MailBox1 flag */
+	CAN_FLAG_M2REQC = (1U << 20) | (1U << 16),	/**< Request MailBox2 flag */
+	CAN_FLAG_M2TXC  = (1U << 20) | (1U << 17),	/**< Transmission OK MailBox2 flag */
+	CAN_FLAG_TXM0   = (1U << 20) | (1U << 26),	/**< Transmit mailbox 0 empty flag */
+	CAN_FLAG_TXM1   = (1U << 20) | (1U << 27),	/**< Transmit mailbox 1 empty flag */
+	CAN_FLAG_TXM2   = (1U << 20) | (1U << 28),	/**< Transmit mailbox 2 empty flag */
+	CAN_FLAG_FF0    = (2U << 20) | (1U << 3),	/**< FIFO 0 Full flag */
+	CAN_FLAG_FOV0   = (2U << 20) | (1U << 4),	/**< FIFO 0 Overrun flag */
+	CAN_FLAG_FF1    = (3U << 20) | (1U << 3),	/**< FIFO 1 Full flag */
+	CAN_FLAG_FOV1   = (3U << 20) | (1U << 4),	/**< FIFO 1 Overrun flag */
+	CAN_FLAG_WARN   = (4U << 20) | (1U << 0),	/**< Error warning flag */
+	CAN_FLAG_PERR   = (4U << 20) | (1U << 1),	/**< Error passive flag */
+	CAN_FLAG_BOF    = (4U << 20) | (1U << 2),	/**< Bus-Off flag */
+} can_flag_t;
+
+/**
+  * @brief CAN Interrupts
+  */
+typedef enum {
+	CAN_IT_TXM   = (1U << 0),	/**< Transmit mailbox empty interrupt bit */
+	CAN_IT_FP0   = (1U << 1),	/**< FIFO0 message pending interrupt bit */
+	CAN_IT_FF0   = (1U << 2),	/**< FIFO0 full interrupt bit */
+	CAN_IT_FOV0  = (1U << 3),	/**< FIFO0 overrun interrupt bit */
+	CAN_IT_FP1   = (1U << 4),	/**< FIFO1 message pending interrupt bit */
+	CAN_IT_FF1   = (1U << 5),	/**< FIFO1 full interrupt bit */
+	CAN_IT_FOV1  = (1U << 6),	/**< FIFO1 overrun interrupt bit */
+	CAN_IT_WARN  = (1U << 8),	/**< Error warning interrupt bit */
+	CAN_IT_PERR  = (1U << 9),	/**< Error passive interrupt bit */
+	CAN_IT_BOF   = (1U << 10),	/**< Bus-off interrupt bit */
+	CAN_IT_PRERR = (1U << 11),	/**< Last error code interrupt bit */
+	CAN_IT_ERR   = (1U << 15),	/**< Error interrupt bit */
+	CAN_IT_WK    = (1U << 16),	/**< wake-up interrupt bit */
+	CAN_IT_SLP   = (1U << 17),	/**< sleep interrupt bit */
+} can_it_t;
+
+/**
+  * @brief CAN filter configuration structure definition
+  */
+typedef struct {
+	uint32_t id_high;		/**< Specifies the filter identification number */
+	uint32_t id_low;		/**< Specifies the filter identification number */
+	uint32_t mask_id_high;		/**< Specifies the filter mask number or identification number */
+	uint32_t mask_id_low;		/**< Specifies the filter mask number or identification number */
+	can_filter_fifo_t fifo;		/**< Specifies the fifo (0 or 1) which will be assigned to the filter. */
+	uint32_t number;		/**< Specifies the filter which will be initialized. */
+	can_filter_mode_t mode;		/**< Specifies the filter mode to be initialized. */
+	can_filter_scale_t scale;	/**< Specifies the filter scale. */
+	type_func_t active;		/**< Enable or disable the filter. */
+	uint32_t bank_number;		/**< Select the start slave bank filter. */
+} can_filter_t;
+
+/**
+  * @brief CAN init structure definition
+  */
+typedef struct {
+	uint32_t psc;			/**< Specifies the length of a time quantum. */
+	can_operate_mode_t mode;	/**< Specifies the CAN operating mode. */
+	can_sjw_t sjw;			/**< Specifies the maximum number of time quanta the CAN hardware is
+	                                       allowed to lengthen or shorten a bit to perform resynchronization. */
+	can_seg1_t seg1;		/**< Specifies the number of time quanta in Bit Segment 1. */
+	can_seg2_t seg2;		/**< Specifies the number of time quanta in Bit Segment 2. */
+	type_func_t ttcm;		/**< Enable or disable the time triggered communication mode. */
+	type_func_t abom;		/**< Enable or disable the automatic bus-off management. */
+	type_func_t awk;		/**< Enable or disable the automatic wake-up mode. */
+	type_func_t artx;		/**< Enable or disable the non-automatic retransmission mode. */
+	type_func_t rfom;		/**< Enable or disable the Receive fifo Locked mode. */
+	type_func_t txmp;		/**< Enable or disable the transmit fifo priority. */
+} can_init_t;
+
+/**
+  * @brief CAN Tx message structure definition
+  */
+typedef struct {
+	uint32_t std;		/**< Specifies the standard identifier. */
+	uint32_t ext;		/**< Specifies the extended identifier. */
+	can_id_type_t type;	/**< Specifies the type of identifier for the message that will be transmitted. */
+	can_remote_req_t rtr;	/**< Specifies the type of frame for the message that will be transmitted. */
+	uint32_t len;		/**< Specifies the length of the frame that will be transmitted. */
+	uint8_t data[8];	/**< Contains the data to be transmitted. */
+} can_tx_msg_t;
+
+/**
+  * @brief CAN Rx message structure definition
+  */
+typedef struct {
+	uint32_t std;		/**< Specifies the standard identifier. */
+	uint32_t ext;		/**< Specifies the extended identifier. */
+	can_id_type_t type;	/**< Specifies the type of identifier for the message that will be received. */
+	can_remote_req_t rtr;	/**< Specifies the type of frame for the received message. */
+	uint32_t len;		/**< Specifies the length of the frame that will be received. */
+	uint8_t data[8];	/**< Contains the data to be received. */
+	uint32_t fmi;		/**< Specifies the index of the filter the message stored in the mailbox passes through. */
+	can_rx_fifo_t num;	/**< Specifies the receive fifo number. */
+} can_rx_msg_t;
+
+/**
+  * @brief CAN handle Structure definition
+  */
+typedef struct can_handle_s {
+	CAN_TypeDef *perh;	/**< Register base address */
+	can_init_t init;	/**< CAN required parameters */
+	can_rx_msg_t *rx_msg;	/**< Pointer to receive message */
+	lock_state_t lock;	/**< CAN locking object */
+	can_state_t state;	/**< CAN communication state */
+	can_error_t err;	/**< CAN Error code */
+
+	void (*tx_cplt_cbk)(struct can_handle_s *arg);	/**< Tx completed callback */
+	void (*rx_cplt_cbk)(struct can_handle_s *arg);	/**< Rx completed callback */
+	void (*error_cbk)(struct can_handle_s *arg);	/**< error callback */
+} can_handle_t;
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Public_Macro CAN Public Macros
+  * @{
+  */
+#define CAN_RESET_HANDLE_STATE(x)	((x)->state = CAN_STATE_RESET)
+#define CAN_RX_MSG_PENDING(x, y)	(((y) == CAN_RX_FIFO0) ? \
+	(READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK)))
+#define CAN_DBG_FREEZE(x, y)	(MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))
+#define CAN_TX_STAMP_ENABLE(x)	(SET_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK))
+#define CAN_TX_STAMP_DISABLE(x)	(CLEAR_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Macros CAN Private Macros
+  * @{
+  */
+#define IS_CAN_ALL(x)	((x) == CAN0)
+#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13)
+#define IS_CAN_MODE(x)	(((x) == CAN_MODE_NORMAL)   || \
+                         ((x) == CAN_MODE_LOOPBACK) || \
+                         ((x) == CAN_MODE_SILENT)   || \
+                         ((x) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(x)	(((x) == CAN_SJW_1) || \
+                         ((x) == CAN_SJW_2) || \
+                         ((x) == CAN_SJW_3) || \
+                         ((x) == CAN_SJW_4))
+#define IS_CAN_BS1(x)	((x) <= CAN_SEG1_16)
+#define IS_CAN_BS2(x)	((x) <= CAN_SEG2_8)
+#define IS_CAN_FILTER_MODE(x)	(((x) == CAN_FILTER_MODE_MASK) || \
+                                 ((x) == CAN_FILTER_MODE_LIST))
+#define IS_CAN_FILTER_SCALE(x)	(((x) == CAN_FILTER_SCALE_16) || \
+                                 ((x) == CAN_FILTER_SCALE_32))
+#define IS_CAN_FILTER_FIFO(x)	(((x) == CAN_FILTER_FIFO0) || \
+                                 ((x) == CAN_FILTER_FIFO1))
+#define IS_CAN_IDTYPE(x)	(((x) == CAN_ID_STD) || \
+                                 ((x) == CAN_ID_EXT))
+#define IS_CAN_RTR(x)	(((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(x)	(((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))
+#define IS_CAN_BANKNUMBER(x)	((x) <= 28)
+#define IS_CAN_TX_MAILBOX(x)	((x) <= CAN_TX_MAILBOX_NONE)
+#define IS_CAN_STDID(x)		((x) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(x)		((x) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DATA_LEN(x)	((x) <= ((uint8_t)0x08))
+#define IS_CAN_PRESCALER(x)	(((x) >= 1) && ((x) <= 1024))
+#define IS_CAN_GET_FLAG(x)	(((x)  == CAN_FLAG_SLPS)   || \
+                                  ((x) == CAN_FLAG_ERR)    || \
+                                  ((x) == CAN_FLAG_WK)     || \
+                                  ((x) == CAN_FLAG_SLP)    || \
+                                  ((x) == CAN_FLAG_M0REQC) || \
+                                  ((x) == CAN_FLAG_M0TXC)  || \
+                                  ((x) == CAN_FLAG_M1REQC) || \
+                                  ((x) == CAN_FLAG_M1TXC)  || \
+                                  ((x) == CAN_FLAG_M2REQC) || \
+                                  ((x) == CAN_FLAG_M2TXC)  || \
+                                  ((x) == CAN_FLAG_TXM0)   || \
+                                  ((x) == CAN_FLAG_TXM1)   || \
+                                  ((x) == CAN_FLAG_TXM2)   || \
+                                  ((x) == CAN_FLAG_FF0)    || \
+                                  ((x) == CAN_FLAG_FOV0)   || \
+                                  ((x) == CAN_FLAG_FF1)    || \
+                                  ((x) == CAN_FLAG_FOV1)   || \
+                                  ((x) == CAN_FLAG_WARN)   || \
+                                  ((x) == CAN_FLAG_PERR)   || \
+                                  ((x) == CAN_FLAG_BOF))
+#define IS_CAN_CLEAR_FLAG(x)	(((x)  == CAN_FLAG_ERR)    || \
+                                  ((x) == CAN_FLAG_WK)     || \
+                                  ((x) == CAN_FLAG_SLP)    || \
+                                  ((x) == CAN_FLAG_M0REQC) || \
+                                  ((x) == CAN_FLAG_M1REQC) || \
+                                  ((x) == CAN_FLAG_M2REQC) || \
+                                  ((x) == CAN_FLAG_FF0)    || \
+                                  ((x) == CAN_FLAG_FOV0)   || \
+                                  ((x) == CAN_FLAG_FF1)    || \
+                                  ((x) == CAN_FLAG_FOV1))
+#define IS_CAN_IT(x)		(((x)  == CAN_IT_TXM)   || \
+                                  ((x) == CAN_IT_FP0) || \
+                                  ((x) == CAN_IT_FF0) || \
+                                  ((x) == CAN_IT_FOV0) || \
+                                  ((x) == CAN_IT_FP1) || \
+                                  ((x) == CAN_IT_FF1)   || \
+                                  ((x) == CAN_IT_FOV1)  || \
+                                  ((x) == CAN_IT_WARN)   || \
+				  ((x) == CAN_IT_PERR) || \
+                                  ((x) == CAN_IT_BOF) || \
+                                  ((x) == CAN_IT_PRERR) || \
+                                  ((x) == CAN_IT_ERR)   || \
+                                  ((x) == CAN_IT_WK)  || \
+                                  ((x) == CAN_IT_SLP))
+#define CAN_TIMEOUT_VALUE  	100
+#define CAN_STATE_TX_MASK	(1U << 4)
+#define CAN_STATE_RX_MASK	(1U << 5)
+/**
+  * @}
+  */
+
+/** @addtogroup CAN_Public_Functions
+  * @{
+  */
+
+/** @addtogroup CAN_Public_Functions_Group1
+  *  @{
+  */
+/* Initialization functions */
+void ald_can_reset(can_handle_t *hperh);
+ald_status_t ald_can_init(can_handle_t *hperh);
+ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config);
+/**
+  * @}
+  */
+
+/** @addtogroup CAN_Public_Functions_Group2
+  * @{
+  */
+/* IO operation functions */
+ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout);
+ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg);
+ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout);
+ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg);
+/**
+  * @}
+  */
+
+/** @addtogroup CAN_Public_Functions_Group3
+  * @{
+  */
+/* Control function */
+ald_status_t ald_can_sleep(can_handle_t *hperh);
+ald_status_t ald_can_wake_up(can_handle_t *hperh);
+void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box);
+void ald_can_irq_handler(can_handle_t *hperh);
+type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box);
+void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state);
+it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it);
+flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag);
+void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag);
+/**
+  * @}
+  */
+
+/** @addtogroup CAN_Public_Functions_Group4
+  * @{
+  */
+/* State and Error functions */
+can_state_t ald_can_get_state(can_handle_t *hperh);
+can_error_t ald_can_get_error(can_handle_t *hperh);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_CAN_H */
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