Bsp nxp support (#8530)

Co-authored-by: StackYuan <yuanjyjyj@outlook.com>

bsp/nxp/README.md

@@ -0,0 +1,8 @@
+# NXP BSP 说明
+
+存放RT-Thread NXP BSP目录，目前支持MCX系列，之前一些老的IC支持(如LPC/Kinetis/I.MXRT)会逐步放到此目录下
+
+| BSP 文件夹名称       | 开发板名称                |
+|:------------------------- |:-------------------------- |
+| mcxn | frdm-mcxn947 |
+| mcxa | frdm-mcxa153 |

bsp/nxp/mcxa/Libraries/.ignore_format.yml

@@ -0,0 +1,4 @@
+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- MCXA153

bsp/nxp/mcxa/Libraries/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/nxp/mcxa/Libraries/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.4
+ * @date     23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/nxp/mcxa/Libraries/CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i)
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

bsp/nxp/mcxa/Libraries/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif  // TZ_CONTEXT_H

bsp/nxp/mcxa/Libraries/CMSIS/LICENSE.txt

@@ -0,0 +1,201 @@
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bsp/nxp/mcxa/Libraries/Kconfig

@@ -0,0 +1,4 @@
+config SOC_MCX
+    bool
+    select ARCH_ARM_CORTEX_M33
+    select ARCH_ARM_CORTEX_FPU

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_aoi.c

@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_aoi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.aoi"
+#endif
+
+#if defined(AOI_RSTS)
+#define AOI_RESETS_ARRAY AOI_RSTS
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to aoi bases for each instance. */
+static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
+
+#if defined(AOI_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_aoiResets[] = AOI_RESETS_ARRAY;
+#endif
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to aoi clocks for each instance. */
+static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for AOI module.
+ *
+ * @param base AOI peripheral base address
+ *
+ * @return The AOI instance
+ */
+static uint32_t AOI_GetInstance(AOI_Type *base);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t AOI_GetInstance(AOI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++)
+    {
+        if (s_aoiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_aoiBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes an AOI instance for operation.
+ *
+ * This function un-gates the AOI clock.
+ *
+ * param base AOI peripheral address.
+ */
+void AOI_Init(AOI_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock gate from clock manager. */
+    CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(AOI_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_aoiResets[AOI_GetInstance(base)]);
+#endif
+}
+
+/*!
+ * brief Deinitializes an AOI instance for operation.
+ *
+ * This function shutdowns AOI module.
+ *
+ * param  base AOI peripheral address.
+ */
+void AOI_Deinit(AOI_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock gate from clock manager */
+    CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the Boolean evaluation associated.
+ *
+ * This function returns the Boolean evaluation associated.
+ *
+ * Example:
+  code
+    aoi_event_config_t demoEventLogicStruct;
+
+    AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
+  endcode
+ *
+ * param  base AOI peripheral address.
+ * param  event Index of the event which will be set of type aoi_event_t.
+ * param  config Selected input configuration .
+ */
+void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
+{
+    assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT);
+    assert(config != NULL);
+
+    uint16_t value;
+    uint16_t temp;
+    /* Read BFCRT01 register at event index. */
+    value = base->BFCRT[event].BFCRT01;
+
+    temp          = (value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT;
+    config->PT0AC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT;
+    config->PT0BC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT;
+    config->PT0CC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT;
+    config->PT0DC = (aoi_input_config_t)temp;
+
+    temp          = (value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT;
+    config->PT1AC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT;
+    config->PT1BC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT;
+    config->PT1CC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT;
+    config->PT1DC = (aoi_input_config_t)temp;
+
+    /* Read BFCRT23 register at event index. */
+    value = base->BFCRT[event].BFCRT23;
+
+    temp          = (value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT;
+    config->PT2AC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT;
+    config->PT2BC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT;
+    config->PT2CC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT;
+    config->PT2DC = (aoi_input_config_t)temp;
+
+    temp          = (value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT;
+    config->PT3AC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT;
+    config->PT3BC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT;
+    config->PT3CC = (aoi_input_config_t)temp;
+    temp          = (value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT;
+    config->PT3DC = (aoi_input_config_t)temp;
+}
+
+/*!
+ * brief Configures an AOI event.
+ *
+ * This function configures an AOI event according
+ * to the aoiEventConfig structure. This function configures all  inputs (A, B, C, and D)
+ * of all  product terms (0, 1, 2, and 3) of a desired event.
+ *
+ * Example:
+  code
+    aoi_event_config_t demoEventLogicStruct;
+
+    demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
+    demoEventLogicStruct.PT0BC = kAOI_InputSignal;
+    demoEventLogicStruct.PT0CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT0DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT1AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT1BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT2AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT2BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT3AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT3BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3DC = kAOI_LogicOne;
+
+    AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
+  endcode
+ *
+ * param  base AOI peripheral address.
+ * param  event Event which will be configured of type aoi_event_t.
+ * param  eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
+ * filling out the members of this structure and passing the pointer to this function.
+ */
+void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
+{
+    assert(eventConfig != NULL);
+    assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT);
+
+    uint16_t value;
+    /* Calculate value to configure product term 0, 1 */
+    value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) |
+            AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) |
+            AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) |
+            AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC);
+    /* Write value to register */
+    base->BFCRT[event].BFCRT01 = value;
+
+    /* Reset and calculate value to configure product term 2, 3 */
+    value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) |
+            AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) |
+            AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) |
+            AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC);
+    /* Write value to register */
+    base->BFCRT[event].BFCRT23 = value;
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_aoi.h

@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_AOI_H_
+#define _FSL_AOI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup aoi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef AOI
+#define AOI AOI0 /*!< AOI peripheral address */
+#endif
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
+/*@}*/
+
+/*!
+ * @brief AOI input configurations.
+ *
+ * The selection item represents the Boolean evaluations.
+ */
+typedef enum _aoi_input_config
+{
+    kAOI_LogicZero      = 0x0U, /*!< Forces the input to logical zero. */
+    kAOI_InputSignal    = 0x1U, /*!< Passes the input signal. */
+    kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */
+    kAOI_LogicOne       = 0x3U  /*!< Forces the input to logical one. */
+} aoi_input_config_t;
+
+/*!
+ * @brief AOI event indexes, where an event is the collection of the four product
+ *        terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
+ */
+typedef enum _aoi_event
+{
+    kAOI_Event0 = 0x0U, /*!< Event 0 index */
+    kAOI_Event1 = 0x1U, /*!< Event 1 index */
+    kAOI_Event2 = 0x2U, /*!< Event 2 index */
+    kAOI_Event3 = 0x3U  /*!< Event 3 index */
+} aoi_event_t;
+
+/*!
+ * @brief AOI event configuration structure
+ *
+ * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make
+ * whole event configuration.
+ */
+typedef struct _aoi_event_config
+{
+    aoi_input_config_t PT0AC; /*!< Product term 0 input A */
+    aoi_input_config_t PT0BC; /*!< Product term 0 input B */
+    aoi_input_config_t PT0CC; /*!< Product term 0 input C */
+    aoi_input_config_t PT0DC; /*!< Product term 0 input D */
+    aoi_input_config_t PT1AC; /*!< Product term 1 input A */
+    aoi_input_config_t PT1BC; /*!< Product term 1 input B */
+    aoi_input_config_t PT1CC; /*!< Product term 1 input C */
+    aoi_input_config_t PT1DC; /*!< Product term 1 input D */
+    aoi_input_config_t PT2AC; /*!< Product term 2 input A */
+    aoi_input_config_t PT2BC; /*!< Product term 2 input B */
+    aoi_input_config_t PT2CC; /*!< Product term 2 input C */
+    aoi_input_config_t PT2DC; /*!< Product term 2 input D */
+    aoi_input_config_t PT3AC; /*!< Product term 3 input A */
+    aoi_input_config_t PT3BC; /*!< Product term 3 input B */
+    aoi_input_config_t PT3CC; /*!< Product term 3 input C */
+    aoi_input_config_t PT3DC; /*!< Product term 3 input D */
+} aoi_event_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name  AOI Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an AOI instance for operation.
+ *
+ * This function un-gates the AOI clock.
+ *
+ * @param base AOI peripheral address.
+ */
+void AOI_Init(AOI_Type *base);
+
+/*!
+ * @brief Deinitializes an AOI instance for operation.
+ *
+ * This function shutdowns AOI module.
+ *
+ * @param  base AOI peripheral address.
+ */
+void AOI_Deinit(AOI_Type *base);
+
+/*@}*/
+
+/*!
+ * @name  AOI Get Set Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the Boolean evaluation associated.
+ *
+ * This function returns the Boolean evaluation associated.
+ *
+ * Example:
+  @code
+    aoi_event_config_t demoEventLogicStruct;
+
+    AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
+  @endcode
+ *
+ * @param  base AOI peripheral address.
+ * @param  event Index of the event which will be set of type aoi_event_t.
+ * @param  config Selected input configuration .
+ */
+void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config);
+
+/*!
+ * @brief Configures an AOI event.
+ *
+ * This function configures an AOI event according
+ * to the aoiEventConfig structure. This function configures all  inputs (A, B, C, and D)
+ * of all  product terms (0, 1, 2, and 3) of a desired event.
+ *
+ * Example:
+  @code
+    aoi_event_config_t demoEventLogicStruct;
+
+    demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
+    demoEventLogicStruct.PT0BC = kAOI_InputSignal;
+    demoEventLogicStruct.PT0CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT0DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT1AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT1BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT2AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT2BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT3AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT3BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3DC = kAOI_LogicOne;
+
+    AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
+  @endcode
+ *
+ * @param  base AOI peripheral address.
+ * @param  event Event which will be configured of type aoi_event_t.
+ * @param  eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
+ * filling out the members of this structure and passing the pointer to this function.
+ */
+void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*@}*/
+
+/*!* @} */
+
+#endif /* _FSL_AOI_H_*/

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_cmc.c

@@ -0,0 +1,293 @@
+/*
+ * Copyright 2022 ~ 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_cmc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mcx_cmc"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
+#define CMC_SRAMDIS_RESERVED_MASK                                                                                   \
+    (~(kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | kCMC_RAMD1 |       \
+       kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | \
+       kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI))
+
+#define CMC_SRAMRET_RESERVED_MASK (CMC_SRAMDIS_RESERVED_MASK)
+#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static uint32_t g_savedPrimask;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Sets clock mode.
+ *
+ * This function configs the amount of clock gating when the core asserts
+ * Sleeping due to WFI, WFE or SLEEPONEXIT.
+ *
+ * param base CMC peripheral base address.
+ * param mode System clock mode.
+ */
+void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode)
+{
+    uint32_t reg;
+
+    reg = base->CKCTRL;
+    reg &= ~CMC_CKCTRL_CKMODE_MASK;
+    reg |= CMC_CKCTRL_CKMODE((mode));
+    base->CKCTRL = reg;
+}
+
+/*!
+ * brief Configures all power mode protection settings.
+ *
+ * This function configures the power mode protection settings for
+ * supported power modes. This should be done before setting the lowPower mode
+ * for each power doamin.
+ *
+ * The allowed lowpower modes are passed as bit map. For example, to allow
+ * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode).
+ * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes).
+ *
+ * param base CMC peripheral base address.
+ * param allowedModes Bitmaps of the allowed power modes.
+ */
+void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes)
+{
+    uint32_t reg;
+
+    reg = base->PMPROT;
+    reg &= ~0xFUL;
+    reg |= allowedModes;
+
+    base->PMPROT = reg;
+}
+
+/*!
+ * brief Configure reset pin.
+ *
+ * This function configures reset pin. When enabled, the low power filter is enabled in both
+ * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers
+ * are enabled, they operate in series.
+ *
+ * param base CMC peripheral base address.
+ * param config Pointer to the reset pin config structure.
+ */
+void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = base->RPC;
+
+    if (config->lowpowerFilterEnable)
+    {
+        reg |= CMC_RPC_LPFEN_MASK;
+    }
+    else
+    {
+        reg &= ~CMC_RPC_LPFEN_MASK;
+    }
+    if (config->resetFilterEnable)
+    {
+        reg |= (CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG(config->resetFilterWidth));
+    }
+    else
+    {
+        reg &= ~(CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG_MASK);
+    }
+    base->RPC = reg;
+}
+
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
+/*!
+ * brief Power off the selected system SRAM always.
+ *
+ * This function powers off the selected system SRAM always. The SRAM arrays should
+ * not be accessed while they are shut down. SRAM array contents are not retained
+ * if they are powered off.
+ *
+ * param base CMC peripheral base address.
+ * param mask Bitmap of the SRAM arrays to be powered off all modes.
+ */
+void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->SRAMDIS[0];
+
+    reg &= ~(CMC_SRAMDIS_DIS_MASK | CMC_SRAMDIS_RESERVED_MASK);
+    reg |= CMC_SRAMDIS_DIS(mask);
+    base->SRAMDIS[0] = reg;
+}
+
+/*!
+ * brief Power off the selected system SRAm during low power mode only.
+ *
+ * This function powers off the selected system SRAM only during low power mode.
+ * SRAM array contents are not retained if they are power off.
+ *
+ * param base CMC peripheral base address.
+ * param mask Bitmap of the SRAM arrays to be power off during low power mode only.
+ */
+void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->SRAMRET[0];
+
+    reg &= ~(CMC_SRAMRET_RET_MASK | CMC_SRAMRET_RESERVED_MASK);
+    reg |= CMC_SRAMRET_RET(mask);
+    base->SRAMRET[0] = reg;
+}
+#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
+
+/*!
+ * brief Configs the low power mode of the on-chip flash memory.
+ *
+ * This function config the low power mode of the on-chip flash memory.
+ *
+ * param base CMC peripheral base address.
+ * param wake
+ *          true    -   Flash will exit low power state during the flash memory accesses.
+ *          false   -    No effect.
+ * param doze
+ *          true    -   Flash is disabled while core is sleeping
+ *          false   -   No effect.
+ * param disable
+ *          true    -   Flash memory is placed in low power state.
+ *          false   -   No effect.
+ */
+void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
+{
+    uint32_t reg = 0UL;
+
+    reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
+           (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)) |
+           (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
+    base->FLASHCR = reg;
+}
+
+/*!
+ * brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering low power modes.
+ *
+ */
+void CMC_PreEnterLowPowerMode(void)
+{
+    g_savedPrimask = DisableGlobalIRQ();
+    __ISB();
+}
+
+/*!
+ * brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after waking up from low power modes.
+ * This function should be used with CMC_PreEnterLowPowerMode()
+ *
+ */
+void CMC_PostExitLowPowerMode(void)
+{
+    EnableGlobalIRQ(g_savedPrimask);
+    __ISB();
+}
+
+/*!
+ * brief Configs the entry into the same low power mode for each power domains.
+ *
+ * This function provides the feature to entry into the same low power mode for each power
+ * domains. Before invoking this function, please ensure the selected power mode have been allowed.
+ *
+ * param base CMC peripheral base address.
+ * param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details.
+ *
+ */
+void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)
+{
+    /* Note: unlock the CKCTRL register if this API will be reinvoked later. */
+    CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
+    CMC_SetGlobalPowerMode(base, lowPowerMode);
+    /* Before executing WFI instruction read back the last register to
+     * ensure all registers writes have completed. */
+    (void)base->GPMCTRL;
+    /* Set the core into DeepSleep mode. */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
+    __WFI();
+    __ISB();
+}
+
+/*!
+ * brief Configs the entry into different low power modes for each of the power domains.
+ *
+ * This function provides the feature to entry into different low power modes for
+ * each power domains. Before invoking this function please ensure the selected
+ * modes are allowed.
+ *
+ * param base CMC peripheral base address.
+ * param base config Pointer to the cmc_power_domain_config_t structure.
+ */
+void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)
+{
+    assert(config != NULL);
+
+#if (CMC_PMCTRL_COUNT > 1U)
+    /* The WAKE domain must never be configured to a lower power mode compared with main power mode. */
+    assert(config->wake_domain <= config->main_domain);
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
+
+    if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode)
+    {
+        /* In This case the power domain doesn't need to be placed in low power state. */
+        /* Note: unlock the register if this API will be reinvoked later. */
+        CMC_SetClockMode(base, config->clock_mode);
+
+        CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode);
+#if (CMC_PMCTRL_COUNT > 1U)
+        CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode);
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
+
+        /* Before executing WFI instruction read back the last register to
+         * ensure all registers writes have completed. */
+        (void)base->CKCTRL;
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+        __DSB();
+        __WFI();
+        __ISB();
+    }
+    else
+    {
+        /* Note: unlock the register if this API will be reinvoked later. */
+        CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
+        CMC_SetMAINPowerMode(base, config->main_domain);
+#if (CMC_PMCTRL_COUNT > 1U)
+        CMC_SetWAKEPowerMode(base, config->wake_domain);
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
+
+        /* Before execute WFI instruction read back the last register to
+         * ensure all registers writes have completed. */
+#if (CMC_PMCTRL_COUNT > 1U)
+        if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain))
+        {
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
+            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+            __DSB();
+            __WFI();
+            __ISB();
+#if (CMC_PMCTRL_COUNT > 1U)
+        }
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
+    }
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_common.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc((size_t)alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
+#endif

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_common.h

@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
+
+/*! @brief Construct the version number for drivers.
+ *
+ * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
+ * and 16-bit platforms(such as DSC).
+ *
+ * @verbatim
+
+   | Unused    || Major Version || Minor Version ||  Bug Fix    |
+   31        25  24           17  16            9  8            0
+
+   @endverbatim
+ */
+#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI      3U  /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC     4U  /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U  /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART      6U  /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART     7U  /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic               = 0,   /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH                 = 1,   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI                 = 4,   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI            = 5,   /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI                  = 6,   /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART           = 7,   /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C            = 8,   /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C                 = 9,   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART                  = 10,  /*!< Group number for UART status codes. */
+    kStatusGroup_I2C                   = 11,  /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI                 = 12,  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART                = 13,  /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI                   = 14,  /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC                  = 15,  /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42                = 16,  /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC                  = 17,  /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC                 = 18,  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI                   = 19,  /*!< Group number for SAI status code */
+    kStatusGroup_MCG                   = 20,  /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG                   = 21,  /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI                 = 22,  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S            = 23,  /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD         = 24,  /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP              = 25,  /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C          = 26,  /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S                   = 27,  /*!< Group number for I2S status codes */
+    kStatusGroup_IUART                 = 28,  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI                   = 29,  /*!< Group number for CSI status codes */
+    kStatusGroup_MIPI_DSI              = 30,  /*!< Group number for MIPI DSI status codes */
+    kStatusGroup_SDRAMC                = 35,  /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER                 = 39,  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET                  = 40,  /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY                   = 41,  /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX                = 42,  /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD             = 43,  /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM                  = 44,  /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI                  = 45,  /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA                   = 50,  /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA                  = 51,  /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR                = 52,  /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN               = 53,  /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC                   = 54,  /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA         = 55,  /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI               = 56,  /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART             = 57,  /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC                  = 58,  /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF                  = 59,  /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI                 = 60,  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP                   = 61,  /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN                  = 62,  /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM                  = 63,  /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI                 = 64,  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC                 = 65,  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C               = 66,  /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_DCP                   = 67,  /*!< Group number for DCP status codes.*/
+    kStatusGroup_MSCAN                 = 68,  /*!< Group number for MSCAN status codes.*/
+    kStatusGroup_ESAI                  = 69,  /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI               = 70,  /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC                  = 71,  /*!< Group number for MMDC status codes. */
+    kStatusGroup_PDM                   = 72,  /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA                  = 73,  /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS                   = 74,  /*!< Group number for ICS status codes. */
+    kStatusGroup_SPDIF                 = 75,  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI           = 76,  /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT             = 77,  /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP           = 78,  /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C                   = 79,  /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1             = 97,  /*!< Group number for LPC_I2C_1 status codes. */
+    kStatusGroup_NOTIFIER              = 98,  /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole          = 99,  /*!< Group number for debug console status codes. */
+    kStatusGroup_SEMC                  = 100, /*!< Group number for SEMC status codes. */
+    kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP                   = 102, /*!< Group number for IAP status codes */
+    kStatusGroup_SFA                   = 103, /*!< Group number for SFA status codes*/
+    kStatusGroup_SPC                   = 104, /*!< Group number for SPC status codes. */
+    kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
+    kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
+    kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */
+
+    kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER      = 123, /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI        = 124, /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C        = 125, /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH      = 126, /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM        = 127, /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG        = 128, /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_HAL_I2S        = 129, /*!< Group number for HAL I2S status codes. */
+    kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
+    kStatusGroup_TIMERMANAGER   = 135, /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER  = 136, /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED            = 137, /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON         = 138, /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM  = 139, /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL          = 140, /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER    = 141, /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST           = 142, /*!< Group number for List status codes. */
+    kStatusGroup_OSA            = 143, /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK    = 144, /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG            = 145, /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP      = 146, /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC          = 148, /*!< Group number for codec status codes. */
+    kStatusGroup_ASRC           = 149, /*!< Group number for codec status ASRC. */
+    kStatusGroup_OTFAD          = 150, /*!< Group number for codec status codes. */
+    kStatusGroup_SDIOSLV        = 151, /*!< Group number for SDIOSLV status codes. */
+    kStatusGroup_MECC           = 152, /*!< Group number for MECC status codes. */
+    kStatusGroup_ENET_QOS       = 153, /*!< Group number for ENET_QOS status codes. */
+    kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
+    kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
+    kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
+    kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */
+    kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
+    kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
+    kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */
+    kStatusGroup_ELS_PKC        = 161, /*!< Group number for ELS PKC status codes. */
+    kStatusGroup_CSS_PKC        = 162, /*!< Group number for CSS PKC status codes. */
+    kStatusGroup_HOSTIF         = 163, /*!< Group number for HOSTIF status codes. */
+    kStatusGroup_CLIF           = 164, /*!< Group number for CLIF status codes. */
+    kStatusGroup_BMA            = 165, /*!< Group number for BMA status codes. */
+    kStatusGroup_NETC           = 166, /*!< Group number for NETC status codes. */
+    kStatusGroup_ELE            = 167, /*!< Group number for ELE status codes. */
+    kStatusGroup_GLIKEY         = 168, /*!< Group number for GLIKEY status codes. */
+};
+
+/*! \public
+ * @brief Generic status return codes.
+ */
+enum
+{
+    kStatus_Success         = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+    kStatus_Fail            = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+    kStatus_ReadOnly        = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+    kStatus_OutOfRange      = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+    kStatus_Timeout         = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+    kStatus_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_Generic, 6),            /*!< Generic status for no transfer in progress. */
+    kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
+    kStatus_NoData =
+        MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*!
+ * @name Min/max macros
+ * @{
+ */
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Suppress fallthrough warning macro */
+/* For switch case code block, if case section ends without "break;" statement, there wil be
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ case section which misses "break;"statement.
+ */
+/* @{ */
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
+
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
+#endif
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ *  if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XTENSA__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
+#endif /* _FSL_COMMON_H_ */

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_common_arm.c

@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common_arm"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[(int32_t)irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+
+/*
+ * When the SYSCON STARTER registers are discontinuous, these functions are
+ * implemented in fsl_power.c.
+ */
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1UL << intNumber;
+    (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERCLR[index] = 1UL << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(DWT)
+/* Use WDT. */
+void MSDK_EnableCpuCycleCounter(void)
+{
+    /* Make sure the DWT trace fucntion is enabled. */
+    if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+    {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* CYCCNT not supported on this device. */
+    assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+    /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
+    if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+    {
+        DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+}
+
+uint32_t MSDK_GetCpuCycleCount(void)
+{
+    return DWT->CYCCNT;
+}
+#endif /* defined(DWT) */
+
+#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
+/* Use software loop. */
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+    SUBS R0, R0, #1
+    CMP  R0, #0
+    BNE  loop
+    BX   LR
+}
+#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    X0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop:                          \n"
+        "    SUB    X0, X0, #1          \n"
+        "    CMP    X0, #0              \n"
+
+        "    BNE    loop                \n"
+        :
+        :
+        : "r0");
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    R0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop:                          \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+        "    SUB    R0, R0, #1          \n"
+#else
+        "    SUBS   R0, R0, #1          \n"
+#endif
+        "    CMP    R0, #0              \n"
+
+        "    BNE    loop                \n"
+        :
+        :
+        : "r0");
+}
+#endif /* defined(__CC_ARM) */
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
+ *  effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
+ *  coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ *  up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+{
+    uint64_t count;
+
+    if (delayTime_us > 0U)
+    {
+        count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+
+        assert(count <= UINT32_MAX);
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
+
+        MSDK_EnableCpuCycleCounter();
+        /* Calculate the count ticks. */
+        count += MSDK_GetCpuCycleCount();
+
+        if (count > UINT32_MAX)
+        {
+            count -= UINT32_MAX;
+            /* Wait for cyccnt overflow. */
+            while (count < MSDK_GetCpuCycleCount())
+            {
+            }
+        }
+
+        /* Wait for cyccnt reach count value. */
+        while (count > MSDK_GetCpuCycleCount())
+        {
+        }
+#else
+        /* Divide value may be different in various environment to ensure delay is precise.
+         * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+         * two instructions in one period, through test here set divide 1.5. Other M cores use
+         * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
+         * not matter because other instructions outside while loop is enough to fill the time.
+         */
+#if (__CORTEX_M == 7)
+        count = count / 3U * 2U;
+#else
+        count = count / 4U;
+#endif
+        DelayLoop((uint32_t)count);
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+    }
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_crc.c

@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.crc"
+#endif
+
+/*! @internal @brief Has data register with name CRC. */
+#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
+#define DATA   CRC
+#define DATALL CRCLL
+#endif
+
+#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-16-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U
+/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#define CRC_DRIVER_DEFAULT_REFLECT_IN false
+/*< Default is no transpose */
+#define CRC_DRIVER_DEFAULT_REFLECT_OUT false
+/*< Default is transpose bytes */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16
+/*< Default is 16-bit CRC protocol */
+#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum
+/*< Default is resutl type is final checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
+
+#if defined(CRC_RSTS)
+#define CRC_RESETS_ARRAY CRC_RSTS
+#endif
+
+/*! @brief CRC type of transpose of read write data */
+typedef enum _crc_transpose_type
+{
+    kCrcTransposeNone         = 0U, /*! No transpose  */
+    kCrcTransposeBits         = 1U, /*! Tranpose bits in bytes  */
+    kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */
+    kCrcTransposeBytes        = 3U, /*! Transpose bytes */
+} crc_transpose_type_t;
+
+/*!
+ * @brief CRC module configuration.
+ *
+ * This structure holds the configuration for the CRC module.
+ */
+typedef struct _crc_module_config
+{
+    uint32_t polynomial;                 /*!< CRC Polynomial, MSBit first.@n
+                                              Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;                       /*!< Starting checksum value */
+    crc_transpose_type_t readTranspose;  /*!< Type of transpose when reading CRC result. */
+    crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */
+    bool complementChecksum;             /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;                  /*!< Selects 16- or 32- bit CRC protocol. */
+} crc_module_config_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(CRC_RESETS_ARRAY)
+/*!
+ * @brief Get instance number for CRC module.
+ *
+ * @param base CRC peripheral base address
+ */
+static uint32_t CRC_GetInstance(CRC_Type *base);
+#endif
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(CRC_RESETS_ARRAY)
+static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS;
+
+/* Reset array */
+static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(CRC_RESETS_ARRAY)
+static uint32_t CRC_GetInstance(CRC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++)
+    {
+        if (s_crcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_crcBases));
+
+    return instance;
+}
+#endif
+
+/*!
+ * @brief Returns transpose type for CRC protocol reflect in parameter.
+ *
+ * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter.
+ *
+ * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
+ */
+static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable)
+{
+    return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
+}
+
+/*!
+ * @brief Returns transpose type for CRC protocol reflect out parameter.
+ *
+ * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter.
+ *
+ * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
+ */
+static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable)
+{
+    return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
+}
+
+/*!
+ * @brief Starts checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts the checksum computation by writing the seed value
+ *
+ * @param base CRC peripheral address.
+ * @param config Pointer to protocol configuration structure.
+ */
+static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
+{
+    uint32_t crcControl;
+
+    /* pre-compute value for CRC control registger based on user configuraton without WAS field */
+    crcControl = 0U | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) |
+                 CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits);
+
+    /* make sure the control register is clear - WAS is deasserted, and protocol is set */
+    base->CTRL = crcControl;
+
+    /* write polynomial register */
+    base->GPOLY = config->polynomial;
+
+    /* write pre-computed control register value along with WAS to start checksum computation */
+    base->CTRL = crcControl | CRC_CTRL_WAS(true);
+
+    /* write seed (initial checksum) */
+    base->DATA = config->seed;
+
+    /* deassert WAS by writing pre-computed CRC control register value */
+    base->CTRL = crcControl;
+}
+
+/*!
+ * @brief Starts final checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts final checksum computation by writing the seed value.
+ * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum
+ *       (output reflection and xor functions are applied).
+ *
+ * @param base CRC peripheral address.
+ * @param protocolConfig Pointer to protocol configuration structure.
+ */
+static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+{
+    crc_module_config_t moduleConfig;
+    /* convert protocol to CRC peripheral module configuration, prepare for final checksum */
+    moduleConfig.polynomial         = protocolConfig->polynomial;
+    moduleConfig.seed               = protocolConfig->seed;
+    moduleConfig.readTranspose      = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
+    moduleConfig.writeTranspose     = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.complementChecksum = protocolConfig->complementChecksum;
+    moduleConfig.crcBits            = protocolConfig->crcBits;
+
+    CRC_ConfigureAndStart(base, &moduleConfig);
+}
+
+/*!
+ * @brief Starts intermediate checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts intermediate checksum computation by writing the seed value.
+ * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value).
+ *
+ * @param base CRC peripheral address.
+ * @param protocolConfig Pointer to protocol configuration structure.
+ */
+static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+{
+    crc_module_config_t moduleConfig;
+    /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
+    moduleConfig.polynomial = protocolConfig->polynomial;
+    moduleConfig.seed       = protocolConfig->seed;
+    moduleConfig.readTranspose =
+        kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
+    moduleConfig.writeTranspose     = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
+    moduleConfig.crcBits            = protocolConfig->crcBits;
+
+    CRC_ConfigureAndStart(base, &moduleConfig);
+}
+
+/*!
+ * brief Enables and configures the CRC peripheral module.
+ *
+ * This function enables the clock gate in the SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts a checksum computation by writing the seed.
+ *
+ * param base CRC peripheral address.
+ * param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* ungate clock */
+    CLOCK_EnableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(CRC_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]);
+#endif
+
+    /* configure CRC module and write the seed */
+    if (config->crcResult == kCrcFinalChecksum)
+    {
+        CRC_SetProtocolConfig(base, config);
+    }
+    else
+    {
+        CRC_SetRawProtocolConfig(base, config);
+    }
+}
+
+/*!
+ * brief Loads default values to the CRC protocol configuration structure.
+ *
+ * Loads default values to the CRC protocol configuration structure. The default values are as follows.
+ * code
+ *   config->polynomial = 0x1021;
+ *   config->seed = 0xFFFF;
+ *   config->reflectIn = false;
+ *   config->reflectOut = false;
+ *   config->complementChecksum = false;
+ *   config->crcBits = kCrcBits16;
+ *   config->crcResult = kCrcFinalChecksum;
+ * endcode
+ *
+ * param config CRC protocol configuration structure.
+ */
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    static const crc_config_t crc16ccit = {
+        CRC_DRIVER_DEFAULT_POLYNOMIAL,          CRC_DRIVER_DEFAULT_SEED,
+        CRC_DRIVER_DEFAULT_REFLECT_IN,          CRC_DRIVER_DEFAULT_REFLECT_OUT,
+        CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS,
+        CRC_DRIVER_DEFAULT_CRC_RESULT,
+    };
+
+    *config = crc16ccit;
+}
+
+/*!
+ * brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to the CRC data register.
+ * The configured type of transpose is applied.
+ *
+ * param base CRC peripheral address.
+ * param data Input data stream, MSByte in data[0].
+ * param dataSize Size in bytes of the input data buffer.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
+    {
+        base->ACCESS8BIT.DATALL = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)(uint32_t)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        base->DATA = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (dataSize != 0U)
+    {
+        base->ACCESS8BIT.DATALL = *data;
+        data++;
+        dataSize--;
+    }
+}
+
+/*!
+ * brief Reads the 32-bit checksum from the CRC module.
+ *
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
+ *
+ * param base CRC peripheral address.
+ * return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
+ */
+uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->DATA;
+}
+
+/*!
+ * brief Reads a 16-bit checksum from the CRC module.
+ *
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
+ *
+ * param base CRC peripheral address.
+ * return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
+ */
+uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    uint32_t retval;
+    uint32_t totr; /* type of transpose read bitfield */
+
+    retval = base->DATA;
+    totr   = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT;
+
+    /* check transpose type to get 16-bit out of 32-bit register */
+    if (totr >= 2U)
+    {
+        /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */
+        retval &= 0xFFFF0000U;
+        retval = retval >> 16U;
+    }
+    else
+    {
+        /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */
+        retval &= 0x0000FFFFU;
+    }
+    return (uint16_t)retval;
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_crc.h

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.0.4.
+ *
+ * Current version: 2.0.4
+ *
+ * Change log:
+ *
+ * - Version 2.0.4
+ *   - Release peripheral from reset if necessary in init function.
+ *
+ * - Version 2.0.3
+ *   - Fix MISRA issues
+ *
+ * - Version 2.0.2
+ *   - Fix MISRA issues
+ *
+ * - Version 2.0.1
+ *   - move DATA and DATALL macro definition from header file to source file
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
+#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC bit width */
+typedef enum _crc_bits
+{
+    kCrcBits16 = 0U, /*!< Generate 16-bit CRC code  */
+    kCrcBits32 = 1U  /*!< Generate 32-bit CRC code  */
+} crc_bits_t;
+
+/*! @brief CRC result type */
+typedef enum _crc_result
+{
+    kCrcFinalChecksum = 0U,       /*!< CRC data register read value is the final checksum.
+                                      Reflect out and final xor protocol features are applied. */
+    kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value).
+                                      Reflect out and final xor protocol feature are not applied.
+                                      Intermediate checksum can be used as a seed for CRC_Init()
+                                      to continue adding data to this checksum. */
+} crc_result_t;
+
+/*!
+ * @brief CRC protocol configuration.
+ *
+ * This structure holds the configuration for the CRC protocol.
+ *
+ */
+typedef struct _crc_config
+{
+    uint32_t polynomial;     /*!< CRC Polynomial, MSBit first.
+                                  Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;           /*!< Starting checksum value */
+    bool reflectIn;          /*!< Reflect bits on input. */
+    bool reflectOut;         /*!< Reflect bits on output. */
+    bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;      /*!< Selects 16- or 32- bit CRC protocol. */
+    crc_result_t crcResult;  /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
+                                CRC_Get32bitResult() */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This function enables the clock gate in the SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts a checksum computation by writing the seed.
+ *
+ * @param base CRC peripheral address.
+ * @param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This function disables the clock gate in the SIM module for the CRC peripheral.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* gate clock */
+    CLOCK_DisableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Loads default values to the CRC protocol configuration structure.
+ *
+ * Loads default values to the CRC protocol configuration structure. The default values are as follows.
+ * @code
+ *   config->polynomial = 0x1021;
+ *   config->seed = 0xFFFF;
+ *   config->reflectIn = false;
+ *   config->reflectOut = false;
+ *   config->complementChecksum = false;
+ *   config->crcBits = kCrcBits16;
+ *   config->crcResult = kCrcFinalChecksum;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure.
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to the CRC data register.
+ * The configured type of transpose is applied.
+ *
+ * @param base CRC peripheral address.
+ * @param data Input data stream, MSByte in data[0].
+ * @param dataSize Size in bytes of the input data buffer.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads the 32-bit checksum from the CRC module.
+ *
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
+ *
+ * @param base CRC peripheral address.
+ * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
+ */
+uint32_t CRC_Get32bitResult(CRC_Type *base);
+
+/*!
+ * @brief Reads a 16-bit checksum from the CRC module.
+ *
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
+ *
+ * @param base CRC peripheral address.
+ * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
+ */
+uint16_t CRC_Get16bitResult(CRC_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_edma_core.h

@@ -0,0 +1,299 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_EDMA_CORE_H_
+#define _FSL_EDMA_CORE_H_
+
+#include "fsl_edma_soc.h"
+
+/*!
+ * @addtogroup edma_core
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4
+#define DMA_CSR_INTMAJOR_MASK          DMA_TCD_CSR_INTMAJOR_MASK
+#define DMA_CSR_INTHALF_MASK           DMA_TCD_CSR_INTHALF_MASK
+#define DMA_CSR_DREQ_MASK              DMA_TCD_CSR_DREQ_MASK
+#define DMA_CSR_ESG_MASK               DMA_TCD_CSR_ESG_MASK
+#define DMA_CSR_BWC_MASK               DMA_TCD_CSR_BWC_MASK
+#define DMA_CSR_BWC(x)                 DMA_TCD_CSR_BWC(x)
+#define DMA_CSR_START_MASK             DMA_TCD_CSR_START_MASK
+#define DMA_CITER_ELINKNO_CITER_MASK   DMA_TCD_CITER_ELINKNO_CITER_MASK
+#define DMA_BITER_ELINKNO_BITER_MASK   DMA_TCD_BITER_ELINKNO_BITER_MASK
+#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA_TCD_CITER_ELINKNO_CITER_SHIFT
+#define DMA_CITER_ELINKYES_CITER_MASK  DMA_TCD_CITER_ELINKYES_CITER_MASK
+#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
+#define DMA_ATTR_SMOD_MASK             DMA_TCD_ATTR_SMOD_MASK
+#define DMA_ATTR_DMOD_MASK             DMA_TCD_ATTR_DMOD_MASK
+#define DMA_CITER_ELINKNO_ELINK_MASK   DMA_TCD_CITER_ELINKNO_ELINK_MASK
+#define DMA_CSR_MAJORELINK_MASK        DMA_TCD_CSR_MAJORELINK_MASK
+#define DMA_BITER_ELINKYES_ELINK_MASK  DMA_TCD_BITER_ELINKYES_ELINK_MASK
+#define DMA_CITER_ELINKYES_ELINK_MASK  DMA_TCD_CITER_ELINKYES_ELINK_MASK
+#define DMA_CSR_MAJORLINKCH_MASK       DMA_TCD_CSR_MAJORLINKCH_MASK
+#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
+#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK
+#define DMA_ATTR_DMOD(x)               DMA_TCD_ATTR_DMOD(x)
+#define DMA_ATTR_SMOD(X)               DMA_TCD_ATTR_SMOD(X)
+#define DMA_BITER_ELINKYES_LINKCH(x)   DMA_TCD_BITER_ELINKYES_LINKCH(x)
+#define DMA_CITER_ELINKYES_LINKCH(x)   DMA_TCD_CITER_ELINKYES_LINKCH(x)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
+#define DMA_ATTR_DSIZE(x)              DMA_TCD_ATTR_DSIZE(x)
+#define DMA_ATTR_SSIZE(x)              DMA_TCD_ATTR_SSIZE(x)
+#define DMA_CSR_DREQ(x)                DMA_TCD_CSR_DREQ(x)
+#define DMA_CSR_MAJORLINKCH(x)         DMA_TCD_CSR_MAJORLINKCH(x)
+#define DMA_CH_MATTR_WCACHE(x)         DMA4_CH_MATTR_WCACHE(x)
+#define DMA_CH_MATTR_RCACHE(x)         DMA4_CH_MATTR_RCACHE(x)
+#define DMA_CH_CSR_SIGNEXT_MASK        DMA4_CH_CSR_SIGNEXT_MASK
+#define DMA_CH_CSR_SIGNEXT_SHIFT       DMA4_CH_CSR_SIGNEXT_SHIFT
+#define DMA_CH_CSR_SWAP_MASK           DMA4_CH_CSR_SWAP_MASK
+#define DMA_CH_CSR_SWAP_SHIFT          DMA4_CH_CSR_SWAP_SHIFT
+#define DMA_CH_SBR_INSTR_MASK          DMA4_CH_SBR_INSTR_MASK
+#define DMA_CH_SBR_INSTR_SHIFT         DMA4_CH_SBR_INSTR_SHIFT
+#define DMA_CH_MUX_SOURCE(x)           DMA4_CH_MUX_SRC(x)
+#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \
+    (!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4))
+#define DMA_CSR_INTMAJOR_MASK          DMA_TCD_CSR_INTMAJOR_MASK
+#define DMA_CSR_INTHALF_MASK           DMA_TCD_CSR_INTHALF_MASK
+#define DMA_CSR_DREQ_MASK              DMA_TCD_CSR_DREQ_MASK
+#define DMA_CSR_ESG_MASK               DMA_TCD_CSR_ESG_MASK
+#define DMA_CSR_BWC_MASK               DMA_TCD_CSR_BWC_MASK
+#define DMA_CSR_BWC(x)                 DMA_TCD_CSR_BWC(x)
+#define DMA_CSR_START_MASK             DMA_TCD_CSR_START_MASK
+#define DMA_CITER_ELINKNO_CITER_MASK   DMA_TCD_CITER_ELINKNO_CITER_MASK
+#define DMA_BITER_ELINKNO_BITER_MASK   DMA_TCD_BITER_ELINKNO_BITER_MASK
+#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA_TCD_CITER_ELINKNO_CITER_SHIFT
+#define DMA_CITER_ELINKYES_CITER_MASK  DMA_TCD_CITER_ELINKYES_CITER_MASK
+#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
+#define DMA_ATTR_SMOD_MASK             DMA_TCD_ATTR_SMOD_MASK
+#define DMA_ATTR_DMOD_MASK             DMA_TCD_ATTR_DMOD_MASK
+#define DMA_CITER_ELINKNO_ELINK_MASK   DMA_TCD_CITER_ELINKNO_ELINK_MASK
+#define DMA_CSR_MAJORELINK_MASK        DMA_TCD_CSR_MAJORELINK_MASK
+#define DMA_BITER_ELINKYES_ELINK_MASK  DMA_TCD_BITER_ELINKYES_ELINK_MASK
+#define DMA_CITER_ELINKYES_ELINK_MASK  DMA_TCD_CITER_ELINKYES_ELINK_MASK
+#define DMA_CSR_MAJORLINKCH_MASK       DMA_TCD_CSR_MAJORLINKCH_MASK
+#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
+#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
+#define DMA_ATTR_DMOD(x)               DMA_TCD_ATTR_DMOD(x)
+#define DMA_ATTR_SMOD(X)               DMA_TCD_ATTR_SMOD(X)
+#define DMA_BITER_ELINKYES_LINKCH(x)   DMA_TCD_BITER_ELINKYES_LINKCH(x)
+#define DMA_CITER_ELINKYES_LINKCH(x)   DMA_TCD_CITER_ELINKYES_LINKCH(x)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
+#define DMA_ATTR_DSIZE(x)              DMA_TCD_ATTR_DSIZE(x)
+#define DMA_ATTR_SSIZE(x)              DMA_TCD_ATTR_SSIZE(x)
+#define DMA_CSR_DREQ(x)                DMA_TCD_CSR_DREQ(x)
+#define DMA_CSR_MAJORLINKCH(x)         DMA_TCD_CSR_MAJORLINKCH(x)
+#define DMA_CH_MUX_SOURCE(x)           DMA_CH_MUX_SRC(x)
+#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \
+    (!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3))
+#define DMA_CSR_INTMAJOR_MASK          DMA4_CSR_INTMAJOR_MASK
+#define DMA_CSR_INTHALF_MASK           DMA4_CSR_INTHALF_MASK
+#define DMA_CSR_DREQ_MASK              DMA4_CSR_DREQ_MASK
+#define DMA_CSR_ESG_MASK               DMA4_CSR_ESG_MASK
+#define DMA_CSR_BWC_MASK               DMA4_CSR_BWC_MASK
+#define DMA_CSR_BWC(x)                 DMA4_CSR_BWC(x)
+#define DMA_CSR_START_MASK             DMA4_CSR_START_MASK
+#define DMA_CITER_ELINKNO_CITER_MASK   DMA4_CITER_ELINKNO_CITER_MASK
+#define DMA_BITER_ELINKNO_BITER_MASK   DMA4_BITER_ELINKNO_BITER_MASK
+#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA4_CITER_ELINKNO_CITER_SHIFT
+#define DMA_CITER_ELINKYES_CITER_MASK  DMA4_CITER_ELINKYES_CITER_MASK
+#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT
+#define DMA_ATTR_SMOD_MASK             DMA4_ATTR_SMOD_MASK
+#define DMA_ATTR_DMOD_MASK             DMA4_ATTR_DMOD_MASK
+#define DMA_CITER_ELINKNO_ELINK_MASK   DMA4_CITER_ELINKNO_ELINK_MASK
+#define DMA_CSR_MAJORELINK_MASK        DMA4_CSR_MAJORELINK_MASK
+#define DMA_BITER_ELINKYES_ELINK_MASK  DMA4_BITER_ELINKYES_ELINK_MASK
+#define DMA_CITER_ELINKYES_ELINK_MASK  DMA4_CITER_ELINKYES_ELINK_MASK
+#define DMA_CSR_MAJORLINKCH_MASK       DMA4_CSR_MAJORLINKCH_MASK
+#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK
+#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK
+#define DMA_ATTR_DMOD(x)               DMA4_ATTR_DMOD(x)
+#define DMA_ATTR_SMOD(X)               DMA4_ATTR_SMOD(X)
+#define DMA_BITER_ELINKYES_LINKCH(x)   DMA4_BITER_ELINKYES_LINKCH(x)
+#define DMA_CITER_ELINKYES_LINKCH(x)   DMA4_CITER_ELINKYES_LINKCH(x)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA4_NBYTES_MLOFFYES_MLOFF(x)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA4_NBYTES_MLOFFYES_DMLOE(x)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA4_NBYTES_MLOFFYES_SMLOE(x)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA4_NBYTES_MLOFFNO_NBYTES(x)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA4_NBYTES_MLOFFYES_NBYTES(x)
+#define DMA_ATTR_DSIZE(x)              DMA4_ATTR_DSIZE(x)
+#define DMA_ATTR_SSIZE(x)              DMA4_ATTR_SSIZE(x)
+#define DMA_CSR_DREQ(x)                DMA4_CSR_DREQ(x)
+#define DMA_CSR_MAJORLINKCH(x)         DMA4_CSR_MAJORLINKCH(x)
+#define DMA_CH_MATTR_WCACHE(x)         DMA4_CH_MATTR_WCACHE(x)
+#define DMA_CH_MATTR_RCACHE(x)         DMA4_CH_MATTR_RCACHE(x)
+#define DMA_CH_CSR_SIGNEXT_MASK        DMA4_CH_CSR_SIGNEXT_MASK
+#define DMA_CH_CSR_SIGNEXT_SHIFT       DMA4_CH_CSR_SIGNEXT_SHIFT
+#define DMA_CH_CSR_SWAP_MASK           DMA4_CH_CSR_SWAP_MASK
+#define DMA_CH_CSR_SWAP_SHIFT          DMA4_CH_CSR_SWAP_SHIFT
+#define DMA_CH_SBR_INSTR_MASK          DMA4_CH_SBR_INSTR_MASK
+#define DMA_CH_SBR_INSTR_SHIFT         DMA4_CH_SBR_INSTR_SHIFT
+#define DMA_CH_MUX_SOURCE(x)           DMA4_CH_MUX_SRC(x)
+#define DMA_CH_CSR_DONE_MASK           DMA4_CH_CSR_DONE_MASK
+#define DMA_CH_CSR_ERQ_MASK            DMA4_CH_CSR_ERQ_MASK
+#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
+/*! intentional empty */
+#endif
+
+/*! @brief DMA error flag */
+#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
+#define DMA_ERR_DBE_FLAG     DMA_ES_DBE_MASK
+#define DMA_ERR_SBE_FLAG     DMA_ES_SBE_MASK
+#define DMA_ERR_SGE_FLAG     DMA_ES_SGE_MASK
+#define DMA_ERR_NCE_FLAG     DMA_ES_NCE_MASK
+#define DMA_ERR_DOE_FLAG     DMA_ES_DOE_MASK
+#define DMA_ERR_DAE_FLAG     DMA_ES_DAE_MASK
+#define DMA_ERR_SOE_FLAG     DMA_ES_SOE_MASK
+#define DMA_ERR_SAE_FLAG     DMA_ES_SAE_MASK
+#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK
+#define DMA_ERR_CPE_FLAG     DMA_ES_CPE_MASK
+#define DMA_ERR_ECX_FLAG     DMA_ES_ECX_MASK
+#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
+#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK
+#endif
+#define DMA_ERR_FLAG DMA_ES_VLD_MASK
+
+/*! @brief get/clear DONE status*/
+#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel)
+#define DMA_GET_DONE_STATUS(base, channel) \
+    ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+/*! @brief enable/disable error interrupt*/
+#define DMA_ENABLE_ERROR_INT(base, channel)  (base->EEI |= ((uint32_t)0x1U << channel))
+#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel)))
+/*! @brief get/clear error status*/
+#define DMA_GET_ERROR_STATUS(base, channel)   (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U)
+#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel)
+/*! @brief get/clear int status*/
+#define DMA_GET_INT_STATUS(base, channel)   ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U))
+#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel)
+
+#else
+
+#define DMA_ERR_DBE_FLAG                     DMA_MP_ES_DBE_MASK
+#define DMA_ERR_SBE_FLAG                     DMA_MP_ES_SBE_MASK
+#define DMA_ERR_SGE_FLAG                     DMA_MP_ES_SGE_MASK
+#define DMA_ERR_NCE_FLAG                     DMA_MP_ES_NCE_MASK
+#define DMA_ERR_DOE_FLAG                     DMA_MP_ES_DOE_MASK
+#define DMA_ERR_DAE_FLAG                     DMA_MP_ES_DAE_MASK
+#define DMA_ERR_SOE_FLAG                     DMA_MP_ES_SOE_MASK
+#define DMA_ERR_SAE_FLAG                     DMA_MP_ES_SAE_MASK
+#define DMA_ERR_ERRCHAN_FLAG                 DMA_MP_ES_ERRCHN_MASK
+#define DMA_ERR_ECX_FLAG                     DMA_MP_ES_ECX_MASK
+#define DMA_ERR_FLAG                         DMA_MP_ES_VLD_MASK
+
+/*! @brief get/clear DONE bit*/
+#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK)
+#define DMA_GET_DONE_STATUS(base, channel) \
+    ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT)
+/*! @brief enable/disable error interupt*/
+#define DMA_ENABLE_ERROR_INT(base, channel)   (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK)
+#define DMA_DISABLE_ERROR_INT(base, channel)  (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK)
+/*! @brief get/clear error status*/
+#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK)
+#define DMA_GET_ERROR_STATUS(base, channel) \
+    (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U)
+/*! @brief get/clear INT status*/
+#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK)
+#define DMA_GET_INT_STATUS(base, channel)   ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U))
+#endif /*FSL_EDMA_SOC_IP_EDMA*/
+
+/*! @brief enable/dsiable MAJOR/HALF INT*/
+#define DMA_ENABLE_MAJOR_INT(base, channel)  (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTMAJOR_MASK)
+#define DMA_ENABLE_HALF_INT(base, channel)   (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTHALF_MASK)
+#define DMA_DISABLE_MAJOR_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK)
+#define DMA_DISABLE_HALF_INT(base, channel)  (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
+
+/*!@brief EDMA tcd align size */
+#define EDMA_TCD_ALIGN_SIZE (32U)
+
+/*!@brief edma core channel struture definition */
+typedef struct _edma_core_mp
+{
+    __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
+    __IO uint32_t MP_ES;  /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
+} edma_core_mp_t;
+
+/*!@brief edma core channel struture definition */
+typedef struct _edma_core_channel
+{
+    __IO uint32_t CH_CSR;   /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
+    __IO uint32_t CH_ES;    /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
+    __IO uint32_t CH_INT;   /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
+    __IO uint32_t CH_SBR;   /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
+    __IO uint32_t CH_PRI;   /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
+    __IO uint32_t CH_MUX;   /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
+    __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+} edma_core_channel_t;
+
+/*!@brief edma core TCD struture definition */
+typedef struct _edma_core_tcd
+{
+    __IO uint32_t SADDR;     /*!< SADDR register, used to save source address */
+    __IO uint16_t SOFF;      /*!< SOFF register, save offset bytes every transfer */
+    __IO uint16_t ATTR;      /*!< ATTR register, source/destination transfer size and modulo */
+    __IO uint32_t NBYTES;    /*!< Nbytes register, minor loop length in bytes */
+    __IO uint32_t SLAST;     /*!< SLAST register */
+    __IO uint32_t DADDR;     /*!< DADDR register, used for destination address */
+    __IO uint16_t DOFF;      /*!< DOFF register, used for destination offset */
+    __IO uint16_t CITER;     /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
+    __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
+    __IO uint16_t CSR;       /*!< CSR register, for TCD control status */
+    __IO uint16_t BITER;     /*!< BITER register, begin minor loop count. */
+} edma_core_tcd_t;
+
+/*!@brief EDMA typedef */
+typedef edma_core_channel_t EDMA_ChannelType;
+typedef edma_core_tcd_t EDMA_TCDType;
+typedef void EDMA_Type;
+
+/*!@brief EDMA base address convert macro */
+#define EDMA_BASE(base)
+#define EDMA_CHANNEL_BASE(base, channel)                                          \
+    ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \
+                             (channel)*EDMA_CHANNEL_ARRAY_STEP(base)))
+#define EDMA_TCD_BASE(base, channel)                                          \
+    ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \
+                         (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
+#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base)))
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_EDMA_CORE_H_ */

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_edma_soc.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_edma_soc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.edma_soc"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void DMA_CH0_DriverIRQHandler(void);
+extern void DMA_CH1_DriverIRQHandler(void);
+extern void DMA_CH2_DriverIRQHandler(void);
+extern void DMA_CH3_DriverIRQHandler(void);
+extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief DMA instance 0, channel 0 IRQ handler.
+ *
+ */
+void DMA_CH0_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 0 */
+    EDMA_DriverIRQHandler(0U, 0U);
+}
+
+/*!
+ * brief DMA instance 0, channel 1 IRQ handler.
+ *
+ */
+void DMA_CH1_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 1 */
+    EDMA_DriverIRQHandler(0U, 1U);
+}
+
+/*!
+ * brief DMA instance 0, channel 2 IRQ handler.
+ *
+ */
+void DMA_CH2_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 2 */
+    EDMA_DriverIRQHandler(0U, 2U);
+}
+
+/*!
+ * brief DMA instance 0, channel 3 IRQ handler.
+ *
+ */
+void DMA_CH3_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 3 */
+    EDMA_DriverIRQHandler(0U, 3U);
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_edma_soc.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_EDMA_SOC_H_
+#define _FSL_EDMA_SOC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup edma_soc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!@brief DMA IP version */
+#define FSL_EDMA_SOC_IP_DMA3 (1)
+#define FSL_EDMA_SOC_IP_DMA4 (0)
+
+/*!@brief DMA base table */
+#define EDMA_BASE_PTRS \
+    {                  \
+        DMA0           \
+    }
+
+#define EDMA_CHN_IRQS                                              \
+    {                                                              \
+        {                                                          \
+            DMA_CH0_IRQn, DMA_CH1_IRQn, DMA_CH2_IRQn, DMA_CH3_IRQn \
+        }                                                          \
+    }
+
+/*!@brief EDMA base address convert macro */
+#define EDMA_CHANNEL_OFFSET           0x1000U
+#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_EDMA_SOC_H_ */

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_eim.c

@@ -0,0 +1,312 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_eim.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.eim"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to EIM bases for each instance. */
+static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to EIM clocks for each instance. */
+static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t EIM_GetInstance(EIM_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++)
+    {
+        if (s_eimBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_eimBases));
+
+    return instance;
+}
+
+/*!
+ * brief EIM module initialization function.
+ *
+ * param base EIM base address.
+ */
+void EIM_Init(EIM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate EIM clock. */
+    CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    base->EIMCR  = 0x00U;
+    base->EICHEN = 0x00U;
+}
+
+/*!
+ * brief Deinitializes the EIM.
+ *
+ */
+void EIM_Deinit(EIM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate EIM clock. */
+    CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
+{
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask);
+            break;
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
+            base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
+            base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case 3U:
+            base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case 4U:
+            base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case 5U:
+            base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case 6U:
+            base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case 7U:
+            base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case 8U:
+            base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask);
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+}
+
+uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
+{
+    uint8_t mask = 0x00U;
+
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
+            mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
+            mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case 3U:
+            mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case 4U:
+            mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case 5U:
+            mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case 6U:
+            mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case 7U:
+            mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case 8U:
+            mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >>
+                             EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT);
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+
+    return mask;
+}
+
+void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
+{
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            base->EICHD0_WORD1 = mask;
+            break;
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
+            base->EICHD1_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
+            base->EICHD2_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case kEIM_MemoryChannelRAMC:
+            base->EICHD3_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case kEIM_MemoryChannelRAMD:
+            base->EICHD4_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case kEIM_MemoryChannelRAME:
+            base->EICHD5_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case kEIM_MemoryChannelRAMF:
+            base->EICHD6_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case kEIM_MemoryChannelLPCACRAM:
+            base->EICHD7_WORD1 = mask;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case kEIM_MemoryChannelPKCRAM:
+            base->EICHD8_WORD1 = mask;
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+}
+
+uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel)
+{
+    uint32_t mask = 0x00U;
+
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
+            mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
+            mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case 3U:
+            mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case 4U:
+            mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case 5U:
+            mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case 6U:
+            mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case 7U:
+            mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case 8U:
+            mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT;
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+
+    return mask;
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_eim.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_EIM_H_
+#define _FSL_EIM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup eim
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version. */
+#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*@}*/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief EIM module initialization function.
+ *
+ * @param base EIM base address.
+ */
+void EIM_Init(EIM_Type *base);
+
+/*!
+ * @brief De-initializes the EIM.
+ *
+ */
+void EIM_Deinit(EIM_Type *base);
+
+/* @} */
+
+/*!
+ * @name functional
+ * @{
+ */
+
+/*!
+ * @brief EIM module enable global error injection.
+ *
+ * @param base EIM base address.
+ * @param mask The interrupts to enable.
+ */
+static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->EIMCR = EIM_EIMCR_GEIEN_MASK;
+    }
+    else
+    {
+        base->EIMCR = ~EIM_EIMCR_GEIEN_MASK;
+    }
+}
+
+/*!
+ * @brief EIM module enable error injection for memory channel n, this function enables the corresponding error
+ * injection channel. The Global Error Injection Enable function must also be called to enable error injection.
+ *
+ * @param base EIM base address.
+ * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
+ */
+static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
+{
+    base->EICHEN |= mask;
+}
+
+/*!
+ * @brief EIM module disable error injection for memory channel n.
+ *
+ * @param base EIM base address.
+ * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
+ */
+static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
+{
+    base->EICHEN &= ~mask;
+}
+
+/*!
+ * @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation
+ * might result in undefined behavior.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @param mask The interrupts to enable.
+ */
+void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
+
+/*!
+ * @brief EIM module get checkbit mask for memory channel n.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @retval return checkbit mask.
+ */
+uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel);
+
+/*!
+ * @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation
+ * might result in undefined behavior.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @param mask The interrupts to enable.
+ */
+void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
+
+/*!
+ * @brief EIM module get databit mask for memory channel n.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @retval return checkbit mask.
+ */
+uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_eqdc.c

@@ -0,0 +1,298 @@
+/*
+ * Copyright 2022, 2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_eqdc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.eqdc"
+#endif
+
+#if defined(EQDC_RSTS)
+#define EQDC_RESETS_ARRAY EQDC_RSTS
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for EQDC module.
+ *
+ * @param base EQDC peripheral base address
+ */
+static uint32_t EQDC_GetInstance(EQDC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to EQDC bases for each instance. */
+static EQDC_Type *const s_eqdcBases[] = EQDC_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to EQDC clocks for each instance. */
+#if defined(QDC_CLOCKS)
+static const clock_ip_name_t s_eqdcClocks[] = QDC_CLOCKS;
+#elif defined(ENC_CLOCKS)
+static const clock_ip_name_t s_eqdcClocks[] = ENC_CLOCKS;
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(EQDC_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_eqdcResets[] = EQDC_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t EQDC_GetInstance(EQDC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_eqdcBases); instance++)
+    {
+        if (s_eqdcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_eqdcBases));
+
+    return instance;
+}
+
+/*
+ * Initializes the EQDC module.
+ *
+ * This function initializes the EQDC by enabling the IP bus clock (optional).
+ *
+ * param base   EQDC peripheral base address.
+ * param psConfig Pointer to configuration structure.
+ */
+void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)
+{
+    assert(NULL != psConfig);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_eqdcClocks[EQDC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(EQDC_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_eqdcResets[EQDC_GetInstance(base)]);
+#endif
+
+    /* Initialize Double-set registers */
+    EQDC_ClearBufferedRegisterLoadUpdateMode(base);
+    EQDC_ClearEqdcLdok(base);
+
+    /* Counter value. */
+    EQDC_SetPositionCounterValue(base, psConfig->positionCounterValue);
+
+    /* Initial value. */
+    EQDC_SetInitialPositionValue(base, psConfig->positionInitialValue);
+
+    /* Modulus value. */
+    EQDC_SetPositionModulusValue(base, psConfig->positionModulusValue);
+
+    /* Compare value. */
+    EQDC_SetPositionCompare0Value(base, psConfig->positionCompareValue[0]);
+    EQDC_SetPositionCompare1Value(base, psConfig->positionCompareValue[1]);
+    EQDC_SetPositionCompare2Value(base, psConfig->positionCompareValue[2]);
+    EQDC_SetPositionCompare3Value(base, psConfig->positionCompareValue[3]);
+
+    EQDC_SetEqdcLdok(base);
+    while (EQDC_GetEqdcLdok(base) != 0U)
+    {
+    }
+
+    /* Watchdog. */
+    EQDC_SetWatchdogTimeout(base, psConfig->watchdogTimeoutValue);
+
+    /* EQDC_IMR. */
+    base->IMR = EQDC_IMR_FPHA(psConfig->filterPhaseA) | EQDC_IMR_FPHB(psConfig->filterPhaseB) |
+                EQDC_IMR_FIND_PRE(psConfig->filterIndPre) | EQDC_IMR_FHOM_ENA(psConfig->filterHomEna);
+
+    /* EQDC_FILT. */
+    base->FILT = EQDC_FILT_PRSC(psConfig->prescaler) | /* Prescaler used by LASTEDGE and POSDPER. */
+                 EQDC_FILT_FILT_CS(psConfig->filterClockSourceselection) |
+                 EQDC_FILT_FILT_CNT(psConfig->filterSampleCount) | EQDC_FILT_FILT_PER(psConfig->filterSamplePeriod);
+
+    /* EQDC_CTRL. */
+    base->CTRL = EQDC_CTRL_W1C_FLAGS |                                /* W1C flags. */
+                 (uint16_t)psConfig->homeEnableInitPosCounterMode |  /* HOME Enable trigger. */
+                 (uint16_t)psConfig->indexPresetInitPosCounterMode | /* INDEX Preset trigger. */
+                 EQDC_CTRL_REV(psConfig->enableReverseDirection) |   /* Reverse direction. */
+                 EQDC_CTRL_WDE(psConfig->enableWatchdog) |           /* Enable watchdog. */
+                 EQDC_CTRL_DMAEN(psConfig->enableDma);               /* Enable Dma. */
+
+    /* Set mode of count. */
+    EQDC_SetCountMode(base, psConfig->countMode); /* eqdcoder count mode. */
+
+    /* EQDC_CTRL2. */
+    base->CTRL2 =
+        EQDC_CTRL2_ONCE(psConfig->countOnce) |
+        EQDC_CTRL2_INITPOS(psConfig->enableTriggerInitPositionCounter) | /* TRIGGER initializes position counter. */
+#if (defined(FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD) && FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD)
+        EQDC_CTRL2_EMIP(psConfig->enableIndexInitPositionCounter)|       /* Index Event Edge Mark initializes position counter */
+#endif /* FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD */
+        EQDC_CTRL2_PMEN(psConfig->enablePeriodMeasurement) |             /* Enable period measurement. */
+        EQDC_CTRL2_OUTCTL(psConfig->outputPulseMode) |                   /* Output pulse. */
+        EQDC_CTRL2_REVMOD(psConfig->revolutionCountCondition) |          /* Revolution count condition. */
+        EQDC_CTRL2_LDMOD(psConfig->bufferedRegisterLoadMode) | /* Buffered register load (Update) mode select. */
+        EQDC_CTRL2_UPDPOS(psConfig->enableTriggerClearPositionRegisters) | /* TRIGGER clears position register. */
+        EQDC_CTRL2_UPDHLD(psConfig->enableTriggerHoldPositionRegisters);   /* TRIGGER loads position registers. */
+
+    /* Set mode of operation. */
+    EQDC_SetOperateMode(base, psConfig->operateMode); /* eqdcoder work mode. */
+
+    /* Enable interrupts. */
+    EQDC_EnableInterrupts(base, psConfig->enabledInterruptsMask);
+}
+
+/*
+ * De-initializes the EQDC module.
+ *
+ * This function deinitializes the EQDC by:
+ * 1. Disables the IP bus clock (optional).
+ *
+ * param base EQDC peripheral base address.
+ */
+void EQDC_Deinit(EQDC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_eqdcClocks[EQDC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * Gets an available pre-defined configuration.
+ *
+ * The default value are:
+ *    psConfig->enableReverseDirection              = false;
+ *    psConfig->countOnce                           = false;
+ *    psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode;
+ *    psConfig->countMode                           = kEQDC_QuadratureX4;
+ *    psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
+ *    psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
+ *    psConfig->enableIndexInitPositionCounter      = false;
+ *    psConfig->enableDma                           = false;
+ *    psConfig->bufferedRegisterLoadMode            = false;
+ *    psConfig->enableTriggerInitPositionCounter    = false;
+ *    psConfig->enableTriggerClearPositionRegisters = false;
+ *    psConfig->enableTriggerHoldPositionRegisters  = false;
+ *    psConfig->enableWatchdog                      = false;
+ *    psConfig->watchdogTimeoutValue                = 0xFFFFU;
+ *    psConfig->filterPhaseA                        = 0U;
+ *    psConfig->filterPhaseB                        = 0U;
+ *    psConfig->filterIndPre                        = 0U;
+ *    psConfig->filterHomEna                        = 0U;
+ *    psConfig->filterClockSourceselection          = false;
+ *    psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
+ *    psConfig->filterSamplePeriod                  = 0U;
+ *    psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
+ *    psConfig->positionCompareValue[0]         = 0xFFFFFFFFU;
+ *    psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
+ *    psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
+ *    psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
+ *    psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
+ *    psConfig->positionModulusValue                = 0U;
+ *    psConfig->positionInitialValue                = 0U;
+ *    psConfig->positionCounterValue                = 0U;
+ *    psConfig->enablePeriodMeasurement             = false;
+ *    psConfig->prescaler                           = kEQDC_Prescaler1;
+ *    psConfig->enabledInterruptsMask               = 0U;
+ *
+ * param psConfig Pointer to configuration structure.
+ */
+void EQDC_GetDefaultConfig(eqdc_config_t *psConfig)
+{
+    assert(NULL != psConfig);
+
+    psConfig->enableReverseDirection              = false;
+    psConfig->countOnce                           = false;
+    psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode; /*!< Decode Mode. */
+    psConfig->countMode                           = kEQDC_QuadratureX4;
+    psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
+    psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
+#if (defined(FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD) && FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD)
+    psConfig->enableIndexInitPositionCounter      = false;
+#endif /* FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD */
+    psConfig->enableDma                           = false;
+    psConfig->bufferedRegisterLoadMode            = false;
+    psConfig->enableTriggerInitPositionCounter    = false;
+    psConfig->enableTriggerClearPositionRegisters = false;
+    psConfig->enableTriggerHoldPositionRegisters  = false;
+    psConfig->enableWatchdog                      = false;
+    psConfig->watchdogTimeoutValue                = 0xFFFFU;
+    psConfig->filterPhaseA                        = 0U;
+    psConfig->filterPhaseB                        = 0U;
+    psConfig->filterIndPre                        = 0U;
+    psConfig->filterHomEna                        = 0U;
+    psConfig->filterClockSourceselection          = false;
+    psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
+    psConfig->filterSamplePeriod                  = 0U;
+    psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
+    psConfig->positionCompareValue[0]             = 0xFFFFFFFFU;
+    psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
+    psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
+    psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
+    psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
+    psConfig->positionModulusValue                = 0U;
+    psConfig->positionInitialValue                = 0U;
+    psConfig->positionCounterValue                = 0U;
+    psConfig->enablePeriodMeasurement             = false;
+    psConfig->prescaler                           = kEQDC_Prescaler1;
+    psConfig->enabledInterruptsMask               = 0U;
+}
+
+/*
+ * Initializes the mode of operation.
+ *
+ * The Quadrature Decoder operates in following 4 operation modes:
+ *   1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0)
+ *   2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1)
+ *   3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0)
+ *   4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1)
+ *
+ * param base   EQDC peripheral base address.
+ * param psConfig Pointer to configuration structure.
+ */
+void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)
+{
+    switch (operateMode)
+    {
+        case kEQDC_QuadratureDecodeOperationMode:
+            base->CTRL &= ~EQDC_CTRL_PH1_MASK;
+            base->CTRL2 &= ~EQDC_CTRL2_OPMODE_MASK;
+            break;
+
+        case kEQDC_QuadratureCountOperationMode:
+            base->CTRL &= ~EQDC_CTRL_PH1_MASK;
+            base->CTRL2 |= EQDC_CTRL2_OPMODE_MASK;
+            break;
+
+        case kEQDC_SinglePhaseDecodeOperationMode:
+            base->CTRL |= EQDC_CTRL_PH1_MASK;
+            base->CTRL2 &= ~EQDC_CTRL2_OPMODE_MASK;
+            break;
+
+        case kEQDC_SinglePhaseCountOperationMode:
+            base->CTRL |= EQDC_CTRL_PH1_MASK;
+            base->CTRL2 |= EQDC_CTRL2_OPMODE_MASK;
+            break;
+
+        default:
+            assert(false);
+            break;
+    }
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_erm.c

@@ -0,0 +1,317 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_erm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.erm"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to ERM bases for each instance. */
+static ERM_Type *const s_ermBases[] = ERM_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to ERM clocks for each instance. */
+static const clock_ip_name_t s_ermClocks[] = ERM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t ERM_GetInstance(ERM_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_ermBases); instance++)
+    {
+        if (s_ermBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_ermBases));
+
+    return instance;
+}
+
+/*!
+ * brief ERM module initialization function.
+ *
+ * param base ERM base address.
+ */
+void ERM_Init(ERM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate ERM clock. */
+    CLOCK_EnableClock(s_ermClocks[ERM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    base->CR0 = 0x00U;
+#ifdef ERM_CR1_ENCIE8_MASK
+    base->CR1 = 0x00U;
+#endif
+    base->SR0 = 0xFFFFFFFFU;
+#ifdef ERM_SR1_SBC8_MASK
+    base->SR1 = 0xFFFFFFFFU;
+#endif
+}
+
+/*!
+ * brief Deinitializes the ERM.
+ *
+ */
+void ERM_Deinit(ERM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate ERM clock. */
+    CLOCK_DisableClock(s_ermClocks[ERM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel)
+{
+    uint32_t absoluteErrorAddress = 0x00U;
+
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            absoluteErrorAddress = base->EAR0;
+            break;
+#ifdef ERM_EAR1_EAR_MASK
+        case 1U:
+            absoluteErrorAddress = base->EAR1;
+            break;
+#endif
+#ifdef ERM_EAR2_EAR_MASK
+        case 2U:
+            absoluteErrorAddress = base->EAR2;
+            break;
+#endif
+#ifdef ERM_EAR3_EAR_MASK
+        case 3U:
+            absoluteErrorAddress = base->EAR3;
+            break;
+#endif
+#ifdef ERM_EAR4_EAR_MASK
+        case 4U:
+            absoluteErrorAddress = base->EAR4;
+            break;
+#endif
+#ifdef ERM_EAR5_EAR_MASK
+        case 5U:
+            absoluteErrorAddress = base->EAR5;
+            break;
+#endif
+#ifdef ERM_EAR6_EAR_MASK
+        case 6U:
+            absoluteErrorAddress = base->EAR6;
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+
+    return absoluteErrorAddress;
+}
+
+uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel)
+{
+    uint32_t syndrome = 0x00U;
+
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT;
+            break;
+#ifdef ERM_SYN1_SYNDROME_MASK
+        case 1U:
+            syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN2_SYNDROME_MASK
+        case 2U:
+            syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN3_SYNDROME_MASK
+        case 3U:
+            syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN4_SYNDROME_MASK
+        case 4U:
+            syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN5_SYNDROME_MASK
+        case 5U:
+            syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN6_SYNDROME_MASK
+        case 6U:
+            syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN7_SYNDROME_MASK
+        case 7U:
+            syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN8_SYNDROME_MASK
+        case 8U:
+            syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT;
+            break;
+#endif
+#ifdef ERM_SYN9_SYNDROME_MASK
+        case 8U:
+            syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT;
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+
+    return syndrome;
+}
+
+uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
+{
+    uint32_t count = 0x00U;
+
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT;
+            break;
+#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK
+        case 1U:
+            count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK
+        case 2U:
+            count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK
+        case 3U:
+            count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK
+        case 4U:
+            count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK
+        case 5U:
+            count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
+        case 6U:
+            count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK
+        case 7U:
+            count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK
+        case 8U:
+            count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK
+        case 9U:
+            count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT;
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+
+    return count;
+}
+
+void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
+{
+    switch ((uint8_t)channel)
+    {
+        case 0U:
+            base->CORR_ERR_CNT0 = 0x00U;
+            break;
+
+#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK
+        case 1U:
+            base->CORR_ERR_CNT1 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK
+        case 2U:
+            base->CORR_ERR_CNT2 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK
+        case 3U:
+            base->CORR_ERR_CNT3 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK
+        case 4U:
+            base->CORR_ERR_CNT4 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK
+        case 5U:
+            base->CORR_ERR_CNT5 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
+        case 6U:
+            base->CORR_ERR_CNT6 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
+        case 7U:
+            base->CORR_ERR_CNT7 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK
+        case 8U:
+            base->CORR_ERR_CNT8 = 0x00U;
+            break;
+#endif
+#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK
+        case 9U:
+            base->CORR_ERR_CNT9 = 0x00U;
+            break;
+#endif
+        default:
+            assert(NULL);
+            break;
+    }
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_erm.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_ERM_H_
+#define _FSL_ERM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup erm
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version. */
+#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*@}*/
+
+/*!
+ * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
+ *
+ * This structure contains the settings for all of the ERM interrupt configurations.
+ */
+enum
+{
+    kERM_SingleCorrectionIntEnable = 0x08U, /*!< Single Correction Interrupt Notification enable.*/
+    kERM_NonCorrectableIntEnable   = 0x04U, /*!< Non-Correction Interrupt Notification enable.*/
+
+    kERM_AllInterruptsEnable = 0xFFFFFFFFUL, /*!< All Interrupts enable */
+};
+
+/*!
+ * @brief ERM interrupt status, _erm_interrupt_flag.
+ *
+ * This provides constants for the ERM event status for use in the ERM functions.
+ */
+enum
+{
+    kERM_SingleBitCorrectionIntFlag = 0x08U, /*!< Single-Bit Correction Event.*/
+    kERM_NonCorrectableErrorIntFlag = 0x04U, /*!< Non-Correctable Error Event.*/
+
+    kERM_AllIntsFlag = 0xFFFFFFFFUL, /*!< All Events. */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and de-initialization
+ * @{
+ */
+
+/*!
+ * @brief ERM module initialization function.
+ *
+ * @param base ERM base address.
+ */
+void ERM_Init(ERM_Type *base);
+
+/*!
+ * @brief De-initializes the ERM.
+ *
+ */
+void ERM_Deinit(ERM_Type *base);
+
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+/*!
+ * @brief ERM enable interrupts.
+ *
+ * @param base ERM peripheral base address.
+ * @param channel memory channel.
+ * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region.
+ * Refer to "_erm_interrupt_enable" enumeration.
+ */
+static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)
+{
+    uint32_t temp = 0x00U;
+    if ((uint32_t)channel <= 0x07U)
+    {
+        temp = base->CR0;
+        base->CR0 =
+            (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U));
+    }
+#ifdef ERM_CR1_ESCIE8_MASK
+    else
+    {
+        temp      = base->CR1;
+        base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) |
+                    (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
+    }
+#endif
+}
+
+/*!
+ * @brief ERM module disable interrupts.
+ *
+ * @param base ERM base address.
+ * @param channel memory channel.
+ * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region.
+ * Refer to "_erm_interrupt_enable" enumeration.
+ */
+static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)
+{
+    if ((uint32_t)channel <= 0x07U)
+    {
+        base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U));
+    }
+#ifdef ERM_CR1_ESCIE8_MASK
+    else
+    {
+        base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
+    }
+#endif
+}
+
+/*!
+ * @brief Gets ERM interrupt flags.
+ *
+ * @param base ERM peripheral base address.
+ * @return ERM event flags.
+ */
+static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel_t channel)
+{
+    if ((uint32_t)channel <= 0x07U)
+    {
+        return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U);
+    }
+#ifdef ERM_SR1_SBC8_MASK
+    else
+    {
+        return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U));
+    }
+#else
+    {
+        return 0;
+    }
+#endif
+}
+
+/*!
+ * @brief ERM module clear interrupt status flag.
+ *
+ * @param base ERM base address.
+ * @param mask event flag to clear. Refer to "_erm_interrupt_flag" enumeration.
+ */
+static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)
+{
+    if ((uint32_t)channel <= 0x07U)
+    {
+        base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U);
+    }
+#ifdef ERM_SR1_SBC8_MASK
+    else
+    {
+        base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U);
+    }
+#endif
+}
+
+/* @} */
+
+/*!
+ * @name functional
+ * @{
+ */
+
+/*!
+ * @brief ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n.
+ *
+ * @param base ERM base address.
+ * @param channel memory channel.
+ * @retval memory error absolute address.
+ */
+
+uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel);
+
+/*!
+ * @brief ERM get syndrome, which identifies the pertinent bit position on a correctable, single-bit data inversion or a
+ * non-correctable, single-bit address inversion. The syndrome value does not provide any additional diagnostic
+ * information on non-correctable, multi-bit inversions.
+ *
+ * @param base ERM base address.
+ * @param channel memory channel.
+ * @retval syndrome value.
+ */
+uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel);
+
+/*!
+ * @brief ERM get error count, which  records the count value of the number of correctable ECC error events for Memory
+ * n. Non-correctable errors are considered a serious fault, so the ERM does not provide any mechanism to count
+ * non-correctable errors. Only correctable errors are counted.
+ *
+ * @param base ERM base address.
+ * @param channel memory channel.
+ * @retval error count.
+ */
+uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel);
+
+/*!
+ * @brief ERM reset error count.
+ *
+ * @param base ERM base address.
+ * @param channel memory channel.
+ */
+void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_freqme.c

@@ -0,0 +1,155 @@
+/*
+ * Copyright 2021-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_freqme.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme"
+#endif
+
+#if defined(FREQME_RSTS_N)
+#define FREQME_RESETS_ARRAY FREQME_RSTS_N
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static uint32_t FREQME_GetInstance(FREQME_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Array to map freqme instance number to base address. */
+static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to FREQME clocks for each instance. */
+static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FREQME_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY;
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t FREQME_GetInstance(FREQME_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0U; instance < ARRAY_SIZE(s_freqmeBases); instance++)
+    {
+        if (s_freqmeBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_freqmeBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle.
+ *
+ * param base FREQME peripheral base address.
+ * param config The pointer to module basic configuration, please refer to freq_measure_config_t.
+ */
+void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config)
+{
+    assert(config);
+
+    uint32_t tmp32 = 0UL;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable FREQME clock. */
+    CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FREQME_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]);
+#endif
+
+    if (config->startMeasurement)
+    {
+        tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK;
+    }
+    tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) |
+             FREQME_CTRL_W_PULSE_MODE(config->operateMode);
+    if (config->operateMode == kFREQME_FreqMeasurementMode)
+    {
+        tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor);
+    }
+    else
+    {
+        tmp32 |= FREQME_CTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity);
+    }
+
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * brief Get default configuration.
+ *
+ * code
+ *      config->operateMode = kFREQME_FreqMeasurementMode;
+ *      config->operateModeAttribute.refClkScaleFactor = 0U;
+ *      config->enableContinuousMode                   = false;
+ *      config->startMeasurement                       = false;
+ * endcode
+ *
+ * param config The pointer to module basic configuration, please refer to freq_measure_config_t.
+ */
+void FREQME_GetDefaultConfig(freq_measure_config_t *config)
+{
+    assert(config);
+
+    (void)memset(config, 0, sizeof(*config));
+
+    config->operateMode                            = kFREQME_FreqMeasurementMode;
+    config->operateModeAttribute.refClkScaleFactor = 0U;
+    config->enableContinuousMode                   = false;
+    config->startMeasurement                       = false;
+}
+
+/*!
+ * brief Calculate the frequency of selected target clock.
+ *
+ * note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE.
+ *
+ * note This function only useful when the operate mode is selected as frequency measurement mode.
+ *
+ * param base FREQME peripheral base address.
+ * param refClkFrequency The frequency of reference clock.
+ * return The frequency of target clock, if the output result is 0, please check the module's operate mode.
+ */
+uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency)
+{
+    uint32_t measureResult = 0UL;
+    uint32_t targetFreq    = 0UL;
+    uint64_t tmp64         = 0ULL;
+
+    while ((base->CTRL_R & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL)
+    {
+    }
+
+    if (!FREQME_CheckOperateMode(base))
+    {
+        measureResult = base->CTRL_R & FREQME_CTRL_R_RESULT_MASK;
+        tmp64         = ((uint64_t)measureResult - 2ULL) * (uint64_t)refClkFrequency;
+        targetFreq    = (uint32_t)(tmp64 / (1ULL << (uint64_t)FREQME_GetReferenceClkScaleValue(base)));
+    }
+
+    return targetFreq;
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_freqme.h

@@ -0,0 +1,441 @@
+/*
+ * Copyright 2021-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FREQME_
+#define _FSL_FREQME_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_freqme
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FREQME driver version 2.1.2. */
+#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*@}*/
+
+/*!
+ * @brief The enumeration of interrupt status flags.
+ * @anchor _freqme_interrupt_status_flags
+ */
+enum _freqme_interrupt_status_flags
+{
+    kFREQME_UnderflowInterruptStatusFlag = FREQME_CTRLSTAT_LT_MIN_STAT_MASK,   /*!< Indicate the measurement is
+                                                                                     just done and the result is less
+                                                                                     than minimun value. */
+    kFREQME_OverflowInterruptStatusFlag = FREQME_CTRLSTAT_GT_MAX_STAT_MASK,    /*!< Indicate the measurement is
+                                                                                     just done and the result is greater
+                                                                                     than maximum value. */
+    kFREQME_ReadyInterruptStatusFlag = FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is
+                                                                                 just done and the result is ready to
+                                                                                 read. */
+    kFREQME_AllInterruptStatusFlags = FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK |
+                                      FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt
+                                                                                        status flags. */
+};
+
+/*!
+ * @brief The enumeration of interrupts, including underflow interrupt, overflow interrupt,
+ * and result ready interrupt.
+ * @anchor _freqme_interrupt_enable
+ */
+enum _freqme_interrupt_enable
+{
+    kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is
+                                                                                   less than minimum value. */
+    kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK,  /*!< Enable interrupt when the result is
+                                                                                   greater than maximum value. */
+    kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a
+                                                                                 measurement completes and the result
+                                                                                 is ready. */
+};
+
+/*!
+ * @brief FREQME module operate mode enumeration, including frequency measurement mode
+ * and pulse width measurement mode.
+ */
+typedef enum _freqme_operate_mode
+{
+    kFREQME_FreqMeasurementMode = 0U,  /*!< The module works in the frequency measurement mode. */
+    kFREOME_PulseWidthMeasurementMode, /*!< The module works in the pulse width measurement mode. */
+} freqme_operate_mode_t;
+
+/*!
+ * @brief The enumeration of pulse polarity.
+ */
+typedef enum _freqme_pulse_polarity
+{
+    kFREQME_PulseHighPeriod = 0U, /*!< Select high period of the reference clock. */
+    kFREQME_PulseLowPeriod,       /*!< Select low period of the reference clock. */
+} freqme_pulse_polarity_t;
+
+/*!
+ * @brief The union of operate mode attribute.
+ * @note If the operate mode is selected as frequency measurement mode the member \b refClkScaleFactor should be used,
+ * if the operate mode is selected as pulse width measurement mode the member \b pulsePolarity should be used.
+ */
+typedef union _freqme_mode_attribute
+{
+    uint8_t refClkScaleFactor;             /*!< Only useful in frequency measurement operate mode,
+                                               used to set the reference clock counter scaling factor. */
+    freqme_pulse_polarity_t pulsePolarity; /*!< Only Useful in pulse width measurement operate mode,
+                                               used to set period polarity. */
+} freqme_mode_attribute_t;
+
+/*!
+ * @brief The structure of freqme module basic configuration,
+ * including operate mode, operate mode attribute and so on.
+ */
+typedef struct _freq_measure_config
+{
+    freqme_operate_mode_t operateMode; /*!< Select operate mode, please refer to @ref freqme_operate_mode_t. */
+    freqme_mode_attribute_t operateModeAttribute; /*!< Used to set the attribute of the selected operate mode, if
+                                                the operate mode is selected as @ref kFREQME_FreqMeasurementMode
+                                                set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is
+                                                selected as @ref kFREOME_PulseWidthMeasurementMode, please set
+                                                freqme_mode_attribute_t::pulsePolarity.  */
+
+    bool enableContinuousMode; /*!< Enable/disable continuous mode, if continuous mode is enable,
+                                  the measurement is performed continuously and the result for the
+                                  last completed measurement is available in the result register. */
+    bool startMeasurement;
+} freq_measure_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Basic Control APIs
+ * @{
+ */
+/*!
+ * @brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle.
+ *
+ * @param base FREQME peripheral base address.
+ * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t.
+ */
+void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config);
+
+/*!
+ * @brief Get default configuration.
+ *
+ * @code
+ *      config->operateMode = kFREQME_FreqMeasurementMode;
+ *      config->operateModeAttribute.refClkScaleFactor = 0U;
+ *      config->enableContinuousMode                   = false;
+ *      config->startMeasurement                       = false;
+ * @endcode
+ *
+ * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t.
+ */
+void FREQME_GetDefaultConfig(freq_measure_config_t *config);
+
+/*!
+ * @brief Start frequency or pulse width measurement process.
+ *
+ * @param base FREQME peripheral base address.
+ */
+static inline void FREQME_StartMeasurementCycle(FREQME_Type *base)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+    tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK;
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * @brief Force the termination of any measurement cycle currently in progress and resets RESULT or just reset
+ * RESULT if the module in idle state.
+ *
+ * @param base FREQME peripheral base address.
+ */
+static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * @brief Enable/disable Continuous mode.
+ *
+ * @param base FREQME peripheral base address.
+ * @param enable Used to enable/disable continuous mode,
+ *              - \b true Enable Continuous mode.
+ *              - \b false Disable Continuous mode.
+ */
+static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+    if (enable)
+    {
+        tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK;
+    }
+
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * @brief Check whether continuous mode is enabled.
+ *
+ * @param base FREQME peripheral base address.
+ * @retval True Continuous mode is enabled, the measurement is performed continuously.
+ * @retval False Continuous mode is disabled.
+ */
+static inline bool FREQME_CheckContinuousMode(FREQME_Type *base)
+{
+    return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL);
+}
+
+/*!
+ * @brief Set operate mode of freqme module.
+ *
+ * @param base FREQME peripheral base address.
+ * @param operateMode The operate mode to be set, please refer to @ref freqme_operate_mode_t.
+ */
+static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+    if (operateMode == kFREOME_PulseWidthMeasurementMode)
+    {
+        tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK;
+    }
+
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * @brief Check module's operate mode.
+ *
+ * @param base FREQME peripheral base address.
+ * @retval True Pulse width measurement mode.
+ * @retval False Frequency measurement mode.
+ */
+static inline bool FREQME_CheckOperateMode(FREQME_Type *base)
+{
+    return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL);
+
+}
+
+/*!
+ * @brief Set the minimum expected value for the measurement result.
+ *
+ * @param base FREQME peripheral base address.
+ * @param minValue The minimum value to set, please note that this value is 31 bits width.
+ */
+static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue)
+{
+    base->MIN = minValue;
+}
+
+/*!
+ * @brief Set the maximum expected value for the measurement result.
+ *
+ * @param base FREQME peripheral base address.
+ * @param maxValue The maximum value to set, please note that this value is 31 bits width.
+ */
+static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue)
+{
+    base->MAX = maxValue;
+}
+
+/*! @} */
+
+/*!
+ * @name Frequency Measurement Mode Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Calculate the frequency of selected target clock。
+ *
+ * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE.
+ *
+ * @note This function only useful when the operate mode is selected as frequency measurement mode.
+ *
+ * @param base FREQME peripheral base address.
+ * @param refClkFrequency The frequency of reference clock.
+ * @return The frequency of target clock the unit is Hz, if the output result is 0, please check the module's
+ *         operate mode.
+ */
+uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency);
+
+/*!
+ * @brief Get reference clock scaling factor.
+ *
+ * @param base FREQME peripheral base address.
+ * @return Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale.
+ */
+static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base)
+{
+    return (uint8_t)(base->CTRLSTAT & FREQME_CTRLSTAT_REF_SCALE_MASK);
+}
+
+/*! @} */
+
+/*!
+ * @name Pulse Width Measurement Mode Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Set pulse polarity when operate mode is selected as Pulse Width Measurement mode.
+ *
+ * @param base FREQME peripheral base address.
+ * @param pulsePolarity The pulse polarity to be set, please refer to @ref freqme_pulse_polarity_t.
+ */
+static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+
+    if (pulsePolarity != kFREQME_PulseHighPeriod)
+    {
+        tmp32 |= FREQME_CTRL_W_PULSE_POL_MASK;
+    }
+
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * @brief Check pulse polarity when the operate mode is selected as pulse width measurement mode.
+ *
+ * @param base FREQME peripheral base address.
+ * @retval True Low period.
+ * @retval False High period.
+ */
+static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base)
+{
+    return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_POL_MASK) != 0UL);
+}
+
+/*!
+ * @brief Get measurement result, if operate mode is selected as pulse width measurement mode this function can
+ * be used to calculate pulse width.
+ *
+ * @note Pulse width = counter result / Frequency of target clock.
+ *
+ * @param base FREQME peripheral base address.
+ * @return Measurement result.
+ */
+static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base)
+{
+    return base->CTRL_R & FREQME_CTRL_R_RESULT_MASK;
+}
+
+/*! @} */
+
+/*!
+ * @name Status Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Get interrupt status flags, such as overflow interrupt status flag,
+ * underflow interrupt status flag, and so on.
+ *
+ * @param base FREQME peripheral base address.
+ * @return Current interrupt status flags, should be the OR'ed value of @ref _freqme_interrupt_status_flags.
+ */
+static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base)
+{
+    return (base->CTRLSTAT & (uint32_t)kFREQME_AllInterruptStatusFlags);
+}
+
+/*!
+ * @brief Clear interrupt status flags.
+ *
+ * @param base FREQME peripheral base address.
+ * @param statusFlags The combination of interrupt status flags to clear,
+ *                    should be the OR'ed value of @ref _freqme_interrupt_status_flags.
+ */
+static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags)
+{
+    base->CTRLSTAT |= statusFlags;
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupt Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Enable interrupts, such as result ready interrupt, overflow interrupt and so on.
+ *
+ * @param base FREQME peripheral base address.
+ * @param masks The mask of interrupts to enable, should be the OR'ed value of @ref _freqme_interrupt_enable.
+ */
+static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK |
+               FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+
+    tmp32 |= masks;
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * @brief Disable interrupts, such as result ready interrupt, overflow interrupt and so on.
+ *
+ * @param base FREQME peripheral base address.
+ * @param masks The mask of interrupts to disable, should be the OR'ed value of @ref _freqme_interrupt_enable.
+ */
+static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->CTRLSTAT;
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK |
+               FREQME_CTRLSTAT_RESULT_READY_STAT_MASK | masks);
+
+    base->CTRL_W = tmp32;
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* __FSL_FREQME_H__ */

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_glikey.c

@@ -0,0 +1,397 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_glikey.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.glikey"
+#endif
+
+#define GLIKEY_SFR_LOCK   0x05u
+#define GLIKEY_SFR_UNLOCK 0x0Au
+
+/* Define to select between write to CTRL0_WR_0 or CTRL1_WR_1 */
+#define WR_EN0 (0x0Fu)
+#define WR_EN1 (0xF0u)
+
+#define WR_EN0_VALUE_SHIFT (0u)
+#define WR_EN1_VALUE_SHIFT (16u)
+
+#define CTRL_SEL_CODEWORD_SHIFT (24u)
+
+#define WR_0_INIT (0x2u)
+#define WR_1_INIT (0x0u)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static inline void Glikey_Internal_Set_WR_0(GLIKEY_Type *base, uint32_t value);
+static inline void Glikey_Internal_Set_WR_1(GLIKEY_Type *base, uint32_t value);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * Weak implementation of GLIKEY IRQ, should be re-defined by user when using GLIKEY IRQ
+
+__WEAK void GLIKEY0_DriverIRQHandler(void)
+{
+    // GLIKEY generates IRQ until corresponding bit in STATUS is cleared by calling
+    // GLIKEY_ClearStatusFlags();
+    //
+}
+*/
+
+static inline void Glikey_Internal_Set_WR_0(GLIKEY_Type *base, uint32_t value)
+{
+    uint32_t ctrl0 = ((GLIKEY_Type *)base)->CTRL_0;
+
+    /* Clear WR_0 */
+    ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WR_EN_0_MASK);
+
+    /* Assign value */
+    ((GLIKEY_Type *)base)->CTRL_0 = ctrl0 | GLIKEY_CTRL_0_WR_EN_0(value);
+}
+
+static inline void Glikey_Internal_Set_WR_1(GLIKEY_Type *base, uint32_t value)
+{
+    uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
+
+    /* Clear WR_1 */
+    ctrl1 = ctrl1 & (~GLIKEY_CTRL_1_WR_EN_1_MASK);
+
+    /* Assign value */
+    ((GLIKEY_Type *)base)->CTRL_1 = ctrl1 | GLIKEY_CTRL_1_WR_EN_1(value);
+}
+
+uint32_t GLIKEY_GetStatus(GLIKEY_Type *base)
+{
+    return ((GLIKEY_Type *)base)->STATUS;
+}
+
+status_t GLIKEY_IsLocked(GLIKEY_Type *base)
+{
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked == retCode)
+    {
+        return kStatus_GLIKEY_NotLocked;
+    }
+    else
+    {
+        return kStatus_GLIKEY_Locked;
+    }
+}
+
+status_t GLIKEY_CheckLock(GLIKEY_Type *base)
+{
+    uint32_t sfrLock = (((GLIKEY_Type *)base)->CTRL_1 & GLIKEY_CTRL_1_SFR_LOCK_MASK) >> GLIKEY_CTRL_1_SFR_LOCK_SHIFT;
+
+    if (GLIKEY_SFR_UNLOCK != sfrLock) /* Locked */
+    {
+        return kStatus_GLIKEY_LockedError;
+    }
+
+    return kStatus_GLIKEY_NotLocked;
+}
+
+status_t GLIKEY_GetVersion(GLIKEY_Type *base, uint32_t *result)
+{
+    *result = ((GLIKEY_Type *)base)->VERSION;
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_SyncReset(GLIKEY_Type *base)
+{
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* Set CTRL_0.SFT_RST = 1 */
+    ((GLIKEY_Type *)base)->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK;
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value)
+{
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    ((GLIKEY_Type *)base)->INTR_CTRL = GLIKEY_INTR_CTRL_INT_EN(value);
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value)
+{
+    *value = ((GLIKEY_Type *)base)->INTR_CTRL & GLIKEY_INTR_CTRL_INT_EN_MASK;
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)
+{
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    ((GLIKEY_Type *)base)->INTR_CTRL |= GLIKEY_INTR_CTRL_INT_CLR_MASK;
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)
+{
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    ((GLIKEY_Type *)base)->INTR_CTRL |= GLIKEY_INTR_CTRL_INT_SET_MASK;
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_Lock(GLIKEY_Type *base)
+{
+    /* Check if SFR_LOCK is locked */
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode) /* Glikey is not locked -> lock */
+    {
+        uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
+        /* Clear SFR_LOCK */
+        ctrl1 = ctrl1 & (~GLIKEY_CTRL_1_SFR_LOCK_MASK);
+        /* Lock Gliekey */
+        ((GLIKEY_Type *)base)->CTRL_1 = ctrl1 | GLIKEY_CTRL_1_SFR_LOCK(GLIKEY_SFR_LOCK);
+    }
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index)
+{
+    /* Set CTRL_1.READ_INDEX = index */
+    uint32_t ctr1Val = ((GLIKEY_Type *)base)->CTRL_1;
+    /* Clear READ_INDEX */
+    ctr1Val = ctr1Val & (~GLIKEY_CTRL_1_READ_INDEX_MASK);
+    /* Set index value */
+    ((GLIKEY_Type *)base)->CTRL_1 = ctr1Val | GLIKEY_CTRL_1_READ_INDEX(index);
+
+    /* Check ERROR_STATUS */
+    if (0u != (GLIKEY_GetStatus(base) & GLIKEY_STATUS_ERROR_STATUS_MASK))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if STATUS.LOCK_STATUS is 0 */
+    if (0u == (GLIKEY_GetStatus(base) & GLIKEY_STATUS_LOCK_STATUS_MASK))
+    {
+        return kStatus_GLIKEY_NotLocked;
+    }
+    else
+    {
+        return kStatus_GLIKEY_Locked;
+    }
+}
+
+status_t GLIKEY_LockIndex(GLIKEY_Type *base)
+{
+    /* Check if Glikey SFR locked */
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* Check if FSM is in WR_EN state */
+    uint32_t state = (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT;
+    if (GLIKEY_FSM_WR_EN == state)
+    {
+        /* Set WR_EN0 = b11 */
+        ((GLIKEY_Type *)base)->CTRL_0 |= GLIKEY_CTRL_0_WR_EN_0(0x3u);
+        return kStatus_GLIKEY_Locked;
+    }
+    else
+    {
+        return kStatus_GLIKEY_DisabledError;
+    }
+}
+
+status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
+{
+    /* Check if Glikey SFR locked */
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* Check if index is locked */
+    retCode = GLIKEY_IsIndexLocked(base, index);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* CTRL0 */
+    uint32_t ctrl0 = ((GLIKEY_Type *)base)->CTRL_0;
+    /* Clear old index */
+    ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WRITE_INDEX_MASK);
+    /* Clear old CTRL0.WR_EN_0 */
+    ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WR_EN_0_MASK);
+    /* Set new index */
+    ctrl0 |= GLIKEY_CTRL_0_WRITE_INDEX(index);
+
+    /* Start the enable process by writting 0x01 to CTRL0.WR_EN_0 */
+    ctrl0 = ctrl0 | (0x01u << GLIKEY_CTRL_0_WR_EN_0_SHIFT);
+
+    /* Write to CTRL0 (new index and WR_EN_0 = 0x01) */
+    ((GLIKEY_Type *)base)->CTRL_0 = ctrl0;
+
+    /* CTRL1 */
+    uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
+    /* Clear CTRL1.WR_EN_1 */
+    ctrl1 &= ~GLIKEY_CTRL_1_WR_EN_1_MASK;
+    //((GLIKEY_Type*)base)->CTRL_1 = ctrl1;
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)
+{
+    /* Check if Glikey SFR locked */
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* Set correctly we_en0 and wr_en1 according to codeword */
+    /* Select between CTRL0/CTRL1 */
+    if (WR_EN1 == (codeword >> CTRL_SEL_CODEWORD_SHIFT))
+    {
+        Glikey_Internal_Set_WR_1(base, codeword >> WR_EN1_VALUE_SHIFT);
+    }
+    else if (WR_EN0 == (codeword >> CTRL_SEL_CODEWORD_SHIFT))
+    {
+        Glikey_Internal_Set_WR_0(base, codeword >> WR_EN0_VALUE_SHIFT);
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+
+    if (0u != (GLIKEY_GetStatus(base) & GLIKEY_STATUS_ERROR_STATUS_MASK))
+    {
+        return kStatus_GLIKEY_DisabledError;
+    }
+
+    /* Validate codeword - check if XXYZ^UUVW == 0xFFFF */
+    if (0xFFFFu != (((codeword) ^ (codeword >> 16u)) & 0xFFFFu))
+    {
+        return kStatus_Fail;
+    }
+
+    return kStatus_Success;
+}
+
+status_t GLIKEY_EndOperation(GLIKEY_Type *base)
+{
+    /* Check if Glikey SFR locked */
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    // check state
+    uint32_t state = (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT;
+
+    switch (state)
+    {
+        case GLIKEY_FSM_LOCKED:
+        {
+            /* If locked -> try to go to init with wr_en0 = WR_0_INIT (0x02); wr_en1 = WR_1_INIT (0x00) */
+            Glikey_Internal_Set_WR_0(base, WR_0_INIT);
+            Glikey_Internal_Set_WR_1(base, WR_1_INIT);
+
+            /* if still locked return locked - need to change index */
+            if (GLIKEY_FSM_LOCKED ==
+                (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT)
+            {
+                return kStatus_GLIKEY_Locked;
+            }
+
+            return kStatus_Success;
+        }
+
+        case GLIKEY_FSM_SSR_RESET:
+        case GLIKEY_FSM_WR_EN:
+        {
+            /* If FSM in RESET -> wr_en0 = WR_0_INIT; wr_en1 = WR_1_INIT */
+            /* If FSM in WR_EN -> wr_en0 = WR_0_INIT; wr_en1 = WR_1_INIT */
+            Glikey_Internal_Set_WR_0(base, WR_0_INIT);
+            Glikey_Internal_Set_WR_1(base, WR_1_INIT);
+
+            return kStatus_Success;
+        }
+
+        default:
+            /* Disabled error */
+            return kStatus_GLIKEY_DisabledError;
+    }
+}
+
+status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index)
+{
+    /* Check if Glikey SFR locked */
+    uint32_t retCode = GLIKEY_CheckLock(base);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* Check if index is locked */
+    retCode = GLIKEY_IsIndexLocked(base, index);
+    if (kStatus_GLIKEY_NotLocked != retCode)
+    {
+        return retCode;
+    }
+
+    /* Check if FSM is in INIT state */
+    uint32_t state = (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT;
+    if (GLIKEY_FSM_INIT == state)
+    {
+        /* CTRL0.WRITE_INDEX = index */
+        uint32_t ctrl0 = ((GLIKEY_Type *)base)->CTRL_0;
+        /* Clear index */
+        ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WRITE_INDEX_MASK);
+        /* Write new value */
+        ((GLIKEY_Type *)base)->CTRL_0 = ctrl0 | GLIKEY_CTRL_0_WRITE_INDEX(index);
+
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_GLIKEY_DisabledError;
+    }
+}

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_glikey.h

@@ -0,0 +1,312 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_GLIKEY_H_
+#define _FSL_GLIKEY_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup GLIKEY
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines GLIKEY driver version 2.0.0.
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version
+ */
+#define FSL_GLIKEY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+
+enum
+{
+    kStatus_GLIKEY_LockedError =
+        MAKE_STATUS(kStatusGroup_GLIKEY, 0x1u), /*!< GLIKEY status for locked SFR registers (unexpected) . */
+    kStatus_GLIKEY_NotLocked = MAKE_STATUS(kStatusGroup_GLIKEY, 0x2u), /*!< GLIKEY status for unlocked SFR registers. */
+    kStatus_GLIKEY_Locked    = MAKE_STATUS(kStatusGroup_GLIKEY, 0x3u), /*!< GLIKEY status for locked SFR registers. */
+    kStatus_GLIKEY_DisabledError = MAKE_STATUS(kStatusGroup_GLIKEY, 0x4u), /*!< GLIKEY status for disabled error. */
+};
+
+/* [Design]
+    Value: XX YZ UU VW
+    - XX: F0: write to WR_EN1, 0F: do not write to WR_EN1
+    - UU: F0: write to WR_EN0, 0F: do not write to WR_EN0
+    - Y:  equal to <step> ^ W
+    - Z:  value to write to WR_EN1 or equal to ~W
+    - V:  equal to <step> ^ Z
+    - W:  value to write to WR_EN0 or equal to ~Z
+    Invariant: XXYZ ^ UUVW == 0xFFFF
+*/
+#define GLIKEY_CODEWORD_STEP1   ((uint32_t)0xF0C10F3EU) /*< Codeword for transition from STEP1 --> STEP2 */
+#define GLIKEY_CODEWORD_STEP2   ((uint32_t)0x0F1DF0E2U) /*< Codeword for transition from STEP2 --> STEP3 */
+#define GLIKEY_CODEWORD_STEP3   ((uint32_t)0xF0B00F4FU) /*< Codeword for transition from STEP3 --> STEP4 */
+#define GLIKEY_CODEWORD_STEP4   ((uint32_t)0x0F4EF0B1U) /*< Codeword for transition from STEP4 --> STEP5 */
+#define GLIKEY_CODEWORD_STEP5   ((uint32_t)0xF0810F7EU) /*< Codeword for transition from STEP5 --> STEP6 */
+#define GLIKEY_CODEWORD_STEP6   ((uint32_t)0x0F5DF0A2U) /*< Codeword for transition from STEP6 --> STEP7 */
+#define GLIKEY_CODEWORD_STEP7   ((uint32_t)0xF0700F8FU) /*< Codeword for transition from STEP7 --> STEP8 */
+#define GLIKEY_CODEWORD_STEP_EN ((uint32_t)0x0FFFF000U) /*< Codeword for transition from STEP 4/8 --> WR_EN */
+
+#define GLIKEY_FSM_WR_DIS    0x0Bu
+#define GLIKEY_FSM_INIT      0x16u
+#define GLIKEY_FSM_STEP1     0x2Cu
+#define GLIKEY_FSM_STEP2     0x58u
+#define GLIKEY_FSM_STEP3     0xB0u
+#define GLIKEY_FSM_STEP4     0x160u
+#define GLIKEY_FSM_LOCKED    0xC01u
+#define GLIKEY_FSM_WR_EN     0x1802u
+#define GLIKEY_FSM_SSR_RESET 0x1005u
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+extern void GLIKEY0_IRQHandler(void);
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name GLIKEY Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Retreives the current status of Glikey.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Glikey status information
+ */
+uint32_t GLIKEY_GetStatus(GLIKEY_Type *base);
+
+/*!
+ * @brief Get if Glikey is locked
+ *
+ * This operation returns the locking status of Glikey.
+ *
+ * @return Status
+ * @retval kStatus_GLIKEY_Locked if locked
+ * @retval kStatus_GLIKEY_NotLocked if unlocked
+ */
+status_t GLIKEY_IsLocked(GLIKEY_Type *base);
+
+/*!
+ * @brief Check if Glikey is locked
+ *
+ * This operation returns the locking status of Glikey.
+ *
+ * @return Status kStatus_Success if success
+ * @retval kStatus_GLIKEY_LockedError if locked
+ * @retval kStatus_GLIKEY_NotLocked if unlocked
+ */
+status_t GLIKEY_CheckLock(GLIKEY_Type *base);
+
+/*!
+ * @brief Retreives the version and configuration of Glikey.
+ *
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ * @param[out]  result  Pointer which will be filled with the Glikey hardware version
+ *
+ * @return Status kStatus_Success if success
+ */
+status_t GLIKEY_GetVersion(GLIKEY_Type *base, uint32_t *result);
+
+/*!
+ * @brief Perform a synchronous reset of Glikey.
+ *
+ * This function performs a synchrounous reset of the Glikey. This results in:
+ * - Glikey will return to the INIT state, unless it is in the LOCK state
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError
+ */
+status_t GLIKEY_SyncReset(GLIKEY_Type *base);
+
+/*!
+ * @brief Set interrupt enable flag of Glikey.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ * @param[in]   value   Value to set the interrupt enable flag to, see #[TODO: add reference to constants]
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError
+ */
+status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value);
+
+/*!
+ * @brief Get interrupt enable flag of Glikey.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ * @param[out]  value   Pointer which will be filled with the interrupt enable status, see #[TODO: add reference to
+ * constants]
+ *
+ * @return Status kStatus_Success if success
+ */
+status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value);
+
+/*!
+ * @brief Clear the interrupt status flag of Glikey.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError
+ */
+status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base);
+
+/*!
+ * @brief Set the interrupt status flag of Glikey.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError
+ */
+status_t GLIKEY_SetIntStatus(GLIKEY_Type *base);
+
+/*!
+ * @brief Lock Glikey SFR (Special Function Registers) interface
+ *
+ * This operation locks the Glikey SFR interface if it is not locked yet.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Status kStatus_Success if success
+ */
+status_t GLIKEY_Lock(GLIKEY_Type *base);
+
+/*!
+ * @brief Lock Glikey index
+ *
+ * This operation is used to lock a Glikey index. It can only be executed from the WR_EN state,
+ * executing it from any other state will result in Glikey entering WR_DIS state. When this happens
+ * Glikey requires a reset (synchrous or asynchronous) to go back to INIT state.
+ * If the Glikey SFR lock is active this operation will return an error.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError
+ */
+status_t GLIKEY_LockIndex(GLIKEY_Type *base);
+
+/*!
+ * @brief Check if Glikey index is locked
+ *
+ * This operation returns the locking status of Glikey index.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ * @param[in]   index   The index of the Glikey instance
+ *
+ * @return kStatus_GLIKEY_Locked if locked, kStatus_GLIKEY_NotLocked if unlocked
+ * Possible errors: kStatus_Fail
+ */
+status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index);
+
+/**
+ * @brief Start Glikey enable
+ *
+ * This operation is used to set a new index and start a the sequence to enable it. It needs to be
+ * started from the INIT state. If the new index is already locked Glikey will go to LOCKED state,
+ * otherwise it will go to STEP1 state.
+ * If this operation is used when Glikey is in any state other than INIT Glikey will go to WR_DIS
+ * state. It can only recover from this state through a reset (synchrounous or asyncrhonous).
+ * If the Glikey SFR lock is active this operation will return an error.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ * @param[in]   index   The index of the Glikey instance
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail
+ */
+status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index);
+
+/**
+ * @brief Continue Glikey enable
+ *
+ * This operation is used to progress through the different states of the state machine, starting
+ * from STEP1 until the state WR_EN is reached. Each next state of the state machine can only be
+ * reached by providing the right codeword to this function. If anything goes wrong the state machine
+ * will go to WR_DIS state and can only recover from it through a reset (synchrous or asynchronous).
+ * If the Glikey SFR lock is active this operation will return an error.
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ * @param[in]   codeword   Encoded word for progressing to next FSM state (see GLIKEY_CODEWORD_STEPx/EN)
+ *
+ * @return Status kStatus_Success if success
+ * Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail, kStatus_GLIKEY_DisabledError
+ */
+/* [Design]
+    - Check if Glikey is locked
+        if ( GLIKEY_LOCKED == GLIKEY_GET_SFR_LOCK(base) ) return NXPCLGLIKEY_STATUS_LOCKED_ERROR
+    - Decode the codeword and write to Glikey CTRL[]
+        Write GLIKEY_CTRL(base, EnableSelect, EnableValue)
+    - Check if an error occured
+        - the only possible error here is FSM error which results in a transition to WR_DIS state
+        - alternatively this can be confirmed by checking FSM state value
+    - Only now we will check if the codeword itself is valid
+        - this is done in this order to assure that the state machine reaches WR_DIS state when needed
+        - check if XXYZ^UUVW == 0xFFFF and return kStatus_Fail when it fails
+    - Return kStatus_Success
+*/
+status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword);
+
+/**
+ * @brief End Glikey operation
+ *
+ * This operation is used to end a Glikey operation. It can only be executed from the WR_EN, LOCKED
+ * and RESET states. Executing it from any other state will result in Glikey entering WR_DIS state.
+ * When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state.
+ * After this operation Glikey will go to INIT state or stay in LOCKED state when the index was locked.
+ * If the Glikey SFR lock is active this operation will return an error.
+ *
+ * @return A code-flow protected error code (see @ref nxpCsslFlowProtection)
+ *
+ * @param[in]   base    The base address of the Glikey instance
+ *
+ * @return Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked
+ * Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError
+ */
+status_t GLIKEY_EndOperation(GLIKEY_Type *base);
+
+/**
+ * @brief Reset Glikey index
+ *
+ * This operation is used to reset a Glikey index. It can only be executed from the INIT state,
+ * executing it from any other state will result in Glikey entering WR_DIS state. When this happens
+ * Glikey requires a reset (synchrous or asynchronous) to go back to INIT state.
+ * If the Glikey SFR lock is active or the index is locked this operation will return an error.
+ *
+ * @return A code-flow protected error code (see @ref nxpCsslFlowProtection)
+ *
+ * @return Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked
+ * Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError
+ */
+status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif   /* __cplusplus */
+
+/*! @}*/ /* end of group glikey */
+
+#endif   /* _FSL_GLIKEY_H_ */

bsp/nxp/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_gpio.c

@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gpio"
+#endif
+
+#if defined(GPIO_RSTS)
+#define GPIO_RESETS_ARRAY GPIO_RSTS
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#endif
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+#if defined(GPIO_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * @brief Gets the GPIO instance according to the GPIO base
+ *
+ * @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+ * @retval GPIO instance
+ */
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gpioBases));
+
+    return instance;
+}
+#endif
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param pin    GPIO port pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(NULL != config);
+
+#if defined(GPIO_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
+#endif
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
+    }
+    else
+    {
+        GPIO_PinWrite(base, pin, config->outputLogic);
+        base->PDDR |= GPIO_FIT_REG((1UL << pin));
+    }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
+void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
+{
+    info->feature = (uint16_t)base->VERID;
+    info->minor   = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT);
+    info->major   = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT);
+}
+#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * brief Reads the GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = (uint8_t)GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+#else
+/*!
+ * brief Read the GPIO interrupt status flags.
+ *
+ * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
+ * return The current GPIO's interrupt status flag.
+ *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
+ *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
+ */
+uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)
+{
+    return base->ISFR[0];
+}
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
+ * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
+ * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
+ *
+ * return The current GPIO's interrupt status flag based on the selected interrupt channel.
+ *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
+ *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
+ */
+uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)
+{
+    assert(channel < 2U);
+    return base->ISFR[channel];
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
+/*!
+ * brief Read individual pin's interrupt status flag.
+ *
+ * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
+ * param pin GPIO specific pin number.
+ * return The current selected pin's interrupt status flag.
+ */
+uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
+{
+    return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT);
+}
+#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * brief Clears multiple GPIO pin interrupt status flags.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param mask GPIO pin number macro
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance       = (uint8_t)GPIO_GetInstance(base);
+    portBase       = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+#else
+/*!
+ * brief Clears GPIO pin interrupt status flags.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param mask GPIO pin number macro
+ */
+void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    base->ISFR[0] = GPIO_FIT_REG(mask);
+}
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param mask GPIO pin number macro
+ * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
+ */
+void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)
+{
+    assert(channel < 2U);
+    base->ISFR[channel] = GPIO_FIT_REG(mask);
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
+/*!
+ * brief Clear GPIO individual pin's interrupt status flag.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
+ * param pin GPIO specific pin number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)
+{
+    base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U));
+}
+#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
+ * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
+ * endian data convention.
+ *
+ * param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param attribute GPIO checker attribute
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
+    base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT);
+#else
+    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
+#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */
+}
+#endif
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * @brief Gets the FGPIO instance according to the GPIO base
+ *
+ * @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+ * @retval FGPIO instance
+ */
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
+    {
+        if (s_fgpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_fgpioBases));
+
+    return instance;
+}
+#endif
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+/*!
+ * brief Initializes the FGPIO peripheral.
+ *
+ * This function ungates the FGPIO clock.
+ *
+ * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ */
+void FGPIO_PortInit(FGPIO_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate FGPIO periphral clock */
+    CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+/*!
+ * brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration:
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * param pin    FGPIO port pin number
+ * param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(NULL != config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1UL << pin);
+    }
+    else
+    {
+        FGPIO_PinWrite(base, pin, config->outputLogic);
+        base->PDDR |= (1UL << pin);
+    }
+}
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * brief Reads the FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base)
+{
+    uint8_t instance;
+    instance = (uint8_t)FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+/*!
+ * brief Clears the multiple FGPIO pin interrupt status flag.
+ *
+ * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * param mask FGPIO pin number macro
+ */
+void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    instance = (uint8_t)FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase       = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+#endif
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * param attribute FGPIO checker attribute
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */