mirror of
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[NXP]升级RT1170-EVK开发板SDK2.12版本(#6264)
This commit is contained in:
xjy198903
GitHub
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@@ -1,13 +1,13 @@
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/*
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** ###################################################################
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** Version: rev. 1.0, 2020-12-29
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** Build: b210910
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** Build: b220216
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2021 NXP
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** Copyright 2016-2022 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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@@ -269,6 +269,8 @@
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/* @brief Has no ITRM register. */
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#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1)
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/* @brief Has hardware trigger. */
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#define FSL_FEATURE_DAC12_HAS_HW_TRIGGER (0)
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/* DCDC module features */
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@@ -377,6 +379,8 @@
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#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
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/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
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#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
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/* @brief ENET Has Extra Clock Gate.(RW610). */
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#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0)
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/* ENET_QOS module features */
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@@ -423,7 +427,7 @@
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/* @brief Has FLEXRAM_MAGIC_ADDR. */
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#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
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/* @brief If FLEXRAM has ECC function. */
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#define FSL_FEATURE_FLEXRAM_HAS_ECC (1)
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#define FSL_FEATURE_FLEXRAM_HAS_ECC (0)
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/* FLEXSPI module features */
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@@ -516,6 +520,18 @@
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#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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/* @brief Has offset trim (register OFSTRIM). */
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#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
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/* @brief Has power select (bitfield CFG[PWRSEL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
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/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
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/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
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/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
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/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
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/* @brief Conversion averaged bitfiled width. */
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#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
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/* LPI2C module features */
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@@ -671,6 +687,10 @@
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#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
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/* @brief PDM Has Low Frequency */
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#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1)
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/* @brief CLKDIV factor in Medium, High and Low Quality modes */
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#define FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR (93)
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/* @brief CLKDIV factor in Very Low Quality modes */
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#define FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR (43)
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/* PIT module features */
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@@ -797,11 +817,11 @@
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/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
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#define FSL_FEATURE_SNVS_HAS_SRTC (1)
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/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
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#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (1)
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#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0)
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/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
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#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (1)
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#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0)
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/* @brief Number of TAMPER. */
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#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10)
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#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0)
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/* SSARC_HP module features */
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File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
@@ -1,13 +1,13 @@
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/*
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** ###################################################################
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** Version: rev. 1.0, 2020-12-29
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** Build: b210910
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** Build: b220216
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||||
**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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||||
** Copyright 2016-2021 NXP
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** Copyright 2016-2022 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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@@ -265,6 +265,8 @@
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/* @brief Has no ITRM register. */
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#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1)
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/* @brief Has hardware trigger. */
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#define FSL_FEATURE_DAC12_HAS_HW_TRIGGER (0)
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/* DCDC module features */
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@@ -373,6 +375,8 @@
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#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
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/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
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#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
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/* @brief ENET Has Extra Clock Gate.(RW610). */
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#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0)
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/* ENET_QOS module features */
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@@ -419,7 +423,7 @@
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/* @brief Has FLEXRAM_MAGIC_ADDR. */
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#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
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/* @brief If FLEXRAM has ECC function. */
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#define FSL_FEATURE_FLEXRAM_HAS_ECC (1)
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#define FSL_FEATURE_FLEXRAM_HAS_ECC (0)
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/* FLEXSPI module features */
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@@ -501,6 +505,18 @@
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#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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/* @brief Has offset trim (register OFSTRIM). */
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#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
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/* @brief Has power select (bitfield CFG[PWRSEL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
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/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
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/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
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/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
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/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
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/* @brief Conversion averaged bitfiled width. */
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#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
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/* LPI2C module features */
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@@ -651,6 +667,10 @@
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#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
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/* @brief PDM Has Low Frequency */
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#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1)
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/* @brief CLKDIV factor in Medium, High and Low Quality modes */
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#define FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR (93)
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/* @brief CLKDIV factor in Very Low Quality modes */
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#define FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR (43)
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/* PIT module features */
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@@ -777,11 +797,11 @@
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/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
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#define FSL_FEATURE_SNVS_HAS_SRTC (1)
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/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
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#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (1)
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#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0)
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/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
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#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (1)
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#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0)
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/* @brief Number of TAMPER. */
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#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10)
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#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0)
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/* SSARC_HP module features */
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+136
-136
@@ -1,136 +1,136 @@
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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
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/*
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** ###################################################################
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** Processors: MIMXRT1176AVM8A_cm4
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** MIMXRT1176CVM8A_cm4
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** MIMXRT1176DVMAA_cm4
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: IMXRT1170RM, Rev 1, 02/2021
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** Version: rev. 1.0, 2020-12-29
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** Build: b210709
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2021 NXP
|
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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#if (defined(__ram_vector_table__))
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#define __ram_vector_table_size__ 0x00000400
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#else
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#define __ram_vector_table_size__ 0x00000000
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#endif
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#define m_flash_config_start 0x08000400
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#define m_flash_config_size 0x00000C00
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#define m_ivt_start 0x08001000
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#define m_ivt_size 0x00001000
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#define m_interrupts_start 0x08002000
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#define m_interrupts_size 0x00000400
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#define m_text_start 0x08002400
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#define m_text_size 0x00FFDC00
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#define m_qacode_start 0x1FFE0000
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#define m_qacode_size 0x00020000
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#define m_interrupts_ram_start 0x20000000
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#define m_interrupts_ram_size __ram_vector_table_size__
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#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
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#define m_data_size (0x00020000 - m_interrupts_ram_size)
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#define m_ncache_start 0x20280000
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#define m_ncache_size 0x00040000
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#define m_data2_start 0x20240000
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#define m_data2_size 0x00040000
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size 0x0400
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
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RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
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* (.boot_hdr.conf, +FIRST)
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}
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RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
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* (.boot_hdr.ivt, +FIRST)
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* (.boot_hdr.boot_data)
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* (.boot_hdr.dcd_data)
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}
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#else
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LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
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#endif
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VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
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* (.isr_vector,+FIRST)
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}
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ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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#if (defined(__ram_vector_table__))
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VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
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}
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#else
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VECTOR_RAM m_interrupts_start EMPTY 0 {
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}
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#endif
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#if (defined(__heap_noncacheable__))
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RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
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#else
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RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
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#endif
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.ANY (+RW +ZI)
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* (RamFunction)
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* (DataQuickAccess)
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}
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#if (!defined(__heap_noncacheable__))
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ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
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}
|
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#endif
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ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
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}
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RW_m_ram_text m_qacode_start m_qacode_size { ;
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* (CodeQuickAccess)
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}
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#if (defined(__heap_noncacheable__))
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RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
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#else
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RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
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#endif
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* (NonCacheable.init)
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* (*NonCacheable)
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}
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#if (defined(__heap_noncacheable__))
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ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
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}
|
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RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
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#else
|
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RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x08000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x08001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x08002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x08002400
|
||||
#define m_text_size 0x00FFDC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_interrupts_ram_start 0x20000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x00020000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_ncache_start 0x20280000
|
||||
#define m_ncache_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x20240000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
* (RamFunction)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
+164
-143
@@ -1,143 +1,164 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x08000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x08001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x08002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x08002400
|
||||
#define m_text_size 0x00FFDC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_interrupts_ram_start 0x80000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x03000000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x20240000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data2 m_data2_start m_data2_size {
|
||||
* (RamFunction)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x08000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x08001000
|
||||
#define m_ivt_size 0x00000020
|
||||
|
||||
#define m_boot_data_start 0x08001020
|
||||
#define m_boot_data_size 0x00000010
|
||||
|
||||
#define m_dcd_data_start 0x08001030
|
||||
#define m_dcd_data_size 0x000006E8
|
||||
|
||||
#define m_xmcd_data_start 0x08001040
|
||||
#define m_xmcd_data_size 0x00000204
|
||||
|
||||
#define m_interrupts_start 0x08002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x08002400
|
||||
#define m_text_size 0x00FFDC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_interrupts_ram_start 0x80000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x03000000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x20240000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_boot_data_text m_boot_data_start FIXED m_boot_data_size { ; load address = execution address
|
||||
* (.boot_hdr.boot_data, +FIRST)
|
||||
}
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
RW_m_dcd_data_text m_dcd_data_start FIXED m_dcd_data_size { ; load address = execution address
|
||||
* (.boot_hdr.dcd_data, +FIRST)
|
||||
}
|
||||
#elif defined(XIP_BOOT_HEADER_XMCD_ENABLE) && (XIP_BOOT_HEADER_XMCD_ENABLE == 1)
|
||||
RW_m_xmcd_data_text m_xmcd_data_start FIXED m_xmcd_data_size { ; load address = execution address
|
||||
* (.boot_hdr.xmcd_data, +FIRST)
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data2 m_data2_start m_data2_size {
|
||||
* (RamFunction)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,102 +1,102 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x20200000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x20200400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_ncache_start 0x20280000
|
||||
#define m_ncache_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x20240000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x20200000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x20200400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_ncache_start 0x20280000
|
||||
#define m_ncache_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x20240000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,109 +1,109 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x1FFE0000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x1FFE0400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_ncache_start 0x20280000
|
||||
#define m_ncache_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x20240000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_rpmsg_sh_mem_start 0x202C0000
|
||||
#define m_rpmsg_sh_mem_size 0x00002000
|
||||
#endif
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
#if (defined(__use_shmem__))
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
RPMSG_SH_MEM_unused +0 EMPTY m_rpmsg_sh_mem_size-ImageLength(RPMSG_SH_MEM) { ; Empty region added for MPU configuration
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x1FFE0000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x1FFE0400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_ncache_start 0x20280000
|
||||
#define m_ncache_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x20240000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_rpmsg_sh_mem_start 0x202C0000
|
||||
#define m_rpmsg_sh_mem_size 0x00002000
|
||||
#endif
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
#if (defined(__use_shmem__))
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
RPMSG_SH_MEM_unused +0 EMPTY m_rpmsg_sh_mem_size-ImageLength(RPMSG_SH_MEM) { ; Empty region added for MPU configuration
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1,104 +1,104 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x1FFE0000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x1FFE0400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x03000000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x20240000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x1FFE0000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x1FFE0400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x03000000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x20240000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,109 +1,109 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x80000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x80000400
|
||||
#define m_text_size 0x001FFC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_data_start 0x20240000
|
||||
#define m_data_size 0x00080000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x80200000
|
||||
#define m_data3_size 0x02E00000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm4
|
||||
** MIMXRT1176CVM8A_cm4
|
||||
** MIMXRT1176DVMAA_cm4
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x80000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x80000400
|
||||
#define m_text_size 0x001FFC00
|
||||
|
||||
#define m_qacode_start 0x1FFE0000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_data_start 0x20240000
|
||||
#define m_data_size 0x00080000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x80200000
|
||||
#define m_data3_size 0x02E00000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
+144
-144
@@ -1,144 +1,144 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x30000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x30001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x30002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x30002400
|
||||
#define m_text_size 0x00FBDC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00040000
|
||||
|
||||
#define m_interrupts_ram_start 0x20000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x00040000 - m_interrupts_ram_size)
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_rpmsg_sh_mem_start 0x202C0000
|
||||
#define m_rpmsg_sh_mem_size 0x00002000
|
||||
|
||||
#define m_data2_start 0x202C2000
|
||||
#define m_data2_size 0x0007E000
|
||||
#else
|
||||
#define m_data2_start 0x202C0000
|
||||
#define m_data2_size 0x00080000
|
||||
#endif
|
||||
|
||||
#define m_core1_image_start 0x30FC0000
|
||||
#define m_core1_image_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (RamFunction)
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
#if (defined(__use_shmem__))
|
||||
RW_m_ncache m_rpmsg_sh_mem_start EMPTY 0 {
|
||||
}
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
RW_m_ncache_unused m_rpmsg_sh_mem_start+m_rpmsg_sh_mem_size EMPTY 0 { ; Empty region added for MPU configuration
|
||||
}
|
||||
#else
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_ncache m_data2_start EMPTY 0 {
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
LR_CORE1_IMAGE m_core1_image_start {
|
||||
CORE1_REGION m_core1_image_start m_core1_image_size {
|
||||
*(*core1_code)
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x30000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x30001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x30002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x30002400
|
||||
#define m_text_size 0x00FBDC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00040000
|
||||
|
||||
#define m_interrupts_ram_start 0x20000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x00040000 - m_interrupts_ram_size)
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_rpmsg_sh_mem_start 0x202C0000
|
||||
#define m_rpmsg_sh_mem_size 0x00002000
|
||||
|
||||
#define m_data2_start 0x202C2000
|
||||
#define m_data2_size 0x0007E000
|
||||
#else
|
||||
#define m_data2_start 0x202C0000
|
||||
#define m_data2_size 0x00080000
|
||||
#endif
|
||||
|
||||
#define m_core1_image_start 0x30FC0000
|
||||
#define m_core1_image_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (RamFunction)
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
#if (defined(__use_shmem__))
|
||||
RW_m_ncache m_rpmsg_sh_mem_start EMPTY 0 {
|
||||
}
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
RW_m_ncache_unused m_rpmsg_sh_mem_start+m_rpmsg_sh_mem_size EMPTY 0 { ; Empty region added for MPU configuration
|
||||
}
|
||||
#else
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_ncache m_data2_start EMPTY 0 {
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
LR_CORE1_IMAGE m_core1_image_start {
|
||||
CORE1_REGION m_core1_image_start m_core1_image_size {
|
||||
*(*core1_code)
|
||||
}
|
||||
}
|
||||
|
||||
+164
-143
@@ -1,143 +1,164 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x30000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x30001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x30002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x30002400
|
||||
#define m_text_size 0x00FFDC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00040000
|
||||
|
||||
#define m_interrupts_ram_start 0x80000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x03000000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#define m_data3_start 0x202C0000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data2 m_data2_start m_data2_size {
|
||||
* (RamFunction)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x30000400
|
||||
#define m_flash_config_size 0x00000C00
|
||||
|
||||
#define m_ivt_start 0x30001000
|
||||
#define m_ivt_size 0x00000020
|
||||
|
||||
#define m_boot_data_start 0x30001020
|
||||
#define m_boot_data_size 0x00000010
|
||||
|
||||
#define m_dcd_data_start 0x30001030
|
||||
#define m_dcd_data_size 0x000006E8
|
||||
|
||||
#define m_xmcd_data_start 0x30001040
|
||||
#define m_xmcd_data_size 0x00000204
|
||||
|
||||
#define m_interrupts_start 0x30002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x30002400
|
||||
#define m_text_size 0x00FFDC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00040000
|
||||
|
||||
#define m_interrupts_ram_start 0x80000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x03000000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#define m_data3_start 0x202C0000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_boot_data_text m_boot_data_start FIXED m_boot_data_size { ; load address = execution address
|
||||
* (.boot_hdr.boot_data, +FIRST)
|
||||
}
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
RW_m_dcd_data_text m_dcd_data_start FIXED m_dcd_data_size { ; load address = execution address
|
||||
* (.boot_hdr.dcd_data, +FIRST)
|
||||
}
|
||||
#elif defined(XIP_BOOT_HEADER_XMCD_ENABLE) && (XIP_BOOT_HEADER_XMCD_ENABLE == 1)
|
||||
RW_m_xmcd_data_text m_xmcd_data_start FIXED m_xmcd_data_size { ; load address = execution address
|
||||
* (.boot_hdr.xmcd_data, +FIRST)
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data2 m_data2_start m_data2_size {
|
||||
* (RamFunction)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,78 +1,78 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0003FC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x202C0000
|
||||
#define m_data2_size 0x00080000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_data2_start EMPTY 0 {
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0003FC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00040000
|
||||
|
||||
#define m_data2_start 0x202C0000
|
||||
#define m_data2_size 0x00080000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_data2_start EMPTY 0 {
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,104 +1,104 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0003FC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x03000000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#define m_data3_start 0x202C0000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0003FC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x03000000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#define m_data3_start 0x202C0000
|
||||
#define m_data3_size 0x00080000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
* (CodeQuickAccess)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,109 +1,109 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.0, 2020-12-29
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x80000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x80000400
|
||||
#define m_text_size 0x001FFC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00040000
|
||||
|
||||
#define m_data_start 0x202C0000
|
||||
#define m_data_size 0x00080000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#define m_data3_start 0x80200000
|
||||
#define m_data3_size 0x02E00000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1176AVM8A_cm7
|
||||
** MIMXRT1176CVM8A_cm7
|
||||
** MIMXRT1176DVMAA_cm7
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
||||
** Version: rev. 1.1, 2022-04-02
|
||||
** Build: b220402
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2022 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x80000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x80000400
|
||||
#define m_text_size 0x001FFC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00040000
|
||||
|
||||
#define m_data_start 0x202C0000
|
||||
#define m_data_size 0x00080000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
#define m_data3_start 0x80200000
|
||||
#define m_data3_size 0x02E00000
|
||||
|
||||
#define m_ncache_start 0x83000000
|
||||
#define m_ncache_size 0x01000000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
|
||||
#else
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
#endif
|
||||
.ANY (+RW +ZI)
|
||||
*(*m_usb_dma_init_data)
|
||||
*(*m_usb_dma_noninit_data)
|
||||
}
|
||||
#if (!defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
#endif
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_data2 m_data2_start m_data2_size { ;
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache data
|
||||
#else
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache data
|
||||
#endif
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
#if (defined(__heap_noncacheable__))
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
|
||||
#else
|
||||
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -30,9 +30,9 @@ enum
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief CAAM driver version. Version 2.1.5.
|
||||
/*! @brief CAAM driver version. Version 2.1.6.
|
||||
*
|
||||
* Current version: 2.1.4
|
||||
* Current version: 2.1.6
|
||||
*
|
||||
* Change log:
|
||||
* - Version 2.0.0
|
||||
@@ -58,8 +58,10 @@ enum
|
||||
* - Version 2.1.5
|
||||
* - Support EXTENDED data size for all AES, HASH and RNG operations.
|
||||
* - Support multiple De-Initialization/Initialization of CAAM driver within one POR event.
|
||||
* - Version 2.1.6
|
||||
* - Improve DCACHE handling. Requires CAAM used and cached memory set in write-trough mode.
|
||||
*/
|
||||
#define FSL_CAAM_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
|
||||
#define FSL_CAAM_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief CAAM callback function. */
|
||||
@@ -1305,7 +1307,7 @@ status_t CAAM_RNG_Reseed(CAAM_Type *base,
|
||||
status_t CAAM_RNG_GetRandomData(CAAM_Type *base,
|
||||
caam_handle_t *handle,
|
||||
caam_rng_state_handle_t stateHandle,
|
||||
void *data,
|
||||
uint8_t *data,
|
||||
size_t dataSize,
|
||||
caam_rng_random_type_t dataType,
|
||||
caam_rng_generic256_t additionalEntropy);
|
||||
|
||||
@@ -38,7 +38,6 @@ void CDOG_GetDefaultConfig(cdog_config_t *conf)
|
||||
conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */
|
||||
conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */
|
||||
conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */
|
||||
conf->control = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Control */
|
||||
conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */
|
||||
conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */
|
||||
conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */
|
||||
@@ -243,7 +242,9 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
|
||||
{
|
||||
/* Ungate clock to CDOG engine and reset it */
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
#ifdef CDOG_CLOCKS
|
||||
CLOCK_EnableClock(kCLOCK_Cdog);
|
||||
#endif /* CDOG_CLOCKS */
|
||||
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
|
||||
@@ -278,7 +279,6 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
|
||||
CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */
|
||||
CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */
|
||||
CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */
|
||||
CDOG_CONTROL_CONTROL_CTRL(conf->control) | /* Action if the control error event is triggered */
|
||||
CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */
|
||||
CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */
|
||||
CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */
|
||||
@@ -307,6 +307,8 @@ void CDOG_Deinit(CDOG_Type *base)
|
||||
#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
#ifdef CDOG_CLOCKS
|
||||
CLOCK_DisableClock(kCLOCK_Cdog);
|
||||
#endif /* CDOG_CLOCKS */
|
||||
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
@@ -22,9 +22,11 @@
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief Defines CDOG driver version 2.1.0.
|
||||
/*! @brief Defines CDOG driver version 2.1.1.
|
||||
*
|
||||
* Change log:
|
||||
* - Version 2.1.1
|
||||
* - Remove bit CONTROL[CONTROL_CTRL]
|
||||
* - Version 2.1.0
|
||||
* - Rename CWT to CDOG
|
||||
* - Version 2.0.2
|
||||
@@ -34,7 +36,7 @@
|
||||
* - Version 2.0.0
|
||||
* - initial version
|
||||
*/
|
||||
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
|
||||
/*@}*/
|
||||
|
||||
typedef struct
|
||||
@@ -43,7 +45,6 @@ typedef struct
|
||||
uint8_t timeout : 3;
|
||||
uint8_t miscompare : 3;
|
||||
uint8_t sequence : 3;
|
||||
uint8_t control : 3;
|
||||
uint8_t state : 3;
|
||||
uint8_t address : 3;
|
||||
uint8_t reserved : 8;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2019 - 2021 NXP
|
||||
* Copyright 2019-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -122,11 +122,11 @@ void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
|
||||
|
||||
uint32_t reg;
|
||||
|
||||
if (((ANADIG_PLL->ARM_PLL_CTRL & (ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)) != 0UL) &&
|
||||
((ANADIG_PLL->ARM_PLL_CTRL & (ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider))) ==
|
||||
(ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider))) &&
|
||||
((ANADIG_PLL->ARM_PLL_CTRL & (ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider))) ==
|
||||
(ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider))))
|
||||
if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) &&
|
||||
((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) ==
|
||||
ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider)) &&
|
||||
((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) ==
|
||||
ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider)))
|
||||
{
|
||||
/* no need to reconfigure the PLL if all the configuration is the same */
|
||||
if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2019-2021 NXP
|
||||
* Copyright 2019-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -40,7 +40,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief CLOCK driver version. */
|
||||
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
|
||||
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
|
||||
|
||||
/* Definition for delay API in clock driver, users can redefine it to the real application. */
|
||||
#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
|
||||
@@ -485,9 +485,9 @@
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for XBARA. */
|
||||
#define XBARA_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Xbar1 \
|
||||
#define XBARA_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_IpInvalid, kCLOCK_Xbar1 \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for XBARB. */
|
||||
|
||||
@@ -21,13 +21,14 @@ typedef struct _mem_align_control_block
|
||||
#define FSL_COMPONENT_ID "platform.drivers.common"
|
||||
#endif
|
||||
|
||||
#if !((defined(__DSC__) && defined(__CW__)))
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||
{
|
||||
mem_align_cb_t *p_cb = NULL;
|
||||
uint32_t alignedsize;
|
||||
|
||||
/* Check overflow. */
|
||||
alignedsize = SDK_SIZEALIGN(size, alignbytes);
|
||||
alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
|
||||
if (alignedsize < size)
|
||||
{
|
||||
return NULL;
|
||||
@@ -38,19 +39,15 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
alignedsize += alignbytes + sizeof(mem_align_cb_t);
|
||||
alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
|
||||
|
||||
union
|
||||
{
|
||||
void *pointer_value;
|
||||
#if (defined(__DSC__) && defined(__CW__))
|
||||
uint32_t unsigned_value;
|
||||
#else
|
||||
uintptr_t unsigned_value;
|
||||
#endif
|
||||
} p_align_addr, p_addr;
|
||||
|
||||
p_addr.pointer_value = malloc(alignedsize);
|
||||
p_addr.pointer_value = malloc((size_t)alignedsize);
|
||||
|
||||
if (p_addr.pointer_value == NULL)
|
||||
{
|
||||
@@ -71,11 +68,7 @@ void SDK_Free(void *ptr)
|
||||
union
|
||||
{
|
||||
void *pointer_value;
|
||||
#if (defined(__DSC__) && defined(__CW__))
|
||||
uint32_t unsigned_value;
|
||||
#else
|
||||
uintptr_t unsigned_value;
|
||||
#endif
|
||||
} p_free;
|
||||
p_free.pointer_value = ptr;
|
||||
mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
|
||||
@@ -89,3 +82,4 @@ void SDK_Free(void *ptr)
|
||||
|
||||
free(p_free.pointer_value);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -59,7 +59,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
@@ -190,6 +190,11 @@ enum _status_groups
|
||||
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
|
||||
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
|
||||
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
|
||||
kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */
|
||||
kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */
|
||||
kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */
|
||||
kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */
|
||||
};
|
||||
|
||||
/*! \public
|
||||
@@ -264,6 +269,7 @@ typedef int32_t status_t;
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !((defined(__DSC__) && defined(__CW__)))
|
||||
/*!
|
||||
* @brief Allocate memory with given alignment and aligned size.
|
||||
*
|
||||
@@ -281,6 +287,7 @@ void *SDK_Malloc(size_t size, size_t alignbytes);
|
||||
* @param ptr The memory to be release.
|
||||
*/
|
||||
void SDK_Free(void *ptr);
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Delay at least for some time.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -314,19 +314,19 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm
|
||||
*
|
||||
* param base eDMA peripheral base address.
|
||||
* param channel eDMA channel number.
|
||||
* param type A channel link type, which can be one of the following:
|
||||
* param linkType A channel link type, which can be one of the following:
|
||||
* arg kEDMA_LinkNone
|
||||
* arg kEDMA_MinorLink
|
||||
* arg kEDMA_MajorLink
|
||||
* param linkedChannel The linked channel number.
|
||||
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
|
||||
*/
|
||||
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
|
||||
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
||||
assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
||||
|
||||
EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel);
|
||||
EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], linkType, linkedChannel);
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -458,7 +458,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
|
||||
tcd->CITER = 0U;
|
||||
tcd->DLAST_SGA = 0U;
|
||||
/* Enable auto disable request feature */
|
||||
tcd->CSR = DMA_CSR_DREQ(true);
|
||||
tcd->CSR = DMA_CSR_DREQ(1U);
|
||||
tcd->BITER = 0U;
|
||||
}
|
||||
|
||||
@@ -466,7 +466,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
|
||||
* brief Configures the eDMA TCD transfer attribute.
|
||||
*
|
||||
* The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
|
||||
* The STCD is used in the scatter-gather mode.
|
||||
* The TCD is used in the scatter-gather mode.
|
||||
* This function configures the TCD transfer attribute, including source address, destination address,
|
||||
* transfer size, address offset, and so on. It also configures the scatter gather feature if the
|
||||
* user supplies the next TCD address.
|
||||
@@ -592,19 +592,19 @@ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t
|
||||
*
|
||||
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
|
||||
* param tcd Point to the TCD structure.
|
||||
* param type Channel link type, it can be one of:
|
||||
* param linkType Channel link type, it can be one of:
|
||||
* arg kEDMA_LinkNone
|
||||
* arg kEDMA_MinorLink
|
||||
* arg kEDMA_MajorLink
|
||||
* param linkedChannel The linked channel number.
|
||||
*/
|
||||
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
|
||||
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel)
|
||||
{
|
||||
assert(tcd != NULL);
|
||||
assert(((uint32_t)tcd & 0x1FU) == 0U);
|
||||
assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
||||
|
||||
if (type == kEDMA_MinorLink) /* Minor link config */
|
||||
if (linkType == kEDMA_MinorLink) /* Minor link config */
|
||||
{
|
||||
uint16_t tmpreg;
|
||||
|
||||
@@ -619,7 +619,7 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
|
||||
tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
|
||||
tcd->BITER = tmpreg;
|
||||
}
|
||||
else if (type == kEDMA_MajorLink) /* Major link config */
|
||||
else if (linkType == kEDMA_MajorLink) /* Major link config */
|
||||
{
|
||||
uint16_t tmpreg;
|
||||
|
||||
@@ -1044,7 +1044,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
|
||||
* param destWidth eDMA transfer destination address width(bytes).
|
||||
* param bytesEachRequest eDMA transfer bytes per channel request.
|
||||
* param transferBytes eDMA transfer bytes to be transferred.
|
||||
* param type eDMA transfer type.
|
||||
* param transferType eDMA transfer type.
|
||||
* note The data address and the data width must be consistent. For example, if the SRC
|
||||
* is 4 bytes, the source address must be 4 bytes aligned, or it results in
|
||||
* source address error (SAE).
|
||||
@@ -1056,13 +1056,13 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
|
||||
uint32_t destWidth,
|
||||
uint32_t bytesEachRequest,
|
||||
uint32_t transferBytes,
|
||||
edma_transfer_type_t type)
|
||||
edma_transfer_type_t transferType)
|
||||
{
|
||||
assert(config != NULL);
|
||||
|
||||
int16_t srcOffset = 0, destOffset = 0;
|
||||
|
||||
switch (type)
|
||||
switch (transferType)
|
||||
{
|
||||
case kEDMA_MemoryToMemory:
|
||||
destOffset = (int16_t)destWidth;
|
||||
@@ -1468,6 +1468,15 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
|
||||
{
|
||||
tcds_done += handle->tcdSize;
|
||||
}
|
||||
/*
|
||||
* While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware
|
||||
* so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD
|
||||
* overwritten.
|
||||
*/
|
||||
if (transfer_done)
|
||||
{
|
||||
handle->base->CDNE = handle->channel;
|
||||
}
|
||||
}
|
||||
/* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
|
||||
handle->header = (int8_t)new_header;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -438,14 +438,14 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm
|
||||
*
|
||||
* @param base eDMA peripheral base address.
|
||||
* @param channel eDMA channel number.
|
||||
* @param type A channel link type, which can be one of the following:
|
||||
* @param linkType A channel link type, which can be one of the following:
|
||||
* @arg kEDMA_LinkNone
|
||||
* @arg kEDMA_MinorLink
|
||||
* @arg kEDMA_MajorLink
|
||||
* @param linkedChannel The linked channel number.
|
||||
* @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
|
||||
*/
|
||||
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
|
||||
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel);
|
||||
|
||||
/*!
|
||||
* @brief Sets the bandwidth for the eDMA transfer.
|
||||
@@ -563,7 +563,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd);
|
||||
* @brief Configures the eDMA TCD transfer attribute.
|
||||
*
|
||||
* The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
|
||||
* The STCD is used in the scatter-gather mode.
|
||||
* The TCD is used in the scatter-gather mode.
|
||||
* This function configures the TCD transfer attribute, including source address, destination address,
|
||||
* transfer size, address offset, and so on. It also configures the scatter gather feature if the
|
||||
* user supplies the next TCD address.
|
||||
@@ -608,13 +608,13 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi
|
||||
*
|
||||
* @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
|
||||
* @param tcd Point to the TCD structure.
|
||||
* @param type Channel link type, it can be one of:
|
||||
* @param linkType Channel link type, it can be one of:
|
||||
* @arg kEDMA_LinkNone
|
||||
* @arg kEDMA_MinorLink
|
||||
* @arg kEDMA_MajorLink
|
||||
* @param linkedChannel The linked channel number.
|
||||
*/
|
||||
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
|
||||
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel);
|
||||
|
||||
/*!
|
||||
* @brief Sets the bandwidth for the eDMA TCD.
|
||||
@@ -890,7 +890,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
|
||||
* @param destWidth eDMA transfer destination address width(bytes).
|
||||
* @param bytesEachRequest eDMA transfer bytes per channel request.
|
||||
* @param transferBytes eDMA transfer bytes to be transferred.
|
||||
* @param type eDMA transfer type.
|
||||
* @param transferType eDMA transfer type.
|
||||
* @note The data address and the data width must be consistent. For example, if the SRC
|
||||
* is 4 bytes, the source address must be 4 bytes aligned, or it results in
|
||||
* source address error (SAE).
|
||||
@@ -902,7 +902,7 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
|
||||
uint32_t destWidth,
|
||||
uint32_t bytesEachRequest,
|
||||
uint32_t transferBytes,
|
||||
edma_transfer_type_t type);
|
||||
edma_transfer_type_t transferType);
|
||||
|
||||
/*!
|
||||
* @brief Submits the eDMA transfer request.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2019-2021 NXP
|
||||
* Copyright 2019-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -51,6 +51,13 @@
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Mask the cache management code if cache control is disabled. */
|
||||
#if !defined(FSL_ETH_ENABLE_CACHE_CONTROL)
|
||||
#define ENET_QOS_DcacheInvalidateByRange(address, sizeByte)
|
||||
#else
|
||||
#define ENET_QOS_DcacheInvalidateByRange(address, sizeByte) DCACHE_InvalidateByRange(address, sizeByte)
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Increase the index in the ring.
|
||||
*
|
||||
@@ -519,6 +526,7 @@ static status_t ENET_QOS_TxDescriptorsInit(ENET_QOS_Type *base,
|
||||
enet_qos_tx_bd_struct_t *txbdPtr;
|
||||
uint32_t control = intTxEnable ? ENET_QOS_TXDESCRIP_RD_IOC_MASK : 0U;
|
||||
const enet_qos_buffer_config_t *buffCfg = bufferConfig;
|
||||
uint32_t txDescAddr, txDescTail;
|
||||
|
||||
if (buffCfg == NULL)
|
||||
{
|
||||
@@ -531,10 +539,14 @@ static status_t ENET_QOS_TxDescriptorsInit(ENET_QOS_Type *base,
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
/* Set the tx descriptor start/tail pointer, shall be word aligned. */
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR =
|
||||
(uint32_t)buffCfg->txDescStartAddrAlign & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK;
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR =
|
||||
(uint32_t)buffCfg->txDescTailAddrAlign & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK;
|
||||
txDescAddr = (uint32_t)(uintptr_t)buffCfg->txDescStartAddrAlign & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK;
|
||||
txDescTail = (uint32_t)(uintptr_t)buffCfg->txDescTailAddrAlign & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK;
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
txDescAddr = MEMORY_ConvertMemoryMapAddress(txDescAddr, kMEMORY_Local2DMA);
|
||||
txDescTail = MEMORY_ConvertMemoryMapAddress(txDescTail, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR = txDescAddr;
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTail;
|
||||
/* Set the tx ring length. */
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_RING_LENGTH =
|
||||
((uint32_t)buffCfg->txRingLen - 1U) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK;
|
||||
@@ -566,6 +578,7 @@ static status_t ENET_QOS_RxDescriptorsInit(ENET_QOS_Type *base,
|
||||
bool doubleBuffEnable = ((config->specialControl & (uint32_t)kENET_QOS_DescDoubleBuffer) != 0U) ? true : false;
|
||||
const enet_qos_buffer_config_t *buffCfg = bufferConfig;
|
||||
uint32_t control = ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK;
|
||||
uint32_t rxDescAddr, rxDescTail;
|
||||
|
||||
if (buffCfg == NULL)
|
||||
{
|
||||
@@ -595,12 +608,22 @@ static status_t ENET_QOS_RxDescriptorsInit(ENET_QOS_Type *base,
|
||||
}
|
||||
|
||||
/* Set the rx descriptor start/tail pointer, shall be word aligned. */
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR =
|
||||
(uint32_t)buffCfg->rxDescStartAddrAlign & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK;
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR =
|
||||
(uint32_t)buffCfg->rxDescTailAddrAlign & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK;
|
||||
rxDescAddr = (uint32_t)(uintptr_t)buffCfg->rxDescStartAddrAlign & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK;
|
||||
rxDescTail = (uint32_t)(uintptr_t)buffCfg->rxDescTailAddrAlign & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK;
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
rxDescAddr = MEMORY_ConvertMemoryMapAddress(rxDescAddr, kMEMORY_Local2DMA);
|
||||
rxDescTail = MEMORY_ConvertMemoryMapAddress(rxDescTail, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR = rxDescAddr;
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTail;
|
||||
/* Register DMA_CHX_RXDESC_RING_LENGTH renamed to DMA_CHX_RX_CONTROL2 */
|
||||
#if defined(ENET_QOS_DMA_CHX_RX_CONTROL2_COUNT) && ENET_QOS_DMA_CHX_RX_CONTROL2_COUNT
|
||||
base->DMA_CH[channel].DMA_CHX_RX_CONTROL2 =
|
||||
((uint32_t)buffCfg->rxRingLen - 1U) & ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_MASK;
|
||||
#else
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_RING_LENGTH =
|
||||
((uint32_t)buffCfg->rxRingLen - 1U) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK;
|
||||
#endif
|
||||
reg = base->DMA_CH[channel].DMA_CHX_RX_CTRL & ~ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK;
|
||||
reg |= ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(buffCfg->rxBuffSizeAlign >> ENET_QOS_RXBUFF_IGNORELSB_BITS);
|
||||
base->DMA_CH[channel].DMA_CHX_RX_CTRL = reg;
|
||||
@@ -622,7 +645,7 @@ static status_t ENET_QOS_RxDescriptorsInit(ENET_QOS_Type *base,
|
||||
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffCfg->rxBufferStartAddr[index] =
|
||||
MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBufferStartAddr[index], kMEMORY_Local2DMA);
|
||||
MEMORY_ConvertMemoryMapAddress((uintptr_t)buffCfg->rxBufferStartAddr[index], kMEMORY_Local2DMA);
|
||||
#endif
|
||||
rxbdPtr->buff1Addr = buffCfg->rxBufferStartAddr[index];
|
||||
|
||||
@@ -630,8 +653,8 @@ static status_t ENET_QOS_RxDescriptorsInit(ENET_QOS_Type *base,
|
||||
if (doubleBuffEnable)
|
||||
{
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffCfg->rxBufferStartAddr[index + 1U] =
|
||||
MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBufferStartAddr[index + 1U], kMEMORY_Local2DMA);
|
||||
buffCfg->rxBufferStartAddr[index + 1U] = MEMORY_ConvertMemoryMapAddress(
|
||||
(uintptr_t)buffCfg->rxBufferStartAddr[index + 1U], kMEMORY_Local2DMA);
|
||||
#endif
|
||||
rxbdPtr->buff2Addr = buffCfg->rxBufferStartAddr[index + 1U];
|
||||
}
|
||||
@@ -847,9 +870,10 @@ status_t ENET_QOS_Init(
|
||||
{
|
||||
assert(config != NULL);
|
||||
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t instance = ENET_QOS_GetInstance(base);
|
||||
status_t result = kStatus_Success;
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
uint32_t instance = ENET_QOS_GetInstance(base);
|
||||
|
||||
/* Ungate ENET clock. */
|
||||
(void)CLOCK_EnableClock(s_enetqosClock[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
@@ -883,6 +907,7 @@ void ENET_QOS_Down(ENET_QOS_Type *base)
|
||||
enet_qos_tx_bd_struct_t *txbdPtr;
|
||||
uint8_t index;
|
||||
uint32_t primask, j;
|
||||
uint32_t txDescAddr;
|
||||
|
||||
/* Disable all interrupts */
|
||||
ENET_QOS_DisableInterrupts(base, 0xFF);
|
||||
@@ -922,8 +947,12 @@ void ENET_QOS_Down(ENET_QOS_Type *base)
|
||||
}
|
||||
|
||||
/* Reset hardware ring buffer */
|
||||
base->DMA_CH[index].DMA_CHX_TXDESC_LIST_ADDR =
|
||||
(uint32_t)handle->txBdRing[index].txBdBase & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK;
|
||||
txDescAddr =
|
||||
(uint32_t)(uintptr_t)handle->txBdRing[index].txBdBase & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK;
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
txDescAddr = MEMORY_ConvertMemoryMapAddress(txDescAddr, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[index].DMA_CHX_TXDESC_LIST_ADDR = txDescAddr;
|
||||
|
||||
/* Reset software ring buffer */
|
||||
handle->txBdRing[index].txGenIdx = 0;
|
||||
@@ -1077,7 +1106,7 @@ status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handl
|
||||
index = j;
|
||||
}
|
||||
|
||||
buffAddr = (uint32_t)(uint32_t *)handle->rxBuffAlloc(base, handle->userData, channel);
|
||||
buffAddr = (uint32_t)(uintptr_t)(uint8_t *)handle->rxBuffAlloc(base, handle->userData, channel);
|
||||
if (buffAddr == 0U)
|
||||
{
|
||||
result = kStatus_ENET_QOS_InitMemoryFail;
|
||||
@@ -1085,7 +1114,7 @@ status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handl
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffAddr = MEMORY_ConvertMemoryMapAddress(buffAddr, kMEMORY_Local2DMA);
|
||||
buffAddr = (uint32_t)MEMORY_ConvertMemoryMapAddress(buffAddr, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
rxbdPtr->buff1Addr = buffAddr;
|
||||
handle->rxBufferStartAddr[channel][index] = buffAddr;
|
||||
@@ -1093,7 +1122,7 @@ status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handl
|
||||
/* The second buffer is set with 0 because it is not required for normal case. */
|
||||
if (handle->doubleBuffEnable)
|
||||
{
|
||||
buffAddr = (uint32_t)(uint32_t *)handle->rxBuffAlloc(base, handle->userData, channel);
|
||||
buffAddr = (uint32_t)(uintptr_t)(uint8_t *)handle->rxBuffAlloc(base, handle->userData, channel);
|
||||
if (buffAddr == 0U)
|
||||
{
|
||||
result = kStatus_ENET_QOS_InitMemoryFail;
|
||||
@@ -1101,7 +1130,7 @@ status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handl
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffAddr = MEMORY_ConvertMemoryMapAddress(buffAddr, kMEMORY_Local2DMA);
|
||||
buffAddr = (uint32_t)MEMORY_ConvertMemoryMapAddress(buffAddr, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
rxbdPtr->buff2Addr = buffAddr;
|
||||
handle->rxBufferStartAddr[channel][index + 1U] = buffAddr;
|
||||
@@ -1156,28 +1185,28 @@ void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle)
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffAddr = MEMORY_ConvertMemoryMapAddress((uint32_t)handle->rxBufferStartAddr[channel][index],
|
||||
buffAddr = MEMORY_ConvertMemoryMapAddress((uintptr_t)handle->rxBufferStartAddr[channel][index],
|
||||
kMEMORY_DMA2Local);
|
||||
#else
|
||||
buffAddr = (uint32_t)handle->rxBufferStartAddr[channel][index];
|
||||
#endif
|
||||
if (buffAddr != 0U)
|
||||
{
|
||||
handle->rxBuffFree(base, (void *)(uint32_t *)buffAddr, handle->userData, channel);
|
||||
handle->rxBuffFree(base, (void *)(uint8_t *)(uintptr_t)buffAddr, handle->userData, channel);
|
||||
}
|
||||
|
||||
/* The second buffer is set with 0 because it is not required for normal case. */
|
||||
if (handle->doubleBuffEnable)
|
||||
{
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffAddr = MEMORY_ConvertMemoryMapAddress((uint32_t)handle->rxBufferStartAddr[channel][index + 1],
|
||||
buffAddr = MEMORY_ConvertMemoryMapAddress((uintptr_t)handle->rxBufferStartAddr[channel][index + 1U],
|
||||
kMEMORY_DMA2Local);
|
||||
#else
|
||||
buffAddr = (uint32_t)handle->rxBufferStartAddr[channel][index + 1U];
|
||||
#endif
|
||||
if (buffAddr != 0U)
|
||||
{
|
||||
handle->rxBuffFree(base, (void *)(uint32_t *)buffAddr, handle->userData, channel);
|
||||
handle->rxBuffFree(base, (void *)(uint8_t *)(uintptr_t)buffAddr, handle->userData, channel);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1883,16 +1912,21 @@ static void ENET_QOS_DropFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, u
|
||||
{
|
||||
enet_qos_rx_bd_ring_t *rxBdRing = (enet_qos_rx_bd_ring_t *)&handle->rxBdRing[channel];
|
||||
enet_qos_rx_bd_struct_t *rxDesc;
|
||||
uint16_t index = rxBdRing->rxGenIdx;
|
||||
bool tsAvailable = false;
|
||||
uint32_t buff1Addr = 0;
|
||||
uint32_t buff2Addr = 0;
|
||||
uint16_t index = rxBdRing->rxGenIdx;
|
||||
bool tsAvailable = false;
|
||||
uintptr_t buff1Addr = 0;
|
||||
uintptr_t buff2Addr = 0;
|
||||
uint32_t rxDescTail;
|
||||
uint32_t rdesc1;
|
||||
uint32_t rdesc3;
|
||||
|
||||
/* Not check DMA ownership here, assume there's at least one valid frame left in BD ring */
|
||||
do
|
||||
{
|
||||
/* Get the control flag. */
|
||||
rxDesc = &rxBdRing->rxBdBase[rxBdRing->rxGenIdx];
|
||||
rdesc1 = rxDesc->reserved;
|
||||
rdesc3 = rxDesc->control;
|
||||
|
||||
if (!handle->doubleBuffEnable)
|
||||
{
|
||||
@@ -1911,11 +1945,11 @@ static void ENET_QOS_DropFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, u
|
||||
rxBdRing->rxGenIdx = ENET_QOS_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
|
||||
|
||||
/* Find the last buffer descriptor for the frame. */
|
||||
if ((rxDesc->control & ENET_QOS_RXDESCRIP_WR_LD_MASK) != 0U)
|
||||
if ((rdesc3 & ENET_QOS_RXDESCRIP_WR_LD_MASK) != 0U)
|
||||
{
|
||||
if ((rxDesc->control & ENET_QOS_RXDESCRIP_WR_RS1V_MASK) != 0U)
|
||||
if ((rdesc3 & ENET_QOS_RXDESCRIP_WR_RS1V_MASK) != 0U)
|
||||
{
|
||||
if ((rxDesc->reserved & ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK) != 0U)
|
||||
if ((rdesc1 & ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK) != 0U)
|
||||
{
|
||||
tsAvailable = true;
|
||||
}
|
||||
@@ -1946,7 +1980,11 @@ static void ENET_QOS_DropFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, u
|
||||
} while (rxBdRing->rxGenIdx != index);
|
||||
|
||||
/* Always try to start receive, in case it had stopped */
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = (uint32_t)(uint8_t *)&rxBdRing->rxBdBase[rxBdRing->rxRingLen];
|
||||
rxDescTail = (uint32_t)(uintptr_t)&rxBdRing->rxBdBase[rxBdRing->rxRingLen];
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
rxDescTail = MEMORY_ConvertMemoryMapAddress(rxDescTail, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTail;
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1999,9 +2037,10 @@ status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
|
||||
bool isLastBuff = false;
|
||||
enet_qos_rx_bd_ring_t *rxBdRing = (enet_qos_rx_bd_ring_t *)&handle->rxBdRing[channel];
|
||||
enet_qos_rx_bd_struct_t *rxDesc;
|
||||
status_t result = kStatus_Fail;
|
||||
uint32_t buff1Addr = 0; /*!< Buffer 1 address */
|
||||
uint32_t buff2Addr = 0; /*!< Buffer 2 or next descriptor address */
|
||||
status_t result = kStatus_Fail;
|
||||
uintptr_t buff1Addr = 0; /*!< Buffer 1 address */
|
||||
uintptr_t buff2Addr = 0; /*!< Buffer 2 or next descriptor address */
|
||||
uint32_t rxDescTail;
|
||||
|
||||
bool tsAvailable = false;
|
||||
|
||||
@@ -2013,7 +2052,7 @@ status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
|
||||
}
|
||||
else
|
||||
{
|
||||
while ((!isLastBuff))
|
||||
while (!isLastBuff)
|
||||
{
|
||||
/* The last buffer descriptor of a frame. */
|
||||
rxDesc = &rxBdRing->rxBdBase[rxBdRing->rxGenIdx];
|
||||
@@ -2026,11 +2065,11 @@ status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
|
||||
{
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
/* Add the cache invalidate maintain. */
|
||||
DCACHE_InvalidateByRange(MEMORY_ConvertMemoryMapAddress(buff1Addr, kMEMORY_DMA2Local),
|
||||
rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(MEMORY_ConvertMemoryMapAddress(buff1Addr, kMEMORY_DMA2Local),
|
||||
rxBdRing->rxBuffSizeAlign);
|
||||
#else
|
||||
/* Add the cache invalidate maintain. */
|
||||
DCACHE_InvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@@ -2042,16 +2081,16 @@ status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
|
||||
{
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
/* Add the cache invalidate maintain. */
|
||||
DCACHE_InvalidateByRange(MEMORY_ConvertMemoryMapAddress(buff1Addr, kMEMORY_DMA2Local),
|
||||
rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(MEMORY_ConvertMemoryMapAddress(buff1Addr, kMEMORY_DMA2Local),
|
||||
rxBdRing->rxBuffSizeAlign);
|
||||
/* Add the cache invalidate maintain. */
|
||||
DCACHE_InvalidateByRange(MEMORY_ConvertMemoryMapAddress(buff2Addr, kMEMORY_DMA2Local),
|
||||
rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(MEMORY_ConvertMemoryMapAddress(buff2Addr, kMEMORY_DMA2Local),
|
||||
rxBdRing->rxBuffSizeAlign);
|
||||
#else
|
||||
/* Add the cache invalidate maintain. */
|
||||
DCACHE_InvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
/* Add the cache invalidate maintain. */
|
||||
DCACHE_InvalidateByRange(buff2Addr, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(buff2Addr, rxBdRing->rxBuffSizeAlign);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@@ -2199,7 +2238,11 @@ status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
|
||||
}
|
||||
|
||||
/* Always try to start receive, in case it had stopped */
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = (uint32_t)(uint8_t *)&rxBdRing->rxBdBase[rxBdRing->rxRingLen];
|
||||
rxDescTail = (uint32_t)(uintptr_t)&rxBdRing->rxBdBase[rxBdRing->rxRingLen];
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
rxDescTail = MEMORY_ConvertMemoryMapAddress(rxDescTail, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTail;
|
||||
}
|
||||
|
||||
return result;
|
||||
@@ -2238,11 +2281,11 @@ void ENET_QOS_UpdateRxDescriptor(
|
||||
/* Update the buffer if needed. */
|
||||
if (buffer1 != NULL)
|
||||
{
|
||||
rxDesc->buff1Addr = (uint32_t)(uint8_t *)buffer1;
|
||||
rxDesc->buff1Addr = (uint32_t)(uintptr_t)(uint8_t *)buffer1;
|
||||
}
|
||||
if (buffer2 != NULL)
|
||||
{
|
||||
rxDesc->buff2Addr = (uint32_t)(uint8_t *)buffer2;
|
||||
rxDesc->buff2Addr = (uint32_t)(uintptr_t)(uint8_t *)buffer2;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -2312,13 +2355,13 @@ void ENET_QOS_SetupTxDescriptor(enet_qos_tx_bd_struct_t *txDesc,
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buffer1 = (void *)(uint32_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)buffer1, kMEMORY_Local2DMA);
|
||||
buffer2 = (void *)(uint32_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)buffer2, kMEMORY_Local2DMA);
|
||||
buffer1 = (void *)(uint8_t *)MEMORY_ConvertMemoryMapAddress((uintptr_t)(uint8_t *)buffer1, kMEMORY_Local2DMA);
|
||||
buffer2 = (void *)(uint8_t *)MEMORY_ConvertMemoryMapAddress((uintptr_t)(uint8_t *)buffer2, kMEMORY_Local2DMA);
|
||||
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
|
||||
|
||||
/* Preare the descriptor for transmit. */
|
||||
txDesc->buff1Addr = (uint32_t)(uint8_t *)buffer1;
|
||||
txDesc->buff2Addr = (uint32_t)(uint8_t *)buffer2;
|
||||
txDesc->buff1Addr = (uint32_t)(uintptr_t)(uint8_t *)buffer1;
|
||||
txDesc->buff2Addr = (uint32_t)(uintptr_t)(uint8_t *)buffer2;
|
||||
txDesc->buffLen = control;
|
||||
|
||||
/* Make sure all fields of descriptor are written before setting ownership */
|
||||
@@ -2443,6 +2486,7 @@ status_t ENET_QOS_SendFrame(ENET_QOS_Type *base,
|
||||
enet_qos_tx_dirty_ring_t *txDirtyRing;
|
||||
enet_qos_frame_info_t *txDirty;
|
||||
uint32_t primask;
|
||||
uint32_t txDescTail;
|
||||
|
||||
if (length > 2U * ENET_QOS_TXDESCRIP_RD_BL1_MASK)
|
||||
{
|
||||
@@ -2486,7 +2530,11 @@ status_t ENET_QOS_SendFrame(ENET_QOS_Type *base,
|
||||
{
|
||||
txDesc = &txBdRing->txBdBase[txBdRing->txRingLen];
|
||||
}
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = (uint32_t)txDesc & ~ENET_QOS_ADDR_ALIGNMENT;
|
||||
txDescTail = (uint32_t)(uintptr_t)txDesc & ~ENET_QOS_ADDR_ALIGNMENT;
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
txDescTail = MEMORY_ConvertMemoryMapAddress(txDescTail, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTail;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
@@ -2589,8 +2637,8 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
enet_qos_rx_bd_struct_t *rxDesc = &rxBdRing->rxBdBase[rxBdRing->rxGenIdx];
|
||||
uint16_t index = rxBdRing->rxGenIdx;
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t buff1Addr = 0;
|
||||
uint32_t buff2Addr = 0;
|
||||
uintptr_t buff1Addr = 0;
|
||||
uintptr_t buff2Addr = 0;
|
||||
uint16_t buff1Len = 0;
|
||||
uint16_t buff2Len = 0;
|
||||
uint16_t offset = 0;
|
||||
@@ -2599,6 +2647,7 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
bool isDrop = false;
|
||||
bool isLastBuff = false;
|
||||
bool tsAvailable = false;
|
||||
uint32_t rxDescTail;
|
||||
|
||||
/* Check the frame status. */
|
||||
do
|
||||
@@ -2753,9 +2802,9 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
|
||||
if (handle->rxMaintainEnable[channel])
|
||||
{
|
||||
DCACHE_InvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
}
|
||||
rxFrame->rxBuffArray[index].buffer = (void *)(uint32_t *)buff1Addr;
|
||||
rxFrame->rxBuffArray[index].buffer = (void *)(uint8_t *)buff1Addr;
|
||||
rxFrame->rxBuffArray[index].length = buff1Len;
|
||||
index++;
|
||||
}
|
||||
@@ -2767,9 +2816,9 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
|
||||
if (handle->rxMaintainEnable[channel])
|
||||
{
|
||||
DCACHE_InvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign);
|
||||
}
|
||||
rxFrame->rxBuffArray[index].buffer = (void *)(uint32_t *)buff1Addr;
|
||||
rxFrame->rxBuffArray[index].buffer = (void *)(uint8_t *)buff1Addr;
|
||||
rxFrame->rxBuffArray[index].length = buff1Len;
|
||||
index++;
|
||||
|
||||
@@ -2782,9 +2831,9 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
|
||||
if (handle->rxMaintainEnable[channel])
|
||||
{
|
||||
DCACHE_InvalidateByRange(buff2Addr, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange(buff2Addr, rxBdRing->rxBuffSizeAlign);
|
||||
}
|
||||
rxFrame->rxBuffArray[index].buffer = (void *)(uint32_t *)buff2Addr;
|
||||
rxFrame->rxBuffArray[index].buffer = (void *)(uint8_t *)buff2Addr;
|
||||
rxFrame->rxBuffArray[index].length = buff2Len;
|
||||
index++;
|
||||
}
|
||||
@@ -2795,27 +2844,27 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
{
|
||||
if (handle->rxMaintainEnable[channel])
|
||||
{
|
||||
DCACHE_InvalidateByRange((uint32_t)(uint32_t *)newBuff1, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange((uintptr_t)(uint8_t *)newBuff1, rxBdRing->rxBuffSizeAlign);
|
||||
}
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buff1Addr = MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)newBuff1, kMEMORY_Local2DMA);
|
||||
buff1Addr = MEMORY_ConvertMemoryMapAddress((uintptr_t)(uint8_t *)newBuff1, kMEMORY_Local2DMA);
|
||||
#else
|
||||
buff1Addr = (uint32_t)(uint32_t *)newBuff1;
|
||||
buff1Addr = (uintptr_t)(uint8_t *)newBuff1;
|
||||
#endif
|
||||
handle->rxBufferStartAddr[channel][rxBdRing->rxGenIdx] = buff1Addr;
|
||||
ENET_QOS_UpdateRxDescriptor(rxDesc, (void *)(uint32_t *)buff1Addr, NULL, handle->rxintEnable,
|
||||
ENET_QOS_UpdateRxDescriptor(rxDesc, (void *)(uint8_t *)buff1Addr, NULL, handle->rxintEnable,
|
||||
handle->doubleBuffEnable);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (handle->rxMaintainEnable[channel])
|
||||
{
|
||||
DCACHE_InvalidateByRange((uint32_t)(uint32_t *)newBuff1, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange((uintptr_t)(uint8_t *)newBuff1, rxBdRing->rxBuffSizeAlign);
|
||||
}
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buff1Addr = MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)newBuff1, kMEMORY_Local2DMA);
|
||||
buff1Addr = MEMORY_ConvertMemoryMapAddress((uintptr_t)(uint8_t *)newBuff1, kMEMORY_Local2DMA);
|
||||
#else
|
||||
buff1Addr = (uint32_t)(uint32_t *)newBuff1;
|
||||
buff1Addr = (uintptr_t)(uint8_t *)newBuff1;
|
||||
#endif
|
||||
handle->rxBufferStartAddr[channel][2U * rxBdRing->rxGenIdx] = buff1Addr;
|
||||
|
||||
@@ -2823,12 +2872,13 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
{
|
||||
if (handle->rxMaintainEnable[channel])
|
||||
{
|
||||
DCACHE_InvalidateByRange((uint32_t)(uint32_t *)newBuff2, rxBdRing->rxBuffSizeAlign);
|
||||
ENET_QOS_DcacheInvalidateByRange((uintptr_t)(uint8_t *)newBuff2, rxBdRing->rxBuffSizeAlign);
|
||||
}
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
buff2Addr = MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)newBuff2, kMEMORY_Local2DMA);
|
||||
buff2Addr =
|
||||
(uint32_t)MEMORY_ConvertMemoryMapAddress((uintptr_t)(uint8_t *)newBuff2, kMEMORY_Local2DMA);
|
||||
#else
|
||||
buff2Addr = (uint32_t)(uint32_t *)newBuff2;
|
||||
buff2Addr = (uintptr_t)(uint8_t *)newBuff2;
|
||||
#endif
|
||||
handle->rxBufferStartAddr[channel][2U * rxBdRing->rxGenIdx + 1U] = buff2Addr;
|
||||
}
|
||||
@@ -2838,7 +2888,7 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
buff2Addr = handle->rxBufferStartAddr[channel][2U * rxBdRing->rxGenIdx + 1U];
|
||||
}
|
||||
|
||||
ENET_QOS_UpdateRxDescriptor(rxDesc, (void *)(uint32_t *)buff1Addr, (void *)(uint32_t *)buff2Addr,
|
||||
ENET_QOS_UpdateRxDescriptor(rxDesc, (void *)(uint8_t *)buff1Addr, (void *)(uint8_t *)buff2Addr,
|
||||
handle->rxintEnable, handle->doubleBuffEnable);
|
||||
}
|
||||
rxBdRing->rxGenIdx = ENET_QOS_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
|
||||
@@ -2869,8 +2919,11 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
}
|
||||
}
|
||||
/* Always try to start receive, in case it had stopped */
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR =
|
||||
(uint32_t)(uint8_t *)&rxBdRing->rxBdBase[rxBdRing->rxRingLen];
|
||||
rxDescTail = (uint32_t)(uintptr_t)&rxBdRing->rxBdBase[rxBdRing->rxRingLen];
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
rxDescTail = MEMORY_ConvertMemoryMapAddress(rxDescTail, kMEMORY_Local2DMA);
|
||||
#endif
|
||||
base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTail;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -3059,8 +3112,8 @@ status_t ENET_QOS_Ptp1588PpsSetTrgtTime(ENET_QOS_Type *base,
|
||||
uint32_t *mac_pps_trgt_ns;
|
||||
uint32_t *mac_pps_trgt_s;
|
||||
|
||||
mac_pps_trgt_ns = (uint32_t *)((uint32_t)&base->MAC_PPS0_TARGET_TIME_NANOSECONDS + 0x10U * (uint32_t)instance);
|
||||
mac_pps_trgt_s = (uint32_t *)((uint32_t)&base->MAC_PPS0_TARGET_TIME_SECONDS + 0x10U * (uint32_t)instance);
|
||||
mac_pps_trgt_ns = (uint32_t *)((uintptr_t)&base->MAC_PPS0_TARGET_TIME_NANOSECONDS + 0x10U * (uint32_t)instance);
|
||||
mac_pps_trgt_s = (uint32_t *)((uintptr_t)&base->MAC_PPS0_TARGET_TIME_SECONDS + 0x10U * (uint32_t)instance);
|
||||
|
||||
if ((*mac_pps_trgt_ns & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK) != 0U)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* Copyright 2020-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -8,10 +8,19 @@
|
||||
#define _FSL_ENET_QOS_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#if defined(FSL_ETH_ENABLE_CACHE_CONTROL)
|
||||
#include "fsl_cache.h"
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
|
||||
#include "fsl_memory.h"
|
||||
#endif
|
||||
|
||||
#if !defined(ENET_QOS)
|
||||
/* Keep reusing ENET_QOS for platforms which renames it to Ethernet Controller with TSN (EQoS-TSN) */
|
||||
#if defined(ENET_QOS_TSN)
|
||||
#define ENET_QOS ENET_QOS_TSN
|
||||
#endif
|
||||
#endif
|
||||
/*!
|
||||
* @addtogroup enet_qos_qos
|
||||
* @{
|
||||
@@ -24,7 +33,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief Defines the driver version. */
|
||||
#define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
|
||||
#define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
|
||||
/*@}*/
|
||||
|
||||
/*! @name Control and status region bit masks of the receive buffer descriptor. */
|
||||
@@ -1686,7 +1695,7 @@ static inline void ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type *base,
|
||||
{
|
||||
uint32_t *mac_pps_width;
|
||||
|
||||
mac_pps_width = (uint32_t *)((uint32_t)&base->MAC_PPS0_WIDTH + 0x10U * (uint32_t)instance);
|
||||
mac_pps_width = (uint32_t *)((uintptr_t)&base->MAC_PPS0_WIDTH + 0x10U * (uint32_t)instance);
|
||||
|
||||
*mac_pps_width = ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(width);
|
||||
}
|
||||
@@ -1705,7 +1714,7 @@ static inline void ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type *base,
|
||||
{
|
||||
uint32_t *mac_pps_interval;
|
||||
|
||||
mac_pps_interval = (uint32_t *)((uint32_t)&base->MAC_PPS0_INTERVAL + 0x10U * (uint32_t)instance);
|
||||
mac_pps_interval = (uint32_t *)((uintptr_t)&base->MAC_PPS0_INTERVAL + 0x10U * (uint32_t)instance);
|
||||
|
||||
*mac_pps_interval = ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(interval);
|
||||
}
|
||||
@@ -1757,6 +1766,7 @@ status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
|
||||
enet_qos_handle_t *handle,
|
||||
enet_qos_rx_frame_struct_t *rxFrame,
|
||||
uint8_t channel);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -96,10 +96,10 @@
|
||||
|
||||
/* Define the range of memory that needs to be initialized when the device has memory error detection feature. */
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
|
||||
#define CAN_INIT_RXFIR ((uint32_t)base + 0x4Cu)
|
||||
#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1)
|
||||
#define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu)
|
||||
#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1)
|
||||
#define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1
|
||||
#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2)
|
||||
#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2)
|
||||
#define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2
|
||||
#endif
|
||||
|
||||
@@ -365,6 +365,23 @@ static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR;
|
||||
static flexcan_isr_t s_flexcanIsr;
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Implementation of 32-bit memset
|
||||
******************************************************************************/
|
||||
|
||||
static void flexcan_memset(void *s, uint32_t c, size_t n)
|
||||
{
|
||||
size_t m;
|
||||
uint32_t *ptr = s;
|
||||
|
||||
m = n / sizeof(*ptr);
|
||||
|
||||
while ((m--) != (size_t)0)
|
||||
{
|
||||
*ptr++ = c;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
@@ -733,8 +750,8 @@ static void FLEXCAN_Reset(CAN_Type *base)
|
||||
/* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly
|
||||
updated. */
|
||||
*(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U;
|
||||
(void)memset((void *)CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1);
|
||||
(void)memset((void *)CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2);
|
||||
flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1);
|
||||
flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2);
|
||||
/* Disable unrestricted write access to FlexCAN memory. */
|
||||
base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK;
|
||||
|
||||
@@ -742,7 +759,7 @@ static void FLEXCAN_Reset(CAN_Type *base)
|
||||
FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag);
|
||||
#else
|
||||
/* Only need clean all Message Buffer memory. */
|
||||
(void)memset((void *)&base->MB[0], 0, sizeof(base->MB));
|
||||
flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB));
|
||||
#endif
|
||||
|
||||
/* Clean all individual Rx Mask of Message Buffers. */
|
||||
@@ -818,7 +835,7 @@ static void FLEXCAN_SetBitRate(CAN_Type *base,
|
||||
}
|
||||
|
||||
/* Update actual timing characteristic. */
|
||||
FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
|
||||
FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig);
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
|
||||
@@ -869,7 +886,7 @@ static void FLEXCAN_SetFDBitRate(CAN_Type *base,
|
||||
}
|
||||
|
||||
/* Update actual timing characteristic. */
|
||||
FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
|
||||
FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -2692,17 +2709,12 @@ void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_rep
|
||||
*/
|
||||
static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
|
||||
{
|
||||
uint32_t dbg_temp = 0U;
|
||||
uint32_t u32TempCS = 0U;
|
||||
uint32_t u32Timeout = DELAY_BUSIDLE;
|
||||
uint32_t u32TempIMASK1 = base->IMASK1;
|
||||
/*after backup all interruption, disable ALL interruption*/
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
||||
uint32_t u32TempIMASK2 = base->IMASK2;
|
||||
base->IMASK2 = 0;
|
||||
#endif
|
||||
base->IMASK1 = 0;
|
||||
dbg_temp = (uint32_t)(base->DBG1);
|
||||
uint32_t dbg_temp = 0U;
|
||||
uint32_t u32TempCS = 0U;
|
||||
uint32_t u32Timeout = DELAY_BUSIDLE;
|
||||
/*disable ALL interrupts to prevent any context switching*/
|
||||
uint32_t irqMask = DisableGlobalIRQ();
|
||||
dbg_temp = (uint32_t)(base->DBG1);
|
||||
switch (dbg_temp & CAN_DBG1_CFSM_MASK)
|
||||
{
|
||||
case RXINTERMISSION:
|
||||
@@ -2743,10 +2755,7 @@ static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
|
||||
*mbCSAddr = u32TempCS;
|
||||
}
|
||||
/*restore interruption*/
|
||||
base->IMASK1 = u32TempIMASK1;
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
||||
base->IMASK2 = u32TempIMASK2;
|
||||
#endif
|
||||
EnableGlobalIRQ(irqMask);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -2776,12 +2785,12 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
|
||||
uint32_t cs_temp = 0;
|
||||
status_t status;
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
|
||||
FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
|
||||
#endif
|
||||
/* Check if Message Buffer is available. */
|
||||
if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
|
||||
{
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
|
||||
FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
|
||||
#endif
|
||||
/* Inactive Tx Message Buffer. */
|
||||
base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
||||
|
||||
@@ -2862,14 +2871,13 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra
|
||||
volatile uint32_t *mbAddr = &(base->MB[0].CS);
|
||||
uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
|
||||
FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
|
||||
#endif
|
||||
|
||||
can_cs = mbAddr[offset];
|
||||
/* Check if Message Buffer is available. */
|
||||
if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK))
|
||||
{
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
|
||||
FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
|
||||
#endif
|
||||
/* Inactive Tx Message Buffer and Fill Message ID field. */
|
||||
mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
||||
mbAddr[offset + 1U] = pTxFrame->id;
|
||||
@@ -3226,7 +3234,7 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
|
||||
status_t status;
|
||||
|
||||
/* Write Tx Message Buffer to initiate a data sending. */
|
||||
if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uint32_t)pTxFrame))
|
||||
if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame))
|
||||
{
|
||||
/* Wait until CAN Message send out. */
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
||||
@@ -3311,7 +3319,7 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f
|
||||
status_t status;
|
||||
|
||||
/* Write Tx Message Buffer to initiate a data sending. */
|
||||
if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pTxFrame))
|
||||
if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame))
|
||||
{
|
||||
/* Wait until CAN Message send out. */
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
||||
@@ -3563,7 +3571,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl
|
||||
}
|
||||
|
||||
if (kStatus_Success ==
|
||||
FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uint32_t)pMbXfer->frame))
|
||||
FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame))
|
||||
{
|
||||
/* Enable Message Buffer Interrupt. */
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
||||
@@ -3680,7 +3688,7 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han
|
||||
}
|
||||
|
||||
if (kStatus_Success ==
|
||||
FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pMbXfer->framefd))
|
||||
FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd))
|
||||
{
|
||||
/* Enable Message Buffer Interrupt. */
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -22,7 +22,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief FlexCAN driver version. */
|
||||
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 2))
|
||||
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 6))
|
||||
/*@}*/
|
||||
|
||||
#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
|
||||
@@ -396,7 +396,7 @@ enum _flexcan_interrupt_enable
|
||||
kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */
|
||||
kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */
|
||||
kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */
|
||||
kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 22. */
|
||||
kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
|
||||
kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */
|
||||
#endif
|
||||
@@ -1607,8 +1607,7 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
|
||||
/* Solve interrupt enable bits in CTRL1 register. */
|
||||
base->CTRL1 |=
|
||||
(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
|
||||
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
|
||||
(uint32_t)kFLEXCAN_WakeUpInterruptEnable));
|
||||
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1656,8 +1655,7 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
|
||||
/* Solve interrupt enable bits in CTRL1 register. */
|
||||
base->CTRL1 &=
|
||||
~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
|
||||
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
|
||||
(uint32_t)kFLEXCAN_WakeUpInterruptEnable));
|
||||
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1730,9 +1728,9 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
|
||||
* @param base FlexCAN peripheral base address.
|
||||
* @return FlexCAN Rx FIFO Head address.
|
||||
*/
|
||||
static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
|
||||
static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
|
||||
{
|
||||
return (uint32_t) & (base->MB[0].CS);
|
||||
return (uintptr_t) & (base->MB[0].CS);
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2020 NXP
|
||||
* Copyright 2016-2020, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -23,13 +23,13 @@
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief FlexIO SPI driver version 2.2.1. */
|
||||
#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
|
||||
/*! @brief FlexIO SPI driver version. */
|
||||
#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
|
||||
/*@}*/
|
||||
|
||||
#ifndef FLEXIO_SPI_DUMMYDATA
|
||||
/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
|
||||
#define FLEXIO_SPI_DUMMYDATA (0xFFFFU)
|
||||
#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/*! @brief Retry times for waiting flag. */
|
||||
@@ -37,6 +37,9 @@
|
||||
#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
|
||||
#endif
|
||||
|
||||
/*! @brief Get the transfer data format of width and bit order. */
|
||||
#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U))
|
||||
|
||||
/*! @brief Error codes for the FlexIO SPI driver. */
|
||||
enum
|
||||
{
|
||||
@@ -68,6 +71,7 @@ typedef enum _flexio_spi_data_bitcount_mode
|
||||
{
|
||||
kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */
|
||||
kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
|
||||
kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */
|
||||
} flexio_spi_data_bitcount_mode_t;
|
||||
|
||||
/*! @brief Define FlexIO SPI interrupt mask. */
|
||||
@@ -92,20 +96,25 @@ enum _flexio_spi_dma_enable
|
||||
kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
|
||||
};
|
||||
|
||||
/*! @brief Define FlexIO SPI transfer flags. */
|
||||
/*! @brief Define FlexIO SPI transfer flags.
|
||||
* @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */
|
||||
enum _flexio_spi_transfer_flags
|
||||
{
|
||||
kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
|
||||
kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
|
||||
kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
|
||||
kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
|
||||
kFLEXIO_SPI_8bitMsb = 0x0U, /*!< FlexIO SPI 8-bit MSB first */
|
||||
kFLEXIO_SPI_8bitLsb = 0x1U, /*!< FlexIO SPI 8-bit LSB first */
|
||||
kFLEXIO_SPI_16bitMsb = 0x2U, /*!< FlexIO SPI 16-bit MSB first */
|
||||
kFLEXIO_SPI_16bitLsb = 0x3U, /*!< FlexIO SPI 16-bit LSB first */
|
||||
kFLEXIO_SPI_32bitMsb = 0x4U, /*!< FlexIO SPI 32-bit MSB first */
|
||||
kFLEXIO_SPI_32bitLsb = 0x5U, /*!< FlexIO SPI 32-bit LSB first */
|
||||
kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */
|
||||
};
|
||||
|
||||
/*! @brief Define FlexIO SPI access structure typedef. */
|
||||
typedef struct _flexio_spi_type
|
||||
{
|
||||
FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
|
||||
uint8_t SDOPinIndex; /*!< Pin select for data output. */
|
||||
uint8_t SDOPinIndex; /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as
|
||||
GPIO input and disable all pull up/down in application. */
|
||||
uint8_t SDIPinIndex; /*!< Pin select for data input. */
|
||||
uint8_t SCKPinIndex; /*!< Pin select for clock. */
|
||||
uint8_t CSnPinIndex; /*!< Pin select for enable. */
|
||||
@@ -477,9 +486,9 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps,
|
||||
*
|
||||
* @param base Pointer to the FLEXIO_SPI_Type structure.
|
||||
* @param direction Shift direction of MSB first or LSB first.
|
||||
* @param data 8 bit/16 bit data.
|
||||
* @param data 8/16/32 bit data.
|
||||
*/
|
||||
static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data)
|
||||
static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
|
||||
{
|
||||
if (direction == kFLEXIO_SPI_MsbFirst)
|
||||
{
|
||||
@@ -501,15 +510,15 @@ static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_
|
||||
* @param direction Shift direction of MSB first or LSB first.
|
||||
* @return 8 bit/16 bit data received.
|
||||
*/
|
||||
static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
|
||||
static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
|
||||
{
|
||||
if (direction == kFLEXIO_SPI_MsbFirst)
|
||||
{
|
||||
return (uint16_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
|
||||
return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
|
||||
}
|
||||
else
|
||||
{
|
||||
return (uint16_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
|
||||
return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -560,6 +569,14 @@ status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
|
||||
*/
|
||||
status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Flush tx/rx shifters.
|
||||
*
|
||||
* @param base Pointer to the FLEXIO_SPI_Type structure.
|
||||
*/
|
||||
void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
|
||||
/*@}*/
|
||||
|
||||
/*Transactional APIs*/
|
||||
|
||||
/*!
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2020 NXP
|
||||
* Copyright 2016-2020, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -50,17 +50,19 @@ static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool t
|
||||
* @param base pointer to FLEXIO_SPI_Type structure.
|
||||
* @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
|
||||
* @param xfer Pointer to flexio spi transfer structure.
|
||||
* @retval kStatus_Success Successfully create the handle.
|
||||
* @retval kStatus_InvalidArgument The transfer size is not supported.
|
||||
*/
|
||||
static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
flexio_spi_master_edma_handle_t *handle,
|
||||
flexio_spi_transfer_t *xfer);
|
||||
static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
flexio_spi_master_edma_handle_t *handle,
|
||||
flexio_spi_transfer_t *xfer);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/* Dummy data used to send */
|
||||
static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
|
||||
static const uint32_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
|
||||
|
||||
/*< @brief user configurable flexio spi handle count. */
|
||||
#define FLEXIO_SPI_HANDLE_COUNT 2
|
||||
@@ -122,16 +124,17 @@ static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool t
|
||||
}
|
||||
}
|
||||
|
||||
static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
flexio_spi_master_edma_handle_t *handle,
|
||||
flexio_spi_transfer_t *xfer)
|
||||
static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
flexio_spi_master_edma_handle_t *handle,
|
||||
flexio_spi_transfer_t *xfer)
|
||||
{
|
||||
edma_transfer_config_t xferConfig = {0};
|
||||
flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
|
||||
uint8_t bytesPerFrame;
|
||||
uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
|
||||
|
||||
/* Configure the values in handle. */
|
||||
switch (xfer->flags)
|
||||
switch (dataFormat)
|
||||
{
|
||||
case (uint8_t)kFLEXIO_SPI_8bitMsb:
|
||||
bytesPerFrame = 1U;
|
||||
@@ -149,6 +152,14 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
bytesPerFrame = 2U;
|
||||
direction = kFLEXIO_SPI_LsbFirst;
|
||||
break;
|
||||
case (uint8_t)kFLEXIO_SPI_32bitMsb:
|
||||
bytesPerFrame = 4U;
|
||||
direction = kFLEXIO_SPI_MsbFirst;
|
||||
break;
|
||||
case (uint8_t)kFLEXIO_SPI_32bitLsb:
|
||||
bytesPerFrame = 4U;
|
||||
direction = kFLEXIO_SPI_LsbFirst;
|
||||
break;
|
||||
default:
|
||||
bytesPerFrame = 1U;
|
||||
direction = kFLEXIO_SPI_MsbFirst;
|
||||
@@ -156,6 +167,12 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
break;
|
||||
}
|
||||
|
||||
/* Transfer size should be bytesPerFrame divisible. */
|
||||
if ((xfer->dataSize % bytesPerFrame) != 0U)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Save total transfer size. */
|
||||
handle->transferSize = xfer->dataSize;
|
||||
|
||||
@@ -168,7 +185,7 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
|
||||
xferConfig.minorLoopBytes = 1U;
|
||||
}
|
||||
else
|
||||
else if (bytesPerFrame == 2U)
|
||||
{
|
||||
if (direction == kFLEXIO_SPI_MsbFirst)
|
||||
{
|
||||
@@ -178,6 +195,16 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
|
||||
xferConfig.minorLoopBytes = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (direction == kFLEXIO_SPI_MsbFirst)
|
||||
{
|
||||
xferConfig.destAddr -= 3U;
|
||||
}
|
||||
xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes;
|
||||
xferConfig.destTransferSize = kEDMA_TransferSize4Bytes;
|
||||
xferConfig.minorLoopBytes = 4U;
|
||||
}
|
||||
|
||||
/* Configure DMA channel. */
|
||||
if (xfer->txData != NULL)
|
||||
@@ -213,6 +240,16 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
xferConfig.srcAddr -= 1U;
|
||||
}
|
||||
}
|
||||
else if (bytesPerFrame == 4U)
|
||||
{
|
||||
if (direction == kFLEXIO_SPI_LsbFirst)
|
||||
{
|
||||
xferConfig.srcAddr -= 3U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
xferConfig.srcOffset = 0;
|
||||
xferConfig.destAddr = (uint32_t)(xfer->rxData);
|
||||
xferConfig.destOffset = (int16_t)bytesPerFrame;
|
||||
@@ -229,6 +266,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
|
||||
FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true);
|
||||
EDMA_StartTransfer(handle->txHandle);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -321,8 +360,9 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
|
||||
assert(handle != NULL);
|
||||
assert(xfer != NULL);
|
||||
|
||||
uint32_t dataMode = 0;
|
||||
uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
|
||||
uint32_t dataMode = 0;
|
||||
uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
|
||||
uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
|
||||
|
||||
timerCmp &= 0x00FFU;
|
||||
|
||||
@@ -338,27 +378,48 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* configure data mode. */
|
||||
if ((xfer->flags == (uint8_t)kFLEXIO_SPI_8bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_8bitLsb))
|
||||
/* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
|
||||
enables when tx shifter is written and disables when timer compare. The timer compare event causes the
|
||||
transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
|
||||
disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
|
||||
software writes the tx register upon the detection of tx register empty event, the timer enable condition
|
||||
is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
|
||||
if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
|
||||
{
|
||||
dataMode = (8UL * 2UL - 1UL) << 8U;
|
||||
}
|
||||
else if ((xfer->flags == (uint8_t)kFLEXIO_SPI_16bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_16bitLsb))
|
||||
{
|
||||
dataMode = (16UL * 2UL - 1UL) << 8U;
|
||||
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
||||
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
|
||||
FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
|
||||
}
|
||||
else
|
||||
{
|
||||
dataMode = 8UL * 2UL - 1UL;
|
||||
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
||||
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
|
||||
FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
|
||||
}
|
||||
|
||||
/* configure data mode. */
|
||||
if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
|
||||
{
|
||||
dataMode = (8UL * 2UL - 1UL) << 8U;
|
||||
}
|
||||
else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
|
||||
{
|
||||
dataMode = (16UL * 2UL - 1UL) << 8U;
|
||||
}
|
||||
else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
|
||||
{
|
||||
dataMode = (32UL * 2UL - 1UL) << 8U;
|
||||
}
|
||||
else
|
||||
{
|
||||
dataMode = (8UL * 2UL - 1UL) << 8U;
|
||||
}
|
||||
|
||||
dataMode |= timerCmp;
|
||||
|
||||
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
||||
|
||||
FLEXIO_SPI_EDMAConfig(base, handle, xfer);
|
||||
|
||||
return kStatus_Success;
|
||||
return FLEXIO_SPI_EDMAConfig(base, handle, xfer);
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -438,7 +499,8 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
|
||||
assert(handle != NULL);
|
||||
assert(xfer != NULL);
|
||||
|
||||
uint32_t dataMode = 0U;
|
||||
uint32_t dataMode = 0U;
|
||||
uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
|
||||
|
||||
/* Check if the device is busy. */
|
||||
if ((handle->txInProgress) || (handle->rxInProgress))
|
||||
@@ -446,6 +508,33 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
|
||||
return kStatus_FLEXIO_SPI_Busy;
|
||||
}
|
||||
|
||||
/* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
|
||||
/* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
|
||||
before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
|
||||
timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
|
||||
tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
|
||||
FLEXIO_SPI_FlushShifters(base);
|
||||
if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
|
||||
{
|
||||
base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
|
||||
FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
|
||||
{
|
||||
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
||||
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
|
||||
FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
||||
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
|
||||
FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if input parameter invalid. */
|
||||
if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
|
||||
{
|
||||
@@ -453,14 +542,18 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
|
||||
}
|
||||
|
||||
/* configure data mode. */
|
||||
if ((xfer->flags == (uint8_t)kFLEXIO_SPI_8bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_8bitLsb))
|
||||
if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
|
||||
{
|
||||
dataMode = 8U * 2U - 1U;
|
||||
}
|
||||
else if ((xfer->flags == (uint8_t)kFLEXIO_SPI_16bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_16bitLsb))
|
||||
else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
|
||||
{
|
||||
dataMode = 16U * 2U - 1U;
|
||||
}
|
||||
else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
|
||||
{
|
||||
dataMode = 32UL * 2UL - 1UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
dataMode = 8U * 2U - 1U;
|
||||
@@ -468,7 +561,5 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
|
||||
|
||||
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
||||
|
||||
FLEXIO_SPI_EDMAConfig(base, handle, xfer);
|
||||
|
||||
return kStatus_Success;
|
||||
return FLEXIO_SPI_EDMAConfig(base, handle, xfer);
|
||||
}
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2020 NXP
|
||||
* Copyright 2016-2020, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -23,7 +23,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief FlexIO SPI EDMA driver version. */
|
||||
#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
|
||||
#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* Copyright 2017-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
@@ -128,6 +128,55 @@ void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnabl
|
||||
}
|
||||
}
|
||||
|
||||
void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error)
|
||||
{
|
||||
assert(error != NULL);
|
||||
|
||||
switch (memory)
|
||||
{
|
||||
case kFLEXRAM_OCRAM:
|
||||
base->OCRAM_ECC_ERROR_INJEC =
|
||||
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) |
|
||||
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) |
|
||||
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) |
|
||||
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) |
|
||||
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) |
|
||||
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion);
|
||||
break;
|
||||
case kFLEXRAM_ITCM:
|
||||
base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) |
|
||||
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) |
|
||||
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) |
|
||||
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) |
|
||||
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) |
|
||||
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion);
|
||||
break;
|
||||
case kFLEXRAM_D0TCM:
|
||||
base->D0TCM_ECC_ERROR_INJEC =
|
||||
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) |
|
||||
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) |
|
||||
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) |
|
||||
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) |
|
||||
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) |
|
||||
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion);
|
||||
break;
|
||||
case kFLEXRAM_D1TCM:
|
||||
base->D1TCM_ECC_ERROR_INJEC =
|
||||
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) |
|
||||
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) |
|
||||
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) |
|
||||
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) |
|
||||
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) |
|
||||
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion);
|
||||
break;
|
||||
default:
|
||||
assert(NULL);
|
||||
break;
|
||||
}
|
||||
|
||||
__DSB();
|
||||
}
|
||||
|
||||
void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
|
||||
{
|
||||
assert(NULL != info);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* Copyright 2017-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
@@ -23,8 +23,8 @@
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief Driver version 2.1.0. */
|
||||
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))
|
||||
/*! @brief Driver version. */
|
||||
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Get ECC error detailed information. */
|
||||
@@ -108,6 +108,29 @@ enum
|
||||
};
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
|
||||
/*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */
|
||||
typedef enum _flexram_memory_type
|
||||
{
|
||||
kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */
|
||||
kFLEXRAM_ITCM = 1U, /*!< Memory type ITCM */
|
||||
kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */
|
||||
kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */
|
||||
} flexram_memory_type_t;
|
||||
|
||||
/*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */
|
||||
typedef struct _flexram_ecc_error_type
|
||||
{
|
||||
uint8_t SingleBitPos; /*!< Bit position of the bit to inject ECC Error. */
|
||||
uint8_t SecondBitPos; /*!< Bit position of the second bit to inject multi-bit ECC Error */
|
||||
bool Fource1BitDataInversion; /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */
|
||||
bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write
|
||||
access */
|
||||
bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory
|
||||
write access */
|
||||
bool FourceContiNCDataInversion; /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on
|
||||
memory write access */
|
||||
} flexram_ecc_error_type_t;
|
||||
|
||||
/*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */
|
||||
typedef struct _flexram_ocram_ecc_single_error_info
|
||||
{
|
||||
@@ -422,6 +445,14 @@ static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAd
|
||||
*/
|
||||
void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
|
||||
|
||||
/*!
|
||||
* @brief FLEXRAM ECC error injection.
|
||||
* @param base FLEXRAM base address.
|
||||
* @param memory memory type, such as OCRAM/ITCM/DTCM.
|
||||
* @param error ECC error type.
|
||||
*/
|
||||
void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error);
|
||||
|
||||
/*!
|
||||
* @brief FLEXRAM get ocram ecc single error information.
|
||||
* @param base FLEXRAM base address.
|
||||
|
||||
@@ -33,10 +33,14 @@ enum
|
||||
FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */
|
||||
kFLEXSPI_FlashASampleClockRefDelayLocked =
|
||||
FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
|
||||
kFLEXSPI_FlashBSampleClockSlaveDelayLocked =
|
||||
FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */
|
||||
#endif
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK))
|
||||
kFLEXSPI_FlashBSampleClockRefDelayLocked =
|
||||
FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */
|
||||
@@ -293,10 +297,15 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
|
||||
|
||||
/* Configure MCR2 configurations. */
|
||||
configValue = base->MCR2;
|
||||
configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK |
|
||||
FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
|
||||
configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK |
|
||||
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
|
||||
FLEXSPI_MCR2_SCKBDIFFOPT_MASK |
|
||||
#endif
|
||||
FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
|
||||
configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
|
||||
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
|
||||
FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
|
||||
#endif
|
||||
FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
|
||||
FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
|
||||
|
||||
@@ -354,9 +363,11 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
|
||||
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
|
||||
config->enableCombination = false;
|
||||
#endif
|
||||
config->enableDoze = true;
|
||||
config->enableHalfSpeedAccess = false;
|
||||
config->enableSckBDiffOpt = false;
|
||||
config->enableDoze = true;
|
||||
config->enableHalfSpeedAccess = false;
|
||||
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
|
||||
config->enableSckBDiffOpt = false;
|
||||
#endif
|
||||
config->enableSameConfigForAll = false;
|
||||
config->seqTimeoutCycle = 0xFFFFU;
|
||||
config->ipGrantTimeoutCycle = 0xFFU;
|
||||
@@ -432,12 +443,18 @@ void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config,
|
||||
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
|
||||
|
||||
/* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
|
||||
statusValue =
|
||||
(index == 0U) ?
|
||||
((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked |
|
||||
(uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked) :
|
||||
if (index == 0U)
|
||||
{
|
||||
statusValue =
|
||||
((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked);
|
||||
}
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
|
||||
else
|
||||
{
|
||||
statusValue =
|
||||
((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked);
|
||||
|
||||
}
|
||||
#endif
|
||||
if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK))
|
||||
{
|
||||
/* Wait slave delay line locked and slave reference delay line locked. */
|
||||
@@ -527,11 +544,13 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
|
||||
base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
|
||||
base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask);
|
||||
}
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB))
|
||||
else
|
||||
{
|
||||
base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK;
|
||||
base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Exit stop mode. */
|
||||
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
|
||||
@@ -564,8 +583,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
|
||||
}
|
||||
|
||||
/* Unlock LUT for update. */
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
|
||||
base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
|
||||
base->LUTCR = 0x02;
|
||||
#endif
|
||||
base->LUTCR = 0x02;
|
||||
|
||||
lutBase = &base->LUT[index];
|
||||
for (i = 0; i < count; i++)
|
||||
@@ -574,8 +595,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
|
||||
}
|
||||
|
||||
/* Lock LUT. */
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
|
||||
base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
|
||||
base->LUTCR = 0x01;
|
||||
#endif
|
||||
base->LUTCR = 0x01;
|
||||
}
|
||||
|
||||
/*! brief Update read sample clock source
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief FLEXSPI driver version 2.3.5. */
|
||||
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 5))
|
||||
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6))
|
||||
/*@}*/
|
||||
|
||||
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
|
||||
@@ -190,8 +190,10 @@ typedef enum _flexspi_port
|
||||
{
|
||||
kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
|
||||
kFLEXSPI_PortA2, /*!< Access flash on A2 port. */
|
||||
kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
|
||||
kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
|
||||
kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
|
||||
kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
|
||||
#endif
|
||||
kFLEXSPI_PortCount
|
||||
} flexspi_port_t;
|
||||
|
||||
@@ -231,11 +233,13 @@ typedef struct _flexspi_config
|
||||
bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
|
||||
(SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
|
||||
#endif
|
||||
bool enableDoze; /*!< Enable/disable doze mode support. */
|
||||
bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
|
||||
speed commands. */
|
||||
bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
|
||||
output, when enable, Port B flash access is not available. */
|
||||
bool enableDoze; /*!< Enable/disable doze mode support. */
|
||||
bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
|
||||
speed commands. */
|
||||
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
|
||||
bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
|
||||
output, when enable, Port B flash access is not available. */
|
||||
#endif
|
||||
bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
|
||||
when enabled, same configuration in FLASHA1CRx is applied to all. */
|
||||
uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution,
|
||||
@@ -615,10 +619,12 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
|
||||
*portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
|
||||
}
|
||||
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB))
|
||||
if (portBPhase != NULL)
|
||||
{
|
||||
*portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -683,6 +689,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
|
||||
*/
|
||||
void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
|
||||
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN))
|
||||
/*! @brief Enables/disables the FLEXSPI IP command parallel mode.
|
||||
*
|
||||
* @param base FLEXSPI peripheral base address.
|
||||
@@ -699,7 +706,9 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
|
||||
base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN))
|
||||
/*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
|
||||
*
|
||||
* @param base FLEXSPI peripheral base address.
|
||||
@@ -716,6 +725,7 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
|
||||
base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @brief Updates the LUT table.
|
||||
*
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017, 2020 NXP
|
||||
* Copyright 2016-2017, 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
@@ -17,8 +17,10 @@
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Array of GPIO peripheral base address. */
|
||||
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
|
||||
#endif
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Array of GPIO clock name. */
|
||||
@@ -29,6 +31,7 @@ static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*!
|
||||
* @brief Gets the GPIO instance according to the GPIO base
|
||||
*
|
||||
@@ -58,6 +61,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
|
||||
|
||||
return instance;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* brief Initializes the GPIO peripheral according to the specified
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief GPIO driver version. */
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief GPIO direction definition. */
|
||||
|
||||
@@ -22,7 +22,7 @@
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
|
||||
#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2019-2021 NXP
|
||||
* Copyright 2019-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
@@ -448,3 +448,82 @@ status_t LCDIFV2_GetPorterDuffConfig(lcdifv2_pd_blend_mode_t mode,
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*
|
||||
* brief Get the global alpha values for multiple layer blend.
|
||||
*
|
||||
* When all layers use the global alpha, the relationship blended alpha
|
||||
* and global alpha of each layer is:
|
||||
*
|
||||
* Layer 7: ba7 = ga7
|
||||
* Layer 6: ba6 = ga6 * (1-ga7)
|
||||
* Layer 5: ba5 = ga5 * (1-ga6) * (1-ga7)
|
||||
* Layer 4: ba4 = ga4 * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 3: ba3 = ga3 * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 2: ba2 = ga2 * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 1: ba1 = ga1 * (1-ga2) * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 0: ba0 = 1 * (1-ga1) * (1-ga2) * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
*
|
||||
* Here baN is the blended alpha of layer N, gaN is the global alpha configured to layer N.
|
||||
*
|
||||
* This function calculates the global alpha based on the blended alpha. The blendedAlpha and
|
||||
* globalAlpha are all arrays of size layerCount. The first layer is a background layer,
|
||||
* so blendedAlpha[0] is useless, globalAlpha[0] is always 255.
|
||||
*
|
||||
* param blendedAlpha The desired blended alpha value, alpha range 0~255.
|
||||
* param globalAlpha Calculated global alpha set to each layer register.
|
||||
* param layerCount Total layer count.
|
||||
* retval kStatus_Success Get successfully.
|
||||
* retval kStatus_InvalidArgument The argument is invalid.
|
||||
*/
|
||||
status_t LCDIFV2_GetMultiLayerGlobalAlpha(const uint8_t blendedAlpha[], uint8_t globalAlpha[], uint8_t layerCount)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
int16_t curLayer = (int16_t)layerCount - 1;
|
||||
int left = 255;
|
||||
int tmpAlpha;
|
||||
|
||||
assert((layerCount > 1U) && (layerCount <= (uint8_t)LCDIFV2_LAYER_COUNT));
|
||||
|
||||
/*
|
||||
* Assume the layer counter is 7, and alpha range is 0~1, define:
|
||||
*
|
||||
* left_7 = 1
|
||||
* left_i = (1-ga_(i+1)) * ... * (1-ga7)
|
||||
*
|
||||
* Then:
|
||||
* ba_i = ga_i * left_i
|
||||
* left_i = left_(i+1) - ba_i
|
||||
* ga_i = ba_i / left_i
|
||||
*
|
||||
* Now change alpha range to 0~255, then:
|
||||
*
|
||||
* ga_i = ba_i * 255 / left_i
|
||||
* left_i = left_(i+1) - ba_i
|
||||
*/
|
||||
|
||||
globalAlpha[0] = 255U;
|
||||
|
||||
while (curLayer > 0)
|
||||
{
|
||||
tmpAlpha = (int)blendedAlpha[curLayer] * 255 / left;
|
||||
if (tmpAlpha > 255)
|
||||
{
|
||||
status = kStatus_InvalidArgument;
|
||||
break;
|
||||
}
|
||||
|
||||
globalAlpha[curLayer] = (uint8_t)tmpAlpha;
|
||||
left -= (int)blendedAlpha[curLayer];
|
||||
|
||||
if (left <= 0)
|
||||
{
|
||||
status = kStatus_InvalidArgument;
|
||||
break;
|
||||
}
|
||||
|
||||
curLayer--;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2019-2021 NXP
|
||||
* Copyright 2019-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
@@ -27,7 +27,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief LCDIF v2 driver version */
|
||||
#define FSL_LCDIFV2_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
|
||||
#define FSL_LCDIFV2_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_LCDIFV2_LAYER_COUNT) && (!defined(LCDIFV2_LAYER_COUNT))
|
||||
@@ -606,6 +606,45 @@ status_t LCDIFV2_GetPorterDuffConfig(lcdifv2_pd_blend_mode_t mode,
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Misc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get the global alpha values for multiple layer blend.
|
||||
*
|
||||
* This function calculates the global alpha value for each layer based on the
|
||||
* desired blended alpha.
|
||||
*
|
||||
* When all layers use the global alpha, the relationship of blended alpha
|
||||
* and global alpha of each layer is:
|
||||
*
|
||||
* Layer 7: ba7 = ga7
|
||||
* Layer 6: ba6 = ga6 * (1-ga7)
|
||||
* Layer 5: ba5 = ga5 * (1-ga6) * (1-ga7)
|
||||
* Layer 4: ba4 = ga4 * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 3: ba3 = ga3 * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 2: ba2 = ga2 * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 1: ba1 = ga1 * (1-ga2) * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
* Layer 0: ba0 = 1 * (1-ga1) * (1-ga2) * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)
|
||||
*
|
||||
* Here baN is the blended alpha of layer N, gaN is the global alpha configured to layer N.
|
||||
*
|
||||
* This function calculates the global alpha based on the blended alpha. The @p blendedAlpha and
|
||||
* @p globalAlpha are all arrays of size @p layerCount. The first layer is a background layer,
|
||||
* so blendedAlpha[0] is useless, globalAlpha[0] is always 255.
|
||||
*
|
||||
* @param[in] blendedAlpha The desired blended alpha value, alpha range 0~255.
|
||||
* @param[out] globalAlpha Calculated global alpha set to each layer register.
|
||||
* @param[in] layerCount Total layer count.
|
||||
* @retval kStatus_Success Get successfully.
|
||||
* @retval kStatus_InvalidArgument The argument is invalid.
|
||||
*/
|
||||
status_t LCDIFV2_GetMultiLayerGlobalAlpha(const uint8_t blendedAlpha[], uint8_t globalAlpha[], uint8_t layerCount);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user