Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-03-27 09:32:28 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Remove legacy.

Browse Source
This commit is contained in:
Wayne Lin
2020-08-26 13:09:37 +08:00
parent 241a29a13f
commit 3fef3b845d
437 changed files with 0 additions and 282092 deletions
Download Patch File Download Diff File Expand all files Collapse all files

308
bsp/nuvoton_m05x/.config
View File

@@ -1,308 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=512
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=512
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
#
# Test Packages of RealThread
#
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
CONFIG_RT_USING_UART0=y

5
bsp/nuvoton_m05x/.gitignore vendored
View File

@@ -1,5 +0,0 @@
Nu_Link_Driver.ini
*.uvoptx
*.uvguix.*
scons-cmd.bat
obj

30
bsp/nuvoton_m05x/Kconfig
View File

@@ -1,30 +0,0 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_M051
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config RT_USING_UART0
bool "Using Uart0"
select RT_USING_SERIAL
default y

BIN
bsp/nuvoton_m05x/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
View File

Binary file not shown.

37
bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_common_tables.h
View File

@@ -1,37 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 13/09/14 1:29p $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef[6144];
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
#endif /* ARM_COMMON_TABLES_H */

7556
bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_math.h
View File

File diff suppressed because it is too large Load Diff

673
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0.h
View File

File diff suppressed because it is too large Load Diff

778
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0plus.h
View File

File diff suppressed because it is too large Load Diff

1612
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm3.h
View File

File diff suppressed because it is too large Load Diff

1757
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4.h
View File

File diff suppressed because it is too large Load Diff

649
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4_simd.h
View File

File diff suppressed because it is too large Load Diff

620
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmFunc.h
View File

File diff suppressed because it is too large Load Diff

624
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmInstr.h
View File

File diff suppressed because it is too large Load Diff

798
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc000.h
View File

File diff suppressed because it is too large Load Diff

1583
bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc300.h
View File

File diff suppressed because it is too large Load Diff

6683
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/M051Series.h
View File

File diff suppressed because it is too large Load Diff

99
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/system_M051Series.h
View File

@@ -1,99 +0,0 @@
/**************************************************************************//**
* @file system_M051Series.h
* @version V3.00
* $Revision: 9 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series System Setting Header File
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __SYSTEM_M051Series_H__
#define __SYSTEM_M051Series_H__
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------------------------------------------------*/
/* Macro Definition */
/*---------------------------------------------------------------------------------------------------------*/
#ifndef DEBUG_PORT
# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
#endif
/**
*
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
* default clock source (External crystal or internal 22.1184MHz IRC).
* Enable this option will casue system booting in 50MHz(By XTAL) or 50.1918MHz(By IRC22M) according to
* user configuration setting in CONFIG0
*
*/
//#define INIT_SYSCLK_AT_BOOTING
/*----------------------------------------------------------------------------
Define SYSCLK
*----------------------------------------------------------------------------*/
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
#define __HSI (50000000UL) /*!< PLL default output is 48MHz@12M X'tal */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
#if USE_ASSERT
/**
* @brief Assert Function
*
* @param[in] expr Expression to be evaluated
*
* @return None
*
* @details If the expression is false, an error message will be printed out
* from debug port (UART0 or UART1).
*/
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
void AssertError(uint8_t* file, uint32_t line);
#else
#define ASSERT_PARAM(expr)
#endif
#define assert_param(expr) ASSERT_PARAM(expr)
/**
* @brief System Initializaiton
*
* @param None
*
* @return None
*
* @details The necessary initializaiton of system.
*/
extern void SystemInit(void);
/**
* @brief Update the Variable SystemCoreClock
*
* @param None
*
* @return None
*
* @details This function is used to update the variable SystemCoreClock
* and must be called whenever the core clock is changed.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif
/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */

237
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s
View File

@@ -1,237 +0,0 @@
;/**************************************************************************//**
; * @file startup_M051Series.s
; * @version V2.00
; * $Revision: 9 $
; * $Date: 14/01/10 9:11a $
; * @brief M051 Series Startup Source File
; *
; * @note
; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
; *
; ******************************************************************************/
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; maximum of 32 External Interrupts are possible
DCD BOD_IRQHandler
DCD WDT_IRQHandler
DCD EINT0_IRQHandler
DCD EINT1_IRQHandler
DCD GPIOP0P1_IRQHandler
DCD GPIOP2P3P4_IRQHandler
DCD PWMA_IRQHandler
DCD PWMB_IRQHandler
DCD TMR0_IRQHandler
DCD TMR1_IRQHandler
DCD TMR2_IRQHandler
DCD TMR3_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD Default_Handler
DCD Default_Handler
DCD I2C0_IRQHandler
DCD I2C1_IRQHandler
DCD Default_Handler
DCD Default_Handler
DCD Default_Handler
DCD Default_Handler
DCD Default_Handler
DCD ACMP01_IRQHandler
DCD ACMP23_IRQHandler
DCD Default_Handler
DCD PWRWU_IRQHandler
DCD ADC_IRQHandler
DCD Default_Handler
DCD RTC_IRQHandler
AREA |.text|, CODE, READONLY
; Reset Handler
ENTRY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =0x50000100
; Unlock Register
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Init POR
LDR R2, =0x50000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT GPIOP0P1_IRQHandler [WEAK]
EXPORT GPIOP2P3P4_IRQHandler [WEAK]
EXPORT PWMA_IRQHandler [WEAK]
EXPORT PWMB_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT ACMP01_IRQHandler [WEAK]
EXPORT ACMP23_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPIOP0P1_IRQHandler
GPIOP2P3P4_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
ACMP01_IRQHandler
ACMP23_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

275
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/GCC/startup_M051Series.s
View File

@@ -1,275 +0,0 @@
/**
******************************************************************************
* @file startup_M051Series.s
* @author RT-Thread Develop Team
* @version V1.0.0
* @date 2014-11-24
* @brief M051Series Devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Unlock Register */
ldr r0, =0x50000100
ldr r1, =0x59
str r1, [R0]
ldr r1, =0x16
str r1, [R0]
ldr r1, =0x88
str r1, [r0]
/* Init POR */
ldr r2, =0x50000024
ldr r1, =0x00005AA5
str r1, [r2]
/* Lock register */
movs r1, #0
str r1, [r0]
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2, #4]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/*******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
/* maximum of 32 External Interrupts are possible */
.word BOD_IRQHandler
.word WDT_IRQHandler
.word EINT0_IRQHandler
.word EINT1_IRQHandler
.word GPIOP0P1_IRQHandler
.word GPIOP2P3P4_IRQHandler
.word PWMA_IRQHandler
.word PWMB_IRQHandler
.word TMR0_IRQHandler
.word TMR1_IRQHandler
.word TMR2_IRQHandler
.word TMR3_IRQHandler
.word UART0_IRQHandler
.word UART1_IRQHandler
.word SPI0_IRQHandler
.word SPI1_IRQHandler
.word 0
.word 0
.word I2C0_IRQHandler
.word I2C1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word ACMP01_IRQHandler
.word ACMP23_IRQHandler
.word 0
.word PWRWU_IRQHandler
.word ADC_IRQHandler
.word 0
.word RTC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak BOD_IRQHandler
.thumb_set BOD_IRQHandler,Default_Handler
.weak WDT_IRQHandler
.thumb_set WDT_IRQHandler,Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler,Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler,Default_Handler
.weak GPIOP0P1_IRQHandler
.thumb_set GPIOP0P1_IRQHandler,Default_Handler
.weak GPIOP2P3P4_IRQHandler
.thumb_set GPIOP2P3P4_IRQHandler,Default_Handler
.weak PWMA_IRQHandler
.thumb_set PWMA_IRQHandler,Default_Handler
.weak PWMB_IRQHandler
.thumb_set PWMB_IRQHandler,Default_Handler
.weak TMR0_IRQHandler
.thumb_set TMR0_IRQHandler,Default_Handler
.weak TMR1_IRQHandler
.thumb_set TMR1_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak SPI0_IRQHandler
.thumb_set SPI0_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak I2C0_IRQHandler
.thumb_set I2C0_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak ACMP01_IRQHandler
.thumb_set ACMP01_IRQHandler,Default_Handler
.weak ACMP23_IRQHandler
.thumb_set ACMP23_IRQHandler,Default_Handler
.weak PWRWU_IRQHandler
.thumb_set PWRWU_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
/************************ END OF FILE ***********************/

178
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s
View File

@@ -1,178 +0,0 @@
;/**************************************************************************//**
; * @file startup_M051Series.s
; * @version V2.00
; * $Revision: 8 $
; * $Date: 14/02/12 10:11a $
; * @brief M051 Series Startup Source File for IAR Platform
; *
; * @note
; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
; *
; ******************************************************************************/
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
EXTERN SystemInit
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD __iar_program_start
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD BOD_IRQHandler ; Brownout low voltage detected interrupt
DCD WDT_IRQHandler ; Watch Dog Timer interrupt
DCD EINT0_IRQHandler ; External signal interrupt from PB.14 pin
DCD EINT1_IRQHandler ; External signal interrupt from PB.15 pin
DCD GPIOP0P1_IRQHandler ; External signal interrupt from P0[15:0] / P1[13:0]
DCD GPIOP2P3P4_IRQHandler ; External interrupt from P2[15:0]/P3[15:0]/P4[15:0]
DCD PWMA_IRQHandler ; PWM0 or PWM2 interrupt
DCD PWMB_IRQHandler ; PWM1 or PWM3 interrupt
DCD TMR0_IRQHandler ; Timer 0 interrupt
DCD TMR1_IRQHandler ; Timer 1 interrupt
DCD TMR2_IRQHandler ; Timer 2 interrupt
DCD TMR3_IRQHandler ; Timer 3 interrupt
DCD UART0_IRQHandler ; UART0 interrupt
DCD UART1_IRQHandler ; UART1 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD Default_Handler ; SPI2 interrupt
DCD Default_Handler ; SPI3 interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD ACMP01_IRQHandler ; ACMP0/1 interrupt
DCD ACMP23_IRQHandler ; ACMP2/3 interrupt
DCD Default_Handler ; Reserved
DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power-
DCD ADC_IRQHandler ; ADC interrupt
DCD Default_Handler ; Reserved
DCD RTC_IRQHandler ; Real time clock interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2) ; 4 bytes alignment
Reset_Handler
LDR R0, =0x50000100
; Unlock Register
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Init POR
LDR R2, =0x50000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Disable NMI (Assign to reserved IRQ)
LDR R2, =0x50000380
LDR R1, =0x0000001F
STR R1, [R2]
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK SVC_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK BOD_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK GPIOP0P1_IRQHandler
PUBWEAK GPIOP2P3P4_IRQHandler
PUBWEAK PWMA_IRQHandler
PUBWEAK PWMB_IRQHandler
PUBWEAK TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK ACMP01_IRQHandler
PUBWEAK ACMP23_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(2)
HardFault_Handler
NMI_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPIOP0P1_IRQHandler
GPIOP2P3P4_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
ACMP01_IRQHandler
ACMP23_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
Default_Handler
B Default_Handler
END

148
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
View File

@@ -1,148 +0,0 @@
/**************************************************************************//**
* @file system_M051Series.c
* @version V2.00
* $Revision: 13 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series System Setting Source File
*
* @note
* Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include "M051Series.h"
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
const uint32_t gau32ClkSrcTbl[] = {__HXT, NULL, __HSI, __LIRC, NULL, NULL, NULL, __HIRC};
/**
* @brief Update the Variable SystemCoreClock
*
* @param None
*
* @return None
*
* @details This function is used to update the variable SystemCoreClock
* and must be called whenever the core clock is changed.
*/
void SystemCoreClockUpdate(void)
{
uint32_t u32Freq, u32ClkSrc;
uint32_t u32HclkDiv;
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
/* Update PLL Clock */
PllClock = CLK_GetPLLClockFreq();
if(u32ClkSrc != CLK_CLKSEL0_HCLK_S_PLL)
{
/* Use the clock sources directly */
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
}
else
{
/* Use PLL clock */
u32Freq = PllClock;
}
u32HclkDiv = (CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1;
/* Update System Core Clock */
SystemCoreClock = u32Freq / u32HclkDiv;
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
}
/**
* @brief System Initialization
*
* @param None
*
* @return None
*
* @details The necessary initialization of system. Global variables are forbidden here.
*/
void SystemInit(void)
{
#ifdef INIT_SYSCLK_AT_BOOTING
int32_t i32TimeoutCnt;
uint32_t u32HclkSelect;
int8_t i8IsPllEn;
PllClock = 0;
i8IsPllEn = 0;
u32HclkSelect = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
if(u32HclkSelect == CLK_CLKSEL0_HCLK_S_HXT)
{
/* Set to 50MHz system clock frequency when clock source is from external 12MHz */
CLK->PLLCON = CLK_PLLCON_50MHz_HXT;
/* Waiting for PLL ready */
i32TimeoutCnt = (__HXT / 1000); /* Timeout is about 1ms */
while((CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk) == 0)
{
if(i32TimeoutCnt-- <= 0)
break;
}
i8IsPllEn = 1;
}
else if(u32HclkSelect == CLK_CLKSEL0_HCLK_S_HIRC)
{
/* Set to 50.1918MHz system clock frequency when clock source is from internal 22.1184MHz RC clock */
CLK->PLLCON = CLK_PLLCON_50MHz_HIRC;
/* Waiting for PLL ready */
i32TimeoutCnt = (__HIRC / 1000); /* Timeout is about 1ms */
while((CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk) == 0)
{
if(i32TimeoutCnt-- <= 0)
break;
}
i8IsPllEn = 1;
}
if(i8IsPllEn)
{
/* Set PLL as HCLK clock source (HCLK_S is locked setting)*/
SYS_UnlockReg();
CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL;
SYS_LockReg();
}
#endif
}
#if USE_ASSERT
/**
* @brief Assert Error Message
*
* @param[in] file the source file name
* @param[in] line line number
*
* @return None
*
* @details The function prints the source file name and line number where
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
*/
void AssertError(uint8_t * file, uint32_t line)
{
printf("[%s] line %d : wrong parameters.\r\n", file, line);
/* Infinite loop */
while(1) ;
}
#endif

37
bsp/nuvoton_m05x/Libraries/CMSIS/README.txt
View File

@@ -1,37 +0,0 @@
* -------------------------------------------------------------------
* Copyright (C) 2011-2012 ARM Limited. All rights reserved.
*
* Date: 07 March 2012
* Revision: V3.01
*
* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
* Title: Release Note for CMSIS
*
* -------------------------------------------------------------------
NOTE - Open the index.html file to access CMSIS documentation
The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
and reduces time-to-market for new embedded applications.
CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
Any user of the software package is bound to the terms and conditions of the end user license agreement.
You will find the following sub-directories:
Documentation - Contains CMSIS documentation.
DSP_Lib - MDK project files, Examples and source files etc.. to build the
CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
Include - CMSIS Core Support and CMSIS DSP Include Files.
Lib - CMSIS DSP Libraries.
RTOS - CMSIS RTOS API template header file.
SVD - CMSIS SVD Schema files and Conversion Utility.

14
bsp/nuvoton_m05x/Libraries/CMSIS/index.html
View File

@@ -1,14 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Redirect to the CMSIS main page after 0 seconds</title>
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
</body>
</html>

31
bsp/nuvoton_m05x/Libraries/SConscript
View File

@@ -1,31 +0,0 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
""")
src += Glob('StdDriver/src/*.c')
#add for startup script
if rtconfig.CROSS_TOOL == 'iar':
src = src + ['CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s']
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s']
elif rtconfig.CROSS_TOOL == 'gcc':
src = src + ['CMSIS/Nuvoton/M051Series/Source/GCC/startup_M051Series.s']
path = [cwd + '/StdDriver/inc',
cwd + '/CMSIS/Nuvoton/M051Series/Include',
cwd + '/CMSIS/Include']
#CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
CPPDEFINES = ['INIT_SYSCLK_AT_BOOTING']
group = DefineGroup('M05X_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

167
bsp/nuvoton_m05x/Libraries/StdDriver/inc/acmp.h
View File

@@ -1,167 +0,0 @@
/**************************************************************************//**
* @file acmp.h
* @version V3.00
* $Revision: 6 $
* $Date: 1/28/14 11:32a $
* @brief M051 series Analog Comparator(ACMP) driver header file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_H__
#define __ACMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup M051_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* ACMP_CR constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ACMP_CR_OUTPUT_INV (1UL << ACMP_CR_ACMPOINV_Pos) /*!< ACMP_CR setting for ACMP output inverse function. */
#define ACMP_CR_VNEG_BANDGAP (1UL << ACMP_CR_NEGSEL_Pos) /*!< ACMP_CR setting for selecting band-gap voltage as the source of ACMP V-. */
#define ACMP_CR_VNEG_PIN (0UL << ACMP_CR_NEGSEL_Pos) /*!< ACMP_CR setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
#define ACMP_CR_HYSTERESIS_ENABLE (1UL << ACMP_CR_HYSEN_Pos) /*!< ACMP_CR setting for enabling the hysteresis function. */
#define ACMP_CR_HYSTERESIS_DISABLE (0UL << ACMP_CR_HYSEN_Pos) /*!< ACMP_CR setting for disabling the hysteresis function. */
#define ACMP_CR_INT_ENABLE (1UL << ACMP_CR_ACMPIE_Pos) /*!< ACMP_CR setting for enabling the interrupt function. */
#define ACMP_CR_INT_DISABLE (0UL << ACMP_CR_ACMPIE_Pos) /*!< ACMP_CR setting for disabling the interrupt function. */
#define ACMP_CR_ACMP_ENABLE (1UL << ACMP_CR_ACMPEN_Pos) /*!< ACMP_CR setting for enabling the ACMP analog circuit. */
#define ACMP_CR_ACMP_DISABLE (0UL << ACMP_CR_ACMPEN_Pos) /*!< ACMP_CR setting for disabling the ACMP analog circuit. */
/*@}*/ /* end of group M051_ACMP_EXPORTED_CONSTANTS */
/** @addtogroup M051_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief This macro is used to enable output inverse
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPOINV_Msk)
/**
* @brief This macro is used to disable output inverse
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPOINV_Msk)
/**
* @brief This macro is used to select ACMP negative input source
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Src is comparator0 negative input selection. Including :
* - \ref ACMP_CR_VNEG_PIN
* - \ref ACMP_CR_VNEG_BANDGAP
* @return None
*/
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CR[(u32ChNum)%2] = ((acmp)->CR[(u32ChNum)%2] & ~ACMP_CR_NEGSEL_Msk) | (u32Src))
/**
* @brief This macro is used to enable hysteresis function
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_HYSEN_Msk)
/**
* @brief This macro is used to disable hysteresis function
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_HYSEN_Msk)
/**
* @brief This macro is used to enable interrupt
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPIE_Msk)
/**
* @brief This macro is used to disable interrupt
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPIE_Msk)
/**
* @brief This macro is used to enable ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPEN_Msk)
/**
* @brief This macro is used to disable ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPEN_Msk)
/**
* @brief This macro is used to get ACMP output value
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return 1 or 0
*/
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->SR & (ACMP_SR_ACMPO0_Msk<<((u32ChNum)%2)))?1:0)
/**
* @brief This macro is used to get ACMP interrupt flag
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return ACMP interrupt occurred or not
*/
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->SR & (ACMP_SR_ACMPF0_Msk<<((u32ChNum)%2)))?1:0)
/**
* @brief This macro is used to clear ACMP interrupt flag
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->SR = (ACMP_SR_ACMPF0_Msk<<((u32ChNum)%2)))
void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
/*@}*/ /* end of group M051_ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ACMP_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__ACMP_H__
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

335
bsp/nuvoton_m05x/Libraries/StdDriver/inc/adc.h
View File

@@ -1,335 +0,0 @@
/**************************************************************************//**
* @file adc.h
* @version V3.0
* $Revision: 10 $
* $Date: 14/02/10 2:27p $
* @brief M051 series ADC driver header file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ADC_H__
#define __ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ADC_Driver ADC Driver
@{
*/
/** @addtogroup M051_ADC_EXPORTED_CONSTANTS ADC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* ADCR Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_ADCR_ADEN_CONVERTER_DISABLE (0UL<<ADC_ADCR_ADEN_Pos) /*!< ADC converter disable */
#define ADC_ADCR_ADEN_CONVERTER_ENABLE (1UL<<ADC_ADCR_ADEN_Pos) /*!< ADC converter enable */
#define ADC_ADCR_ADMD_SINGLE (0UL<<ADC_ADCR_ADMD_Pos) /*!< Single mode */
#define ADC_ADCR_ADMD_BURST (1UL<<ADC_ADCR_ADMD_Pos) /*!< Burst mode */
#define ADC_ADCR_ADMD_SINGLE_CYCLE (2UL<<ADC_ADCR_ADMD_Pos) /*!< Single cycle scan mode */
#define ADC_ADCR_ADMD_CONTINUOUS (3UL<<ADC_ADCR_ADMD_Pos) /*!< Continuous scan mode */
#define ADC_ADCR_DIFFEN_SINGLE_END (0UL<<ADC_ADCR_DIFFEN_Pos) /*!< Single end input mode */
#define ADC_ADCR_DIFFEN_DIFFERENTIAL (1UL<<ADC_ADCR_DIFFEN_Pos) /*!< Differential input type */
#define ADC_ADCR_DMOF_UNSIGNED_OUTPUT (0UL<<ADC_ADCR_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */
#define ADC_ADCR_DMOF_TWOS_COMPLEMENT (1UL<<ADC_ADCR_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */
#define ADC_ADCR_TRGEN_DISABLE (0UL<<ADC_ADCR_TRGEN_Pos) /*!< Disable triggering of A/D conversion by external STADC pin or PWM */
#define ADC_ADCR_TRGEN_ENABLE (1UL<<ADC_ADCR_TRGEN_Pos) /*!< Enable triggering of A/D conversion by external STADC pin or PWM */
#define ADC_ADCR_TRGS_STADC (0UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by external STADC pin */
#define ADC_ADCR_TRGS_PWM (3UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by PWM */
#define ADC_ADCR_TRGCOND_LOW_LEVEL (0UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Low level active */
#define ADC_ADCR_TRGCOND_HIGH_LEVEL (1UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC High level active */
#define ADC_ADCR_TRGCOND_FALLING_EDGE (2UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Falling edge active */
#define ADC_ADCR_TRGCOND_RISING_EDGE (3UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Rising edge active */
/*---------------------------------------------------------------------------------------------------------*/
/* ADCHER Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_ADCHER_PRESEL_EXT_INPUT_SIGNAL (0UL<<ADC_ADCHER_PRESEL_Pos) /*!< The input source of channel 7 is the external analog input */
#define ADC_ADCHER_PRESEL_INT_BANDGAP (1UL<<ADC_ADCHER_PRESEL_Pos) /*!< The input source of channel 7 is the internal bandgap voltage */
#define ADC_ADCHER_PRESEL_INT_TEMPERATURE_SENSOR (2UL<<ADC_ADCHER_PRESEL_Pos) /*!< The input source of channel 7 is the output of internal temperature sensor */
/*---------------------------------------------------------------------------------------------------------*/
/* ADCMPR Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_ADCMPR_CMPD(x) ((x) << ADC_ADCMPR_CMPD_Pos) /*!< Compare value for compare function */
#define ADC_ADCMPR_CMPMATCNT(x) (((x)-1) << ADC_ADCMPR_CMPMATCNT_Pos) /*!< Match count for compare function */
#define ADC_ADCMPR_CMPCH(x) ((x) << ADC_ADCMPR_CMPCH_Pos) /*!< Compare channel for compare function */
#define ADC_ADCMPR_CMPCOND_LESS_THAN (0<<ADC_ADCMPR_CMPCOND_Pos) /*!< The compare condition is "less than" */
#define ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL (1<<ADC_ADCMPR_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
#define ADC_ADCMPR_CMPIE_INTERRUPT_ENABLE (ADC_ADCMPR_CMPIE_Msk) /*!< The compare function interrupt enable */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC Interrupt Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_ADF_INT (ADC_ADSR_ADF_Msk) /*!< ADC convert complete interrupt */
#define ADC_CMP0_INT (ADC_ADSR_CMPF0_Msk) /*!< ADC comparator 0 interrupt */
#define ADC_CMP1_INT (ADC_ADSR_CMPF1_Msk) /*!< ADC comparator 1 interrupt */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC Operation Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_SINGLE_MODE 0 /*!< ADC single mode */
#define ADC_BURST_MODE 1 /*!< ADC burst mode */
#define ADC_SINGLE_CYCLE_MODE 2 /*!< ADC single-cycle scan mode */
#define ADC_CONTINUOUS_MODE 3 /*!< ADC continuous scan mode */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC Trigger Condition Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_LOW_LEVEL 0 /*!< ADC external trigger condition is low level trigger */
#define ADC_HIGH_LEVEL 1 /*!< ADC external trigger condition is high level trigger */
#define ADC_FALLING_EDGE 2 /*!< ADC external trigger condition is falling edge trigger */
#define ADC_RISING_EDGE 3 /*!< ADC external trigger condition is rising edge trigger */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC Compare Condition Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_LESS_THAN 0 /*!< ADC compare condition is "less than the compare value" */
#define ADC_GREATER_OR_EQUAL 1 /*!< ADC compare condition is "greater than or equal to the compare value" */
/*---------------------------------------------------------------------------------------------------------*/
/* Constant Definitions of ADC Channel 7 Input Source */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_CH7_EXT_INPUT_SIGNAL 0 /*!< External input signal */
#define ADC_CH7_INT_BANDGAP 1 /*!< Internal band-gap voltage */
#define ADC_CH7_INT_TEMPERATURE_SENSOR 2 /*!< Internal temperature sensor */
/*@}*/ /* end of group M051_ADC_EXPORTED_CONSTANTS */
/** @addtogroup M051_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
@{
*/
/**
* @brief Configure the analog input source of channel 7.
* @param[in] adc Base address of ADC module.
* @param[in] u32Source Decides the analog input source of channel 7. Valid values are:
* - \ref ADC_ADCHER_PRESEL_EXT_INPUT_SIGNAL : External analog input.
* - \ref ADC_ADCHER_PRESEL_INT_BANDGAP : Internal bandgap voltage.
* - \ref ADC_ADCHER_PRESEL_INT_TEMPERATURE_SENSOR : Output of internal temperature sensor.
* @return None
* @note While using VBG as channel 7 source, ADC module clock must /b not exceed 300kHz.
*/
#define ADC_CONFIG_CH7(adc, u32Source) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_PRESEL_Msk) | (u32Source))
/**
* @brief Get conversion data of specified channel.
* @param[in] adc Base address of ADC module.
* @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
* @return Read RSLT bit field to get conversion data.
*/
#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((ADC->ADDR[(u32ChNum)] & ADC_ADDR_RSLT_Msk)>>ADC_ADDR_RSLT_Pos)
/**
* @brief Return the user-specified interrupt flags.
* @param[in] adc Base address of ADC module.
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
* Valid values are:
* - \ref ADC_ADF_INT :Convert complete interrupt flag.
* - \ref ADC_CMP0_INT :Comparator 0 interrupt flag.
* - \ref ADC_CMP1_INT :Comparator 1 interrupt flag.
* @return User specified interrupt flags.
*/
#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->ADSR & (u32Mask))
/**
* @brief This macro clear the selected interrupt status bits.
* @param[in] adc Base address of ADC module.
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
* Valid values are:
* - \ref ADC_ADF_INT :Convert complete interrupt flag
* - \ref ADC_CMP0_INT :Comparator 0 interrupt flag
* - \ref ADC_CMP1_INT :Comparator 1 interrupt flag
* @return None
*/
#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->ADSR = u32Mask)
/**
* @brief Get the busy state of ADC.
* @param[in] adc Base address of ADC module.
* @return busy state of ADC.
* @retval 0 ADC is not busy.
* @retval 1 ADC is busy.
*/
#define ADC_IS_BUSY(adc) (ADC->ADSR & ADC_ADSR_BUSY_Msk ? 1 : 0)
/**
* @brief Check if the ADC conversion data is over written or not.
* @param[in] adc Base address of ADC module.
* @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
* @return Over run state of ADC data.
* @retval 0 ADC data is not overrun.
* @retval 1 ADC data us overrun.
*/
#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->ADSR & (u32ChNum<<ADC_ADSR_OVERRUN_Pos) ? 1 : 0)
/**
* @brief Check if the ADC conversion data is valid or not.
* @param[in] adc Base address of ADC module.
* @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
* @return Valid state of ADC data.
* @retval 0 ADC data is not valid.
* @retval 1 ADC data us valid.
*/
#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->ADSR & (0x1<<(ADC_ADSR_VALID_Pos+u32ChNum)) ? 1 : 0)
/**
* @brief Power down ADC module.
* @param[in] adc Base address of ADC module.
* @return None
*/
#define ADC_POWER_DOWN(adc) (ADC->ADCR &= ~ADC_ADCR_ADEN_Msk)
/**
* @brief Power on ADC module.
* @param[in] adc Base address of ADC module.
* @return None
*/
#define ADC_POWER_ON(adc) (ADC->ADCR |= ADC_ADCR_ADEN_Msk)
/**
* @brief Configure the comparator 0 and enable it.
* @param[in] adc Base address of ADC module.
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7.
* @param[in] u32Condition Specifies the compare condition. Valid values are:
* - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
* - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
* @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
* @return None
* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
* Means ADC will assert comparator 0 flag if channel 5 conversion result is greater or
* equal to 0x800 for 10 times continuously.
* @note When DIFFEN bit is set to 1, ADC comparator compares CMPD with conversion result with unsigned
* format (M05xxBN only). u32Data should be filled in unsigned format (straight binary format).
*/
#define ADC_ENABLE_CMP0(adc, \
u32ChNum, \
u32Condition, \
u32Data, \
u32MatchCount) (ADC->ADCMPR[0] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
u32Condition | \
((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
(((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
ADC_ADCMPR_CMPEN_Msk)
/**
* @brief Disable comparator 0
* @param[in] adc Base address of ADC module
*/
#define ADC_DISABLE_CMP0(adc) (ADC->ADCMPR[0] = 0)
/**
* @brief Configure the comparator 1 and enable it.
* @param[in] adc Base address of ADC module.
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7.
* @param[in] u32Condition Specifies the compare condition. Valid values are:
* - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
* - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
* @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
* @return None
* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
* Means ADC will assert comparator 1 flag if channel 5 conversion result is greater or
* equal to 0x800 for 10 times continuously.
*/
#define ADC_ENABLE_CMP1(adc, \
u32ChNum, \
u32Condition, \
u32Data, \
u32MatchCount) (ADC->ADCMPR[1] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
u32Condition | \
((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
(((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
ADC_ADCMPR_CMPEN_Msk)
/**
* @brief Disable comparator 1.
* @param[in] adc Base address of ADC module.
*/
#define ADC_DISABLE_CMP1(adc) (ADC->ADCMPR[1] = 0)
/**
* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
* @param[in] adc Base address of ADC module.
* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7.
* @return None
* @note M051 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
* with smallest number will be convert.
*/
#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32Mask))
/**
* @brief Set the output format mode.
* @param[in] adc Base address of ADC module.
* @param[in] u32Format Decides the output format. Valid values are:
* - \ref ADC_ADCR_DMOF_UNSIGNED_OUTPUT :Select the straight binary format as the output format of the conversion result.
* - \ref ADC_ADCR_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
* @return None
* @note Burst mode and ADC compare function can not support 2's complement output format,
* this u32Format must be 0 (M05xxBN only).
*/
#define ADC_SET_DMOF(adc, u32Format) (ADC->ADCR = (ADC->ADCR & ~ADC_ADCR_DMOF_Msk) | (u32Format))
/**
* @brief Start the A/D conversion.
* @param[in] adc Base address of ADC module.
* @return None
*/
#define ADC_START_CONV(adc) (ADC->ADCR |= ADC_ADCR_ADST_Msk)
/**
* @brief Stop the A/D conversion.
* @param[in] adc Base address of ADC module.
* @return None
* @note When hardware clears the ADST bit, the ADST bit must be kept at 0 at least one ADC peripheral clock
* period before setting it to 1 again, otherwise the A/D converter may not work (M05xxBN only). If ADST
* bit is cleared to 0 when ADC is in converting, the BUSY bit will be cleared to 0 immediately, ADC will
* finish the current conversion and save the result to the ADDRx register of the enabled channel (M05xxBN only).
* But, ADC can not finish the current conversion and A/D converter enters idle state directly (M05xxDN only).
*/
#define ADC_STOP_CONV(adc) (ADC->ADCR &= ~ADC_ADCR_ADST_Msk)
void ADC_Open(ADC_T *adc,
uint32_t u32InputMode,
uint32_t u32OpMode,
uint32_t u32ChMask);
void ADC_Close(ADC_T *adc);
void ADC_EnableHWTrigger(ADC_T *adc,
uint32_t u32Source,
uint32_t u32Param);
void ADC_DisableHWTrigger(ADC_T *adc);
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
/*@}*/ /* end of group M051_ADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ADC_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__ADC_H__
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

279
bsp/nuvoton_m05x/Libraries/StdDriver/inc/clk.h
View File

@@ -1,279 +0,0 @@
/**************************************************************************//**
* @file clk.h
* @version V3.0
* $Revision: 17 $
* $Date: 14/01/28 1:11p $
* @brief M051 Series Clock Control Driver Header File
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __CLK_H__
#define __CLK_H__
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_CLK_Driver CLK Driver
@{
*/
/** @addtogroup M051_CLK_EXPORTED_FUNCTIONS CLK Exported Constants
@{
*/
#define FREQ_25MHZ 25000000
#define FREQ_50MHZ 50000000
#define FREQ_100MHZ 100000000
#define FREQ_200MHZ 200000000
/*---------------------------------------------------------------------------------------------------------*/
/* PWRCON constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PWRCON_HXT_EN (0x01UL<<CLK_PWRCON_XTL12M_EN_Pos) /*!< Enable 4~24 MHz External High Speed Crystal (HXT) */
#define CLK_PWRCON_HIRC_EN (0x01UL<<CLK_PWRCON_OSC22M_EN_Pos) /*!< Enable 22.1184 MHz Internal High Speed RC Oscillator (HIRC) */
#define CLK_PWRCON_LIRC_EN (0x01UL<<CLK_PWRCON_OSC10K_EN_Pos) /*!< Enable 10 kHz Internal Low Speed RC Oscillator (LIRC) */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL0 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL0_HCLK_S_HXT 0x00UL /*!< Setting HCLK clock source as HXT */
#define CLK_CLKSEL0_HCLK_S_PLL 0x02UL /*!< Setting HCLK clock source as PLL */
#define CLK_CLKSEL0_HCLK_S_LIRC 0x03UL /*!< Setting HCLK clock source as LIRC */
#define CLK_CLKSEL0_HCLK_S_HIRC 0x07UL /*!< Setting HCLKclock source as HIRC */
#define CLK_CLKSEL0_STCLK_S_HXT 0x00UL /*!< Setting SysTick clock source as HXT */
#define CLK_CLKSEL0_STCLK_S_HXT_DIV2 0x10UL /*!< Setting SysTick clock source as HXT/2 */
#define CLK_CLKSEL0_STCLK_S_HCLK_DIV2 0x18UL /*!< Setting SysTick clock source as HCLK/2 */
#define CLK_CLKSEL0_STCLK_S_HIRC_DIV2 0x38UL /*!< Setting SysTick clock source as internal HIRC/2 */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL1_WDT_S_HCLK_DIV2048 0x00000002UL /*!< Setting WDT clock source as HCLK/2048 */
#define CLK_CLKSEL1_WDT_S_LIRC 0x00000003UL /*!< Setting WDT clock source as LIRC */
#define CLK_CLKSEL1_ADC_S_HXT 0x00000000UL /*!< Setting ADC clock source as HXT */
#define CLK_CLKSEL1_ADC_S_PLL 0x00000004UL /*!< Setting ADC clock source as PLL */
#define CLK_CLKSEL1_ADC_S_HCLK 0x00000008UL /*!< Setting ADC clock source as HCLK */
#define CLK_CLKSEL1_ADC_S_HIRC 0x0000000CUL /*!< Setting ADC clock source as HIRC */
#define CLK_CLKSEL1_SPI0_S_PLL 0x00000000UL /*!< Setting SPI0 clock source as PLL */
#define CLK_CLKSEL1_SPI0_S_HCLK 0x00000010UL /*!< Setting SPI0 clock source as HCLK */
#define CLK_CLKSEL1_SPI1_S_PLL 0x00000000UL /*!< Setting SPI1 clock source as PLL */
#define CLK_CLKSEL1_SPI1_S_HCLK 0x00000020UL /*!< Setting SPI1 clock source as HCLK */
#define CLK_CLKSEL1_TMR0_S_HXT 0x00000000UL /*!< Setting Timer 0 clock source as HXT */
#define CLK_CLKSEL1_TMR0_S_HCLK 0x00000200UL /*!< Setting Timer 0 clock source as HCLK */
#define CLK_CLKSEL1_TMR0_S_T0 0x00000300UL /*!< Setting Timer 0 clock source as T0 */
#define CLK_CLKSEL1_TMR0_S_LIRC 0x00000500UL /*!< Setting Timer 0 clock source as LIRC */
#define CLK_CLKSEL1_TMR0_S_HIRC 0x00000700UL /*!< Setting Timer 0 clock source as HIRC */
#define CLK_CLKSEL1_TMR1_S_HXT 0x00000000UL /*!< Setting Timer 1 clock source as HXT */
#define CLK_CLKSEL1_TMR1_S_HCLK 0x00002000UL /*!< Setting Timer 1 clock source as HCLK */
#define CLK_CLKSEL1_TMR1_S_T1 0x00003000UL /*!< Setting Timer 1 clock source as T1 */
#define CLK_CLKSEL1_TMR1_S_LIRC 0x00005000UL /*!< Setting Timer 1 clock source as LIRC */
#define CLK_CLKSEL1_TMR1_S_HIRC 0x00007000UL /*!< Setting Timer 1 clock source as HIRC */
#define CLK_CLKSEL1_TMR2_S_HXT 0x00000000UL /*!< Setting Timer 2 clock source as HXT */
#define CLK_CLKSEL1_TMR2_S_S_HCLK 0x00020000UL /*!< Setting Timer 2 clock source as HCLK */
#define CLK_CLKSEL1_TMR2_S_T2 0x00030000UL /*!< Setting Timer 2 clock source as T2 */
#define CLK_CLKSEL1_TMR2_S_LIRC 0x00050000UL /*!< Setting Timer 2 clock source as LIRC */
#define CLK_CLKSEL1_TMR2_S_HIRC 0x00070000UL /*!< Setting Timer 2 clock source as HIRC */
#define CLK_CLKSEL1_TMR3_S_HXT 0x00000000UL /*!< Setting Timer 3 clock source as HXT */
#define CLK_CLKSEL1_TMR3_S_HCLK 0x00200000UL /*!< Setting Timer 3 clock source as HCLK */
#define CLK_CLKSEL1_TMR3_S_S_T3 0x00300000UL /*!< Setting Timer 3 clock source as T3 */
#define CLK_CLKSEL1_TMR3_S_LIRC 0x00500000UL /*!< Setting Timer 3 clock source as LIRC */
#define CLK_CLKSEL1_TMR3_S_HIRC 0x00700000UL /*!< Setting Timer 3 clock source as HIRC */
#define CLK_CLKSEL1_UART_S_HXT 0x00000000UL /*!< Setting UART clock source as HXT */
#define CLK_CLKSEL1_UART_S_PLL 0x01000000UL /*!< Setting UART clock source as PLL */
#define CLK_CLKSEL1_UART_S_HIRC 0x03000000UL /*!< Setting UART clock source as HIRC */
#define CLK_CLKSEL1_PWM01_S_HXT 0x00000000UL /*!< Setting PWM01 clock source as HXT */
#define CLK_CLKSEL1_PWM01_S_LIRC 0x10000000UL /*!< Setting PWM01 clock source as LIRC */
#define CLK_CLKSEL1_PWM01_S_HCLK 0x20000000UL /*!< Setting PWM01 clock source as HCLK */
#define CLK_CLKSEL1_PWM01_S_HIRC 0x30000000UL /*!< Setting PWM01 clock source as HIRC */
#define CLK_CLKSEL1_PWM23_S_HXT 0x00000000UL /*!< Setting PWM23 clock source as HXT */
#define CLK_CLKSEL1_PWM23_S_LIRC 0x40000000UL /*!< Setting PWM23 clock source as LIRC */
#define CLK_CLKSEL1_PWM23_S_HCLK 0x80000000UL /*!< Setting PWM23 clock source as HCLK */
#define CLK_CLKSEL1_PWM23_S_HIRC 0xC0000000UL /*!< Setting PWM23 clock source as HIRC */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL2_FRQDIV_S_HXT 0x00000000UL /*!< Setting FRQDIV clock source as HXT */
#define CLK_CLKSEL2_FRQDIV_S_LIRC 0x00000004UL /*!< Setting FRQDIV clock source as LIRC */
#define CLK_CLKSEL2_FRQDIV_S_HCLK 0x00000008UL /*!< Setting FRQDIV clock source as HCLK */
#define CLK_CLKSEL2_FRQDIV_S_HIRC 0x0000000CUL /*!< Setting FRQDIV clock source as HIRC */
#define CLK_CLKSEL2_PWM45_S_HXT 0x00000000UL /*!< Setting PWM45 clock source as HXT */
#define CLK_CLKSEL2_PWM45_S_LIRC 0x00000010UL /*!< Setting PWM45 clock source as LIRC */
#define CLK_CLKSEL2_PWM45_S_HCLK 0x00000020UL /*!< Setting PWM45 clock source as HCLK */
#define CLK_CLKSEL2_PWM45_S_HIRC 0x00000030UL /*!< Setting PWM45 clock source as HIRC */
#define CLK_CLKSEL2_PWM67_S_HXT 0x00000000UL /*!< Setting PWM67 clock source as HXT */
#define CLK_CLKSEL2_PWM67_S_LIRC 0x00000040UL /*!< Setting PWM67 clock source as LIRC */
#define CLK_CLKSEL2_PWM67_S_HCLK 0x00000080UL /*!< Setting PWM67 clock source as HCLK */
#define CLK_CLKSEL2_PWM67_S_HIRC 0x000000C0UL /*!< Setting PWM67 clock source as HIRC */
#define CLK_CLKSEL2_WWDT_S_HCLK_DIV2048 0x00020000UL /*!< Setting WWDT clock source as HCLK/2048 */
#define CLK_CLKSEL2_WWDT_S_LIRC 0x00030000UL /*!< Setting WWDT clock source as LIRC */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV_ADC(x) (((x)-1) << 16) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 */
#define CLK_CLKDIV_UART(x) (((x)-1) << 8) /*!< CLKDIV Setting for UART clock divider. It could be 1~16 */
#define CLK_CLKDIV_HCLK(x) ((x)-1) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 */
/*---------------------------------------------------------------------------------------------------------*/
/* PLLCON constant definitions. PLL = FIN * NF / NR / NO */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PLLCON_PLL_SRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN < 24MHz */
#define CLK_PLLCON_PLL_SRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN < 24MHz */
#define CLK_PLLCON_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 15MHz */
#define CLK_PLLCON_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.) */
#define CLK_PLLCON_NO_1 0x0000UL /*!< For output divider is 1 */
#define CLK_PLLCON_NO_2 0x4000UL /*!< For output divider is 2 */
#define CLK_PLLCON_NO_4 0xC000UL /*!< For output divider is 4 */
#define CLK_PLLCON_50MHz_HXT (CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR(3) | CLK_PLLCON_NF( 25) | CLK_PLLCON_NO_2) /*!< Predefined PLLCON setting for 50MHz PLL output with 12MHz X'tal */
#define CLK_PLLCON_50MHz_HIRC (CLK_PLLCON_PLL_SRC_HIRC | CLK_PLLCON_NR(13) | CLK_PLLCON_NF( 59) | CLK_PLLCON_NO_2) /*!< Predefined PLLCON setting for 50.1918MHz PLL output with 22.1184MHz IRC */
/*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define MODULE_APBCLK(x) ((x >>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
/*-------------------------------------------------------------------------------------------------------------------------------------------------*/
/* APBCLK(31)|CLKSEL(30:29)|CLKSEL_Msk(28:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0)*/
/*-------------------------------------------------------------------------------------------------------------------------------------------------*/
#define WDT_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |( 0<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_WDT_EN_Pos ) /*!< WDT Module */
#define TMR0_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |( 8<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR0_EN_Pos) /*!< TMR0 Module */
#define TMR1_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |(12<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR1_EN_Pos) /*!< TMR1 Module */
#define TMR2_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |(16<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR0_EN_Pos) /*!< TMR2 Module */
#define TMR3_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |(20<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR1_EN_Pos) /*!< TMR3 Module */
#define FDIV_MODULE ((0x0<<31)|(0x3<<29) |(0x3<<25) |( 2<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_FDIV_EN_Pos) /*!< FDIV Module */
#define I2C0_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_I2C0_EN_Pos) /*!< I2C0 Module */
#define I2C1_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_I2C1_EN_Pos) /*!< I2C1 Module */
#define SPI0_MODULE ((0x0<<31)|(0x1<<29) |(0x1<<25) |( 4<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_SPI0_EN_Pos) /*!< SPI0 Module */
#define SPI1_MODULE ((0x0<<31)|(0x1<<29) |(0x1<<25) |( 5<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_SPI1_EN_Pos) /*!< SPI1 Module */
#define UART0_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(24<<20) |(0x0<<18) |(0x0F<<10) |( 8<<5) |CLK_APBCLK_UART0_EN_Pos) /*!< UART0 Module */
#define UART1_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(24<<20) |(0x0<<18) |(0x0F<<10) |( 8<<5) |CLK_APBCLK_UART1_EN_Pos) /*!< UART1 Module */
#define PWM01_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(28<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM01_EN_Pos) /*!< PWM01 Module */
#define PWM23_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(30<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM23_EN_Pos) /*!< PWM23 Module */
#define PWM45_MODULE ((0x0<<31)|(0x3<<29) |(0x3<<25) |( 4<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM45_EN_Pos) /*!< PWM45 Module */
#define PWM67_MODULE ((0x0<<31)|(0x3<<29) |(0x3<<25) |( 6<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM67_EN_Pos) /*!< PWM67 Module */
#define ADC_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |( 2<<20) |(0x0<<18) |(0xFF<<10) |(16<<5) |CLK_APBCLK_ADC_EN_Pos) /*!< ADC Module */
#define ACMP01_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_ACMP01_EN_Pos) /*!< ACMP01 Module */
#define ACMP23_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_ACMP23_EN_Pos) /*!< ACMP23 Module */
#define WWDT_MODULE ((MODULE_NoMsk<<31)|(0x3<<29)|(0x3<<25) |(16<<20) |(MODULE_NoMsk<<10) |MODULE_NoMsk ) /*!< WWDT Module */
/*@}*/ /* end of group M051_CLK_EXPORTED_CONSTANTS */
/** @addtogroup M051_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
@{
*/
/**
* @brief This function get PLL frequency. The frequency unit is Hz.
* @return PLL frequency
*/
static __INLINE uint32_t CLK_GetPLLClockFreq(void)
{
uint32_t u32PllFreq = 0, u32PllReg;
uint32_t u32FIN, u32NF, u32NR, u32NO;
uint8_t au8NoTbl[4] = {1, 2, 2, 4};
u32PllReg = CLK->PLLCON;
if(u32PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk))
return 0; /* PLL is in power down mode or fix low */
if(u32PllReg & CLK_PLLCON_PLL_SRC_HIRC)
u32FIN = __HIRC; /* PLL source clock from HIRC */
else
u32FIN = __HXT; /* PLL source clock from HXT */
if(u32PllReg & CLK_PLLCON_BP_Msk)
return u32FIN; /* PLL is in bypass mode */
/* PLL is output enabled in normal work mode */
u32NO = au8NoTbl[((u32PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)];
u32NF = ((u32PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
u32NR = ((u32PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
/* u32FIN is shifted 2 bits to avoid overflow */
u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
return u32PllFreq;
}
/**
* @brief This function execute delay function.
* @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
* 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
* @return None
* @details Use the SysTick to generate the delay time and the UNIT is in us.
* The SysTick clock source is from HCLK, i.e the same as system core clock.
*/
static __INLINE void CLK_SysTickDelay(uint32_t us)
{
SysTick->LOAD = us * CyclesPerUs;
SysTick->VAL = (0x00);
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
}
void CLK_DisableCKO(void);
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
void CLK_PowerDown(void);
void CLK_Idle(void);
uint32_t CLK_GetHXTFreq(void);
uint32_t CLK_GetLXTFreq(void);
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetPCLKFreq(void);
uint32_t CLK_GetCPUFreq(void);
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
void CLK_EnableXtalRC(uint32_t u32ClkMask);
void CLK_DisableXtalRC(uint32_t u32ClkMask);
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
void CLK_DisablePLL(void);
void CLK_WaitClockReady(uint32_t u32ClkMask);
/*@}*/ /* end of group M051_CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_CLK_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#endif //__CLK_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

114
bsp/nuvoton_m05x/Libraries/StdDriver/inc/ebi.h
View File

@@ -1,114 +0,0 @@
/**************************************************************************//**
* @file ebi.h
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series EBI driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_H__
#define __EBI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_EBI_Driver EBI Driver
@{
*/
/** @addtogroup M051_EBI_EXPORTED_CONSTANTS EBI Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BASE_ADDR 0x60000000UL /*!< EBI base address */
#define EBI_MAX_SIZE 0x00020000UL /*!< Maximum EBI size */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI data bus width */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI MCLK divider and Timing */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest */
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast */
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast */
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal */
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow */
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow */
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest */
/*@}*/ /* end of group M051_EBI_EXPORTED_CONSTANTS */
/** @addtogroup M051_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @details This macro read 8-bit data from specify EBI address.
*/
#define EBI_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BASE_ADDR+u32Addr)))
/**
* @details This macro write 8-bit data to specify EBI address.
*/
#define EBI_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BASE_ADDR+u32Addr)) = u32Data)
/**
* @details This macro read 16-bit data from specify EBI address.
*/
#define EBI_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BASE_ADDR+u32Addr)))
/**
* @details This macro write 16-bit data to specify EBI address.
*/
#define EBI_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BASE_ADDR+u32Addr)) = u32Data)
/**
* @details This macro read 32-bit data from specify EBI address.
*/
#define EBI_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BASE_ADDR+u32Addr)))
/**
* @details This macro write 32-bit data to specify EBI address.
*/
#define EBI_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BASE_ADDR+u32Addr)) = u32Data)Write 32-bit data to EBI bank 0
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
void EBI_Close(uint32_t u32Bank);
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
/*@}*/ /* end of group M051_EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_EBI_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__EBI_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

333
bsp/nuvoton_m05x/Libraries/StdDriver/inc/fmc.h
View File

@@ -1,333 +0,0 @@
/**************************************************************************//**
* @file FMC.h
* @version V3.0
* $Revision: 13 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series Flash Memory Controller Driver Header File
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __FMC_H__
#define __FMC_H__
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_FMC_Driver FMC Driver
@{
*/
/** @addtogroup M051_FMC_EXPORTED_CONSTANTS FMC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define Base Address */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 Bytes) */
#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 KBytes) */
/*---------------------------------------------------------------------------------------------------------*/
/* ISPCON constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_ISPCON_BS_LDROM 0x2 /*!< ISPCON setting to select to boot from LDROM */
#define FMC_ISPCON_BS_APROM 0x0 /*!< ISPCON setting to select to boot from APROM */
/*---------------------------------------------------------------------------------------------------------*/
/* ISPCMD constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Program Flash */
#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
#define FMC_ISPCMD_VECMAP 0x2e /*!< ISP Command: Set VECMAP */
#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */
/*@}*/ /* end of group M051_FMC_EXPORTED_CONSTANTS */
/** @addtogroup M051_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* FMC Macro Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_ENABLE_ISP() (FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk) /*!< Enable ISP Function */
#define FMC_DISABLE_ISP() (FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk) /*!< Disable ISP Function */
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk) /*!< Enable LDROM Update Function */
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk) /*!< Disable LDROM Update Function */
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCON |= FMC_ISPCON_APUEN_Msk) /*!< Enable APROM Update Function */
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk) /*!< Disable APROM Update Function */
#define FMC_GET_FAIL_FLAG() ((FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) ? 1 : 0) /*!< Get ISP fail flag */
#define FMC_SET_APROM_BOOT() (FMC->ISPCON &= ~FMC_ISPCON_BS_Msk) /*!< Select booting from APROM */
#define FMC_SET_LDROM_BOOT() (FMC->ISPCON |= FMC_ISPCON_BS_Msk) /*!< Select booting from LDROM */
/*---------------------------------------------------------------------------------------------------------*/
/* inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief Program 32-bit data into specified address of flash
*
* @param[in] u32addr Flash address include APROM, LDROM, Data Flash, and CONFIG
* @param[in] u32data 32-bit Data to program
*
* @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
* The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
*
* @note
* Please make sure that Register Write-Protection Function has been disabled
* before using this function.
*/
static __INLINE void FMC_Write(uint32_t u32addr, uint32_t u32data)
{
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; /* Set ISP Command Code */
FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be word alignment. */
FMC->ISPDAT = u32data; /* Set Data to Program */
FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG); /* Waiting for ISP Done */
}
/**
* @brief Read 32-bit Data from specified address of flash
*
* @param[in] u32addr Flash address include APROM, LDROM, Data Flash, and CONFIG
*
* @return The data of specified address
*
* @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
*
* @note
* Please make sure that Register Write-Protection Function has been disabled
* before using this function.
*/
static __INLINE uint32_t FMC_Read(uint32_t u32addr)
{
FMC->ISPCMD = FMC_ISPCMD_READ; /* Set ISP Command Code */
FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be word alignment. */
FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG); /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Flash page erase
*
* @param[in] u32addr Flash address including APROM, LDROM, Data Flash, and CONFIG
*
* @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
* The page size is 512 bytes.
*
* @retval 0: Success
* @retval -1: Erase failed
*
* @note
* Please make sure that Register Write-Protection Function has been disabled
* before using this function.
*/
static __INLINE int32_t FMC_Erase(uint32_t u32addr)
{
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; /* Set ISP Command Code */
FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be page alignment. */
FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG); /* Waiting for ISP Done */
/* Check ISPFF flag to know whether erase OK or fail. */
if(FMC->ISPCON & FMC_ISPCON_ISPFF_Msk)
{
FMC->ISPCON = FMC_ISPCON_ISPFF_Msk;
return -1;
}
return 0;
}
/**
* @brief Read Unique ID
*
* @param[in] u8index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
*
* @return The 32-bit unique ID data of specified UID index.
*
* @details To read out 96-bit Unique ID.
*
* @note
* Please make sure that Register Write-Protection Function has been disabled
* before using this function.
*/
static __INLINE uint32_t FMC_ReadUID(uint8_t u8index)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
FMC->ISPADR = (u8index << 2); /* Set UID Address. It must be word alignment. */
FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG); /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Read company ID
*
* @retval The company ID (32-bit)
*
* @details The company ID of Nuvoton is fixed to be 0xDA
*/
static __INLINE uint32_t FMC_ReadCID(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
FMC->ISPADR = 0x0; /* Must keep 0x0 when read CID */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Read device ID
*
* @retval The device ID (32-bit)
*
*/
static __INLINE uint32_t FMC_ReadDID(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
FMC->ISPADR = 0; /* Must keep 0x0 when read DID */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Read product ID
*
* @retval The product ID (32-bit)
*
*/
static __INLINE uint32_t FMC_ReadPID(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
FMC->ISPADR = 0x04; /* Must keep 0x4 when read PID */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief To read UCID
*
* @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
*
* @retval The UCID of specified index
*
*/
static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
FMC->ISPADR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Set vector mapping address
*
* @param[in] u32MapAddr The page address to remap to address 0x0. The address must be page alignment.
*
* @details To set VECMAP to remap specified page address to 0x0.
*
* @note
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
*
*/
static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
{
FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
FMC->ISPADR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
__ISB(); /* To make sure ISP/CPU be Synchronized */
while(FMC->ISPTRG); /* Waiting for ISP Done */
}
/**
* @brief Get current vector mapping address.
*
* @return The current vector mapping address.
*
* @details To get VECMAP value which is the page address for remapping to 0x0.
*
* @note
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
*
*/
static __INLINE uint32_t FMC_GetVECMAP(void)
{
return (FMC->ISPSTA & FMC_ISPSTA_VECMAP_Msk);
}
extern void FMC_Open(void);
extern void FMC_Close(void);
extern void FMC_EnableAPUpdate(void);
extern void FMC_DisableAPUpdate(void);
extern void FMC_EnableConfigUpdate(void);
extern void FMC_DisableConfigUpdate(void);
extern void FMC_EnableLDUpdate(void);
extern void FMC_DisableLDUpdate(void);
extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
extern void FMC_SetBootSource(int32_t i32BootSrc);
extern int32_t FMC_GetBootSource(void);
extern uint32_t FMC_ReadDataFlashBaseAddr(void);
/*@}*/ /* end of group M051_FMC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_FMC_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif

376
bsp/nuvoton_m05x/Libraries/StdDriver/inc/gpio.h
View File

@@ -1,376 +0,0 @@
/**************************************************************************//**
* @file GPIO.h
* @version V2.1
* $Revision: 5 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series General Purpose I/O Driver Header File
*
* @note
* Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup M051_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
@{
*/
#define GPIO_PIN_MAX 8 /*!< Specify Maximum Pins of Each GPIO Port */
/*---------------------------------------------------------------------------------------------------------*/
/* PMD Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_PMD_INPUT 0x0UL /*!< Input Mode */
#define GPIO_PMD_OUTPUT 0x1UL /*!< Output Mode */
#define GPIO_PMD_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
#define GPIO_PMD_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
/*---------------------------------------------------------------------------------------------------------*/
/* IMD Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */
#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* DBNCECON Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INT_CLK_ON 0x00000020UL /*!< DBNCECON setting for all IO pins edge detection circuit is always active after reset */
#define GPIO_INT_CLK_OFF 0x00000000UL /*!< DBNCECON setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
#define GPIO_DBCLKSRC_LIRC 0x00000010UL /*!< DBNCECON setting for de-bounce counter clock source is the internal 10 kHz */
#define GPIO_DBCLKSRC_HCLK 0x00000000UL /*!< DBNCECON setting for de-bounce counter clock source is the HCLK */
#define GPIO_DBCLKSEL_1 0x00000000UL /*!< DBNCECON setting for sampling cycle = 1 clocks */
#define GPIO_DBCLKSEL_2 0x00000001UL /*!< DBNCECON setting for sampling cycle = 2 clocks */
#define GPIO_DBCLKSEL_4 0x00000002UL /*!< DBNCECON setting for sampling cycle = 4 clocks */
#define GPIO_DBCLKSEL_8 0x00000003UL /*!< DBNCECON setting for sampling cycle = 8 clocks */
#define GPIO_DBCLKSEL_16 0x00000004UL /*!< DBNCECON setting for sampling cycle = 16 clocks */
#define GPIO_DBCLKSEL_32 0x00000005UL /*!< DBNCECON setting for sampling cycle = 32 clocks */
#define GPIO_DBCLKSEL_64 0x00000006UL /*!< DBNCECON setting for sampling cycle = 64 clocks */
#define GPIO_DBCLKSEL_128 0x00000007UL /*!< DBNCECON setting for sampling cycle = 128 clocks */
#define GPIO_DBCLKSEL_256 0x00000008UL /*!< DBNCECON setting for sampling cycle = 256 clocks */
#define GPIO_DBCLKSEL_512 0x00000009UL /*!< DBNCECON setting for sampling cycle = 512 clocks */
#define GPIO_DBCLKSEL_1024 0x0000000AUL /*!< DBNCECON setting for sampling cycle = 1024 clocks */
#define GPIO_DBCLKSEL_2048 0x0000000BUL /*!< DBNCECON setting for sampling cycle = 2048 clocks */
#define GPIO_DBCLKSEL_4096 0x0000000CUL /*!< DBNCECON setting for sampling cycle = 4096 clocks */
#define GPIO_DBCLKSEL_8192 0x0000000DUL /*!< DBNCECON setting for sampling cycle = 8192 clocks */
#define GPIO_DBCLKSEL_16384 0x0000000EUL /*!< DBNCECON setting for sampling cycle = 16384 clocks */
#define GPIO_DBCLKSEL_32768 0x0000000FUL /*!< DBNCECON setting for sampling cycle = 32768 clocks */
/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
* Example 1:
*
* P00 = 1;
*
* It is used to set P0.0 to high;
*
* Example 2:
*
* if (P00)
* P00 = 0;
*
* If P0.0 pin status is high, then set P0.0 data output to low.
*/
#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x20*(port))) + ((pin)<<2))))
#define P00 GPIO_PIN_ADDR(0, 0) /*!< Specify P00 Pin Data Input/Output */
#define P01 GPIO_PIN_ADDR(0, 1) /*!< Specify P01 Pin Data Input/Output */
#define P02 GPIO_PIN_ADDR(0, 2) /*!< Specify P02 Pin Data Input/Output */
#define P03 GPIO_PIN_ADDR(0, 3) /*!< Specify P03 Pin Data Input/Output */
#define P04 GPIO_PIN_ADDR(0, 4) /*!< Specify P04 Pin Data Input/Output */
#define P05 GPIO_PIN_ADDR(0, 5) /*!< Specify P05 Pin Data Input/Output */
#define P06 GPIO_PIN_ADDR(0, 6) /*!< Specify P06 Pin Data Input/Output */
#define P07 GPIO_PIN_ADDR(0, 7) /*!< Specify P07 Pin Data Input/Output */
#define P10 GPIO_PIN_ADDR(1, 0) /*!< Specify P10 Pin Data Input/Output */
#define P11 GPIO_PIN_ADDR(1, 1) /*!< Specify P11 Pin Data Input/Output */
#define P12 GPIO_PIN_ADDR(1, 2) /*!< Specify P12 Pin Data Input/Output */
#define P13 GPIO_PIN_ADDR(1, 3) /*!< Specify P13 Pin Data Input/Output */
#define P14 GPIO_PIN_ADDR(1, 4) /*!< Specify P14 Pin Data Input/Output */
#define P15 GPIO_PIN_ADDR(1, 5) /*!< Specify P15 Pin Data Input/Output */
#define P16 GPIO_PIN_ADDR(1, 6) /*!< Specify P16 Pin Data Input/Output */
#define P17 GPIO_PIN_ADDR(1, 7) /*!< Specify P17 Pin Data Input/Output */
#define P20 GPIO_PIN_ADDR(2, 0) /*!< Specify P20 Pin Data Input/Output */
#define P21 GPIO_PIN_ADDR(2, 1) /*!< Specify P21 Pin Data Input/Output */
#define P22 GPIO_PIN_ADDR(2, 2) /*!< Specify P22 Pin Data Input/Output */
#define P23 GPIO_PIN_ADDR(2, 3) /*!< Specify P23 Pin Data Input/Output */
#define P24 GPIO_PIN_ADDR(2, 4) /*!< Specify P24 Pin Data Input/Output */
#define P25 GPIO_PIN_ADDR(2, 5) /*!< Specify P25 Pin Data Input/Output */
#define P26 GPIO_PIN_ADDR(2, 6) /*!< Specify P26 Pin Data Input/Output */
#define P27 GPIO_PIN_ADDR(2, 7) /*!< Specify P27 Pin Data Input/Output */
#define P30 GPIO_PIN_ADDR(3, 0) /*!< Specify P30 Pin Data Input/Output */
#define P31 GPIO_PIN_ADDR(3, 1) /*!< Specify P31 Pin Data Input/Output */
#define P32 GPIO_PIN_ADDR(3, 2) /*!< Specify P32 Pin Data Input/Output */
#define P33 GPIO_PIN_ADDR(3, 3) /*!< Specify P33 Pin Data Input/Output */
#define P34 GPIO_PIN_ADDR(3, 4) /*!< Specify P34 Pin Data Input/Output */
#define P35 GPIO_PIN_ADDR(3, 5) /*!< Specify P35 Pin Data Input/Output */
#define P36 GPIO_PIN_ADDR(3, 6) /*!< Specify P36 Pin Data Input/Output */
#define P37 GPIO_PIN_ADDR(3, 7) /*!< Specify P37 Pin Data Input/Output */
#define P40 GPIO_PIN_ADDR(4, 0) /*!< Specify P40 Pin Data Input/Output */
#define P41 GPIO_PIN_ADDR(4, 1) /*!< Specify P41 Pin Data Input/Output */
#define P42 GPIO_PIN_ADDR(4, 2) /*!< Specify P42 Pin Data Input/Output */
#define P43 GPIO_PIN_ADDR(4, 3) /*!< Specify P43 Pin Data Input/Output */
#define P44 GPIO_PIN_ADDR(4, 4) /*!< Specify P44 Pin Data Input/Output */
#define P45 GPIO_PIN_ADDR(4, 5) /*!< Specify P45 Pin Data Input/Output */
#define P46 GPIO_PIN_ADDR(4, 6) /*!< Specify P46 Pin Data Input/Output */
#define P47 GPIO_PIN_ADDR(4, 7) /*!< Specify P47 Pin Data Input/Output */
/*@}*/ /* end of group M051_GPIO_EXPORTED_CONSTANTS */
/** @addtogroup M051_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
@{
*/
/**
* @brief Clear GPIO Pin Interrupt Flag
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @return None
*
* @details Clear the interrupt status of specified GPIO pin.
*/
#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->ISRC = u32PinMask)
/**
* @brief Disable Pin De-bounce Function
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @return None
*
* @details Disable the interrupt de-bounce function of specified GPIO pin.
*/
#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~u32PinMask)
/**
* @brief Enable Pin De-bounce Function
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
* @return None
*
* @details Enable the interrupt de-bounce function of specified GPIO pin.
*/
#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= u32PinMask)
/**
* @brief Disable I/O Digital Input Path
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @return None
*
* @details Disable I/O digital input path of specified GPIO pin.
*/
#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->OFFD |= u32PinMask)
/**
* @brief Enable I/O Digital Input Path
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @return None
*
* @details Enable I/O digital input path of specified GPIO pin.
*/
#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->OFFD &= ~u32PinMask)
/**
* @brief Disable I/O DOUT mask
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @return None
*
* @details Disable I/O DOUT mask of specified GPIO pin.
*/
#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DMASK |= u32PinMask)
/**
* @brief Enable I/O DOUT mask
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @return None
*
* @details Enable I/O DOUT mask of specified GPIO pin.
*/
#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DMASK &= ~u32PinMask)
/**
* @brief Get GPIO Pin Interrupt Flag
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT7.
*
* @retval 0 No interrupt at specified GPIO pin
* @retval 1 The specified GPIO pin generate an interrupt
*
* @details Get the interrupt status of specified GPIO pin.
*/
#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->ISRC & u32PinMask)
/**
* @brief Set De-bounce Sampling Cycle Time
*
* @param[in] clksrc The de-bounce counter clock source. It could be GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_LIRC.
* @param[in] clksel The de-bounce sampling cycle selection. It could be \n
* GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, GPIO_DBCLKSEL_8, \n
* GPIO_DBCLKSEL_16, GPIO_DBCLKSEL_32, GPIO_DBCLKSEL_64, GPIO_DBCLKSEL_128, \n
* GPIO_DBCLKSEL_256, GPIO_DBCLKSEL_512, GPIO_DBCLKSEL_1024, GPIO_DBCLKSEL_2048, \n
* GPIO_DBCLKSEL_4096, GPIO_DBCLKSEL_8192, GPIO_DBCLKSEL_16384, GPIO_DBCLKSEL_32768.
*
* @return None
*
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
* Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBNCECON_DBCLKSRC_IRC10K, GPIO_DBNCECON_DBCLKSEL_4). \n
* It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
* Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
* and system will sampling interrupt input once per 1600 us.
*/
#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBNCECON = (GPIO_DBNCECON_ICLK_ON_Msk | u32ClkSrc | u32ClkSel))
/**
* @brief Get GPIO Port IN Data
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
*
* @retval The specified port data
*
* @details Get the PIN register of specified GPIO port.
*/
#define GPIO_GET_IN_DATA(port) ((port)->PIN)
/**
* @brief Set GPIO Port OUT Data
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Data GPIO port data.
*
* @retval None
*
* @details Set the Data into specified GPIO port.
*/
#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
/**
* @brief Toggle Specified GPIO pin
*
* @param[in] u32Pin Pxy
*
* @retval None
*
* @details Toggle the specified GPIO pint.
*/
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
/**
* @brief Enable External GPIO Interrupt 0
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_EnableEINT0 GPIO_EnableInt
/**
* @brief Disable External GPIO Interrupt 0
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_DisableEINT0 GPIO_DisableInt
/**
* @brief Enable External GPIO Interrupt 1
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_EnableEINT1 GPIO_EnableInt
/**
* @brief Disable External GPIO Interrupt 1
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_DisableEINT1 GPIO_DisableInt
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
/*@}*/ /* end of group M051_GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_GPIO_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__GPIO_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

61
bsp/nuvoton_m05x/Libraries/StdDriver/inc/hdiv.h
View File

@@ -1,61 +0,0 @@
/**************************************************************************//**
* @file DIV.h
* @version V2.1
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series DIV Driver Header File
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __DIVIDER_H__
#define __DIVIDER_H__
/**
* @brief Division function to calculate (x/y)
*
* @param[in] x the dividend of the division
* @param[in] y the divisor of the division
*
* @return The result of (x/y)
*
* @details This is a division function to calculate x/y
*
*/
static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)
{
uint32_t *p32;
p32 = (uint32_t *)HDIV_BASE;
*p32++ = x;
*p32++ = y;
return *p32;
}
/**
* @brief To calculate the remainder of x/y, i.e., the result of x mod y.
*
* @param[in] x the dividend of the division
* @param[in] y the divisor of the division
*
* @return The remainder of (x/y)
*
* @details This function is used to calculate the remainder of x/y.
*/
static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)
{
uint32_t *p32;
p32 = (uint32_t *)HDIV_BASE;
*p32++ = x;
*p32++ = y;
return p32[1];
}
#endif

187
bsp/nuvoton_m05x/Libraries/StdDriver/inc/i2c.h
View File

@@ -1,187 +0,0 @@
/**************************************************************************//**
* @file I2C.h
* @version V3.0
* $Revision: 9 $
* $Date: 14/02/10 3:04p $
* @brief M051 Series I2C Driver Header File
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __I2C_H__
#define __I2C_H__
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_I2C_Driver I2C Driver
@{
*/
/** @addtogroup M051_I2C_EXPORTED_CONSTANTS I2C Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* I2CON constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_I2CON_STA_STO_SI 0x38UL /*!< I2CON setting for I2C control bits. It would set STA, STO and SI bits */
#define I2C_I2CON_STA_STO_SI_AA 0x3CUL /*!< I2CON setting for I2C control bits. It would set STA, STO, SI and AA bits */
#define I2C_I2CON_STA_SI 0x28UL /*!< I2CON setting for I2C control bits. It would set STA and SI bits */
#define I2C_I2CON_STA_SI_AA 0x2CUL /*!< I2CON setting for I2C control bits. It would set STA, SI and AA bits */
#define I2C_I2CON_STO_SI 0x18UL /*!< I2CON setting for I2C control bits. It would set STO and SI bits */
#define I2C_I2CON_STO_SI_AA 0x1CUL /*!< I2CON setting for I2C control bits. It would set STO, SI and AA bits */
#define I2C_I2CON_SI 0x08UL /*!< I2CON setting for I2C control bits. It would set SI bit */
#define I2C_I2CON_SI_AA 0x0CUL /*!< I2CON setting for I2C control bits. It would set SI and AA bits */
#define I2C_I2CON_STA 0x20UL /*!< I2CON setting for I2C control bits. It would set STA bit */
#define I2C_I2CON_STO 0x10UL /*!< I2CON setting for I2C control bits. It would set STO bit */
#define I2C_I2CON_AA 0x04UL /*!< I2CON setting for I2C control bits. It would set AA bit */
/*@}*/ /* end of group M051_I2C_EXPORTED_CONSTANTS */
/** @addtogroup M051_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
@{
*/
/**
* @brief The macro is used to set I2C bus condition at One Time
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details To control I2C bus conditions of START, STOP, SI, ACK.
*/
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->I2CON = ((i2c)->I2CON & ~0x3c) | u8Ctrl)
/**
* @brief The macro is used to set START condition of I2C Bus
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details To set the I2C bus START condition
*/
#define I2C_START(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STA_Msk)
/**
* @brief The macro is used to set STOP condition of I2C Bus
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details To set the I2C bus STOP condition
*/
#define I2C_STOP(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STO_Msk)
/**
* @brief The macro is used to wait I2C bus status get ready
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details When a new status is presented of I2C bus, SI flag will be set.
*/
#define I2C_WAIT_READY(i2c) while(!((i2c)->I2CON & I2C_I2CON_SI_Msk))
/**
* @brief The macro is used to Read I2C Bus Data Register
*
* @param[in] i2c Specify I2C port
* @return A byte of I2C data register
*
* @details I2C controller read data from bus and save it in I2CDAT
*/
#define I2C_GET_DATA(i2c) ((i2c)->I2CDAT)
/**
* @brief The macro is used to write a Data to I2C Data Register
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details I2C controller send a byte data to bus.
*/
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->I2CDAT = u8Data)
/**
* @brief The macro is used to get I2C Bus Status Code
*
* @param[in] i2c Specify I2C port
* @return I2C status code
*
* @details To get ths status code of I2C Bus.
*/
#define I2C_GET_STATUS(i2c) ((i2c)->I2CSTATUS)
/**
* @brief The macro is used to get time-out flag
*
* @param[in] i2c Specify I2C port
* @return Time-out flag status
* @retval 0 Bus time-out is not happened
* @retval 1 Bus time-out is happened
*
* @details To get time-out flag of I2C bus
*/
#define I2C_GET_TIMEOUT_FLAG(i2c) ( (i2c->I2CTOC & I2C_I2CTOC_TIF_Msk) == I2C_I2CTOC_TIF_Msk ? 1:0 )
/**
* @brief The macro is used to get wake-up flag
*
* @param[in] i2c Specify I2C port
* @return Wake-up flag status
* @retval 0 Chip is not woken-up from power-down mode
* @retval 1 Chip is woken-up from power-down mode
*
* @detail To get wake-up status of I2C bus
*/
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->I2CWKUPSTS & I2C_I2CWKUPSTS_WKUPIF_Msk) == I2C_I2CWKUPSTS_WKUPIF_Msk ? 1:0 )
/**
* @brief The macro is used to clear wake-up flag
*
* @param[in] i2c Specify I2C port
* @return None
*
* @detail To clear wake-up flag of I2C bus when wake-up flag is set.
*/
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->I2CWKUPSTS |= I2C_I2CWKUPSTS_WKUPIF_Msk)
void I2C_ClearTimeoutFlag(I2C_T *i2c);
void I2C_Close(I2C_T *i2c);
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
void I2C_DisableInt(I2C_T *i2c);
void I2C_EnableInt(I2C_T *i2c);
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
uint32_t I2C_GetIntFlag(I2C_T *i2c);
uint32_t I2C_GetStatus(I2C_T *i2c);
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
uint8_t I2C_GetData(I2C_T *i2c);
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
uint32_t I2C_SetClockBusFreq(I2C_T *i2c, uint32_t u32BusClock);
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
void I2C_DisableTimeout(I2C_T *i2c);
void I2C_EnableWakeup(I2C_T *i2c);
void I2C_DisableWakeup(I2C_T *i2c);
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
/*@}*/ /* end of group M051_I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_I2C_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__I2C_H__

275
bsp/nuvoton_m05x/Libraries/StdDriver/inc/pwm.h
View File

@@ -1,275 +0,0 @@
/**************************************************************************//**
* @file pwm.h
* @version V1.00
* $Revision: 8 $
* $Date: 14/01/28 10:49a $
* @brief M051 series PWM driver header file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_PWM_Driver PWM Driver
@{
*/
/** @addtogroup M051_PWM_EXPORTED_CONSTANTS PWM Exported Constants
@{
*/
#define PWM_CHANNEL_NUM (4) /*!< PWM channel number */
#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */
#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */
#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */
#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */
#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */
#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */
#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type */
#define PWM_DUTY_TRIGGER_ADC (PWM_TCON_PWM0DTEN_Msk) /*!< PWM trigger ADC while counter matches CMR in edge-aligned or center-aligned mode */
#define PWM_PERIOD_TRIGGER_ADC (PWM_TCON_PWM0TEN_Msk) /*!< PWM trigger ADC while counter matches 0 in edge-aligned mode or matches (CNR+1) or zero in center-aligned mode */
#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMR (0) /*!< PWM duty interrupt triggered if down count match CMR */
#define PWM_DUTY_INT_UP_COUNT_MATCH_CMR (PWM_PIER_INT01DTYPE_Msk) /*!< PWM duty interrupt triggered if up down match CMR */
#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt triggered if counter underflow */
#define PWM_PERIOD_INT_MATCH_CNR (PWM_PIER_INT01TYPE_Msk) /*!< PWM period interrupt triggered if counter match CNR */
#define PWM_CAPTURE_INT_RISING_LATCH (PWM_CCR0_CRL_IE0_Msk) /*!< PWM capture interrupt if channel has rising transition */
#define PWM_CAPTURE_INT_FALLING_LATCH (PWM_CCR0_CFL_IE0_Msk) /*!< PWM capture interrupt if channel has falling transition */
/*---------------------------------------------------------------------------------------------------------*/
/* PWM Group channel number constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_CH0 0x0 /*!< PWM Group A/B channel 0 */
#define PWM_CH1 0x1 /*!< PWM Group A/B channel 1 */
#define PWM_CH2 0x2 /*!< PWM Group A/B channel 2 */
#define PWM_CH3 0x3 /*!< PWM Group A/B channel 3 */
#define PWM_CCR_MASK 0x000F000F /*!< PWM CCR0/CCR2 bit0~3 and bit16~19 mask */
/*@}*/ /* end of group M051_PWM_EXPORTED_CONSTANTS */
/** @addtogroup M051_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
@{
*/
/**
* @brief Enable timer synchronous mode of specified channel(s)
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to enable timer synchronous mode of specified channel(s)
*/
#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) \
do{ \
int i;\
for(i = 0; i < 4; i++) { \
if((u32ChannelMask) & (1 << i)) \
(pwm)->PSCR |= (PWM_PSCR_PSSEN0_Msk << (i * 8)); \
} \
}while(0)
/**
* @brief Disable timer synchronous mode of specified channel(s)
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to disable timer synchronous mode of specified channel(s)
*/
#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
do{ \
int i;\
for(i = 0; i < 4; i++) { \
if((u32ChannelMask) & (1 << i)) \
(pwm)->PSCR &= ~(PWM_PSCR_PSSEN0_Msk << (i * 8)); \
} \
}while(0)
/**
* @brief Enable output inverter of specified channel(s)
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to enable capture input inverter for specified channel(s)
*/
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
do{ \
int i;\
(pwm)->PCR &= ~(PWM_PCR_CH0INV_Msk|PWM_PCR_CH1INV_Msk|PWM_PCR_CH2INV_Msk|PWM_PCR_CH3INV_Msk);\
for(i = 0; i < 4; i++) { \
if((u32ChannelMask) & (1 << i)) \
(pwm)->PCR |= (PWM_PCR_CH0INV_Msk << (PWM_PCR_CH0INV_Pos * (i * 4))); \
} \
}while(0)
/**
* @brief Get captured rising data of specified channel
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
* @return uint32_t Return the timer counter, 0~0xFFFF
* @details This macro is used to get captured rising data for specified channel
*/
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CRLR0)) + (u32ChannelNum) * 8))))
/**
* @brief Get captured falling data of specified channel
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
* @return uint32_t Return the timer counter, 0~0xFFFF
* @details This macro is used to get captured falling data for specified channel
*/
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CFLR0)) + (u32ChannelNum) * 8))))
/**
* @brief Set the prescaler of the selected channel
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
* @return None
* @details This macro is used to set timer pre-scale for specified channel
* @note - If u32Prescaler = 0, corresponding PWM-timer will be stopped
* - If u32Prescaler = x (x not equal to 0), it means Clock input is divided by (x + 1) before it is fed to the corresponding PWM counter.
*/
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
((pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
/**
* @brief Set the divider of the selected channel
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
* @param[in] u32Divider Clock divider of specified channel. Valid values are
* - \ref PWM_CLK_DIV_1
* - \ref PWM_CLK_DIV_2
* - \ref PWM_CLK_DIV_4
* - \ref PWM_CLK_DIV_8
* - \ref PWM_CLK_DIV_16
* @return None
* @details This macro is used to set Timer clock source divider selection for specified channel
*/
#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
((pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
/**
* @brief Set the duty of the selected channel
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set PWM Comparator value for specified channel
* @note This new setting will take effect on next PWM period
*/
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CMR0)) + (u32ChannelNum) * 12))) = u32CMR)
/**
* @brief Set the period of the selected channel
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set timer loaded value(CNR) for specified channel.\n
* Loaded value determines the PWM period.
* @note This new setting will take effect on next PWM period
* @note PWM counter will stop if period length set to 0
*/
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CNR0)) + (u32ChannelNum) * 12))) = u32CNR)
/**
* @brief Set the PWM aligned type
* @param[in] pwm The base address of PWM module
* - PWMA : PWM Group A
* - PWMB : PWM Group B
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32AlignedType PWM aligned type, valid values are:
* - \ref PWM_EDGE_ALIGNED
* - \ref PWM_CENTER_ALIGNED
* @return None
* @details This macro is used to set the PWM aligned type
*/
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
do{ \
int i; \
for(i = 0; i < 4; i++) { \
if((u32ChannelMask) & (1 << i)) \
(pwm)->PCR = ((pwm)->PCR & ~(PWM_PCR_PWM01TYPE_Msk << (i >> 1))) | (u32AlignedType << (PWM_PCR_PWM01TYPE_Pos + (i >> 1))); \
} \
}while(0)
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32UnitTimeNsec,
uint32_t u32CaptureEdge);
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequncy,
uint32_t u32DutyCycle);
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
/*@}*/ /* end of group M051_PWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_PWM_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__PWM_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

267
bsp/nuvoton_m05x/Libraries/StdDriver/inc/spi.h
View File

@@ -1,267 +0,0 @@
/**************************************************************************//**
* @file spi.h
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series SPI driver header file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_H__
#define __SPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_SPI_Driver SPI Driver
@{
*/
/** @addtogroup M051_SPI_EXPORTED_CONSTANTS SPI Exported Constants
@{
*/
#define SPI_MODE_0 (SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
#define SPI_MODE_1 (SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
#define SPI_MODE_2 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
#define SPI_MODE_3 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
#define SPI_SLAVE (SPI_CNTRL_SLAVE_Msk) /*!< Set as slave */
#define SPI_MASTER (0x0) /*!< Set as master */
#define SPI_SS (SPI_SSR_SSR_Msk) /*!< Set SS */
#define SPI_SS_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS active high */
#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
#define SPI_UNIT_INT_MASK (0x01) /*!< Unit transfer interrupt mask */
#define SPI_SSTA_INT_MASK (0x02) /*!< Slave 3-Wire mode start interrupt mask */
#define SPI_FIFO_TX_INT_MASK (0x04) /*!< FIFO TX interrupt mask */
#define SPI_FIFO_RX_INT_MASK (0x08) /*!< FIFO RX interrupt mask */
#define SPI_FIFO_RXOV_INT_MASK (0x10) /*!< FIFO RX overrun interrupt mask */
#define SPI_FIFO_TIMEOUT_INT_MASK (0x20) /*!< FIFO RX timeout interrupt mask */
#define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
#define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
#define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
#define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
#define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
/*@}*/ /* end of group M051_SPI_EXPORTED_CONSTANTS */
/** @addtogroup M051_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
@{
*/
/**
* @brief Abort the current transfer in slave 3-wire mode.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_ABORT_3WIRE_TRANSFER(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk)
/**
* @brief Clear the slave 3-wire mode start interrupt flag.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_SLV_START_INTSTS_Msk)
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->CNTRL |= SPI_CNTRL_IF_Msk))
/**
* @brief Disable slave 3-wire mode.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk)
/**
* @brief Enable slave 3-wire mode.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk)
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] spi is the base address of SPI module.
* @return The count of available data in RX FIFO.
*/
#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos)
/**
* @brief Get the RX FIFO empty flag.
* @param[in] spi is the base address of SPI module.
* @return RX FIFO empty flag
* @retval 0: RX FIFO is not empty
* @retval 1: RX FIFO is empty
*/
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk)>>SPI_STATUS_RX_EMPTY_Pos)
/**
* @brief Get the TX FIFO empty flag.
* @param[in] spi is the base address of SPI module.
* @return Tx FIFO empty flag
* @retval 0: TX FIFO is not empty
* @retval 1: TX FIFO is empty
*/
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk)>>SPI_STATUS_TX_EMPTY_Pos)
/**
* @brief Get the TX FIFO full flag.
* @param[in] spi is the base address of SPI module.
* @return TX FIFO full flag
* @retval 0: TX FIFO is not full
* @retval 1: TX FIFO is full
*/
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_FULL_Msk)>>SPI_STATUS_TX_FULL_Pos)
/**
* @brief Get the datum read from RX0 register.
* @param[in] spi is the base address of SPI module.
* @return Data in RX0 register
*/
#define SPI_READ_RX0(spi) ((spi)->RX0)
/**
* @brief Get the datum read from RX1 register.
* @param[in] spi is the base address of SPI module.
* @return Data in RX1 register
*/
#define SPI_READ_RX1(spi) ((spi)->RX1)
/**
* @brief Write datum to TX0 register.
* @param[in] spi is the base address of SPI module.
* @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
* @return None
*/
#define SPI_WRITE_TX0(spi, u32TxData) ((spi)->TX0 = (u32TxData))
/**
* @brief Write datum to TX1 register.
* @param[in] spi is the base address of SPI module.
* @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
* @return None
*/
#define SPI_WRITE_TX1(spi, u32TxData) ((spi)->TX1 = (u32TxData))
/**
* @brief Disable automatic slave select function and set SPI_SS pin to high state.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_SET_SS_HIGH(spi) ((spi)->SSR = ((spi)->SSR & (~SPI_SSR_AUTOSS_Msk)) | (SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk))
/**
* @brief Disable automatic slave select function and set SPI_SS pin to low state.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_SET_SS_LOW(spi) ((spi)->SSR = ((spi)->SSR & (~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk))) | SPI_SSR_SSR_Msk)
/**
* @brief Enable byte reorder function.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CNTRL = ((spi)->CNTRL & (~SPI_CNTRL_REORDER_Msk)) | (1<<SPI_CNTRL_REORDER_Pos))
/**
* @brief Disable byte reorder function.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CNTRL &= ~SPI_CNTRL_REORDER_Msk)
/**
* @brief Set the length of suspend interval.
* @param[in] spi is the base address of SPI module.
* @param[in] u32SuspCycle decides the length of suspend interval.
* @return None
*/
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | ((u32SuspCycle) << SPI_CNTRL_SP_CYCLE_Pos))
/**
* @brief Set the SPI transfer sequence with LSB first.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_SET_LSB_FIRST(spi) ((spi)->CNTRL |= SPI_CNTRL_LSB_Msk)
/**
* @brief Set the SPI transfer sequence with MSB first.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_SET_MSB_FIRST(spi) ((spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk)
/**
* @brief Set the data width of a SPI transaction.
* @param[in] spi is the base address of SPI module.
* @param[in] u32Width is the bit width of transfer data.
* @return None
*/
#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_TX_BIT_LEN_Msk) | (((u32Width)&0x1F) << SPI_CNTRL_TX_BIT_LEN_Pos))
/**
* @brief Get the SPI busy state.
* @param[in] spi is the base address of SPI module.
* @return SPI busy status
* @retval 0: SPI module is not busy
* @retval 1: SPI module is busy
*/
#define SPI_IS_BUSY(spi) ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk)>>SPI_CNTRL_GO_BUSY_Pos )
/**
* @brief Set the GO_BUSY bit to trigger SPI transfer.
* @param[in] spi is the base address of SPI module.
* @return None
*/
#define SPI_TRIGGER(spi) ((spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk)
/* Function prototype declaration */
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI_Close(SPI_T *spi);
void SPI_ClearRxFIFO(SPI_T *spi);
void SPI_ClearTxFIFO(SPI_T *spi);
void SPI_DisableAutoSS(SPI_T *spi);
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
void SPI_DisableFIFO(SPI_T *spi);
uint32_t SPI_GetBusClock(SPI_T *spi);
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
/*@}*/ /* end of group M051_SPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_SPI_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__SPI_H__
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

499
bsp/nuvoton_m05x/Libraries/StdDriver/inc/sys.h
View File

@@ -1,499 +0,0 @@
/**************************************************************************//**
* @file SYS.h
* @version V2.1
* $Revision: 10 $
* $Date: 14/02/05 1:17p $
* @brief M051 Series Global Control and Clock Control Driver Header File
*
* @note
* Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __SYS_H__
#define __SYS_H__
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_SYS_Driver SYS Driver
@{
*/
/** @addtogroup M051_SYS_EXPORTED_CONSTANTS SYS Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Module Reset Control Resister constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CHIP_RST ((0x0<<24) | SYS_IPRSTC1_CPU_RST_Pos ) /*!< CPU reset is one of the SYS_ResetModule parameter */
#define CPU_RST ((0x0<<24) | SYS_IPRSTC1_CHIP_RST_Pos ) /*!< CHIP reset is one of the SYS_ResetModule parameter */
#define EBI_RST ((0x0<<24) | SYS_IPRSTC1_EBI_RST_Pos ) /*!< EBI reset is one of the SYS_ResetModule parameter */
#define HDIV_RST ((0x0<<24) | SYS_IPRSTC1_HDIV_RST_Pos ) /*!< HDIV reset is one of the SYS_ResetModule parameter */
#define GPIO_RST ((0x4<<24) | SYS_IPRSTC2_GPIO_RST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */
#define TMR0_RST ((0x4<<24) | SYS_IPRSTC2_TMR0_RST_Pos ) /*!< TMR0 reset is one of the SYS_ResetModule parameter */
#define TMR1_RST ((0x4<<24) | SYS_IPRSTC2_TMR1_RST_Pos ) /*!< TMR1 reset is one of the SYS_ResetModule parameter */
#define TMR2_RST ((0x4<<24) | SYS_IPRSTC2_TMR2_RST_Pos ) /*!< TMR2 reset is one of the SYS_ResetModule parameter */
#define TMR3_RST ((0x4<<24) | SYS_IPRSTC2_TMR3_RST_Pos ) /*!< TMR3 reset is one of the SYS_ResetModule parameter */
#define I2C0_RST ((0x4<<24) | SYS_IPRSTC2_I2C0_RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
#define I2C1_RST ((0x4<<24) | SYS_IPRSTC2_I2C1_RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
#define SPI0_RST ((0x4<<24) | SYS_IPRSTC2_SPI0_RST_Pos ) /*!< SPI0 reset is one of the SYS_ResetModule parameter */
#define SPI1_RST ((0x4<<24) | SYS_IPRSTC2_SPI1_RST_Pos ) /*!< SPI1 reset is one of the SYS_ResetModule parameter */
#define UART0_RST ((0x4<<24) | SYS_IPRSTC2_UART0_RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */
#define UART1_RST ((0x4<<24) | SYS_IPRSTC2_UART1_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */
#define PWM03_RST ((0x4<<24) | SYS_IPRSTC2_PWM03_RST_Pos ) /*!< PWM03 reset is one of the SYS_ResetModule parameter */
#define PWM47_RST ((0x4<<24) | SYS_IPRSTC2_PWM47_RST_Pos ) /*!< PWM47 reset is one of the SYS_ResetModule parameter */
#define ACMP01_RST ((0x4<<24) | SYS_IPRSTC2_ACMP01_RST_Pos ) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */
#define ACMP23_RST ((0x4<<24) | SYS_IPRSTC2_ACMP23_RST_Pos ) /*!< ACMP23 reset is one of the SYS_ResetModule parameter */
#define ADC_RST ((0x4<<24) | SYS_IPRSTC2_ADC_RST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */
/*---------------------------------------------------------------------------------------------------------*/
/* Brown Out Detector Threshold Voltage Selection constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define SYS_BODCR_BOD_RST_EN (1UL<<SYS_BODCR_BOD_RSTEN_Pos) /*!< Brown-out Reset Enable */
#define SYS_BODCR_BOD_INTERRUPT_EN (0UL<<SYS_BODCR_BOD_RSTEN_Pos) /*!< Brown-out Interrupt Enable */
#define SYS_BODCR_BOD_VL_4_4V (3UL<<SYS_BODCR_BOD_VL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 4.4V */
#define SYS_BODCR_BOD_VL_3_7V (2UL<<SYS_BODCR_BOD_VL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
#define SYS_BODCR_BOD_VL_2_7V (1UL<<SYS_BODCR_BOD_VL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
#define SYS_BODCR_BOD_VL_2_2V (0UL<<SYS_BODCR_BOD_VL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
/*---------------------------------------------------------------------------------------------------------*/
/* Multi-Function constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))
#define SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))
#define SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))
#define SYS_MFP_P00_GPIO 0x00000000UL /*!< P0_MFP pin 0 setting for GPIO */
#define SYS_MFP_P00_AD0 0x00000001UL /*!< P0_MFP pin 0 setting for AD0 */
#define SYS_MFP_P00_CTS1 0x00000100UL /*!< P0_MFP pin 0 setting for CTS1 */
#define SYS_MFP_P00_TXD1 0x00000101UL /*!< P0_MFP pin 0 setting for TXD1 */
#define SYS_MFP_P00_ACMP3_P 0x01000000UL /*!< P0_MFP pin 0 setting for ACMP3_P */
#define SYS_MFP_P00_Msk 0x01000101UL /*!< P0_MFP pin 0 mask */
#define SYS_MFP_P01_GPIO 0x00000000UL /*!< P0_MFP pin 1 setting for GPIO */
#define SYS_MFP_P01_AD1 0x00000002UL /*!< P0_MFP pin 1 setting for AD1 */
#define SYS_MFP_P01_RTS1 0x00000200UL /*!< P0_MFP pin 1 setting for RTS1 */
#define SYS_MFP_P01_RXD1 0x00000202UL /*!< P0_MFP pin 1 setting for RXD1 */
#define SYS_MFP_P01_ACMP3_N 0x02000000UL /*!< P0_MFP pin 1 setting for ACMP3_N */
#define SYS_MFP_P01_Msk 0x02000202UL /*!< P0_MFP pin 1 mask */
#define SYS_MFP_P02_GPIO 0x00000000UL /*!< P0_MFP pin 2 setting for GPIO */
#define SYS_MFP_P02_AD2 0x00000004UL /*!< P0_MFP pin 2 setting for AD2 */
#define SYS_MFP_P02_CTS0 0x00000400UL /*!< P0_MFP pin 2 setting for CTS0 */
#define SYS_MFP_P02_TXD0 0x00000404UL /*!< P0_MFP pin 2 setting for TXD0 */
#define SYS_MFP_P02_Msk 0x00000404UL /*!< P0_MFP pin 2 mask */
#define SYS_MFP_P03_GPIO 0x00000000UL /*!< P0_MFP pin 3 setting for GPIO */
#define SYS_MFP_P03_AD3 0x00000008UL /*!< P0_MFP pin 3 setting for AD3 */
#define SYS_MFP_P03_RTS0 0x00000800UL /*!< P0_MFP pin 3 setting for RTS0 */
#define SYS_MFP_P03_RXD0 0x00000808UL /*!< P0_MFP pin 3 setting for RXD0 */
#define SYS_MFP_P03_Msk 0x00000808UL /*!< P0_MFP pin 3 mask */
#define SYS_MFP_P04_GPIO 0x00000000UL /*!< P0_MFP pin 4 setting for GPIO */
#define SYS_MFP_P04_AD4 0x00000010UL /*!< P0_MFP pin 4 setting for AD4 */
#define SYS_MFP_P04_SPISS1 0x00001000UL /*!< P0_MFP pin 4 setting for SPISS1 */
#define SYS_MFP_P04_Msk 0x00001010UL /*!< P0_MFP pin 4 mask */
#define SYS_MFP_P05_GPIO 0x00000000UL /*!< P0_MFP pin 5 setting for GPIO */
#define SYS_MFP_P05_AD5 0x00000020UL /*!< P0_MFP pin 5 setting for AD5 */
#define SYS_MFP_P05_MOSI_1 0x00002000UL /*!< P0_MFP pin 5 setting for MOSI_1 */
#define SYS_MFP_P05_Msk 0x00002020UL /*!< P0_MFP pin 5 mask */
#define SYS_MFP_P06_GPIO 0x00000000UL /*!< P0_MFP pin 6 setting for GPIO */
#define SYS_MFP_P06_AD6 0x00000040UL /*!< P0_MFP pin 6 setting for AD6 */
#define SYS_MFP_P06_MISO_1 0x00004000UL /*!< P0_MFP pin 6 setting for MISO_1 */
#define SYS_MFP_P06_Msk 0x00004040UL /*!< P0_MFP pin 6 mask */
#define SYS_MFP_P07_GPIO 0x00000000UL /*!< P0_MFP pin 7 setting for GPIO */
#define SYS_MFP_P07_AD7 0x00000080UL /*!< P0_MFP pin 7 setting for AD7 */
#define SYS_MFP_P07_SPICLK1 0x00008000UL /*!< P0_MFP pin 7 setting for SPICLK1 */
#define SYS_MFP_P07_Msk 0x00008080UL /*!< P0_MFP pin 7 mask */
#define SYS_MFP_P10_GPIO 0x00000000UL /*!< P1_MFP pin 0 setting for GPIO */
#define SYS_MFP_P10_AIN0 0x00000001UL /*!< P1_MFP pin 0 setting for AIN0 */
#define SYS_MFP_P10_T2 0x00000100UL /*!< P1_MFP pin 0 setting for T2 */
#define SYS_MFP_P10_nWRL 0x00000101UL /*!< P1_MFP pin 0 setting for nWRL */
#define SYS_MFP_P10_Msk 0x00000101UL /*!< P1_MFP pin 0 mask */
#define SYS_MFP_P11_GPIO 0x00000000UL /*!< P1_MFP pin 1 setting for GPIO */
#define SYS_MFP_P11_AIN1 0x00000002UL /*!< P1_MFP pin 1 setting for AIN1 */
#define SYS_MFP_P11_T3 0x00000200UL /*!< P1_MFP pin 1 setting for T3 */
#define SYS_MFP_P11_nWRH 0x00000202UL /*!< P1_MFP pin 1 setting for nWRH */
#define SYS_MFP_P11_Msk 0x00000202UL /*!< P1_MFP pin 1 mask */
#define SYS_MFP_P12_GPIO 0x00000000UL /*!< P1_MFP pin 2 setting for GPIO */
#define SYS_MFP_P12_AIN2 0x00000004UL /*!< P1_MFP pin 2 setting for AIN2 */
#define SYS_MFP_P12_RXD1 0x00000400UL /*!< P1_MFP pin 2 setting for RXD1 */
#define SYS_MFP_P12_Msk 0x00000404UL /*!< P1_MFP pin 2 mask */
#define SYS_MFP_P13_GPIO 0x00000000UL /*!< P1_MFP pin 3 setting for GPIO */
#define SYS_MFP_P13_AIN3 0x00000008UL /*!< P1_MFP pin 3 setting for AIN3 */
#define SYS_MFP_P13_TXD1 0x00000800UL /*!< P1_MFP pin 3 setting for TXD1 */
#define SYS_MFP_P13_Msk 0x00000808UL /*!< P1_MFP pin 3 mask */
#define SYS_MFP_P14_GPIO 0x00000000UL /*!< P1_MFP pin 4 setting for GPIO */
#define SYS_MFP_P14_AIN4 0x00000010UL /*!< P1_MFP pin 4 setting for AIN4 */
#define SYS_MFP_P14_SPISS0 0x00001000UL /*!< P1_MFP pin 4 setting for SPISS0 */
#define SYS_MFP_P14_CPN0 0x00001010UL /*!< P1_MFP pin 4 setting for CPN0 */
#define SYS_MFP_P14_ACMP0_N 0x00001010UL /*!< P1_MFP pin 4 setting for ACMP0_N */
#define SYS_MFP_P14_Msk 0x00001010UL /*!< P1_MFP pin 4 mask */
#define SYS_MFP_P15_GPIO 0x00000000UL /*!< P1_MFP pin 5 setting for GPIO */
#define SYS_MFP_P15_AIN5 0x00000020UL /*!< P1_MFP pin 5 setting for AIN5 */
#define SYS_MFP_P15_MOSI_0 0x00002000UL /*!< P1_MFP pin 5 setting for MOSI_0 */
#define SYS_MFP_P15_CPP0 0x00002020UL /*!< P1_MFP pin 5 setting for CPP0 */
#define SYS_MFP_P15_ACMP0_P 0x00002020UL /*!< P1_MFP pin 5 setting for ACMP0_P */
#define SYS_MFP_P15_Msk 0x00002020UL /*!< P1_MFP pin 5 mask */
#define SYS_MFP_P16_GPIO 0x00000000UL /*!< P1_MFP pin 6 setting for GPIO */
#define SYS_MFP_P16_AIN6 0x00000040UL /*!< P1_MFP pin 6 setting for AIN6 */
#define SYS_MFP_P16_MISO_0 0x00004000UL /*!< P1_MFP pin 6 setting for MISO_0 */
#define SYS_MFP_P16_ACMP2_N 0x00004040UL /*!< P1_MFP pin 6 setting for ACMP2_N */
#define SYS_MFP_P16_Msk 0x00004040UL /*!< P1_MFP pin 6 mask */
#define SYS_MFP_P17_GPIO 0x00000000UL /*!< P1_MFP pin 7 setting for GPIO */
#define SYS_MFP_P17_AIN7 0x00000080UL /*!< P1_MFP pin 7 setting for AIN7 */
#define SYS_MFP_P17_SPICLK0 0x00008000UL /*!< P1_MFP pin 7 setting for SPICLK0 */
#define SYS_MFP_P17_ACMP2_P 0x00008080UL /*!< P1_MFP pin 7 setting for ACMP2_P */
#define SYS_MFP_P17_Msk 0x00008080UL /*!< P1_MFP pin 7 mask */
#define SYS_MFP_P20_GPIO 0x00000000UL /*!< P2_MFP pin 0 setting for GPIO */
#define SYS_MFP_P20_AD8 0x00000001UL /*!< P2_MFP pin 0 setting for AD8 */
#define SYS_MFP_P20_PWM0 0x00000100UL /*!< P2_MFP pin 0 setting for PWM0 */
#define SYS_MFP_P20_Msk 0x00000101UL /*!< P2_MFP pin 0 mask */
#define SYS_MFP_P21_GPIO 0x00000000UL /*!< P2_MFP pin 1 setting for GPIO */
#define SYS_MFP_P21_AD9 0x00000002UL /*!< P2_MFP pin 1 setting for AD9 */
#define SYS_MFP_P21_PWM1 0x00000200UL /*!< P2_MFP pin 1 setting for PWM1 */
#define SYS_MFP_P21_Msk 0x00000202UL /*!< P2_MFP pin 1 mask */
#define SYS_MFP_P22_GPIO 0x00000000UL /*!< P2_MFP pin 2 setting for GPIO */
#define SYS_MFP_P22_AD10 0x00000004UL /*!< P2_MFP pin 2 setting for AD10 */
#define SYS_MFP_P22_PWM2 0x00000400UL /*!< P2_MFP pin 2 setting for PWM2 */
#define SYS_MFP_P22_Msk 0x00000404UL /*!< P2_MFP pin 2 mask */
#define SYS_MFP_P23_GPIO 0x00000000UL /*!< P2_MFP pin 3 setting for GPIO */
#define SYS_MFP_P23_AD11 0x00000008UL /*!< P2_MFP pin 3 setting for AD11 */
#define SYS_MFP_P23_PWM3 0x00000800UL /*!< P2_MFP pin 3 setting for PWM3 */
#define SYS_MFP_P23_Msk 0x00000808UL /*!< P2_MFP pin 3 mask */
#define SYS_MFP_P24_GPIO 0x00000000UL /*!< P2_MFP pin 4 setting for GPIO */
#define SYS_MFP_P24_AD12 0x00000010UL /*!< P2_MFP pin 4 setting for AD12 */
#define SYS_MFP_P24_PWM4 0x00001000UL /*!< P2_MFP pin 4 setting for PWM4 */
#define SYS_MFP_P24_SCL1 0x00001010UL /*!< P2_MFP pin 4 setting for SCL1 */
#define SYS_MFP_P24_Msk 0x00001010UL /*!< P2_MFP pin 4 mask */
#define SYS_MFP_P25_GPIO 0x00000000UL /*!< P2_MFP pin 5 setting for GPIO */
#define SYS_MFP_P25_AD13 0x00000020UL /*!< P2_MFP pin 5 setting for AD13 */
#define SYS_MFP_P25_PWM5 0x00002000UL /*!< P2_MFP pin 5 setting for PWM5 */
#define SYS_MFP_P25_SDA1 0x00002020UL /*!< P2_MFP pin 5 setting for SDA1 */
#define SYS_MFP_P25_Msk 0x00002020UL /*!< P2_MFP pin 5 mask */
#define SYS_MFP_P26_GPIO 0x00000000UL /*!< P2_MFP pin 6 setting for GPIO */
#define SYS_MFP_P26_AD14 0x00000040UL /*!< P2_MFP pin 6 setting for AD14 */
#define SYS_MFP_P26_PWM6 0x00004000UL /*!< P2_MFP pin 6 setting for PWM6 */
#define SYS_MFP_P26_CPO1 0x00004040UL /*!< P2_MFP pin 6 setting for CPO1 */
#define SYS_MFP_P26_ACMP1_O 0x00004040UL /*!< P2_MFP pin 6 setting for ACMP1_O */
#define SYS_MFP_P26_Msk 0x00004040UL /*!< P2_MFP pin 6 mask */
#define SYS_MFP_P27_GPIO 0x00000000UL /*!< P2_MFP pin 7 setting for GPIO */
#define SYS_MFP_P27_AD15 0x00000080UL /*!< P2_MFP pin 7 setting for AD15 */
#define SYS_MFP_P27_PWM7 0x00008000UL /*!< P2_MFP pin 7 setting for PWM7 */
#define SYS_MFP_P27_Msk 0x00008080UL /*!< P2_MFP pin 7 mask */
#define SYS_MFP_P30_GPIO 0x00000000UL /*!< P3_MFP pin 0 setting for GPIO */
#define SYS_MFP_P30_RXD0 0x00000001UL /*!< P3_MFP pin 0 setting for RXD0 */
#define SYS_MFP_P30_CPN1 0x00000100UL /*!< P3_MFP pin 0 setting for CPN1 */
#define SYS_MFP_P30_ACMP1_N 0x00000100UL /*!< P3_MFP pin 0 setting for ACMP1_N */
#define SYS_MFP_P30_Msk 0x00000101UL /*!< P3_MFP pin 0 mask */
#define SYS_MFP_P31_GPIO 0x00000000UL /*!< P3_MFP pin 1 setting for GPIO */
#define SYS_MFP_P31_TXD0 0x00000002UL /*!< P3_MFP pin 1 setting for TXD0 */
#define SYS_MFP_P31_CPP1 0x00000200UL /*!< P3_MFP pin 1 setting for CPP1 */
#define SYS_MFP_P31_ACMP1_P 0x00000200UL /*!< P3_MFP pin 1 setting for ACMP1_P */
#define SYS_MFP_P31_Msk 0x00000202UL /*!< P3_MFP pin 1 mask */
#define SYS_MFP_P32_GPIO 0x00000000UL /*!< P3_MFP pin 2 setting for GPIO */
#define SYS_MFP_P32_INT0 0x00000004UL /*!< P3_MFP pin 2 setting for /INT0 */
#define SYS_MFP_P32_T0EX 0x00000400UL /*!< P3_MFP pin 2 setting for T0EX */
#define SYS_MFP_P32_Msk 0x00000404UL /*!< P3_MFP pin 2 mask */
#define SYS_MFP_P33_GPIO 0x00000000UL /*!< P3_MFP pin 3 setting for GPIO */
#define SYS_MFP_P33_INT1 0x00000008UL /*!< P3_MFP pin 3 setting for /INT1 */
#define SYS_MFP_P33_MCLK 0x00000800UL /*!< P3_MFP pin 3 setting for MCLK */
#define SYS_MFP_P33_T1EX 0x00000808UL /*!< P3_MFP pin 3 setting for T1EX */
#define SYS_MFP_P33_Msk 0x00000808UL /*!< P3_MFP pin 3 mask */
#define SYS_MFP_P34_GPIO 0x00000000UL /*!< P3_MFP pin 4 setting for GPIO */
#define SYS_MFP_P34_T0 0x00000010UL /*!< P3_MFP pin 4 setting for T0 */
#define SYS_MFP_P34_SDA0 0x00001000UL /*!< P3_MFP pin 4 setting for SDA0 */
#define SYS_MFP_P34_Msk 0x00001010UL /*!< P3_MFP pin 4 mask */
#define SYS_MFP_P35_GPIO 0x00000000UL /*!< P3_MFP pin 5 setting for GPIO */
#define SYS_MFP_P35_T1 0x00000020UL /*!< P3_MFP pin 5 setting for T1 */
#define SYS_MFP_P35_SCL0 0x00002000UL /*!< P3_MFP pin 5 setting for SCL0 */
#define SYS_MFP_P35_CKO 0x00002020UL /*!< P3_MFP pin 5 setting for CKO */
#define SYS_MFP_P35_Msk 0x00002020UL /*!< P3_MFP pin 5 mask */
#define SYS_MFP_P36_GPIO 0x00000000UL /*!< P3_MFP pin 6 setting for GPIO */
#define SYS_MFP_P36_nWR 0x00000040UL /*!< P3_MFP pin 6 setting for nWR */
#define SYS_MFP_P36_CKO 0x00004000UL /*!< P3_MFP pin 6 setting for CKO */
#define SYS_MFP_P36_CPO0 0x00004040UL /*!< P3_MFP pin 6 setting for CPO0 */
#define SYS_MFP_P36_ACMP0_O 0x00004040UL /*!< P3_MFP pin 6 setting for ACMP0_O */
#define SYS_MFP_P36_Msk 0x00004040UL /*!< P3_MFP pin 6 mask */
#define SYS_MFP_P37_GPIO 0x00000000UL /*!< P3_MFP pin 7 setting for GPIO */
#define SYS_MFP_P37_nRD 0x00000080UL /*!< P3_MFP pin 7 setting for nWR */
#define SYS_MFP_P37_Msk 0x00008080UL /*!< P3_MFP pin 7 mask */
#define SYS_MFP_P40_GPIO 0x00000000UL /*!< P4_MFP pin 0 setting for GPIO */
#define SYS_MFP_P40_PWM0 0x00000001UL /*!< P4_MFP pin 0 setting for PWM0 */
#define SYS_MFP_P40_T2EX 0x00000100UL /*!< P4_MFP pin 0 setting for T2EX */
#define SYS_MFP_P40_Msk 0x00000101UL /*!< P4_MFP pin 0 mask */
#define SYS_MFP_P41_GPIO 0x00000000UL /*!< P4_MFP pin 1 setting for GPIO */
#define SYS_MFP_P41_PWM1 0x00000002UL /*!< P4_MFP pin 1 setting for PWM1 */
#define SYS_MFP_P41_T3EX 0x00000200UL /*!< P4_MFP pin 1 setting for T3EX */
#define SYS_MFP_P41_Msk 0x00000202UL /*!< P4_MFP pin 1 mask */
#define SYS_MFP_P42_GPIO 0x00000000UL /*!< P4_MFP pin 2 setting for GPIO */
#define SYS_MFP_P42_PWM2 0x00000004UL /*!< P4_MFP pin 2 setting for PWM2 */
#define SYS_MFP_P42_Msk 0x00000404UL /*!< P4_MFP pin 2 mask */
#define SYS_MFP_P43_GPIO 0x00000000UL /*!< P4_MFP pin 3 setting for GPIO */
#define SYS_MFP_P43_PWM3 0x00000008UL /*!< P4_MFP pin 3 setting for PWM3 */
#define SYS_MFP_P43_Msk 0x00000808UL /*!< P4_MFP pin 3 mask */
#define SYS_MFP_P44_GPIO 0x00000000UL /*!< P4_MFP pin 4 setting for GPIO */
#define SYS_MFP_P44_nCS 0x00000010UL /*!< P4_MFP pin 4 setting for nCS */
#define SYS_MFP_P44_SCL1 0x00001000UL /*!< P4_MFP pin 4 setting for SCL1 */
#define SYS_MFP_P44_Msk 0x00001010UL /*!< P4_MFP pin 4 mask */
#define SYS_MFP_P45_GPIO 0x00000000UL /*!< P4_MFP pin 5 setting for GPIO */
#define SYS_MFP_P45_ALE 0x00000020UL /*!< P4_MFP pin 5 setting for ALE */
#define SYS_MFP_P45_SDA1 0x00002000UL /*!< P4_MFP pin 5 setting for SDA1 */
#define SYS_MFP_P45_Msk 0x00002020UL /*!< P4_MFP pin 5 mask */
#define SYS_MFP_P46_GPIO 0x00000000UL /*!< P4_MFP pin 6 setting for GPIO */
#define SYS_MFP_P46_ICE_CLK 0x00000040UL /*!< P4_MFP pin 6 setting for ICE_CLK */
#define SYS_MFP_P46_Msk 0x00004040UL /*!< P4_MFP pin 6 mask */
#define SYS_MFP_P47_GPIO 0x00000000UL /*!< P4_MFP pin 7 setting for GPIO */
#define SYS_MFP_P47_ICE_DAT 0x00000080UL /*!< P4_MFP pin 7 setting for ICE_DAT */
#define SYS_MFP_P47_Msk 0x00008080UL /*!< P4_MFP pin 7 mask */
/*@}*/ /* end of group M051_SYS_EXPORTED_CONSTANTS */
/** @addtogroup M051_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
@{
*/
/**
* @brief This macro clear Brown-out interrupt flag.
* @return None
*/
#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCR |= SYS_BODCR_BOD_INTF_Msk)
/**
* @brief This macro set Brown-out detect to normal mode.
* @return None
*/
#define SYS_CLEAR_BOD_LPM() (SYS->BODCR &= ~SYS_BODCR_BOD_LPM_Msk)
/**
* @brief This macro disable Brown-out detect function.
* @return None
*/
#define SYS_DISABLE_BOD() (SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk)
/**
* @brief This macro enable Brown-out detect function.
* @return None
*/
#define SYS_ENABLE_BOD() (SYS->BODCR |= SYS_BODCR_BOD_EN_Msk)
/**
* @brief This macro get Brown-out detect interrupt flag.
* @return 0: Brown-out detect interrupt flag is not set.
* 1: Brown-out detect interrupt flag is set.
*/
#define SYS_GET_BOD_INT_FLAG() ((SYS->BODCR & SYS_BODCR_BOD_INTF_Msk)>>SYS_BODCR_BOD_INTF_Pos)
/**
* @brief This macro get Brown-out detector output status.
* @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
* 1: System voltage is lower than BOD_VL setting.
* @details If the BOD_EN is 0, this function always return 0.
*/
#define SYS_GET_BOD_OUTPUT() ((SYS->BODCR & SYS_BODCR_BOD_OUT_Msk)>>SYS_BODCR_BOD_OUT_Msk)
/**
* @brief This macro enable Brown-out detect interrupt function.
* @return None
*/
#define SYS_DISABLE_BOD_RST() (SYS->BODCR &= ~SYS_BODCR_BOD_RSTEN_Msk)
/**
* @brief This macro enable Brown-out detect reset function.
* @return None
*/
#define SYS_ENABLE_BOD_RST() (SYS->BODCR |= SYS_BODCR_BOD_RSTEN_Msk)
/**
* @brief This macro set Brown-out detect to low power mode.
* @return None
*/
#define SYS_SET_BOD_LPM() (SYS->BODCR |= SYS_BODCR_BOD_LPM_Msk)
/**
* @brief This macro set Brown-out detect voltage level.
* @param u32Level is Brown-out voltage level. Including :
* - \ref SYS_BODCR_BOD_VL_4_4V
* - \ref SYS_BODCR_BOD_VL_3_7V
* - \ref SYS_BODCR_BOD_VL_2_7V
* - \ref SYS_BODCR_BOD_VL_2_2V
* @return None
*/
#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | u32Level)
/**
* @brief This macro get previous reset source is from Brown-out detect reset.
* @return 0: Previous reset source is not from Brown-out detect reset
* 1: Previous reset source is from Brown-out detect reset
*/
#define SYS_IS_BOD_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_BOD_Msk)
/**
* @brief This macro get previous reset source is from Low-Voltage-Reset.
* @return 0: Previous reset source is not from CPU reset
* 1: Previous reset source is from CPU reset
*/
#define SYS_IS_CPU_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_CPU_Msk)
/**
* @brief This macro get previous reset source is from Power-on Reset.
* @return 0: Previous reset source is not from Low-Voltage-Reset
* 1: Previous reset source is from Low-Voltage-Reset
*/
#define SYS_IS_POR_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_POR_Msk)
/**
* @brief This macro get previous reset source is from reset pin reset.
* @return 0: Previous reset source is not from Power-on Reset
* 1: Previous reset source is from Power-on Reset
*/
#define SYS_IS_RSTPIN_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_RESET_Msk)
/**
* @brief This macro get previous reset source is from system reset.
* @return 0: Previous reset source is not from reset pin reset
* 1: Previous reset source is from reset pin reset
*/
#define SYS_IS_SYSTEM_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_MCU_Msk)
/**
* @brief This macro get previous reset source is from window watch dog reset.
* @return 0: Previous reset source is not from reset system reset
* 1: Previous reset source is from reset system reset
*/
#define SYS_IS_WDT_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_WDT_Msk)
/**
* @brief This macro disable Low-Voltage-Reset function.
* @return None
*/
#define SYS_DISABLE_LVR() (SYS->BODCR &= ~SYS_BODCR_LVR_EN_Msk)
/**
* @brief This macro enable Low-Voltage-Reset function.
* @return None
*/
#define SYS_ENABLE_LVR() (SYS->BODCR |= SYS_BODCR_LVR_EN_Msk)
/**
* @brief This macro disable Power-on Reset function.
* @return None
*/
#define SYS_DISABLE_POR() (SYS->PORCR = 0x5AA5)
/**
* @brief This macro enable Power-on Reset function.
* @return None
*/
#define SYS_ENABLE_POR() (SYS->PORCR = 0)
/**
* @brief This macro clear reset source flag.
* @param u32RstSrc is reset source.
* @return None
*/
#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSRC | u32RstSrc )
/**
* @brief This function enable register write-protection function
* @return None
* @details To lock the protected register to forbid write access
*/
static __INLINE void SYS_LockReg(void)
{
SYS->REGWRPROT = 0;
}
/**
* @brief This function disable register write-protection function
* @return None
* @details To unlock the protected register to allow write access
*/
static __INLINE void SYS_UnlockReg(void)
{
while(SYS->REGWRPROT != SYS_REGWRPROT_REGPROTDIS_Msk)
{
SYS->REGWRPROT = 0x59;
SYS->REGWRPROT = 0x16;
SYS->REGWRPROT = 0x88;
}
}
void SYS_ClearResetSrc(uint32_t u32Src);
uint32_t SYS_GetBODStatus(void);
uint32_t SYS_GetResetSrc(void);
uint32_t SYS_IsRegLocked(void);
uint32_t SYS_ReadPDID(void);
void SYS_ResetChip(void);
void SYS_ResetCPU(void);
void SYS_ResetModule(uint32_t u32ModuleIndex);
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
void SYS_DisableBOD(void);
/*@}*/ /* end of group M051_SYS_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_SYS_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__SYS_H__

312
bsp/nuvoton_m05x/Libraries/StdDriver/inc/timer.h
View File

@@ -1,312 +0,0 @@
/**************************************************************************//**
* @file timer.h
* @version V3.00
* $Revision: 6 $
* $Date: 14/01/28 10:49a $
* @brief M051 series Timer driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_TIMER_Driver TIMER Driver
@{
*/
/** @addtogroup M051_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
@{
*/
#define TIMER_ONESHOT_MODE (0UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in one-shot mode */
#define TIMER_PERIODIC_MODE (1UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in periodic mode */
#define TIMER_TOGGLE_MODE (2UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in toggle-output mode */
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in continuous counting mode */
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in continuous counting mode */
#define TIMER_CAPTURE_FROM_TXEX_PIN (0UL << TIMER_TCSR_CAP_SRC_Pos) /*!< Timer capture source is from TxEX pin */
#define TIMER_CAPTURE_FROM_INTERNAL_ACMP (1UL << TIMER_TCSR_CAP_SRC_Pos) /*!< Timer capture source is from internal ACMP output signal */
#define TIMER_TOUT_PIN_FROM_TX_PIN (0UL << TIMER_TCSR_TOUT_SEL_Pos) /*!< Timer toggle-output pin is from Tx pin */
#define TIMER_TOUT_PIN_FROM_TXEX_PIN (1UL << TIMER_TCSR_TOUT_SEL_Pos) /*!< Timer toggle-output pin is from TxEX pin */
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< Timer capture event to get timer counter value */
#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< Timer capture event to reset timer counter */
#define TIMER_CAPTURE_FALLING_EDGE (0UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Falling edge trigger timer capture */
#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Rising edge trigger timer capture */
#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE (2UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Both falling and rising edge trigger timer capture */
#define TIMER_COUNTER_FALLING_EDGE (0UL << TIMER_TEXCON_TX_PHASE_Pos) /*!< Counter increase on falling edge */
#define TIMER_COUNTER_RISING_EDGE (1UL << TIMER_TEXCON_TX_PHASE_Pos) /*!< Counter increase on rising edge */
/*@}*/ /* end of group M051_TIMER_EXPORTED_CONSTANTS */
/** @addtogroup M051_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
@{
*/
/**
* @brief Set Timer Compare Value
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
*
* @return None
*
* @details This macro is used to set new Timer compared value.
*/
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->TCMPR = (u32Value))
/**
* @brief Set Timer Prescale Value
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
*
* @return None
*
* @details This macro is used to set new Timer prescale value.
* @note Clock input is divided by (prescale + 1) before it is fed into timer.
*/
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->TCSR = ((timer)->TCSR & ~TIMER_TCSR_PRESCALE_Msk) | (u32Value))
/**
* @brief Check specify Timer Status
*
* @return Timer counter is activate or inactivate
* @retval 0 Timer 24-bit up counter is inactive
* @retval 1 Timer 24-bit up counter is active
*
* @details This macro is used to check if specify Timer is inactive or active.
*/
#define TIMER_IS_ACTIVE(timer) ((timer)->TCSR & TIMER_TCSR_CACT_Msk ? 1 : 0)
/**
* @brief Select Toggle-output Pin
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32ToutSel Toggle-output pin selection, valid values are:
* - \ref TIMER_TOUT_PIN_FROM_TX_PIN
* - \ref TIMER_TOUT_PIN_FROM_TXEX_PIN
*
* @return None
*
* @details This macro is used to select Timer toggle-output pin.
*/
#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->TCSR = ((timer)->TCSR & ~TIMER_TCSR_TOUT_SEL_Msk) | (u32ToutSel))
/**
* @details This function is used to start Timer counting.
*/
static __INLINE void TIMER_Start(TIMER_T *timer)
{
timer->TCSR |= TIMER_TCSR_CEN_Msk;
}
/**
* @details This function is used to stop Timer counting.
*/
static __INLINE void TIMER_Stop(TIMER_T *timer)
{
timer->TCSR &= ~TIMER_TCSR_CEN_Msk;
}
/**
* @details This function is used to enable the Timer wake-up function.
* @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
*/
static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
{
timer->TCSR |= TIMER_TCSR_WAKE_EN_Msk;
}
/**
* @details This function is used to disable the Timer wake-up function.
*/
static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
{
timer->TCSR &= ~TIMER_TCSR_WAKE_EN_Msk;
}
/**
* @details This function is used to enable the capture pin detection de-bounce function.
*/
static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
{
timer->TEXCON |= TIMER_TEXCON_TEXDB_Msk;
}
/**
* @details This function is used to disable the capture pin detection de-bounce function.
*/
static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
{
timer->TEXCON &= ~TIMER_TEXCON_TEXDB_Msk;
}
/**
* @details This function is used to enable the counter pin detection de-bounce function.
*/
static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
{
timer->TEXCON |= TIMER_TEXCON_TCDB_Msk;
}
/**
* @details This function is used to disable the counter pin detection de-bounce function.
*/
static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
{
timer->TEXCON &= ~TIMER_TEXCON_TCDB_Msk;
}
/**
* @details This function is used to enable the Timer time-out interrupt function.
*/
static __INLINE void TIMER_EnableInt(TIMER_T *timer)
{
timer->TCSR |= TIMER_TCSR_IE_Msk;
}
/**
* @details This function is used to disable the Timer time-out interrupt function.
*/
static __INLINE void TIMER_DisableInt(TIMER_T *timer)
{
timer->TCSR &= ~TIMER_TCSR_IE_Msk;
}
/**
* @details This function is used to enable the Timer capture trigger interrupt function.
*/
static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
{
timer->TEXCON |= TIMER_TEXCON_TEXIEN_Msk;
}
/**
* @details This function is used to disable the Timer capture trigger interrupt function.
*/
static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
{
timer->TEXCON &= ~TIMER_TEXCON_TEXIEN_Msk;
}
/**
* @brief Get Timer Time-out Interrupt Flag
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Timer time-out interrupt occurred or not
* @retval 0 Timer time-out interrupt did not occur
* @retval 1 Timer time-out interrupt occurred
*
* @details This function indicates Timer time-out interrupt occurred or not.
*/
static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
{
return (timer->TISR & TIMER_TISR_TIF_Msk ? 1 : 0);
}
/**
* @details This function clears Timer time-out interrupt flag.
*/
static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
{
timer->TISR = TIMER_TISR_TIF_Msk;
}
/**
* @brief Get Timer Capture Interrupt Flag
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Timer capture interrupt occurred or not
* @retval 0 Timer capture interrupt did not occur
* @retval 1 Timer capture interrupt occurred
*
* @details This function indicates Timer capture interrupt occurred or not.
*/
static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
{
return timer->TEXISR;
}
/**
* @details This function clears Timer capture interrupt flag.
*/
static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
{
timer->TEXISR = TIMER_TEXISR_TEXIF_Msk;
}
/**
* @brief Get Timer Wakeup Flag
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Timer has waked up system or not
* @retval 0 Timer did not wake up system
* @retval 1 Timer Timer wake up system
*
* @details This function indicates Timer has waked up system or not.
*/
static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
{
return (timer->TISR & TIMER_TISR_TWF_Msk ? 1 : 0);
}
/**
* @details This function clears the Timer wake-up system flag.
*/
static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
{
timer->TISR = TIMER_TISR_TWF_Msk;
}
/**
* @details This function reports the current timer capture data value.
*/
static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
{
return timer->TCAP;
}
/**
* @details This function reports the current timer counter value.
*/
static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
{
return timer->TDR;
}
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
void TIMER_Close(TIMER_T *timer);
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
void TIMER_DisableCapture(TIMER_T *timer);
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
void TIMER_DisableEventCounter(TIMER_T *timer);
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
/*@}*/ /* end of group M051_TIMER_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_TIMER_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__TIMER_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

380
bsp/nuvoton_m05x/Libraries/StdDriver/inc/uart.h
View File

@@ -1,380 +0,0 @@
/**************************************************************************//**
* @file UART.h
* @version V1.00
* $Revision: 7 $
* $Date: 14/02/05 10:27a $
* @brief Mini51 series UART driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UART_H__
#define __UART_H__
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_UART_Driver UART Driver
@{
*/
/** @addtogroup M051_UART_EXPORTED_CONSTANTS UART Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* UA_FCR constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FCR_RFITL_1BYTE (0x0 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 1 bit */
#define UART_FCR_RFITL_4BYTES (0x1 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 4 bits */
#define UART_FCR_RFITL_8BYTES (0x2 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 8 bits */
#define UART_FCR_RFITL_14BYTES (0x3 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 14 bits */
#define UART_FCR_RTS_TRI_LEV_1BYTE (0x0 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 1 bit */
#define UART_FCR_RTS_TRI_LEV_4BYTES (0x1 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 4 bits */
#define UART_FCR_RTS_TRI_LEV_8BYTES (0x2 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 8 bits */
#define UART_FCR_RTS_TRI_LEV_14BYTES (0x3 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 14 bits */
/*---------------------------------------------------------------------------------------------------------*/
/* UA_LCR constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_WORD_LEN_5 (0) /*!< UA_LCR setting to set UART word length to 5 bits */
#define UART_WORD_LEN_6 (1) /*!< UA_LCR setting to set UART word length to 6 bits */
#define UART_WORD_LEN_7 (2) /*!< UA_LCR setting to set UART word length to 7 bits */
#define UART_WORD_LEN_8 (3) /*!< UA_LCR setting to set UART word length to 8 bits */
#define UART_PARITY_NONE (0x0 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as no parity */
#define UART_PARITY_ODD (0x1 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as odd parity */
#define UART_PARITY_EVEN (0x3 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as even parity */
#define UART_PARITY_MARK (0x5 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to keep parity bit as '1' */
#define UART_PARITY_SPACE (0x7 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to keep parity bit as '0' */
#define UART_STOP_BIT_1 (0x0 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for one stop bit */
#define UART_STOP_BIT_1_5 (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for 1.5 stop bit when 5-bit word length */
#define UART_STOP_BIT_2 (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for two stop bit when 6, 7, 8-bit word length */
/*---------------------------------------------------------------------------------------------------------*/
/* UART RTS LEVEL TRIGGER constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x1 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is High Level Active */
#define UART_RTS_IS_LOW_LEV_ACTIVE (0x0 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is Low Level Active */
/*---------------------------------------------------------------------------------------------------------*/
/* UA_IRCR constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_IRCR_TX_SELECT (1) /*!< Set IrDA function Tx mode */
#define UART_IRCR_RX_SELECT (0) /*!< Set IrDA function Rx mode */
/*---------------------------------------------------------------------------------------------------------*/
/* UA_FUNC_SEL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FUNC_SEL_UART (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set UART Function (Default) */
#define UART_FUNC_SEL_LIN (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set LIN Function */
#define UART_FUNC_SEL_IrDA (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set IrDA Function */
#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set RS485 Function */
/*@}*/ /* end of group M051_UART_EXPORTED_CONSTANTS */
/** @addtogroup M051_UART_EXPORTED_FUNCTIONS UART Exported Functions
@{
*/
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param None
*
* @return UART baudrate mode0 register setting value
*
*/
#define UART_BAUD_MODE0 (0)
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param None
*
* @return UART baudrate mode2 register setting value
*
*/
#define UART_BAUD_MODE2 (UART_BAUD_DIV_X_EN_Msk | UART_BAUD_DIV_X_ONE_Msk)
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param u32SrcFreq UART clock frequency
* @param u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode0 divider
*
*/
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
/**
* @brief Calculate UART baudrate mode2 divider
*
* @param u32SrcFreq UART clock frequency
* @param u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode2 divider
*/
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
/**
* @brief Write Data to Tx data register
*
* @param uart The base address of UART module.
* @param u8Data Data byte to transmit
*
* @return None
*/
#define UART_WRITE(uart, u8Data) (uart->THR = (u8Data))
/**
* @brief Read Rx data register
*
* @param uart The base address of UART module.
*
* @return The oldest data byte in RX FIFO
*/
#define UART_READ(uart) (uart->RBR)
/**
* @brief Get Tx empty register value.
*
* @param uart The base address of UART module
*
* @return Tx empty register value.
*/
#define UART_GET_TX_EMPTY(uart) (uart->FSR & UART_FSR_TX_EMPTY_Msk)
/**
* @brief Get Rx empty register value.
*
* @param uart The base address of UART module
*
* @return Rx empty register value.
*/
#define UART_GET_RX_EMPTY(uart) (uart->FSR & UART_FSR_RX_EMPTY_Msk)
/**
* @brief Check specified uart port transmission is over.
*
* @param uart The base address of UART module
*
* @return TE_Flag.
*/
#define UART_IS_TX_EMPTY(uart) ((uart->FSR & UART_FSR_TE_FLAG_Msk) >> UART_FSR_TE_FLAG_Pos)
/**
* @brief Wait specified uart port transmission is over
*
* @param uart The base address of UART module
*
* @return None
*/
#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FSR) & UART_FSR_TE_FLAG_Msk) >> UART_FSR_TE_FLAG_Pos))
/**
* @brief Check RDA_IF is set or not
*
* @param uart The base address of UART module
*
* @return
* 0 : The number of bytes in the RX FIFO is less than the RFITL
* 1 : The number of bytes in the RX FIFO equals or larger than RFITL
*/
#define UART_IS_RX_READY(uart) ((uart->ISR & UART_ISR_RDA_IF_Msk)>>UART_ISR_RDA_IF_Pos)
/**
* @brief Check TX FIFO is full or not
*
* @param uart The base address of UART module
*
* @return
* 1 = TX FIFO is full
* 0 = TX FIFO is not full
*/
#define UART_IS_TX_FULL(uart) ((uart->FSR & UART_FSR_TX_FULL_Msk)>>UART_FSR_TX_FULL_Pos)
/**
* @brief Check RX FIFO is full or not
*
* @param uart The base address of UART module
*
* @return
* 1 = RX FIFO is full
* 0 = RX FIFO is not full
*
*/
#define UART_IS_RX_FULL(uart) ((uart->FSR & UART_FSR_RX_FULL_Msk)>>UART_FSR_RX_FULL_Pos)
/**
* @brief Get Tx full register value
*
* @param uart The base address of UART module
*
* @return Tx full register value
*/
#define UART_GET_TX_FULL(uart) (uart->FSR & UART_FSR_TX_FULL_Msk)
/**
* @brief Get Rx full register value
*
* @param uart The base address of UART module
*
* @return Rx full register value
*/
#define UART_GET_RX_FULL(uart) (uart->FSR & UART_FSR_RX_FULL_Msk)
/**
* @brief Enable specified interrupt
*
* @param uart The base address of UART module
* @param u32eIntSel Interrupt type select
* - UART_IER_LIN_RX_BRK_IEN_Msk : Lin bus Rx break field interrupt
* - UART_IER_WAKE_EN_Msk : Wakeup interrupt
* - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt
* - UART_IER_RTO_IEN_Msk : Rx time-out interrupt
* - UART_IER_MODEM_IEN_Msk : Modem interrupt
* - UART_IER_RLS_IEN_Msk : Rx Line status interrupt
* - UART_IER_THRE_IEN_Msk : Tx empty interrupt
* - UART_IER_RDA_IEN_Msk : Rx ready interrupt
*
* @return None
*/
#define UART_ENABLE_INT(uart, u32eIntSel) (uart->IER |= (u32eIntSel))
/**
* @brief Disable specified interrupt
*
* @param uart The base address of UART module
* @param u32eIntSel Interrupt type select
* - UART_IER_LIN_RX_BRK_IEN_Msk : Lin bus Rx break field interrupt
* - UART_IER_WAKE_EN_Msk : Wakeup interrupt
* - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt
* - UART_IER_RTO_IEN_Msk : Rx time-out interrupt
* - UART_IER_MODEM_IEN_Msk : Modem interrupt
* - UART_IER_RLS_IEN_Msk : Rx Line status interrupt
* - UART_IER_THRE_IEN_Msk : Tx empty interrupt
* - UART_IER_RDA_IEN_Msk : Rx ready interrupt
* @return None
*/
#define UART_DISABLE_INT(uart, u32eIntSel) (uart->IER &= ~ (u32eIntSel))
/**
* @brief Get specified interrupt flag/status
*
* @param uart The base address of UART module
* @param u32eIntTypeFlag Interrupt Type Flag,should be
* - UART_ISR_LIN_RX_BREAK_INT_Msk : Lin bus interrupt
* - UART_ISR_BUF_ERR_INT_Msk : Buffer Error interrupt
* - UART_ISR_TOUT_INT_Msk : Rx time-out interrupt
* - UART_ISR_MODEM_INT_Msk : Modem interrupt
* - UART_ISR_RLS_INT_Msk : Rx Line status interrupt
* - UART_ISR_THRE_INT_Msk : Tx empty interrupt
* - UART_ISR_RDA_INT_Msk : Rx ready interrupt
*
* @return
* 0 = The specified interrupt is not happened.
* 1 = The specified interrupt is happened.
*/
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->ISR & (u32eIntTypeFlag))?1:0)
/**
* @brief Set RTS pin is low
*
* @param uart The base address of UART module
* @return None
*/
__INLINE void UART_CLEAR_RTS(UART_T* uart)
{
uart->MCR |= UART_MCR_LEV_RTS_Msk;
uart->MCR &= ~UART_MCR_RTS_Msk;
}
/**
* @brief Set RTS pin is high
*
* @param uart The base address of UART module
* @return None
*/
__INLINE void UART_SET_RTS(UART_T* uart)
{
uart->MCR |= UART_MCR_LEV_RTS_Msk | UART_MCR_RTS_Msk;
}
/**
* @brief Clear RS-485 Address Byte Detection Flag
*
* @param uart The base address of UART module
* @return None
*/
#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FSR |= UART_FSR_RS485_ADD_DETF_Msk)
/**
* @brief Get RS-485 Address Byte Detection Flag
*
* @param uart The base address of UART module
* @return RS-485 Address Byte Detection Flag
*/
#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->FSR & UART_FSR_RS485_ADD_DETF_Msk) >> UART_FSR_RS485_ADD_DETF_Pos)
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
void UART_Close(UART_T* uart);
void UART_DisableFlowCtrl(UART_T* uart);
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);
void UART_EnableFlowCtrl(UART_T* uart);
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);
void UART_Open(UART_T* uart, uint32_t u32baudrate);
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
/*@}*/ /* end of group M051_UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_UART_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__UART_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

173
bsp/nuvoton_m05x/Libraries/StdDriver/inc/wdt.h
View File

@@ -1,173 +0,0 @@
/**************************************************************************//**
* @file wdt.h
* @version V3.00
* $Revision: 3 $
* $Date: 14/01/28 10:49a $
* @brief M051 series WDT driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_H__
#define __WDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_WDT_Driver WDT Driver
@{
*/
/** @addtogroup M051_WDT_EXPORTED_CONSTANTS WDT Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* WTCR Constants Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_TIMEOUT_2POW4 (0UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
#define WDT_TIMEOUT_2POW6 (1UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
#define WDT_TIMEOUT_2POW8 (2UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
#define WDT_TIMEOUT_2POW10 (3UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
#define WDT_TIMEOUT_2POW12 (4UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
#define WDT_TIMEOUT_2POW14 (5UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
#define WDT_TIMEOUT_2POW16 (6UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
#define WDT_TIMEOUT_2POW18 (7UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
/*---------------------------------------------------------------------------------------------------------*/
/* WTCRALT Constants Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
#define WDT_RESET_DELAY_130CLK (1UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
#define WDT_RESET_DELAY_18CLK (2UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
#define WDT_RESET_DELAY_3CLK (3UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
/*@}*/ /* end of group M051_WDT_EXPORTED_CONSTANTS */
/** @addtogroup M051_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
@{
*/
/**
* @details This macro clear WDT time-out reset system flag.
*/
#define WDT_CLEAR_RESET_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTRF_Msk)
/**
* @details This macro clear WDT time-out interrupt flag.
*/
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTIF_Msk)
/**
* @details This macro clear WDT time-out wake-up system flag.
*/
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk)) | WDT_WTCR_WTWKF_Msk)
/**
* @brief Get WDT Time-out Reset Flag
*
* @return WDT reset system or not
* @retval 0 WDT did not cause system reset
* @retval 1 WDT caused system reset
*
* @details This macro indicate WDT time-out to reset system or not.
*/
#define WDT_GET_RESET_FLAG() (WDT->WTCR & WDT_WTCR_WTRF_Msk ? 1 : 0)
/**
* @brief Get WDT Time-out Interrupt Flag
*
* @return WDT time-out interrupt occurred or not
* @retval 0 WDT time-out interrupt did not occur
* @retval 1 WDT time-out interrupt occurred
*
* @details This macro indicate WDT time-out interrupt occurred or not.
*/
#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->WTCR & WDT_WTCR_WTIF_Msk ? 1 : 0)
/**
* @brief Get WDT Time-out Wake-up Flag
*
* @return WDT time-out waked system up or not
* @retval 0 WDT did not wake up system
* @retval 1 WDT waked up system
*
* @details This macro indicate WDT time-out waked system up or not
*/
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR & WDT_WTCR_WTWKF_Msk ? 1 : 0)
/**
* @details This macro is used to reset 18-bit WDT counter.
* @note If WDT is activated and enabled to reset system, software must reset WDT counter \n
* before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
*/
#define WDT_RESET_COUNTER() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk | WDT_WTCR_WTRF_Msk)) | WDT_WTCR_WTR_Msk)
/**
* @brief Stop WDT Counting
*
* @param None
*
* @return None
*
* @details This function stops WDT counting and disable WDT module.
*/
static __INLINE void WDT_Close(void)
{
WDT->WTCR = 0;
return;
}
/**
* @brief Enable WDT Time-out Interrupt
*
* @param None
*
* @return None
*
* @details This function enable the WDT time-out interrupt.
*/
static __INLINE void WDT_EnableInt(void)
{
WDT->WTCR |= WDT_WTCR_WTIE_Msk;
return;
}
/**
* @brief Disable WDT Time-out Interrupt
*
* @param None
*
* @return None
*
* @details This function disables the WDT time-out interrupt.
*/
static __INLINE void WDT_DisableInt(void)
{
// Do not touch write 1 clear bits
WDT->WTCR &= ~(WDT_WTCR_WTIE_Msk | WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk);
return;
}
void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
/*@}*/ /* end of group M051_WDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_WDT_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__WDT_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

118
bsp/nuvoton_m05x/Libraries/StdDriver/inc/wwdt.h
View File

@@ -1,118 +0,0 @@
/**************************************************************************//**
* @file wwdt.h
* @version V3.00
* $Revision: 6 $
* $Date: 14/01/28 10:49a $
* @brief M051 series WWDT driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_H__
#define __WWDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup M051_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* WWDTCR Constants Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WWDT_PRESCALER_1 (0 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_2 (1 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_4 (2 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_8 (3 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_16 (4 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_32 (5 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_64 (6 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_128 (7 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_192 (8 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_256 (9 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_384 (10 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_512 (11 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_768 (12 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_1024 (13 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_1536 (14 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_2048 (15 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDTRLD register to reload WWDT counter */
/*@}*/ /* end of group M051_WWDT_EXPORTED_CONSTANTS */
/** @addtogroup M051_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
@{
*/
/**
* @details This macro clear WWDT counter time-out reset system flag.
*/
#define WWDT_CLEAR_RESET_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTRF_Msk)
/**
* @details This macro clear WWDT counter compare match interrupt flag.
*/
#define WWDT_CLEAR_INT_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTIF_Msk)
/**
* @brief Get WWDT Reset Flag
*
* @return WWDT counter time-out reset system or not
* @retval 0 WWDT did not cause system reset
* @retval 1 WWDT counter time-out caused system reset
*
* @details This macro is used to indicate WWDT counter time-out reset system flag.
*/
#define WWDT_GET_RESET_FLAG() ((((WWDT->WWDTSR) & WWDT_WWDTSR_WWDTRF_Msk) == WWDT_WWDTSR_WWDTRF_Msk)? 1:0)
/**
* @brief Get WWDT Compared Match Interrupt Flag
*
* @return WWDT compare match interrupt occurred or not
* @retval 0 WWDT counter compare match interrupt did not occur
* @retval 1 WWDT counter compare match interrupt occurred
*
* @details This macro indicate WWDT counter compare match interrupt occurred or not.
*/
#define WWDT_GET_INT_FLAG() ((((WWDT->WWDTSR) & WWDT_WWDTSR_WWDTIF_Msk) == WWDT_WWDTSR_WWDTIF_Msk)? 1:0)
/**
* @details This macro to reflects the current WWDT counter value.
*/
#define WWDT_GET_COUNTER() (WWDT->WWDTCVR)
/**
* @details This macro is used to reload the WWDT counter value to 0x3F.
* @note After WWDT enabled, application must reload WWDT counter while current counter is less than compare value \n
* and larger than 0, otherwise WWDT will cause system reset immediately.
*/
#define WWDT_RELOAD_COUNTER() (WWDT->WWDTRLD = WWDT_RELOAD_WORD)
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
/*@}*/ /* end of group M051_WWDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_WWDT_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__WWDT_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

78
bsp/nuvoton_m05x/Libraries/StdDriver/src/acmp.c
View File

@@ -1,78 +0,0 @@
/**************************************************************************//**
* @file acmp.c
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series Analog Comparator(ACMP) driver source file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup M051_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief Configure the specified ACMP module
*
* @param[in] Acmp The base address of ACMP module
* @param[in] u32ChNum comparator number.
* @param[in] u32NegSrc is comparator negative input selection. Including:
* - \ref ACMP_CR_VNEG_PIN
* - \ref ACMP_CR_VNEG_BANDGAP
*
* @param[in] u32HysteresisEn is the hysteresis function option. Including:
* - \ref ACMP_CR_HYSTERESIS_ENABLE
* - \ref ACMP_CR_HYSTERESIS_DISABLE
* @return None
*/
void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
{
Acmp->CR[u32ChNum % 2] = (Acmp->CR[u32ChNum % 2] & (~(ACMP_CR_NEGSEL_Msk | ACMP_CR_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CR_ACMPEN_Msk);
}
/**
* @brief This function close comparator
*
* @param[in] Acmp The base address of ACMP module
* @param[in] u32ChNum comparator number.
*
* @return None
*/
void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
{
Acmp->CR[u32ChNum % 2] &= (~ACMP_CR_ACMPEN_Msk);
}
/*@}*/ /* end of group M051_ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ACMP_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

170
bsp/nuvoton_m05x/Libraries/StdDriver/src/adc.c
View File

@@ -1,170 +0,0 @@
/**************************************************************************//**
* @file adc.c
* @version V3.00
* $Revision: 5 $
* $Date: 14/02/10 2:47p $
* @brief M051 series ADC driver source file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ADC_Driver ADC Driver
@{
*/
/** @addtogroup M051_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
@{
*/
/**
* @brief This API configures ADC module to be ready for convert the input from selected channel
* @param[in] adc Base address of ADC module
* @param[in] u32InputMode Decides the ADC analog input mode. Valid values are:
* - \ref ADC_ADCR_DIFFEN_SINGLE_END :Single end input mode
* - \ref ADC_ADCR_DIFFEN_DIFFERENTIAL :Differential input type
* @param[in] u32OpMode Decides the ADC operation mode. Valid values are:
* - \ref ADC_ADCR_ADMD_SINGLE :Single mode.
* - \ref ADC_ADCR_ADMD_BURST :Burst mode.
* - \ref ADC_ADCR_ADMD_SINGLE_CYCLE :Single cycle scan mode.
* - \ref ADC_ADCR_ADMD_CONTINUOUS :Continuous scan mode.
* @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7.
* @return None
* @note M051 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
* with smallest number will be convert.
* @note This API does not turn on ADC power nor does trigger ADC conversion
*/
void ADC_Open(ADC_T *adc,
uint32_t u32InputMode,
uint32_t u32OpMode,
uint32_t u32ChMask)
{
ADC->ADCR = (ADC->ADCR & (~(ADC_ADCR_DIFFEN_Msk | ADC_ADCR_ADMD_Msk))) | \
u32InputMode | \
u32OpMode;
ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32ChMask);
return;
}
/**
* @brief Disable ADC module
* @param[in] adc Base address of ADC module
* @return None
*/
void ADC_Close(ADC_T *adc)
{
SYS->IPRSTC2 |= SYS_IPRSTC2_ADC_RST_Msk;
SYS->IPRSTC2 &= ~SYS_IPRSTC2_ADC_RST_Msk;
return;
}
/**
* @brief Configure the hardware trigger condition and enable hardware trigger
* @param[in] adc Base address of ADC module
* @param[in] u32Source Decides the hardware trigger source. Valid values are:
* - \ref ADC_ADCR_TRGS_STADC :A/D conversion is started by external STADC pin.
* - \ref ADC_ADCR_TRGS_PWM :A/D conversion is started by PWM.
* @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
* trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
* time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
* is used to set trigger condition. Valid values are:
* - \ref ADC_ADCR_TRGCOND_LOW_LEVEL :STADC Low level active
* - \ref ADC_ADCR_TRGCOND_HIGH_LEVEL :STADC High level active
* - \ref ADC_ADCR_TRGCOND_FALLING_EDGE :STADC Falling edge active
* - \ref ADC_ADCR_TRGCOND_RISING_EDGE :STADC Rising edge active
* @return None
* @note ADC hardware trigger source does not support PWM trigger (M05xxBN only).
*/
void ADC_EnableHWTrigger(ADC_T *adc,
uint32_t u32Source,
uint32_t u32Param)
{
ADC->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
if(u32Source == ADC_ADCR_TRGS_STADC)
{
ADC->ADCR |= u32Source | u32Param | ADC_ADCR_TRGEN_Msk;
}
else
{
ADC->ADTDCR = (ADC->ADTDCR & ~ADC_ADTDCR_PTDT_Msk) | u32Param;
ADC->ADCR |= u32Source | ADC_ADCR_TRGEN_Msk;
}
return;
}
/**
* @brief Disable hardware trigger ADC function.
* @param[in] adc Base address of ADC module
* @return None
*/
void ADC_DisableHWTrigger(ADC_T *adc)
{
ADC->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
return;
}
/**
* @brief Enable the interrupt(s) selected by u32Mask parameter.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
* corresponds to a interrupt status. This parameter decides which
* interrupts will be enabled.
* - \ref ADC_ADF_INT :ADC convert complete interrupt
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
* @return None
*/
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
{
if(u32Mask & ADC_ADF_INT)
ADC->ADCR |= ADC_ADCR_ADIE_Msk;
if(u32Mask & ADC_CMP0_INT)
ADC->ADCMPR[0] |= ADC_ADCMPR_CMPIE_Msk;
if(u32Mask & ADC_CMP1_INT)
ADC->ADCMPR[1] |= ADC_ADCMPR_CMPIE_Msk;
return;
}
/**
* @brief Disable the interrupt(s) selected by u32Mask parameter.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
* corresponds to a interrupt status. This parameter decides which
* interrupts will be disabled.
* - \ref ADC_ADF_INT :ADC convert complete interrupt
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
* @return None
*/
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
{
if(u32Mask & ADC_ADF_INT)
ADC->ADCR &= ~ADC_ADCR_ADIE_Msk;
if(u32Mask & ADC_CMP0_INT)
ADC->ADCMPR[0] &= ~ADC_ADCMPR_CMPIE_Msk;
if(u32Mask & ADC_CMP1_INT)
ADC->ADCMPR[1] &= ~ADC_ADCMPR_CMPIE_Msk;
return;
}
/*@}*/ /* end of group M051_ADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ADC_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

470
bsp/nuvoton_m05x/Libraries/StdDriver/src/clk.c
View File

@@ -1,470 +0,0 @@
/**************************************************************************//**
* @file clk.c
* @version V3.00
* $Revision: 15 $
* $Date: 14/01/28 10:49a $
* @brief M051 series CLK driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_CLK_Driver CLK Driver
@{
*/
/** @addtogroup M051_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
@{
*/
/**
* @brief This function disable frequency output function.
* @return None
*/
void CLK_DisableCKO(void)
{
/* Disable CKO clock source */
CLK_DisableModuleClock(FDIV_MODULE);
}
/**
* @brief This function enable frequency divider module clock,
* enable frequency divider clock function and configure frequency divider.
* @param u32ClkSrc is frequency divider function clock source. Including :
* - \ref CLK_CLKSEL2_FRQDIV_S_HXT
* - \ref CLK_CLKSEL2_FRQDIV_S_LIRC
* - \ref CLK_CLKSEL2_FRQDIV_S_HCLK
* - \ref CLK_CLKSEL2_FRQDIV_S_HIRC
* @param u32ClkDiv is divider output frequency selection.
* @param u32ClkDivBy1En is frequency divided by one enable.
* @return None
*
* @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
* The formula is:
* CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
* This function is just used to set CKO clock.
* User must enable I/O for CKO clock output pin by themselves.
*/
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
{
/* CKO = clock source / 2^(u32ClkDiv + 1) */
CLK->FRQDIV = CLK_FRQDIV_DIVIDER_EN_Msk | u32ClkDiv | u32ClkDivBy1En << CLK_FRQDIV_DIVIDER1_Pos;
/* Enable CKO clock source */
CLK_EnableModuleClock(FDIV_MODULE);
/* Select CKO clock source */
CLK_SetModuleClock(FDIV_MODULE, u32ClkSrc, 0);
}
/**
* @brief This function let system enter to Power-down mode.
* @return None
*/
void CLK_PowerDown(void)
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
CLK->PWRCON |= (CLK_PWRCON_PWR_DOWN_EN_Msk | CLK_PWRCON_PD_WAIT_CPU_Msk);
__WFI();
}
/**
* @brief This function let system enter to Idle mode.
* @return None
*/
void CLK_Idle(void)
{
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
CLK->PWRCON &= ~CLK_PWRCON_PWR_DOWN_EN_Msk;
__WFI();
}
/**
* @brief This function get external high frequency crystal frequency. The frequency unit is Hz.
* @return External high frequency crystal frequency
*/
uint32_t CLK_GetHXTFreq(void)
{
if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
return __HXT;
else
return 0;
}
/**
* @brief This function get HCLK frequency. The frequency unit is Hz.
* @return HCLK frequency
*/
uint32_t CLK_GetHCLKFreq(void)
{
SystemCoreClockUpdate();
return SystemCoreClock;
}
/**
* @brief This function get CPU frequency. The frequency unit is Hz.
* @return CPU frequency
*/
uint32_t CLK_GetCPUFreq(void)
{
SystemCoreClockUpdate();
return SystemCoreClock;
}
/**
* @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz
* @param u32Hclk is HCLK frequency
* @return HCLK frequency
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
if(u32Hclk > FREQ_50MHZ)
u32Hclk = FREQ_50MHZ;
else if(u32Hclk < FREQ_25MHZ)
u32Hclk = FREQ_25MHZ;
if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);
else
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
return u32Hclk;
}
/**
* @brief This function set HCLK clock source and HCLK clock divider
* @param u32ClkSrc is HCLK clock source. Including :
* - \ref CLK_CLKSEL0_HCLK_S_HXT
* - \ref CLK_CLKSEL0_HCLK_S_PLL
* - \ref CLK_CLKSEL0_HCLK_S_LIRC
* - \ref CLK_CLKSEL0_HCLK_S_HIRC
* @param u32ClkDiv is HCLK clock divider. Including :
* - \ref CLK_CLKDIV_HCLK(x)
* @return None
*/
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_HCLK_N_Msk) | u32ClkDiv;
SystemCoreClockUpdate();
}
/**
* @brief This function set selected module clock source and module clock divider
* @param u32ModuleIdx is module index.
* @param u32ClkSrc is module clock source.
* @param u32ClkDiv is module clock divider.
* @return None
* @details Valid parameter combinations listed in following table:
*
* |Module index |Clock source |Divider |
* | :---------------- | :----------------------------------- | :--------------------- |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_HCLK_DIV2048 | x |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_LIRC | x |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HXT |\ref CLK_CLKDIV_ADC(x) |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_PLL |\ref CLK_CLKDIV_ADC(x) |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HCLK |\ref CLK_CLKDIV_ADC(x) |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HIRC |\ref CLK_CLKDIV_ADC(x) |
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0_S_HCLK | x |
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0_S_PLL | x |
* |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1_S_HCLK | x |
* |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1_S_PLL | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HCLK | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_T0 | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_HCLK | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_T1 | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HXT | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HCLK | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_T2 | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_LIRC | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HIRC | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HXT | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HCLK | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_T3 | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_LIRC | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HIRC | x |
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) |
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) |
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) |
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) |
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) |
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) |
* |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_HXT | x |
* |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_LIRC | x |
* |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_HCLK | x |
* |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_HIRC | x |
* |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_HXT | x |
* |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_LIRC | x |
* |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_HCLK | x |
* |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_HIRC | x |
* |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HXT | x |
* |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_LIRC | x |
* |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HCLK | x |
* |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HIRC | x
* |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_HXT | x |
* |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_LIRC | x |
* |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_HCLK | x |
* |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_HIRC | x |
* |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_HXT | x |
* |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_LIRC | x |
* |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_HCLK | x |
* |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_HIRC | x |
* |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDT_S_HCLK_DIV2048 | x |
* |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDT_S_LIRC | x |
*/
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{
uint32_t u32tmp = 0, u32sel = 0, u32div = 0;
if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
{
u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4);
u32tmp = *(volatile uint32_t *)(u32sel);
u32tmp = u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)) | u32ClkSrc;
*(volatile uint32_t *)(u32sel) = u32tmp;
}
if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
{
u32div = (uint32_t)&CLK->CLKDIV + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
u32tmp = *(volatile uint32_t *)(u32div);
u32tmp = (u32tmp & ~MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)) | u32ClkDiv;
*(volatile uint32_t *)(u32div) = u32tmp;
}
}
/**
* @brief This function set systick clock source
* @param u32ClkSrc is module clock source. Including
* - \ref CLK_CLKSEL0_STCLK_S_HXT
* - \ref CLK_CLKSEL0_STCLK_S_HXT_DIV2
* - \ref CLK_CLKSEL0_STCLK_S_HCLK_DIV2
* - \ref CLK_CLKSEL0_STCLK_S_HIRC_DIV2
* @return None
*/
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
{
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | u32ClkSrc;
}
/**
* @brief This function enable clock source
* @param u32ClkMask is clock source mask. Including :
* - \ref CLK_PWRCON_XTL12M_EN_Msk
* - \ref CLK_PWRCON_OSC22M_EN_Msk
* - \ref CLK_PWRCON_OSC10K_EN_Msk
* @return None
*/
void CLK_EnableXtalRC(uint32_t u32ClkMask)
{
CLK->PWRCON |= u32ClkMask;
}
/**
* @brief This function disable clock source
* @param u32ClkMask is clock source mask. Including :
* - \ref CLK_PWRCON_XTL12M_EN_Msk
* - \ref CLK_PWRCON_OSC22M_EN_Msk
* - \ref CLK_PWRCON_OSC10K_EN_Msk
* @return None
*/
void CLK_DisableXtalRC(uint32_t u32ClkMask)
{
CLK->PWRCON &= ~u32ClkMask;
}
/**
* @brief This function enable module clock
* @param u32ModuleIdx is module index. Including :
* - \ref WDT_MODULE
* - \ref TMR0_MODULE
* - \ref TMR1_MODULE
* - \ref TMR2_MODULE
* - \ref TMR3_MODULE
* - \ref FDIV_MODULE
* - \ref I2C0_MODULE
* - \ref I2C1_MODULE
* - \ref SPI0_MODULE
* - \ref SPI1_MODULE
* - \ref UART0_MODULE
* - \ref UART1_MODULE
* - \ref PWM01_MODULE
* - \ref PWM23_MODULE
* - \ref PWM45_MODULE
* - \ref PWM67_MODULE
* - \ref ADC_MODULE
* - \ref ACMP01_MODULE
* - \ref ACMP23_MODULE
* @return None
*/
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
{
*(volatile uint32_t *)((uint32_t)&CLK->APBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
}
/**
* @brief This function disable module clock
* @param u32ModuleIdx is module index
* - \ref WDT_MODULE
* - \ref TMR0_MODULE
* - \ref TMR1_MODULE
* - \ref TMR2_MODULE
* - \ref TMR3_MODULE
* - \ref FDIV_MODULE
* - \ref I2C0_MODULE
* - \ref I2C1_MODULE
* - \ref SPI0_MODULE
* - \ref SPI1_MODULE
* - \ref UART0_MODULE
* - \ref UART1_MODULE
* - \ref PWM01_MODULE
* - \ref PWM23_MODULE
* - \ref PWM45_MODULE
* - \ref PWM67_MODULE
* - \ref ADC_MODULE
* - \ref ACMP01_MODULE
* - \ref ACMP23_MODULE
* @return None
*/
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
{
*(volatile uint32_t *)((uint32_t)&CLK->APBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
}
/**
* @brief This function set PLL frequency
* @param u32PllClkSrc is PLL clock source. Including :
* - \ref CLK_PLLCON_PLL_SRC_HXT
* - \ref CLK_PLLCON_PLL_SRC_HIRC
* @param u32PllFreq is PLL frequency
* @return PLL frequency
*/
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
{
uint32_t u32PllSrcClk, u32PLLReg, u32NR, u32NF, u32NO;
if(u32PllClkSrc == CLK_PLLCON_PLL_SRC_HXT)
{
/* PLL source clock from HXT */
CLK->PLLCON &= ~CLK_PLLCON_PLL_SRC_Msk;
u32PllSrcClk = __HXT;
}
else
{
/* PLL source clock from HIRC */
CLK->PLLCON |= CLK_PLLCON_PLL_SRC_Msk;
u32PllSrcClk = __HIRC;
}
if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq > FREQ_100MHZ))
{
u32NO = 0;
}
else if((u32PllFreq <= FREQ_100MHZ) && (u32PllFreq > FREQ_50MHZ))
{
u32NO = 1;
u32PllFreq = u32PllFreq << 1;
}
else if((u32PllFreq <= FREQ_50MHZ) && (u32PllFreq >= FREQ_25MHZ))
{
u32NO = 3;
u32PllFreq = u32PllFreq << 2;
}
else
{
if(u32PllClkSrc == CLK_PLLCON_PLL_SRC_HXT)
CLK->PLLCON = 0xC22E;
else
CLK->PLLCON = 0xD66F;
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
return CLK_GetPLLClockFreq();
}
u32NF = u32PllFreq / 1000000;
u32NR = u32PllSrcClk / 1000000;
while(1)
{
if((u32NR & 0x01) || (u32NF & 0x01) || (u32NR == 2) || (u32NF == 2))
{
break;
}
else
{
u32NR >>= 1;
u32NF >>= 1;
}
}
u32PLLReg = (u32NO << 14) | ((u32NR - 2) << 9) | (u32NF - 2);
CLK->PLLCON = (CLK->PLLCON & ~(CLK_PLLCON_FB_DV_Msk | CLK_PLLCON_IN_DV_Msk | CLK_PLLCON_OUT_DV_Msk)) | u32PLLReg;
CLK->PLLCON &= ~(CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk);
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
return ((u32PllSrcClk * u32NF) / (u32NR * (u32NO + 1)));
}
/**
* @brief This function disable PLL
* @param None
* @return None
*/
void CLK_DisablePLL(void)
{
CLK->PLLCON |= CLK_PLLCON_PD_Msk;
}
/**
* @brief This function check selected clock source status
* @param u32ClkMask is selected clock source. Including :
* - \ref CLK_CLKSTATUS_OSC22M_STB_Msk
* - \ref CLK_CLKSTATUS_OSC10K_STB_Msk
* - \ref CLK_CLKSTATUS_XTL12M_STB_Msk
* - \ref CLK_CLKSTATUS_PLL_STB_Msk
*
* @return None
*/
void CLK_WaitClockReady(uint32_t u32ClkMask)
{
int32_t i32TimeOutCnt;
i32TimeOutCnt = __HSI / 200; /* About 5ms */
while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask)
{
if(i32TimeOutCnt-- <= 0)
break;
}
}
/*@}*/ /* end of group M051_CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_CLK_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

156
bsp/nuvoton_m05x/Libraries/StdDriver/src/ebi.c
View File

@@ -1,156 +0,0 @@
/**************************************************************************//**
* @file ebi.c
* @version V3.00
* $Revision: 3 $
* $Date: 14/01/28 10:49a $
* @brief M051 series EBI driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_EBI_Driver EBI Driver
@{
*/
/** @addtogroup M051_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @brief Initialize EBI function
*
* @param[in] u32Bank Bank number for EBI. This parameter is current not used.
* @param[in] u32DataWidth Data bus width. Valid values are:
* - \ref EBI_BUSWIDTH_8BIT
* - \ref EBI_BUSWIDTH_16BIT
* @param[in] u32TimingClass Default timing configuration. Valid values are:
* - \ref EBI_TIMING_FASTEST
* - \ref EBI_TIMING_VERYFAST
* - \ref EBI_TIMING_FAST
* - \ref EBI_TIMING_NORMAL
* - \ref EBI_TIMING_SLOW
* - \ref EBI_TIMING_VERYSLOW
* - \ref EBI_TIMING_SLOWEST
* @param[in] u32BusMode Enable EBI separate mode. This parameter is current not used.
* @param[in] u32CSActiveLevel CS is active High/Low. This parameter is current not used.
*
* @return none
*
* @details This function make EBI module be ready for read and write operation.
* @note Only u32DataWidth and u32TimingClass is valid in M051 series.
*/
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
{
if(u32DataWidth == EBI_BUSWIDTH_8BIT)
EBI->EBICON &= ~EBI_EBICON_ExtBW16_Msk;
else
EBI->EBICON |= EBI_EBICON_ExtBW16_Msk;
switch(u32TimingClass)
{
case EBI_TIMING_FASTEST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk;
EBI->EXTIME = 0x0;
break;
case EBI_TIMING_VERYFAST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x3 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x03003318;
break;
case EBI_TIMING_FAST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk;
EBI->EXTIME = 0x0;
break;
case EBI_TIMING_NORMAL:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x3 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x03003318;
break;
case EBI_TIMING_SLOW:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x7 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x07007738;
break;
case EBI_TIMING_VERYSLOW:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_4 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x7 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x07007738;
break;
case EBI_TIMING_SLOWEST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_8 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x7 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x07007738;
break;
default:
EBI->EBICON &= ~EBI_EBICON_ExtEN_Msk;
break;
}
}
/**
* @brief Disable EBI function
*
* @param[in] u32Bank Bank number for EBI. This parameter is current not used.
*
* @return none
*
* @details This function close EBI module.
*/
void EBI_Close(uint32_t u32Bank)
{
EBI->EBICON &= ~EBI_EBICON_ExtEN_Msk;
}
/**
* @brief Set EBI bus timings
*
* @param[in] u32Bank Bank number for EBI. This parameter is current not used.
*
* @param[in] u32TimingConfig Configure EBI timing settings, ExttACC, ExttAHD, ExtIW2X and ExtIR2R.
* @param[in] u32MclkDiv Divider for MCLK. Valid values are:
* - \ref EBI_MCLKDIV_1
* - \ref EBI_MCLKDIV_2
* - \ref EBI_MCLKDIV_4
* - \ref EBI_MCLKDIV_8
* - \ref EBI_MCLKDIV_16
* - \ref EBI_MCLKDIV_32
*
* @return none
*
* @details This function make EBI module be ready for read and write operation.
*/
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
{
EBI->EBICON = (EBI->EBICON & ~EBI_EBICON_MCLKDIV_Msk) | (u32MclkDiv << EBI_EBICON_MCLKDIV_Pos);
EBI->EXTIME = u32TimingConfig;
}
/*@}*/ /* end of group M051_EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_EBI_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

227
bsp/nuvoton_m05x/Libraries/StdDriver/src/fmc.c
View File

@@ -1,227 +0,0 @@
/**************************************************************************//**
* @file fmc.c
* @version V3.00
* $Revision: 11 $
* $Date: 14/01/28 10:49a $
* @brief M051 series FMC driver source file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
//* Includes ------------------------------------------------------------------*/
#include <stdio.h>
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_FMC_Driver FMC Driver
@{
*/
/** @addtogroup M051_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
@{
*/
/**
* @brief Set boot source from LDROM or APROM after next software reset.
*
* @param i32BootSrc[in]
* 1: Boot from LDROM
* 0: Boot from APROM
*
* @details This function is used to switch APROM boot or LDROM boot. User need to call
* FMC_SetBootSource to select boot source first, then use CPU reset or
* System Reset Request to reset system.
*
*/
void FMC_SetBootSource(int32_t i32BootSrc)
{
if(i32BootSrc)
FMC->ISPCON |= FMC_ISPCON_BS_Msk; /* Boot from LDROM */
else
FMC->ISPCON &= ~FMC_ISPCON_BS_Msk;/* Boot from APROM */
}
/**
* @brief Disable ISP Functions
*/
void FMC_Close(void)
{
FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk;
}
/**
* @brief Disable APROM update function
*
* @details Disable APROM update function will forbid APROM programming when boot form APROM.
* APROM update is default to be disable.
*
*/
void FMC_DisableAPUpdate(void)
{
FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk;
}
/**
* @brief Disable User Configuration update function
*
* @details Disable User Configuration update function will forbid User Configuration programming.
* User Configuration update is default to be disable.
*/
void FMC_DisableConfigUpdate(void)
{
FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk;
}
/**
* @brief Disable LDROM update function
*
* @details Disable LDROM update function will forbid LDROM programming.
* LDROM update is default to be disable.
*/
void FMC_DisableLDUpdate(void)
{
FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk;
}
/**
* @brief Enable APROM update function
*
* @details Enable APROM to be able to program when boot from APROM.
*
*/
void FMC_EnableAPUpdate(void)
{
FMC->ISPCON |= FMC_ISPCON_APUEN_Msk;
}
/**
* @brief Enable User Configuration update function
*
* @details Enable User Configuration to be able to program.
*
*/
void FMC_EnableConfigUpdate(void)
{
FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk;
}
/**
* @brief Enable LDROM update function
*
* @details Enable LDROM to be able to program.
*
*/
void FMC_EnableLDUpdate(void)
{
FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk;
}
/**
* @brief Get the current boot source
*
* @retval 0: This chip is currently booting from APROM
* @retval 1: This chip is currently booting from LDROM
*
* @note This function only show the boot source.
* User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
*/
int32_t FMC_GetBootSource(void)
{
if(FMC->ISPCON & FMC_ISPCON_BS_Msk)
return 1;
else
return 0;
}
/**
* @brief Enable FMC ISP function
*
* @details ISPEN bit of ISPCON must be set before we can use ISP commands.
*
*/
void FMC_Open(void)
{
FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk;
}
/**
* @brief Get the base address of Data Flash if enabled.
* @retval The base address of Data Flash
*/
uint32_t FMC_ReadDataFlashBaseAddr(void)
{
return FMC->DFBADR;
}
/**
* @brief Read the User Configuration words.
* @param[out] u32Config The word buffer to store the User Configuration data.
* @param[in] u32Count The word count to be read.
* @retval 0: Success
* @retval -1: Failed
*/
int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
{
int32_t i;
for(i = 0; i < u32Count; i++)
u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
return 0;
}
/**
* @brief Write User Configuration
*
* @param u32Config: The word buffer to store the User Configuration data.
* @param u32Count: The word count to program to User Configuration.
*
* @retval 0: Success
* @retval -1: Failed
*
* @details User must enable User Configuration update before writing it.
* User must erase User Configuration before writing it.
* User Configuration is also be page erase. User needs to backup necessary data
* before erase User Configuration.
*/
int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
{
int32_t i;
for(i = 0; i < u32Count; i++)
{
FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
return -1;
}
return 0;
}
/*@}*/ /* end of group M051_FMC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_FMC_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

92
bsp/nuvoton_m05x/Libraries/StdDriver/src/gpio.c
View File

@@ -1,92 +0,0 @@
/**************************************************************************//**
* @file gpio.c
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series GPIO driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup M051_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
@{
*/
/**
* @brief Set GPIO operation mode
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. It could be BIT0 ~ BIT7.
* @param[in] u32Mode Operation mode. GPIO_PMD_INPUT, GPIO_PMD_OUTPUT, GPIO_PMD_OPEN_DRAIN, GPIO_PMD_QUASI
*
* @return None
*
* @details This function is used to set specified GPIO operation mode.
*/
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{
uint32_t i;
for(i = 0; i < GPIO_PIN_MAX; i++)
{
if(u32PinMask & (1 << i))
{
port->PMD = (port->PMD & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
}
}
}
/**
* @brief Enable GPIO interrupt
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
{
port->IMD |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
port->IEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
}
/**
* @brief Disable GPIO interrupt
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
{
port->IMD &= ~(1UL << u32Pin);
port->IEN &= ~((0x00010001UL) << u32Pin);
}
/*@}*/ /* end of group M051_GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_GPIO_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

380
bsp/nuvoton_m05x/Libraries/StdDriver/src/i2c.c
View File

@@ -1,380 +0,0 @@
/**************************************************************************//**
* @file i2c.c
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series I2C driver source file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_I2C_Driver I2C Driver
@{
*/
/** @addtogroup M051_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
@{
*/
/**
* @brief Enable specify I2C controller and set divider
*
* @param[in] i2c Specify I2C port
* @param[in] u32BusClock The target I2C bus clock in Hz
*
* @return Actual I2C bus clock frequency
*
* @details The function enable the specify I2C controller and set proper clock divider
* in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
* I2C bus clock = PCLK / (4*(divider+1).
*
*/
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
{
uint32_t u32Div;
u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
i2c->I2CLK = u32Div;
/* Enable I2C */
i2c->I2CON |= I2C_I2CON_ENS1_Msk;
return (SystemCoreClock / ((u32Div + 1) << 2));
}
/**
* @brief Disable specify I2C controller
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Reset I2C controller and disable specify I2C port.
*
*/
void I2C_Close(I2C_T *i2c)
{
/* Reset I2C controller */
SYS->IPRSTC2 |= SYS_IPRSTC2_I2C_RST_Msk;
SYS->IPRSTC2 &= ~SYS_IPRSTC2_I2C_RST_Msk;
/* Disable I2C */
i2c->I2CON &= ~I2C_I2CON_ENS1_Msk;
}
/**
* @brief Clear time-out flag
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details The function is used for clear I2C bus time-out flag.
*
*/
void I2C_ClearTimeoutFlag(I2C_T *i2c)
{
i2c->I2CTOC |= I2C_I2CTOC_TIF_Msk;
}
/**
* @brief Set control bit of I2C controller
*
* @param[in] i2c Specify I2C port
* @param[in] u8Start Set I2C START condition
* @param[in] u8Stop Set I2C STOP condition
* @param[in] u8Si Clear SI flag
* @param[in] u8Ack Set I2C ACK bit
*
* @return None
*
* @details The function set I2C control bit of I2C bus protocol.
*
*/
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
{
uint32_t u32Reg = 0;
if(u8Start)
u32Reg |= I2C_I2CON_STA;
if(u8Stop)
u32Reg |= I2C_I2CON_STO;
if(u8Si)
u32Reg |= I2C_I2CON_SI;
if(u8Ack)
u32Reg |= I2C_I2CON_AA;
i2c->I2CON = (i2c->I2CON & ~0x3C) | u32Reg;
}
/**
* @brief Disable Interrupt of I2C Controller
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details The function is used for disable I2C interrupt
*
*/
void I2C_DisableInt(I2C_T *i2c)
{
i2c->I2CON &= ~I2C_I2CON_EI_Msk;
}
/**
* @brief Enable Interrupt of I2C Controller
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details The function is used for enable I2C interrupt
*
*/
void I2C_EnableInt(I2C_T *i2c)
{
i2c->I2CON |= I2C_I2CON_EI_Msk;
}
/**
* @brief Get I2C Bus Clock
*
* @param[in] i2c Specify I2C port
*
* @return The actual I2C Bus clock in Hz
*
* @details To get the actual I2C Bus Clock frequency.
*/
uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
{
uint32_t u32Divider = i2c->I2CLK;
return (SystemCoreClock / ((u32Divider + 1) << 2));
}
/**
* @brief Set I2C Bus Clock
*
* @param[in] i2c Specify I2C port
* @param[in] u32BusClock The target I2C Bus Clock in Hz
*
* @return The actual I2C Bus clock in Hz
*
* @details To set the actual I2C Bus Clock frequency.
*/
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
{
uint32_t u32Div;
u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
i2c->I2CLK = u32Div;
return (SystemCoreClock / ((u32Div + 1) << 2));
}
/**
* @brief Get Interrupt Flag
*
* @param[in] i2c Specify I2C port
*
* @return I2C interrupt flag status
*
* @details To get I2C Bus interrupt flag.
*/
uint32_t I2C_GetIntFlag(I2C_T *i2c)
{
return ((i2c->I2CON & I2C_I2CON_SI_Msk) == I2C_I2CON_SI_Msk ? 1 : 0);
}
/**
* @brief Get I2C bus Status code
*
* @param[in] i2c Specify I2C port
*
* @return I2C status code
*
* @details To get I2C bus status code.
*/
uint32_t I2C_GetStatus(I2C_T *i2c)
{
return (i2c->I2CSTATUS);
}
/**
* @brief Read a Byte from I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @return I2C Data
*
* @details To read a bytes data from specify I2C port.
*/
uint8_t I2C_GetData(I2C_T *i2c)
{
return (i2c->I2CDAT);
}
/**
* @brief Send a byte to I2C bus
*
* @param[in] i2c I2C port
* @param[in] u8Data The data to send to I2C bus
*
* @return None
*
* @details This function is used to write a byte to specified I2C port
*/
void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
{
i2c->I2CDAT = u8Data;
}
/**
* @brief Set 7-bit Slave Address and GC Mode
*
* @param[in] i2c I2C port
* @param[in] u8SlaveNo Set the number of I2C address register (0~3)
* @param[in] u8SlaveAddr 7-bit slave address
* @param[in] u8GCMode Enable GC mode
*
* @return None
*
* @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
* and enable GC mode.
*
*/
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
{
switch(u8SlaveNo)
{
case 1:
i2c->I2CADDR1 = (u8SlaveAddr << 1) | u8GCMode;
break;
case 2:
i2c->I2CADDR2 = (u8SlaveAddr << 1) | u8GCMode;
break;
case 3:
i2c->I2CADDR3 = (u8SlaveAddr << 1) | u8GCMode;
break;
case 0:
default:
i2c->I2CADDR0 = (u8SlaveAddr << 1) | u8GCMode;
break;
}
}
/**
* @brief Configure the mask bits of 7-bit Slave Address
*
* @param[in] i2c I2C port
* @param[in] u8SlaveNo Set the number of I2C address mask register (0~3)
* @param[in] u8SlaveAddrMask A byte for slave address mask
*
* @return None
*
* @details This function is used to set 7-bit slave addresses.
*
*/
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
{
switch(u8SlaveNo)
{
case 1:
i2c->I2CADM1 = u8SlaveAddrMask << 1;
break;
case 2:
i2c->I2CADM2 = u8SlaveAddrMask << 1;
break;
case 3:
i2c->I2CADM3 = u8SlaveAddrMask << 1;
break;
case 0:
default:
i2c->I2CADM0 = u8SlaveAddrMask << 1;
break;
}
}
/**
* @brief Enable Time-out Function and support long time-out
*
* @param[in] i2c I2C port
* @param[in] u8LongTimeout Configure DIV4 to enable long time-out
*
* @return None
*
* @details This function enable time-out function and configure DIV4 to support long
* time-out.
*
*/
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
{
if(u8LongTimeout)
i2c->I2CTOC |= I2C_I2CTOC_DIV4_Msk;
else
i2c->I2CTOC &= ~I2C_I2CTOC_DIV4_Msk;
i2c->I2CTOC |= I2C_I2CTOC_ENTI_Msk;
}
/**
* @brief Disable Time-out Function
*
* @param[in] i2c I2C port
*
* @return None
*
* @details This function disable time-out function.
*
*/
void I2C_DisableTimeout(I2C_T *i2c)
{
i2c->I2CTOC &= ~I2C_I2CTOC_ENTI_Msk;
}
/**
* @brief Enable I2C Wake-up Function
*
* @param[in] i2c I2C port
*
* @return None
*
* @details The function is used to enable wake-up function of I2C controller
*
*/
void I2C_EnableWakeup(I2C_T *i2c)
{
i2c->I2CWKUPCON |= I2C_I2CWKUPCON_WKUPEN_Msk;
}
/**
* @brief Disable I2C Wake-up Function
*
* @param[in] i2c I2C port
*
* @return None
*
* @details The function is used to disable wake-up function of I2C controller
*
*/
void I2C_DisableWakeup(I2C_T *i2c)
{
i2c->I2CWKUPCON &= ~I2C_I2CWKUPCON_WKUPEN_Msk;
}
/*@}*/ /* end of group M051_I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_I2C_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

648
bsp/nuvoton_m05x/Libraries/StdDriver/src/pwm.c
View File

File diff suppressed because it is too large Load Diff

661
bsp/nuvoton_m05x/Libraries/StdDriver/src/spi.c
View File

File diff suppressed because it is too large Load Diff

161
bsp/nuvoton_m05x/Libraries/StdDriver/src/sys.c
View File

@@ -1,161 +0,0 @@
/**************************************************************************//**
* @file sys.c
* @version V3.00
* $Revision: 6 $
* $Date: 14/01/28 6:58p $
* @brief M051 series SYS driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_SYS_Driver SYS Driver
@{
*/
/** @addtogroup M051_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
@{
*/
/**
* @brief This function clear the selected system reset source
* @param u32Src is system reset source
* @return None
*/
void SYS_ClearResetSrc(uint32_t u32Src)
{
SYS->RSTSRC |= u32Src;
}
/**
* @brief This function get Brown-out detector output status
* @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
* 1: System voltage is lower than BOD_VL setting.
* Note : If the BOD_EN is 0, this function always return 0.
*/
uint32_t SYS_GetBODStatus(void)
{
return (SYS->BODCR & SYS_BODCR_BOD_OUT_Msk) ? 1 : 0;
}
/**
* @brief This function get the system reset source register value
* @return Reset source
*/
uint32_t SYS_GetResetSrc(void)
{
return (SYS->RSTSRC);
}
/**
* @brief This function check register write-protection bit setting
* @return 0: Write-protection function is disabled.
* 1: Write-protection function is enabled.
*/
uint32_t SYS_IsRegLocked(void)
{
return !(SYS->REGWRPROT & SYS_REGWRPROT_REGPROTDIS_Msk);
}
/**
* @brief This function get product ID.
* @return Product ID
*/
uint32_t SYS_ReadPDID(void)
{
return SYS->PDID;
}
/**
* @brief This function reset chip.
* @return None
*/
void SYS_ResetChip(void)
{
SYS->IPRSTC1 |= SYS_IPRSTC1_CHIP_RST_Msk;
}
/**
* @brief This function reset CPU.
* @return None
*/
void SYS_ResetCPU(void)
{
SYS->IPRSTC1 |= SYS_IPRSTC1_CPU_RST_Msk;
}
/**
* @brief This function reset selected modules.
* @param u32ModuleIndex is module index. Including :
* - \ref CHIP_RST
* - \ref CPU_RST
* - \ref EBI_RST
* - \ref HDIV_RST
* - \ref GPIO_RST
* - \ref TMR0_RST
* - \ref TMR1_RST
* - \ref TMR2_RST
* - \ref TMR3_RST
* - \ref I2C0_RST
* - \ref I2C1_RST
* - \ref SPI0_RST
* - \ref SPI1_RST
* - \ref UART0_RST
* - \ref UART1_RST
* - \ref PWM03_RST
* - \ref PWM47_RST
* - \ref ACMP01_RST
* - \ref ACMP23_RST
* - \ref ADC_RST
* @return None
*/
void SYS_ResetModule(uint32_t u32ModuleIndex)
{
*(volatile uint32_t *)(&(SYS->IPRSTC1) + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
*(volatile uint32_t *)(&(SYS->IPRSTC1) + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
}
/**
* @brief This function configure BOD function.
* Configure BOD reset or interrupt mode and set Brown-out voltage level.
* Enable Brown-out function
* @param i32Mode is reset or interrupt mode. Including :
* - \ref SYS_BODCR_BOD_RST_EN
* - \ref SYS_BODCR_BOD_INTERRUPT_EN
* @param u32BODLevel is Brown-out voltage level. Including :
* - \ref SYS_BODCR_BOD_VL_4_4V
* - \ref SYS_BODCR_BOD_VL_3_7V
* - \ref SYS_BODCR_BOD_VL_2_7V
* - \ref SYS_BODCR_BOD_VL_2_2V
* @return None
*/
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
{
SYS->BODCR |= SYS_BODCR_BOD_EN_Msk;
SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_RSTEN_Msk) | i32Mode;
SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | u32BODLevel;
}
/**
* @brief This function disable BOD function.
* @return None
*/
void SYS_DisableBOD(void)
{
SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk;
}
/*@}*/ /* end of group M051_SYS_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_SYS_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

292
bsp/nuvoton_m05x/Libraries/StdDriver/src/timer.c
View File

@@ -1,292 +0,0 @@
/**************************************************************************//**
* @file timer.c
* @version V3.00
* $Revision: 6 $
* $Date: 14/01/28 4:19p $
* @brief M051 series Timer driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_TIMER_Driver TIMER Driver
@{
*/
/** @addtogroup M051_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
@{
*/
/**
* @brief Open Timer in specified mode and frequency
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Mode Operation mode. Possible options are
* - \ref TIMER_ONESHOT_MODE
* - \ref TIMER_PERIODIC_MODE
* - \ref TIMER_TOGGLE_MODE
* - \ref TIMER_CONTINUOUS_MODE
* @param[in] u32Freq Target working frequency
*
* @return Real Timer working frequency
*
* @details This API is used to configure timer to operate in specified mode and frequency.
* If timer cannot work in target frequency, a closest frequency will be chose and returned.
* @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
* \ref TIMER_Start macro or program registers directly.
*/
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
{
uint32_t u32Clk = TIMER_GetModuleClock(timer);
uint32_t u32Cmpr = 0, u32Prescale = 0;
// Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0.
if(u32Freq > (u32Clk / 2))
{
u32Cmpr = 2;
}
else
{
if(u32Clk >= 0x4000000)
{
u32Prescale = 7; // real prescaler value is 8
u32Clk >>= 3;
}
else if(u32Clk >= 0x2000000)
{
u32Prescale = 3; // real prescaler value is 4
u32Clk >>= 2;
}
else if(u32Clk >= 0x1000000)
{
u32Prescale = 1; // real prescaler value is 2
u32Clk >>= 1;
}
u32Cmpr = u32Clk / u32Freq;
}
timer->TCSR = u32Mode | u32Prescale;
timer->TCMPR = u32Cmpr;
return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
}
/**
* @brief Stop Timer Counting
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This API stops Timer counting and disable the Timer interrupt function.
*/
void TIMER_Close(TIMER_T *timer)
{
timer->TCSR = 0;
timer->TEXCON = 0;
}
/**
* @brief Open Timer in specified mode and frequency
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
*
* @return None
*
* @details This API is used to create a delay loop for u32usec micro seconds.
* @note This API overwrites the register setting of the timer used to count the delay time.
* @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
*/
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
{
uint32_t u32Clk = TIMER_GetModuleClock(timer);
uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
uint32_t u32Cmpr, u32NsecPerTick;
// Clear current timer configuration/
timer->TCSR = 0;
timer->TEXCON = 0;
if (u32Clk <= 1000000) // min delay is 1000 us if timer clock source is <= 1 MHz
{
if (u32Usec < 1000)
u32Usec = 1000;
if (u32Usec > 1000000)
u32Usec = 1000000;
}
else
{
if (u32Usec < 100)
u32Usec = 100;
if (u32Usec > 1000000)
u32Usec = 1000000;
}
if (u32Clk <= 1000000)
{
u32Prescale = 0;
u32NsecPerTick = 1000000000 / u32Clk;
u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
}
else
{
if (u32Clk > 64000000)
{
u32Prescale = 7; // real prescaler value is 8
u32Clk >>= 3;
}
else if (u32Clk > 32000000)
{
u32Prescale = 3; // real prescaler value is 4
u32Clk >>= 2;
}
else if (u32Clk > 16000000)
{
u32Prescale = 1; // real prescaler value is 2
u32Clk >>= 1;
}
if (u32Usec < 250)
{
u32Cmpr = (u32Usec * u32Clk) / 1000000;
}
else
{
u32NsecPerTick = 1000000000 / u32Clk;
u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
}
}
timer->TCMPR = u32Cmpr;
timer->TCSR = TIMER_TCSR_CEN_Msk | (u32Prescale - 1); // one shot mode
// When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
// And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
for(; delay > 0; delay--)
{
__NOP();
}
while(timer->TCSR & TIMER_TCSR_CACT_Msk);
}
/**
* @brief Enable Timer Capture Function
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32CapMode Timer capture mode. Could be
* - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
* - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
* @param[in] u32Edge Timer capture edge. Possible values are
* - \ref TIMER_CAPTURE_FALLING_EDGE
* - \ref TIMER_CAPTURE_RISING_EDGE
* - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE
*
* @return None
*
* @details This API is used to enable timer capture function with specified mode and capture edge.
* @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
*/
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
{
timer->TEXCON = (timer->TEXCON & ~(TIMER_TEXCON_RSTCAPSEL_Msk |
TIMER_TEXCON_TEX_EDGE_Msk)) |
u32CapMode | u32Edge | TIMER_TEXCON_TEXEN_Msk;
}
/**
* @brief Disable Timer Capture Function
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This API is used to disable the Timer capture function.
*/
void TIMER_DisableCapture(TIMER_T *timer)
{
timer->TEXCON &= ~TIMER_TEXCON_TEXEN_Msk;
}
/**
* @brief Enable Timer Counter Function
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Edge Detection edge of counter pin. Could be ether
* - \ref TIMER_COUNTER_FALLING_EDGE, or
* - \ref TIMER_COUNTER_RISING_EDGE
*
* @return None
*
* @details This function is used to enable the Timer counter function with specify detection edge.
* @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
* @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
*/
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
{
timer->TEXCON = (timer->TEXCON & ~TIMER_TEXCON_TX_PHASE_Msk) | u32Edge;
timer->TCSR |= TIMER_TCSR_CTB_Msk;
}
/**
* @brief Disable Timer Counter Function
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This API is used to disable the Timer event counter function.
*/
void TIMER_DisableEventCounter(TIMER_T *timer)
{
timer->TCSR &= ~TIMER_TCSR_CTB_Msk;
}
/**
* @brief Get Timer Clock Frequency
*
* @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Timer clock frequency
*
* @details This API is used to get the clock frequency of Timer.
* @note This API cannot return correct clock rate if timer source is external clock input.
*/
uint32_t TIMER_GetModuleClock(TIMER_T *timer)
{
uint32_t u32Src;
const uint32_t au32Clk[] = {__HXT, 0, 0, 0, 0, __LIRC, 0, __HIRC};
if(timer == TIMER0)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos;
else if(timer == TIMER1)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos;
else if(timer == TIMER2)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2_S_Msk) >> CLK_CLKSEL1_TMR2_S_Pos;
else // Timer 3
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3_S_Msk) >> CLK_CLKSEL1_TMR3_S_Pos;
if(u32Src == 2)
{
return(SystemCoreClock);
}
return(au32Clk[u32Src]);
}
/*@}*/ /* end of group M051_TIMER_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_TIMER_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

Some files were not shown because too many files have changed in this diff Show More