mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-11-09 20:45:41 +08:00
Merge branch 'master' into BSP_HC32L196
This commit is contained in:
336 files changed
+199494
-63
No files matched your search
@@ -25,6 +25,7 @@ documentation/html
|
||||
tools/kconfig-frontends/kconfig-mconf
|
||||
packages
|
||||
dist
|
||||
dist_ide_project
|
||||
cconfig.h
|
||||
GPUCache
|
||||
|
||||
|
||||
@@ -216,6 +216,17 @@ Path:
|
||||
- bsp/hc32f4a0/Libraries/CMSIS
|
||||
- bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver
|
||||
|
||||
### hc32f460
|
||||
|
||||
License: bsd-new
|
||||
|
||||
Copyright: Copyright (c) 2020, Huada Semiconductor Co., Ltd.
|
||||
|
||||
Path:
|
||||
|
||||
- bsp/hc32f460/Libraries/CMSIS
|
||||
- bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver
|
||||
|
||||
### hc32l196
|
||||
|
||||
License: bsd-new
|
||||
|
||||
@@ -413,7 +413,6 @@ void list_irq(void)
|
||||
}
|
||||
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT(list_irq, list system irq);
|
||||
|
||||
#ifdef FINSH_USING_MSH
|
||||
int cmd_list_irq(int argc, char** argv)
|
||||
@@ -421,8 +420,7 @@ int cmd_list_irq(int argc, char** argv)
|
||||
list_irq();
|
||||
return 0;
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -38,15 +38,14 @@ int cmd_reset(int argc, char** argv)
|
||||
rt_hw_cpu_reset();
|
||||
return 0;
|
||||
}
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system);
|
||||
|
||||
int cmd_shutdown(int argc, char** argv)
|
||||
{
|
||||
rt_hw_cpu_shutdown();
|
||||
return 0;
|
||||
}
|
||||
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -445,7 +445,6 @@ void list_irq(void)
|
||||
}
|
||||
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT(list_irq, list system irq);
|
||||
|
||||
#ifdef FINSH_USING_MSH
|
||||
int cmd_list_irq(int argc, char** argv)
|
||||
@@ -453,8 +452,7 @@ int cmd_list_irq(int argc, char** argv)
|
||||
list_irq();
|
||||
return 0;
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -30,7 +30,6 @@ void machine_shutdown(void)
|
||||
#ifdef RT_USING_FINSH
|
||||
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
|
||||
|
||||
#ifdef FINSH_USING_MSH
|
||||
int cmd_reset(int argc, char** argv)
|
||||
@@ -38,15 +37,14 @@ int cmd_reset(int argc, char** argv)
|
||||
rt_hw_cpu_reset();
|
||||
return 0;
|
||||
}
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system);
|
||||
|
||||
int cmd_shutdown(int argc, char** argv)
|
||||
{
|
||||
rt_hw_cpu_shutdown();
|
||||
return 0;
|
||||
}
|
||||
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -163,5 +163,4 @@ void rt_hw_cpu_reset(void)
|
||||
REG32(PRM_DEVICE(prcm_base)) = 0x1;
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, __cmd_reboot, reboot the cpu);
|
||||
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);
|
||||
@@ -1751,7 +1751,7 @@ int cmd_dump_emac_stats(int argc, char** argv)
|
||||
dump_emac_stats();
|
||||
return 0;
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_dump_emac_stats, __cmd_dump_emac_stats, dump emac statistics.);
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_dump_emac_stats, dump_emac_stats, dump emac statistics);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -286,8 +286,7 @@ int cmd_list_irq(int argc, char** argv)
|
||||
list_irq();
|
||||
return 0;
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -39,7 +39,6 @@ void machine_shutdown()
|
||||
#ifdef RT_USING_FINSH
|
||||
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
|
||||
|
||||
#ifdef FINSH_USING_MSH
|
||||
int cmd_reset(int argc, char** argv)
|
||||
@@ -47,15 +46,14 @@ int cmd_reset(int argc, char** argv)
|
||||
rt_hw_cpu_reset();
|
||||
return 0;
|
||||
}
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system);
|
||||
|
||||
int cmd_shutdown(int argc, char** argv)
|
||||
{
|
||||
rt_hw_cpu_shutdown();
|
||||
return 0;
|
||||
}
|
||||
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
|
||||
MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -22,7 +22,7 @@ static void reboot(uint8_t argc, char **argv)
|
||||
{
|
||||
rt_hw_cpu_reset();
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
|
||||
MSH_CMD_EXPORT(reboot, reboot system);
|
||||
#endif /* RT_USING_FINSH */
|
||||
|
||||
/* SysTick configuration */
|
||||
|
||||
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@@ -0,0 +1,8 @@
|
||||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
file_path:
|
||||
|
||||
dir_path:
|
||||
- Libraries
|
||||
@@ -0,0 +1,25 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "drivers/Kconfig"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
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@@ -0,0 +1,60 @@
|
||||
/*!
|
||||
\file system_gd32f10x.h
|
||||
\brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for
|
||||
GD32F10x Device Series
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32F10X_H
|
||||
#define SYSTEM_GD32F10X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit(void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32F10X_H */
|
||||
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@@ -0,0 +1,81 @@
|
||||
/*!
|
||||
\file gd32f10x_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_CRC_H
|
||||
#define GD32F10X_CRC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register to the value of initializaiton data register */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32F10X_CRC_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,152 @@
|
||||
/*!
|
||||
\file gd32f10x_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_DBG_H
|
||||
#define GD32F10X_DBG_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL */
|
||||
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||
#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
|
||||
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */
|
||||
#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */
|
||||
#ifdef GD32F10x_CL
|
||||
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
|
||||
#endif /* GD32F10x_CL */
|
||||
#ifdef GD32F10X_XD
|
||||
#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */
|
||||
#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */
|
||||
#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */
|
||||
#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */
|
||||
#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */
|
||||
#endif /* GD32F10x_XD */
|
||||
|
||||
/* constants definitions */
|
||||
/* debug hold when core is halted */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
|
||||
DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */
|
||||
#ifdef GD32F10x_CL
|
||||
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
|
||||
#endif /* GD32F10x_CL */
|
||||
#if (defined(GD32F10x_XD) || defined(GD32F10x_CL))
|
||||
DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */
|
||||
DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */
|
||||
DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */
|
||||
DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */
|
||||
DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */
|
||||
DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
|
||||
#endif /* GD32F10x_XD || GD32F10x_CL*/
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* DBG low power mode configurations */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* DBG_CTL0_TRACE_MODE configurations */
|
||||
#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
|
||||
#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
|
||||
|
||||
/* function declarations */
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* low power behavior configuration */
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* peripheral behavior configuration */
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
/* trace pin assignment configuration */
|
||||
/* enable trace pin assignment */
|
||||
void dbg_trace_pin_enable(void);
|
||||
/* disable trace pin assignment */
|
||||
void dbg_trace_pin_disable(void);
|
||||
/* set trace pin mode */
|
||||
void dbg_trace_pin_mode_set(uint32_t trace_mode);
|
||||
|
||||
#endif /* GD32F10x_DBG_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,108 @@
|
||||
/*!
|
||||
\file gd32f10x_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_FWDGT_H
|
||||
#define GD32F10X_FWDGT_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
|
||||
/* constants definitions */
|
||||
/* psc register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32F10X_FWDGT_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,95 @@
|
||||
/*!
|
||||
\file gd32f10x_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_MISC_H
|
||||
#define GD32F10X_MISC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* priority group - define the pre-emption priority and the subpriority */
|
||||
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
|
||||
|
||||
/* choose the method to enter or exit the lowpower mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
/* set the priority group */
|
||||
void nvic_priority_group_set(uint32_t nvic_prigroup);
|
||||
|
||||
/* enable NVIC request */
|
||||
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
|
||||
/* disable NVIC request */
|
||||
void nvic_irq_disable(uint8_t nvic_irq);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32F10X_MISC_H */
|
||||
@@ -0,0 +1,129 @@
|
||||
/*!
|
||||
\file gd32f10x_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_PMU_H
|
||||
#define GD32F10X_PMU_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
|
||||
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work at sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work at deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work at standby mode */
|
||||
void pmu_to_standbymode(uint8_t standbymodecmd);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(void);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(void);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable write access to the registers in backup domain */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable write access to the registers in backup domain */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag_reset);
|
||||
|
||||
#endif /* GD32F10X_PMU_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,152 @@
|
||||
/*!
|
||||
\file gd32f10x_rtc.h
|
||||
\brief definitions for the RTC
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_RTC_H
|
||||
#define GD32F10X_RTC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* RTC definitions */
|
||||
#define RTC RTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
|
||||
#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
|
||||
#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
|
||||
#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
|
||||
#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
|
||||
#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
|
||||
#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
|
||||
#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
|
||||
#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
|
||||
#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTC_INTEN */
|
||||
#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
|
||||
#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
|
||||
#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC_CTL */
|
||||
#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
|
||||
#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
|
||||
#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
|
||||
#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
|
||||
#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
|
||||
#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
|
||||
|
||||
/* RTC_PSCH */
|
||||
#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
|
||||
|
||||
/* RTC_PSCL */
|
||||
#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
|
||||
|
||||
/* RTC_DIVH */
|
||||
#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
|
||||
|
||||
/* RTC_DIVL */
|
||||
#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
|
||||
|
||||
/* RTC_CNTH */
|
||||
#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
|
||||
|
||||
/* RTC_CNTL */
|
||||
#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
|
||||
|
||||
/* RTC_ALRMH */
|
||||
#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
|
||||
|
||||
/* RTC_ALRML */
|
||||
#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
|
||||
|
||||
/* constants definitions */
|
||||
/* RTC interrupt enable or disable definitions */
|
||||
#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
|
||||
#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
|
||||
#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC interrupt flag definitions */
|
||||
#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
|
||||
/* RTC flag definitions */
|
||||
#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
|
||||
#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* enter RTC configuration mode */
|
||||
void rtc_configuration_mode_enter(void);
|
||||
/* exit RTC configuration mode */
|
||||
void rtc_configuration_mode_exit(void);
|
||||
/* set RTC counter value */
|
||||
void rtc_counter_set(uint32_t cnt);
|
||||
/* set RTC prescaler value */
|
||||
void rtc_prescaler_set(uint32_t psc);
|
||||
|
||||
/* operation functions */
|
||||
/* wait RTC last write operation finished flag set */
|
||||
void rtc_lwoff_wait(void);
|
||||
/* wait RTC registers synchronized flag set */
|
||||
void rtc_register_sync_wait(void);
|
||||
/* set RTC alarm value */
|
||||
void rtc_alarm_config(uint32_t alarm);
|
||||
/* get RTC counter value */
|
||||
uint32_t rtc_counter_get(void);
|
||||
/* get RTC divider value */
|
||||
uint32_t rtc_divider_get(void);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* get RTC flag status */
|
||||
FlagStatus rtc_flag_get(uint32_t flag);
|
||||
/* clear RTC flag status */
|
||||
void rtc_flag_clear(uint32_t flag);
|
||||
/* get RTC interrupt flag status */
|
||||
FlagStatus rtc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear RTC interrupt flag status */
|
||||
void rtc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable RTC interrupt */
|
||||
void rtc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable RTC interrupt */
|
||||
void rtc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F10X_RTC_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,90 @@
|
||||
/*!
|
||||
\file gd32f10x_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_WWDGT_H
|
||||
#define GD32F10X_WWDGT_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
|
||||
#endif /* GD32F10X_WWDGT_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,131 @@
|
||||
/*!
|
||||
\file gd32f10x_crc.c
|
||||
\brief CRC driver
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f10x_crc.h"
|
||||
|
||||
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
|
||||
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
|
||||
|
||||
/*!
|
||||
\brief deinit CRC calculation unit
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_deinit(void)
|
||||
{
|
||||
CRC_DATA = CRC_DATA_RESET_VALUE;
|
||||
CRC_FDATA = CRC_FDATA_RESET_VALUE;
|
||||
CRC_CTL = (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset data register to the value of initializaiton data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_data_register_reset(void)
|
||||
{
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the value of the data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 32-bit value of the data register
|
||||
*/
|
||||
uint32_t crc_data_register_read(void)
|
||||
{
|
||||
uint32_t data;
|
||||
data = CRC_DATA;
|
||||
return (data);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the value of the free data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 8-bit value of the free data register
|
||||
*/
|
||||
uint8_t crc_free_data_register_read(void)
|
||||
{
|
||||
uint8_t fdata;
|
||||
fdata = (uint8_t)CRC_FDATA;
|
||||
return (fdata);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the free data register
|
||||
\param[in] free_data: specify 8-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_free_data_register_write(uint8_t free_data)
|
||||
{
|
||||
CRC_FDATA = (uint32_t)free_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief calculate the CRC value of a 32-bit data
|
||||
\param[in] sdata: specified 32-bit data
|
||||
\param[out] none
|
||||
\retval 32-bit value calculated by CRC
|
||||
*/
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata)
|
||||
{
|
||||
CRC_DATA = sdata;
|
||||
return (CRC_DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief calculate the CRC value of an array of 32-bit values
|
||||
\param[in] array: pointer to an array of 32-bit values
|
||||
\param[in] size: size of the array
|
||||
\param[out] none
|
||||
\retval 32-bit value calculated by CRC
|
||||
*/
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
|
||||
{
|
||||
uint32_t index;
|
||||
for(index = 0U; index < size; index++){
|
||||
CRC_DATA = array[index];
|
||||
}
|
||||
return (CRC_DATA);
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,153 @@
|
||||
/*!
|
||||
\file gd32f10x_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f10x_dbg.h"
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_CTL |= (uint32_t)dbg_periph;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_CTL &= ~(uint32_t)dbg_periph;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable trace pin assignment
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_trace_pin_enable(void)
|
||||
{
|
||||
DBG_CTL |= DBG_CTL_TRACE_IOEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable trace pin assignment
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_trace_pin_disable(void)
|
||||
{
|
||||
DBG_CTL &= ~DBG_CTL_TRACE_IOEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief trace pin mode selection
|
||||
\param[in] trace_mode:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg TRACE_MODE_ASYNC: trace pin used for async mode
|
||||
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
|
||||
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
|
||||
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_trace_pin_mode_set(uint32_t trace_mode)
|
||||
{
|
||||
DBG_CTL &= ~DBG_CTL_TRACE_MODE;
|
||||
DBG_CTL |= trace_mode;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,155 @@
|
||||
/*!
|
||||
\file gd32f10x_fwdgt.c
|
||||
\brief FWDGT driver
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f10x_fwdgt.h"
|
||||
|
||||
/* write value to FWDGT_CTL_CMD bit field */
|
||||
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/*!
|
||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_disable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the free watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reload the counter of FWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_counter_reload(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter reload value, and prescaler divider value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_div: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
/* wait until the PUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_div;
|
||||
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
/* wait until the RUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
if(FWDGT_STAT & flag){
|
||||
return SET;
|
||||
}
|
||||
|
||||
return RESET;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,187 @@
|
||||
/*!
|
||||
\file gd32f10x_misc.c
|
||||
\brief MISC driver
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f10x_misc.h"
|
||||
|
||||
/*!
|
||||
\brief set the priority group
|
||||
\param[in] nvic_prigroup: the NVIC priority group
|
||||
\arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_priority_group_set(uint32_t nvic_prigroup)
|
||||
{
|
||||
/* set the priority group value */
|
||||
SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
|
||||
\param[in] nvic_irq_sub_priority: the subpriority needed to set
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_enable(uint8_t nvic_irq,
|
||||
uint8_t nvic_irq_pre_priority,
|
||||
uint8_t nvic_irq_sub_priority)
|
||||
{
|
||||
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
|
||||
|
||||
/* use the priority group value to get the temp_pre and the temp_sub */
|
||||
switch ((SCB->AIRCR) & (uint32_t)0x700U) {
|
||||
case NVIC_PRIGROUP_PRE0_SUB4:
|
||||
temp_pre = 0U;
|
||||
temp_sub = 0x4U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE1_SUB3:
|
||||
temp_pre = 1U;
|
||||
temp_sub = 0x3U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE2_SUB2:
|
||||
temp_pre = 2U;
|
||||
temp_sub = 0x2U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE3_SUB1:
|
||||
temp_pre = 3U;
|
||||
temp_sub = 0x1U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE4_SUB0:
|
||||
temp_pre = 4U;
|
||||
temp_sub = 0x0U;
|
||||
break;
|
||||
default:
|
||||
nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
|
||||
temp_pre = 2U;
|
||||
temp_sub = 0x2U;
|
||||
break;
|
||||
}
|
||||
|
||||
/* get the temp_priority to fill the NVIC->IP register */
|
||||
temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
|
||||
temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
|
||||
temp_priority = temp_priority << 0x04U;
|
||||
NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
|
||||
|
||||
/* enable the selected IRQ */
|
||||
NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_disable(uint8_t nvic_irq)
|
||||
{
|
||||
/* disable the selected IRQ.*/
|
||||
NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the NVIC vector table base address
|
||||
\param[in] nvic_vict_tab: the RAM or FLASH base address
|
||||
\arg NVIC_VECTTAB_RAM: RAM base address
|
||||
\are NVIC_VECTTAB_FLASH: Flash base address
|
||||
\param[in] offset: Vector Table offset
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
|
||||
{
|
||||
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
|
||||
by all the enable and disable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_set(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR |= (uint32_t)lowpower_mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
|
||||
woke up by the enable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_reset(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR &= (~(uint32_t)lowpower_mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the systick clock source
|
||||
\param[in] systick_clksource: the systick clock source needed to choose
|
||||
\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
|
||||
\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
|
||||
void systick_clksource_set(uint32_t systick_clksource)
|
||||
{
|
||||
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
|
||||
/* set the systick clock source from HCLK */
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}else{
|
||||
/* set the systick clock source from HCLK/8 */
|
||||
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,150 @@
|
||||
/*!
|
||||
\file gd32f10x_wwdgt.c
|
||||
\brief WWDGT driver
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f10x_wwdgt.h"
|
||||
|
||||
/* write value to WWDGT_CTL_CNT bit field */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
/* write value to WWDGT_CFG_WIN bit field */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/*!
|
||||
\brief reset the window watchdog timer configuration
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_WWDGTRST);
|
||||
rcu_periph_reset_disable(RCU_WWDGTRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the window watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_enable(void)
|
||||
{
|
||||
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the window watchdog timer counter value
|
||||
\param[in] counter_value: 0x00 - 0x7F
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_counter_update(uint16_t counter_value)
|
||||
{
|
||||
uint32_t reg = 0U;
|
||||
|
||||
reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
|
||||
reg |= CTL_CNT(counter_value);
|
||||
|
||||
WWDGT_CTL = reg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter value, window value, and prescaler divider value
|
||||
\param[in] counter: 0x00 - 0x7F
|
||||
\param[in] window: 0x00 - 0x7F
|
||||
\param[in] prescaler: wwdgt prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
|
||||
\arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
|
||||
\arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
|
||||
\arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
|
||||
{
|
||||
uint32_t reg_cfg = 0U, reg_ctl = 0U;
|
||||
|
||||
/* clear WIN and PSC bits, clear CNT bit */
|
||||
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
|
||||
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
|
||||
|
||||
/* configure WIN and PSC bits, configure CNT bit */
|
||||
reg_cfg |= CFG_WIN(window);
|
||||
reg_cfg |= prescaler;
|
||||
reg_ctl |= CTL_CNT(counter);
|
||||
|
||||
WWDGT_CTL = reg_ctl;
|
||||
WWDGT_CFG = reg_cfg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable early wakeup interrupt of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_interrupt_enable(void)
|
||||
{
|
||||
WWDGT_CFG |= WWDGT_CFG_EWIE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief check early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus wwdgt_flag_get(void)
|
||||
{
|
||||
if(WWDGT_STAT & WWDGT_STAT_EWIF){
|
||||
return SET;
|
||||
}
|
||||
|
||||
return RESET;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_flag_clear(void)
|
||||
{
|
||||
WWDGT_STAT &= (~WWDGT_STAT_EWIF);
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,62 @@
|
||||
/*!
|
||||
\file usbd_int.h
|
||||
\brief USB device interrupt handler header file
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBD_INT_H
|
||||
#define USBD_INT_H
|
||||
|
||||
#include "usbd_core.h"
|
||||
#include "usbd_std.h"
|
||||
#include "usbd_pwr.h"
|
||||
|
||||
/* constants definitions */
|
||||
extern usbd_core_handle_struct usb_device_dev;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */
|
||||
}usbd_int_cb_struct;
|
||||
|
||||
extern usbd_int_cb_struct *usbd_int_fops;
|
||||
|
||||
/* function declarations */
|
||||
/* USB device interrupt service routine */
|
||||
void usbd_isr (void);
|
||||
/* handle USB high priority successful transfer event */
|
||||
uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev);
|
||||
|
||||
#endif /* USBD_INT_H */
|
||||
@@ -0,0 +1,52 @@
|
||||
/*!
|
||||
\file usbd_pwr.h
|
||||
\brief USB device power management functions prototype
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBD_PWR_H
|
||||
#define USBD_PWR_H
|
||||
|
||||
#include "usbd_core.h"
|
||||
|
||||
/* function declarations */
|
||||
/* USB wakeup first operation is to wakeup mcu */
|
||||
void resume_mcu (void);
|
||||
/* set USB device to suspend mode */
|
||||
void usbd_suspend (void);
|
||||
/* start to remote wakeup */
|
||||
void usbd_remote_wakeup_active (void);
|
||||
|
||||
#endif /* USBD_PWR_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,159 @@
|
||||
/*!
|
||||
\file usbd_pwr.c
|
||||
\brief USB device power management driver
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "usbd_pwr.h"
|
||||
|
||||
#ifdef USBD_LOWPWR_MODE_ENABLE
|
||||
static void lowpower_mode_exit (void);
|
||||
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
||||
|
||||
__IO uint8_t g_ESOF_count = 0U;
|
||||
__IO uint8_t g_suspend_enabled = 1U;
|
||||
__IO uint8_t g_remote_wakeup_on = 0U;
|
||||
|
||||
#ifdef LPM_ENABLED
|
||||
extern __IO uint32_t L1_resume;
|
||||
#endif /* LPM_ENABLED */
|
||||
|
||||
/*!
|
||||
\brief USB wakeup first operation is to wakeup mcu
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void resume_mcu (void)
|
||||
{
|
||||
/* clear low_power mode bit in USBD_CTL */
|
||||
USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM));
|
||||
|
||||
#ifdef USBD_LOWPWR_MODE_ENABLE
|
||||
|
||||
/* restore normal operations */
|
||||
lowpower_mode_exit();
|
||||
|
||||
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
||||
|
||||
/* clear SETSPS bit */
|
||||
USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS));
|
||||
}
|
||||
|
||||
#ifdef USBD_LOWPWR_MODE_ENABLE
|
||||
|
||||
/*!
|
||||
\brief restore system clocks and power while exiting suspend mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void lowpower_mode_exit (void)
|
||||
{
|
||||
/* restore system clock */
|
||||
|
||||
/* enable HSE */
|
||||
rcu_osci_on(RCU_HXTAL);
|
||||
|
||||
/* wait till HSE is ready */
|
||||
while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB));
|
||||
|
||||
/* enable PLL */
|
||||
rcu_osci_on(RCU_PLL_CK);
|
||||
|
||||
/* wait till PLL is ready */
|
||||
while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB));
|
||||
|
||||
/* select PLL as system clock source */
|
||||
rcu_system_clock_source_config(RCU_CKSYSSRC_PLL);
|
||||
|
||||
/* wait till PLL is used as system clock source */
|
||||
while(0x08 != rcu_system_clock_source_get());
|
||||
|
||||
/* low power sleep on exit disabled */
|
||||
system_lowpower_reset(SCB_LPM_DEEPSLEEP);
|
||||
}
|
||||
|
||||
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
||||
|
||||
/*!
|
||||
\brief set USB device to suspend mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void usbd_suspend (void)
|
||||
{
|
||||
/* set usb module to suspend and low-power mode */
|
||||
USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM);
|
||||
|
||||
#ifdef USBD_LOWPWR_MODE_ENABLE
|
||||
|
||||
/* check wakeup flag is set */
|
||||
if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) {
|
||||
/* enter DEEP_SLEEP mode with LDO in low power mode */
|
||||
pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
|
||||
} else {
|
||||
/* clear wakeup interrupt flag */
|
||||
USBD_REG_SET(USBD_INTF, CLR_WKUPIF);
|
||||
|
||||
/* clear set_suspend flag */
|
||||
USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS);
|
||||
}
|
||||
|
||||
#endif /* USBD_LOWPWR_MODE_ENABLE */
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start to remote wakeup
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void usbd_remote_wakeup_active(void)
|
||||
{
|
||||
resume_mcu();
|
||||
|
||||
#ifdef LPM_ENABLED
|
||||
USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ);
|
||||
|
||||
L1_resume = 1U;
|
||||
#else
|
||||
g_remote_wakeup_on = 1U;
|
||||
|
||||
g_ESOF_count = 15U;
|
||||
USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ);
|
||||
#endif /* LPM_ENABLED */
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,128 @@
|
||||
/*!
|
||||
\file usb_defines.h
|
||||
\brief USB core defines
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USB_DEFINES_H
|
||||
#define USB_DEFINES_H
|
||||
|
||||
#include "usb_conf.h"
|
||||
|
||||
/* constants definitions */
|
||||
typedef enum
|
||||
{
|
||||
USB_HS_CORE_ID = 0,
|
||||
USB_FS_CORE_ID = 1
|
||||
}usb_core_id_enum;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
USB_SPEED_UNKNOWN = 0,
|
||||
USB_SPEED_LOW,
|
||||
USB_SPEED_FULL,
|
||||
USB_SPEED_HIGH
|
||||
}usb_speed_enum;
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL (void *)0 /*!< USB null marco value*/
|
||||
#endif /* NULL */
|
||||
|
||||
#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */
|
||||
#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */
|
||||
|
||||
#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */
|
||||
#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */
|
||||
#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */
|
||||
#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */
|
||||
|
||||
#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */
|
||||
#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */
|
||||
#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */
|
||||
#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */
|
||||
|
||||
#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */
|
||||
#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */
|
||||
|
||||
#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
|
||||
#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
|
||||
#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
|
||||
#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
|
||||
|
||||
#define GRSTATR_RPCKST_IN 2U /* in data packet received */
|
||||
#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* in transfer completed (generates an interrupt if poped) */
|
||||
#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */
|
||||
#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */
|
||||
|
||||
#define DEVICE_MODE 0U /* USB core in device mode */
|
||||
#define HOST_MODE 1U /* USB core in host mode */
|
||||
#define OTG_MODE 2U /* USB core in OTG mode */
|
||||
|
||||
#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */
|
||||
#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */
|
||||
#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */
|
||||
#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */
|
||||
#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */
|
||||
|
||||
#define RXSTAT_GOUT_NAK 1U /* global out NAK (triggers an interrupt) */
|
||||
#define RXSTAT_DATA_UPDT 2U /* out data packet received */
|
||||
#define RXSTAT_XFER_COMP 3U /* out transfer completed (triggers an interrupt) */
|
||||
#define RXSTAT_SETUP_COMP 4U /* setup transaction completed (triggers an interrupt) */
|
||||
#define RXSTAT_SETUP_UPDT 6U /* setup data packet received */
|
||||
|
||||
#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */
|
||||
#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */
|
||||
#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */
|
||||
#define DPID_MDATA 3U /* device endpoint data PID is MDATA */
|
||||
|
||||
#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */
|
||||
#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */
|
||||
#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */
|
||||
#define HC_PID_SETUP 3U /* host channel data PID is SETUP */
|
||||
|
||||
#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */
|
||||
#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */
|
||||
#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */
|
||||
|
||||
#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */
|
||||
#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */
|
||||
#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */
|
||||
|
||||
#define HCCHAR_CTRL 0U /* control channel type */
|
||||
#define HCCHAR_ISOC 1U /* synchronous channel type */
|
||||
#define HCCHAR_BULK 2U /* bulk channel type */
|
||||
#define HCCHAR_INTR 3U /* interrupt channel type */
|
||||
|
||||
#endif /* USB_DEFINES_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,81 @@
|
||||
/*!
|
||||
\file usbd_core.h
|
||||
\brief USB device mode core driver header file
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBD_CORE_H
|
||||
#define USBD_CORE_H
|
||||
|
||||
#include "usbd_conf.h"
|
||||
#include "usb_core.h"
|
||||
#include "usbd_std.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* device status */
|
||||
#define USB_STATUS_DEFAULT 1U /* default status */
|
||||
#define USB_STATUS_ADDRESSED 2U /* addressed status */
|
||||
#define USB_STATUS_CONFIGURED 3U /* configured status */
|
||||
#define USB_STATUS_SUSPENDED 4U /* suspended status */
|
||||
|
||||
/* function declarations */
|
||||
/* initailizes the USB device-mode handler stack */
|
||||
void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
|
||||
/* endpoint initialization */
|
||||
void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc);
|
||||
/* endpoint deinitialize */
|
||||
void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr);
|
||||
/* endpoint prepare to receive data */
|
||||
void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
|
||||
/* endpoint prepare to transmit data */
|
||||
void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
|
||||
/* transmit data on the control channel */
|
||||
usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
|
||||
/* receive data on the control channel */
|
||||
usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
|
||||
/* transmit status on the control channel */
|
||||
usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev);
|
||||
/* receive status on the control channel */
|
||||
usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev);
|
||||
/* set an endpoint to stall status */
|
||||
void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
|
||||
/* clear endpoint stalled status */
|
||||
void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
|
||||
/* flushes the fifos */
|
||||
void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr);
|
||||
/* get the received data length */
|
||||
uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num);
|
||||
|
||||
#endif /* USBD_CORE_H */
|
||||
@@ -0,0 +1,57 @@
|
||||
/*!
|
||||
\file usbd_int.h
|
||||
\brief USB device mode interrupt handler header file
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBD_INT_H
|
||||
#define USBD_INT_H
|
||||
|
||||
#include "usbd_core.h"
|
||||
|
||||
/* constants definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t (*SOF) (usb_core_handle_struct *pudev);
|
||||
}usbd_int_cb_struct;
|
||||
|
||||
extern usbd_int_cb_struct *usbd_int_fops;
|
||||
|
||||
/* function declaration */
|
||||
/* USB device-mode interrupts global service routine handler */
|
||||
uint32_t usbd_isr (usb_core_handle_struct *pudev);
|
||||
|
||||
#endif /* USBD_INT_H */
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
/*!
|
||||
\file usbd_std.h
|
||||
\brief USB 2.0 standard defines
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBD_STD_H
|
||||
#define USBD_STD_H
|
||||
|
||||
#include "usb_std.h"
|
||||
#include "usbd_core.h"
|
||||
#include "usbd_conf.h"
|
||||
#include <wchar.h>
|
||||
|
||||
/* constants definitions */
|
||||
#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/
|
||||
#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/
|
||||
#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/
|
||||
#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/
|
||||
#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/
|
||||
#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/
|
||||
|
||||
#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/
|
||||
#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/
|
||||
|
||||
#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/
|
||||
#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/
|
||||
#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/
|
||||
|
||||
#define ENG_LANGID 0x0409U /*!< USB english language id*/
|
||||
#define CHN_LANGID 0x0804U /*!< USB chinese language id*/
|
||||
|
||||
#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/
|
||||
|
||||
#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/
|
||||
#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/
|
||||
|
||||
#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/
|
||||
|
||||
#define WIDE_STRING(string) _WIDE_STRING(string)
|
||||
#define _WIDE_STRING(string) L##string
|
||||
|
||||
#define USBD_STRING_DESC(string) \
|
||||
(uint8_t *)&(struct { \
|
||||
uint8_t _len; \
|
||||
uint8_t _type; \
|
||||
wchar_t _data[sizeof(string)]; \
|
||||
}) { \
|
||||
sizeof(WIDE_STRING(string)) + 2U - 2U, \
|
||||
USB_DESCTYPE_STRING, \
|
||||
WIDE_STRING(string) \
|
||||
}
|
||||
|
||||
#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
|
||||
|
||||
/* function declarations */
|
||||
/* USB device setup transaction*/
|
||||
usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev);
|
||||
/* USB device out transaction*/
|
||||
usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
|
||||
/* USB device in transaction*/
|
||||
usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
|
||||
/* USB device enum error handle*/
|
||||
void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req);
|
||||
|
||||
#endif /* USBD_STD_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,73 @@
|
||||
/*!
|
||||
\file usbh_ctrl.h
|
||||
\brief header file for usbh_ctrl.c
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBH_CTRL_H
|
||||
#define USBH_CTRL_H
|
||||
|
||||
#include "usbh_core.h"
|
||||
#include "usbh_usr.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* the enum of CTRL event */
|
||||
typedef enum
|
||||
{
|
||||
CTRL_EVENT_IDLE = 0, /* the ctrl idle event */
|
||||
CTRL_EVENT_SETUP, /* the ctrl setup event */
|
||||
CTRL_EVENT_DATA, /* the ctrl data event */
|
||||
CTRL_EVENT_STATUS, /* the ctrl status event */
|
||||
CTRL_EVENT_COMPLETE, /* the ctrl complete event */
|
||||
CTRL_EVENT_ERROR, /* the ctrl error event */
|
||||
CTRL_EVENT_STALLED, /* the ctrl stalled event */
|
||||
}ctrl_event_enum;
|
||||
|
||||
#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */
|
||||
|
||||
extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE];
|
||||
extern uint8_t ctrl_polling_handle_flag;
|
||||
|
||||
/* function declarations */
|
||||
/* the polling function of control transfer state handle */
|
||||
usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
|
||||
/* send datas from the host channel */
|
||||
usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len);
|
||||
/* send the setup packet to the device */
|
||||
usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num);
|
||||
/* this function prepare a hc and start a transfer */
|
||||
uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num);
|
||||
|
||||
#endif /* USBH_CTRL_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/*!
|
||||
\file usbh_hcs.h
|
||||
\brief header file for usbh_hcs.c
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBH_HCS_H
|
||||
#define USBH_HCS_H
|
||||
|
||||
#include "usbh_core.h"
|
||||
|
||||
/* constants definitions */
|
||||
#define HC_MAX 8U
|
||||
#define HC_OK 0x0000U
|
||||
#define HC_USED 0x8000U
|
||||
#define HC_ERROR 0xFFFFU
|
||||
#define HC_USED_MASK 0x7FFFU
|
||||
|
||||
/* function declarations */
|
||||
/* allocate a new channel for the pipe */
|
||||
uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr);
|
||||
/* free all usb host channel */
|
||||
uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev);
|
||||
/* free the usb host channel */
|
||||
uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index);
|
||||
/* open a channel */
|
||||
uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
|
||||
uint8_t channel_num,
|
||||
uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_mps);
|
||||
/* modify a channel */
|
||||
uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
|
||||
uint8_t channel_num,
|
||||
uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_mps);
|
||||
|
||||
#endif /* USBH_HCS_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*!
|
||||
\file usbh_int.h
|
||||
\brief USB host mode interrupt handler header file
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBH_INT_H
|
||||
#define USBH_INT_H
|
||||
|
||||
#include "usb_core.h"
|
||||
|
||||
/* constants definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t (*sof) (usb_core_handle_struct *pudev);
|
||||
uint8_t (*device_connected) (usb_core_handle_struct *pudev);
|
||||
uint8_t (*device_disconnected) (usb_core_handle_struct *pudev);
|
||||
}usbh_hcd_int_cb_struct;
|
||||
|
||||
extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops;
|
||||
|
||||
/* function declarations */
|
||||
/* handle global host interrupt */
|
||||
uint32_t usbh_isr (usb_core_handle_struct *pudev);
|
||||
|
||||
#endif /* USBH_INT_H */
|
||||
@@ -0,0 +1,101 @@
|
||||
/*!
|
||||
\file usbh_std.h
|
||||
\brief header file for usbh_std.c
|
||||
|
||||
\version 2014-12-26, V1.0.0, firmware for GD32F10x
|
||||
\version 2017-06-20, V2.0.0, firmware for GD32F10x
|
||||
\version 2018-07-31, V2.1.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USBH_STD_H
|
||||
#define USBH_STD_H
|
||||
|
||||
#include "usbh_core.h"
|
||||
#include "usbh_usr.h"
|
||||
|
||||
/* constants definitions */
|
||||
typedef enum
|
||||
{
|
||||
ENUN_EVENT_IDLE = 0, /* the enum idle event */
|
||||
ENUM_EVENT_SET_ADDR, /* the enum set address event */
|
||||
ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */
|
||||
ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */
|
||||
ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */
|
||||
ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */
|
||||
ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */
|
||||
ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */
|
||||
ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */
|
||||
ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */
|
||||
}enum_event_enum;
|
||||
/* standard feature selector for clear feature command */
|
||||
#define FEATURE_SELECTOR_ENDPOINT 0x00U
|
||||
#define FEATURE_SELECTOR_DEVICE 0x01U
|
||||
|
||||
#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */
|
||||
#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */
|
||||
|
||||
extern uint8_t usbh_cfg_desc[512];
|
||||
extern uint8_t enum_polling_handle_flag;
|
||||
extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE];
|
||||
|
||||
/* function declarations */
|
||||
/* the polling function of enumeration state */
|
||||
usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
|
||||
/* get descriptor in usb host enumeration stage */
|
||||
void usbh_enum_desc_get (usb_core_handle_struct *pudev,
|
||||
usbh_host_struct *puhost,
|
||||
uint8_t *buf,
|
||||
uint8_t req_type,
|
||||
uint16_t value_idx,
|
||||
uint16_t len);
|
||||
/* set address in usb host enumeration stage */
|
||||
void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address);
|
||||
/* set configuration in usb host enumeration stage */
|
||||
void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx);
|
||||
/* parse the device descriptor */
|
||||
void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len);
|
||||
/* parse the configuration descriptor */
|
||||
void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
|
||||
usb_descriptor_interface_struct *itf_desc,
|
||||
usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
|
||||
uint8_t *buf,
|
||||
uint16_t len);
|
||||
/* parse the interface descriptor */
|
||||
void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf);
|
||||
/* parse the endpoint descriptor */
|
||||
void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf);
|
||||
/* parse the string descriptor */
|
||||
void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
|
||||
/* get the next descriptor header */
|
||||
usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr);
|
||||
|
||||
#endif /* USBH_STD_H */
|
||||
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Loaded 100 of 336 files, more files were not shown because too many files have changed in this diff.
Show more
Reference in new issue
Block a user