mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-11-09 20:45:41 +08:00
Merge branch 'master' of https://github.com/RT-Thread/rt-thread
This commit is contained in:
Bernard Xiong committed
commit
3c04d0b0a0
125 files changed
+50047
-142
No files matched your search
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,36 @@
|
||||
/** @file dmm.h
|
||||
* @brief DMM Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
|
||||
#ifndef __DMM_H__
|
||||
#define __DMM_H__
|
||||
|
||||
#include "reg_dmm.h"
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup DMM DMM
|
||||
* @brief Data Modification Module.
|
||||
*
|
||||
* The DMM module provides the capability to modify data in the entire 4 GB address space of the device from an external peripheral,
|
||||
* with minimal interruption of the application.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_dmm.h
|
||||
* - dmm.h
|
||||
* - dmm.c
|
||||
* @addtogroup DMM
|
||||
* @{
|
||||
*/
|
||||
/* DMM Interface Functions */
|
||||
|
||||
void dmmInit(void);
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
@@ -0,0 +1,125 @@
|
||||
/**
|
||||
* \file emac.h
|
||||
*
|
||||
* \brief EMAC APIs and macros.
|
||||
*
|
||||
* This file contains the driver API prototypes and macro definitions.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __EMAC_H__
|
||||
#define __EMAC_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "hw_emac.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
** Macros which can be used as speed parameter to the API EMACRMIISpeedSet
|
||||
*/
|
||||
#define EMAC_RMIISPEED_10MBPS (0x00000000U)
|
||||
#define EMAC_RMIISPEED_100MBPS (0x00008000U)
|
||||
|
||||
/*
|
||||
** Macros which can be used as duplexMode parameter to the API
|
||||
** EMACDuplexSet
|
||||
*/
|
||||
#define EMAC_DUPLEX_FULL (0x00000001U)
|
||||
#define EMAC_DUPLEX_HALF (0x00000000U)
|
||||
|
||||
/*
|
||||
** Macros which can be used as matchFilt parameters to the API
|
||||
** EMACMACAddrSet
|
||||
*/
|
||||
/* Address not used to match/filter incoming packets */
|
||||
#define EMAC_MACADDR_NO_MATCH_NO_FILTER (0x00000000U)
|
||||
|
||||
/* Address will be used to filter incoming packets */
|
||||
#define EMAC_MACADDR_FILTER (0x00100000U)
|
||||
|
||||
/* Address will be used to match incoming packets */
|
||||
#define EMAC_MACADDR_MATCH (0x00180000U)
|
||||
|
||||
/*
|
||||
** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API
|
||||
*/
|
||||
#define EMAC_INT_CORE0_RX (0x1U)
|
||||
#define EMAC_INT_CORE1_RX (0x5U)
|
||||
#define EMAC_INT_CORE2_RX (0x9U)
|
||||
|
||||
/*
|
||||
** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API
|
||||
*/
|
||||
#define EMAC_INT_CORE0_TX (0x2U)
|
||||
#define EMAC_INT_CORE1_TX (0x6U)
|
||||
#define EMAC_INT_CORE2_TX (0xAU)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @defgroup EMACMDIO EMAC/MDIO
|
||||
* @brief Ethernet Media Access Controller/Management Data Input/Output.
|
||||
*
|
||||
* The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY
|
||||
* configuration and status monitoring.
|
||||
*
|
||||
* Both the EMAC and the MDIO modules interface to the system core through a custom interface that
|
||||
* allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
|
||||
* module and is considered integral to the EMAC/MDIO peripheral
|
||||
*
|
||||
* Related Files
|
||||
* - emac.h
|
||||
* - emac.c
|
||||
* - hw_emac.h
|
||||
* - hw_emac_ctrl.h
|
||||
* - hw_mdio.h
|
||||
* - hw_reg_access.h
|
||||
* - mdio.h
|
||||
* - mdio.c
|
||||
* @addtogroup EMACMDIO
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
** Prototypes for the APIs
|
||||
*/
|
||||
extern void EMACTxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
|
||||
uint32 ctrlCore, uint32 channel);
|
||||
extern void EMACTxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
|
||||
uint32 ctrlCore, uint32 channel);
|
||||
extern void EMACRxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
|
||||
uint32 ctrlCore, uint32 channel);
|
||||
extern void EMACRxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
|
||||
uint32 ctrlCore, uint32 channel);
|
||||
extern void EMACRMIISpeedSet(uint32 emacBase, uint32 speed);
|
||||
extern void EMACDuplexSet(uint32 emacBase, uint32 duplexMode);
|
||||
extern void EMACTxEnable(uint32 emacBase);
|
||||
extern void EMACRxEnable(uint32 emacBase);
|
||||
extern void EMACTxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
|
||||
uint32 channel);
|
||||
extern void EMACRxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
|
||||
uint32 channel);
|
||||
extern void EMACInit(uint32 emacCtrlBase, uint32 emacBase);
|
||||
extern void EMACMACSrcAddrSet(uint32 emacBase, uint8 * macAddr);
|
||||
extern void EMACMACAddrSet(uint32 emacBase, uint32 channel,
|
||||
uint8 * macAddr, uint32 matchFilt);
|
||||
extern void EMACMIIEnable(uint32 emacBase);
|
||||
extern void EMACRxUnicastSet(uint32 emacBase, uint32 channel);
|
||||
extern void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag);
|
||||
extern void EMACTxCPWrite(uint32 emacBase, uint32 channel,
|
||||
uint32 comPtr);
|
||||
extern void EMACRxCPWrite(uint32 emacBase, uint32 channel,
|
||||
uint32 comPtr);
|
||||
extern void EMACRxBroadCastEnable(uint32 emacBase, uint32 channel);
|
||||
extern void EMACNumFreeBufSet(uint32 emacBase, uint32 channel,
|
||||
uint32 nBuf);
|
||||
extern uint32 EMACIntVectorGet(uint32 emacBase);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* __EMAC_H__ */
|
||||
@@ -0,0 +1,101 @@
|
||||
/** @file emif.h
|
||||
* @brief emif Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef _EMIF_H_
|
||||
#define _EMIF_H_
|
||||
|
||||
#include "reg_emif.h"
|
||||
|
||||
|
||||
|
||||
/** @enum emif_pins
|
||||
* @brief Alias for emif pins
|
||||
*
|
||||
*/
|
||||
enum emif_pins
|
||||
{
|
||||
emif_wait_pin0 = 0U,
|
||||
emif_wait_pin1 = 1U
|
||||
};
|
||||
|
||||
|
||||
/** @enum emif_size
|
||||
* @brief Alias for emif page size
|
||||
*
|
||||
*/
|
||||
enum emif_size
|
||||
{
|
||||
elements_256 = 0U,
|
||||
elements_512 = 1U,
|
||||
elements_1024 = 2U,
|
||||
elements_2048 = 3U
|
||||
};
|
||||
|
||||
/** @enum emif_port
|
||||
* @brief Alias for emif port
|
||||
*
|
||||
*/
|
||||
enum emif_port
|
||||
{
|
||||
emif_8_bit_port = 0U,
|
||||
emif_16_bit_port = 1U
|
||||
};
|
||||
|
||||
|
||||
/** @enum emif_pagesize
|
||||
* @brief Alias for emif pagesize
|
||||
*
|
||||
*/
|
||||
enum emif_pagesize
|
||||
{
|
||||
emif_4_words = 0U,
|
||||
emif_8_words = 1U
|
||||
};
|
||||
|
||||
/** @enum emif_wait_polarity
|
||||
* @brief Alias for emif wait polarity
|
||||
*
|
||||
*/
|
||||
enum emif_wait_polarity
|
||||
{
|
||||
emif_pin_low = 0U,
|
||||
emif_pin_high = 1U
|
||||
};
|
||||
|
||||
|
||||
#define PTR (uint32 *)(0x80000000U)
|
||||
|
||||
/**
|
||||
* @defgroup EMIF EMIF
|
||||
* @brief Error Signaling Module.
|
||||
*
|
||||
* This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 16-bit
|
||||
* data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external
|
||||
* devices including:
|
||||
* - Single data rate (SDR) SDRAM
|
||||
* - Asynchronous devices including NOR Flash and SRAM
|
||||
* The most common use for the EMIF is to interface with both a flash device and an SDRAM device
|
||||
* simultaneously. contains an example of operating the EMIF in this configuration.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_emif.h
|
||||
* - emif.h
|
||||
* - emif.c
|
||||
* @addtogroup EMIF
|
||||
* @{
|
||||
*/
|
||||
/* EMIF Interface Functions */
|
||||
|
||||
void emif_SDRAMInit(void);
|
||||
void emif_ASYNC1Init(void);
|
||||
void emif_ASYNC2Init(void);
|
||||
void emif_ASYNC3Init(void);
|
||||
|
||||
/**@}*/
|
||||
#endif /*EMIF_H_*/
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,45 @@
|
||||
/** @file gio.h
|
||||
* @brief GIO Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __GIO_H__
|
||||
#define __GIO_H__
|
||||
|
||||
#include "reg_gio.h"
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup GIO GIO
|
||||
* @brief General-Purpose Input/Output Module.
|
||||
*
|
||||
* The GIO module provides the family of devices with input/output (I/O) capability.
|
||||
* The I/O pins are bidirectional and bit-programmable.
|
||||
* The GIO module also supports external interrupt capability.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_gio.h
|
||||
* - gio.h
|
||||
* - gio.c
|
||||
* @addtogroup GIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* GIO Interface Functions */
|
||||
void gioInit(void);
|
||||
void gioSetDirection(gioPORT_t *port, uint32 dir);
|
||||
void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value);
|
||||
void gioSetPort(gioPORT_t *port, uint32 value);
|
||||
uint32 gioGetBit(gioPORT_t *port, uint32 bit);
|
||||
uint32 gioGetPort(gioPORT_t *port);
|
||||
void gioToggleBit(gioPORT_t *port, uint32 bit);
|
||||
void gioEnableNotification(gioPORT_t *port, uint32 bit);
|
||||
void gioDisableNotification(gioPORT_t *port, uint32 bit);
|
||||
void gioNotification(gioPORT_t *port, sint32 bit);
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
@@ -0,0 +1,104 @@
|
||||
/** @file hal_stdtypes.h
|
||||
* @brief HALCoGen standard types header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Type and Global definitions which are relevant for all drivers.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __HAL_STDTYPES_H__
|
||||
#define __HAL_STDTYPES_H__
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
/************************************************************/
|
||||
/* Type Definitions */
|
||||
/************************************************************/
|
||||
#ifndef _UINT64_DECLARED
|
||||
typedef unsigned long long uint64;
|
||||
#define _UINT64_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT32_DECLARED
|
||||
typedef unsigned int uint32;
|
||||
#define _UINT32_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT16_DECLARED
|
||||
typedef unsigned short uint16;
|
||||
#define _UINT16_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT8_DECLARED
|
||||
typedef unsigned char uint8;
|
||||
#define _UINT8_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _BOOLEAN_DECLARED
|
||||
typedef unsigned char boolean;
|
||||
typedef unsigned char boolean_t;
|
||||
#define _BOOLEAN_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _SINT64_DECLARED
|
||||
typedef signed long long sint64;
|
||||
#define _SINT64_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _SINT32_DECLARED
|
||||
typedef signed int sint32;
|
||||
#define _SINT32_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _SINT16_DECLARED
|
||||
typedef signed short sint16;
|
||||
#define _SINT16_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _SINT8_DECLARED
|
||||
typedef signed char sint8;
|
||||
#define _SINT8_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _FLOAT32_DECLARED
|
||||
typedef float float32;
|
||||
#define _FLOAT32_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _FLOAT64_DECLARED
|
||||
typedef double float64;
|
||||
#define _FLOAT64_DECLARED
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************/
|
||||
/* Global Definitions */
|
||||
/************************************************************/
|
||||
/** @def NULL
|
||||
* @brief NULL definition
|
||||
*/
|
||||
#ifndef NULL
|
||||
#define NULL ((void *) 0U)
|
||||
#endif
|
||||
|
||||
/** @def TRUE
|
||||
* @brief definition for TRUE
|
||||
*/
|
||||
#ifndef TRUE
|
||||
#define TRUE (boolean)1U
|
||||
#endif
|
||||
|
||||
/** @def FALSE
|
||||
* @brief BOOLEAN definition for FALSE
|
||||
*/
|
||||
#ifndef FALSE
|
||||
#define FALSE (boolean)0U
|
||||
#endif
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
#endif /* __HAL_STDTYPES_H__ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,25 @@
|
||||
/** @file htu.h
|
||||
* @brief HTU Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
|
||||
#ifndef __HTU_H__
|
||||
#define __HTU_H__
|
||||
|
||||
#include "reg_htu.h"
|
||||
|
||||
/* HTU General Definitions */
|
||||
|
||||
|
||||
#define HTU1PARLOC (*(volatile uint32 *)0xFF4E0200U)
|
||||
#define HTU2PARLOC (*(volatile uint32 *)0xFF4C0200U)
|
||||
|
||||
#define HTU1RAMLOC (*(volatile uint32 *)0xFF4E0000U)
|
||||
#define HTU2RAMLOC (*(volatile uint32 *)0xFF4C0000U)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* hw_emac1.h
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef _HW_EMAC_CTRL_H_
|
||||
#define _HW_EMAC_CTRL_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EMAC_CTRL_REVID (0x0U)
|
||||
#define EMAC_CTRL_SOFTRESET (0x4U)
|
||||
#define EMAC_CTRL_INTCONTROL (0xCU)
|
||||
#define EMAC_CTRL_C0RXTHRESHEN (0x10U)
|
||||
#define EMAC_CTRL_CnRXEN(n) (0x14u + ((n) << 4))
|
||||
#define EMAC_CTRL_CnTXEN(n) (0x18u + ((n) << 4))
|
||||
#define EMAC_CTRL_CnMISCEN(n) (0x1Cu + ((n) << 4))
|
||||
#define EMAC_CTRL_CnRXTHRESHEN(n) (0x20u + ((n) << 4))
|
||||
#define EMAC_CTRL_C0RXTHRESHSTAT (0x40U)
|
||||
#define EMAC_CTRL_C0RXSTAT (0x44U)
|
||||
#define EMAC_CTRL_C0TXSTAT (0x48U)
|
||||
#define EMAC_CTRL_C0MISCSTAT (0x4CU)
|
||||
#define EMAC_CTRL_C1RXTHRESHSTAT (0x50U)
|
||||
#define EMAC_CTRL_C1RXSTAT (0x54U)
|
||||
#define EMAC_CTRL_C1TXSTAT (0x58U)
|
||||
#define EMAC_CTRL_C1MISCSTAT (0x5CU)
|
||||
#define EMAC_CTRL_C2RXTHRESHSTAT (0x60U)
|
||||
#define EMAC_CTRL_C2RXSTAT (0x64U)
|
||||
#define EMAC_CTRL_C2TXSTAT (0x68U)
|
||||
#define EMAC_CTRL_C2MISCSTAT (0x6CU)
|
||||
#define EMAC_CTRL_C0RXIMAX (0x70U)
|
||||
#define EMAC_CTRL_C0TXIMAX (0x74U)
|
||||
#define EMAC_CTRL_C1RXIMAX (0x78U)
|
||||
#define EMAC_CTRL_C1TXIMAX (0x7CU)
|
||||
#define EMAC_CTRL_C2RXIMAX (0x80U)
|
||||
#define EMAC_CTRL_C2TXIMAX (0x84U)
|
||||
|
||||
/**************************************************************************\
|
||||
* Field Definition Macros
|
||||
\**************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* hw_reg_access.h.h
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef _HW_REG_ACCESS_H_
|
||||
#define _HW_REG_ACCESS_H_
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Macros for hardware access, both direct and via the bit-band region.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define HWREG(x) \
|
||||
(*((volatile uint32 *)(x)))
|
||||
#define HWREGH(x) \
|
||||
(*((volatile uint16 *)(x)))
|
||||
#define HWREGB(x) \
|
||||
(*((volatile uint8 *)(x)))
|
||||
#define HWREGBITW(x, b) \
|
||||
HWREG(((uint32)(x) & 0xF0000000U) | 0x02000000U | \
|
||||
(((uint32)(x) & 0x000FFFFFU) << 5U) | ((b) << 2U))
|
||||
#define HWREGBITH(x, b) \
|
||||
HWREGH(((uint32)(x) & 0xF0000000U) | 0x02000000U | \
|
||||
(((uint32)(x) & 0x000FFFFFU) << 5U) | ((b) << 2U))
|
||||
#define HWREGBITB(x, b) \
|
||||
HWREGB(((uint32)(x) & 0xF0000000U) | 0x02000000U | \
|
||||
(((uint32)(x) & 0x000FFFFFU) << 5U) | ((b) << 2U))
|
||||
|
||||
|
||||
|
||||
#endif /* __HW_TYPES_H__ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,156 @@
|
||||
/** @file I2C.h
|
||||
* @brief I2C Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
#include "reg_i2c.h"
|
||||
|
||||
|
||||
|
||||
/** @enum i2cMode
|
||||
* @brief Alias names for i2c modes
|
||||
* This enumeration is used to provide alias names for I2C modes:
|
||||
*/
|
||||
|
||||
enum i2cMode
|
||||
{
|
||||
I2C_FD_FORMAT = 0x0008U, /* Free Data Format */
|
||||
I2C_START_BYTE = 0x0010U,
|
||||
I2C_RESET_OUT = 0x0020U, I2C_RESET_IN = 0x0000U,
|
||||
I2C_DLOOPBACK = 0x0040U,
|
||||
I2C_REPEATMODE = 0x0080U, /* In Master Mode only */
|
||||
I2C_10BIT_AMODE = 0x0100U, I2C_7BIT_AMODE = 0x0000U,
|
||||
I2C_TRANSMITTER = 0x0200U, I2C_RECEIVER = 0x0000U,
|
||||
I2C_MASTER = 0x0400U, I2C_SLAVE = 0x0000U,
|
||||
I2C_STOP_COND = 0x0800U, /* In Master Mode only */
|
||||
I2C_START_COND = 0x2000U, /* In Master Mode only */
|
||||
I2C_FREE_RUN = 0x4000U,
|
||||
I2C_NACK_MODE = 0x8000U
|
||||
};
|
||||
|
||||
|
||||
/** @enum i2cBitCount
|
||||
* @brief Alias names for i2c bit count
|
||||
* This enumeration is used to provide alias names for I2C bit count:
|
||||
*/
|
||||
|
||||
enum i2cBitCount
|
||||
{
|
||||
I2C_2_BIT = 0x2U,
|
||||
I2C_3_BIT = 0x3U,
|
||||
I2C_4_BIT = 0x4U,
|
||||
I2C_5_BIT = 0x5U,
|
||||
I2C_6_BIT = 0x6U,
|
||||
I2C_7_BIT = 0x7U,
|
||||
I2C_8_BIT = 0x0U
|
||||
};
|
||||
|
||||
|
||||
|
||||
/** @enum i2cIntFlags
|
||||
* @brief Interrupt Flag Definitions
|
||||
*
|
||||
* Used with I2CEnableNotification, I2CDisableNotification
|
||||
*/
|
||||
enum i2cIntFlags
|
||||
{
|
||||
I2C_AL_INT = 0x0001U, /* arbitration lost */
|
||||
I2C_NACK_INT = 0x0002U, /* no acknowledgment */
|
||||
I2C_ARDY_INT = 0x0004U, /* access ready */
|
||||
I2C_RX_INT = 0x0008U, /* receive data ready */
|
||||
I2C_TX_INT = 0x0010U, /* transmit data ready */
|
||||
I2C_SCD_INT = 0x0020U, /* stop condition detect */
|
||||
I2C_AAS_INT = 0x0040U /* address as slave */
|
||||
};
|
||||
|
||||
|
||||
/** @enum i2cStatFlags
|
||||
* @brief Interrupt Status Definitions
|
||||
*
|
||||
*/
|
||||
enum i2cStatFlags
|
||||
{
|
||||
I2C_AL = 0x0001U, /* arbitration lost */
|
||||
I2C_NACK = 0x0002U, /* no acknowledgement */
|
||||
I2C_ARDY = 0x0004U, /* access ready */
|
||||
I2C_RX = 0x0008U, /* receive data ready */
|
||||
I2C_TX = 0x0010U, /* transmit data ready */
|
||||
I2C_SCD = 0x0020U, /* stop condition detect */
|
||||
I2C_AD0 = 0x0100U, /* address Zero Status */
|
||||
I2C_AAS = 0x0200U, /* address as slave */
|
||||
I2C_XSMT = 0x0400U, /* Transmit shift empty not */
|
||||
I2C_RXFULL = 0x0800U, /* receive full */
|
||||
I2C_BUSBUSY = 0x1000U, /* bus busy */
|
||||
I2C_NACKSNT = 0x2000U, /* No Ack Sent */
|
||||
I2C_SDIR = 0x4000U /* Slave Direction */
|
||||
};
|
||||
|
||||
|
||||
/** @enum i2cDMA
|
||||
* @brief I2C DMA definitions
|
||||
*
|
||||
* Used before i2c transfer
|
||||
*/
|
||||
enum i2cDMA
|
||||
{
|
||||
I2C_TXDMA = 0x20U,
|
||||
I2C_RXDMA = 0x10U
|
||||
};
|
||||
|
||||
/**
|
||||
* @defgroup I2C I2C
|
||||
* @brief Inter-Integrated Circuit Module.
|
||||
*
|
||||
* The I2C is a multi-master communication module providing an interface between the Texas Instruments (TI) microcontroller
|
||||
* and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2Cbus.
|
||||
* This module will support any slave or master I2C compatible device.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_i2c.h
|
||||
* - i2c.h
|
||||
* - i2c.c
|
||||
* @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I2C Interface Functions */
|
||||
void i2cInit(void);
|
||||
void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd);
|
||||
void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd);
|
||||
void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud);
|
||||
uint32 i2cIsTxReady(i2cBASE_t *i2c);
|
||||
void i2cSendByte(i2cBASE_t *i2c, uint8 byte);
|
||||
void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data);
|
||||
uint32 i2cIsRxReady(i2cBASE_t *i2c);
|
||||
void i2cClearSCD(i2cBASE_t *i2c);
|
||||
uint32 i2cRxError(i2cBASE_t *i2c);
|
||||
uint32 i2cReceiveByte(i2cBASE_t *i2c);
|
||||
void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data);
|
||||
void i2cEnableNotification(i2cBASE_t *i2c, uint32 flags);
|
||||
void i2cDisableNotification(i2cBASE_t *i2c, uint32 flags);
|
||||
void i2cSetStart(i2cBASE_t *i2c);
|
||||
void i2cSetStop(i2cBASE_t *i2c);
|
||||
void i2cSetCount(i2cBASE_t *i2c ,uint32 cnt);
|
||||
void i2cEnableLoopback(i2cBASE_t *i2c);
|
||||
void i2cDisableLoopback(i2cBASE_t *i2c);
|
||||
|
||||
/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags)
|
||||
* @brief Interrupt callback
|
||||
* @param[in] i2c - I2C module base address
|
||||
* @param[in] flags - copy of error interrupt flags
|
||||
*
|
||||
* This is a callback that is provided by the application and is called apon
|
||||
* an interrupt. The parameter passed to the callback is a copy of the
|
||||
* interrupt flag register.
|
||||
*/
|
||||
void i2cNotification(i2cBASE_t *i2c, uint32 flags);
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,43 @@
|
||||
/**
|
||||
* \file mdio.h
|
||||
*
|
||||
* \brief MDIO APIs and macros.
|
||||
*
|
||||
* This file contains the driver API prototypes and macro definitions.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __MDIO_H__
|
||||
#define __MDIO_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "hw_mdio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/*****************************************************************************/
|
||||
|
||||
/**
|
||||
* @addtogroup EMACMDIO
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
** Prototypes for the APIs
|
||||
*/
|
||||
extern uint32 MDIOPhyAliveStatusGet(uint32 baseAddr);
|
||||
extern uint32 MDIOPhyLinkStatusGet(uint32 baseAddr);
|
||||
extern void MDIOInit(uint32 baseAddr, uint32 mdioInputFreq,
|
||||
uint32 mdioOutputFreq);
|
||||
extern uint32 MDIOPhyRegRead(uint32 baseAddr, uint32 phyAddr,
|
||||
uint32 regNum, volatile uint16 * dataPtr);
|
||||
extern void MDIOPhyRegWrite(uint32 baseAddr, uint32 phyAddr,
|
||||
uint32 regNum, uint16 RegVal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* __MDIO_H__ */
|
||||
@@ -0,0 +1,159 @@
|
||||
/** @file mibspi.h
|
||||
* @brief MIBSPI Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
|
||||
#ifndef __MIBSPI_H__
|
||||
#define __MIBSPI_H__
|
||||
|
||||
#include "reg_mibspi.h"
|
||||
|
||||
|
||||
/** @enum triggerEvent
|
||||
* @brief Transfer Group Trigger Event
|
||||
*/
|
||||
enum triggerEvent
|
||||
{
|
||||
TRG_NEVER = 0U,
|
||||
TRG_RISING = 1U,
|
||||
TRG_FALLING = 2U,
|
||||
TRG_BOTH = 3U,
|
||||
TRG_HIGH = 5U,
|
||||
TRG_LOW = 6U,
|
||||
TRG_ALWAYS = 7U
|
||||
};
|
||||
|
||||
/** @enum triggerSource
|
||||
* @brief Transfer Group Trigger Source
|
||||
*/
|
||||
enum triggerSource
|
||||
{
|
||||
TRG_DISABLED,
|
||||
TRG_GIOA0,
|
||||
TRG_GIOA1,
|
||||
TRG_GIOA2,
|
||||
TRG_GIOA3,
|
||||
TRG_GIOA4,
|
||||
TRG_GIOA5,
|
||||
TRG_GIOA6,
|
||||
TRG_GIOA7,
|
||||
TRG_HET1_8,
|
||||
TRG_HET1_10,
|
||||
TRG_HET1_12,
|
||||
TRG_HET1_14,
|
||||
TRG_HET1_16,
|
||||
TRG_HET1_18,
|
||||
TRG_TICK
|
||||
};
|
||||
|
||||
|
||||
/** @enum mibspiPinSelect
|
||||
* @brief mibspi Pin Select
|
||||
*/
|
||||
enum mibspiPinSelect
|
||||
{
|
||||
PIN_CS0 = 0U,
|
||||
PIN_CS1 = 1U,
|
||||
PIN_CS2 = 2U,
|
||||
PIN_CS3 = 3U,
|
||||
PIN_CS4 = 4U,
|
||||
PIN_CS5 = 5U,
|
||||
PIN_CS6 = 6U,
|
||||
PIN_CS7 = 7U,
|
||||
PIN_ENA = 8U,
|
||||
PIN_CLK = 9U,
|
||||
PIN_SIMO = 10U,
|
||||
PIN_SOMI = 11U,
|
||||
PIN_SIMO_1 = 17U,
|
||||
PIN_SIMO_2 = 18U,
|
||||
PIN_SIMO_3 = 19U,
|
||||
PIN_SIMO_4 = 20U,
|
||||
PIN_SIMO_5 = 21U,
|
||||
PIN_SIMO_6 = 22U,
|
||||
PIN_SIMO_7 = 23U,
|
||||
PIN_SOMI_1 = 25U,
|
||||
PIN_SOMI_2 = 26U,
|
||||
PIN_SOMI_3 = 27U,
|
||||
PIN_SOMI_4 = 28U,
|
||||
PIN_SOMI_5 = 29U,
|
||||
PIN_SOMI_6 = 30U,
|
||||
PIN_SOMI_7 = 31U
|
||||
};
|
||||
|
||||
|
||||
/** @enum chipSelect
|
||||
* @brief Transfer Group Chip Select
|
||||
*/
|
||||
enum chipSelect
|
||||
{
|
||||
CS_NONE = 0xFFU,
|
||||
CS_0 = 0xFEU,
|
||||
CS_1 = 0xFDU,
|
||||
CS_2 = 0xFBU,
|
||||
CS_3 = 0xF7U,
|
||||
CS_4 = 0xEFU,
|
||||
CS_5 = 0xDFU,
|
||||
CS_6 = 0xBFU,
|
||||
CS_7 = 0x7FU
|
||||
};
|
||||
|
||||
/**
|
||||
* @defgroup MIBSPI MIBSPI
|
||||
* @brief Multi-Buffered Serial Peripheral Interface Module.
|
||||
*
|
||||
* The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a serial bit stream of
|
||||
* programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
|
||||
* The MibSPI has a programmable buffer memory that enables programmed transmission to be completed
|
||||
* without CPU intervention
|
||||
*
|
||||
* Related Files
|
||||
* - reg_mibspi.h
|
||||
* - mibspi.h
|
||||
* - mibspi.c
|
||||
* @addtogroup MIBSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* MIBSPI Interface Functions */
|
||||
void mibspiInit(void);
|
||||
void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port);
|
||||
void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
|
||||
uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
|
||||
void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group);
|
||||
boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group);
|
||||
void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level);
|
||||
void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group);
|
||||
void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype);
|
||||
void mibspiDisableLoopback(mibspiBASE_t *mibspi);
|
||||
|
||||
|
||||
/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
|
||||
* @brief Error interrupt callback
|
||||
* @param[in] mibspi - mibSpi module base address
|
||||
* @param[in] flags - Copy of error interrupt flags
|
||||
*
|
||||
* This is a error callback that is provided by the application and is call upon
|
||||
* an error interrupt. The paramer passed to the callback is a copy of the error
|
||||
* interrupt flag register.
|
||||
*/
|
||||
void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags);
|
||||
|
||||
|
||||
/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
|
||||
* @brief Transfer complete notification callback
|
||||
* @param[in] mibspi - mibSpi module base address
|
||||
* @param[in] group - Transfer group
|
||||
*
|
||||
* This is a callback function provided by the application. It is call when
|
||||
* a transfer is complete. The parameter is the transfer group that triggered
|
||||
* the interrupt.
|
||||
*/
|
||||
void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group);
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,97 @@
|
||||
/** @file pom.h
|
||||
* @brief POM Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __POM_H__
|
||||
#define __POM_H__
|
||||
|
||||
#include "reg_pom.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/** @enum pom_region_size
|
||||
* @brief Alias names for pom region size
|
||||
* This enumeration is used to provide alias names for POM region size:
|
||||
*/
|
||||
enum pom_region_size
|
||||
{
|
||||
SIZE_32BYTES = 0U,
|
||||
SIZE_64BYTES = 1U,
|
||||
SIZE_128BYTES = 2U,
|
||||
SIZE_256BYTES = 3U,
|
||||
SIZE_512BYTES = 4U,
|
||||
SIZE_1KB = 5U,
|
||||
SIZE_2KB = 6U,
|
||||
SIZE_4KB = 7U,
|
||||
SIZE_8KB = 8U,
|
||||
SIZE_16KB = 9U,
|
||||
SIZE_32KB = 10U,
|
||||
SIZE_64KB = 11U,
|
||||
SIZE_128KB = 12U,
|
||||
SIZE_256KB = 13U
|
||||
};
|
||||
|
||||
/** @def INTERNAL_RAM
|
||||
* @brief Alias name for Internal RAM
|
||||
*/
|
||||
#define INTERNAL_RAM 0x08000000U
|
||||
|
||||
/** @def SDRAM
|
||||
* @brief Alias name for SD RAM
|
||||
*/
|
||||
#define SDRAM 0x80000000U
|
||||
|
||||
/** @def ASYNC_MEMORY
|
||||
* @brief Alias name for Async RAM
|
||||
*/
|
||||
#define ASYNC_MEMORY 0x60000000U
|
||||
|
||||
|
||||
typedef uint32 REGION_t;
|
||||
|
||||
/** @struct REGION_CONFIG_ST
|
||||
* @brief POM region configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32 Prog_Reg_Sta_Addr;
|
||||
uint32 Ovly_Reg_Sta_Addr;
|
||||
uint32 Reg_Size;
|
||||
}REGION_CONFIG_t;
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
/**
|
||||
* @defgroup POM POM
|
||||
* @brief Parameter Overlay Module.
|
||||
*
|
||||
* The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory
|
||||
* internal or external to the device. The data requested by the CPU will be fetched from the overlay memory
|
||||
* instead of the main non-volatile memory.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_pom.h
|
||||
* - pom.h
|
||||
* - pom.c
|
||||
* @addtogroup POM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* POM Interface Functions */
|
||||
void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num);
|
||||
void POM_Reset(void);
|
||||
void POM_Init(void);
|
||||
void POM_Disable(void);
|
||||
|
||||
/**@}*/
|
||||
#endif /* __POM_H_*/
|
||||
@@ -0,0 +1,162 @@
|
||||
/** @file reg_adc.h
|
||||
* @brief ADC Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the ADC driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_ADC_H__
|
||||
#define __REG_ADC_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Adc Register Frame Definition */
|
||||
/** @struct adcBase
|
||||
* @brief ADC Register Frame Definition
|
||||
*
|
||||
* This type is used to access the ADC Registers.
|
||||
*/
|
||||
/** @typedef adcBASE_t
|
||||
* @brief ADC Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the ADC Registers.
|
||||
*/
|
||||
typedef volatile struct adcBase
|
||||
{
|
||||
uint32 RSTCR; /**< 0x0000: Reset control register */
|
||||
uint32 OPMODECR; /**< 0x0004: Operating mode control register */
|
||||
uint32 CLOCKCR; /**< 0x0008: Clock control register */
|
||||
uint32 CALCR; /**< 0x000C: Calibration control register */
|
||||
uint32 GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
|
||||
uint32 G0SRC; /**< 0x001C: Group 0 trigger source control register */
|
||||
uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */
|
||||
uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */
|
||||
uint32 GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */
|
||||
uint32 GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */
|
||||
uint32 GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */
|
||||
uint32 G0DMACR; /**< 0x004C: Group 0 DMA control register */
|
||||
uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */
|
||||
uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */
|
||||
uint32 BNDCR; /**< 0x0058: Buffer boundary control register */
|
||||
uint32 BNDEND; /**< 0x005C: Buffer boundary end register */
|
||||
uint32 G0SAMP; /**< 0x0060: Group 0 sample window register */
|
||||
uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */
|
||||
uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */
|
||||
uint32 G0SR; /**< 0x006C: Group 0 status register */
|
||||
uint32 G1SR; /**< 0x0070: Group 1 status register */
|
||||
uint32 G2SR; /**< 0x0074: Group 2 status register */
|
||||
uint32 GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */
|
||||
uint32 CALR; /**< 0x0084: Calibration register */
|
||||
uint32 SMSTATE; /**< 0x0088: State machine state register */
|
||||
uint32 LASTCONV; /**< 0x008C: Last conversion register */
|
||||
struct
|
||||
{
|
||||
uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */
|
||||
uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */
|
||||
uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */
|
||||
uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */
|
||||
uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */
|
||||
uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */
|
||||
uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */
|
||||
uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */
|
||||
} GxBUF[3U];
|
||||
uint32 G0EMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */
|
||||
uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */
|
||||
uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */
|
||||
uint32 EVTDIR; /**< 0x00FC: Event pin direction register */
|
||||
uint32 EVTOUT; /**< 0x0100: Event pin digital output register */
|
||||
uint32 EVTIN; /**< 0x0104: Event pin digital input register */
|
||||
uint32 EVTSET; /**< 0x0108: Event pin set register */
|
||||
uint32 EVTCLR; /**< 0x010C: Event pin clear register */
|
||||
uint32 EVTPDR; /**< 0x0110: Event pin open drain register */
|
||||
uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */
|
||||
uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */
|
||||
uint32 G0SAMPDISEN; /**< 0x011C: Group 0 sample discharge register */
|
||||
uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */
|
||||
uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */
|
||||
uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */
|
||||
uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */
|
||||
uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */
|
||||
uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */
|
||||
uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */
|
||||
uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */
|
||||
uint32 MAGINTCR4; /**< 0x0140: Magnitude interrupt control register 4 */
|
||||
uint32 MAGINT4MASK; /**< 0x0144: Magnitude interrupt mask register 4 */
|
||||
uint32 MAGINTCR5; /**< 0x0148: Magnitude interrupt control register 5 */
|
||||
uint32 MAGINT5MASK; /**< 0x014C: Magnitude interrupt mask register 5 */
|
||||
uint32 MAGINTCR6; /**< 0x0150: Magnitude interrupt control register 6 */
|
||||
uint32 MAGINT6MASK; /**< 0x0154: Magnitude interrupt mask register 6 */
|
||||
uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */
|
||||
uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */
|
||||
uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */
|
||||
uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */
|
||||
uint32 GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */
|
||||
uint32 G0RAMADDR; /**< 0x0174: Group 0 RAM pointer register */
|
||||
uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */
|
||||
uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */
|
||||
uint32 PARCR; /**< 0x0180: Parity control register */
|
||||
uint32 PARADDR; /**< 0x0184: Parity error address register */
|
||||
uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */
|
||||
} adcBASE_t;
|
||||
|
||||
|
||||
/** @def adcREG1
|
||||
* @brief ADC1 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the ADC driver to access the ADC1 registers.
|
||||
*/
|
||||
#define adcREG1 ((adcBASE_t *)0xFFF7C000U)
|
||||
|
||||
/** @def adcREG2
|
||||
* @brief ADC2 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the ADC driver to access the ADC2 registers.
|
||||
*/
|
||||
#define adcREG2 ((adcBASE_t *)0xFFF7C200U)
|
||||
|
||||
/** @def adcRAM1
|
||||
* @brief ADC1 RAM Pointer
|
||||
*
|
||||
* This pointer is used by the ADC driver to access the ADC1 RAM.
|
||||
*/
|
||||
#define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
|
||||
|
||||
/** @def adcRAM2
|
||||
* @brief ADC2 RAM Pointer
|
||||
*
|
||||
* This pointer is used by the ADC driver to access the ADC2 RAM.
|
||||
*/
|
||||
#define adcRAM2 (*(volatile uint32 *)0xFF3A0000U)
|
||||
|
||||
/** @def adcPARRAM1
|
||||
* @brief ADC1 Parity RAM Pointer
|
||||
*
|
||||
* This pointer is used by the ADC driver to access the ADC1 Parity RAM.
|
||||
*/
|
||||
#define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
|
||||
|
||||
/** @def adcPARRAM2
|
||||
* @brief ADC2 Parity RAM Pointer
|
||||
*
|
||||
* This pointer is used by the ADC driver to access the ADC2 Parity RAM.
|
||||
*/
|
||||
#define adcPARRAM2 (*(volatile uint32 *)(0xFF3A0000U + 0x1000U))
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,178 @@
|
||||
/** @file reg_can.h
|
||||
* @brief CAN Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the CAN driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_CAN_H__
|
||||
#define __REG_CAN_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Can Register Frame Definition */
|
||||
/** @struct canBase
|
||||
* @brief CAN Register Frame Definition
|
||||
*
|
||||
* This type is used to access the CAN Registers.
|
||||
*/
|
||||
/** @typedef canBASE_t
|
||||
* @brief CAN Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the CAN Registers.
|
||||
*/
|
||||
typedef volatile struct canBase
|
||||
{
|
||||
uint32 CTL; /**< 0x0000: Control Register */
|
||||
uint32 ES; /**< 0x0004: Error and Status Register */
|
||||
uint32 EERC; /**< 0x0008: Error Counter Register */
|
||||
uint32 BTR; /**< 0x000C: Bit Timing Register */
|
||||
uint32 INT; /**< 0x0010: Interrupt Register */
|
||||
uint32 TEST; /**< 0x0014: Test Register */
|
||||
uint32 rsvd1; /**< 0x0018: Reserved */
|
||||
uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */
|
||||
uint32 REL; /**< 0x0020: Core Release Register */
|
||||
uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */
|
||||
uint32 ECCDIADSTAT; /**< 0x0028: ECC Diagnostic Status Register */
|
||||
uint32 rsvd2[21]; /**< 0x002C: Reserved */
|
||||
uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */
|
||||
uint32 TXRQX; /**< 0x0084: Transmission Request X Register */
|
||||
uint32 TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */
|
||||
uint32 NWDATX; /**< 0x0098: New Data X Register */
|
||||
uint32 NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */
|
||||
uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */
|
||||
uint32 INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */
|
||||
uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */
|
||||
uint32 MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */
|
||||
uint32 rsvd3; /**< 0x00D4: Reserved */
|
||||
uint32 INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
|
||||
uint32 rsvd4[6]; /**< 0x00E8: Reserved */
|
||||
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
|
||||
uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
|
||||
uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
|
||||
uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
|
||||
uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
|
||||
#else
|
||||
uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
|
||||
uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
|
||||
uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
|
||||
uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
|
||||
#endif
|
||||
uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */
|
||||
uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */
|
||||
uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */
|
||||
uint8 IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */
|
||||
uint32 rsvd5[2]; /**< 0x0118: Reserved */
|
||||
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
|
||||
uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */
|
||||
uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
|
||||
uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
|
||||
uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
|
||||
#else
|
||||
uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
|
||||
uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
|
||||
uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
|
||||
uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */
|
||||
#endif
|
||||
uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */
|
||||
uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */
|
||||
uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */
|
||||
uint8 IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */
|
||||
uint32 rsvd6[2]; /**< 0x0138: Reserved */
|
||||
uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */
|
||||
uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */
|
||||
uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */
|
||||
uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */
|
||||
uint8 IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */
|
||||
uint32 rsvd7[2]; /**< 0x0158: Reserved */
|
||||
uint32 IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */
|
||||
uint32 rsvd8[28]; /**< 0x0170: Reserved */
|
||||
uint32 TIOC; /**< 0x01E0: TX IO Control Register */
|
||||
uint32 RIOC; /**< 0x01E4: RX IO Control Register */
|
||||
} canBASE_t;
|
||||
|
||||
|
||||
/** @def canREG1
|
||||
* @brief CAN1 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN1 registers.
|
||||
*/
|
||||
#define canREG1 ((canBASE_t *)0xFFF7DC00U)
|
||||
|
||||
/** @def canREG2
|
||||
* @brief CAN2 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN2 registers.
|
||||
*/
|
||||
#define canREG2 ((canBASE_t *)0xFFF7DE00U)
|
||||
|
||||
/** @def canREG3
|
||||
* @brief CAN3 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN3 registers.
|
||||
*/
|
||||
#define canREG3 ((canBASE_t *)0xFFF7E000U)
|
||||
|
||||
/** @def canRAM1
|
||||
* @brief CAN1 Mailbox RAM Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN1 RAM.
|
||||
*/
|
||||
#define canRAM1 (*(volatile uint32 *)0xFF1E0000U)
|
||||
|
||||
/** @def canRAM2
|
||||
* @brief CAN2 Mailbox RAM Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN2 RAM.
|
||||
*/
|
||||
#define canRAM2 (*(volatile uint32 *)0xFF1C0000U)
|
||||
|
||||
/** @def canRAM3
|
||||
* @brief CAN3 Mailbox RAM Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN3 RAM.
|
||||
*/
|
||||
#define canRAM3 (*(volatile uint32 *)0xFF1A0000U)
|
||||
|
||||
/** @def canPARRAM1
|
||||
* @brief CAN1 Mailbox Parity RAM Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN1 Parity RAM
|
||||
* for testing RAM parity error detect logic.
|
||||
*/
|
||||
#define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U))
|
||||
|
||||
/** @def canPARRAM2
|
||||
* @brief CAN2 Mailbox Parity RAM Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN2 Parity RAM
|
||||
* for testing RAM parity error detect logic.
|
||||
*/
|
||||
#define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U))
|
||||
|
||||
/** @def canPARRAM3
|
||||
* @brief CAN3 Mailbox Parity RAM Pointer
|
||||
*
|
||||
* This pointer is used by the CAN driver to access the CAN3 Parity RAM
|
||||
* for testing RAM parity error detect logic.
|
||||
*/
|
||||
#define canPARRAM3 (*(volatile uint32 *)(0xFF1A0000U + 0x10U))
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,96 @@
|
||||
/** @file reg_crc.h
|
||||
* @brief CRC Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the CRC driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_CRC_H__
|
||||
#define __REG_CRC_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Crc Register Frame Definition */
|
||||
/** @struct crcBase
|
||||
* @brief CRC Register Frame Definition
|
||||
*
|
||||
* This type is used to access the CRC Registers.
|
||||
*/
|
||||
/** @typedef crcBASE_t
|
||||
* @brief CRC Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the CRC Registers.
|
||||
*/
|
||||
typedef volatile struct crcBase
|
||||
{
|
||||
uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/
|
||||
uint32 rsvd1; /**< 0x0004: reserved >**/
|
||||
uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/
|
||||
uint32 rsvd2; /**< 0x000C: reserved >**/
|
||||
uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/
|
||||
uint32 rsvd3; /**< 0x0014: reserved >**/
|
||||
uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/
|
||||
uint32 rsvd4; /**< 0x001C: reserved >**/
|
||||
uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/
|
||||
uint32 rsvd5; /**< 0x0024: reserved >**/
|
||||
uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/
|
||||
uint32 rsvd6; /**< 0x002C: reserved >**/
|
||||
uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/
|
||||
uint32 rsvd7; /**< 0x0034: reserved >**/
|
||||
uint32 BUSY; /**< 0x0038: CRC Busy Register >**/
|
||||
uint32 rsvd8; /**< 0x003C: reserved >**/
|
||||
uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/
|
||||
uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/
|
||||
uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/
|
||||
uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
|
||||
uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
|
||||
uint32 rsvd9[3]; /**< 0x0054: reserved >**/
|
||||
uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/
|
||||
uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/
|
||||
uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/
|
||||
uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/
|
||||
uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/
|
||||
uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/
|
||||
uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/
|
||||
uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/
|
||||
uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
|
||||
uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/
|
||||
uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/
|
||||
uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
|
||||
uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
|
||||
uint32 rsvd10[3]; /**< 0x0094: reserved >**/
|
||||
uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/
|
||||
uint32 PSA_SIGREGH2; /**< 0x00A8: Channel 2 PSA signature high register >**/
|
||||
uint32 REGL2; /**< 0x00AC: Channel 2 CRC value low register >**/
|
||||
uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/
|
||||
uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/
|
||||
uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/
|
||||
uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/
|
||||
uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/
|
||||
}crcBASE_t;
|
||||
|
||||
/** @def crcREG
|
||||
* @brief CRC Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the CRC driver to access the CRC registers.
|
||||
*/
|
||||
#define crcREG ((crcBASE_t *)0xFE000000U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,72 @@
|
||||
/** @file reg_dcc.h
|
||||
* @brief DCC Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the DCC driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_DCC_H__
|
||||
#define __REG_DCC_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Dcc Register Frame Definition */
|
||||
/** @struct dccBase
|
||||
* @brief DCC Base Register Definition
|
||||
*
|
||||
* This structure is used to access the DCC module registers.
|
||||
*/
|
||||
/** @typedef dccBASE_t
|
||||
* @brief DCC Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the DCC Registers.
|
||||
*/
|
||||
typedef volatile struct dccBase
|
||||
{
|
||||
uint32 GCTRL; /**< 0x0000: DCC Control Register */
|
||||
uint32 REV; /**< 0x0004: DCC Revision Id Register */
|
||||
uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */
|
||||
uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */
|
||||
uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */
|
||||
uint32 STAT; /**< 0x0014: DCC Status Register */
|
||||
uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */
|
||||
uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */
|
||||
uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */
|
||||
uint32 CLKSRC1; /**< 0x0024: DCC Counter1 Clock Source Selection Register */
|
||||
uint32 CLKSRC0; /**< 0x0028: DCC Counter0 Clock Source Selection Register */
|
||||
} dccBASE_t;
|
||||
|
||||
|
||||
/** @def dccREG1
|
||||
* @brief DCC1 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the DCC driver to access the dcc2 module registers.
|
||||
*/
|
||||
#define dccREG1 ((dccBASE_t *)0xFFFFEC00U)
|
||||
|
||||
|
||||
/** @def dccREG2
|
||||
* @brief DCC2 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the DCC driver to access the dcc2 module registers.
|
||||
*/
|
||||
#define dccREG2 ((dccBASE_t *)0xFFFFF400U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,146 @@
|
||||
/** @file reg_dma.h
|
||||
* @brief DMA Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the DMA driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_DMA_H__
|
||||
#define __REG_DMA_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* DMA Register Frame Definition */
|
||||
/** @struct dmaBase
|
||||
* @brief DMA Register Frame Definition
|
||||
*
|
||||
* This type is used to access the DMA Registers.
|
||||
*/
|
||||
/** @struct dmaBASE_t
|
||||
* @brief DMA Register Definition
|
||||
*
|
||||
* This structure is used to access the DMA module egisters.
|
||||
*/
|
||||
typedef volatile struct dmaBase
|
||||
{
|
||||
|
||||
uint32 GCTRL; /**< 0x0000: Global Control Register */
|
||||
uint32 PEND; /**< 0x0004: Channel Pending Register */
|
||||
uint32 FBREG; /**< 0x0008: Fall Back Register */
|
||||
uint32 DMASTAT; /**< 0x000C: Status Register */
|
||||
uint32 rsvd1; /**< 0x0010: Reserved */
|
||||
uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */
|
||||
uint32 rsvd2; /**< 0x0018: Reserved */
|
||||
uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */
|
||||
uint32 rsvd3; /**< 0x0020: Reserved */
|
||||
uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */
|
||||
uint32 rsvd4; /**< 0x0028: Reserved */
|
||||
uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */
|
||||
uint32 rsvd5; /**< 0x0030: Reserved */
|
||||
uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */
|
||||
uint32 rsvd6; /**< 0x0038: Reserved */
|
||||
uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */
|
||||
uint32 rsvd7; /**< 0x0040: Reserved */
|
||||
uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */
|
||||
uint32 rsvd8; /**< 0x0048: Reserved */
|
||||
uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Set */
|
||||
uint32 rsvd9; /**< 0x0050: Reserved */
|
||||
uint32 DREQASI[8U];/**< 0x0054 - 0x70: DMA Request Assignment Register */
|
||||
uint32 rsvd10[8U];/**< 0x0074 - 0x90: Reserved */
|
||||
uint32 PAR[4U]; /**< 0x0094 - 0xA0: Port Assignment Register */
|
||||
uint32 rsvd11[4U];/**< 0x00A4 - 0xB0: Reserved */
|
||||
uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */
|
||||
uint32 rsvd12; /**< 0x00B8: Reserved */
|
||||
uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */
|
||||
uint32 rsvd13; /**< 0x00C0: Reserved */
|
||||
uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */
|
||||
uint32 rsvd14; /**< 0x00C8: Reserved */
|
||||
uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */
|
||||
uint32 rsvd15; /**< 0x00D0: Reserved */
|
||||
uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */
|
||||
uint32 rsvd16; /**< 0x00D8: Reserved */
|
||||
uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */
|
||||
uint32 rsvd17; /**< 0x00E0: Reserved */
|
||||
uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */
|
||||
uint32 rsvd18; /**< 0x00E8: Reserved */
|
||||
uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */
|
||||
uint32 rsvd19; /**< 0x00F0: Reserved */
|
||||
uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */
|
||||
uint32 rsvd20; /**< 0x00F8: Reserved */
|
||||
uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */
|
||||
uint32 rsvd21; /**< 0x0100: Reserved */
|
||||
uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */
|
||||
uint32 rsvd22; /**< 0x0108: Reserved */
|
||||
uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */
|
||||
uint32 rsvd23; /**< 0x0110: Reserved */
|
||||
uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */
|
||||
uint32 rsvd24; /**< 0x0118: Reserved */
|
||||
uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */
|
||||
uint32 rsvd25; /**< 0x0120: Reserved */
|
||||
uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */
|
||||
uint32 rsvd26; /**< 0x0128: Reserved */
|
||||
uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */
|
||||
uint32 rsvd27; /**< 0x0130: Reserved */
|
||||
uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */
|
||||
uint32 rsvd28; /**< 0x0138: Reserved */
|
||||
uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */
|
||||
uint32 rsvd29; /**< 0x0140: Reserved */
|
||||
uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */
|
||||
uint32 rsvd30; /**< 0x0148: Reserved */
|
||||
uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */
|
||||
uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */
|
||||
uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */
|
||||
uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */
|
||||
uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */
|
||||
uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */
|
||||
uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */
|
||||
uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */
|
||||
uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */
|
||||
uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */
|
||||
uint32 rsvd31; /**< 0x0174: Reserved */
|
||||
uint32 PTCRL; /**< 0x0178: Port Control Register */
|
||||
uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */
|
||||
uint32 DCTRL; /**< 0x0180: Debug Control */
|
||||
uint32 WPR; /**< 0x0184: Watch Point Register */
|
||||
uint32 WMR; /**< 0x0188: Watch Mask Register */
|
||||
uint32 PAACSADDR; /**< 0x018C: */
|
||||
uint32 PAACDADDR; /**< 0x0190: */
|
||||
uint32 PAACTC; /**< 0x0194: */
|
||||
uint32 PBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */
|
||||
uint32 PBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */
|
||||
uint32 PBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */
|
||||
uint32 rsvd32; /**< 0x01A4: Reserved */
|
||||
uint32 DMAPCR; /**< 0x01A8: Parity Control Register */
|
||||
uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */
|
||||
uint32 DMAMPCTRL; /**< 0x01B0: DMA Memory Protection Control Register */
|
||||
uint32 DMAMPST; /**< 0x01B4: DMA Memory Protection Status Register */
|
||||
struct
|
||||
{
|
||||
uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register */
|
||||
uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register */
|
||||
}DMAMPR[4U];
|
||||
} dmaBASE_t;
|
||||
|
||||
|
||||
/** @def dmaREG
|
||||
* @brief DMA1 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the DMA driver to access the DMA module registers.
|
||||
*/
|
||||
#define dmaREG ((dmaBASE_t *)0xFFFFF000U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,99 @@
|
||||
/** @file reg_dmm.h
|
||||
* @brief DMM Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the DMM driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_DMM_H__
|
||||
#define __REG_DMM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Dmm Register Frame Definition */
|
||||
/** @struct dmmBase
|
||||
* @brief DMM Base Register Definition
|
||||
*
|
||||
* This structure is used to access the DMM module registers.
|
||||
*/
|
||||
/** @typedef dmmBASE_t
|
||||
* @brief DMM Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the DMM Registers.
|
||||
*/
|
||||
|
||||
typedef volatile struct dmmBase
|
||||
{
|
||||
uint32 GLBCTRL; /**< 0x0000: Global control register 0 */
|
||||
uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */
|
||||
uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */
|
||||
uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */
|
||||
uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */
|
||||
uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */
|
||||
uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */
|
||||
uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */
|
||||
uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */
|
||||
uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */
|
||||
uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */
|
||||
uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */
|
||||
uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */
|
||||
uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */
|
||||
uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */
|
||||
uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */
|
||||
uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */
|
||||
uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */
|
||||
uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */
|
||||
uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */
|
||||
uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */
|
||||
uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */
|
||||
uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */
|
||||
uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */
|
||||
uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */
|
||||
uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */
|
||||
uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */
|
||||
uint32 PC0; /**< 0x006C: DMM Pin Control 0 */
|
||||
uint32 PC1; /**< 0x0070: DMM Pin Control 1 */
|
||||
uint32 PC2; /**< 0x0074: DMM Pin Control 2 */
|
||||
uint32 PC3; /**< 0x0078: DMM Pin Control 3 */
|
||||
uint32 PC4; /**< 0x007C: DMM Pin Control 4 */
|
||||
uint32 PC5; /**< 0x0080: DMM Pin Control 5 */
|
||||
uint32 PC6; /**< 0x0084: DMM Pin Control 6 */
|
||||
uint32 PC7; /**< 0x0088: DMM Pin Control 7 */
|
||||
uint32 PC8; /**< 0x008C: DMM Pin Control 8 */
|
||||
} dmmBASE_t;
|
||||
|
||||
|
||||
/** @def dmmREG
|
||||
* @brief DMM Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the DMM driver to access the DMM module registers.
|
||||
*/
|
||||
#define dmmREG ((dmmBASE_t *)0xFFFFF700U)
|
||||
|
||||
/** @def dmmPORT
|
||||
* @brief DMM Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of DMM
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define dmmPORT ((gioPORT_t *)0xFFFFF738U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
/** @file reg_efc.h
|
||||
* @brief EFC Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_EFC_H__
|
||||
#define __REG_EFC_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Efc Register Frame Definition */
|
||||
/** @struct efcBase
|
||||
* @brief Efc Register Frame Definition
|
||||
*
|
||||
* This type is used to access the Efc Registers.
|
||||
*/
|
||||
/** @typedef efcBASE_t
|
||||
* @brief Efc Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the Efc Registers.
|
||||
*/
|
||||
typedef volatile struct efcBase
|
||||
{
|
||||
uint32 INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */
|
||||
uint32 ADDRESS; /* 0x4 ADDRESS REGISTER */
|
||||
uint32 DATA_UPPER; /* 0x8 DATA UPPER REGISTER */
|
||||
uint32 DATA_LOWER; /* 0xc DATA LOWER REGISTER */
|
||||
uint32 SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */
|
||||
uint32 SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */
|
||||
uint32 ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */
|
||||
uint32 BOUNDARY; /* 0x1C BOUNDARY REGISTER */
|
||||
uint32 KEY_FLAG; /* 0x20 KEY FLAG REGISTER */
|
||||
uint32 KEY; /* 0x24 KEY REGISTER */
|
||||
uint32 rsvd1; /* 0x28 RESERVED */
|
||||
uint32 PINS; /* 0x2C PINS REGISTER */
|
||||
uint32 CRA; /* 0x30 CRA */
|
||||
uint32 READ; /* 0x34 READ REGISTER */
|
||||
uint32 PROGRAMME; /* 0x38 PROGRAMME REGISTER */
|
||||
uint32 ERROR; /* 0x3C ERROR STATUS REGISTER */
|
||||
uint32 SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */
|
||||
uint32 TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */
|
||||
uint32 SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */
|
||||
uint32 SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */
|
||||
} efcBASE_t;
|
||||
|
||||
#define efcREG ((efcBASE_t *)0xFFF8C000U)
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,60 @@
|
||||
/** @file reg_emif.h
|
||||
* @brief EMIF Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the EMIF driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_EMIF_H__
|
||||
#define __REG_EMIF_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Emif Register Frame Definition */
|
||||
/** @struct emifBASE_t
|
||||
* @brief emifBASE Register Definition
|
||||
*
|
||||
* This structure is used to access the EMIF module registers.
|
||||
*/
|
||||
typedef volatile struct emifBase
|
||||
{
|
||||
uint32 MIDR; /**< 0x0000 Module ID Register */
|
||||
uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/
|
||||
uint32 SDCR; /**< 0x0008 SDRAM configuration register */
|
||||
uint32 SDRCR ; /**< 0x000C Set Interrupt Enable Register */
|
||||
uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */
|
||||
uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */
|
||||
uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */
|
||||
uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */
|
||||
uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */
|
||||
uint32 dummy1[6]; /** reserved **/
|
||||
uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */
|
||||
uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/
|
||||
uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */
|
||||
uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */
|
||||
uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */
|
||||
uint32 dummy2[6]; /** reserved **/
|
||||
uint32 PMCR; /**< 0x0068 Page Mode Control Register*/
|
||||
|
||||
} emifBASE_t;
|
||||
|
||||
#define emifREG ((emifBASE_t *)0xFCFFE800U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,74 @@
|
||||
/** @file reg_esm.h
|
||||
* @brief ESM Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the ESM driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_ESM_H__
|
||||
#define __REG_ESM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Esm Register Frame Definition */
|
||||
/** @struct esmBase
|
||||
* @brief Esm Register Frame Definition
|
||||
*
|
||||
* This type is used to access the Esm Registers.
|
||||
*/
|
||||
/** @typedef esmBASE_t
|
||||
* @brief Esm Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the Esm Registers.
|
||||
*/
|
||||
typedef volatile struct esmBase
|
||||
{
|
||||
uint32 EPENASET1; /* 0x0000 */
|
||||
uint32 EPENACLR1; /* 0x0004 */
|
||||
uint32 INTENASET1; /* 0x0008 */
|
||||
uint32 INTENACLR1; /* 0x000C */
|
||||
uint32 INTLVLSET1; /* 0x0010 */
|
||||
uint32 INTLVLCLR1; /* 0x0014 */
|
||||
uint32 ESTATUS1[3U]; /* 0x0018, 0x001C, 0x0020 */
|
||||
uint32 EPSTATUS; /* 0x0024 */
|
||||
uint32 INTOFFH; /* 0x0028 */
|
||||
uint32 INTOFFL; /* 0x002C */
|
||||
uint32 LTC; /* 0x0030 */
|
||||
uint32 LTCPRELOAD; /* 0x0034 */
|
||||
uint32 KEY; /* 0x0038 */
|
||||
uint32 ESTATUS2EMU; /* 0x003C */
|
||||
uint32 EPENASET4; /* 0x0040 */
|
||||
uint32 EPENACLR4; /* 0x0044 */
|
||||
uint32 INTENASET4; /* 0x0048 */
|
||||
uint32 INTENACLR4; /* 0x004C */
|
||||
uint32 INTLVLSET4; /* 0x0050 */
|
||||
uint32 INTLVLCLR4; /* 0x0054 */
|
||||
uint32 ESTATUS4[3U]; /* 0x0058, 0x005C, 0x0060 */
|
||||
uint32 ESTATUS5EMU; /* 0x0064 */
|
||||
} esmBASE_t;
|
||||
|
||||
/** @def esmREG
|
||||
* @brief Esm Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the Esm driver to access the Esm registers.
|
||||
*/
|
||||
#define esmREG ((esmBASE_t *)0xFFFFF500U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,111 @@
|
||||
/** @file reg_flash.h
|
||||
* @brief Flash Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_FLASH_H__
|
||||
#define __REG_FLASH_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* Flash Register Frame Definition */
|
||||
/** @struct flashWBase
|
||||
* @brief Flash Wrapper Register Frame Definition
|
||||
*
|
||||
* This type is used to access the Flash Wrapper Registers.
|
||||
*/
|
||||
/** @typedef flashWBASE_t
|
||||
* @brief Flash Wrapper Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the Flash Wrapper Registers.
|
||||
*/
|
||||
typedef volatile struct flashWBase
|
||||
{
|
||||
uint32 FRDCNTL; /* 0x0000 */
|
||||
uint32 FSPRD; /* 0x0004 */
|
||||
uint32 FEDACCTRL1; /* 0x0008 */
|
||||
uint32 FEDACCTRL2; /* 0x000C */
|
||||
uint32 FCORERRCNT; /* 0x0010 */
|
||||
uint32 FCORERRADD; /* 0x0014 */
|
||||
uint32 FCORERRPOS; /* 0x0018 */
|
||||
uint32 FEDACSTATUS; /* 0x001C */
|
||||
uint32 FUNCERRADD; /* 0x0020 */
|
||||
uint32 FEDACSDIS; /* 0x0024 */
|
||||
uint32 FPRIMADDTAG; /* 0x0028 */
|
||||
uint32 FREDUADDTAG; /* 0x002C */
|
||||
uint32 FBPROT; /* 0x0030 */
|
||||
uint32 FBSE; /* 0x0034 */
|
||||
uint32 FBBUSY; /* 0x0038 */
|
||||
uint32 FBAC; /* 0x003C */
|
||||
uint32 FBFALLBACK; /* 0x0040 */
|
||||
uint32 FBPRDY; /* 0x0044 */
|
||||
uint32 FPAC1; /* 0x0048 */
|
||||
uint32 FPAC2; /* 0x004C */
|
||||
uint32 FMAC; /* 0x0050 */
|
||||
uint32 FMSTAT; /* 0x0054 */
|
||||
uint32 FEMUDMSW; /* 0x0058 */
|
||||
uint32 FEMUDLSW; /* 0x005C */
|
||||
uint32 FEMUECC; /* 0x0060 */
|
||||
uint32 FLOCK; /* 0x0064 */
|
||||
uint32 FEMUADDR; /* 0x0068 */
|
||||
uint32 FDIAGCTRL; /* 0x006C */
|
||||
uint32 FRAWDATAH; /* 0x0070 */
|
||||
uint32 FRAWDATAL; /* 0x0074 */
|
||||
uint32 FRAWECC; /* 0x0078 */
|
||||
uint32 FPAROVR; /* 0x007C */
|
||||
uint32 FVREADCT; /* 0x0080 */
|
||||
uint32 FVHVCT1; /* 0x0084 */
|
||||
uint32 FVHVCT2; /* 0x0088 */
|
||||
uint32 FVNVCT; /* 0x008C */
|
||||
uint32 FVPPCT; /* 0x0090 */
|
||||
uint32 FVWLCT; /* 0x0094 */
|
||||
uint32 FEFUSE; /* 0x0098 */
|
||||
uint32 rsvd1[9U]; /* 0x009C */
|
||||
uint32 FEDACSDIS2; /* 0x00C0 */
|
||||
uint32 rsvd2[15U]; /* 0x00C4 */
|
||||
uint32 FBSTROBES; /* 0x0100 */
|
||||
uint32 FPSTROBES; /* 0x0104 */
|
||||
uint32 FBMODE; /* 0x0108 */
|
||||
uint32 FTCR; /* 0x010C */
|
||||
uint32 FADDR; /* 0x0110 */
|
||||
uint32 FWRITE; /* 0x0114 */
|
||||
uint32 FCBITSEL; /* 0x0118 */
|
||||
uint32 FTCTRL; /* 0x011C */
|
||||
uint32 FWPWRITE0; /* 0x0120 */
|
||||
uint32 FWPWRITE1; /* 0x0124 */
|
||||
uint32 FWPWRITE2; /* 0x0128 */
|
||||
uint32 FWPWRITE3; /* 0x012C */
|
||||
uint32 FWPWRITE4; /* 0x0130 */
|
||||
uint32 rsvd3[85U]; /* 0x0134 */
|
||||
uint32 FSMWRENA; /* 0x0288 */
|
||||
uint32 rsvd4[6U]; /* 0x028C */
|
||||
uint32 FSMSECTOR; /* 0x02A4 */
|
||||
uint32 rsvd5[4U]; /* 0x02A8 */
|
||||
uint32 EEPROMCONFIG;/* 0x02B8 */
|
||||
uint32 rsvd6[19U]; /* 0x02BC */
|
||||
uint32 EECTRL1; /* 0x0308 */
|
||||
uint32 EECTRL2; /* 0x030C */
|
||||
uint32 EECORRERRCNT;/* 0x0310 */
|
||||
uint32 EECORRERRADD;/* 0x0314 */
|
||||
uint32 EECORRERRPOS;/* 0x0318 */
|
||||
uint32 EESTATUS; /* 0x031C */
|
||||
uint32 EEUNCERRADD; /* 0x0320 */
|
||||
} flashWBASE_t;
|
||||
|
||||
/** @def flashWREG
|
||||
* @brief Flash Wrapper Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the system driver to access the flash wrapper registers.
|
||||
*/
|
||||
#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,99 @@
|
||||
/** @file reg_gio.h
|
||||
* @brief GIO Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the GIO driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_GIO_H__
|
||||
#define __REG_GIO_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Gio Register Frame Definition */
|
||||
/** @struct gioBase
|
||||
* @brief GIO Base Register Definition
|
||||
*
|
||||
* This structure is used to access the GIO module registers.
|
||||
*/
|
||||
/** @typedef gioBASE_t
|
||||
* @brief GIO Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the GIO Registers.
|
||||
*/
|
||||
typedef volatile struct gioBase
|
||||
{
|
||||
uint32 GCR0; /**< 0x0000: Global Control Register */
|
||||
uint32 PWDN; /**< 0x0004: Power Down Register */
|
||||
uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/
|
||||
uint32 POL; /**< 0x000C: Interrupt Polarity Register */
|
||||
uint32 INTENASET; /**< 0x0010: Interrupt Enable Set Register */
|
||||
uint32 INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */
|
||||
uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */
|
||||
uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */
|
||||
uint32 FLG; /**< 0x0020: Interrupt Flag Register */
|
||||
uint32 OFFSET0; /**< 0x0024: Interrupt Offset A Register */
|
||||
uint32 OFFSET1; /**< 0x0028: Interrupt Offset B Register */
|
||||
} gioBASE_t;
|
||||
|
||||
|
||||
/** @struct gioPort
|
||||
* @brief GIO Port Register Definition
|
||||
*/
|
||||
/** @typedef gioPORT_t
|
||||
* @brief GIO Port Register Type Definition
|
||||
*
|
||||
* This type is used to access the GIO Port Registers.
|
||||
*/
|
||||
typedef volatile struct gioPort
|
||||
{
|
||||
uint32 DIR; /**< 0x0000: Data Direction Register */
|
||||
uint32 DIN; /**< 0x0004: Data Input Register */
|
||||
uint32 DOUT; /**< 0x0008: Data Output Register */
|
||||
uint32 DSET; /**< 0x000C: Data Output Set Register */
|
||||
uint32 DCLR; /**< 0x0010: Data Output Clear Register */
|
||||
uint32 PDR; /**< 0x0014: Open Drain Register */
|
||||
uint32 PULDIS; /**< 0x0018: Pullup Disable Register */
|
||||
uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */
|
||||
} gioPORT_t;
|
||||
|
||||
|
||||
/** @def gioREG
|
||||
* @brief GIO Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the GIO driver to access the gio module registers.
|
||||
*/
|
||||
#define gioREG ((gioBASE_t *)0xFFF7BC00U)
|
||||
|
||||
/** @def gioPORTA
|
||||
* @brief GIO Port (A) Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access PORTA
|
||||
*/
|
||||
#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
|
||||
|
||||
/** @def gioPORTB
|
||||
* @brief GIO Port (B) Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access PORTB
|
||||
*/
|
||||
#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,152 @@
|
||||
/** @file reg_het.h
|
||||
* @brief HET Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the HET driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_HET_H__
|
||||
#define __REG_HET_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Het Register Frame Definition */
|
||||
/** @struct hetBase
|
||||
* @brief HET Base Register Definition
|
||||
*
|
||||
* This structure is used to access the HET module registers.
|
||||
*/
|
||||
/** @typedef hetBASE_t
|
||||
* @brief HET Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the HET Registers.
|
||||
*/
|
||||
|
||||
typedef volatile struct hetBase
|
||||
{
|
||||
uint32 GCR; /**< 0x0000: Global control register */
|
||||
uint32 PFR; /**< 0x0004: Prescale factor register */
|
||||
uint32 ADDR; /**< 0x0008: Current address register */
|
||||
uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */
|
||||
uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */
|
||||
uint32 INTENAS; /**< 0x0014: Interrupt enable set register */
|
||||
uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */
|
||||
uint32 EXC1; /**< 0x001C: Exception control register 1 */
|
||||
uint32 EXC2; /**< 0x0020: Exception control register 2 */
|
||||
uint32 PRY; /**< 0x0024: Interrupt priority register */
|
||||
uint32 FLG; /**< 0x0028: Interrupt flag register */
|
||||
uint32 AND; /**< 0x002C: AND share control register */
|
||||
uint32 rsvd1; /**< 0x0030: Reserved */
|
||||
uint32 HRSH; /**< 0x0034: High resolution share register */
|
||||
uint32 XOR; /**< 0x0038: XOR share register */
|
||||
uint32 REQENS; /**< 0x003C: Request enable set register */
|
||||
uint32 REQENC; /**< 0x0040: Request enable clear register */
|
||||
uint32 REQDS; /**< 0x0044: Request destination select register */
|
||||
uint32 rsvd2; /**< 0x0048: Reserved */
|
||||
uint32 DIR; /**< 0x004C: Direction register */
|
||||
uint32 DIN; /**< 0x0050: Data input register */
|
||||
uint32 DOUT; /**< 0x0054: Data output register */
|
||||
uint32 DSET; /**< 0x0058: Data output set register */
|
||||
uint32 DCLR; /**< 0x005C: Data output clear register */
|
||||
uint32 PDR; /**< 0x0060: Open drain register */
|
||||
uint32 PULDIS; /**< 0x0064: Pull disable register */
|
||||
uint32 PSL; /**< 0x0068: Pull select register */
|
||||
uint32 rsvd3; /**< 0x006C: Reserved */
|
||||
uint32 rsvd4; /**< 0x0070: Reserved */
|
||||
uint32 PCR; /**< 0x0074: Parity control register */
|
||||
uint32 PAR; /**< 0x0078: Parity address register */
|
||||
uint32 PPR; /**< 0x007C: Parity pin select register */
|
||||
uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */
|
||||
uint32 SFENA; /**< 0x0084: Suppression filter enable register */
|
||||
uint32 rsvd5; /**< 0x0088: Reserved */
|
||||
uint32 LBPSEL; /**< 0x008C: Loop back pair select register */
|
||||
uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */
|
||||
uint32 PINDIS; /**< 0x0094: Pin disable register */
|
||||
uint32 rsvd6; /**< 0x0098: Reserved */
|
||||
uint32 HWAPINSEL;/**< 0x009C: HWAG Pin select register */
|
||||
uint32 HWAGCR0; /**< 0x00A0: HWAG Global control register 0 */
|
||||
uint32 HWAGCR1; /**< 0x00A4: HWAG Global control register 1 */
|
||||
uint32 HWAGCR2; /**< 0x00A8: HWAG Global control register 2 */
|
||||
uint32 HWAENASET;/**< 0x00AC: HWAG Interrupt enable set register */
|
||||
uint32 HWAENACLR;/**< 0x00B0: HWAG Interrupt enable clear register*/
|
||||
uint32 HWALVLSET;/**< 0x00B4: HWAG Interrupt level set register */
|
||||
uint32 HWALVLCLR;/**< 0x00B8: HWAG Interrupt level clear register */
|
||||
uint32 HWAFLG; /**< 0x00BC: HWAG Interrupt flag register */
|
||||
uint32 HWAOFF1; /**< 0x00C0: HWAG Interrupt offset 1 register */
|
||||
uint32 HWAOFF2; /**< 0x00C4: HWAG Interrupt offset 2 register */
|
||||
uint32 HWAACNT; /**< 0x00C8: HWAG Angle value register */
|
||||
uint32 HWAPCNT1; /**< 0x00CC: HWAG Period value register 1 */
|
||||
uint32 HWAPCNT; /**< 0x00D0: HWAG Period value register */
|
||||
uint32 HWASTWD; /**< 0x00D4: HWAG Step width register */
|
||||
uint32 HWATHNB; /**< 0x00D8: HWAG Teeth number register */
|
||||
uint32 HWATHVL; /**< 0x00DC: HWAG Teeth Value register */
|
||||
uint32 HWAFIL; /**< 0x00E0: HWAG Filter register */
|
||||
uint32 rsvd7; /**< 0x00E4: Reserved */
|
||||
uint32 HWAFIL2; /**< 0x00E8: HWAG Second filter register */
|
||||
uint32 rsvd8; /**< 0x00EC: Reserved */
|
||||
uint32 HWAANGI; /**< 0x00F0: HWAG Angle increment register */
|
||||
} hetBASE_t;
|
||||
|
||||
|
||||
/** @def hetREG1
|
||||
* @brief HET Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the HET driver to access the het module registers.
|
||||
*/
|
||||
#define hetREG1 ((hetBASE_t *)0xFFF7B800U)
|
||||
|
||||
|
||||
/** @def hetPORT1
|
||||
* @brief HET GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of HET1
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define hetPORT1 ((gioPORT_t *)0xFFF7B84CU)
|
||||
|
||||
|
||||
/** @def hetREG2
|
||||
* @brief HET2 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the HET driver to access the het module registers.
|
||||
*/
|
||||
#define hetREG2 ((hetBASE_t *)0xFFF7B900U)
|
||||
|
||||
|
||||
/** @def hetPORT2
|
||||
* @brief HET2 GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of HET2
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define hetPORT2 ((gioPORT_t *)0xFFF7B94CU)
|
||||
|
||||
#define hetRAM1 ((hetRAMBASE_t *)0xFF460000U)
|
||||
|
||||
#define hetRAM2 ((hetRAMBASE_t *)0xFF440000U)
|
||||
|
||||
#define NHET1RAMPARLOC (*(volatile uint32 *)0xFF462000U)
|
||||
#define NHET1RAMLOC (*(volatile uint32 *)0xFF460000U)
|
||||
|
||||
#define NHET2RAMPARLOC (*(volatile uint32 *)0xFF442000U)
|
||||
#define NHET2RAMLOC (*(volatile uint32 *)0xFF440000U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,101 @@
|
||||
/** @file reg_htu.h
|
||||
* @brief HTU Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the HTU driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_HTU_H__
|
||||
#define __REG_HTU_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* htu Register Frame Definition */
|
||||
/** @struct htuBase
|
||||
* @brief HTU Base Register Definition
|
||||
*
|
||||
* This structure is used to access the HTU module registers.
|
||||
*/
|
||||
/** @typedef htuBASE_t
|
||||
* @brief HTU Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the HTU Registers.
|
||||
*/
|
||||
typedef volatile struct htuBase
|
||||
{
|
||||
uint32 GC; /** 0x00 */
|
||||
uint32 CPENA; /** 0x04 */
|
||||
uint32 BUSY0; /** 0x08 */
|
||||
uint32 BUSY1; /** 0x0C */
|
||||
uint32 BUSY2; /** 0x10 */
|
||||
uint32 BUSY3; /** 0x14 */
|
||||
uint32 ACPE; /** 0x18 */
|
||||
uint32 rsvd1; /** 0x1C */
|
||||
uint32 RLBECTRL; /** 0x20 */
|
||||
uint32 BFINTS; /** 0x24 */
|
||||
uint32 BFINTC; /** 0x28 */
|
||||
uint32 INTMAP; /** 0x2C */
|
||||
uint32 rsvd2; /** 0x30 */
|
||||
uint32 INTOFF0; /** 0x34 */
|
||||
uint32 INTOFF1; /** 0x38 */
|
||||
uint32 BIM; /** 0x3C */
|
||||
uint32 RLOSTFL; /** 0x40 */
|
||||
uint32 BFINTFL; /** 0x44 */
|
||||
uint32 BERINTFL; /** 0x48 */
|
||||
uint32 MP1S; /** 0x4C */
|
||||
uint32 MP1E; /** 0x50 */
|
||||
uint32 DCTRL; /** 0x54 */
|
||||
uint32 WPR; /** 0x58 */
|
||||
uint32 WMR; /** 0x5C */
|
||||
uint32 ID; /** 0x60 */
|
||||
uint32 PCR; /** 0x64 */
|
||||
uint32 PAR; /** 0x68 */
|
||||
uint32 rsvd3; /** 0x6C */
|
||||
uint32 MPCS; /** 0x70 */
|
||||
uint32 MP0S; /** 0x74 */
|
||||
uint32 MP0E; /** 0x78 */
|
||||
} htuBASE_t;
|
||||
|
||||
typedef volatile struct htudcp
|
||||
{
|
||||
uint32 IFADDRA;
|
||||
uint32 IFADDRB;
|
||||
uint32 IHADDRCT;
|
||||
uint32 ITCOUNT;
|
||||
} htudcp_t;
|
||||
|
||||
typedef volatile struct htucdcp
|
||||
{
|
||||
uint32 CFADDRA;
|
||||
uint32 CFADDRB;
|
||||
uint32 CFCOUNT;
|
||||
uint32 rsvd4;
|
||||
} htucdcp_t;
|
||||
|
||||
#define htuREG1 ((htuBASE_t *)0xFFF7A400U)
|
||||
#define htuREG2 ((htuBASE_t *)0xFFF7A500U)
|
||||
|
||||
#define htuDCP1 ((htudcp_t *)0xFF4E0000U)
|
||||
#define htuDCP2 ((htudcp_t *)0xFF4C0000U)
|
||||
|
||||
#define htuCDCP1 ((htucdcp_t *)0xFF4E0100U)
|
||||
#define htuCDCP2 ((htucdcp_t *)0xFF4C0100U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,94 @@
|
||||
/** @file reg_i2c.h
|
||||
* @brief I2C Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the I2C driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_I2C_H__
|
||||
#define __REG_I2C_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* I2c Register Frame Definition */
|
||||
/** @struct i2cBase
|
||||
* @brief I2C Base Register Definition
|
||||
*
|
||||
* This structure is used to access the I2C module registers.
|
||||
*/
|
||||
/** @typedef i2cBASE_t
|
||||
* @brief I2C Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the I2C Registers.
|
||||
*/
|
||||
typedef volatile struct i2cBase
|
||||
{
|
||||
|
||||
uint32 OAR; /**< 0x0000 I2C Own Address register */
|
||||
uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */
|
||||
uint32 STR; /**< 0x0008 I2C Interrupt Status register */
|
||||
uint32 CLKL; /**< 0x000C I2C Clock Divider Low register */
|
||||
uint32 CLKH; /**< 0x0010 I2C Clock Divider High register */
|
||||
uint32 CNT; /**< 0x0014 I2C Data Count register */
|
||||
uint32 DRR; /**< 0x0018 I2C Data Receive register */
|
||||
uint32 SAR; /**< 0x001C I2C Slave Address register */
|
||||
uint32 DXR; /**< 0x0020 I2C Data Transmit register */
|
||||
uint32 MDR; /**< 0x0024 I2C Mode register */
|
||||
uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */
|
||||
uint32 EMDR; /**< 0x002C I2C Extended Mode register */
|
||||
uint32 PSC; /**< 0x0030 I2C Prescaler register */
|
||||
uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */
|
||||
uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */
|
||||
uint32 DMAC; /**< 0x003C I2C DMA Control Register */
|
||||
uint32 rsvd1; /**< 0x0040 Reserved */
|
||||
uint32 rsvd2; /**< 0x0044 Reserved */
|
||||
uint32 FUN; /**< 0x0048 Pin Function Register */
|
||||
uint32 DIR; /**< 0x004C Pin Direction Register */
|
||||
uint32 DIN; /**< 0x0050 Pin Data In Register */
|
||||
uint32 DOUT; /**< 0x0054 Pin Data Out Register */
|
||||
uint32 SET; /**< 0x0058 Pin Data Set Register */
|
||||
uint32 CLR; /**< 0x005C Pin Data Clr Register */
|
||||
uint32 ODR; /**< 0x0060 Pin Open Drain Output Enable Register */
|
||||
uint32 PD; /**< 0x0064 Pin Pullup/Pulldown Disable Register */
|
||||
uint32 PSL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */
|
||||
} i2cBASE_t;
|
||||
|
||||
|
||||
/** @def i2cREG1
|
||||
* @brief I2C Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the I2C driver to access the I2C module registers.
|
||||
*/
|
||||
#define i2cREG1 ((i2cBASE_t *)0xFFF7D400U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/** @def i2cPORT1
|
||||
* @brief I2C GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of I2C
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define i2cPORT1 ((gioPORT_t *)0xFFF7D44CU)
|
||||
|
||||
/* USER CODE BEGIN (2) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,97 @@
|
||||
/** @file reg_lin.h
|
||||
* @brief LIN Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the LIN driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_LIN_H__
|
||||
#define __REG_LIN_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Lin Register Frame Definition */
|
||||
/** @struct linBase
|
||||
* @brief LIN Base Register Definition
|
||||
*
|
||||
* This structure is used to access the LIN module registers.
|
||||
*/
|
||||
/** @typedef linBASE_t
|
||||
* @brief LIN Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the LIN Registers.
|
||||
*/
|
||||
|
||||
typedef volatile struct linBase
|
||||
{
|
||||
uint32 GCR0; /**< 0x0000: Global control register 0 */
|
||||
uint32 GCR1; /**< 0x0004: Global control register 1 */
|
||||
uint32 GCR2; /**< 0x0008: Global control register 2 */
|
||||
uint32 SETINT; /**< 0x000C: Set interrupt enable register */
|
||||
uint32 CLRINT; /**< 0x0010: Clear interrupt enable register */
|
||||
uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */
|
||||
uint32 CLRINTLVL; /**< 0x0018: Set interrupt level register */
|
||||
uint32 FLR; /**< 0x001C: interrupt flag register */
|
||||
uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */
|
||||
uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */
|
||||
uint32 FORMAT; /**< 0x0028: Format Control Register */
|
||||
uint32 BRSR; /**< 0x002C: Baud rate selection register */
|
||||
uint32 ED; /**< 0x0030: Emulation register */
|
||||
uint32 RD; /**< 0x0034: Receive data register */
|
||||
uint32 TD; /**< 0x0038: Transmit data register */
|
||||
uint32 FUN; /**< 0x003C: Pin function register */
|
||||
uint32 DIR; /**< 0x0040: Pin direction register */
|
||||
uint32 DIN; /**< 0x0044: Pin data in register */
|
||||
uint32 DOUT; /**< 0x0048: Pin data out register */
|
||||
uint32 SET; /**< 0x004C: Pin data set register */
|
||||
uint32 CLR; /**< 0x0050: Pin data clr register */
|
||||
uint32 ODR; /**< 0x0054: Pin open drain output enable register */
|
||||
uint32 PD; /**< 0x0058: Pin pullup/pulldown disable register */
|
||||
uint32 PSL; /**< 0x005C: Pin pullup/pulldown selection register */
|
||||
uint32 COMP; /**< 0x0060: Compare register */
|
||||
uint8 RDx[8U]; /**< 0x0064-0x0068: RX buffer register */
|
||||
uint32 MASK; /**< 0x006C: Mask register */
|
||||
uint32 ID; /**< 0x0070: Identification Register */
|
||||
uint8 TDx[8U]; /**< 0x0074-0x0078: TX buffer register */
|
||||
uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */
|
||||
uint32 SL; /**< 0x0080: Pin slew rate register */
|
||||
uint32 rsvd1[3U]; /**< 0x0084: Reserved */
|
||||
uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */
|
||||
} linBASE_t;
|
||||
|
||||
|
||||
/** @def linREG
|
||||
* @brief LIN Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the LIN driver to access the lin module registers.
|
||||
*/
|
||||
#define linREG ((linBASE_t *)0xFFF7E400U)
|
||||
|
||||
|
||||
/** @def linPORT
|
||||
* @brief LIN GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of LIN
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define linPORT ((gioPORT_t *)0xFFF7E440U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,65 @@
|
||||
/** @file reg_pbist.h
|
||||
* @brief PBIST Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_PBIST_H__
|
||||
#define __REG_PBIST_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* PBIST Register Frame Definition */
|
||||
/** @struct pbistBase
|
||||
* @brief PBIST Base Register Definition
|
||||
*
|
||||
* This structure is used to access the PBIST module registers.
|
||||
*/
|
||||
/** @typedef pbistBASE_t
|
||||
* @brief PBIST Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the PBIST Registers.
|
||||
*/
|
||||
typedef volatile struct pbistBase
|
||||
{
|
||||
uint32 RAMT; /* 0x0160: RAM Configuration Register */
|
||||
uint32 DLR; /* 0x0164: Datalogger Register */
|
||||
uint32 rsvd1[6U]; /* 0x0168 */
|
||||
uint32 PACT; /* 0x0180: PBIST Activate Register */
|
||||
uint32 PBISTID; /* 0x0184: PBIST ID Register */
|
||||
uint32 OVER; /* 0x0188: Override Register */
|
||||
uint32 rsvd2; /* 0x018C */
|
||||
uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */
|
||||
uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */
|
||||
uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */
|
||||
uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */
|
||||
uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */
|
||||
uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */
|
||||
uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */
|
||||
uint32 rsvd3; /* 0x01AC */
|
||||
uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */
|
||||
uint32 rsvd4[3U]; /* 0x01B4 */
|
||||
uint32 ROM; /* 0x01C0: ROM Mask Register */
|
||||
uint32 ALGO; /* 0x01C4: Algorithm Mask Register */
|
||||
uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */
|
||||
uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */
|
||||
} pbistBASE_t;
|
||||
|
||||
#define pbistREG ((pbistBASE_t *)0xFFFFE560U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,80 @@
|
||||
/** @file reg_pcr.h
|
||||
* @brief PCR Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_PCR_H__
|
||||
#define __REG_PCR_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Pcr Register Frame Definition */
|
||||
/** @struct pcrBase
|
||||
* @brief Pcr Register Frame Definition
|
||||
*
|
||||
* This type is used to access the Pcr Registers.
|
||||
*/
|
||||
/** @typedef pcrBASE_t
|
||||
* @brief PCR Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the PCR Registers.
|
||||
*/
|
||||
typedef volatile struct pcrBase
|
||||
{
|
||||
uint32 PMPROTSET0; /* 0x0000 */
|
||||
uint32 PMPROTSET1; /* 0x0004 */
|
||||
uint32 rsvd1[2U]; /* 0x0008 */
|
||||
uint32 PMPROTCLR0; /* 0x0010 */
|
||||
uint32 PMPROTCLR1; /* 0x0014 */
|
||||
uint32 rsvd2[2U]; /* 0x0018 */
|
||||
uint32 PPROTSET0; /* 0x0020 */
|
||||
uint32 PPROTSET1; /* 0x0024 */
|
||||
uint32 PPROTSET2; /* 0x0028 */
|
||||
uint32 PPROTSET3; /* 0x002C */
|
||||
uint32 rsvd3[4U]; /* 0x0030 */
|
||||
uint32 PPROTCLR0; /* 0x0040 */
|
||||
uint32 PPROTCLR1; /* 0x0044 */
|
||||
uint32 PPROTCLR2; /* 0x0048 */
|
||||
uint32 PPROTCLR3; /* 0x004C */
|
||||
uint32 rsvd4[4U]; /* 0x0050 */
|
||||
uint32 PCSPWRDWNSET0; /* 0x0060 */
|
||||
uint32 PCSPWRDWNSET1; /* 0x0064 */
|
||||
uint32 rsvd5[2U]; /* 0x0068 */
|
||||
uint32 PCSPWRDWNCLR0; /* 0x0070 */
|
||||
uint32 PCSPWRDWNCLR1; /* 0x0074 */
|
||||
uint32 rsvd6[2U]; /* 0x0078 */
|
||||
uint32 PSPWRDWNSET0; /* 0x0080 */
|
||||
uint32 PSPWRDWNSET1; /* 0x0084 */
|
||||
uint32 PSPWRDWNSET2; /* 0x0088 */
|
||||
uint32 PSPWRDWNSET3; /* 0x008C */
|
||||
uint32 rsvd7[4U]; /* 0x0090 */
|
||||
uint32 PSPWRDWNCLR0; /* 0x00A0 */
|
||||
uint32 PSPWRDWNCLR1; /* 0x00A4 */
|
||||
uint32 PSPWRDWNCLR2; /* 0x00A8 */
|
||||
uint32 PSPWRDWNCLR3; /* 0x00AC */
|
||||
} pcrBASE_t;
|
||||
|
||||
/** @def pcrREG
|
||||
* @brief Pcr Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the system driver to access the Pcr registers.
|
||||
*/
|
||||
#define pcrREG ((pcrBASE_t *)0xFFFFE000U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,129 @@
|
||||
/** @file reg_pinmux.h
|
||||
* @brief PINMUX Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the PINMUX driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_PINMUX_H__
|
||||
#define __REG_PINMUX_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* IOMM Revision and Boot Register */
|
||||
#define REVISION_REG (*(volatile uint32 *)0xFFFFEA00U)
|
||||
#define ENDIAN_REG (*(volatile uint32 *)0xFFFFEA20U)
|
||||
|
||||
/* IOMM Error and Fault Registers */
|
||||
/** @struct iommErrFault
|
||||
* @brief IOMM Error and Fault Register Definition
|
||||
*
|
||||
* This structure is used to access the IOMM Error and Fault registers.
|
||||
*/
|
||||
typedef volatile struct iommErrFault
|
||||
{
|
||||
uint32 ERR_RAW_STATUS_REG; /* Error Raw Status / Set Register */
|
||||
uint32 ERR_ENABLED_STATUS_REG; /* Error Enabled Status / Clear Register */
|
||||
uint32 ERR_ENABLE_REG; /* Error Signaling Enable Register */
|
||||
uint32 ERR_ENABLE_CLR_REG; /* Error Signaling Enable Clear Register */
|
||||
uint32 rsvd; /* Reserved */
|
||||
uint32 FAULT_ADDRESS_REG; /* Fault Address Register */
|
||||
uint32 FAULT_STATUS_REG; /* Fault Status Register */
|
||||
uint32 FAULT_CLEAR_REG; /* Fault Clear Register */
|
||||
} iommErrFault_t;
|
||||
/* Pinmux Register Frame Definition */
|
||||
/** @struct pinMuxKicker
|
||||
* @brief Pin Muxing Kicker Register Definition
|
||||
*
|
||||
* This structure is used to access the Pin Muxing Kicker registers.
|
||||
*/
|
||||
typedef volatile struct pinMuxKicker
|
||||
{
|
||||
uint32 KICKER0; /* kicker 0 register */
|
||||
uint32 KICKER1; /* kicker 1 register */
|
||||
} pinMuxKICKER_t;
|
||||
|
||||
/** @struct pinMuxBase
|
||||
* @brief PINMUX Register Definition
|
||||
*
|
||||
* This structure is used to access the PINMUX module registers.
|
||||
*/
|
||||
/** @typedef pinMuxBASE_t
|
||||
* @brief PINMUX Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the PINMUX Registers.
|
||||
*/
|
||||
typedef volatile struct pinMuxBase
|
||||
{
|
||||
uint32 PINMMR0; /**< 0xEB10 Pin Mux 0 register*/
|
||||
uint32 PINMMR1; /**< 0xEB14 Pin Mux 1 register*/
|
||||
uint32 PINMMR2; /**< 0xEB18 Pin Mux 2 register*/
|
||||
uint32 PINMMR3; /**< 0xEB1C Pin Mux 3 register*/
|
||||
uint32 PINMMR4; /**< 0xEB20 Pin Mux 4 register*/
|
||||
uint32 PINMMR5; /**< 0xEB24 Pin Mux 5 register*/
|
||||
uint32 PINMMR6; /**< 0xEB28 Pin Mux 6 register*/
|
||||
uint32 PINMMR7; /**< 0xEB2C Pin Mux 7 register*/
|
||||
uint32 PINMMR8; /**< 0xEB30 Pin Mux 8 register*/
|
||||
uint32 PINMMR9; /**< 0xEB34 Pin Mux 9 register*/
|
||||
uint32 PINMMR10; /**< 0xEB38 Pin Mux 10 register*/
|
||||
uint32 PINMMR11; /**< 0xEB3C Pin Mux 11 register*/
|
||||
uint32 PINMMR12; /**< 0xEB40 Pin Mux 12 register*/
|
||||
uint32 PINMMR13; /**< 0xEB44 Pin Mux 13 register*/
|
||||
uint32 PINMMR14; /**< 0xEB48 Pin Mux 14 register*/
|
||||
uint32 PINMMR15; /**< 0xEB4C Pin Mux 15 register*/
|
||||
uint32 PINMMR16; /**< 0xEB50 Pin Mux 16 register*/
|
||||
uint32 PINMMR17; /**< 0xEB54 Pin Mux 17 register*/
|
||||
uint32 PINMMR18; /**< 0xEB58 Pin Mux 18 register*/
|
||||
uint32 PINMMR19; /**< 0xEB5C Pin Mux 19 register*/
|
||||
uint32 PINMMR20; /**< 0xEB60 Pin Mux 20 register*/
|
||||
uint32 PINMMR21; /**< 0xEB64 Pin Mux 21 register*/
|
||||
uint32 PINMMR22; /**< 0xEB68 Pin Mux 22 register*/
|
||||
uint32 PINMMR23; /**< 0xEB6C Pin Mux 23 register*/
|
||||
uint32 PINMMR24; /**< 0xEB70 Pin Mux 24 register*/
|
||||
uint32 PINMMR25; /**< 0xEB74 Pin Mux 25 register*/
|
||||
uint32 PINMMR26; /**< 0xEB78 Pin Mux 26 register*/
|
||||
uint32 PINMMR27; /**< 0xEB7C Pin Mux 27 register*/
|
||||
uint32 PINMMR28; /**< 0xEB80 Pin Mux 28 register*/
|
||||
uint32 PINMMR29; /**< 0xEB84 Pin Mux 29 register*/
|
||||
uint32 PINMMR30; /**< 0xEB88 Pin Mux 30 register*/
|
||||
}pinMuxBASE_t;
|
||||
|
||||
|
||||
/** @def iommErrFaultReg
|
||||
* @brief IOMM Error Fault Register Frame Pointer
|
||||
*
|
||||
* This pointer is used to control IOMM Error and Fault across the device.
|
||||
*/
|
||||
#define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAEOU)
|
||||
|
||||
/** @def kickerReg
|
||||
* @brief Pin Muxing Kicker Register Frame Pointer
|
||||
*
|
||||
* This pointer is used to enable and disable muxing accross the device.
|
||||
*/
|
||||
#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U)
|
||||
|
||||
/** @def pinMuxReg
|
||||
* @brief Pin Muxing Control Register Frame Pointer
|
||||
*
|
||||
* This pointer is used to set the muxing registers accross the device.
|
||||
*/
|
||||
#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,78 @@
|
||||
/** @file reg_pmm.h
|
||||
* @brief PMM Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the PMM driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_PMM_H__
|
||||
#define __REG_PMM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Pmm Register Frame Definition */
|
||||
/** @struct pmmBase
|
||||
* @brief Pmm Register Frame Definition
|
||||
*
|
||||
* This type is used to access the Pmm Registers.
|
||||
*/
|
||||
/** @typedef pmmBase_t
|
||||
* @brief Pmm Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the Pmm Registers.
|
||||
*/
|
||||
typedef volatile struct pmmBase
|
||||
{
|
||||
uint32 LOGICPDPWRCTRL0; /**< 0x0000: Logic Power Domain Control Register 0 */
|
||||
uint32 rsvd1[3U]; /**< 0x0004: Reserved*/
|
||||
uint32 MEMPDPWRCTRL0; /**< 0x0010: Memory Power Domain Control Register 0 */
|
||||
uint32 rsvd2[3U]; /**< 0x0014: Reserved*/
|
||||
uint32 PDCLKDISREG; /**< 0x0020: Power Domain Clock Disable Register */
|
||||
uint32 PDCLKDISSETREG; /**< 0x0024: Power Domain Clock Disable Set Register */
|
||||
uint32 PDCLKDISCLRREG; /**< 0x0028: Power Domain Clock Disable Clear Register */
|
||||
uint32 rsvd3[5U]; /**< 0x002C: Reserved */
|
||||
uint32 LOGICPDPWRSTAT[4U]; /**< 0x0040, 0x0044, 0x0048, 0x004C: Logic Power Domain Power Status Register
|
||||
- 0: PD2
|
||||
- 1: PD3
|
||||
- 2: PD4
|
||||
- 3: PD5 */
|
||||
uint32 rsvd4[12U]; /**< 0x0050: Reserved*/
|
||||
uint32 MEMPDPWRSTAT[3U]; /**< 0x0080, 0x0084, 0x0088: Memory Power Domain Power Status Register
|
||||
- 0: RAM_PD1
|
||||
- 1: RAM_PD2
|
||||
- 2: RAM_PD3 */
|
||||
uint32 rsvd5[5U]; /**< 0x008C: Reserved */
|
||||
uint32 GLOBALCTRL1; /**< 0x00A0: Global Control Register 1 */
|
||||
uint32 rsvd6; /**< 0x00A4: Reserved */
|
||||
uint32 GLOBALSTAT; /**< 0x00A8: Global Status Register */
|
||||
uint32 PRCKEYREG; /**< 0x00AC: PSCON Diagnostic Compare Key Register */
|
||||
uint32 LPDDCSTAT1; /**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */
|
||||
uint32 LPDDCSTAT2; /**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */
|
||||
uint32 MPDDCSTAT1; /**< 0x00B8: Memory PD PSCON Diagnostic Compare Status Register 1 */
|
||||
uint32 MPDDCSTAT2; /**< 0x00BC: Memory PD PSCON Diagnostic Compare Status Register 2 */
|
||||
uint32 ISODIAGSTAT; /**< 0x00C0: Isolation Diagnostic Status Register */
|
||||
}pmmBase_t;
|
||||
|
||||
|
||||
/** @def pmmREG
|
||||
* @brief Pmm Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the Pmm driver to access the Pmm registers.
|
||||
*/
|
||||
#define pmmREG ((pmmBase_t *)0xFFFF0000U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,94 @@
|
||||
/** @file reg_pom.h
|
||||
* @brief POM Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the POM driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_POM_H__
|
||||
#define __REG_POM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Pom Register Frame Definition */
|
||||
/** @struct POMBase
|
||||
* @brief POM Register Frame Definition
|
||||
*
|
||||
* This structure is used to access the POM module registers(POM Register Map).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32 POMGLBCTRL_UL; /* 0x00 */
|
||||
uint32 POMREV_UL; /* 0x04 */
|
||||
uint32 POMCLKCTRL_UL; /* 0x08 */
|
||||
uint32 POMFLG_UL; /* 0x0C */
|
||||
struct
|
||||
{
|
||||
uint32 rsdv1;
|
||||
}RESERVED_REG[124U];
|
||||
struct /* 0x200 ... */
|
||||
{
|
||||
uint32 POMPROGSTART_UL;
|
||||
uint32 POMOVLSTART_UL;
|
||||
uint32 POMREGSIZE_UL;
|
||||
uint32 rsdv2;
|
||||
}POMRGNCONF_ST[32U];
|
||||
}pomBASE_t;
|
||||
|
||||
|
||||
/** @struct POM_CORESIGHT_ST
|
||||
* @brief POM_CORESIGHT_ST Register Definition
|
||||
*
|
||||
* This structure is used to access the POM module registers(POM CoreSight Registers ).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32 POMITCTRL_UL; /* 0xF00 */
|
||||
struct /* 0xF04 to 0xF9C */
|
||||
{
|
||||
uint32 Reserved_Reg_UL;
|
||||
}Reserved1_ST[39U];
|
||||
uint32 POMCLAIMSET_UL; /* 0xFA0 */
|
||||
uint32 POMCLAIMCLR_UL; /* 0xFA4 */
|
||||
uint32 rsvd1[2U]; /* 0xFA8 */
|
||||
uint32 POMLOCKACCESS_UL; /* 0xFB0 */
|
||||
uint32 POMLOCKSTATUS_UL; /* 0xFB4 */
|
||||
uint32 POMAUTHSTATUS_UL; /* 0xFB8 */
|
||||
uint32 rsvd2[3U]; /* 0xFBC */
|
||||
uint32 POMDEVID_UL; /* 0xFC8 */
|
||||
uint32 POMDEVTYPE_UL; /* 0xFCC */
|
||||
uint32 POMPERIPHERALID4_UL; /* 0xFD0 */
|
||||
uint32 POMPERIPHERALID5_UL; /* 0xFD4 */
|
||||
uint32 POMPERIPHERALID6_UL; /* 0xFD8 */
|
||||
uint32 POMPERIPHERALID7_UL; /* 0xFDC */
|
||||
uint32 POMPERIPHERALID0_UL; /* 0xFE0 */
|
||||
uint32 POMPERIPHERALID1_UL; /* 0xFE4 */
|
||||
uint32 POMPERIPHERALID2_UL; /* 0xFE8 */
|
||||
uint32 POMPERIPHERALID3_UL; /* 0xFEC */
|
||||
uint32 POMCOMPONENTID0_UL; /* 0xFF0 */
|
||||
uint32 POMCOMPONENTID1_UL; /* 0xFF4 */
|
||||
uint32 POMCOMPONENTID2_UL; /* 0xFF8 */
|
||||
uint32 POMCOMPONENTID3_UL; /* 0xFFC */
|
||||
}POM_CORESIGHT_ST;
|
||||
|
||||
|
||||
#define pomREG ((pomBASE_t *)0xFFA04000U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,96 @@
|
||||
/** @file reg_rti.h
|
||||
* @brief RTI Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the RTI driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_RTI_H__
|
||||
#define __REG_RTI_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Rti Register Frame Definition */
|
||||
/** @struct rtiBase
|
||||
* @brief RTI Register Frame Definition
|
||||
*
|
||||
* This type is used to access the RTI Registers.
|
||||
*/
|
||||
/** @typedef rtiBASE_t
|
||||
* @brief RTI Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the RTI Registers.
|
||||
*/
|
||||
typedef volatile struct rtiBase
|
||||
{
|
||||
uint32 GCTRL; /**< 0x0000: Global Control Register */
|
||||
uint32 TBCTRL; /**< 0x0004: Timebase Control Register */
|
||||
uint32 CAPCTRL; /**< 0x0008: Capture Control Register */
|
||||
uint32 COMPCTRL; /**< 0x000C: Compare Control Register */
|
||||
struct
|
||||
{
|
||||
uint32 FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */
|
||||
uint32 UCx; /**< 0x0014,0x0034: Up Counter x Register */
|
||||
uint32 CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */
|
||||
uint32 rsvd1; /**< 0x001C,0x003C: Reserved */
|
||||
uint32 CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */
|
||||
uint32 CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */
|
||||
uint32 rsvd2[2U]; /**< 0x0028,0x0048: Reserved */
|
||||
} CNT[2U]; /**< Counter x selection:
|
||||
- 0: Counter 0
|
||||
- 1: Counter 1 */
|
||||
struct
|
||||
{
|
||||
uint32 COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */
|
||||
uint32 UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */
|
||||
} CMP[4U]; /**< Compare x selection:
|
||||
- 0: Compare 0
|
||||
- 1: Compare 1
|
||||
- 2: Compare 2
|
||||
- 3: Compare 3 */
|
||||
uint32 TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */
|
||||
uint32 TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */
|
||||
uint32 rsvd3[2U]; /**< 0x0078: Reserved */
|
||||
uint32 SETINT; /**< 0x0080: Set/Status Interrupt Register */
|
||||
uint32 CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */
|
||||
uint32 INTFLAG; /**< 0x0088: Interrupt Flag Register */
|
||||
uint32 rsvd4; /**< 0x008C: Reserved */
|
||||
uint32 DWDCTRL; /**< 0x0090: Digital Watchdog Control Register */
|
||||
uint32 DWDPRLD; /**< 0x0094: Digital Watchdog Preload Register */
|
||||
uint32 WDSTATUS; /**< 0x0098: Watchdog Status Register */
|
||||
uint32 WDKEY; /**< 0x009C: Watchdog Key Register */
|
||||
uint32 DWDCNTR; /**< 0x00A0: Digital Watchdog Down Counter */
|
||||
uint32 WWDRXNCTRL; /**< 0x00A4: Digital Windowed Watchdog Reaction Control */
|
||||
uint32 WWDSIZECTRL; /**< 0x00A8: Digital Windowed Watchdog Window Size Control */
|
||||
uint32 INTCLRENABLE; /**< 0x00AC: RTI Compare Interrupt Clear Enable Register */
|
||||
uint32 COMP0CLR; /**< 0x00B0: RTI Compare 0 Clear Register */
|
||||
uint32 COMP1CLR; /**< 0x00B4: RTI Compare 1 Clear Register */
|
||||
uint32 COMP2CLR; /**< 0x00B8: RTI Compare 2 Clear Register */
|
||||
uint32 COMP3CLR; /**< 0x00BC: RTI Compare 3 Clear Register */
|
||||
} rtiBASE_t;
|
||||
|
||||
/** @def rtiREG1
|
||||
* @brief RTI1 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the RTI driver to access the RTI1 registers.
|
||||
*/
|
||||
#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,83 @@
|
||||
/** @file reg_rtp.h
|
||||
* @brief RTP Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the RTP driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_RTP_H__
|
||||
#define __REG_RTP_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Rtp Register Frame Definition */
|
||||
/** @struct rtpBase
|
||||
* @brief RTP Base Register Definition
|
||||
*
|
||||
* This structure is used to access the RTP module registers.
|
||||
*/
|
||||
/** @typedef rtpBASE_t
|
||||
* @brief RTP Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the RTP Registers.
|
||||
*/
|
||||
typedef volatile struct rtpBase
|
||||
{
|
||||
uint32 GLBCTRL; /**< 0x0000: RTP Global Control Register */
|
||||
uint32 TRENA; /**< 0x0004: RTP Trace Enable Register */
|
||||
uint32 GSR; /**< 0x0008: RTP Global Status Register */
|
||||
uint32 RAM1REG1; /**< 0x000C: RTP RAM 1 Trace Region 1 Register */
|
||||
uint32 RAM1REG2; /**< 0x0010: RTP RAM 1 Trace Region 2 Register */
|
||||
uint32 RAM2REG1; /**< 0x0014: RTP RAM 2 Trace Region 1 Register */
|
||||
uint32 RAM2REG2; /**< 0x0018: RTP RAM 2 Trace Region 2 Register */
|
||||
uint32 rsvd1[2U]; /**< 0x001C: Reserved */
|
||||
uint32 ERREG1; /**< 0x0024: RTP Peripheral Trace Region 1 Register */
|
||||
uint32 ERREG2; /**< 0x0028: RTP Peripheral Trace Region 2 Register */
|
||||
uint32 DDMW; /**< 0x002C: RTP Direct Data Mode Write Register */
|
||||
uint32 rsvd2; /**< 0x0030: Reserved */
|
||||
uint32 PC0; /**< 0x0034: RTP Pin Control 0 Register */
|
||||
uint32 PC1; /**< 0x0038: RTP Pin Control 1 Register */
|
||||
uint32 PC2; /**< 0x003C: RTP Pin Control 2 Register */
|
||||
uint32 PC3; /**< 0x0040: RTP Pin Control 3 Register */
|
||||
uint32 PC4; /**< 0x0044: RTP Pin Control 4 Register */
|
||||
uint32 PC5; /**< 0x0048: RTP Pin Control 5 Register */
|
||||
uint32 PC6; /**< 0x004C: RTP Pin Control 6 Register */
|
||||
uint32 PC7; /**< 0x0050: RTP Pin Control 7 Register */
|
||||
uint32 PC8; /**< 0x0054: RTP Pin Control 8 Register */
|
||||
} rtpBASE_t;
|
||||
|
||||
|
||||
/** @def rtpREG
|
||||
* @brief RTP Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the RTP driver to access the RTP module registers.
|
||||
*/
|
||||
#define rtpREG ((rtpBASE_t *)0xFFFFFA00U)
|
||||
|
||||
/** @def rtpPORT
|
||||
* @brief RTP Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of RTP
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define rtpPORT ((gioPORT_t *)0xFFFFFA38U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,106 @@
|
||||
/** @file reg_sci.h
|
||||
* @brief SCI Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the SCI driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_SCI_H__
|
||||
#define __REG_SCI_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Sci Register Frame Definition */
|
||||
/** @struct sciBase
|
||||
* @brief SCI Base Register Definition
|
||||
*
|
||||
* This structure is used to access the SCI module registers.
|
||||
*/
|
||||
/** @typedef sciBASE_t
|
||||
* @brief SCI Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the SCI Registers.
|
||||
*/
|
||||
typedef volatile struct sciBase
|
||||
{
|
||||
uint32 GCR0; /**< 0x0000 Global Control Register 0 */
|
||||
uint32 GCR1; /**< 0x0004 Global Control Register 1 */
|
||||
uint32 GCR2; /**< 0x0008 Global Control Register 2 */
|
||||
uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */
|
||||
uint32 CLRINT; /**< 0x0010 Clear Interrupt Enable Register */
|
||||
uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */
|
||||
uint32 CLRINTLVL; /**< 0x0018 Set Interrupt Level Register */
|
||||
uint32 FLR; /**< 0x001C Interrupt Flag Register */
|
||||
uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */
|
||||
uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */
|
||||
uint32 FORMAT; /**< 0x0028 Format Control Register */
|
||||
uint32 BRS; /**< 0x002C Baud Rate Selection Register */
|
||||
uint32 ED; /**< 0x0030 Emulation Register */
|
||||
uint32 RD; /**< 0x0034 Receive Data Buffer */
|
||||
uint32 TD; /**< 0x0038 Transmit Data Buffer */
|
||||
uint32 FUN; /**< 0x003C Pin Function Register */
|
||||
uint32 DIR; /**< 0x0040 Pin Direction Register */
|
||||
uint32 DIN; /**< 0x0044 Pin Data In Register */
|
||||
uint32 DOUT; /**< 0x0048 Pin Data Out Register */
|
||||
uint32 SET; /**< 0x004C Pin Data Set Register */
|
||||
uint32 CLR; /**< 0x0050 Pin Data Clr Register */
|
||||
uint32 ODR; /**< 0x0054: Pin Open Drain Output Enable Register */
|
||||
uint32 PD; /**< 0x0058: Pin Pullup/Pulldown Disable Register */
|
||||
uint32 PSL; /**< 0x005C: Pin Pullup/Pulldown Selection Register */
|
||||
uint32 rsdv1[12U]; /**< 0x060: Reserved */
|
||||
uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */
|
||||
} sciBASE_t;
|
||||
|
||||
|
||||
/** @def sciREG
|
||||
* @brief Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SCI driver to access the sci module registers.
|
||||
*/
|
||||
#define sciREG ((sciBASE_t *)0xFFF7E500U)
|
||||
|
||||
|
||||
/** @def sciPORT
|
||||
* @brief SCI GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of SCI
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define sciPORT ((gioPORT_t *)0xFFF7E540U)
|
||||
|
||||
|
||||
/** @def scilinREG
|
||||
* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SCI driver to access the sci module registers.
|
||||
*/
|
||||
#define scilinREG ((sciBASE_t *)0xFFF7E400U)
|
||||
|
||||
|
||||
/** @def scilinPORT
|
||||
* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of LIN
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define scilinPORT ((gioPORT_t *)0xFFF7E440U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,155 @@
|
||||
/** @file reg_spi.h
|
||||
* @brief SPI Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* - Interface Prototypes
|
||||
* .
|
||||
* which are relevant for the SPI driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_SPI_H__
|
||||
#define __REG_SPI_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Spi Register Frame Definition */
|
||||
/** @struct spiBase
|
||||
* @brief SPI Register Definition
|
||||
*
|
||||
* This structure is used to access the SPI module registers.
|
||||
*/
|
||||
/** @typedef spiBASE_t
|
||||
* @brief SPI Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the SPI Registers.
|
||||
*/
|
||||
typedef volatile struct spiBase
|
||||
{
|
||||
uint32 GCR0; /**< 0x0000: Global Control 0 */
|
||||
uint32 GCR1; /**< 0x0004: Global Control 1 */
|
||||
uint32 INT0; /**< 0x0008: Interrupt Register */
|
||||
uint32 LVL; /**< 0x000C: Interrupt Level */
|
||||
uint32 FLG; /**< 0x0010: Interrupt flags */
|
||||
uint32 PCFUN; /**< 0x0014: Function Pin Enable */
|
||||
uint32 PCDIR; /**< 0x0018: Pin Direction */
|
||||
uint32 PCDIN; /**< 0x001C: Pin Input Latch */
|
||||
uint32 PCDOUT; /**< 0x0020: Pin Output Latch */
|
||||
uint32 PCSET; /**< 0x0024: Output Pin Set */
|
||||
uint32 PCCLR; /**< 0x0028: Output Pin Clr */
|
||||
uint32 PCPDR; /**< 0x002C: Open Drain Output Enable */
|
||||
uint32 PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
|
||||
uint32 PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
|
||||
uint32 DAT0; /**< 0x0038: Transmit Data */
|
||||
uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
|
||||
uint32 BUF; /**< 0x0040: Receive Buffer */
|
||||
uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
|
||||
uint32 DELAY; /**< 0x0048: Delays */
|
||||
uint32 CSDEF; /**< 0x004C: Default Chip Select */
|
||||
uint32 FMT0; /**< 0x0050: Data Format 0 */
|
||||
uint32 FMT1; /**< 0x0054: Data Format 1 */
|
||||
uint32 FMT2; /**< 0x0058: Data Format 2 */
|
||||
uint32 FMT3; /**< 0x005C: Data Format 3 */
|
||||
uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
|
||||
uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
|
||||
uint32 SRSEL; /**< 0x0068: Slew Rate Select */
|
||||
uint32 RESERVED[50U]; /**< 0x006C to 0x0130: Reserved */
|
||||
uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
|
||||
} spiBASE_t;
|
||||
|
||||
/** @def spiREG1
|
||||
* @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SPI driver to access the spi module registers.
|
||||
*/
|
||||
#define spiREG1 ((spiBASE_t *)0xFFF7F400U)
|
||||
|
||||
|
||||
/** @def spiPORT1
|
||||
* @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of SPI1
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define spiPORT1 ((gioPORT_t *)0xFFF7F418U)
|
||||
|
||||
/** @def spiREG2
|
||||
* @brief SPI2 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SPI driver to access the spi module registers.
|
||||
*/
|
||||
#define spiREG2 ((spiBASE_t *)0xFFF7F600U)
|
||||
|
||||
|
||||
/** @def spiPORT2
|
||||
* @brief SPI2 GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of SPI2
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define spiPORT2 ((gioPORT_t *)0xFFF7F618U)
|
||||
|
||||
/** @def spiREG3
|
||||
* @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SPI driver to access the spi module registers.
|
||||
*/
|
||||
#define spiREG3 ((spiBASE_t *)0xFFF7F800U)
|
||||
|
||||
|
||||
/** @def spiPORT3
|
||||
* @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of SPI3
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define spiPORT3 ((gioPORT_t *)0xFFF7F818U)
|
||||
|
||||
/** @def spiREG4
|
||||
* @brief SPI4 Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SPI driver to access the spi module registers.
|
||||
*/
|
||||
#define spiREG4 ((spiBASE_t *)0xFFF7FA00U)
|
||||
|
||||
|
||||
/** @def spiPORT4
|
||||
* @brief SPI4 GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of SPI4
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define spiPORT4 ((gioPORT_t *)0xFFF7FA18U)
|
||||
|
||||
/** @def spiREG5
|
||||
* @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer
|
||||
*
|
||||
* This pointer is used by the SPI driver to access the spi module registers.
|
||||
*/
|
||||
#define spiREG5 ((spiBASE_t *)0xFFF7FC00U)
|
||||
|
||||
|
||||
/** @def spiPORT5
|
||||
* @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of SPI5
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define spiPORT5 ((gioPORT_t *)0xFFF7FC18U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,60 @@
|
||||
/** @file reg_stc.h
|
||||
* @brief STC Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_STC_H__
|
||||
#define __REG_STC_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Stc Register Frame Definition */
|
||||
/** @struct stcBase
|
||||
* @brief STC Base Register Definition
|
||||
*
|
||||
* This structure is used to access the STC module registers.
|
||||
*/
|
||||
/** @typedef stcBASE_t
|
||||
* @brief STC Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the STC Registers.
|
||||
*/
|
||||
typedef volatile struct stcBase
|
||||
{
|
||||
uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */
|
||||
uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */
|
||||
uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */
|
||||
uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */
|
||||
uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */
|
||||
uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */
|
||||
uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */
|
||||
uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */
|
||||
uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */
|
||||
uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */
|
||||
uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */
|
||||
uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */
|
||||
uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */
|
||||
uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */
|
||||
uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */
|
||||
uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */
|
||||
} stcBASE_t;
|
||||
|
||||
#define stcREG ((stcBASE_t *)0xFFFFE600U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,159 @@
|
||||
/** @file reg_system.h
|
||||
* @brief System Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_SYSTEM_H__
|
||||
#define __REG_SYSTEM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "gio.h"
|
||||
|
||||
|
||||
/* System Register Frame 1 Definition */
|
||||
/** @struct systemBase1
|
||||
* @brief System Register Frame 1 Definition
|
||||
*
|
||||
* This type is used to access the System 1 Registers.
|
||||
*/
|
||||
/** @typedef systemBASE1_t
|
||||
* @brief System Register Frame 1 Type Definition
|
||||
*
|
||||
* This type is used to access the System 1 Registers.
|
||||
*/
|
||||
typedef volatile struct systemBase1
|
||||
{
|
||||
uint32 SYSPC1; /* 0x0000 */
|
||||
uint32 SYSPC2; /* 0x0004 */
|
||||
uint32 SYSPC3; /* 0x0008 */
|
||||
uint32 SYSPC4; /* 0x000C */
|
||||
uint32 SYSPC5; /* 0x0010 */
|
||||
uint32 SYSPC6; /* 0x0014 */
|
||||
uint32 SYSPC7; /* 0x0018 */
|
||||
uint32 SYSPC8; /* 0x001C */
|
||||
uint32 SYSPC9; /* 0x0020 */
|
||||
uint32 SSWPLL1; /* 0x0024 */
|
||||
uint32 SSWPLL2; /* 0x0028 */
|
||||
uint32 SSWPLL3; /* 0x002C */
|
||||
uint32 CSDIS; /* 0x0030 */
|
||||
uint32 CSDISSET; /* 0x0034 */
|
||||
uint32 CSDISCLR; /* 0x0038 */
|
||||
uint32 CDDIS; /* 0x003C */
|
||||
uint32 CDDISSET; /* 0x0040 */
|
||||
uint32 CDDISCLR; /* 0x0044 */
|
||||
uint32 GHVSRC; /* 0x0048 */
|
||||
uint32 VCLKASRC; /* 0x004C */
|
||||
uint32 RCLKSRC; /* 0x0050 */
|
||||
uint32 CSVSTAT; /* 0x0054 */
|
||||
uint32 MSTGCR; /* 0x0058 */
|
||||
uint32 MINITGCR; /* 0x005C */
|
||||
uint32 MSINENA; /* 0x0060 */
|
||||
uint32 MSTFAIL; /* 0x0064 */
|
||||
uint32 MSTCGSTAT; /* 0x0068 */
|
||||
uint32 MINISTAT; /* 0x006C */
|
||||
uint32 PLLCTL1; /* 0x0070 */
|
||||
uint32 PLLCTL2; /* 0x0074 */
|
||||
uint32 UERFLAG; /* 0x0078 */
|
||||
uint32 DIEIDL; /* 0x007C */
|
||||
uint32 DIEIDH; /* 0x0080 */
|
||||
uint32 VRCTL; /* 0x0084 */
|
||||
uint32 LPOMONCTL; /* 0x0088 */
|
||||
uint32 CLKTEST; /* 0x008C */
|
||||
uint32 DFTCTRLREG1; /* 0x0090 */
|
||||
uint32 DFTCTRLREG2; /* 0x0094 */
|
||||
uint32 rsvd1; /* 0x0098 */
|
||||
uint32 rsvd2; /* 0x009C */
|
||||
uint32 GPREG1; /* 0x00A0 */
|
||||
uint32 BTRMSEL; /* 0x00A4 */
|
||||
uint32 IMPFASTS; /* 0x00A8 */
|
||||
uint32 IMPFTADD; /* 0x00AC */
|
||||
uint32 SSISR1; /* 0x00B0 */
|
||||
uint32 SSISR2; /* 0x00B4 */
|
||||
uint32 SSISR3; /* 0x00B8 */
|
||||
uint32 SSISR4; /* 0x00BC */
|
||||
uint32 RAMGCR; /* 0x00C0 */
|
||||
uint32 BMMCR1; /* 0x00C4 */
|
||||
uint32 BMMCR2; /* 0x00C8 */
|
||||
uint32 MMUGCR; /* 0x00CC */
|
||||
uint32 CLKCNTL; /* 0x00D0 */
|
||||
uint32 ECPCNTL; /* 0x00D4 */
|
||||
uint32 DSPGCR; /* 0x00D8 */
|
||||
uint32 DEVCR1; /* 0x00DC */
|
||||
uint32 SYSECR; /* 0x00E0 */
|
||||
uint32 SYSESR; /* 0x00E4 */
|
||||
uint32 SYSTASR; /* 0x00E8 */
|
||||
uint32 GBLSTAT; /* 0x00EC */
|
||||
uint32 DEV; /* 0x00F0 */
|
||||
uint32 SSIVEC; /* 0x00F4 */
|
||||
uint32 SSIF; /* 0x00F8 */
|
||||
uint32 SSIR1; /* 0x00FC */
|
||||
} systemBASE1_t;
|
||||
|
||||
|
||||
/** @def systemREG1
|
||||
* @brief System Register Frame 1 Pointer
|
||||
*
|
||||
* This pointer is used by the system driver to access the system frame 1 registers.
|
||||
*/
|
||||
#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
|
||||
|
||||
/** @def systemPORT
|
||||
* @brief ECLK GIO Port Register Pointer
|
||||
*
|
||||
* Pointer used by the GIO driver to access I/O PORT of System/Eclk
|
||||
* (use the GIO drivers to access the port pins).
|
||||
*/
|
||||
#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* System Register Frame 2 Definition */
|
||||
/** @struct systemBase2
|
||||
* @brief System Register Frame 2 Definition
|
||||
*
|
||||
* This type is used to access the System 2 Registers.
|
||||
*/
|
||||
/** @typedef systemBASE2_t
|
||||
* @brief System Register Frame 2 Type Definition
|
||||
*
|
||||
* This type is used to access the System 2 Registers.
|
||||
*/
|
||||
typedef volatile struct systemBase2
|
||||
{
|
||||
uint32 PLLCTL3; /* 0x0000 */
|
||||
uint32 rsvd1; /* 0x0004 */
|
||||
uint32 STCCLKDIV; /* 0x0008 */
|
||||
uint32 rsvd2[6U]; /* 0x000C */
|
||||
uint32 ECPCNTRL0; /* 0x0024 */
|
||||
uint32 rsvd3[5U]; /* 0x0028 */
|
||||
uint32 CLK2CNTL; /* 0x003C */
|
||||
uint32 VCLKACON1; /* 0x0040 */
|
||||
uint32 rsvd4[11U]; /* 0x0044 */
|
||||
uint32 CLKSLIP; /* 0x0070 */
|
||||
uint32 rsvd5[30U]; /* 0x0074 */
|
||||
uint32 EFC_CTLEN; /* 0x00EC */
|
||||
uint32 DIEIDL_REG0; /* 0x00F0 */
|
||||
uint32 DIEIDH_REG1; /* 0x00F4 */
|
||||
uint32 DIEIDL_REG2; /* 0x00F8 */
|
||||
uint32 DIEIDH_REG3; /* 0x00FC */
|
||||
} systemBASE2_t;
|
||||
|
||||
/** @def systemREG2
|
||||
* @brief System Register Frame 2 Pointer
|
||||
*
|
||||
* This pointer is used by the system driver to access the system frame 2 registers.
|
||||
*/
|
||||
#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/** @file reg_tcram.h
|
||||
* @brief TCRAM Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_TCRAM_H__
|
||||
#define __REG_TCRAM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* Tcram Register Frame Definition */
|
||||
/** @struct tcramBase
|
||||
* @brief TCRAM Wrapper Register Frame Definition
|
||||
*
|
||||
* This type is used to access the TCRAM Wrapper Registers.
|
||||
*/
|
||||
/** @typedef tcramBASE_t
|
||||
* @brief TCRAM Wrapper Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the TCRAM Wrapper Registers.
|
||||
*/
|
||||
|
||||
typedef volatile struct tcramBase
|
||||
{
|
||||
uint32 RAMCTRL; /* 0x0000 */
|
||||
uint32 RAMTHRESHOLD; /* 0x0004 */
|
||||
uint32 RAMOCCUR; /* 0x0008 */
|
||||
uint32 RAMINTCTRL; /* 0x000C */
|
||||
uint32 RAMERRSTATUS; /* 0x0010 */
|
||||
uint32 RAMSERRADDR; /* 0x0014 */
|
||||
uint32 rsvd1; /* 0x0018 */
|
||||
uint32 RAMUERRADDR; /* 0x001C */
|
||||
uint32 rsvd2[4U]; /* 0x0020 */
|
||||
uint32 RAMTEST; /* 0x0030 */
|
||||
uint32 rsvd3; /* 0x0034 */
|
||||
uint32 RAMADDRDECVECT; /* 0x0038 */
|
||||
uint32 RAMPERADDR; /* 0x003C */
|
||||
} tcramBASE_t;
|
||||
|
||||
#define tcram1REG ((tcramBASE_t *)(0xFFFFF800U))
|
||||
#define tcram2REG ((tcramBASE_t *)(0xFFFFF900U))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,77 @@
|
||||
/** @file reg_vim.h
|
||||
* @brief VIM Register Layer Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __REG_VIM_H__
|
||||
#define __REG_VIM_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Vim Register Frame Definition */
|
||||
/** @struct vimBase
|
||||
* @brief Vim Register Frame Definition
|
||||
*
|
||||
* This type is used to access the Vim Registers.
|
||||
*/
|
||||
/** @typedef vimBASE_t
|
||||
* @brief VIM Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the VIM Registers.
|
||||
*/
|
||||
typedef volatile struct vimBase
|
||||
{
|
||||
uint32 IRQINDEX; /* 0x0000 */
|
||||
uint32 FIQINDEX; /* 0x0004 */
|
||||
uint32 rsvd1; /* 0x0008 */
|
||||
uint32 rsvd2; /* 0x000C */
|
||||
uint32 FIRQPR0; /* 0x0010 */
|
||||
uint32 FIRQPR1; /* 0x0014 */
|
||||
uint32 FIRQPR2; /* 0x0018 */
|
||||
uint32 FIRQPR3; /* 0x001C */
|
||||
uint32 INTREQ0; /* 0x0020 */
|
||||
uint32 INTREQ1; /* 0x0024 */
|
||||
uint32 INTREQ2; /* 0x0028 */
|
||||
uint32 INTREQ3; /* 0x002C */
|
||||
uint32 REQMASKSET0; /* 0x0030 */
|
||||
uint32 REQMASKSET1; /* 0x0034 */
|
||||
uint32 REQMASKSET2; /* 0x0038 */
|
||||
uint32 REQMASKSET3; /* 0x003C */
|
||||
uint32 REQMASKCLR0; /* 0x0040 */
|
||||
uint32 REQMASKCLR1; /* 0x0044 */
|
||||
uint32 REQMASKCLR2; /* 0x0048 */
|
||||
uint32 REQMASKCLR3; /* 0x004C */
|
||||
uint32 WAKEMASKSET0; /* 0x0050 */
|
||||
uint32 WAKEMASKSET1; /* 0x0054 */
|
||||
uint32 WAKEMASKSET2; /* 0x0058 */
|
||||
uint32 WAKEMASKSET3; /* 0x005C */
|
||||
uint32 WAKEMASKCLR0; /* 0x0060 */
|
||||
uint32 WAKEMASKCLR1; /* 0x0064 */
|
||||
uint32 WAKEMASKCLR2; /* 0x0068 */
|
||||
uint32 WAKEMASKCLR3; /* 0x006C */
|
||||
uint32 IRQVECREG; /* 0x0070 */
|
||||
uint32 FIQVECREG; /* 0x0074 */
|
||||
uint32 CAPEVT; /* 0x0078 */
|
||||
uint32 rsvd3; /* 0x007C */
|
||||
uint32 CHANCTRL[24U]; /* 0x0080-0x017C */
|
||||
} vimBASE_t;
|
||||
|
||||
#define vimREG ((vimBASE_t *)0xFFFFFE00U)
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,35 @@
|
||||
/** @file rtp.h
|
||||
* @brief RTP Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
|
||||
#ifndef __RTP_H__
|
||||
#define __RTP_H__
|
||||
|
||||
#include "reg_rtp.h"
|
||||
|
||||
/**
|
||||
* @defgroup RTP RTP
|
||||
* @brief RAM Trace Port.
|
||||
*
|
||||
* RAM Trace Port (RTP) module provides the features to datalog the RAM contents of the devices
|
||||
* or accesses to peripherals without program intrusion. It can trace all data write or read accesses to internal RAM.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_rtp.h
|
||||
* - rtp.h
|
||||
* - rtp.c
|
||||
* @addtogroup RTP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* RTP Interface Functions */
|
||||
void rtpInit(void);
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
@@ -0,0 +1,102 @@
|
||||
/** @file sci.h
|
||||
* @brief SCI Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
|
||||
#ifndef __SCI_H__
|
||||
#define __SCI_H__
|
||||
|
||||
#include "reg_sci.h"
|
||||
|
||||
|
||||
/** @enum sciIntFlags
|
||||
* @brief Interrupt Flag Definitions
|
||||
*
|
||||
* Used with sciEnableNotification, sciDisableNotification
|
||||
*/
|
||||
enum sciIntFlags
|
||||
{
|
||||
SCI_FE_INT = 0x04000000U, /* framing error */
|
||||
SCI_OE_INT = 0x02000000U, /* overrun error */
|
||||
SCI_PE_INT = 0x01000000U, /* parity error */
|
||||
SCI_RX_INT = 0x00000200U, /* receive buffer ready */
|
||||
SCI_TX_INT = 0x00000100U, /* transmit buffer ready */
|
||||
SCI_WAKE_INT = 0x00000002U, /* wakeup */
|
||||
SCI_BREAK_INT = 0x00000001U /* break detect */
|
||||
};
|
||||
|
||||
/** @def SCI_IDLE
|
||||
* @brief Alias name for the SCI IDLE Flag
|
||||
*
|
||||
* This is an alias name for the SCI IDLE Flag.
|
||||
*
|
||||
*/
|
||||
#define SCI_IDLE 0x00000004U
|
||||
|
||||
/** @struct sciBase
|
||||
* @brief SCI Register Definition
|
||||
*
|
||||
* This structure is used to access the SCI module registers.
|
||||
*/
|
||||
/** @typedef sciBASE_t
|
||||
* @brief SCI Register Frame Type Definition
|
||||
*
|
||||
* This type is used to access the SCI Registers.
|
||||
*/
|
||||
|
||||
enum sciPinSelect
|
||||
{
|
||||
PIN_SCI_TX = 0U,
|
||||
PIN_SCI_RX = 1U
|
||||
};
|
||||
|
||||
/**
|
||||
* @defgroup SCI SCI
|
||||
* @brief Serial Communication Interface Module.
|
||||
*
|
||||
* The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
|
||||
* to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_sci.h
|
||||
* - sci.h
|
||||
* - sci.c
|
||||
* @addtogroup SCI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SCI Interface Functions */
|
||||
void sciInit(void);
|
||||
void sciSetFunctional(sciBASE_t *sci, uint32 port);
|
||||
void sciSetBaudrate(sciBASE_t *sci, uint32 baud);
|
||||
uint32 sciIsTxReady(sciBASE_t *sci);
|
||||
void sciSendByte(sciBASE_t *sci, uint8 byte);
|
||||
void sciSend(sciBASE_t *sci, uint32 length, uint8 * data);
|
||||
uint32 sciIsRxReady(sciBASE_t *sci);
|
||||
uint32 sciIsIdleDetected(sciBASE_t *sci);
|
||||
uint32 sciRxError(sciBASE_t *sci);
|
||||
uint32 sciReceiveByte(sciBASE_t *sci);
|
||||
void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data);
|
||||
void sciEnableNotification(sciBASE_t *sci, uint32 flags);
|
||||
void sciDisableNotification(sciBASE_t *sci, uint32 flags);
|
||||
void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype);
|
||||
void sciDisableLoopback(sciBASE_t *sci);
|
||||
|
||||
/** @fn void sciNotification(sciBASE_t *sci, uint32 flags)
|
||||
* @brief Interrupt callback
|
||||
* @param[in] sci - sci module base address
|
||||
* @param[in] flags - copy of error interrupt flags
|
||||
*
|
||||
* This is a callback that is provided by the application and is called upon
|
||||
* an interrupt. The parameter passed to the callback is a copy of the
|
||||
* interrupt flag register.
|
||||
*/
|
||||
void sciNotification(sciBASE_t *sci, uint32 flags);
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
@@ -0,0 +1,154 @@
|
||||
/** @file spi.h
|
||||
* @brief SPI Driver Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
#include "reg_spi.h"
|
||||
|
||||
/** @enum chipSelect
|
||||
* @brief Transfer Group Chip Select
|
||||
*/
|
||||
enum spiChipSelect
|
||||
{
|
||||
SPI_CS_NONE = 0xFFU,
|
||||
SPI_CS_0 = 0xFEU,
|
||||
SPI_CS_1 = 0xFDU,
|
||||
SPI_CS_2 = 0xFBU,
|
||||
SPI_CS_3 = 0xF7U,
|
||||
SPI_CS_4 = 0xEFU,
|
||||
SPI_CS_5 = 0xDFU,
|
||||
SPI_CS_6 = 0xBFU,
|
||||
SPI_CS_7 = 0x7FU
|
||||
};
|
||||
|
||||
/** @enum spiPinSelect
|
||||
* @brief spi Pin Select
|
||||
*/
|
||||
enum spiPinSelect
|
||||
{
|
||||
SPI_PIN_CS0 = 0U,
|
||||
SPI_PIN_CS1 = 1U,
|
||||
SPI_PIN_CS2 = 2U,
|
||||
SPI_PIN_CS3 = 3U,
|
||||
SPI_PIN_CS4 = 4U,
|
||||
SPI_PIN_CS5 = 5U,
|
||||
SPI_PIN_CS6 = 6U,
|
||||
SPI_PIN_CS7 = 7U,
|
||||
SPI_PIN_ENA = 8U,
|
||||
SPI_PIN_CLK = 9U,
|
||||
SPI_PIN_SIMO = 10U,
|
||||
SPI_PIN_SOMI = 11U,
|
||||
SPI_PIN_SIMO_1 = 17U,
|
||||
SPI_PIN_SIMO_2 = 18U,
|
||||
SPI_PIN_SIMO_3 = 19U,
|
||||
SPI_PIN_SIMO_4 = 20U,
|
||||
SPI_PIN_SIMO_5 = 21U,
|
||||
SPI_PIN_SIMO_6 = 22U,
|
||||
SPI_PIN_SIMO_7 = 23U,
|
||||
SPI_PIN_SOMI_1 = 25U,
|
||||
SPI_PIN_SOMI_2 = 26U,
|
||||
SPI_PIN_SOMI_3 = 27U,
|
||||
SPI_PIN_SOMI_4 = 28U,
|
||||
SPI_PIN_SOMI_5 = 29U,
|
||||
SPI_PIN_SOMI_6 = 30U,
|
||||
SPI_PIN_SOMI_7 = 31U
|
||||
};
|
||||
|
||||
/** @enum dataformat
|
||||
* @brief SPI dataformat register select
|
||||
*/
|
||||
typedef enum dataformat
|
||||
{
|
||||
SPI_FMT_0 = 0U,
|
||||
SPI_FMT_1 = 1U,
|
||||
SPI_FMT_2 = 2U,
|
||||
SPI_FMT_3 = 3U
|
||||
}SPIDATAFMT_t;
|
||||
|
||||
/** @struct spiDAT1RegConfig
|
||||
* @brief SPI data register configuration
|
||||
*/
|
||||
typedef struct spiDAT1RegConfig
|
||||
{
|
||||
boolean CS_HOLD;
|
||||
boolean WDEL;
|
||||
SPIDATAFMT_t DFSEL;
|
||||
uint8 CSNR;
|
||||
}spiDAT1_t;
|
||||
|
||||
/** @enum SpiTxRxDataStatus
|
||||
* @brief SPI Data Status
|
||||
*/
|
||||
typedef enum SpiTxRxDataStatus
|
||||
{
|
||||
SPI_READY = 0U,
|
||||
SPI_PENDING = 1U,
|
||||
SPI_COMPLETED = 2U
|
||||
}SpiDataStatus_t;
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/**
|
||||
* @defgroup SPI SPI
|
||||
* @brief Serial Peripheral Interface Module.
|
||||
*
|
||||
* SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
|
||||
* programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
|
||||
*
|
||||
* Related Files
|
||||
* - reg_spi.h
|
||||
* - spi.h
|
||||
* - spi.c
|
||||
* @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SPI Interface Functions */
|
||||
void spiInit(void);
|
||||
void spiSetFunctional(spiBASE_t *spi, uint32 port);
|
||||
void spiEnableNotification(spiBASE_t *spi, uint32 flags);
|
||||
void spiDisableNotification(spiBASE_t *spi, uint32 flags);
|
||||
uint32 spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
|
||||
void spiSendData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
|
||||
uint32 spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
|
||||
void spiGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
|
||||
uint32 spiTransmitAndReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
|
||||
void spiSendAndGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
|
||||
void spiEnableLoopback(spiBASE_t *spi, loopBackType_t Loopbacktype);
|
||||
void spiDisableLoopback(spiBASE_t *spi);
|
||||
SpiDataStatus_t SpiTxStatus(spiBASE_t *spi);
|
||||
SpiDataStatus_t SpiRxStatus(spiBASE_t *spi);
|
||||
|
||||
/** @fn void spiNotification(spiBASE_t *spi, uint32 flags)
|
||||
* @brief Interrupt callback
|
||||
* @param[in] spi - Spi module base address
|
||||
* @param[in] flags - Copy of error interrupt flags
|
||||
*
|
||||
* This is a callback that is provided by the application and is called upon
|
||||
* an interrupt. The parameter passed to the callback is a copy of the
|
||||
* interrupt flag register.
|
||||
*/
|
||||
void spiNotification(spiBASE_t *spi, uint32 flags);
|
||||
|
||||
/** @fn void spiEndNotification(spiBASE_t *spi)
|
||||
* @brief Interrupt callback for End of TX or RX data length.
|
||||
* @param[in] spi - Spi module base address
|
||||
*
|
||||
* This is a callback that is provided by the application and is called upon
|
||||
* an interrupt at the End of TX or RX data length.
|
||||
*/
|
||||
void spiEndNotification(spiBASE_t *spi);
|
||||
|
||||
/**@}*/
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,80 @@
|
||||
/** @file sys_common.h
|
||||
* @brief Common Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - General Definitions
|
||||
* .
|
||||
* which are relevant for all drivers.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __SYS_COMMON_H__
|
||||
#define __SYS_COMMON_H__
|
||||
|
||||
#include "hal_stdtypes.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/************************************************************/
|
||||
/* Type Definitions */
|
||||
/************************************************************/
|
||||
|
||||
#ifndef _TBOOLEAN_DECLARED
|
||||
typedef boolean tBoolean;
|
||||
#define _TBOOLEAN_DECLARED
|
||||
#endif
|
||||
|
||||
/** @enum loopBackType
|
||||
* @brief Loopback type definition
|
||||
*/
|
||||
/** @typedef loopBackType_t
|
||||
* @brief Loopback type Type Definition
|
||||
*
|
||||
* This type is used to select the module Loopback type Digital or Analog loopback.
|
||||
*/
|
||||
typedef enum loopBackType
|
||||
{
|
||||
Digital = 0U,
|
||||
Analog = 1U
|
||||
}loopBackType_t;
|
||||
|
||||
/** @enum config_value_type
|
||||
* @brief config type definition
|
||||
*/
|
||||
/** @typedef config_value_type_t
|
||||
* @brief config type Type Definition
|
||||
*
|
||||
* This type is used to specify the Initial and Current value.
|
||||
*/
|
||||
typedef enum config_value_type
|
||||
{
|
||||
InitialValue,
|
||||
CurrentValue
|
||||
}config_value_type_t;
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
/********************************************************************************/
|
||||
/* The ASSERT macro, which does the actual assertion checking. Typically, this */
|
||||
/* will be for procedure arguments. */
|
||||
/********************************************************************************/
|
||||
#ifdef DEBUG
|
||||
#define ASSERT(expr) { \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
/* USER CODE BEGIN (2) */
|
||||
/* USER CODE END */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,141 @@
|
||||
/** @file sys_pmm.h
|
||||
* @brief PMM Driver Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Definitions
|
||||
* - Types
|
||||
* .
|
||||
* which are relevant for the System driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __SYS_PMM_H__
|
||||
#define __SYS_PMM_H__
|
||||
|
||||
#include "reg_pmm.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Bit Masks */
|
||||
#define PMM_LOGICPDPWRCTRL0_LOGICPDON0 (0xFU << 24U) /*PD2*/
|
||||
#define PMM_LOGICPDPWRCTRL0_LOGICPDON1 (0xFU << 16U) /*PD3*/
|
||||
#define PMM_LOGICPDPWRCTRL0_LOGICPDON2 (0xFU << 8U) /*PD4*/
|
||||
#define PMM_LOGICPDPWRCTRL0_LOGICPDON3 (0xFU << 0U) /*PD5*/
|
||||
|
||||
#define PMM_MEMPDPWRCTRL0_MEMPDON0 (0xFU << 24U) /*RAM_PD1*/
|
||||
#define PMM_MEMPDPWRCTRL0_MEMPDON1 (0xFU << 16U) /*RAM_PD2*/
|
||||
#define PMM_MEMPDPWRCTRL0_MEMPDON2 (0xFU << 8U) /*RAM_PD3*/
|
||||
|
||||
#define PMM_LOGICPDPWRSTAT_DOMAINON (1U << 8U)
|
||||
#define PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT (0x3U << 0U)
|
||||
#define PMM_MEMPDPWRSTAT_DOMAINON (1U << 8U)
|
||||
#define PMM_MEMPDPWRSTAT_MEMPDPWRSTAT (0x3U << 0U)
|
||||
#define PMM_GLOBALCTRL1_AUTOCLKWAKEENA (1U << 0U)
|
||||
|
||||
/* Configuration registers initial value */
|
||||
#define PMM_LOGICPDPWRCTRL0_CONFIGVALUE (((1U)?0x5U:0xAU) << 24U) \
|
||||
| (((1U)?0x5U:0xAU) << 16U) \
|
||||
| (((0U)?0x5U:0xAU) << 8U) \
|
||||
| (((1U)?0x5U:0xAU) << 0U)
|
||||
|
||||
#define PMM_MEMPDPWRCTRL0_CONFIGVALUE (((1U)?0x5U:0xAU) << 24U) \
|
||||
| (((1U)?0x5U:0xAU) << 16U) \
|
||||
| (((1U)?0x5U:0xAU) << 8U)
|
||||
|
||||
#define PMM_PDCLKDISREG_CONFIGVALUE ((!1U) << 0U)\
|
||||
| ((!1U) << 1U)\
|
||||
| ((!0U) << 2U)\
|
||||
| ((!1U) << 3U)
|
||||
|
||||
#define PMM_GLOBALCTRL1_CONFIGVALUE (0U << 8U) | (0U << 0U)
|
||||
|
||||
|
||||
/** @enum pmmLogicPDTag
|
||||
* @brief PMM Logic Power Domain
|
||||
*
|
||||
* Used to define PMM Logic Power Domain
|
||||
*/
|
||||
typedef enum pmmLogicPDTag
|
||||
{
|
||||
PMM_LOGICPD1 = 4U, /*-- NOT USED*/
|
||||
PMM_LOGICPD2 = 0U,
|
||||
PMM_LOGICPD3 = 1U,
|
||||
PMM_LOGICPD4 = 2U,
|
||||
PMM_LOGICPD5 = 3U
|
||||
}pmm_LogicPD_t;
|
||||
|
||||
|
||||
/** @enum pmmMemPDTag
|
||||
* @brief PMM Memory-Only Power Domain
|
||||
*
|
||||
* Used to define PMM Memory-Only Power Domain
|
||||
*/
|
||||
typedef enum pmmMemPDTag
|
||||
{
|
||||
PMM_MEMPD1 = 0U,
|
||||
PMM_MEMPD2 = 1U,
|
||||
PMM_MEMPD3 = 2U
|
||||
}pmm_MemPD_t;
|
||||
|
||||
|
||||
/** @enum pmmModeTag
|
||||
* @brief PSCON operating mode
|
||||
*
|
||||
* Used to define the operating mode of PSCON Compare Block
|
||||
*/
|
||||
typedef enum pmmModeTag
|
||||
{
|
||||
LockStep = 0x0U,
|
||||
SelfTest = 0x6U,
|
||||
ErrorForcing = 0x9U,
|
||||
SelfTestErrorForcing = 0xFU
|
||||
}pmm_Mode_t;
|
||||
|
||||
/*Pmm Configuration Registers*/
|
||||
typedef struct pmm_config_reg
|
||||
{
|
||||
uint32 CONFIG_LOGICPDPWRCTRL0;
|
||||
uint32 CONFIG_MEMPDPWRCTRL0;
|
||||
uint32 CONFIG_PDCLKDISREG;
|
||||
uint32 CONFIG_GLOBALCTRL1;
|
||||
}pmm_config_reg_t;
|
||||
|
||||
/**
|
||||
* @defgroup PMM PMM
|
||||
* @brief Power Management Module
|
||||
*
|
||||
* The PMM provides memory-mapped registers that control the states of the supported power domains.
|
||||
* The PMM includes interfaces to the Power Mode Controller (PMC) and the Power State Controller (PSCON).
|
||||
* The PMC and PSCON control the power up/down sequence of each power domain.
|
||||
*
|
||||
* Related files:
|
||||
* - reg_pmm.h
|
||||
* - sys_pmm.h
|
||||
* - sys_pmm.c
|
||||
*
|
||||
* @addtogroup PMM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Pmm Interface Functions */
|
||||
void pmmInit(void);
|
||||
void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD);
|
||||
void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD);
|
||||
void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD);
|
||||
void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD);
|
||||
boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD);
|
||||
boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD);
|
||||
void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type);
|
||||
void pmmSetMode(pmm_Mode_t mode);
|
||||
boolean pmmPerformSelfTest(void);
|
||||
|
||||
/**@}*/
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,191 @@
|
||||
/** @file sys_pmu.h
|
||||
* @brief System Pmu Header File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Pmu Interface Functions
|
||||
* .
|
||||
* which are relevant for the performance monitor unit driver.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#ifndef __SYS_PMU_H__
|
||||
#define __SYS_PMU_H__
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/** @def pmuCOUNTER0
|
||||
* @brief pmu event counter 0
|
||||
*
|
||||
* Alias for pmu event counter 0
|
||||
*/
|
||||
#define pmuCOUNTER0 0x00000001U
|
||||
|
||||
/** @def pmuCOUNTER1
|
||||
* @brief pmu event counter 1
|
||||
*
|
||||
* Alias for pmu event counter 1
|
||||
*/
|
||||
#define pmuCOUNTER1 0x00000002U
|
||||
|
||||
/** @def pmuCOUNTER2
|
||||
* @brief pmu event counter 2
|
||||
*
|
||||
* Alias for pmu event counter 2
|
||||
*/
|
||||
#define pmuCOUNTER2 0x00000004U
|
||||
|
||||
/** @def pmuCYCLE_COUNTER
|
||||
* @brief pmu cycle counter
|
||||
*
|
||||
* Alias for pmu event counter
|
||||
*/
|
||||
#define pmuCYCLE_COUNTER 0x80000000U
|
||||
|
||||
/** @enum pmuEvent
|
||||
* @brief pmu event
|
||||
*
|
||||
* Alias for pmu event counter increment source
|
||||
*/
|
||||
enum pmuEvent
|
||||
{
|
||||
PMU_INST_CACHE_MISS = 0x01U,
|
||||
PMU_DATA_CACHE_MISS = 0x03U,
|
||||
PMU_DATA_CACHE_ACCESS = 0x04U,
|
||||
PMU_DATA_READ_ARCH_EXECUTED = 0x06U,
|
||||
PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U,
|
||||
PMU_INST_ARCH_EXECUTED = 0x08U,
|
||||
PMU_EXCEPTION_TAKEN = 0x09U,
|
||||
PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU,
|
||||
PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU,
|
||||
PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU,
|
||||
PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU,
|
||||
PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU,
|
||||
PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU,
|
||||
PMU_BRANCH_MISSPREDICTED = 0x10U,
|
||||
PMU_CYCLE_COUNT = 0x11U,
|
||||
PMU_PREDICTABLE_BRANCHES = 0x12U,
|
||||
PMU_INST_BUFFER_STALL = 0x40U,
|
||||
PMU_DATA_DEPENDENCY_INST_STALL = 0x41U,
|
||||
PMU_DATA_CACHE_WRITE_BACK = 0x42U,
|
||||
PMU_EXT_MEMORY_REQUEST = 0x43U,
|
||||
PMU_LSU_BUSY_STALL = 0x44U,
|
||||
PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U,
|
||||
PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U,
|
||||
PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U,
|
||||
PMU_ETMEXTOUT_0 = 0x48U,
|
||||
PMU_ETMEXTOUT_1 = 0x49U,
|
||||
PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU,
|
||||
PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU,
|
||||
PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU,
|
||||
PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU,
|
||||
PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU,
|
||||
PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU,
|
||||
PMU_STORE_BUFFER_MERGE = 0x50U,
|
||||
PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U,
|
||||
PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U,
|
||||
PMU_INTEGER_DIV_EXECUTED = 0x53U,
|
||||
PMU_STALL_INTEGER_DIV = 0x54U,
|
||||
PMU_PLD_INST_LINE_FILL = 0x55U,
|
||||
PMU_PLD_INST_NO_LINE_FILL = 0x56U,
|
||||
PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U,
|
||||
PMU_INST_CACHE_ACCESS = 0x58U,
|
||||
PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U,
|
||||
PMU_DUAL_ISSUE_CASE_A = 0x5AU,
|
||||
PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU,
|
||||
PMU_DUAL_ISSUE_OTHER = 0x5CU,
|
||||
PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU,
|
||||
PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU,
|
||||
PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U,
|
||||
PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U,
|
||||
PMU_PROCESSOR_LIVE_LOCK = 0x62U,
|
||||
PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U,
|
||||
PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U,
|
||||
PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U,
|
||||
PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U,
|
||||
PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U,
|
||||
PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U,
|
||||
PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU,
|
||||
PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU,
|
||||
PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU,
|
||||
PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU
|
||||
};
|
||||
|
||||
/** @fn void _pmuInit_(void)
|
||||
* @brief Initialize Performance Monitor Unit
|
||||
*/
|
||||
void _pmuInit_(void);
|
||||
|
||||
/** @fn void _pmuEnableCountersGlobal_(void)
|
||||
* @brief Enable and reset cycle counter and all 3 event counters
|
||||
*/
|
||||
void _pmuEnableCountersGlobal_(void);
|
||||
|
||||
/** @fn void _pmuDisableCountersGlobal_(void)
|
||||
* @brief Disable cycle counter and all 3 event counters
|
||||
*/
|
||||
void _pmuDisableCountersGlobal_(void);
|
||||
|
||||
/** @fn void _pmuResetCycleCounter_(void)
|
||||
* @brief Reset cycle counter
|
||||
*/
|
||||
void _pmuResetCycleCounter_(void);
|
||||
|
||||
/** @fn void _pmuResetEventCounters_(void)
|
||||
* @brief Reset event counters 0-2
|
||||
*/
|
||||
void _pmuResetEventCounters_(void);
|
||||
|
||||
/** @fn void _pmuResetCounters_(void)
|
||||
* @brief Reset cycle counter and event counters 0-2
|
||||
*/
|
||||
void _pmuResetCounters_(void);
|
||||
|
||||
/** @fn void _pmuStartCounters_(uint32 counters)
|
||||
* @brief Starts selected counters
|
||||
* @param[in] counters - Counter mask
|
||||
*/
|
||||
void _pmuStartCounters_(uint32 counters);
|
||||
|
||||
/** @fn void _pmuStopCounters_(uint32 counters)
|
||||
* @brief Stops selected counters
|
||||
* @param[in] counters - Counter mask
|
||||
*/
|
||||
void _pmuStopCounters_(uint32 counters);
|
||||
|
||||
/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event)
|
||||
* @brief Set event counter count event
|
||||
* @param[in] counter - Counter select 0..2
|
||||
* @param[in] event - Count event
|
||||
*/
|
||||
void _pmuSetCountEvent_(uint32 counter, uint32 event);
|
||||
|
||||
/** @fn uint32 _pmuGetCycleCount_(void)
|
||||
* @brief Returns current cycle counter value
|
||||
*
|
||||
* @return cycle count.
|
||||
*/
|
||||
uint32 _pmuGetCycleCount_(void);
|
||||
|
||||
/** @fn uint32 _pmuGetEventCount_(uint32 counter)
|
||||
* @brief Returns current event counter value
|
||||
* @param[in] counter - Counter select 0..2
|
||||
*
|
||||
* @return event counter count.
|
||||
*/
|
||||
uint32 _pmuGetEventCount_(uint32 counter);
|
||||
|
||||
/** @fn uint32 _pmuGetOverflow_(void)
|
||||
* @brief Returns current overflow register and clear flags
|
||||
*
|
||||
* @return overflow flags.
|
||||
*/
|
||||
uint32 _pmuGetOverflow_(void);
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,53 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// usb-ids.h - Definitions of VIDs and PIDs used by Stellaris USB examples.
|
||||
//
|
||||
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Texas Instruments (TI) is supplying this software for use solely and
|
||||
// exclusively on TI's microcontroller products. The software is owned by
|
||||
// TI and/or its suppliers, and is protected under applicable copyright
|
||||
// laws. You may not combine this software with "viral" open-source
|
||||
// software in order to form a larger program.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
|
||||
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
|
||||
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
|
||||
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
|
||||
// DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 6288 of the Stellaris USB Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __USBIDS_H__
|
||||
#define __USBIDS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TI Vendor ID.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_VID_TI 0x0000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Product IDs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_PID_MOUSE 0x0000
|
||||
#define USB_PID_KEYBOARD 0x0001
|
||||
#define USB_PID_SERIAL 0x0000
|
||||
#define USB_PID_BULK 0x0003
|
||||
#define USB_PID_SCOPE 0x0004
|
||||
#define USB_PID_MSC 0x0005
|
||||
#define USB_PID_AUDIO 0x0006
|
||||
#define USB_PID_COMP_SERIAL 0x0007
|
||||
#define USB_PID_COMP_AUDIO_HID 0x0008
|
||||
#define USB_PID_COMP_HID_SER 0x0009
|
||||
#define USB_PID_DFU 0x00FF
|
||||
|
||||
|
||||
#endif /* __USBIDS_H__ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,48 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// usb_serial_structs.h - Data structures defining this USB CDC device.
|
||||
//
|
||||
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Texas Instruments (TI) is supplying this software for use solely and
|
||||
// exclusively on TI's microcontroller products. The software is owned by
|
||||
// TI and/or its suppliers, and is protected under applicable copyright
|
||||
// laws. You may not combine this software with "viral" open-source
|
||||
// software in order to form a larger program.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
|
||||
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
|
||||
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
|
||||
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
|
||||
// DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef _USB_SERIAL_STRUCTS_H_
|
||||
#define _USB_SERIAL_STRUCTS_H_
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The size of the transmit and receive buffers used for the redirected UART.
|
||||
// This number should be a power of 2 for best performance. 256 is chosen
|
||||
// pretty much at random though the buffer should be at least twice the size of
|
||||
// a maxmum-sized USB packet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_BUFFER_SIZE 0x0001
|
||||
|
||||
extern uint32 RxHandler(void *pvCBData, uint32 ulEvent,
|
||||
uint32 ulMsgValue, void *pvMsgData);
|
||||
extern uint32 TxHandler(void *pvlCBData, uint32 ulEvent,
|
||||
uint32 ulMsgValue, void *pvMsgData);
|
||||
|
||||
extern const tUSBBuffer g_sTxBuffer;
|
||||
extern const tUSBBuffer g_sRxBuffer;
|
||||
extern const tUSBDCDCDevice g_sCDCDevice;
|
||||
extern uint8 g_pucUSBTxBuffer[];
|
||||
extern uint8 g_pucUSBRxBuffer[];
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,140 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// usbdevice.h - types and definitions used during USB enumeration.
|
||||
//
|
||||
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Texas Instruments (TI) is supplying this software for use solely and
|
||||
// exclusively on TI's microcontroller products. The software is owned by
|
||||
// TI and/or its suppliers, and is protected under applicable copyright
|
||||
// laws. You may not combine this software with "viral" open-source
|
||||
// software in order to form a larger program.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
|
||||
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
|
||||
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
|
||||
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
|
||||
// DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __USBDEVICE_H__
|
||||
#define __USBDEVICE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup device_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! The maximum number of independent interfaces that any single device
|
||||
//! implementation can support. Independent interfaces means interface
|
||||
//! descriptors with different bInterfaceNumber values - several interface
|
||||
//! descriptors offering different alternative settings but the same interface
|
||||
//! number count as a single interface.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_MAX_INTERFACES_PER_DEVICE 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The default USB endpoint FIFO configuration structure. This structure
|
||||
// contains definitions to set all USB FIFOs into single buffered mode with
|
||||
// no DMA use. Each endpoint's FIFO is sized to hold the largest maximum
|
||||
// packet size for any interface alternate setting in the current config
|
||||
// descriptor. A pointer to this structure may be passed in the psFIFOConfig
|
||||
// field of the tDeviceInfo structure passed to USBCDCInit if the application
|
||||
// does not require any special handling of the USB controller FIFO.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern const tFIFOConfig g_sUSBDefaultFIFOConfig;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Public APIs offered by the USB library device control driver.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void USBDCDInit(uint32 ulIndex, tDeviceInfo *psDevice);
|
||||
extern void USBDCDTerm(uint32 ulIndex);
|
||||
extern void USBDCDStallEP0(uint32 ulIndex);
|
||||
extern void USBDCDRequestDataEP0(uint32 ulIndex, uint8 *pucData,
|
||||
uint32 ulSize);
|
||||
extern void USBDCDSendDataEP0(uint32 ulIndex, uint8 *pucData,
|
||||
uint32 ulSize);
|
||||
extern void USBDCDSetDefaultConfiguration(uint32 ulIndex,
|
||||
uint32 ulDefaultConfig);
|
||||
extern uint32 USBDCDConfigDescGetSize(const tConfigHeader *psConfig);
|
||||
extern uint32 USBDCDConfigDescGetNum(const tConfigHeader *psConfig,
|
||||
uint32 ulType);
|
||||
extern tDescriptorHeader *USBDCDConfigDescGet(const tConfigHeader *psConfig,
|
||||
uint32 ulType,
|
||||
uint32 ulIndex,
|
||||
uint32 *pulSection);
|
||||
extern uint32
|
||||
USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
|
||||
uint8 ucInterfaceNumber);
|
||||
extern tInterfaceDescriptor *
|
||||
USBDCDConfigGetInterface(const tConfigHeader *psConfig,
|
||||
uint32 ulIndex, uint32 ulAltCfg,
|
||||
uint32 *pulSection);
|
||||
extern tEndpointDescriptor *
|
||||
USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
|
||||
uint32 ulInterfaceNumber,
|
||||
uint32 ulAltCfg,
|
||||
uint32 ulIndex);
|
||||
extern void USBDCDPowerStatusSet(uint32 ulIndex, uint8 ucPower);
|
||||
extern tBoolean USBDCDRemoteWakeupRequest(uint32 ulIndex);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Early releases of the USB library had the following function named
|
||||
// incorrectly. This macro ensures that any code which used the previous name
|
||||
// will still operate as expected.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define USBCDCConfigGetInterfaceEndpoint(a, b, c, d) \
|
||||
USBDCDConfigGetInterfaceEndpoint((a), (b), (c), (d))
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Device mode interrupt handler for controller index 0.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void USB0DeviceIntHandler(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __USBENUM_H__
|
||||
@@ -0,0 +1,65 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// usbdevicepriv.h - Private header file used to share internal variables and
|
||||
// function prototypes between the various device-related
|
||||
// modules in the USB library. This header MUST NOT be
|
||||
// used by application code.
|
||||
//
|
||||
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Texas Instruments (TI) is supplying this software for use solely and
|
||||
// exclusively on TI's microcontroller products. The software is owned by
|
||||
// TI and/or its suppliers, and is protected under applicable copyright
|
||||
// laws. You may not combine this software with "viral" open-source
|
||||
// software in order to form a larger program.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
|
||||
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
|
||||
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
|
||||
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
|
||||
// DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __USBDEVICEPRIV_H__
|
||||
#define __USBDEVICEPRIV_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Device enumeration functions provided by device/usbenum.c and called from
|
||||
// the interrupt handler in device/usbhandler.c
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern tBoolean USBDeviceConfig(uint32 ulIndex,
|
||||
const tConfigHeader *psConfig,
|
||||
const tFIFOConfig *psFIFOConfig);
|
||||
extern tBoolean USBDeviceConfigAlternate(uint32 ulIndex,
|
||||
const tConfigHeader *psConfig,
|
||||
uint8 ucInterfaceNum,
|
||||
uint8 ucAlternateSetting);
|
||||
extern void USBDeviceResumeTickHandler(uint32 ulIndex);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __USBDEVICEPRIV_H__
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,56 @@
|
||||
Generic
|
||||
-------
|
||||
/*SAFETYMCUSW 26 S MR:12.3 <REVIEWED> "Infinite loops needed" */
|
||||
/*SAFETYMCUSW 69 S MR:12.2 <REVIEWED> "pragma for interrupts a must" */
|
||||
/*SAFETYMCUSW 134 S MR:12.3 <REVIEWED> "Volatile variables in expressions cannot be avoided" */
|
||||
/*SAFETYMCUSW 139 S MR:13.7 <REVIEWED> "GUI parameter substitution is a feature" */
|
||||
/*SAFETYMCUSW 139 S MR:13.7 <REVIEWED> "LDRA-Space around -> or [] can be ignored" */
|
||||
/*SAFETYMCUSW 440 S MR:11.3 <REVIEWED> "Casting for #defines" */
|
||||
/*SAFETYMCUSW 5 C MR: <REVIEWED> "Infinite loops needed" */
|
||||
/*SAFETYMCUSW 28 D MR: <REVIEWED> "Infinite loops needed" */
|
||||
/*SAFETYMCUSW 24 D MR:8.1 <REVIEWED> "ISR’s declaration is there in the vector table" */
|
||||
/*SAFETYMCUSW 30 S MR:12.2 <REVIEWED> "++ and -- usage cannot be avoided" */
|
||||
(Advisory)
|
||||
/*SAFETYMCUSW 189 S MR: <REVIEWED> "Input lines may exceed" */
|
||||
/*SAFETYMCUSW 62 D MR:16.7 <REVIEWED> "Pointer parameters to be const" */
|
||||
|
||||
Module Specific
|
||||
---------------
|
||||
/*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
|
||||
/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
|
||||
/*SAFETYMCUSW 96 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */
|
||||
/*SAFETYMCUSW 488 S MR:10.1 <REVIEWED> "Cannot avoid multiple OR’ing" */
|
||||
/*SAFETYMCUSW 493 S MR:21.1 <REVIEWED> "Cannot avoid multiple OR’ing" */
|
||||
/*SAFETYMCUSW 45 D MR:21.1 <REVIEWED> "Pointer NULL check needs structural change in the Halcogen" */
|
||||
/*SAFETYMCUSW 63 S MR:11.1 <REVIEWED> "LDRA-Definitions for gio.h and system.h already present" */
|
||||
/*SAFETYMCUSW 77 D MR:17.6 <REVIEWED> "LDRA-Structure Pass By Value is appropriate" */
|
||||
(Advisory)
|
||||
/*SAFETYMCUSW 88 S MR:2.1 <REVIEWED> "Assembly in C" */
|
||||
/*SAFETYMCUSW 93 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */
|
||||
|
||||
Startup code
|
||||
------------
|
||||
/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
|
||||
/*SAFETYMCUSW 122 S MR:20.11 <REVIEWED> "Startup code(exit and abort need to be present)" */
|
||||
/*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */
|
||||
/*SAFETYMCUSW 298 S MR: <REVIEWED> "Startup code(handler pointers)" */
|
||||
/*SAFETYMCUSW 299 S MR: <REVIEWED> "Startup code(typedef for handler pointers in library )" */
|
||||
/*SAFETYMCUSW 326 S MR:8.2 <REVIEWED> "Startup code(Declaration for main in library)" */
|
||||
/*SAFETYMCUSW 60 D MR:8.8 <REVIEWED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
|
||||
/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
|
||||
/*SAFETYMCUSW 354 S MR:1.4 <REVIEWED> " Startup code(Extern declaration present in the library)" */
|
||||
(Advisory)
|
||||
/*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
|
||||
|
||||
EMAC and MDIO
|
||||
-------------
|
||||
/*SAFETYMCUSW 95 S MR:11.1 <REVIEWED> "EMAC & MDIO-Casting operation to a pointer" */
|
||||
/*SAFETYMCUSW 340 S MR:19.7 <REVIEWED> "EMAC & MDIO-Function like Macro" */
|
||||
/*SAFETYMCUSW 384 S MR:5.1 <REVIEWED> "EMAC & MDIO-Size of Macro" */
|
||||
/*SAFETYMCUSW 446 S MR:10.1 <REVIEWED> "EMAC & MDIO-Narrower int conversion without cast" */
|
||||
/*SAFETYMCUSW 436 S MR:17.1 <REVIEWED> "EMAC & MDIO-Array declaration issue" */
|
||||
/*SAFETYMCUSW 7 C MR:14.7 <REVIEWED> "EMAC & MDIO-More than one exit" */
|
||||
(Advisory)
|
||||
/*SAFETYMCUSW 185 S MR: <REVIEWED> "EMAC & MDIO-space >< unary operators" */
|
||||
/*SAFETYMCUSW 25 D MR:8.7 <REVIEWED> "EMAC & MDIO-scope of the variable to be reduced" */
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
;-------------------------------------------------------------------------------
|
||||
; dabort.asm
|
||||
;
|
||||
; (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
;
|
||||
|
||||
.text
|
||||
.arm
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Run Memory Test
|
||||
|
||||
.ref custom_dabort
|
||||
.def _dabort
|
||||
.asmfunc
|
||||
|
||||
_dabort
|
||||
stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
|
||||
|
||||
ldr r12, esmsr3 ; ESM Group3 status register
|
||||
ldr r0, [r12]
|
||||
tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
|
||||
bne ramErrorFound
|
||||
tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
|
||||
bne ramErrorFound
|
||||
|
||||
noRAMerror
|
||||
tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
|
||||
bne flashErrorFound
|
||||
|
||||
bl custom_dabort ; custom data abort handler required
|
||||
; If this custom handler is written in assembly, all registers used in the routine
|
||||
; and the link register must be saved on to the stack upon entry, and restored before
|
||||
; return from the routine.
|
||||
|
||||
ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
|
||||
subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
|
||||
|
||||
ramErrorFound
|
||||
ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
|
||||
ldr r2, [r1]
|
||||
tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
|
||||
beq ramErrorReal
|
||||
mov r2, #0x20
|
||||
str r2, [r1, #0x10] ; clear RAM error status register
|
||||
ldr r1, ram2ctrl
|
||||
str r2, [r1, #0x10] ; clear RAM error status register
|
||||
|
||||
mov r2, #0x28
|
||||
str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors
|
||||
mov r2, #5
|
||||
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
|
||||
|
||||
ldmfd r13!, {r0 - r12, lr}
|
||||
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
|
||||
; this is the case because the data abort was caused intentionally
|
||||
; and we do not want to cause the same data abort again.
|
||||
|
||||
ramErrorReal
|
||||
b ramErrorReal ; branch here forever as continuing operation is not recommended
|
||||
|
||||
flashErrorFound
|
||||
ldr r1, flashbase
|
||||
ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
|
||||
|
||||
mov r2, r2, lsr #16
|
||||
tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
|
||||
beq flashErrorReal
|
||||
mov r2, #1
|
||||
mov r2, r2, lsl #8
|
||||
|
||||
str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
|
||||
|
||||
mov r2, #0x80
|
||||
str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
|
||||
mov r2, #5
|
||||
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
|
||||
|
||||
ldmfd r13!, {r0 - r12, lr}
|
||||
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
|
||||
; this is the case because the data abort was caused intentionally
|
||||
; and we do not want to cause the same data abort again.
|
||||
|
||||
|
||||
flashErrorReal
|
||||
b flashErrorReal ; branch here forever as continuing operation is not recommended
|
||||
|
||||
esmsr3 .word 0xFFFFF520
|
||||
ramctrl .word 0xFFFFF800
|
||||
ram2ctrl .word 0xFFFFF900
|
||||
ram1errstat .word 0xFFFFF810
|
||||
ram2errstat .word 0xFFFFF910
|
||||
flashbase .word 0xFFF87000
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,125 @@
|
||||
/** @file notification.c
|
||||
* @brief User Notification Definition File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file defines empty notification routines to avoid
|
||||
* linker errors, Driver expects user to define the notification.
|
||||
* The user needs to either remove this file and use their custom
|
||||
* notification function or place their code sequence in this file
|
||||
* between the provided USER CODE BEGIN and USER CODE END.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Include Files */
|
||||
|
||||
#include "esm.h"
|
||||
#include "sys_selftest.h"
|
||||
#include "gio.h"
|
||||
#include "sci.h"
|
||||
#include "rti.h"
|
||||
#include "sys_dma.h"
|
||||
/* USER CODE BEGIN (0) */
|
||||
#include <stdint.h>
|
||||
/* USER CODE END */
|
||||
|
||||
void esmGroup1Notification(uint32 channel)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (2) */
|
||||
/* USER CODE END */
|
||||
|
||||
void esmGroup2Notification(uint32 channel)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (3) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (4) */
|
||||
/* USER CODE END */
|
||||
|
||||
void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (5) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (6) */
|
||||
/* USER CODE END */
|
||||
|
||||
void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (7) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (8) */
|
||||
/* USER CODE END */
|
||||
void rtiNotification(uint32 notification)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (9) */
|
||||
sciSendByte(scilinREG, 'I');
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (10) */
|
||||
/* USER CODE END */
|
||||
void gioNotification(gioPORT_t *port, sint32 bit)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (19) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (20) */
|
||||
/* USER CODE END */
|
||||
|
||||
void sciNotification(sciBASE_t *sci, uint32 flags)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (29) */
|
||||
if (sci == scilinREG && flags == SCI_RX_INT)
|
||||
{
|
||||
}
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (30) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (43) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/* USER CODE BEGIN (47) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/* USER CODE BEGIN (50) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/* USER CODE BEGIN (53) */
|
||||
/* USER CODE END */
|
||||
|
||||
void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
|
||||
{
|
||||
/* enter user code between the USER CODE BEGIN and USER CODE END. */
|
||||
/* USER CODE BEGIN (54) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
/* USER CODE BEGIN (55) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* USER CODE BEGIN (56) */
|
||||
/* USER CODE END */
|
||||
@@ -0,0 +1,121 @@
|
||||
/** @file pinmux.c
|
||||
* @brief PINMUX Driver Inmplmentation File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
/* Include Files */
|
||||
|
||||
#include "pinmux.h"
|
||||
|
||||
#define PINMUX_SET(REG, BALLID, MUX) \
|
||||
pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
|
||||
|
||||
#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \
|
||||
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
|
||||
|
||||
#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
|
||||
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
|
||||
|
||||
#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
|
||||
pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
|
||||
|
||||
#define PINMUX_ETHERNET_SELECT(interface) \
|
||||
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
void muxInit(void){
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Enable Pin Muxing */
|
||||
kickerReg->KICKER0 = 0x83E70B13U;
|
||||
kickerReg->KICKER1 = 0x95A4F1E0U;
|
||||
|
||||
/* USER CODE BEGIN (2) */
|
||||
/* USER CODE END */
|
||||
|
||||
pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
|
||||
|
||||
pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
|
||||
|
||||
pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
|
||||
|
||||
pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
|
||||
|
||||
pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
|
||||
|
||||
pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
|
||||
|
||||
pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
|
||||
|
||||
pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
|
||||
|
||||
pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
|
||||
|
||||
pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
|
||||
|
||||
pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
|
||||
|
||||
pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
|
||||
|
||||
pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
|
||||
|
||||
pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
|
||||
|
||||
pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
|
||||
|
||||
pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
|
||||
|
||||
pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
|
||||
|
||||
pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
|
||||
|
||||
pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
|
||||
|
||||
pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
|
||||
|
||||
pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
|
||||
|
||||
pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
|
||||
|
||||
pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
|
||||
|
||||
pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
|
||||
|
||||
pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
|
||||
|
||||
pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
|
||||
|
||||
pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
|
||||
|
||||
pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
|
||||
|
||||
pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
|
||||
|
||||
pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
|
||||
|
||||
PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
|
||||
PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
|
||||
PINMUX_ALT_ADC_TRIGGER_SELECT(1);
|
||||
PINMUX_ETHERNET_SELECT(RMII);
|
||||
|
||||
/* USER CODE BEGIN (3) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Disable Pin Muxing */
|
||||
kickerReg->KICKER0 = 0x00000000U;
|
||||
kickerReg->KICKER1 = 0x00000000U;
|
||||
|
||||
/* USER CODE BEGIN (4) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (5) */
|
||||
/* USER CODE END */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,44 @@
|
||||
;-------------------------------------------------------------------------------
|
||||
; sys_intvecs.asm
|
||||
;
|
||||
; (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
;
|
||||
|
||||
.sect ".intvecs"
|
||||
.arm
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; import reference for interrupt routines
|
||||
|
||||
.ref _c_int00
|
||||
.ref _dabort
|
||||
.ref IRQ_Handler
|
||||
|
||||
.def resetEntry
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; interrupt vectors
|
||||
|
||||
resetEntry
|
||||
b _c_int00
|
||||
b turnon_VFP
|
||||
svcEntry
|
||||
b svcEntry
|
||||
prefetchEntry
|
||||
b prefetchEntry
|
||||
b _dabort
|
||||
reservedEntry
|
||||
b reservedEntry
|
||||
b IRQ_Handler
|
||||
ldr pc,[pc,#-0x1b0]
|
||||
|
||||
.sect ".text"
|
||||
turnon_VFP
|
||||
; Enable FPV
|
||||
STMDB sp!, {r0}
|
||||
fmrx r0, fpexc
|
||||
orr r0, r0, #0x40000000
|
||||
fmxr fpexc, r0
|
||||
LDMIA sp!, {r0}
|
||||
subs pc, lr, #4
|
||||
;-------------------------------------------------------------------------------
|
||||
@@ -0,0 +1,85 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* sys_link.cmd */
|
||||
/* */
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
/* */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN (7) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Linker Settings */
|
||||
|
||||
--retain="*(.intvecs)"
|
||||
--retain="*(FSymTab)"
|
||||
--retain="*(VSymTab)"
|
||||
|
||||
/* USER CODE BEGIN (8) */
|
||||
/* USER CODE END */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Memory Map */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (X) : origin=0x00000000 length=0x00000020
|
||||
FLASH0 (RX) : origin=0x00000020 length=0x0017FFE0
|
||||
FLASH1 (RX) : origin=0x00180000 length=0x00180000
|
||||
STACKS (RW) : origin=0x08000000 length=0x00001500
|
||||
RAM (RW) : origin=0x08001500 length=0x0003eaff
|
||||
|
||||
/* USER CODE BEGIN (9) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (10) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Section Configuration */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.intvecs : {} > VECTORS
|
||||
.text : {} > FLASH0 | FLASH1
|
||||
.const : {} > FLASH0 | FLASH1
|
||||
.cinit : {} > FLASH0 | FLASH1
|
||||
.pinit : {} > FLASH0 | FLASH1
|
||||
GROUP
|
||||
{
|
||||
.bss : {}
|
||||
.data : {}
|
||||
.sysmem : {}
|
||||
._dummy : {system_data_end = .;}
|
||||
} > RAM
|
||||
|
||||
|
||||
/* USER CODE BEGIN (11) */
|
||||
/* place this section in the last section in RAM. The brain damaged linker
|
||||
* could only create symbols in sections. */
|
||||
._FSymTab : {
|
||||
__fsymtab_start = .;
|
||||
*(FSymTab)
|
||||
__fsymtab_end = .;
|
||||
} > FLASH0 | FLASH1
|
||||
._VSymTab : {
|
||||
__vsymtab_start = .;
|
||||
*(VSymTab)
|
||||
__vsymtab_end = .;
|
||||
} > FLASH0 | FLASH1
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (12) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Misc */
|
||||
|
||||
/* USER CODE BEGIN (13) */
|
||||
/* USER CODE END */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
/** @file sys_main.c
|
||||
* @brief Application main file
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains an empty main function,
|
||||
* which can be used for the application.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* we will use our own main and get rid off everything from HALCoGen here */
|
||||
#if 0
|
||||
#include <stdint.h>
|
||||
/* USER CODE END */
|
||||
|
||||
/* Include Files */
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "system.h"
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
|
||||
/* Include HET header file - types, definitions and function declarations for system driver */
|
||||
#include "het.h"
|
||||
#include "esm.h"
|
||||
#include "sci.h"
|
||||
#include "rti.h"
|
||||
|
||||
/* Task1 */
|
||||
void vTaskDelay(int t)
|
||||
{
|
||||
for (; t; t--)
|
||||
{
|
||||
int i;
|
||||
for(i = 100000;i ; i--)
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
/* USER CODE END */
|
||||
|
||||
/** @fn void main(void)
|
||||
* @brief Application main function
|
||||
* @note This function is empty by default.
|
||||
*
|
||||
* This function is called after startup.
|
||||
* The user can use this function to implement the application.
|
||||
*/
|
||||
|
||||
/* USER CODE BEGIN (2) */
|
||||
uint8_t sci_buf;
|
||||
/* USER CODE END */
|
||||
|
||||
void main(void)
|
||||
{
|
||||
/* USER CODE BEGIN (3) */
|
||||
|
||||
/* Set high end timer GIO port hetPort pin direction to all output */
|
||||
gioSetDirection(hetPORT1, 0xFFFFFFFF);
|
||||
sciInit();
|
||||
rtiInit();
|
||||
rtiStartCounter(rtiCOUNTER_BLOCK1);
|
||||
rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
|
||||
_enable_IRQ();
|
||||
sciReceive(scilinREG, 1, &sci_buf);
|
||||
|
||||
for(;;)
|
||||
{
|
||||
gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
|
||||
/* Taggle HET[1] with timer tick */
|
||||
/*sciSendByte(scilinREG, 'b');*/
|
||||
vTaskDelay(100);
|
||||
/*sciSendByte(scilinREG, 'a');*/
|
||||
}
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (4) */
|
||||
#endif
|
||||
/* USER CODE END */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,32 @@
|
||||
/** @file sys_phantom.c
|
||||
* @brief Phantom Interrupt Source File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Phantom Interrupt Handler
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Phantom Interrupt Handler */
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
#pragma CODE_STATE(phantomInterrupt, 32)
|
||||
#pragma INTERRUPT(phantomInterrupt, IRQ)
|
||||
|
||||
void phantomInterrupt(void)
|
||||
{
|
||||
/* USER CODE BEGIN (2) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (3) */
|
||||
/* USER CODE END */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
Loaded 100 of 125 files, more files were not shown because too many files have changed in this diff.
Show more
Reference in new issue
Block a user