[BSP][GD32]add gd32e503v-eval

.github/workflows/bsp_buildings.yml

@@ -278,6 +278,7 @@ jobs:
                 - "gd32/arm/gd32450z-eval" 
                 - "gd32/arm/gd32470z-lckfb"
                 - "gd32/arm/gd32h759i-start"
+                - "gd32/arm/gd32e503v-eval"
                 - "n32/n32g43xcl-stb"
                 - "n32/n32g45xcl-stb"
                 - "n32/n32g45xml-stb"

bsp/gd32/arm/README.md

@@ -22,6 +22,8 @@ GD32 ARM 系列 BSP 目前支持情况如下表所示：
 | [gd32407v-lckfb](gd32407v-lckfb) | 立创天空星  GD32F407VET6 开发板 |
 | [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
 | [gd32470z-lckfb](gd32470z-lckfb) | 立创梁山派  GD32F470ZGT6 开发板 |
+| **E5 系列** |  |
+| [gd32e503v-eval](gd32e503v-eval) | 兆易创新 官方 GD32E503V-EVAL 开发板 |
 
 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
 

bsp/gd32/arm/gd32e503v-eval/Kconfig

@@ -0,0 +1,12 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../../..
+
+PKGS_DIR := packages
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+rsource "board/Kconfig"

bsp/gd32/arm/gd32e503v-eval/README.md

@@ -0,0 +1,107 @@
+# GD32E503V-EVAL 开发板 BSP 说明
+
+## 简介
+
+GD32E503V-EVAL 评估板使用 GD32E503VET6 作为主控制器。评估板使用 GD-Link Mini
+USB 接口提供 5V 电源。提供包括扩展引脚在内的及 Reset， Boot， K2， LED， I2S， I2CEEPROM， LCD， NAND Flash， SPI-Flash， SDIO， USB， USART 转 USB 接口等外设资源。
+
+该开发板常用 ** 板载资源 ** 如下：
+
+- GD32E503VET6，主频 180MHz，512KB FLASH ，128KB RAM
+- 常用外设
+
+  - LED ：5 个，LEDPWR (电源指示灯），LED1（PC0），LED2（PC2），LED3（PE0），LED4（PE1）
+  - 按键：5 个，KEY_A（用户按键，PA0），KEY_B（用户按键，PC13），KEY_C（用户按键，PB14），KEY_D（用户按键，PC5），KEY_Cet（用户按键，PC4）
+  - General TM * 10、Advanced TM * 2、Basic TM * 2
+  - 系统时钟 * 1
+  - 看门狗 * 2
+  - RTC * 1
+  - USART * 4、UART * 2
+  - I2C * 2、I2S * 2
+  - SPI * 3
+  - CAN2.0B * 1
+  - USB2.0 OTG FS * 1
+  - TFT-LCD
+  - EXMC/SDRAM * 1
+  - ADC * 3
+  - DAC * 2
+  - 最多支持 100GPIOs
+- 常用接口：USB 接口
+- 调试接口：GD-LINK
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| ** 片上外设 ** | ** 支持情况 ** | ** 备注 **                   |
+| :----------- | :----------: | :------------------------------- |
+| GPIO         |     支持     | PA0, PA1... ---> PIN: 0, 1...111 |
+| UART         |     支持     | UART0 - UART5                    |
+| I2C          |     支持     | I2C1                             |
+| SPI          |     支持     | SPI0 - SPI2                      |
+| SPI FLASH    |     支持     |                                  |
+| ADC          |     支持     | ADC0 - ADC2                      |
+| ** 扩展模块 ** | ** 支持情况 ** | ** 备注 **                   |
+| 暂无         |   暂不支持   | 暂不支持                         |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境，也可使用 RT-Thread Studio 开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用 USB 转 232 连接 USART1，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 GD-Link  仿真器下载程序，在通过 GD-Link  连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.4 build Jan  9 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
+
+3. 输入 `pkgs --update` 命令更新软件包。
+
+4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [drifting1024](https://github.com/drifting1024), 邮箱：<drifting1024@163.com>

bsp/gd32/arm/gd32e503v-eval/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/gd32/arm/gd32e503v-eval/SConstruct

@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+gd32_library = 'GD32E50x_Firmware_Library'
+rtconfig.BSP_LIBRARY_TYPE = gd32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/gd32/arm/gd32e503v-eval/applications/SConscript

@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/gd32/arm/gd32e503v-eval/applications/main.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-20     BruceOu      first implementation
+ */
+
+#include <stdio.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED1 pin: PC0 */
+#define LED1_PIN GET_PIN(C, 0)
+
+int main(void)
+{
+    int count = 1;
+
+    /* set LED1 pin mode to output */
+    rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED1_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED1_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}

bsp/gd32/arm/gd32e503v-eval/board/SConscript

@@ -0,0 +1,26 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path =  [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += [startup_path_prefix + '/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32e50x_hd.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+    src += [startup_path_prefix + '/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32e50x_hd.s']
+
+CPPDEFINES = ['GD32E50X', 'GD32E50X_HD']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/gd32/arm/gd32e503v-eval/board/board.c

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2024-10-23     drifting1024   first implementation
+ */
+#include <stdint.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+
+#ifdef RT_USING_SERIAL_V2
+#include "drv_usart_v2.h"
+#else
+#include "drv_usart.h"
+#endif
+
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void Error_Handler(void)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+    /* NVIC Configuration */
+#define NVIC_VTOR_MASK              0x3FFFFF80
+#ifdef  VECT_TAB_RAM
+    /* Set the Vector Table base location at 0x10000000 */
+    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+#else  /* VECT_TAB_FLASH  */
+    /* Set the Vector Table base location at 0x08000000 */
+    SCB->VTOR  = (0x08000000 & NVIC_VTOR_MASK);
+#endif
+
+    SystemClock_Config();
+
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+#ifdef BSP_USING_SDRAM
+    rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
+#else
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/gd32/arm/gd32e503v-eval/board/board.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2024-10-23     drifting1024   first implementation
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "gd32e50x.h"
+#include "drv_gpio.h"
+
+#include "gd32e50x_exti.h"
+
+#define EXT_SDRAM_BEGIN    (0xC0000000U) /* the begining address of external SDRAM */
+#define EXT_SDRAM_END      (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
+
+/* <o> Internal SRAM memory size[Kbytes] <96-128>*/
+/*  <i>Default: 128*/
+#ifdef __ICCARM__
+/* Use *.icf ram symbal, to avoid hardcode.*/
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END          &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE         128
+#define GD32_SRAM_END          (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN    (&__bss_end)
+#endif
+
+#define HEAP_END          GD32_SRAM_END
+
+#endif
+

bsp/gd32/arm/gd32e503v-eval/board/gd32e50x_libopt.h

@@ -0,0 +1,100 @@
+/*!
+    \file    gd32e50x_libopt.h
+    \brief   library optional for gd32e50x
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_LIBOPT_H
+#define GD32E50X_LIBOPT_H
+
+#ifndef GD32EPRT
+
+#include "gd32e50x_adc.h"
+#include "gd32e50x_bkp.h"
+#include "gd32e50x_can.h"
+#include "gd32e50x_crc.h"
+#include "gd32e50x_ctc.h"
+#include "gd32e50x_dac.h"
+#include "gd32e50x_dbg.h"
+#include "gd32e50x_dma.h"
+#include "gd32e50x_exmc.h"
+#include "gd32e50x_exti.h"
+#include "gd32e50x_fmc.h"
+#include "gd32e50x_fwdgt.h"
+#include "gd32e50x_gpio.h"
+#include "gd32e50x_shrtimer.h"
+#include "gd32e50x_i2c.h"
+#include "gd32e50x_misc.h"
+#include "gd32e50x_pmu.h"
+#include "gd32e50x_rcu.h"
+#include "gd32e50x_rtc.h"
+#include "gd32e50x_spi.h"
+#include "gd32e50x_timer.h"
+#include "gd32e50x_usart.h"
+#include "gd32e50x_wwdgt.h"
+#include "gd32e50x_sqpi.h"
+
+#if defined (GD32E50X_CL) || defined (GD32E508)
+#include "gd32e50x_enet.h"
+#include "gd32e50x_tmu.h"
+#include "gd32e50x_cmp.h"
+#else /* GD32E50X_CL or GD32E508 */
+#include "gd32e50x_sdio.h"
+#endif /* GD32E50X_CL or GD32E508 */
+
+#else /* GD32EPRT */
+#include "gd32e50x_adc.h"
+#include "gd32e50x_bkp.h"
+#include "gd32e50x_crc.h"
+#include "gd32e50x_ctc.h"
+#include "gd32e50x_dac.h"
+#include "gd32e50x_dbg.h"
+#include "gd32e50x_dma.h"
+#include "gd32e50x_enet.h"
+#include "gd32e50x_exmc.h"
+#include "gd32e50x_exti.h"
+#include "gd32e50x_fmc.h"
+#include "gd32e50x_fwdgt.h"
+#include "gd32e50x_gpio.h"
+#include "gd32e50x_i2c.h"
+#include "gd32e50x_misc.h"
+#include "gd32e50x_pmu.h"
+#include "gd32e50x_rcu.h"
+#include "gd32e50x_rtc.h"
+#include "gd32e50x_spi.h"
+#include "gd32e50x_timer.h"
+#include "gd32e50x_usart.h"
+#include "gd32e50x_wwdgt.h"
+#include "gd32e50x_sqpi.h"
+
+#endif /* GD32EPRT */
+
+#endif /* GD32E50X_LIBOPT_H */

bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x201FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__   = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM1_region  = mem:[from __region_RAM1_start__   to __region_RAM1_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in RAM1_region  { section .sram };

bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.ld

@@ -0,0 +1,142 @@
+/*
+ * linker script for GD32E50x with GNU ld
+ * BruceOu 2021-12-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/gd32/arm/gd32e503v-eval/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/gd32/arm/gd32e503v-eval/rtconfig.h

@@ -0,0 +1,161 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+/* end of kservice optimization */
+
+/* klibc optimization */
+
+/* end of klibc optimization */
+#define RT_USING_DEBUG
+#define RT_DEBUGING_ASSERT
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+#define RT_USING_OVERFLOW_CHECK
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+/* end of Memory Management */
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50200
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+/* end of DFS: device virtual file system */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+/* end of Device Drivers */
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
+
+/* Network */
+
+/* end of Network */
+
+/* Memory protection */
+
+/* end of Memory protection */
+
+/* Utilities */
+
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
+
+/* RT-Thread Utestcases */
+
+/* end of RT-Thread Utestcases */
+
+/* Hardware Drivers Config */
+
+/* SOC Series */
+
+#define SOC_SERIES_GD32E50x
+#define SOC_GD32503V
+/* end of SOC Series */
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+/* end of On-chip Peripheral Drivers */
+
+/* Board extended module Drivers */
+
+/* end of Hardware Drivers Config */
+
+#endif

bsp/gd32/arm/gd32e503v-eval/rtconfig.py

@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM = 'iccarm'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/gd32/arm/gd32e503v-eval/template.uvoptx

@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U59503607 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Include/system_gd32e50x.h

@@ -0,0 +1,50 @@
+/*!
+    \file  system_gd32e50x.h
+    \brief CMSIS Cortex-M33 Device Peripheral Access Layer Header File for
+           GD32E50x Device Series
+*/
+
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2023, GigaDevice Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32E50X_H
+#define SYSTEM_GD32E50X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit (void);
+/* update the SystemCoreClock with current core clock retrieved from CPU registers */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32E50X_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/CMSIS/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/CMSIS/mpu_armv7.h

@@ -0,0 +1,182 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for ARMv7 MPU
+ * @version  V5.0.2
+ * @date     09. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0u
+#define ARM_MPU_AP_PRIV 1u
+#define ARM_MPU_AP_URO  2u
+#define ARM_MPU_AP_FULL 3u
+#define ARM_MPU_AP_PRO  5u
+#define ARM_MPU_AP_RO   6u
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
+
+/**
+* MPU Region Attribut and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((DisableExec      << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+  ((AccessPermission << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+  ((TypeExtField     << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+  ((IsShareable      << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+  ((IsCacheable      << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+  ((IsBufferable     << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+  ((SubRegionDisable << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+  ((Size             << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+  ((1UL              << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _ARM_MPU_Region_t {
+  uint32_t RBAR; /*!< The region base address register value (RBAR)*/
+  uint32_t RASR; /*!< The region attribute and size register value (RASR) \ref MPU_RASR*/
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable()
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0u;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0u; i < len; ++i)
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
+}
+
+#endif

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/CMSIS/tz_context.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/*/ \details Data type that identifies secure software modules called by a process.*/
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/*/ \details TZ Memory ID identifies an allocated memory slot.*/
+typedef uint32_t TZ_MemoryId_t;
+
+/*/ Initialize secure context memory system*/
+/*/ \return execution status (1: success, 0: error)*/
+uint32_t TZ_InitContextSystem_S (void);
+
+/*/ Allocate context memory for calling secure software modules in TrustZone*/
+/*/ \param[in]  module   identifies software modules called from non-secure mode*/
+/*/ \return value != 0 id TrustZone memory slot identifier*/
+/*/ \return value 0    no memory available or internal error*/
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/*/ Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S*/
+/*/ \param[in]  id  TrustZone memory slot identifier*/
+/*/ \return execution status (1: success, 0: error)*/
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/*/ Load secure context (called on RTOS thread context switch)*/
+/*/ \param[in]  id  TrustZone memory slot identifier*/
+/*/ \return execution status (1: success, 0: error)*/
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/*/ Store secure context (called on RTOS thread context switch)*/
+/*/ \param[in]  id  TrustZone memory slot identifier*/
+/*/ \return execution status (1: success, 0: error)*/
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif  /* TZ_CONTEXT_H*/

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_cmp.h

@@ -0,0 +1,131 @@
+/*!
+    \file    gd32e50x_cmp.h
+    \brief   definitions for the CMP
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_CMP_H
+#define GD32E50X_CMP_H
+
+#include "gd32e50x.h"
+
+#ifdef GD32E50X_CL
+
+/* CMP definitions */
+#define CMP                                      CMP_BASE                       /*!< CMP base address */
+
+/* registers definitions */
+#define CMP1_CS                                  REG32((CMP) + 0x00000020U)     /*!< CMP1 control and status register */
+#define CMP3_CS                                  REG32((CMP) + 0x00000028U)     /*!< CMP3 control and status register */
+#define CMP5_CS                                  REG32((CMP) + 0x00000030U)     /*!< CMP5 control and status register */
+
+/* bits definitions */
+/* CMPx_CS */
+#define CMP_CS_CMPXEN                            BIT(0)                         /*!< CMPx enable */
+#define CMP_CS_CMPXMSEL                          BITS(4,6)                      /*!< CMPx_IM input selection */
+#define CMP_CS_CMPXOSEL                          BITS(10,13)                    /*!< CMPx output selection */
+#define CMP_CS_CMPXPL                            BIT(15)                        /*!< CMPx output polarity */
+#define CMP_CS_CMPXBLK                           BITS(18,20)                    /*!< CMPx output blanking source */
+#define CMP_CS_CMPXMSEL_3                        BIT(22)                        /*!< bit3 of CMPx_CS_CMPxMSEL */
+#define CMP_CS_CMPXO                             BIT(30)                        /*!< CMPx output */
+#define CMP_CS_CMPXLK                            BIT(31)                        /*!< CMPx lock */
+
+/* constants definitions */
+/* CMP units */
+typedef enum{
+    CMP1,                                                                       /*!< comparator 1 */
+    CMP3,                                                                       /*!< comparator 3 */
+    CMP5                                                                        /*!< comparator 5 */
+}cmp_enum;
+
+/* CMP inverting input */
+#define CS_CMPXMSEL(regval)                      (BITS(4,6) & ((uint32_t)(regval) << 4U))
+#define CMP_INVERTING_INPUT_1_4VREFINT           CS_CMPXMSEL(0)                 /*!< CMP inverting input 1/4 Vrefint */
+#define CMP_INVERTING_INPUT_1_2VREFINT           CS_CMPXMSEL(1)                 /*!< CMP inverting input 1/2 Vrefint */
+#define CMP_INVERTING_INPUT_3_4VREFINT           CS_CMPXMSEL(2)                 /*!< CMP inverting input 3/4 Vrefint */
+#define CMP_INVERTING_INPUT_VREFINT              CS_CMPXMSEL(3)                 /*!< CMP inverting input Vrefint */
+#define CMP_INVERTING_INPUT_DAC0_OUT0            CS_CMPXMSEL(4)                 /*!< CMP inverting input DAC */
+#define CMP_INVERTING_INPUT_PA5                  CS_CMPXMSEL(5)                 /*!< CMP inverting input PA5 */
+#define CMP_INVERTING_INPUT_PA2                  CS_CMPXMSEL(6)                 /*!< CMP inverting input PA2 only for CMP1 */
+#define CMP_INVERTING_INPUT_PB2_PB15             CS_CMPXMSEL(7)                 /*!< CMP inverting input PB2 for CMP3 or PB15 for CMP5 */
+
+/* CMP output */
+#define CS_CMPXOSEL(regval)                      (BITS(10,13) & ((uint32_t)(regval) << 10U))
+#define CMP_OUTPUT_NONE                          CS_CMPXOSEL(0)                 /*!< CMP output none */
+#define CMP_OUTPUT_TIMER0_BKIN                   CS_CMPXOSEL(1)                 /*!< CMP output TIMER0 break input */
+#define CMP_OUTPUT_TIMER2_IC2                    CS_CMPXOSEL(6)                 /*!< CMP output TIMER2_CH2 input capture only for CMP3 */
+#define CMP_OUTPUT_TIMER1_IC1                    CS_CMPXOSEL(6)                 /*!< CMP output TIMER1_CH1 input capture only for CMP5 */
+#define CMP_OUTPUT_TIMER0_IC0                    CS_CMPXOSEL(7)                 /*!< CMP output TIMER0_CH0 input capture only for CMP1 */
+#define CMP_OUTPUT_TIMER1_IC3                    CS_CMPXOSEL(8)                 /*!< CMP output TIMER1_CH3 input capture only for CMP1 */
+#define CMP_OUTPUT_TIMER2_IC0                    CS_CMPXOSEL(10)                /*!< CMP output TIMER2_CH0 input capture only for CMP1 */
+
+/* CMP output polarity*/
+#define CS_CMPXPL(regval)                        (BIT(15) & ((uint32_t)(regval) << 15U))
+#define CMP_OUTPUT_POLARITY_NONINVERTED          CS_CMPXPL(0)                   /*!< CMP output not inverted */
+#define CMP_OUTPUT_POLARITY_INVERTED             CS_CMPXPL(1)                   /*!< CMP output inverted */
+
+/* CMP blanking suorce */
+#define CS_CMPXBLK(regval)                       (BITS(18,20) & ((uint32_t)(regval) << 18U))
+#define CMP_BLANKING_NONE                        CS_CMPXBLK(0)                  /*!< CMP no blanking source */
+#define CMP_BLANKING_TIMER2_OC3                  CS_CMPXBLK(1)                  /*!< CMP TIMER2_CH3 output compare signal selected as blanking source only for CMP3 */
+#define CMP_BLANKING_TIMER1_OC2                  CS_CMPXBLK(2)                  /*!< CMP TIMER1_CH2 output compare signal selected as blanking source only for CMP1 */
+#define CMP_BLANKING_TIMER2_OC2                  CS_CMPXBLK(3)                  /*!< CMP TIMER2_CH2 output compare signal selected as blanking source only for CMP1 */
+#define CMP_BLANKING_TIMER1_OC3                  CS_CMPXBLK(3)                  /*!< CMP TIMER1_CH3 output compare signal selected as blanking source only for CMP5 */
+
+/* CMP output level */
+#define CMP_OUTPUTLEVEL_HIGH                     ((uint32_t)0x00000001U)        /*!< CMP output high */
+#define CMP_OUTPUTLEVEL_LOW                      ((uint32_t)0x00000000U)        /*!< CMP output low */
+
+/* function declarations */
+/* initialization functions */
+/* CMP deinit */
+void cmp_deinit(cmp_enum cmp_periph);
+/* CMP mode init */
+void cmp_mode_init(cmp_enum cmp_periph, uint32_t inverting_input);
+/* CMP output init */
+void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity);
+/* CMP output blanking function init */
+void cmp_blanking_init(cmp_enum cmp_periph,uint32_t blanking_source_selection);
+
+/* enable functions */
+/* enable CMP */
+void cmp_enable(cmp_enum cmp_periph);
+/* disable CMP */
+void cmp_disable(cmp_enum cmp_periph);
+/* lock the CMP */
+void cmp_lock_enable(cmp_enum cmp_periph);
+
+/* get state related functions */
+/* get output level */
+uint32_t cmp_output_level_get(cmp_enum cmp_periph);
+
+#endif /* GD32E50x_CL */
+#endif /* GD32E50X_CMP_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_crc.h

@@ -0,0 +1,123 @@
+/*!
+    \file    gd32e50x_crc.h
+    \brief   definitions for the CRC
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_CRC_H
+#define GD32E50X_CRC_H
+
+#include "gd32e50x.h"
+
+/* CRC definitions */
+#define CRC                            CRC_BASE                        /*!< CRC base address */
+
+/* registers definitions */
+#define CRC_DATA                       REG32((CRC) + 0x00000000U)      /*!< CRC data register */
+#define CRC_FDATA                      REG32((CRC) + 0x00000004U)      /*!< CRC free data register */
+#define CRC_CTL                        REG32((CRC) + 0x00000008U)      /*!< CRC control register */
+#define CRC_IDATA                      REG32((CRC) + 0x00000010U)      /*!< CRC initialization data register */
+#define CRC_POLY                       REG32((CRC) + 0x00000014U)      /*!< CRC polynomial register */
+
+/* bits definitions */
+/* CRC_DATA */
+#define CRC_DATA_DATA                  BITS(0, 31)                     /*!< CRC data */
+
+/* CRC_FDATA */
+#define CRC_FDATA_FDATA                BITS(0, 7)                      /*!< CRC free data */
+
+/* CRC_CTL */
+#define CRC_CTL_RST                    BIT(0)                          /*!< CRC reset */
+#define CRC_CTL_PS                     BITS(3, 4)                      /*!< size of polynomial */
+#define CRC_CTL_REV_I                  BITS(5, 6)                      /*!< input data reverse */
+#define CRC_CTL_REV_O                  BIT(7)                          /*!< output data reverse */
+
+/* CRC_IDATA */
+#define CRC_IDATA_IDATA                BITS(0, 31)                     /*!< CRC initialization data */
+
+/* CRC_POLY */
+#define CRC_POLY_POLY                  BITS(0, 31)                     /*!< CRC polynomial value */
+
+/* constants definitions */
+/* size of polynomial function */
+#define CTL_PS(regval)                 (BITS(3, 4) & ((regval) << 3))
+#define CRC_CTL_PS_32                  CTL_PS(0)                       /*!< 32-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_16                  CTL_PS(1)                       /*!< 16-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_8                   CTL_PS(2)                       /*!< 8-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_7                   CTL_PS(3)                       /*!< 7-bit polynomial for CRC calculation */
+
+/* input data reverse function */
+#define CTL_REV_I(regval)              (BITS(5, 6) & ((regval) << 5))
+#define CRC_INPUT_DATA_NOT             CTL_REV_I(0)                    /*!< input data not reverse */
+#define CRC_INPUT_DATA_BYTE            CTL_REV_I(1)                    /*!< input data reversed by byte type */
+#define CRC_INPUT_DATA_HALFWORD        CTL_REV_I(2)                    /*!< input data reversed by half-word type */
+#define CRC_INPUT_DATA_WORD            CTL_REV_I(3)                    /*!< input data reversed by word type */
+
+/* input data format */
+#define INPUT_FORMAT_WORD              0U                              /*!< input data in word format */
+#define INPUT_FORMAT_HALFWORD          1U                              /*!< input data in half-word format */
+#define INPUT_FORMAT_BYTE              2U                              /*!< input data in byte format */
+
+/* function declarations */
+/* deinitialize CRC calculation unit */
+void crc_deinit(void);
+/* reset data register to the value of initializaiton data register */
+void crc_data_register_reset(void);
+
+/* enable the reverse operation of output data */
+void crc_reverse_output_data_enable(void);
+/* disable the reverse operation of output data */
+void crc_reverse_output_data_disable(void);
+/* configure the CRC input data function */
+void crc_input_data_reverse_config(uint32_t data_reverse);
+
+/* read the data register */
+uint32_t crc_data_register_read(void);
+
+/* read the free data register */
+uint8_t crc_free_data_register_read(void);
+/* write the free data register */
+void crc_free_data_register_write(uint8_t free_data);
+
+/* write the initializaiton data register */
+void crc_init_data_register_write(uint32_t init_data);
+
+/* configure the CRC size of polynomial function */
+void crc_polynomial_size_set(uint32_t poly_size);
+/* configure the CRC polynomial value function */
+void crc_polynomial_set(uint32_t poly);
+
+/* CRC calculate single data */
+uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
+/* CRC calculate a data array */
+uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
+
+#endif /* GD32E50X_CRC_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_ctc.h

@@ -0,0 +1,182 @@
+/*!
+    \file    gd32e50x_ctc.h
+    \brief   definitions for the CTC
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_CTC_H
+#define GD32E50X_CTC_H
+
+#include "gd32e50x.h"
+
+/* CTC definitions */
+#define CTC                          CTC_BASE                        /*!< CTC base address */
+
+/* registers definitions */
+#define CTC_CTL0                     REG32((CTC) + 0x00000000U)      /*!< CTC control register 0 */
+#define CTC_CTL1                     REG32((CTC) + 0x00000004U)      /*!< CTC control register 1 */
+#define CTC_STAT                     REG32((CTC) + 0x00000008U)      /*!< CTC status register */
+#define CTC_INTC                     REG32((CTC) + 0x0000000CU)      /*!< CTC interrupt clear register */
+
+/* bits definitions */
+/* CTC_CTL0 */
+#define CTC_CTL0_CKOKIE              BIT(0)                    /*!< clock trim OK(CKOKIF) interrupt enable */
+#define CTC_CTL0_CKWARNIE            BIT(1)                    /*!< clock trim warning(CKWARNIF) interrupt enable */
+#define CTC_CTL0_ERRIE               BIT(2)                    /*!< error(ERRIF) interrupt enable */
+#define CTC_CTL0_EREFIE              BIT(3)                    /*!< EREFIF interrupt enable */
+#define CTC_CTL0_CNTEN               BIT(5)                    /*!< CTC counter enable */
+#define CTC_CTL0_AUTOTRIM            BIT(6)                    /*!< hardware automatically trim mode */
+#define CTC_CTL0_SWREFPUL            BIT(7)                    /*!< software reference source sync pulse */
+#define CTC_CTL0_TRIMVALUE           BITS(8,13)                /*!< IRC48M trim value */
+
+/* CTC_CTL1 */
+#define CTC_CTL1_RLVALUE             BITS(0,15)                /*!< CTC counter reload value */
+#define CTC_CTL1_CKLIM               BITS(16,23)               /*!< clock trim base limit value */
+#define CTC_CTL1_REFPSC              BITS(24,26)               /*!< reference signal source prescaler */
+#define CTC_CTL1_REFSEL              BITS(28,29)               /*!< reference signal source selection */
+#define CTC_CTL1_REFPOL              BIT(31)                   /*!< reference signal source polarity */
+
+/* CTC_STAT */
+#define CTC_STAT_CKOKIF              BIT(0)                    /*!< clock trim OK interrupt flag */
+#define CTC_STAT_CKWARNIF            BIT(1)                    /*!< clock trim warning interrupt flag */
+#define CTC_STAT_ERRIF               BIT(2)                    /*!< error interrupt flag */
+#define CTC_STAT_EREFIF              BIT(3)                    /*!< expect reference interrupt flag */
+#define CTC_STAT_CKERR               BIT(8)                    /*!< clock trim error bit */
+#define CTC_STAT_REFMISS             BIT(9)                    /*!< reference sync pulse miss */
+#define CTC_STAT_TRIMERR             BIT(10)                   /*!< trim value error bit */
+#define CTC_STAT_REFDIR              BIT(15)                   /*!< CTC trim counter direction when reference sync pulse occurred */
+#define CTC_STAT_REFCAP              BITS(16,31)               /*!< CTC counter capture when reference sync pulse occurred */
+
+/* CTC_INTC */
+#define CTC_INTC_CKOKIC              BIT(0)                    /*!< CKOKIF interrupt clear bit */
+#define CTC_INTC_CKWARNIC            BIT(1)                    /*!< CKWARNIF interrupt clear bit */
+#define CTC_INTC_ERRIC               BIT(2)                    /*!< ERRIF interrupt clear bit */
+#define CTC_INTC_EREFIC              BIT(3)                    /*!< EREFIF interrupt clear bit */
+
+/* constants definitions */
+/* hardware automatically trim mode definitions */
+#define CTC_HARDWARE_TRIM_MODE_ENABLE                    CTC_CTL0_AUTOTRIM            /*!< hardware automatically trim mode enable*/
+#define CTC_HARDWARE_TRIM_MODE_DISABLE                   ((uint32_t)0x00000000U)      /*!< hardware automatically trim mode disable*/
+
+/* reference signal source polarity definitions */
+#define CTC_REFSOURCE_POLARITY_FALLING                   CTC_CTL1_REFPOL              /*!< reference signal source polarity is falling edge*/
+#define CTC_REFSOURCE_POLARITY_RISING                    ((uint32_t)0x00000000U)      /*!< reference signal source polarity is rising edge*/
+
+/* reference signal source selection definitions */
+#define CTL1_REFSEL(regval)                              (BITS(28,29) & ((uint32_t)(regval) << 28))
+#define CTC_REFSOURCE_GPIO                               CTL1_REFSEL(0)               /*!< GPIO is selected */
+#define CTC_REFSOURCE_LXTAL                              CTL1_REFSEL(1)               /*!< LXTAL is selected */
+
+/* reference signal source prescaler definitions */
+#define CTL1_REFPSC(regval)                              (BITS(24,26) & ((uint32_t)(regval) << 24))
+#define CTC_REFSOURCE_PSC_OFF                            CTL1_REFPSC(0)               /*!< reference signal not divided */
+#define CTC_REFSOURCE_PSC_DIV2                           CTL1_REFPSC(1)               /*!< reference signal divided by 2 */
+#define CTC_REFSOURCE_PSC_DIV4                           CTL1_REFPSC(2)               /*!< reference signal divided by 4 */
+#define CTC_REFSOURCE_PSC_DIV8                           CTL1_REFPSC(3)               /*!< reference signal divided by 8 */
+#define CTC_REFSOURCE_PSC_DIV16                          CTL1_REFPSC(4)               /*!< reference signal divided by 16 */
+#define CTC_REFSOURCE_PSC_DIV32                          CTL1_REFPSC(5)               /*!< reference signal divided by 32 */
+#define CTC_REFSOURCE_PSC_DIV64                          CTL1_REFPSC(6)               /*!< reference signal divided by 64 */
+#define CTC_REFSOURCE_PSC_DIV128                         CTL1_REFPSC(7)               /*!< reference signal divided by 128 */
+
+/* CTC interrupt enable definitions */
+#define CTC_INT_CKOK                                     CTC_CTL0_CKOKIE             /*!< clock trim OK interrupt enable */
+#define CTC_INT_CKWARN                                   CTC_CTL0_CKWARNIE           /*!< clock trim warning interrupt enable */
+#define CTC_INT_ERR                                      CTC_CTL0_ERRIE              /*!< error interrupt enable */
+#define CTC_INT_EREF                                     CTC_CTL0_EREFIE             /*!< expect reference interrupt enable */
+
+/* CTC interrupt source definitions */
+#define CTC_INT_FLAG_CKOK                                CTC_STAT_CKOKIF             /*!< clock trim OK interrupt flag */
+#define CTC_INT_FLAG_CKWARN                              CTC_STAT_CKWARNIF           /*!< clock trim warning interrupt flag */
+#define CTC_INT_FLAG_ERR                                 CTC_STAT_ERRIF              /*!< error interrupt flag */
+#define CTC_INT_FLAG_EREF                                CTC_STAT_EREFIF             /*!< expect reference interrupt flag */
+#define CTC_INT_FLAG_CKERR                               CTC_STAT_CKERR              /*!< clock trim error bit */
+#define CTC_INT_FLAG_REFMISS                             CTC_STAT_REFMISS            /*!< reference sync pulse miss */
+#define CTC_INT_FLAG_TRIMERR                             CTC_STAT_TRIMERR            /*!< trim value error */
+
+/* CTC flag definitions */
+#define CTC_FLAG_CKOK                                    CTC_STAT_CKOKIF             /*!< clock trim OK flag */
+#define CTC_FLAG_CKWARN                                  CTC_STAT_CKWARNIF           /*!< clock trim warning flag */
+#define CTC_FLAG_ERR                                     CTC_STAT_ERRIF              /*!< error flag */
+#define CTC_FLAG_EREF                                    CTC_STAT_EREFIF             /*!< expect reference flag */
+#define CTC_FLAG_CKERR                                   CTC_STAT_CKERR              /*!< clock trim error bit */
+#define CTC_FLAG_REFMISS                                 CTC_STAT_REFMISS            /*!< reference sync pulse miss */
+#define CTC_FLAG_TRIMERR                                 CTC_STAT_TRIMERR            /*!< trim value error bit */
+
+/* function declarations */
+/* reset ctc clock trim controller */
+void ctc_deinit(void);
+/* enable CTC trim counter */
+void ctc_counter_enable(void);
+/* disable CTC trim counter */
+void ctc_counter_disable(void);
+
+/* configure the IRC48M trim value */
+void ctc_irc48m_trim_value_config(uint8_t trim_value);
+/* generate software reference source sync pulse */
+void ctc_software_refsource_pulse_generate(void);
+/* configure hardware automatically trim mode */
+void ctc_hardware_trim_mode_config(uint32_t hardmode);
+
+/* configure reference signal source polarity */
+void ctc_refsource_polarity_config(uint32_t polarity);
+/* select reference signal source */
+void ctc_refsource_signal_select(uint32_t refs);
+/* configure reference signal source prescaler */
+void ctc_refsource_prescaler_config(uint32_t prescaler);
+/* configure clock trim base limit value */
+void ctc_clock_limit_value_config(uint8_t limit_value);
+/* configure CTC counter reload value */
+void ctc_counter_reload_value_config(uint16_t reload_value);
+
+/* read CTC counter capture value when reference sync pulse occurred */
+uint16_t ctc_counter_capture_value_read(void);
+/* read CTC trim counter direction when reference sync pulse occurred */
+FlagStatus ctc_counter_direction_read(void);
+/* read CTC counter reload value */
+uint16_t ctc_counter_reload_value_read(void);
+/* read the IRC48M trim value */
+uint8_t ctc_irc48m_trim_value_read(void);
+
+/* interrupt & flag functions */
+/* get CTC flag */
+FlagStatus ctc_flag_get(uint32_t flag);
+/* clear CTC flag */
+void ctc_flag_clear(uint32_t flag);
+/* enable the CTC interrupt */
+void ctc_interrupt_enable(uint32_t interrupt);
+/* disable the CTC interrupt */
+void ctc_interrupt_disable(uint32_t interrupt);
+/* get CTC interrupt flag */
+FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
+/* clear CTC interrupt flag */
+void ctc_interrupt_flag_clear(uint32_t int_flag);
+
+#endif /* GD32E50X_CTC_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_dbg.h

@@ -0,0 +1,157 @@
+/*!
+    \file    gd32e50x_dbg.h
+    \brief   definitions for the DBG
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_DBG_H
+#define GD32E50X_DBG_H
+
+#include "gd32e50x.h"
+
+/* DBG definitions */
+#define DBG                     DBG_BASE                     /*!< DBG base address */
+
+/* registers definitions */
+#define DBG_ID                  REG32(DBG + 0x00000000U)     /*!< DBG_ID code register */
+#define DBG_CTL                 REG32(DBG + 0x00000004U)     /*!< DBG control register */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE           BITS(0,31)                  /*!< DBG ID code */
+
+/* DBG_CTL */
+#define DBG_CTL_SLP_HOLD         BIT(0)                      /*!< keep debugger connection during sleep mode */
+#define DBG_CTL_DSLP_HOLD        BIT(1)                      /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL_STB_HOLD         BIT(2)                      /*!< keep debugger connection during standby mode */
+#if (defined(GD32E50X_CL) || defined(GD32E508))
+#define DBG_CTL_CAN2_HOLD        BIT(3)                      /*!< hold CAN2 receive register counter when core is halted */
+#endif /* GD32E50X_CL and GD32E508 */
+#define DBG_CTL_TRACE_IOEN       BIT(5)                      /*!< enable trace pin assignment */
+#define DBG_CTL_FWDGT_HOLD       BIT(8)                      /*!< hold FWDGT counter when core is halted */
+#define DBG_CTL_WWDGT_HOLD       BIT(9)                      /*!< hold WWDGT counter when core is halted */
+#define DBG_CTL_TIMER0_HOLD      BIT(10)                     /*!< hold TIMER0 counter when core is halted */
+#define DBG_CTL_TIMER1_HOLD      BIT(11)                     /*!< hold TIMER1 counter when core is halted */
+#define DBG_CTL_TIMER2_HOLD      BIT(12)                     /*!< hold TIMER2 counter when core is halted */
+#define DBG_CTL_TIMER3_HOLD      BIT(13)                     /*!< hold TIMER3 counter when core is halted */
+#if (defined(GD32E50X_HD) || defined(GD32E50X_CL) || defined(GD32E508))
+#define DBG_CTL_CAN0_HOLD        BIT(14)                     /*!< hold CAN0 receive register counter when core is halted */
+#endif /* GD32E50X_HD and GD32E50X_CL and GD32E508 */
+#define DBG_CTL_I2C0_HOLD        BIT(15)                     /*!< hold I2C0 smbus timeout when core is halted */
+#define DBG_CTL_I2C1_HOLD        BIT(16)                     /*!< hold I2C1 smbus timeout when core is halted */
+#define DBG_CTL_TIMER7_HOLD      BIT(17)                     /*!< hold TIMER7 counter when core is halted */
+#define DBG_CTL_TIMER4_HOLD      BIT(18)                     /*!< hold TIMER4 counter when core is halted */
+#define DBG_CTL_TIMER5_HOLD      BIT(19)                     /*!< hold TIMER5 counter when core is halted */
+#define DBG_CTL_TIMER6_HOLD      BIT(20)                     /*!< hold TIMER6 counter when core is halted */
+#if (defined(GD32E50X_HD) || defined(GD32E50X_CL) || defined(GD32E508))
+#define DBG_CTL_CAN1_HOLD        BIT(21)                     /*!< hold CAN1 receive register counter when core is halted */
+#endif /* GD32E50X_HD and GD32E50X_CL and GD32E508 */
+#define DBG_CTL_I2C2_HOLD        BIT(22)                     /*!< hold I2C2 smbus timeout when core is halted */
+#if (defined(GD32E50X_HD) || defined(GD32E50X_CL) || defined(GD32E508))
+#define DBG_CTL_TIMER11_HOLD     BIT(25)                     /*!< hold TIMER11 counter when core is halted */
+#define DBG_CTL_TIMER12_HOLD     BIT(26)                     /*!< hold TIMER12 counter when core is halted */
+#define DBG_CTL_TIMER13_HOLD     BIT(27)                     /*!< hold TIMER13 counter when core is halted */
+#define DBG_CTL_TIMER8_HOLD      BIT(28)                     /*!< hold TIMER8 counter when core is halted */
+#define DBG_CTL_TIMER9_HOLD      BIT(29)                     /*!< hold TIMER9 counter when core is halted */
+#define DBG_CTL_TIMER10_HOLD     BIT(30)                     /*!< hold TIMER10 counter when core is halted */
+#define DBG_CTL_SHRTIMER_HOLD    BIT(31)                     /*!< hold SHRTIMER counter when core is halted */
+#endif /* GD32E50X_HD and GD32E50X_CL and GD32E508 */
+
+/* constants definitions */
+#define DBG_LOW_POWER_SLEEP      DBG_CTL_SLP_HOLD            /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP  DBG_CTL_DSLP_HOLD           /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY    DBG_CTL_STB_HOLD            /*!< keep debugger connection during standby mode */
+
+/* define the peripheral debug hold bit position and its register index offset */
+#define DBG_REGIDX_BIT(regidx, bitpos)      (((regidx) << 6) | (bitpos))
+#define DBG_REG_VAL(periph)                 (REG32(DBG + ((uint32_t)(periph) >> 6)))
+#define DBG_BIT_POS(val)                    ((uint32_t)(val) & 0x1FU)
+
+/* register index */
+#define DBG_IDX_CTL              ((uint32_t)0x00000004U)
+
+typedef enum
+{
+#if (defined(GD32E50X_CL) || defined(GD32E508))
+    DBG_CAN2_HOLD              = DBG_REGIDX_BIT(DBG_IDX_CTL, 3U),                    /*!< hold CAN2 receive register counter when core is halted */
+#endif /* GD32E50X_CL and GD32E508 */
+    DBG_FWDGT_HOLD             = DBG_REGIDX_BIT(DBG_IDX_CTL, 8U),                    /*!< hold FWDGT counter when core is halted */
+    DBG_WWDGT_HOLD             = DBG_REGIDX_BIT(DBG_IDX_CTL, 9U),                    /*!< hold WWDGT counter when core is halted */
+    DBG_TIMER0_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 10U),                   /*!< hold TIMER0 counter when core is halted */
+    DBG_TIMER1_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 11U),                   /*!< hold TIMER1 counter when core is halted */
+    DBG_TIMER2_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 12U),                   /*!< hold TIMER2 counter when core is halted */
+    DBG_TIMER3_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 13U),                   /*!< hold TIMER3 counter when core is halted */
+#if (defined(GD32E50X_HD) || defined(GD32E50X_CL) || defined(GD32E508))
+    DBG_CAN0_HOLD              = DBG_REGIDX_BIT(DBG_IDX_CTL, 14U),                   /*!< hold CAN0 receive register counter when core is halted */
+#endif /* GD32E50X_HD and GD32E50X_CL and GD32E508 */
+    DBG_I2C0_HOLD              = DBG_REGIDX_BIT(DBG_IDX_CTL, 15U),                   /*!< hold I2C0 smbus timeout when core is halted */
+    DBG_I2C1_HOLD              = DBG_REGIDX_BIT(DBG_IDX_CTL, 16U),                   /*!< hold I2C1 smbus timeout when core is halted */
+    DBG_TIMER7_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 17U),                   /*!< hold TIMER7 counter when core is halted */
+    DBG_TIMER4_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 18U),                   /*!< hold TIMER4 counter when core is halted */
+    DBG_TIMER5_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 19U),                   /*!< hold TIMER5 counter when core is halted */
+    DBG_TIMER6_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 20U),                   /*!< hold TIMER6 counter when core is halted */
+#if (defined(GD32E50X_HD) || defined(GD32E50X_CL) || defined(GD32E508))
+    DBG_CAN1_HOLD              = DBG_REGIDX_BIT(DBG_IDX_CTL, 21U),                   /*!< hold CAN1 receive register counter when core is halted */
+#endif /* GD32E50X_HD and GD32E50X_CL and GD32E508 */
+    DBG_I2C2_HOLD              = DBG_REGIDX_BIT(DBG_IDX_CTL, 22U),                   /*!< hold I2C2 smbus timeout when core is halted */
+#if (defined(GD32E50X_HD) || defined(GD32E50X_CL) || defined(GD32E508))
+    DBG_TIMER11_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL, 25U),                   /*!< hold TIMER11 counter when core is halted */
+    DBG_TIMER12_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL, 26U),                   /*!< hold TIMER12 counter when core is halted */
+    DBG_TIMER13_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL, 27U),                   /*!< hold TIMER13 counter when core is halted */
+    DBG_TIMER8_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 28U),                   /*!< hold TIMER8 counter when core is halted */
+    DBG_TIMER9_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL, 29U),                   /*!< hold TIMER9 counter when core is halted */
+    DBG_TIMER10_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL, 30U),                   /*!< hold TIMER10 counter when core is halted */
+    DBG_SHRTIMER_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL, 31U),                   /*!< hold SHRTIMER counter when core is halted */
+#endif /* GD32E50X_HD and GD32E50X_CL and GD32E508 */
+}dbg_periph_enum;
+
+/* function declarations */
+/* deinitialize the DBG */
+void dbg_deinit(void);
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+/* enable trace pin assignment */
+void dbg_trace_pin_enable(void);
+/* disable trace pin assignment */
+void dbg_trace_pin_disable(void);
+
+#endif /* GD32E50X_DBG_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_fwdgt.h

@@ -0,0 +1,111 @@
+/*!
+    \file    gd32e50x_fwdgt.h
+    \brief   definitions for the FWDGT
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_FWDGT_H
+#define GD32E50X_FWDGT_H
+
+#include "gd32e50x.h"
+
+/* FWDGT definitions */
+#define FWDGT                       FWDGT_BASE                                /*!< FWDGT base address */
+
+/* registers definitions */
+#define FWDGT_CTL                   REG32((FWDGT) + 0x00000000U)              /*!< FWDGT control register */
+#define FWDGT_PSC                   REG32((FWDGT) + 0x00000004U)              /*!< FWDGT prescaler register */
+#define FWDGT_RLD                   REG32((FWDGT) + 0x00000008U)              /*!< FWDGT reload register */
+#define FWDGT_STAT                  REG32((FWDGT) + 0x0000000CU)              /*!< FWDGT status register */
+
+/* bits definitions */
+/* FWDGT_CTL */
+#define FWDGT_CTL_CMD               BITS(0,15)                                /*!< FWDGT command value */
+
+/* FWDGT_PSC */
+#define FWDGT_PSC_PSC               BITS(0,2)                                 /*!< FWDGT prescaler divider value */
+
+/* FWDGT_RLD */
+#define FWDGT_RLD_RLD               BITS(0,11)                                /*!< FWDGT counter reload value */
+
+/* FWDGT_STAT */
+#define FWDGT_STAT_PUD              BIT(0)                                    /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD              BIT(1)                                    /*!< FWDGT counter reload value update */
+
+/* constants definitions */
+/* psc register value */
+#define PSC_PSC(regval)             (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))                     /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))                     /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))                     /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))                     /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))                     /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))                     /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))                     /*!< FWDGT prescaler set to 256 */
+
+/* control value */
+#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x5555U)                       /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x0000U)                       /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD            ((uint16_t)0xAAAAU)                       /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE            ((uint16_t)0xCCCCU)                       /*!< FWDGT_CTL bits fwdgt counter enable value */
+
+/* FWDGT timeout value */
+#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_RLD register write operation state flag timeout */
+
+/* FWDGT flag definitions */
+#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                            /*!< FWDGT prescaler divider value update flag */
+#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                            /*!< FWDGT counter reload value update flag */
+
+/* write value to FWDGT_RLD_RLD bit field */
+#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/* function declarations */
+/* enable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_enable(void);
+/* disable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_disable(void);
+/* start the free watchdog timer counter */
+void fwdgt_enable(void);
+
+/* configure the free watchdog timer counter prescaler value */
+ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
+/* configure the free watchdog timer counter reload value */
+ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
+/* reload the counter of FWDGT */
+void fwdgt_counter_reload(void);
+/* configure counter reload value, and prescaler divider value */
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
+
+/* get flag state of FWDGT */
+FlagStatus fwdgt_flag_get(uint16_t flag);
+
+#endif /* GD32E50X_FWDGT_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_misc.h

@@ -0,0 +1,93 @@
+/*!
+    \file    gd32e50x_misc.h
+    \brief   definitions for the MISC
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_MISC_H
+#define GD32E50X_MISC_H
+
+#include "gd32e50x.h"
+
+/* constants definitions */
+/* set the RAM and FLASH base address */
+#define NVIC_VECTTAB_RAM            ((uint32_t)0x20000000) /*!< RAM base address */
+#define NVIC_VECTTAB_FLASH          ((uint32_t)0x08000000) /*!< Flash base address */
+
+/* set the NVIC vector table offset mask */
+#define NVIC_VECTTAB_OFFSET_MASK    ((uint32_t)0x1FFFFF80)
+
+/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
+#define NVIC_AIRCR_VECTKEY_MASK     ((uint32_t)0x05FA0000)
+
+/* priority group - define the pre-emption priority and the subpriority */
+#define NVIC_PRIGROUP_PRE0_SUB4     ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
+#define NVIC_PRIGROUP_PRE1_SUB3     ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
+#define NVIC_PRIGROUP_PRE2_SUB2     ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
+#define NVIC_PRIGROUP_PRE3_SUB1     ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
+#define NVIC_PRIGROUP_PRE4_SUB0     ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
+
+/* choose the method to enter or exit the lowpower mode */
+#define SCB_SCR_SLEEPONEXIT         ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
+#define SCB_SCR_SLEEPDEEP           ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
+#define SCB_SCR_SEVONPEND           ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
+
+#define SCB_LPM_SLEEP_EXIT_ISR      SCB_SCR_SLEEPONEXIT
+#define SCB_LPM_DEEPSLEEP           SCB_SCR_SLEEPDEEP
+#define SCB_LPM_WAKE_BY_ALL_INT     SCB_SCR_SEVONPEND
+
+/* choose the systick clock source */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
+#define SYSTICK_CLKSOURCE_HCLK      ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
+
+/* function declarations */
+/* set the priority group */
+void nvic_priority_group_set(uint32_t nvic_prigroup);
+
+/* enable NVIC request */
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
+/* disable NVIC request */
+void nvic_irq_disable(uint8_t nvic_irq);
+/* initiates a system reset request to reset the MCU */
+void nvic_system_reset(void);
+
+/* set the NVIC vector table base address */
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
+
+/* set the state of the low power mode */
+void system_lowpower_set(uint8_t lowpower_mode);
+/* reset the state of the low power mode */
+void system_lowpower_reset(uint8_t lowpower_mode);
+
+/* set the systick clock source */
+void systick_clksource_set(uint32_t systick_clksource);
+
+#endif /* GD32E50X_MISC_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_rtc.h

@@ -0,0 +1,134 @@
+/*!
+    \file    gd32e50x_rtc.h
+    \brief   definitions for the RTC
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_RTC_H
+#define GD32E50X_RTC_H
+
+#include "gd32e50x.h"
+
+/* RTC definitions */
+#define RTC                          RTC_BASE
+
+/* registers definitions */
+#define RTC_INTEN                    REG32(RTC + 0x00000000U)       /*!< interrupt enable register */
+#define RTC_CTL                      REG32(RTC + 0x00000004U)       /*!< control register */
+#define RTC_PSCH                     REG32(RTC + 0x00000008U)       /*!< prescaler high register */
+#define RTC_PSCL                     REG32(RTC + 0x0000000CU)       /*!< prescaler low register */
+#define RTC_DIVH                     REG32(RTC + 0x00000010U)       /*!< divider high register */
+#define RTC_DIVL                     REG32(RTC + 0x00000014U)       /*!< divider low register */
+#define RTC_CNTH                     REG32(RTC + 0x00000018U)       /*!< counter high register */
+#define RTC_CNTL                     REG32(RTC + 0x0000001CU)       /*!< counter low register */
+#define RTC_ALRMH                    REG32(RTC + 0x00000020U)       /*!< alarm high register */
+#define RTC_ALRML                    REG32(RTC + 0x00000024U)       /*!< alarm low register */
+
+/* bits definitions */
+/* RTC_INTEN */
+#define RTC_INTEN_SCIE               BIT(0)                         /*!< second interrupt enable */
+#define RTC_INTEN_ALRMIE             BIT(1)                         /*!< alarm interrupt enable */
+#define RTC_INTEN_OVIE               BIT(2)                         /*!< overflow interrupt enable */
+
+/* RTC_CTL */
+#define RTC_CTL_SCIF                 BIT(0)                         /*!< second interrupt flag */
+#define RTC_CTL_ALRMIF               BIT(1)                         /*!< alarm interrupt flag */
+#define RTC_CTL_OVIF                 BIT(2)                         /*!< overflow interrupt flag */
+#define RTC_CTL_RSYNF                BIT(3)                         /*!< registers synchronized flag */
+#define RTC_CTL_CMF                  BIT(4)                         /*!< configuration mode flag */
+#define RTC_CTL_LWOFF                BIT(5)                         /*!< last write operation finished flag */
+
+/* RTC_PSC */
+#define RTC_PSCH_PSC                 BITS(0,3)                      /*!< prescaler high value */
+#define RTC_PSCL_PSC                 BITS(0,15)                     /*!< prescaler low value */
+
+/* RTC_DIV */
+#define RTC_DIVH_DIV                 BITS(0,3)                      /*!< divider high value */
+#define RTC_DIVL_DIV                 BITS(0,15)                     /*!< divider low value */
+
+/* RTC_CNT */
+#define RTC_CNTH_CNT                 BITS(0,15)                     /*!< counter high value */
+#define RTC_CNTL_CNT                 BITS(0,15)                     /*!< counter low value */
+
+/* RTC_ALRM */
+#define RTC_ALRMH_ALRM               BITS(0,15)                     /*!< alarm high value */
+#define RTC_ALRML_ALRM               BITS(0,15)                     /*!< alarm low value */
+
+/* constants definitions */
+#define RTC_HIGH_VALUE               ((uint32_t)0x000F0000U)        /*!< RTC high value */
+#define RTC_LOW_VALUE                ((uint32_t)0x0000FFFFU)        /*!< RTC low value */
+
+/* RTC interrupt enable or disable definitions */
+#define RTC_INT_SECOND               RTC_INTEN_SCIE                 /*!< second interrupt enable */
+#define RTC_INT_ALARM                RTC_INTEN_ALRMIE               /*!< alarm interrupt enable */
+#define RTC_INT_OVERFLOW             RTC_INTEN_OVIE                 /*!< overflow interrupt enable */
+
+/* RTC flag definitions */
+#define RTC_FLAG_SECOND              RTC_CTL_SCIF                   /*!< second interrupt flag */
+#define RTC_FLAG_ALARM               RTC_CTL_ALRMIF                 /*!< alarm interrupt flag */
+#define RTC_FLAG_OVERFLOW            RTC_CTL_OVIF                   /*!< overflow interrupt flag */
+#define RTC_FLAG_RSYN                RTC_CTL_RSYNF                  /*!< registers synchronized flag */
+#define RTC_FLAG_LWOF                RTC_CTL_LWOFF                  /*!< last write operation finished flag */
+
+/* function declarations */
+/* enter RTC configuration mode */
+void rtc_configuration_mode_enter(void);
+/* exit RTC configuration mode */
+void rtc_configuration_mode_exit(void);
+
+/* wait RTC last write operation finished flag set */
+void rtc_lwoff_wait(void);
+/* wait RTC registers synchronized flag set */
+void rtc_register_sync_wait(void);
+
+/* get RTC counter value */
+uint32_t rtc_counter_get(void);
+/* set RTC counter value */
+void rtc_counter_set(uint32_t cnt);
+
+/* set RTC prescaler value */
+void rtc_prescaler_set(uint32_t psc);
+/* set RTC alarm value */
+void rtc_alarm_config(uint32_t alarm);
+/* get RTC divider value */
+uint32_t rtc_divider_get(void);
+
+/* enable RTC interrupt */
+void rtc_interrupt_enable(uint32_t interrupt);
+/* disable RTC interrupt */
+void rtc_interrupt_disable(uint32_t interrupt);
+
+/* get RTC flag status */
+FlagStatus rtc_flag_get(uint32_t flag);
+/* clear RTC flag status */
+void rtc_flag_clear(uint32_t flag);
+
+#endif /* GD32E50X_RTC_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_sqpi.h

@@ -0,0 +1,135 @@
+/*!
+    \file    gd32e50x_sqpi.h
+    \brief   definitions for the SQPI
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_SQPI_H
+#define GD32E50X_SQPI_H
+
+#include "gd32e50x.h"
+
+/* SQPI definitions */
+#define SQPI                             SQPI_BASE
+/* SQPI registers definitions */
+#define SQPI_INIT                        REG32((SQPI) + 0x00000000U)            /*!< SQPI initial register*/
+#define SQPI_RCMD                        REG32((SQPI) + 0x00000004U)            /*!< SQPI read command register */
+#define SQPI_WCMD                        REG32((SQPI) + 0x00000008U)            /*!< SQPI write command register */
+#define SQPI_IDL                         REG32((SQPI) + 0x0000000CU)            /*!< SQPI ID low register */
+#define SQPI_IDH                         REG32((SQPI) + 0x00000010U)            /*!< SQPI ID high register */
+
+
+/* bits definitions */
+/* SQPI_INIT */
+#define SQPI_INIT_CMDBIT                 BITS(16,17)                            /*!< bit number of SQPI controller command phase */
+#define SQPI_INIT_CLKDIV                 BITS(18,23)                            /*!< clock divider for SQPI output clock */
+#define SQPI_INIT_ADDRBIT                BITS(24,28)                            /*!< bit number of SPI PSRAM address phase*/
+#define SQPI_INIT_IDLEN                  BITS(29,30)                            /*!< external memory ID length */
+#define SQPI_INIT_PL                     BIT(31)                                /*!< SQPI read data sample polarity */
+
+/* SQPI_RCMD */
+#define SQPI_RCMD_RCMD                   BITS(0,15)                             /*!< SQPI read command for AHB read transfer */
+#define SQPI_RCMD_RWAITCYCLE             BITS(16,19)                            /*!< read command waitcycle number */
+#define SQPI_RCMD_RMODE                  BITS(20,22)                            /*!< read command mode */
+#define SQPI_RCMD_RID                    BIT(31)                                /*!< send read ID command */
+
+/* SQPI_WCMD */
+#define SQPI_WCMD_WCMD                   BITS(0,15)                             /*!< SQPI write command for AHB write transfer */
+#define SQPI_WCMD_WWAITCYCLE             BITS(16,19)                            /*!< write command waitcycle number */
+#define SQPI_WCMD_WMODE                  BITS(20,22)                            /*!< write command mode */
+#define SQPI_WCMD_SCMD                   BIT(31)                                /*!< send special command */
+
+/* SQPI_IDL */
+#define SQPI_IDL_IDL                     BITS(0,31)                             /*!< ID low register */
+
+/* SQPI_IDH */
+#define SQPI_IDH_IDH                     BITS(0,31)                             /*!< ID high register */
+
+
+/* constants definitions */
+/* SQPI parameter struct definitions */
+typedef struct
+{
+    uint32_t polarity;                                                          /*!< SQPI sample polarity*/
+    uint32_t id_length;                                                         /*!< external memory ID length */
+    uint32_t addr_bit;                                                          /*!< bit number of SPI PSRAM address phase */
+    uint32_t clk_div;                                                           /*!< clock divider for SQPI output clock */
+    uint32_t cmd_bit;                                                           /*!< bit number of SQPI controller command phase */
+}sqpi_parameter_struct;
+/* SQPI sample shift */
+#define SQPI_SAMPLE_POLARITY_RISING           ((uint32_t)0x00000000U)           /*!< SQPI read data at rising edge */
+#define SQPI_SAMPLE_POLARITY_FALLING          (SQPI_INIT_PL)                    /*!< SQPI read data at falling edge */
+
+/* SQPI ID length */
+#define INIT_IDLEN(regval)                    (BITS(29,30) & ((uint32_t)(regval) << 29))
+#define SQPI_ID_LENGTH_64_BITS                INIT_IDLEN(0)                     /*!< 64 bits ID */
+#define SQPI_ID_LENGTH_32_BITS                INIT_IDLEN(1)                     /*!< 32 bits ID */
+#define SQPI_ID_LENGTH_16_BITS                INIT_IDLEN(2)                     /*!< 16 bits ID */
+#define SQPI_ID_LENGTH_8_BITS                 INIT_IDLEN(3)                     /*!< 8 bits ID */
+
+/* SQPI command bits */
+#define INIT_CMDBIT(regval)                   (BITS(16,17) & ((uint32_t)(regval) << 16))
+#define SQPI_CMDBIT_4_BITS                    INIT_CMDBIT(0)                    /*!< 4 bits command */
+#define SQPI_CMDBIT_8_BITS                    INIT_CMDBIT(1)                    /*!< 8 bits command */
+#define SQPI_CMDBIT_16_BITS                   INIT_CMDBIT(2)                    /*!< 16 bits command */
+
+/* SQPI mode */
+#define SQPI_MODE(regval)                     (BITS(20,22) & ((uint32_t)(regval) << 20))
+#define SQPI_MODE_SSQ                         SQPI_MODE(0)                      /*!< SQPI SSQ mode */
+#define SQPI_MODE_SSS                         SQPI_MODE(1)                      /*!< SQPI SSS mode */
+#define SQPI_MODE_SQQ                         SQPI_MODE(2)                      /*!< SQPI SQQ mode */
+#define SQPI_MODE_QQQ                         SQPI_MODE(3)                      /*!< SQPI QQQ mode */
+#define SQPI_MODE_SSD                         SQPI_MODE(4)                      /*!< SQPI SSD mode */
+#define SQPI_MODE_SDD                         SQPI_MODE(5)                      /*!< SQPI SDD mode */
+
+/* function declarations */
+/* SQPI deinitialization and initialization functions */
+/* reset SQPI */
+void sqpi_deinit(void);
+/* initialize the parameters of SQPI struct with the default values */
+void sqpi_struct_para_init(sqpi_parameter_struct* sqpi_struct);
+/* initialize SQPI parameter */
+void sqpi_init(sqpi_parameter_struct *sqpi_struct);
+
+/* send SQPI read ID command */
+void sqpi_read_id_command(void);
+/* send SQPI special command */
+void sqpi_special_command(void);
+/* configure SQPI read command */
+void sqpi_read_command_config(uint32_t rmode, uint32_t rwaitcycle, uint32_t rcmd);
+/* configure SQPI write command */
+void sqpi_write_command_config(uint32_t wmode, uint32_t wwaitcycle, uint32_t wcmd);
+/* SQPI receive low ID */
+uint32_t sqpi_low_id_receive(void);
+/* SQPI receive high ID*/
+uint32_t sqpi_high_id_receive(void);
+
+#endif /* GD32E50X_SQPI_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_tmu.h

@@ -0,0 +1,127 @@
+/*!
+    \file    gd32e50x_tmu.h
+    \brief   definitions for the TMU
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_TMU_H
+#define GD32E50X_TMU_H
+
+#include "gd32e50x.h"
+
+#if defined(GD32E50X_CL) || defined(GD32E508)
+
+/* TMU definitions */
+#define TMU                             TMU_BASE
+
+/* registers definitions */
+#define TMU_IDATA0                      REG32((TMU) + 0x00000000U)        /*!< input data0 register */
+#define TMU_IDATA1                      REG32((TMU) + 0x00000004U)        /*!< input data1 register */
+#define TMU_CTL                         REG32((TMU) + 0x00000008U)        /*!< control register */
+#define TMU_DATA0                       REG32((TMU) + 0x0000000CU)        /*!< data0 register */
+#define TMU_DATA1                       REG32((TMU) + 0x00000010U)        /*!< data1 register */
+#define TMU_STAT                        REG32((TMU) + 0x00000014U)        /*!< status register */
+
+/* bits definitions */
+/* TMU_IDATA0 */
+#define TMU_IDATA0_IDATA0               BITS(0,31)                /*!< the value of input data0 register */
+
+/* TMU_IDATA1 */
+#define TMU_IDATA1_IDATA1               BITS(0,31)                /*!< the value of input data1 register */
+
+/* TMU_CTL */
+#define TMU_CTL_TMUEN                   BIT(0)                    /*!< start TMU calculation */
+#define TMU_CTL_MODE                    BITS(1,4)                 /*!< the mode of TMU */
+#define TMU_CTL_CFIE                    BIT(5)                    /*!< enable calculation finishes interrupt */
+#define TMU_CTL_CFIF                    BIT(6)                    /*!< the flag of calculation finishes interrupt */
+
+/* TMU_DATA0 */
+#define TMU_DATA0_DATA0                 BITS(0,31)                /*!< the value of data0 register */
+
+/* TMU_DATA0 */
+#define TMU_DATA1_DATA1                 BITS(0,31)                /*!< the value of data1 register */
+
+/* TMU_STAT */
+#define TMU_STAT_OVRF                   BIT(0)                    /*!< the status of overflow */
+#define TMU_STAT_UDRF                   BIT(1)                    /*!< the status of underflow */
+
+/* constants definitions */
+/* TMU mode definitions */
+#define TMU_MODE(regval)                (BITS(1,4) & ((uint32_t)(regval) << 1))
+#define TMU_MODE0                        TMU_MODE(0)              /*!< the mode0 of TMU */
+#define TMU_MODE1                        TMU_MODE(1)              /*!< the mode1 of TMU */
+#define TMU_MODE2                        TMU_MODE(2)              /*!< the mode2 of TMU */
+#define TMU_MODE3                        TMU_MODE(3)              /*!< the mode3 of TMU */
+#define TMU_MODE4                        TMU_MODE(4)              /*!< the mode4 of TMU */
+#define TMU_MODE5                        TMU_MODE(5)              /*!< the mode5 of TMU */
+#define TMU_MODE6                        TMU_MODE(6)              /*!< the mode6 of TMU */
+#define TMU_MODE7                        TMU_MODE(7)              /*!< the mode7 of TMU */
+#define TMU_MODE8                        TMU_MODE(8)              /*!< the mode8 of TMU */
+
+/* TMU interrupt flag definitions */
+#define TMU_INT_FLAG_CFIF                TMU_CTL_CFIF             /*!< the interrupt flag of calculation finished */
+
+/* TMU flag definitions */
+#define TMU_FLAG_OVRF                    TMU_STAT_OVRF            /*!< the flag of TMU overflow */
+#define TMU_FLAG_UDRF                    TMU_STAT_UDRF            /*!< the flag of TMU underflow */
+
+/* function declarations */
+/* TMU deinitialization and initialization functions */
+/* reset the TMU */
+void tmu_deinit(void);
+/* enable the TMU */
+void tmu_enable(void);
+
+/* configure the TMU calculation */
+/* configure the TMU mode */
+void tmu_mode_set(uint32_t modex);
+/* write the data to TMU input data0 regisetr */
+void tmu_idata0_write(uint32_t idata0);
+/* write the data to TMU input data1 regisetr */
+void tmu_idata1_write(uint32_t idata1);
+/* read the data from TMU data0 regisetr */
+uint32_t tmu_data0_read(void);
+/* read the data from TMU data1 regisetr */
+uint32_t tmu_data1_read(void);
+
+/* flag and interrupt functions */
+/* enable TTMU interrupt */
+void tmu_interrupt_enable(void);
+/* disable TTMU interrupt */
+void tmu_interrupt_disable(void);
+/* check teh TMU status flag */
+FlagStatus tmu_flag_get(uint32_t flag);
+/* check teh TMU interrupt flag */
+FlagStatus tmu_interrupt_flag_get(uint32_t int_flag);
+
+#endif /* GD32E50x_CL and GD32E508 */
+
+#endif /* GD32E50X_TMU_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_wwdgt.h

@@ -0,0 +1,92 @@
+/*!
+    \file    gd32e50x_wwdgt.h
+    \brief   definitions for the WWDGT
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E50X_WWDGT_H
+#define GD32E50X_WWDGT_H
+
+#include "gd32e50x.h"
+
+/* WWDGT definitions */
+#define WWDGT                       WWDGT_BASE                                /*!< WWDGT base address */
+
+/* registers definitions */
+#define WWDGT_CTL                   REG32((WWDGT) + 0x00000000U)              /*!< WWDGT control register */
+#define WWDGT_CFG                   REG32((WWDGT) + 0x00000004U)              /*!< WWDGT configuration register */
+#define WWDGT_STAT                  REG32((WWDGT) + 0x00000008U)              /*!< WWDGT status register */
+
+/* bits definitions */
+/* WWDGT_CTL */
+#define WWDGT_CTL_CNT               BITS(0,6)                                 /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN            BIT(7)                                    /*!< WWDGT counter enable */
+
+/* WWDGT_CFG */
+#define WWDGT_CFG_WIN               BITS(0,6)                                 /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC               BITS(7,8)                                 /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE              BIT(9)                                    /*!< early wakeup interrupt enable */
+
+/* WWDGT_STAT */
+#define WWDGT_STAT_EWIF             BIT(0)                                    /*!< early wakeup interrupt flag */
+
+/* constants definitions */
+#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7))   /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1          CFG_PSC(0)                                /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2          CFG_PSC(1)                                /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4          CFG_PSC(2)                                /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8          CFG_PSC(3)                                /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+
+/* write value to WWDGT_CTL_CNT bit field */
+#define CTL_CNT(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0))
+/* write value to WWDGT_CFG_WIN bit field */
+#define CFG_WIN(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0))
+
+/* function declarations */
+/* reset the window watchdog timer configuration */
+void wwdgt_deinit(void);
+/* start the window watchdog timer counter */
+void wwdgt_enable(void);
+
+/* configure the window watchdog timer counter value */
+void wwdgt_counter_update(uint16_t counter_value);
+/* configure counter value, window value, and prescaler divider value */
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
+
+/* check early wakeup interrupt state of WWDGT */
+FlagStatus wwdgt_flag_get(void);
+/* clear early wakeup interrupt state of WWDGT */
+void wwdgt_flag_clear(void);
+
+/* enable early wakeup interrupt of WWDGT */
+void wwdgt_interrupt_enable(void);
+
+#endif /* GD32E50X_WWDGT_H */

bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_dbg.c

@@ -0,0 +1,148 @@
+/*!
+    \file    gd32e50x_dbg.c
+    \brief   DBG driver
+
+    \version 2023-12-31, V1.4.0, firmware for GD32E50x
+*/
+
+/*
+    Copyright (c) 2023, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e50x_dbg.h"
+
+#define DBG_RESET_VAL       ((uint32_t)0x00000000U)   /*!< DBG reset value */
+
+/*!
+    \brief      deinitialize the DBG
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dbg_deinit(void)
+{
+    DBG_CTL = DBG_RESET_VAL;
+}
+
+/*!
+    \brief      read DBG_ID code register
+    \param[in]  none
+    \param[out] none
+    \retval     DBG_ID code
+*/
+uint32_t dbg_id_get(void)
+{
+    return DBG_ID;
+}
+
+/*!
+    \brief      enable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                one or more parameters can be selected which are shown as below:
+      \arg        DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_enable(uint32_t dbg_low_power)
+{
+    DBG_CTL |= dbg_low_power;
+}
+
+/*!
+    \brief      disable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                one or more parameters can be selected which are shown as below:
+      \arg        DBG_LOW_POWER_SLEEP: do not keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: do not keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: do not keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_disable(uint32_t dbg_low_power)
+{
+    DBG_CTL &= ~dbg_low_power;
+}
+
+/*!
+    \brief      enable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: refer to dbg_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        DBG_FWDGT_HOLD : hold FWDGT counter when core is halted
+      \arg        DBG_WWDGT_HOLD : hold WWDGT counter when core is halted
+      \arg        DBG_CANx_HOLD (x=0,1,2 CAN2 is only available for CL series, CANx are not available for GD32EPRT series): hold CANx receive register counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus timeout when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13, TIMER8..13 are not available for GD32EPRT series): hold TIMERx counter when core is halted
+      \arg        DBG_SHRTIMER_HOLD : hold SHRTIMER counter when core is halted, except for GD32EPRT series
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_enable(dbg_periph_enum dbg_periph)
+{
+    DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
+}
+
+/*!
+    \brief      disable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: refer to dbg_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        DBG_FWDGT_HOLD : hold FWDGT counter when core is halted
+      \arg        DBG_WWDGT_HOLD : hold WWDGT counter when core is halted
+      \arg        DBG_CANx_HOLD (x=0,1,2 CAN2 is only available for CL series, CANx are not available for GD32EPRT series): hold CANx receive register counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus timeout when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for GD32EPRT series): hold TIMERx counter when core is halted
+      \arg        DBG_SHRTIMER_HOLD : hold SHRTIMER counter when core is halted, except for GD32EPRT series
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_disable(dbg_periph_enum dbg_periph)
+{
+    DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
+}
+
+/*!
+    \brief      enable trace pin assignment
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dbg_trace_pin_enable(void)
+{
+    DBG_CTL |= DBG_CTL_TRACE_IOEN;
+}
+
+/*!
+    \brief      disable trace pin assignment
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dbg_trace_pin_disable(void)
+{
+    DBG_CTL &= ~DBG_CTL_TRACE_IOEN;
+}
+