mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-03-24 09:30:19 +08:00
[BSP][GD32]add gd32e503v-eval
This commit is contained in:
zhangjianwu
Meco Man
1
.github/workflows/bsp_buildings.yml
vendored
1
.github/workflows/bsp_buildings.yml
vendored
@@ -278,6 +278,7 @@ jobs:
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- "gd32/arm/gd32450z-eval"
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- "gd32/arm/gd32470z-lckfb"
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- "gd32/arm/gd32h759i-start"
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- "gd32/arm/gd32e503v-eval"
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- "n32/n32g43xcl-stb"
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- "n32/n32g45xcl-stb"
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- "n32/n32g45xml-stb"
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@@ -22,6 +22,8 @@ GD32 ARM 系列 BSP 目前支持情况如下表所示：
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| [gd32407v-lckfb](gd32407v-lckfb) | 立创天空星 GD32F407VET6 开发板 |
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| [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
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| [gd32470z-lckfb](gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 |
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| **E5 系列** | |
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| [gd32e503v-eval](gd32e503v-eval) | 兆易创新 官方 GD32E503V-EVAL 开发板 |
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可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
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300
bsp/gd32/arm/gd32e503v-eval/.config
Normal file
300
bsp/gd32/arm/gd32e503v-eval/.config
Normal file
@@ -0,0 +1,300 @@
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#
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# RT-Thread Kernel
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#
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CONFIG_RT_NAME_MAX=8
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# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
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# CONFIG_RT_USING_NANO is not set
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# CONFIG_RT_USING_AMP is not set
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# CONFIG_RT_USING_SMP is not set
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CONFIG_RT_CPUS_NR=1
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CONFIG_RT_ALIGN_SIZE=8
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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# CONFIG_RT_THREAD_PRIORITY_256 is not set
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CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=100
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_HOOK_USING_FUNC_PTR=y
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# CONFIG_RT_USING_HOOKLIST is not set
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CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=256
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# CONFIG_RT_USING_TIMER_SOFT is not set
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# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
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#
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# kservice optimization
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#
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# CONFIG_RT_USING_TINY_FFS is not set
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# end of kservice optimization
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#
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# klibc optimization
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#
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# CONFIG_RT_KLIBC_USING_STDLIB is not set
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# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set
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# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set
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# end of klibc optimization
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CONFIG_RT_USING_DEBUG=y
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CONFIG_RT_DEBUGING_ASSERT=y
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CONFIG_RT_DEBUGING_COLOR=y
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CONFIG_RT_DEBUGING_CONTEXT=y
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# CONFIG_RT_DEBUGING_AUTO_INIT is not set
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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#
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# Inter-Thread communication
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
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# CONFIG_RT_USING_SIGNALS is not set
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# end of Inter-Thread communication
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#
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# Memory Management
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#
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CONFIG_RT_USING_MEMPOOL=y
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMHEAP is not set
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CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
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# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
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# CONFIG_RT_USING_SLAB_AS_HEAP is not set
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# CONFIG_RT_USING_USERHEAP is not set
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# CONFIG_RT_USING_NOHEAP is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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# CONFIG_RT_USING_HEAP_ISR is not set
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CONFIG_RT_USING_HEAP=y
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# end of Memory Management
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CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_DEVICE_OPS is not set
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
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CONFIG_RT_VER_NUM=0x50200
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# CONFIG_RT_USING_STDC_ATOMIC is not set
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CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
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# end of RT-Thread Kernel
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#
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# RT-Thread Components
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#
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CONFIG_RT_USING_COMPONENTS_INIT=y
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CONFIG_RT_USING_USER_MAIN=y
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CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
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CONFIG_RT_MAIN_THREAD_PRIORITY=10
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# CONFIG_RT_USING_LEGACY is not set
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CONFIG_RT_USING_MSH=y
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CONFIG_RT_USING_FINSH=y
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_THREAD_NAME="tshell"
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_CMD_SIZE=80
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CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_ARG_MAX=10
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CONFIG_FINSH_USING_OPTION_COMPLETION=y
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#
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# DFS: device virtual file system
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#
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# CONFIG_RT_USING_DFS is not set
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# end of DFS: device virtual file system
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# CONFIG_RT_USING_FAL is not set
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#
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# Device Drivers
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#
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# CONFIG_RT_USING_DM is not set
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# CONFIG_RT_USING_DEV_BUS is not set
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CONFIG_RT_USING_DEVICE_IPC=y
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CONFIG_RT_UNAMED_PIPE_NUMBER=64
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CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
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CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
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CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
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CONFIG_RT_USING_SERIAL=y
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CONFIG_RT_USING_SERIAL_V1=y
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# CONFIG_RT_USING_SERIAL_V2 is not set
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CONFIG_RT_SERIAL_USING_DMA=y
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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# CONFIG_RT_USING_PHY is not set
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_DAC is not set
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# CONFIG_RT_USING_NULL is not set
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# CONFIG_RT_USING_ZERO is not set
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# CONFIG_RT_USING_RANDOM is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_PULSE_ENCODER is not set
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# CONFIG_RT_USING_INPUT_CAPTURE is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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# CONFIG_RT_USING_PM is not set
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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# CONFIG_RT_USING_TOUCH is not set
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# CONFIG_RT_USING_LCD is not set
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# CONFIG_RT_USING_HWCRYPTO is not set
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# CONFIG_RT_USING_WIFI is not set
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# CONFIG_RT_USING_VIRTIO is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_KTIME is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CHERRYUSB is not set
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# end of Device Drivers
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#
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# C/C++ and POSIX layer
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#
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#
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# ISO-ANSI C layer
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#
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#
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# Timezone and Daylight Saving Time
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#
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# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
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CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
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CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
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CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
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CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
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# end of Timezone and Daylight Saving Time
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# end of ISO-ANSI C layer
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#
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# POSIX (Portable Operating System Interface) layer
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#
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# CONFIG_RT_USING_POSIX_FS is not set
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# CONFIG_RT_USING_POSIX_DELAY is not set
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# CONFIG_RT_USING_POSIX_CLOCK is not set
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# CONFIG_RT_USING_POSIX_TIMER is not set
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# CONFIG_RT_USING_PTHREADS is not set
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# CONFIG_RT_USING_MODULE is not set
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#
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# Interprocess Communication (IPC)
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#
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# CONFIG_RT_USING_POSIX_PIPE is not set
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# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
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# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
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#
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# Socket is in the 'Network' category
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#
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# end of Interprocess Communication (IPC)
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# end of POSIX (Portable Operating System Interface) layer
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# CONFIG_RT_USING_CPLUSPLUS is not set
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# end of C/C++ and POSIX layer
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#
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# Network
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#
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# CONFIG_RT_USING_SAL is not set
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# CONFIG_RT_USING_NETDEV is not set
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# CONFIG_RT_USING_LWIP is not set
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# CONFIG_RT_USING_AT is not set
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# end of Network
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#
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# Memory protection
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#
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# CONFIG_RT_USING_MEM_PROTECTION is not set
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# CONFIG_RT_USING_HW_STACK_GUARD is not set
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# end of Memory protection
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#
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# Utilities
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#
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# CONFIG_RT_USING_RYM is not set
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# CONFIG_RT_USING_ULOG is not set
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# CONFIG_RT_USING_UTEST is not set
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# CONFIG_RT_USING_VAR_EXPORT is not set
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# CONFIG_RT_USING_RESOURCE_ID is not set
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# CONFIG_RT_USING_ADT is not set
|
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# CONFIG_RT_USING_RT_LINK is not set
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# end of Utilities
|
||||
|
||||
# CONFIG_RT_USING_VBUS is not set
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|
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#
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# Using USB legacy version
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#
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# CONFIG_RT_USING_USB_HOST is not set
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# CONFIG_RT_USING_USB_DEVICE is not set
|
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# end of Using USB legacy version
|
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|
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# CONFIG_RT_USING_FDT is not set
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# end of RT-Thread Components
|
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|
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#
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# RT-Thread Utestcases
|
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#
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# CONFIG_RT_USING_UTESTCASES is not set
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# end of RT-Thread Utestcases
|
||||
|
||||
#
|
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# Hardware Drivers Config
|
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#
|
||||
|
||||
#
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# SOC Series
|
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#
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CONFIG_SOC_SERIES_GD32E50x=y
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CONFIG_SOC_GD32503V=y
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# end of SOC Series
|
||||
|
||||
#
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# Onboard Peripheral Drivers
|
||||
#
|
||||
|
||||
#
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# On-chip Peripheral Drivers
|
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#
|
||||
CONFIG_BSP_USING_GPIO=y
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CONFIG_BSP_USING_UART=y
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CONFIG_BSP_USING_UART0=y
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# CONFIG_BSP_UART0_RX_USING_DMA is not set
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# CONFIG_BSP_USING_UART1 is not set
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# CONFIG_BSP_USING_UART2 is not set
|
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# CONFIG_BSP_USING_UART3 is not set
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# CONFIG_BSP_USING_UART4 is not set
|
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# CONFIG_BSP_USING_UART5 is not set
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# CONFIG_BSP_USING_SPI is not set
|
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# CONFIG_BSP_USING_I2C1 is not set
|
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# CONFIG_BSP_USING_ADC is not set
|
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# CONFIG_BSP_USING_TIM is not set
|
||||
# CONFIG_BSP_USING_ONCHIP_RTC is not set
|
||||
# CONFIG_BSP_USING_WDT is not set
|
||||
# CONFIG_BSP_USING_SDIO is not set
|
||||
# CONFIG_BSP_USING_USBD is not set
|
||||
# CONFIG_BSP_USING_USBH is not set
|
||||
# end of On-chip Peripheral Drivers
|
||||
|
||||
#
|
||||
# Board extended module Drivers
|
||||
#
|
||||
# end of Hardware Drivers Config
|
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12
bsp/gd32/arm/gd32e503v-eval/Kconfig
Normal file
12
bsp/gd32/arm/gd32e503v-eval/Kconfig
Normal file
@@ -0,0 +1,12 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
BSP_DIR := .
|
||||
|
||||
RTT_DIR := ../../../..
|
||||
|
||||
PKGS_DIR := packages
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "../libraries/Kconfig"
|
||||
rsource "board/Kconfig"
|
||||
107
bsp/gd32/arm/gd32e503v-eval/README.md
Normal file
107
bsp/gd32/arm/gd32e503v-eval/README.md
Normal file
@@ -0,0 +1,107 @@
|
||||
# GD32E503V-EVAL 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
GD32E503V-EVAL 评估板使用 GD32E503VET6 作为主控制器。评估板使用 GD-Link Mini
|
||||
USB 接口提供 5V 电源。提供包括扩展引脚在内的及 Reset， Boot， K2， LED， I2S， I2CEEPROM， LCD， NAND Flash， SPI-Flash， SDIO， USB， USART 转 USB 接口等外设资源。
|
||||
|
||||
该开发板常用 ** 板载资源 ** 如下：
|
||||
|
||||
- GD32E503VET6，主频 180MHz，512KB FLASH ，128KB RAM
|
||||
- 常用外设
|
||||
|
||||
- LED ：5 个，LEDPWR (电源指示灯），LED1（PC0），LED2（PC2），LED3（PE0），LED4（PE1）
|
||||
- 按键：5 个，KEY_A（用户按键，PA0），KEY_B（用户按键，PC13），KEY_C（用户按键，PB14），KEY_D（用户按键，PC5），KEY_Cet（用户按键，PC4）
|
||||
- General TM * 10、Advanced TM * 2、Basic TM * 2
|
||||
- 系统时钟 * 1
|
||||
- 看门狗 * 2
|
||||
- RTC * 1
|
||||
- USART * 4、UART * 2
|
||||
- I2C * 2、I2S * 2
|
||||
- SPI * 3
|
||||
- CAN2.0B * 1
|
||||
- USB2.0 OTG FS * 1
|
||||
- TFT-LCD
|
||||
- EXMC/SDRAM * 1
|
||||
- ADC * 3
|
||||
- DAC * 2
|
||||
- 最多支持 100GPIOs
|
||||
- 常用接口：USB 接口
|
||||
- 调试接口：GD-LINK
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| ** 片上外设 ** | ** 支持情况 ** | ** 备注 ** |
|
||||
| :----------- | :----------: | :------------------------------- |
|
||||
| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...111 |
|
||||
| UART | 支持 | UART0 - UART5 |
|
||||
| I2C | 支持 | I2C1 |
|
||||
| SPI | 支持 | SPI0 - SPI2 |
|
||||
| SPI FLASH | 支持 | |
|
||||
| ADC | 支持 | ADC0 - ADC2 |
|
||||
| ** 扩展模块 ** | ** 支持情况 ** | ** 备注 ** |
|
||||
| 暂无 | 暂不支持 | 暂不支持 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境，也可使用 RT-Thread Studio 开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用数据线连接开发板到 PC，使用 USB 转 232 连接 USART1，打开电源开关。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，LED 闪烁。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.4 build Jan 9 2021
|
||||
2006 - 2021 Copyright by rt-thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入 `pkgs --update` 命令更新软件包。
|
||||
|
||||
4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
暂无
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [drifting1024](https://github.com/drifting1024), 邮箱：<drifting1024@163.com>
|
||||
15
bsp/gd32/arm/gd32e503v-eval/SConscript
Normal file
15
bsp/gd32/arm/gd32e503v-eval/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
60
bsp/gd32/arm/gd32e503v-eval/SConstruct
Normal file
60
bsp/gd32/arm/gd32e503v-eval/SConstruct
Normal file
@@ -0,0 +1,60 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
gd32_library = 'GD32E50x_Firmware_Library'
|
||||
rtconfig.BSP_LIBRARY_TYPE = gd32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
15
bsp/gd32/arm/gd32e503v-eval/applications/SConscript
Normal file
15
bsp/gd32/arm/gd32e503v-eval/applications/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
35
bsp/gd32/arm/gd32e503v-eval/applications/main.c
Normal file
35
bsp/gd32/arm/gd32e503v-eval/applications/main.c
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 BruceOu first implementation
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED1 pin: PC0 */
|
||||
#define LED1_PIN GET_PIN(C, 0)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int count = 1;
|
||||
|
||||
/* set LED1 pin mode to output */
|
||||
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (count++)
|
||||
{
|
||||
rt_pin_write(LED1_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED1_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
228
bsp/gd32/arm/gd32e503v-eval/board/Kconfig
Normal file
228
bsp/gd32/arm/gd32e503v-eval/board/Kconfig
Normal file
@@ -0,0 +1,228 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
|
||||
menu "SOC Series"
|
||||
menuconfig SOC_SERIES_GD32E50x
|
||||
bool "Enable GD32E50x"
|
||||
default y
|
||||
select SERIES_GD32E50x
|
||||
if SOC_SERIES_GD32E50x
|
||||
config SOC_GD32503V
|
||||
bool "Enable GD32503V"
|
||||
select GD32503V
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART0
|
||||
bool "Enable UART0"
|
||||
default n
|
||||
|
||||
config BSP_UART0_RX_USING_DMA
|
||||
bool "Enable UART0 RX DMA"
|
||||
depends on BSP_USING_UART0
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART3
|
||||
bool "Enable UART3"
|
||||
default n
|
||||
|
||||
config BSP_UART3_RX_USING_DMA
|
||||
bool "Enable UART3 RX DMA"
|
||||
depends on BSP_USING_UART3
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART4
|
||||
bool "Enable UART4"
|
||||
default n
|
||||
|
||||
config BSP_UART4_RX_USING_DMA
|
||||
bool "Enable UART4 RX DMA"
|
||||
depends on BSP_USING_UART4
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART5
|
||||
bool "Enable UART5"
|
||||
default n
|
||||
|
||||
config BSP_UART5_RX_USING_DMA
|
||||
bool "Enable UART5 RX DMA"
|
||||
depends on BSP_USING_UART5
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI BUS"
|
||||
default n
|
||||
select RT_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_SPI1_TX_USING_DMA
|
||||
bool "Enable SPI1 TX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
default n
|
||||
|
||||
config BSP_SPI1_RX_USING_DMA
|
||||
bool "Enable SPI1 RX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
select BSP_SPI1_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
int "i2c1 scl pin number"
|
||||
range 1 216
|
||||
default 24
|
||||
config BSP_I2C1_SDA_PIN
|
||||
int "I2C1 sda pin number"
|
||||
range 1 216
|
||||
default 25
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
select RT_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
|
||||
config BSP_USING_ADC1
|
||||
bool "Enable ADC1"
|
||||
default n
|
||||
|
||||
config BSP_USING_ADC2
|
||||
bool "Enable ADC2"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_TIM
|
||||
bool "Enable timer"
|
||||
default n
|
||||
select RT_USING_HWTIMER
|
||||
if BSP_USING_TIM
|
||||
config BSP_USING_TIM10
|
||||
bool "Enable TIM10"
|
||||
default n
|
||||
|
||||
config BSP_USING_TIM11
|
||||
bool "Enable TIM11"
|
||||
default n
|
||||
|
||||
config BSP_USING_TIM12
|
||||
bool "Enable TIM13"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ONCHIP_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
if BSP_USING_ONCHIP_RTC
|
||||
choice
|
||||
prompt "Select clock source"
|
||||
default BSP_RTC_USING_LSE
|
||||
|
||||
config BSP_RTC_USING_LSE
|
||||
bool "RTC USING LSE"
|
||||
|
||||
config BSP_RTC_USING_LSI
|
||||
bool "RTC USING LSI"
|
||||
endchoice
|
||||
endif
|
||||
|
||||
config BSP_USING_WDT
|
||||
bool "Enable Watchdog Timer"
|
||||
select RT_USING_WDT
|
||||
default n
|
||||
|
||||
config BSP_USING_SDIO
|
||||
bool "Enable SDIO"
|
||||
select RT_USING_SDIO
|
||||
select RT_USING_DFS
|
||||
default n
|
||||
|
||||
config BSP_USING_USBD
|
||||
bool "Enable USB Device"
|
||||
select RT_USING_USB_DEVICE
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_USBH
|
||||
bool "Enable USB Host"
|
||||
select RT_USING_USB_HOST
|
||||
default n
|
||||
if BSP_USING_USBH
|
||||
menuconfig RT_USBH_MSTORAGE
|
||||
bool "Enable Udisk Drivers"
|
||||
default n
|
||||
if RT_USBH_MSTORAGE
|
||||
config UDISK_MOUNTPOINT
|
||||
string "Udisk mount dir"
|
||||
default "/"
|
||||
endif
|
||||
endif
|
||||
|
||||
rsource "../../libraries/gd32_drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
26
bsp/gd32/arm/gd32e503v-eval/board/SConscript
Normal file
26
bsp/gd32/arm/gd32e503v-eval/board/SConscript
Normal file
@@ -0,0 +1,26 @@
|
||||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src += [startup_path_prefix + '/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32e50x_hd.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32e50x_hd.s']
|
||||
|
||||
CPPDEFINES = ['GD32E50X', 'GD32E50X_HD']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
96
bsp/gd32/arm/gd32e503v-eval/board/board.c
Normal file
96
bsp/gd32/arm/gd32e503v-eval/board/board.c
Normal file
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-10-23 drifting1024 first implementation
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_SERIAL_V2
|
||||
#include "drv_usart_v2.h"
|
||||
#else
|
||||
#include "drv_usart.h"
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
NVIC_SetPriority(SysTick_IRQn, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial GD32 board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
#define NVIC_VTOR_MASK 0x3FFFFF80
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x10000000 */
|
||||
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
|
||||
#else /* VECT_TAB_FLASH */
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
|
||||
#endif
|
||||
|
||||
SystemClock_Config();
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_usart_init();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDRAM
|
||||
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
|
||||
#else
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
46
bsp/gd32/arm/gd32e503v-eval/board/board.h
Normal file
46
bsp/gd32/arm/gd32e503v-eval/board/board.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-10-23 drifting1024 first implementation
|
||||
*/
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "gd32e50x.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#include "gd32e50x_exti.h"
|
||||
|
||||
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
|
||||
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
|
||||
|
||||
/* <o> Internal SRAM memory size[Kbytes] <96-128>*/
|
||||
/* <i>Default: 128*/
|
||||
#ifdef __ICCARM__
|
||||
/* Use *.icf ram symbal, to avoid hardcode.*/
|
||||
extern char __ICFEDIT_region_RAM_end__;
|
||||
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
|
||||
#else
|
||||
#define GD32_SRAM_SIZE 128
|
||||
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END GD32_SRAM_END
|
||||
|
||||
#endif
|
||||
|
||||
100
bsp/gd32/arm/gd32e503v-eval/board/gd32e50x_libopt.h
Normal file
100
bsp/gd32/arm/gd32e503v-eval/board/gd32e50x_libopt.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/*!
|
||||
\file gd32e50x_libopt.h
|
||||
\brief library optional for gd32e50x
|
||||
|
||||
\version 2023-12-31, V1.4.0, firmware for GD32E50x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E50X_LIBOPT_H
|
||||
#define GD32E50X_LIBOPT_H
|
||||
|
||||
#ifndef GD32EPRT
|
||||
|
||||
#include "gd32e50x_adc.h"
|
||||
#include "gd32e50x_bkp.h"
|
||||
#include "gd32e50x_can.h"
|
||||
#include "gd32e50x_crc.h"
|
||||
#include "gd32e50x_ctc.h"
|
||||
#include "gd32e50x_dac.h"
|
||||
#include "gd32e50x_dbg.h"
|
||||
#include "gd32e50x_dma.h"
|
||||
#include "gd32e50x_exmc.h"
|
||||
#include "gd32e50x_exti.h"
|
||||
#include "gd32e50x_fmc.h"
|
||||
#include "gd32e50x_fwdgt.h"
|
||||
#include "gd32e50x_gpio.h"
|
||||
#include "gd32e50x_shrtimer.h"
|
||||
#include "gd32e50x_i2c.h"
|
||||
#include "gd32e50x_misc.h"
|
||||
#include "gd32e50x_pmu.h"
|
||||
#include "gd32e50x_rcu.h"
|
||||
#include "gd32e50x_rtc.h"
|
||||
#include "gd32e50x_spi.h"
|
||||
#include "gd32e50x_timer.h"
|
||||
#include "gd32e50x_usart.h"
|
||||
#include "gd32e50x_wwdgt.h"
|
||||
#include "gd32e50x_sqpi.h"
|
||||
|
||||
#if defined (GD32E50X_CL) || defined (GD32E508)
|
||||
#include "gd32e50x_enet.h"
|
||||
#include "gd32e50x_tmu.h"
|
||||
#include "gd32e50x_cmp.h"
|
||||
#else /* GD32E50X_CL or GD32E508 */
|
||||
#include "gd32e50x_sdio.h"
|
||||
#endif /* GD32E50X_CL or GD32E508 */
|
||||
|
||||
#else /* GD32EPRT */
|
||||
#include "gd32e50x_adc.h"
|
||||
#include "gd32e50x_bkp.h"
|
||||
#include "gd32e50x_crc.h"
|
||||
#include "gd32e50x_ctc.h"
|
||||
#include "gd32e50x_dac.h"
|
||||
#include "gd32e50x_dbg.h"
|
||||
#include "gd32e50x_dma.h"
|
||||
#include "gd32e50x_enet.h"
|
||||
#include "gd32e50x_exmc.h"
|
||||
#include "gd32e50x_exti.h"
|
||||
#include "gd32e50x_fmc.h"
|
||||
#include "gd32e50x_fwdgt.h"
|
||||
#include "gd32e50x_gpio.h"
|
||||
#include "gd32e50x_i2c.h"
|
||||
#include "gd32e50x_misc.h"
|
||||
#include "gd32e50x_pmu.h"
|
||||
#include "gd32e50x_rcu.h"
|
||||
#include "gd32e50x_rtc.h"
|
||||
#include "gd32e50x_spi.h"
|
||||
#include "gd32e50x_timer.h"
|
||||
#include "gd32e50x_usart.h"
|
||||
#include "gd32e50x_wwdgt.h"
|
||||
#include "gd32e50x_sqpi.h"
|
||||
|
||||
#endif /* GD32EPRT */
|
||||
|
||||
#endif /* GD32E50X_LIBOPT_H */
|
||||
40
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.icf
Normal file
40
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.icf
Normal file
@@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x201FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x200;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
|
||||
define symbol __region_RAM1_start__ = 0x10000000;
|
||||
define symbol __region_RAM1_end__ = 0x1000FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section FSymTab };
|
||||
keep { section VSymTab };
|
||||
keep { section .rti_fn* };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM1_region { section .sram };
|
||||
142
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.ld
Normal file
142
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.ld
Normal file
@@ -0,0 +1,142 @@
|
||||
/*
|
||||
* linker script for GD32E50x with GNU ld
|
||||
* BruceOu 2021-12-14
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > CODE = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > CODE
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
15
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.sct
Normal file
15
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.sct
Normal file
@@ -0,0 +1,15 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
BIN
bsp/gd32/arm/gd32e503v-eval/figures/board.jpg
Normal file
BIN
bsp/gd32/arm/gd32e503v-eval/figures/board.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 157 KiB |
3056
bsp/gd32/arm/gd32e503v-eval/project.ewd
Normal file
3056
bsp/gd32/arm/gd32e503v-eval/project.ewd
Normal file
File diff suppressed because it is too large
Load Diff
2145
bsp/gd32/arm/gd32e503v-eval/project.ewp
Normal file
2145
bsp/gd32/arm/gd32e503v-eval/project.ewp
Normal file
File diff suppressed because it is too large
Load Diff
10
bsp/gd32/arm/gd32e503v-eval/project.eww
Normal file
10
bsp/gd32/arm/gd32e503v-eval/project.eww
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
933
bsp/gd32/arm/gd32e503v-eval/project.uvoptx
Normal file
933
bsp/gd32/arm/gd32e503v-eval/project.uvoptx
Normal file
File diff suppressed because it is too large
Load Diff
1107
bsp/gd32/arm/gd32e503v-eval/project.uvproj
Normal file
1107
bsp/gd32/arm/gd32e503v-eval/project.uvproj
Normal file
File diff suppressed because it is too large
Load Diff
2269
bsp/gd32/arm/gd32e503v-eval/project.uvprojx
Normal file
2269
bsp/gd32/arm/gd32e503v-eval/project.uvprojx
Normal file
File diff suppressed because it is too large
Load Diff
161
bsp/gd32/arm/gd32e503v-eval/rtconfig.h
Normal file
161
bsp/gd32/arm/gd32e503v-eval/rtconfig.h
Normal file
@@ -0,0 +1,161 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
/* end of kservice optimization */
|
||||
|
||||
/* klibc optimization */
|
||||
|
||||
/* end of klibc optimization */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_VER_NUM 0x50200
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
/* SOC Series */
|
||||
|
||||
#define SOC_SERIES_GD32E50x
|
||||
#define SOC_GD32503V
|
||||
/* end of SOC Series */
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART0
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
150
bsp/gd32/arm/gd32e503v-eval/rtconfig.py
Normal file
150
bsp/gd32/arm/gd32e503v-eval/rtconfig.py
Normal file
@@ -0,0 +1,150 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='keil'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
1889
bsp/gd32/arm/gd32e503v-eval/template.ewp
Normal file
1889
bsp/gd32/arm/gd32e503v-eval/template.ewp
Normal file
File diff suppressed because it is too large
Load Diff
185
bsp/gd32/arm/gd32e503v-eval/template.uvoptx
Normal file
185
bsp/gd32/arm/gd32e503v-eval/template.uvoptx
Normal file
@@ -0,0 +1,185 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>4</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>Segger\JL2CM3.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U59503607 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
628
bsp/gd32/arm/gd32e503v-eval/template.uvproj
Normal file
628
bsp/gd32/arm/gd32e503v-eval/template.uvproj
Normal file
File diff suppressed because it is too large
Load Diff
414
bsp/gd32/arm/gd32e503v-eval/template.uvprojx
Normal file
414
bsp/gd32/arm/gd32e503v-eval/template.uvprojx
Normal file
@@ -0,0 +1,414 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>GD32E503VE</Device>
|
||||
<Vendor>GigaDevice</Vendor>
|
||||
<PackID>GigaDevice.GD32E50x_DFP.1.5.0</PackID>
|
||||
<PackURL>https://gd32mcu.com/data/documents/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x20000) IROM(0x08000000,0x080000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:GD32E503VE$Device\Include\gd32e50x.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:GD32E503VE$SVD\GD32E50x_HD.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>rtthread-gd32e50x</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M33"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<nBranchProt>0</nBranchProt>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\gd32_rom.ld</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="rt-thread"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,466 @@
|
||||
/*!
|
||||
\file gd32e50x.h
|
||||
\brief general definitions for GD32E50x
|
||||
|
||||
; \version 2023-12-31, V1.4.0, firmware for GD32E50x
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef GD32E50X_H
|
||||
#define GD32E50X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32E50X */
|
||||
#if !defined (GD32EPRT) && !defined (GD32E50X_HD) && !defined (GD32E50X_CL) && !defined (GD32E508)
|
||||
#error "Please select chip type in project configuration"
|
||||
/* #define GD32EPRT */
|
||||
/* #define GD32E50X_HD */
|
||||
/* #define GD32E50X_CL */
|
||||
/* #define GD32E508 */
|
||||
#endif /* define GD32E50X */
|
||||
|
||||
#if !defined (GD32E50X)
|
||||
#error "Please select the target GD32E50x device used in your application (in gd32e50x.h file)"
|
||||
#endif /* undefine GD32E50X tip */
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined HXTAL_VALUE
|
||||
#if defined (GD32E50X_CL) || defined (GD32E508)
|
||||
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
|
||||
#else
|
||||
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 32M *!< value of the external oscillator in Hz*/
|
||||
#endif /* HXTAL_VALUE */
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
||||
#if !defined (IRC8M_VALUE)
|
||||
#define IRC8M_VALUE ((uint32_t)8000000)
|
||||
#endif /* internal 8MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
||||
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 8MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
|
||||
#if !defined (IRC48M_VALUE)
|
||||
#define IRC48M_VALUE ((uint32_t)48000000)
|
||||
#endif /* internal 48MHz RC oscillator value */
|
||||
|
||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
||||
#if !defined (IRC40K_VALUE)
|
||||
#define IRC40K_VALUE ((uint32_t)40000)
|
||||
#endif /* internal 40KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* GD32E50x firmware library version number V1.0 */
|
||||
#define __GD32E50X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __GD32E50X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __GD32E50X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32E50X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32E50X_STDPERIPH_VERSION ((__GD32E50X_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32E50X_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32E50X_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32E50X_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the Cortex-M33 processor and core peripherals */
|
||||
#define __CM33_REV 0x0003U /*!< Core revision r0p3 */
|
||||
#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
|
||||
#define __MPU_PRESENT 1U /*!< MPU is present */
|
||||
#define __VTOR_PRESENT 1U /*!< VTOR is present */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present */
|
||||
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* Cortex-M33 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */
|
||||
HardFault_IRQn = -13, /*!< hard-fault interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M33 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M33 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M33 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M33 sv call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M33 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M33 pend sv interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M33 system tick interrupt */
|
||||
/* interrupt numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
|
||||
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
|
||||
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupt */
|
||||
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupt */
|
||||
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupt */
|
||||
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupt */
|
||||
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupt */
|
||||
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
|
||||
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
|
||||
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
|
||||
|
||||
#ifdef GD32EPRT
|
||||
USBD_HP_IRQn = 19, /*!< USBD High Priority interrupts */
|
||||
USBD_LP_IRQn = 20, /*!< USBD Low Priority interrupts */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
|
||||
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
|
||||
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
|
||||
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupt */
|
||||
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupt */
|
||||
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||||
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
|
||||
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
|
||||
USART5_IRQn = 84, /*!< USART5 interrupt */
|
||||
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
|
||||
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
|
||||
#endif /* GD32EPRT */
|
||||
|
||||
#ifdef GD32E50X_HD
|
||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< USBD High Priority or CAN0 TX interrupts */
|
||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< USBD Low Priority or CAN0 RX0 interrupts */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */
|
||||
SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */
|
||||
SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */
|
||||
SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */
|
||||
SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */
|
||||
SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */
|
||||
SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */
|
||||
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
|
||||
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
|
||||
USART5_IRQn = 84, /*!< USART5 interrupt */
|
||||
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
|
||||
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
|
||||
#endif /* GD32E50X_HD */
|
||||
|
||||
#ifdef GD32E50X_CL
|
||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
|
||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBHS_WKUP_IRQn = 42, /*!< USBHS wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBHS_IRQn = 67, /*!< USBHS global interrupt */
|
||||
SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */
|
||||
SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */
|
||||
SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */
|
||||
SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */
|
||||
SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */
|
||||
USBHS_EP1_OUT_IRQn = 74, /*!< USBHS end point 1 out interrupt */
|
||||
USBHS_EP1_IN_IRQn = 75, /*!< USBHS end point 1 in interrupt */
|
||||
SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */
|
||||
SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */
|
||||
CAN2_TX_IRQn = 78, /*!< CAN2 TX interrupt */
|
||||
CAN2_RX0_IRQn = 79, /*!< CAN2 RX0 interrupt */
|
||||
CAN2_RX1_IRQn = 80, /*!< CAN2 RX1 interrupt */
|
||||
CAN2_EWMC_IRQn = 81, /*!< CAN2 EWMC interrupt */
|
||||
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
|
||||
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
|
||||
USART5_IRQn = 84, /*!< USART5 global interrupt */
|
||||
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
|
||||
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
|
||||
TMU_IRQn = 87, /*!< TMU interrupt */
|
||||
#endif /* GD32E50X_CL */
|
||||
|
||||
#ifdef GD32E508
|
||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
|
||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBHS_WKUP_IRQn = 42, /*!< USBHS wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBHS_IRQn = 67, /*!< USBHS global interrupt */
|
||||
SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */
|
||||
SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */
|
||||
SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */
|
||||
SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */
|
||||
SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */
|
||||
USBHS_EP1_OUT_IRQn = 74, /*!< USBHS end point 1 out interrupt */
|
||||
USBHS_EP1_IN_IRQn = 75, /*!< USBHS end point 1 in interrupt */
|
||||
SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */
|
||||
SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */
|
||||
CAN2_TX_IRQn = 78, /*!< CAN2 TX interrupt */
|
||||
CAN2_RX0_IRQn = 79, /*!< CAN2 RX0 interrupt */
|
||||
CAN2_RX1_IRQn = 80, /*!< CAN2 RX1 interrupt */
|
||||
CAN2_EWMC_IRQn = 81, /*!< CAN2 EWMC interrupt */
|
||||
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
|
||||
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
|
||||
USART5_IRQn = 84, /*!< USART5 global interrupt */
|
||||
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
|
||||
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
|
||||
TMU_IRQn = 87, /*!< TMU interrupt */
|
||||
#endif /* GD32E508 */
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm33.h"
|
||||
#include "system_gd32e50x.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
|
||||
/* bit operations */
|
||||
#define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr))
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
|
||||
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
||||
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
||||
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S_add base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
|
||||
#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */
|
||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
|
||||
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
#define SHRTIMER_BASE (APB2_BUS_BASE + 0x00007400U) /*!< SHRTIMER base address */
|
||||
#define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */
|
||||
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
|
||||
#define TMU_BASE (AHB1_BUS_BASE + 0x00068000U) /*!< TMU base address */
|
||||
#define USBHS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBHS base address */
|
||||
|
||||
/* advanced high performance bus 3 memory map */
|
||||
#define EXMC_BASE (AHB3_BUS_BASE + 0x40000000U) /*!< EXMC base address */
|
||||
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0044000U) /*!< DBG base address */
|
||||
#define SQPI_BASE ((uint32_t)0xA0001000U) /*!< SQPI base address */
|
||||
#include "gd32e50x_libopt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GD32E50X_H */
|
||||
@@ -0,0 +1,50 @@
|
||||
/*!
|
||||
\file system_gd32e50x.h
|
||||
\brief CMSIS Cortex-M33 Device Peripheral Access Layer Header File for
|
||||
GD32E50x Device Series
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32E50X_H
|
||||
#define SYSTEM_GD32E50X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from CPU registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32E50X_H */
|
||||
@@ -0,0 +1,434 @@
|
||||
;/*!
|
||||
; \file startup_gd32e508.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2023-12-31, V1.4.0, firmware for GD32E50x
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBHS_WKUP_IRQHandler ; 58:USBHS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBHS_IRQHandler ; 83:USBHS
|
||||
DCD 0 ; Reserved
|
||||
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
|
||||
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
|
||||
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
|
||||
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
|
||||
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
|
||||
DCD USBHS_EP1_OUT_IRQHandler ; 90:USBHS end point 1 out
|
||||
DCD USBHS_EP1_IN_IRQHandler ; 91:USBHS end point 1 in
|
||||
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
|
||||
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
|
||||
DCD CAN2_TX_IRQHandler ; 94:CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; 95:CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; 96:CAN2 RX1
|
||||
DCD CAN2_EWMC_IRQHandler ; 97:CAN2 EWMC
|
||||
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
|
||||
DCD USART5_IRQHandler ; 100:USART5
|
||||
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
|
||||
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
|
||||
DCD TMU_IRQHandler ; 103:TMU
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ2_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ3_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ4_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ5_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ6_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ0_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_EWMC_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USART5_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TMU_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_I2S1ADD_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBHS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_I2S2ADD_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
SHRTIMER_IRQ2_IRQHandler
|
||||
SHRTIMER_IRQ3_IRQHandler
|
||||
SHRTIMER_IRQ4_IRQHandler
|
||||
SHRTIMER_IRQ5_IRQHandler
|
||||
SHRTIMER_IRQ6_IRQHandler
|
||||
USBHS_EP1_OUT_IRQHandler
|
||||
USBHS_EP1_IN_IRQHandler
|
||||
SHRTIMER_IRQ0_IRQHandler
|
||||
SHRTIMER_IRQ1_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_EWMC_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_WKUP_IRQHandler
|
||||
USART5_WKUP_IRQHandler
|
||||
TMU_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,434 @@
|
||||
;/*!
|
||||
; \file startup_gd32e50x_cl.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2023-12-31, V1.4.0, firmware for GD32E50x
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBHS_WKUP_IRQHandler ; 58:USBHS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBHS_IRQHandler ; 83:USBHS
|
||||
DCD 0 ; Reserved
|
||||
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
|
||||
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
|
||||
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
|
||||
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
|
||||
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
|
||||
DCD USBHS_EP1_OUT_IRQHandler ; 90:USBHS end point 1 out
|
||||
DCD USBHS_EP1_IN_IRQHandler ; 91:USBHS end point 1 in
|
||||
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
|
||||
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
|
||||
DCD CAN2_TX_IRQHandler ; 94:CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; 95:CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; 96:CAN2 RX1
|
||||
DCD CAN2_EWMC_IRQHandler ; 97:CAN2 EWMC
|
||||
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
|
||||
DCD USART5_IRQHandler ; 100:USART5
|
||||
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
|
||||
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
|
||||
DCD TMU_IRQHandler ; 103:TMU
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ2_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ3_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ4_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ5_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ6_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ0_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_EWMC_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USART5_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TMU_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_I2S1ADD_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBHS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_I2S2ADD_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
SHRTIMER_IRQ2_IRQHandler
|
||||
SHRTIMER_IRQ3_IRQHandler
|
||||
SHRTIMER_IRQ4_IRQHandler
|
||||
SHRTIMER_IRQ5_IRQHandler
|
||||
SHRTIMER_IRQ6_IRQHandler
|
||||
USBHS_EP1_OUT_IRQHandler
|
||||
USBHS_EP1_IN_IRQHandler
|
||||
SHRTIMER_IRQ0_IRQHandler
|
||||
SHRTIMER_IRQ1_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_EWMC_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_WKUP_IRQHandler
|
||||
USART5_WKUP_IRQHandler
|
||||
TMU_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,416 @@
|
||||
;/*!
|
||||
; \file startup_gd32e50x_hd.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2023-12-31, V1.4.0, firmware for GD32E50x
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP or CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP or CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD ADC2_IRQHandler ; 63:ADC2
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
|
||||
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
|
||||
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
|
||||
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
|
||||
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
|
||||
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
|
||||
DCD USART5_IRQHandler ; 100:USART5
|
||||
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
|
||||
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBD_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ2_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ3_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ4_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ5_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ6_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ0_IRQHandler [WEAK]
|
||||
EXPORT SHRTIMER_IRQ1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USART5_WKUP_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_I2S1ADD_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBD_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_I2S2ADD_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_4_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
SHRTIMER_IRQ2_IRQHandler
|
||||
SHRTIMER_IRQ3_IRQHandler
|
||||
SHRTIMER_IRQ4_IRQHandler
|
||||
SHRTIMER_IRQ5_IRQHandler
|
||||
SHRTIMER_IRQ6_IRQHandler
|
||||
SHRTIMER_IRQ0_IRQHandler
|
||||
SHRTIMER_IRQ1_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_WKUP_IRQHandler
|
||||
USART5_WKUP_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,392 @@
|
||||
;/*!
|
||||
; \file startup_gd32eprt.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2023-12-31, V1.4.0, firmware for GD32E50x
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD USBD_HP_IRQHandler ; 35:USBD HP
|
||||
DCD USBD_LP_IRQHandler ; 36:USBD LP
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
|
||||
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
|
||||
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
|
||||
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break
|
||||
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update
|
||||
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD ADC2_IRQHandler ; 63:ADC2
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
|
||||
DCD 0 ; Reserved
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
|
||||
DCD USART5_IRQHandler ; 100:USART5
|
||||
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
|
||||
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT USBD_HP_IRQHandler [WEAK]
|
||||
EXPORT USBD_LP_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBD_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USART5_WKUP_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
USBD_HP_IRQHandler
|
||||
USBD_LP_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_IRQHandler
|
||||
TIMER0_UP_IRQHandler
|
||||
TIMER0_TRG_CMT_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_I2S1ADD_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBD_WKUP_IRQHandler
|
||||
TIMER7_BRK_IRQHandler
|
||||
TIMER7_UP_IRQHandler
|
||||
TIMER7_TRG_CMT_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_I2S2ADD_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_WKUP_IRQHandler
|
||||
USART5_WKUP_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,355 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.2
|
||||
* @date 13. February 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* ARM Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* ARM Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
|
||||
#ifndef __ARM_ARCH_6M__
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
#elif (__CORE__ == __ARM7M__)
|
||||
#ifndef __ARM_ARCH_7M__
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#elif (__CORE__ == __ARM7EM__)
|
||||
#ifndef __ARM_ARCH_7EM__
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __noreturn
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __root
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
__packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
/* Workaround for missing __CLZ intrinsic in*/
|
||||
/* various versions of the IAR compilers.*/
|
||||
/* __IAR_FEATURE_CLZ__ should be defined by*/
|
||||
/* the compiler that supports __CLZ internally.*/
|
||||
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
|
||||
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0u)
|
||||
{ return 32u; }
|
||||
|
||||
uint32_t count = 0;
|
||||
uint32_t mask = 0x80000000;
|
||||
|
||||
while ((data & mask) == 0)
|
||||
{
|
||||
count += 1u;
|
||||
mask = mask >> 1u;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TI ARM Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed))T_UINT32
|
||||
{ uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
/* NO RETURN is automatically detected hence no warning here*/
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
1980
bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/CMSIS/cmsis_gcc.h
Normal file
1980
bsp/gd32/arm/libraries/GD32E50x_Firmware_Library/CMSIS/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
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@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
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Reference in New Issue
Block a user