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@@ -0,0 +1,88 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>GD32V103V_EVAL</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>rt-thread</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/include</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/lipcpu</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components/drivers</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components/finsh</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/finsh</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/drivers/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/lipcpu/bumblebee</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/bumblebee</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/lipcpu/common</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/common</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components/drivers/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/drivers/include</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components/drivers/serial</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/drivers/serial</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326" name="GD32VF103xB">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1737722033620" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@@ -0,0 +1,20 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "board/Kconfig"
|
||||
@@ -0,0 +1,119 @@
|
||||
# GD32VF103 #
|
||||
|
||||
## 简介
|
||||
|
||||
gd32vf103v-eval 是由兆易创新公司推出的基于开源指令集 RISC-V 架构的开发板。
|
||||
|
||||
### 板载资源：
|
||||
|
||||
| 硬件 | 描述 |
|
||||
| -- | -- |
|
||||
| 内核 | Bumblebee |
|
||||
| 架构 | 32-bit RV32IMAC |
|
||||
| 主频 | 108 MHz |
|
||||
|
||||
## 编译说明
|
||||
|
||||
### 导入工程
|
||||
打开 Eclipse 选择工作空间
|
||||
|
||||
|
||||
|
||||
打开 Eclipse 后需要导入 RT-Thread 工程
|
||||
|
||||
|
||||
|
||||
选择以存在的工程，并指定工程路径
|
||||
|
||||
|
||||
|
||||
指定工程路径
|
||||
|
||||
|
||||
|
||||
|
||||
### 添加环境变量
|
||||
设置 Build Tools Path
|
||||
|
||||
|
||||
|
||||
点击 MCU 列表中的 Build Tools Path 选项，为其选择 SDK 文件包中提供的对应工具
|
||||
|
||||
设置 OpenOCD Path
|
||||
|
||||
|
||||
|
||||
点击 MCU 列表中的 OpenOCD Path 选项，为其选择 SDK 文件包中提供的对应工具。
|
||||
|
||||
设置 RISC-V Toolchains Path
|
||||
|
||||
|
||||
|
||||
点击 MCU 列表中的 RISC-V Toolchains Paths 选项，为其选择 SDK 文件包中提供的对应工具。
|
||||
|
||||
按照以上步骤设置好路径点击编译即可编译工程
|
||||
|
||||
|
||||
|
||||
## 烧写及执行
|
||||
|
||||
### 替换驱动
|
||||
|
||||
1. 执行 JLink_Windows_V622c.exe (可以是任意版本)安装 JLink 驱动程序。
|
||||
2. 执行 Zadig.exe，点击 Options->List All Devices。
|
||||
3. 在下图 1 处选择 J-Link，2 处选择 WinUSB， 之后点击 3 处 Replace Driver 进行驱动替换。
|
||||
|
||||
|
||||
|
||||
安装完成之后会弹出如下窗口：
|
||||
|
||||
|
||||
|
||||
### 配置 GDB 调试
|
||||
|
||||
在菜单栏中，点击 Run->Debug Configurations，进入 Debug 配置界面，如下图所示：
|
||||
|
||||
|
||||
|
||||
这里使用 OpenOCD 作为 GDB Server，使用GCC工具链中的 GDB 工具作为 GDB Client。双击 GDB OpenOCD Debugging，新建一套 OpenOCD 的配置选项。
|
||||
|
||||
Main 选项卡
|
||||
|
||||
Main 选项卡配置界面
|
||||
|
||||
|
||||
|
||||
选择当前工程 GD32VF103，并且选择当前型号的可执行文件，例如：GD32VF103xB\GD32VF103xB.elf。
|
||||
|
||||
Debugger 选项卡
|
||||
Debugger 选项卡配置界面
|
||||
|
||||
|
||||
|
||||
在 Debugger 选项卡中，确认红圈中的配置正确。
|
||||
其中，“Config options” 是为 OpenOCD 选择配置文件，需要根据当前使用的下载器选择不同的 cfg 文件。
|
||||
|
||||
上述配置内容配置好后，点击应用调试。
|
||||
### 运行结果
|
||||
|
||||
下载程序之后，连接串口(115200-N-8-1)，可以看到 RT-Thread 的输出信息：
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.2 build Jul 24 2019
|
||||
2006 - 2019 Copyright by rt-thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
## 驱动支持情况
|
||||
|
||||
| 驱动 | 支持情况 | 备注 |
|
||||
| ------ | ---- | :------: |
|
||||
| USART | 支持 | UART0_TX/RX：GPIO 9/10 |
|
||||
|
||||
## 5. 联系人信息
|
||||
|
||||
维护人：
|
||||
- [tyustli](https://github.com/tyustli)
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = str(Dir('#'))
|
||||
src = Glob('*.c')
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
group = DefineGroup('', src, depend = [''], CPPPATH = [])
|
||||
#objs += group
|
||||
Return('objs')
|
||||
@@ -0,0 +1,30 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
from building import *
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
env['ASCOM'] = env['ASPPCOM']
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,11 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd, ]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-23 tyustli first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
int main(int argc, char *argv[]) {
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/******************** end of file *******************/
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_GD32VF103V
|
||||
bool
|
||||
select SOC_SERIES_GD32VF103V
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
config BSP_USING_USART
|
||||
bool "Enable USART (usart0)"
|
||||
select BSP_USING_UART
|
||||
select BSP_USING_UART0
|
||||
default y
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable USART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART0
|
||||
bool "Enable USART0"
|
||||
default y
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,11 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-23 tyustli first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
#include <drv_usart.h>
|
||||
#endif
|
||||
|
||||
/* System Tick Configuration */
|
||||
static void systick_config(rt_uint32_t ticks) {
|
||||
/* set value */
|
||||
*(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIMECMP) = ticks;
|
||||
/* enable interrupt */
|
||||
eclic_irq_enable(CLIC_INT_TMR, 0, 0);
|
||||
/* clear value */
|
||||
*(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIME) = 0;
|
||||
}
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void eclic_mtip_handler(void) {
|
||||
/* clear value */
|
||||
*(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIME) = 0;
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
/* tick increase */
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void rt_hw_board_init(void) {
|
||||
systick_config(TMR_FREQ / RT_TICK_PER_SECOND);
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
|
||||
#endif
|
||||
|
||||
/* USART driver initialization is open by default */
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_usart_init();
|
||||
#endif
|
||||
|
||||
/* Set the shell console output device */
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
/* Board underlying hardware initialization */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/******************** end of file *******************/
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-23 tyustli first version
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __BOARD__
|
||||
#define __BOARD__
|
||||
#include "gd32vf103.h"
|
||||
|
||||
extern void *_end;
|
||||
extern void *_heap_end;
|
||||
#define HEAP_BEGIN &_end
|
||||
#define HEAP_END &_heap_end
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif /* __BOARD__ */
|
||||
|
||||
/******************** end of file *******************/
|
||||
@@ -0,0 +1,64 @@
|
||||
/*!
|
||||
\file gd32vf103_libopt.h
|
||||
\brief library optional for gd32vf103
|
||||
|
||||
\version 2019-6-5, V1.0.0, demo for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_LIBOPT_H
|
||||
#define GD32VF103_LIBOPT_H
|
||||
|
||||
#include "gd32vf103_adc.h"
|
||||
#include "gd32vf103_bkp.h"
|
||||
#include "gd32vf103_can.h"
|
||||
#include "gd32vf103_crc.h"
|
||||
#include "gd32vf103_dac.h"
|
||||
#include "gd32vf103_dma.h"
|
||||
#include "gd32vf103_eclic.h"
|
||||
#include "gd32vf103_exmc.h"
|
||||
#include "gd32vf103_exti.h"
|
||||
#include "gd32vf103_fmc.h"
|
||||
#include "gd32vf103_gpio.h"
|
||||
#include "gd32vf103_i2c.h"
|
||||
#include "gd32vf103_fwdgt.h"
|
||||
#include "gd32vf103_dbg.h"
|
||||
#include "gd32vf103_pmu.h"
|
||||
#include "gd32vf103_rcu.h"
|
||||
#include "gd32vf103_rtc.h"
|
||||
#include "gd32vf103_spi.h"
|
||||
#include "gd32vf103_timer.h"
|
||||
#include "gd32vf103_usart.h"
|
||||
#include "gd32vf103_wwdgt.h"
|
||||
#include "n22_func.h"
|
||||
|
||||
#endif /* GD32VF103_LIBOPT_H */
|
||||
|
||||
/******************** end of file *******************/
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Split('''
|
||||
drv_usart.c
|
||||
''')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if GetDepend('RT_USING_PIN'):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
if GetDepend('RT_USING_I2C'):
|
||||
src += ['drv_i2c.c']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,12 @@
|
||||
#ifndef __DRV_UART_H__
|
||||
#define __DRV_UART_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
|
||||
int rt_hw_usart_init(void);
|
||||
|
||||
#endif /* __DRV_USART_H__ */
|
||||
|
||||
/******************* end of file *******************/
|
||||
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|
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@@ -0,0 +1,78 @@
|
||||
/*!
|
||||
\file gd32vf103_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_CRC_H
|
||||
#define GD32VF103_CRC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32VF103_CRC_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,109 @@
|
||||
/*!
|
||||
\file gd32vf103_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_DBG_H
|
||||
#define GD32VF103_DBG_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL */
|
||||
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
|
||||
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
/* debug hold when core is halted */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
|
||||
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* DBG low power mode configurations */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* function declarations */
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* low power behavior configuration */
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* peripheral behavior configuration */
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32VF103_DBG_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,62 @@
|
||||
/*!
|
||||
\file gd32vf103_eclic.h
|
||||
\brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller)
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_ECLIC_H
|
||||
#define GD32VF103_ECLIC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* constants definitions */
|
||||
#define ECLIC_PRIGROUP_LEVEL0_PRIO4 0 /*!< 0 bits for level 4 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL1_PRIO3 1 /*!< 1 bits for level 3 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL2_PRIO2 2 /*!< 2 bits for level 2 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL3_PRIO1 3 /*!< 3 bits for level 1 bits for priority */
|
||||
#define ECLIC_PRIGROUP_LEVEL4_PRIO0 4 /*!< 4 bits for level 0 bits for priority */
|
||||
|
||||
#define __SEV eclic_send_event
|
||||
|
||||
/* function declarations */
|
||||
/* set the priority group */
|
||||
void eclic_priority_group_set(uint32_t prigroup);
|
||||
/* enable the interrupt request */
|
||||
void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority);
|
||||
/* disable the interrupt request */
|
||||
void eclic_irq_disable(uint32_t source);
|
||||
|
||||
/* reset system */
|
||||
void eclic_system_reset(void);
|
||||
/* send event(SEV) */
|
||||
void eclic_send_event(void);
|
||||
|
||||
#endif /* GD32VF103_ECLIC_H */
|
||||
@@ -0,0 +1,126 @@
|
||||
/*!
|
||||
\file gd32vf103_exmc.h
|
||||
\brief definitions for the EXMC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_EXMC_H
|
||||
#define GD32VF103_EXMC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* EXMC definitions */
|
||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||
|
||||
/* registers definitions */
|
||||
/* NOR/PSRAM */
|
||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
|
||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
|
||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
|
||||
|
||||
/* bits definitions */
|
||||
/* NOR/PSRAM */
|
||||
/* EXMC_SNCTLx, x=0 */
|
||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
|
||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
|
||||
|
||||
/* EXMC_SNTCFGx, x=0 */
|
||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
|
||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
|
||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
|
||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXMC NOR/SRAM timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t bus_latency; /*!< configure the bus latency */
|
||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
}exmc_norsram_timing_parameter_struct;
|
||||
|
||||
/* EXMC NOR/SRAM initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */
|
||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */
|
||||
}exmc_norsram_parameter_struct;
|
||||
|
||||
/* EXMC register address */
|
||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
|
||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
|
||||
|
||||
/* NOR bank memory data bus width */
|
||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
|
||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
|
||||
|
||||
/* NOR bank memory type */
|
||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||
|
||||
/* EXMC NOR/SRAM bank region definition */
|
||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||
|
||||
/* EXMC NWAIT signal polarity configuration */
|
||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||
#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_deinit(uint32_t norsram_region);
|
||||
/* exmc_norsram_parameter_struct parameter initialize */
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* initialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* EXMC NOR/SRAM bank enable */
|
||||
void exmc_norsram_enable(uint32_t norsram_region);
|
||||
/* EXMC NOR/SRAM bank disable */
|
||||
void exmc_norsram_disable(uint32_t norsram_region);
|
||||
|
||||
#endif /* GD32VF103_EXMC_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
+104
@@ -0,0 +1,104 @@
|
||||
/*!
|
||||
\file gd32vf103_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_FWDGT_H
|
||||
#define GD32VF103_FWDGT_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
|
||||
/* constants definitions */
|
||||
/* psc register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32VF103_FWDGT_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,125 @@
|
||||
/*!
|
||||
\file gd32vf103_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_PMU_H
|
||||
#define GD32VF103_PMU_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
|
||||
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work at sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work at deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work at standby mode */
|
||||
void pmu_to_standbymode(uint8_t standbymodecmd);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(void);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(void);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable write access to the registers in backup domain */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable write access to the registers in backup domain */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag_reset);
|
||||
|
||||
#endif /* GD32VF103_PMU_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,148 @@
|
||||
/*!
|
||||
\file gd32vf103_rtc.h
|
||||
\brief definitions for the RTC
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_RTC_H
|
||||
#define GD32VF103_RTC_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* RTC definitions */
|
||||
#define RTC RTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
|
||||
#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
|
||||
#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
|
||||
#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
|
||||
#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
|
||||
#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
|
||||
#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
|
||||
#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
|
||||
#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
|
||||
#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTC_INTEN */
|
||||
#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
|
||||
#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
|
||||
#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC_CTL */
|
||||
#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
|
||||
#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
|
||||
#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
|
||||
#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
|
||||
#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
|
||||
#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
|
||||
|
||||
/* RTC_PSCH */
|
||||
#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
|
||||
|
||||
/* RTC_PSCL */
|
||||
#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
|
||||
|
||||
/* RTC_DIVH */
|
||||
#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
|
||||
|
||||
/* RTC_DIVL */
|
||||
#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
|
||||
|
||||
/* RTC_CNTH */
|
||||
#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
|
||||
|
||||
/* RTC_CNTL */
|
||||
#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
|
||||
|
||||
/* RTC_ALRMH */
|
||||
#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
|
||||
|
||||
/* RTC_ALRML */
|
||||
#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
|
||||
|
||||
/* constants definitions */
|
||||
/* RTC interrupt enable or disable definitions */
|
||||
#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
|
||||
#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
|
||||
#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC interrupt flag definitions */
|
||||
#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
|
||||
/* RTC flag definitions */
|
||||
#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
|
||||
#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* enter RTC configuration mode */
|
||||
void rtc_configuration_mode_enter(void);
|
||||
/* exit RTC configuration mode */
|
||||
void rtc_configuration_mode_exit(void);
|
||||
/* set RTC counter value */
|
||||
void rtc_counter_set(uint32_t cnt);
|
||||
/* set RTC prescaler value */
|
||||
void rtc_prescaler_set(uint32_t psc);
|
||||
|
||||
/* operation functions */
|
||||
/* wait RTC last write operation finished flag set */
|
||||
void rtc_lwoff_wait(void);
|
||||
/* wait RTC registers synchronized flag set */
|
||||
void rtc_register_sync_wait(void);
|
||||
/* set RTC alarm value */
|
||||
void rtc_alarm_config(uint32_t alarm);
|
||||
/* get RTC counter value */
|
||||
uint32_t rtc_counter_get(void);
|
||||
/* get RTC divider value */
|
||||
uint32_t rtc_divider_get(void);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* get RTC flag status */
|
||||
FlagStatus rtc_flag_get(uint32_t flag);
|
||||
/* clear RTC flag status */
|
||||
void rtc_flag_clear(uint32_t flag);
|
||||
/* get RTC interrupt flag status */
|
||||
FlagStatus rtc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear RTC interrupt flag status */
|
||||
void rtc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable RTC interrupt */
|
||||
void rtc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable RTC interrupt */
|
||||
void rtc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
#endif /* GD32VF103_RTC_H */
|
||||
File diff suppressed because it is too large.
Load diff
+722
File diff suppressed because it is too large.
Load diff
+374
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,86 @@
|
||||
/*!
|
||||
\file gd32vf103_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32VF103_WWDGT_H
|
||||
#define GD32VF103_WWDGT_H
|
||||
|
||||
#include "gd32vf103.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
|
||||
#endif /* GD32VF103_WWDGT_H */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,127 @@
|
||||
/*!
|
||||
\file gd32vf103_crc.c
|
||||
\brief CRC driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_crc.h"
|
||||
|
||||
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
|
||||
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
|
||||
|
||||
/*!
|
||||
\brief deinit CRC calculation unit
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_deinit(void)
|
||||
{
|
||||
CRC_DATA = CRC_DATA_RESET_VALUE;
|
||||
CRC_FDATA = CRC_FDATA_RESET_VALUE;
|
||||
CRC_CTL = (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_data_register_reset(void)
|
||||
{
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the value of the data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 32-bit value of the data register
|
||||
*/
|
||||
uint32_t crc_data_register_read(void)
|
||||
{
|
||||
uint32_t data;
|
||||
data = CRC_DATA;
|
||||
return (data);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the value of the free data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 8-bit value of the free data register
|
||||
*/
|
||||
uint8_t crc_free_data_register_read(void)
|
||||
{
|
||||
uint8_t fdata;
|
||||
fdata = (uint8_t)CRC_FDATA;
|
||||
return (fdata);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the free data register
|
||||
\param[in] free_data: specified 8-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_free_data_register_write(uint8_t free_data)
|
||||
{
|
||||
CRC_FDATA = (uint32_t)free_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief calculate the CRC value of a 32-bit data
|
||||
\param[in] sdata: specified 32-bit data
|
||||
\param[out] none
|
||||
\retval 32-bit value calculated by CRC
|
||||
*/
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata)
|
||||
{
|
||||
CRC_DATA = sdata;
|
||||
return (CRC_DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief calculate the CRC value of an array of 32-bit values
|
||||
\param[in] array: pointer to an array of 32-bit values
|
||||
\param[in] size: size of the array
|
||||
\param[out] none
|
||||
\retval 32-bit value calculated by CRC
|
||||
*/
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
|
||||
{
|
||||
uint32_t index;
|
||||
for(index = 0U; index < size; index++){
|
||||
CRC_DATA = array[index];
|
||||
}
|
||||
return (CRC_DATA);
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,110 @@
|
||||
/*!
|
||||
\file gd32vf103_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_dbg.h"
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_CTL |= (uint32_t)dbg_periph;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_CTL &= ~(uint32_t)dbg_periph;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,99 @@
|
||||
/*!
|
||||
\file gd32vf103_eclic.c
|
||||
\brief ECLIC(Enhancement Core-Local Interrupt Controller) driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_eclic.h"
|
||||
#include "riscv_encoding.h"
|
||||
|
||||
#define REG_DBGMCU2 ((uint32_t)0xE0042008)
|
||||
#define REG_DBGMCU2EN ((uint32_t)0xE004200C)
|
||||
|
||||
/*!
|
||||
\brief set the priority group
|
||||
\param[in] prigroup: specify the priority group
|
||||
\arg ECLIC_PRIGROUP_LEVEL0_PRIO4
|
||||
\arg ECLIC_PRIGROUP_LEVEL1_PRIO3
|
||||
\arg ECLIC_PRIGROUP_LEVEL2_PRIO2
|
||||
\arg ECLIC_PRIGROUP_LEVEL3_PRIO1
|
||||
\arg ECLIC_PRIGROUP_LEVEL4_PRIO0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_priority_group_set(uint32_t prigroup) {
|
||||
eclic_set_nlbits(prigroup);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the interrupt request
|
||||
\param[in] source: interrupt request, detailed in IRQn_Type
|
||||
\param[in] level: the level needed to set (maximum is 16)
|
||||
\param[in] priority: the priority needed to set (maximum is 16)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) {
|
||||
eclic_enable_interrupt(source);
|
||||
eclic_set_int_level(source, level);
|
||||
eclic_set_int_priority(source, priority);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the interrupt request
|
||||
\param[in] source: interrupt request, detailed in IRQn_Type
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_irq_disable(uint32_t source) {
|
||||
eclic_disable_interrupt(source);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_system_reset(void) {
|
||||
REG32(REG_DBGMCU2EN) = 0x4b5a6978;
|
||||
REG32(REG_DBGMCU2) = 0x1;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief send event(SEV)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void eclic_send_event(void) {
|
||||
set_csr(0x812, 0x1);
|
||||
}
|
||||
@@ -0,0 +1,164 @@
|
||||
/*!
|
||||
\file gd32vf103_exmc.c
|
||||
\brief EXMC driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_exmc.h"
|
||||
|
||||
/* EXMC bank0 register reset value */
|
||||
#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU)
|
||||
#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
|
||||
|
||||
/* EXMC register bit offset */
|
||||
#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
|
||||
#define SNCTL_WREN_OFFSET ((uint32_t)12U)
|
||||
#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
|
||||
#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
|
||||
|
||||
#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
|
||||
#define SNTCFG_DSET_OFFSET ((uint32_t)8U)
|
||||
#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
|
||||
|
||||
/*!
|
||||
\brief deinitialize EXMC NOR/SRAM region
|
||||
\param[in] norsram_region: select the region of bank0
|
||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_deinit(uint32_t norsram_region)
|
||||
{
|
||||
/* reset the registers */
|
||||
if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
|
||||
EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
|
||||
}
|
||||
|
||||
EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize the structure exmc_norsram_parameter_struct
|
||||
\param[in] none
|
||||
\param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||
{
|
||||
/* configure the structure with default value */
|
||||
exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
|
||||
exmc_norsram_init_struct->address_data_mux = ENABLE;
|
||||
exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
|
||||
exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
|
||||
exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
|
||||
exmc_norsram_init_struct->memory_write = ENABLE;
|
||||
exmc_norsram_init_struct->nwait_signal = ENABLE;
|
||||
exmc_norsram_init_struct->asyn_wait = DISABLE;
|
||||
|
||||
/* read/write timing configure */
|
||||
exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
|
||||
exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
|
||||
exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
|
||||
exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize EXMC NOR/SRAM region
|
||||
\param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
|
||||
norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0
|
||||
asyn_wait: ENABLE or DISABLE
|
||||
nwait_signal: ENABLE or DISABLE
|
||||
memory_write: ENABLE or DISABLE
|
||||
nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
|
||||
databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
|
||||
memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
|
||||
address_data_mux: ENABLE
|
||||
read_write_timing: structure exmc_norsram_timing_parameter_struct set the time
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||
{
|
||||
uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U;
|
||||
|
||||
/* get the register value */
|
||||
snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
|
||||
|
||||
/* clear relative bits */
|
||||
snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL |
|
||||
EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
|
||||
|
||||
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
|
||||
exmc_norsram_init_struct->memory_type |
|
||||
exmc_norsram_init_struct->databus_width |
|
||||
exmc_norsram_init_struct->nwait_polarity |
|
||||
(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
|
||||
(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
|
||||
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
|
||||
|
||||
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
|
||||
(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
|
||||
(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
|
||||
(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT );
|
||||
|
||||
/* nor flash access enable */
|
||||
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
|
||||
snctl |= (uint32_t)EXMC_SNCTL_NREN;
|
||||
}
|
||||
|
||||
/* configure the registers */
|
||||
EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
|
||||
EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable EXMC NOR/PSRAM bank region
|
||||
\param[in] norsram_region: specify the region of NOR/PSRAM bank
|
||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_enable(uint32_t norsram_region)
|
||||
{
|
||||
EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable EXMC NOR/PSRAM bank region
|
||||
\param[in] norsram_region: specify the region of NOR/PSRAM bank
|
||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exmc_norsram_disable(uint32_t norsram_region)
|
||||
{
|
||||
EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,151 @@
|
||||
/*!
|
||||
\file gd32vf103_fwdgt.c
|
||||
\brief FWDGT driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_fwdgt.h"
|
||||
|
||||
/* write value to FWDGT_CTL_CMD bit field */
|
||||
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/*!
|
||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_disable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the free watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reload the counter of FWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_counter_reload(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter reload value, and prescaler divider value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_div: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
/* wait until the PUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_div;
|
||||
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
/* wait until the RUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
if(FWDGT_STAT & flag){
|
||||
return SET;
|
||||
}
|
||||
|
||||
return RESET;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
+1965
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,146 @@
|
||||
/*!
|
||||
\file gd32vf103_wwdgt.c
|
||||
\brief WWDGT driver
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32vf103_wwdgt.h"
|
||||
|
||||
/* write value to WWDGT_CTL_CNT bit field */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
/* write value to WWDGT_CFG_WIN bit field */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/*!
|
||||
\brief reset the window watchdog timer configuration
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_WWDGTRST);
|
||||
rcu_periph_reset_disable(RCU_WWDGTRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the window watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_enable(void)
|
||||
{
|
||||
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the window watchdog timer counter value
|
||||
\param[in] counter_value: 0x00 - 0x7F
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_counter_update(uint16_t counter_value)
|
||||
{
|
||||
uint32_t reg = 0U;
|
||||
|
||||
reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
|
||||
reg |= CTL_CNT(counter_value);
|
||||
|
||||
WWDGT_CTL = reg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter value, window value, and prescaler divider value
|
||||
\param[in] counter: 0x00 - 0x7F
|
||||
\param[in] window: 0x00 - 0x7F
|
||||
\param[in] prescaler: wwdgt prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
|
||||
\arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
|
||||
\arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
|
||||
\arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
|
||||
{
|
||||
uint32_t reg_cfg = 0U, reg_ctl = 0U;
|
||||
|
||||
/* clear WIN and PSC bits, clear CNT bit */
|
||||
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
|
||||
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
|
||||
|
||||
/* configure WIN and PSC bits, configure CNT bit */
|
||||
reg_cfg |= CFG_WIN(window);
|
||||
reg_cfg |= prescaler;
|
||||
reg_ctl |= CTL_CNT(counter);
|
||||
|
||||
WWDGT_CTL = reg_ctl;
|
||||
WWDGT_CFG = reg_cfg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable early wakeup interrupt of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_interrupt_enable(void)
|
||||
{
|
||||
WWDGT_CFG |= WWDGT_CFG_EWIE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief check early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus wwdgt_flag_get(void)
|
||||
{
|
||||
if(WWDGT_STAT & WWDGT_STAT_EWIF){
|
||||
return SET;
|
||||
}
|
||||
|
||||
return RESET;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_flag_clear(void)
|
||||
{
|
||||
WWDGT_STAT &= (~WWDGT_STAT_EWIF);
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,60 @@
|
||||
/*!
|
||||
\file system_gd32vf103.h
|
||||
\brief RISC-V Device Peripheral Access Layer Header File for
|
||||
GD32VF103 Device Series
|
||||
|
||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32VF103_H
|
||||
#define SYSTEM_GD32VF103_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit(void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32VF103_H */
|
||||
@@ -0,0 +1,127 @@
|
||||
#ifndef __CORE_V5_H__
|
||||
#define __CORE_V5_H__
|
||||
|
||||
#define MSTATUS_UIE 0x00000001
|
||||
#define MSTATUS_SIE 0x00000002
|
||||
#define MSTATUS_HIE 0x00000004
|
||||
#define MSTATUS_MIE 0x00000008
|
||||
#define MSTATUS_UPIE 0x00000010
|
||||
#define MSTATUS_SPIE 0x00000020
|
||||
#define MSTATUS_HPIE 0x00000040
|
||||
#define MSTATUS_MPIE 0x00000080
|
||||
#define MSTATUS_SPP 0x00000100
|
||||
#define MSTATUS_HPP 0x00000600
|
||||
#define MSTATUS_MPP 0x00001800
|
||||
#define MSTATUS_FS 0x00006000
|
||||
#define MSTATUS_XS 0x00018000
|
||||
#define MSTATUS_MPRV 0x00020000
|
||||
#define MSTATUS_PUM 0x00040000
|
||||
#define MSTATUS_MXR 0x00080000
|
||||
#define MSTATUS_VM 0x1F000000
|
||||
#define MSTATUS32_SD 0x80000000
|
||||
#define MSTATUS64_SD 0x8000000000000000
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x7FFFFFFFUL
|
||||
#endif
|
||||
|
||||
#define IRQ_S_SOFT 1
|
||||
#define IRQ_H_SOFT 2
|
||||
#define IRQ_M_SOFT 3
|
||||
#define IRQ_S_TIMER 5
|
||||
#define IRQ_H_TIMER 6
|
||||
#define IRQ_M_TIMER 7
|
||||
#define IRQ_S_EXT 9
|
||||
#define IRQ_H_EXT 10
|
||||
#define IRQ_M_EXT 11
|
||||
#define IRQ_COP 12
|
||||
#define IRQ_HOST 13
|
||||
|
||||
/* Machine mode MCAUSE */
|
||||
#define TRAP_M_I_ACC_FAULT 1 /* Instruction access fault */
|
||||
#define TRAP_M_L_ACC_FAULT 5 /* Data load access fault */
|
||||
#define TRAP_M_S_ACC_FAULT 7 /* Data store access fault */
|
||||
#define TRAP_U_ECALL 8
|
||||
#define TRAP_S_ECALL 9
|
||||
#define TRAP_H_ECALL 10
|
||||
#define TRAP_M_ECALL 11
|
||||
#define TRAP_M_I_PAGE_FAULT 12 /* Instruction page fault */
|
||||
#define TRAP_M_L_PAGE_FAULT 13 /* Data load page fault */
|
||||
#define TRAP_M_S_PAGE_FAULT 15 /* Data store page fault */
|
||||
#define TRAP_M_STACKOVF 32
|
||||
#define TRAP_M_STACKUDF 33
|
||||
|
||||
/* Supervisor mode SCAUSE */
|
||||
#define TRAP_S_I_ACC_FAULT 1 /* Instruction access fault */
|
||||
#define TRAP_S_L_ACC_FAULT 5 /* Data load access fault */
|
||||
#define TRAP_S_S_ACC_FAULT 7 /* Data store access fault */
|
||||
#define TRAP_S_I_PAGE_FAULT 12 /* Instruction page fault */
|
||||
#define TRAP_S_L_PAGE_FAULT 13 /* Data load page fault */
|
||||
#define TRAP_S_S_PAGE_FAULT 15 /* Data store page fault */
|
||||
|
||||
#define MIP_SSIP (1 << IRQ_S_SOFT)
|
||||
#define MIP_HSIP (1 << IRQ_H_SOFT)
|
||||
#define MIP_MSIP (1 << IRQ_M_SOFT)
|
||||
#define MIP_STIP (1 << IRQ_S_TIMER)
|
||||
#define MIP_HTIP (1 << IRQ_H_TIMER)
|
||||
#define MIP_MTIP (1 << IRQ_M_TIMER)
|
||||
#define MIP_SEIP (1 << IRQ_S_EXT)
|
||||
#define MIP_HEIP (1 << IRQ_H_EXT)
|
||||
#define MIP_MEIP (1 << IRQ_M_EXT)
|
||||
|
||||
/* MILMB and MDLMB */
|
||||
#define MILMB_IEN (0x1UL)
|
||||
#define MDLMB_DEN (0x1UL)
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
# define SLL32 sllw
|
||||
# define STORE sd
|
||||
# define LOAD ld
|
||||
# define LWU lwu
|
||||
# define LOG_REGBYTES 3
|
||||
#else
|
||||
# define SLL32 sll
|
||||
# define STORE sw
|
||||
# define LOAD lw
|
||||
# define LWU lw
|
||||
# define LOG_REGBYTES 2
|
||||
#endif
|
||||
#define REGBYTES (1 << LOG_REGBYTES)
|
||||
|
||||
#if __riscv_flen == 64
|
||||
# define FPSTORE fsd
|
||||
# define FPLOAD fld
|
||||
# define LOG_FPREGBYTES 3
|
||||
#else
|
||||
# define FPSTORE fsw
|
||||
# define FPLOAD flw
|
||||
# define LOG_FPREGBYTES 2
|
||||
#endif
|
||||
#define FPREGBYTES (1 << LOG_FPREGBYTES)
|
||||
|
||||
#define STR(S) #S
|
||||
#define XSTR(S) STR(S)
|
||||
|
||||
#define PUSH XSTR(STORE)
|
||||
#define POP XSTR(LOAD)
|
||||
#define REGSIZE XSTR(REGBYTES)
|
||||
#define FPPUSH XSTR(FPSTORE)
|
||||
#define FPPOP XSTR(FPLOAD)
|
||||
#define FPREGSIZE XSTR(FPREGBYTES)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
|
||||
#define read_csr(reg) __nds__csrr(reg)
|
||||
#define write_csr(reg, val) __nds__csrw(val, reg)
|
||||
#define swap_csr(reg, val) __nds__csrrw(val, reg)
|
||||
#define set_csr(reg, bit) __nds__csrrs(bit, reg)
|
||||
#define clear_csr(reg, bit) __nds__csrrc(bit, reg)
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __CORE_V5_H__
|
||||
@@ -0,0 +1,47 @@
|
||||
// See LICENSE file for licence details
|
||||
|
||||
#ifndef N22_ECLIC_H
|
||||
#define N22_ECLIC_H
|
||||
#include <riscv_const.h>
|
||||
|
||||
#define ECLICINTCTLBITS 4
|
||||
|
||||
//ECLIC memory map
|
||||
// Offset
|
||||
// 0x0000 1B RW ecliccfg
|
||||
#define ECLIC_CFG_OFFSET 0x0
|
||||
// 0x0004 4B R eclicinfo
|
||||
#define ECLIC_INFO_OFFSET 0x4
|
||||
// 0x000B 1B RW mintthresh
|
||||
#define ECLIC_MTH_OFFSET 0xB
|
||||
//
|
||||
// 0x1000+4*i 1B/input RW eclicintip[i]
|
||||
#define ECLIC_INT_IP_OFFSET _AC(0x1000,UL)
|
||||
// 0x1001+4*i 1B/input RW eclicintie[i]
|
||||
#define ECLIC_INT_IE_OFFSET _AC(0x1001,UL)
|
||||
// 0x1002+4*i 1B/input RW eclicintattr[i]
|
||||
#define ECLIC_INT_ATTR_OFFSET _AC(0x1002,UL)
|
||||
|
||||
#define ECLIC_INT_ATTR_SHV 0x01
|
||||
#define ECLIC_INT_ATTR_TRIG_LEVEL 0x00
|
||||
#define ECLIC_INT_ATTR_TRIG_EDGE 0x02
|
||||
#define ECLIC_INT_ATTR_TRIG_POS 0x00
|
||||
#define ECLIC_INT_ATTR_TRIG_NEG 0x04
|
||||
|
||||
// 0x1003+4*i 1B/input RW eclicintctl[i]
|
||||
#define ECLIC_INT_CTRL_OFFSET _AC(0x1003,UL)
|
||||
//
|
||||
// ...
|
||||
//
|
||||
#define ECLIC_ADDR_BASE 0xd2000000
|
||||
|
||||
|
||||
#define ECLIC_CFG_NLBITS_MASK _AC(0x1E,UL)
|
||||
#define ECLIC_CFG_NLBITS_LSB (1u)
|
||||
|
||||
#define MSIP_HANDLER eclic_msip_handler
|
||||
#define MTIME_HANDLER eclic_mtip_handler
|
||||
#define BWEI_HANDLER eclic_bwei_handler
|
||||
#define PMOVI_HANDLER eclic_pmovi_handler
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,82 @@
|
||||
// See LICENSE file for licence details
|
||||
|
||||
#ifndef N22_FUNC_H
|
||||
#define N22_FUNC_H
|
||||
|
||||
|
||||
#include "n22_tmr.h"
|
||||
#include "n22_eclic.h"
|
||||
|
||||
#define ECLIC_GROUP_LEVEL0_PRIO4 0
|
||||
#define ECLIC_GROUP_LEVEL1_PRIO3 1
|
||||
#define ECLIC_GROUP_LEVEL2_PRIO2 2
|
||||
#define ECLIC_GROUP_LEVEL3_PRIO1 3
|
||||
#define ECLIC_GROUP_LEVEL4_PRIO0 4
|
||||
|
||||
void switch_m2u_mode();
|
||||
uint32_t get_tmr_freq();
|
||||
uint32_t mtime_lo(void);
|
||||
uint32_t mtime_hi(void);
|
||||
uint64_t get_timer_value();
|
||||
uint64_t get_instret_value();
|
||||
uint64_t get_cycle_value();
|
||||
|
||||
void eclic_init(uint32_t num_irq);
|
||||
|
||||
void eclic_enable_interrupt(uint32_t source);
|
||||
void eclic_disable_interrupt(uint32_t source);
|
||||
|
||||
void eclic_set_pending(uint32_t source);
|
||||
void eclic_clear_pending(uint32_t source);
|
||||
|
||||
void eclic_set_intctrl(uint32_t source, uint8_t intctrl);
|
||||
uint8_t eclic_get_intctrl(uint32_t source);
|
||||
|
||||
void eclic_set_intattr(uint32_t source, uint8_t intattr);
|
||||
uint8_t eclic_get_intattr(uint32_t source);
|
||||
|
||||
void eclic_set_ecliccfg(uint8_t ecliccfg);
|
||||
uint8_t eclic_get_ecliccfg();
|
||||
|
||||
void eclic_set_mth(uint8_t mth);
|
||||
uint8_t eclic_get_mth();
|
||||
|
||||
void eclic_set_nlbits(uint8_t nlbits);
|
||||
uint8_t eclic_get_nlbits();
|
||||
|
||||
uint8_t eclic_set_int_level(uint32_t source, uint8_t level);
|
||||
uint8_t eclic_get_int_level(uint32_t source);
|
||||
|
||||
uint8_t eclic_set_int_priority(uint32_t source, uint8_t priority);
|
||||
uint8_t eclic_get_int_priority(uint32_t source);
|
||||
|
||||
void eclic_mode_enable();
|
||||
void eclic_set_shv(uint32_t source, uint8_t shv);
|
||||
void eclic_set_trig(uint32_t source, uint8_t trig);
|
||||
|
||||
///** \brief Wait For Interrupt
|
||||
//
|
||||
// Wait For Interrupt is a hint instruction that suspends execution
|
||||
// until one of a number of events occurs.
|
||||
// */
|
||||
__attribute__( ( always_inline ) ) static inline void __WFI(void) {
|
||||
__asm volatile ("wfi");
|
||||
}
|
||||
//
|
||||
//
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static inline void __WFE(void)
|
||||
{
|
||||
__asm volatile ("wfi");
|
||||
}
|
||||
|
||||
void close_timer(void);
|
||||
void open_timer(void);
|
||||
void enable_timer_interrupt(void);
|
||||
void clear_timer_interrupt(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
// See LICENSE file for licence details
|
||||
|
||||
#ifndef N22_TMR_H
|
||||
#define N22_TMR_H
|
||||
|
||||
#define TMR_MSIP 0xFFC
|
||||
#define TMR_MSIP_size 0x4
|
||||
#define TMR_MTIMECMP 0x8
|
||||
#define TMR_MTIMECMP_size 0x8
|
||||
#define TMR_MTIME 0x0
|
||||
#define TMR_MTIME_size 0x8
|
||||
|
||||
#define TMR_CTRL_ADDR 0xd1000000
|
||||
#define TMR_REG(offset) _REG32(TMR_CTRL_ADDR, offset)
|
||||
#define TMR_FREQ ((uint32_t)SystemCoreClock/4) //units HZ
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
// See LICENSE for license details.
|
||||
#ifndef _RISCV_BITS_H
|
||||
#define _RISCV_BITS_H
|
||||
|
||||
#define likely(x) __builtin_expect((x), 1)
|
||||
#define unlikely(x) __builtin_expect((x), 0)
|
||||
|
||||
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
|
||||
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
|
||||
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
|
||||
|
||||
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
|
||||
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
|
||||
|
||||
#define STR(x) XSTR(x)
|
||||
#define XSTR(x) #x
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
# define SLL32 sllw
|
||||
# define STORE sd
|
||||
# define LOAD ld
|
||||
# define LWU lwu
|
||||
# define LOG_REGBYTES 3
|
||||
#else
|
||||
# define SLL32 sll
|
||||
# define STORE sw
|
||||
# define LOAD lw
|
||||
# define LWU lw
|
||||
# define LOG_REGBYTES 2
|
||||
#endif
|
||||
#define REGBYTES (1 << LOG_REGBYTES)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,18 @@
|
||||
// See LICENSE for license details.
|
||||
/* Derived from <linux/const.h> */
|
||||
|
||||
#ifndef _RISCV_CONST_H
|
||||
#define _RISCV_CONST_H
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define _AC(X,Y) X
|
||||
#define _AT(T,X) X
|
||||
#else
|
||||
#define _AC(X,Y) (X##Y)
|
||||
#define _AT(T,X) ((T)(X))
|
||||
#endif /* !__ASSEMBLER__*/
|
||||
|
||||
#define _BITUL(x) (_AC(1,UL) << (x))
|
||||
#define _BITULL(x) (_AC(1,ULL) << (x))
|
||||
|
||||
#endif /* _NUCLEI_CONST_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,17 @@
|
||||
// See LICENSE for license details.
|
||||
#ifndef _SECTIONS_H
|
||||
#define _SECTIONS_H
|
||||
|
||||
extern unsigned char _rom[];
|
||||
extern unsigned char _rom_end[];
|
||||
|
||||
extern unsigned char _ram[];
|
||||
extern unsigned char _ram_end[];
|
||||
|
||||
extern unsigned char _ftext[];
|
||||
extern unsigned char _etext[];
|
||||
extern unsigned char _fbss[];
|
||||
extern unsigned char _ebss[];
|
||||
extern unsigned char _end[];
|
||||
|
||||
#endif /* _SECTIONS_H */
|
||||
@@ -0,0 +1,175 @@
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Run in FLASH */
|
||||
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
|
||||
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
|
||||
|
||||
/* Run in RAM */
|
||||
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
|
||||
ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash
|
||||
|
||||
.ilalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ilm_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.ialign :
|
||||
{
|
||||
PROVIDE( _ilm = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);/*0x80022c8*/
|
||||
PROVIDE (etext = .);/*0x80022c8*/
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash
|
||||
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800);
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . ); /*0X2000,0340*/
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram
|
||||
}
|
||||
@@ -0,0 +1,175 @@
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Run in FLASH */
|
||||
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
|
||||
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
|
||||
|
||||
/* Run in RAM */
|
||||
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
|
||||
ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash
|
||||
|
||||
.ilalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ilm_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.ialign :
|
||||
{
|
||||
PROVIDE( _ilm = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);/*0x80022c8*/
|
||||
PROVIDE (etext = .);/*0x80022c8*/
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash
|
||||
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800);
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . ); /*0X2000,0340*/
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram
|
||||
}
|
||||
@@ -0,0 +1,175 @@
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Run in FLASH */
|
||||
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
|
||||
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
|
||||
|
||||
/* Run in RAM */
|
||||
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
|
||||
ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash
|
||||
|
||||
.ilalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ilm_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.ialign :
|
||||
{
|
||||
PROVIDE( _ilm = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);/*0x80022c8*/
|
||||
PROVIDE (etext = .);/*0x80022c8*/
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash
|
||||
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800);
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . ); /*0X2000,0340*/
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram
|
||||
}
|
||||
@@ -0,0 +1,199 @@
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Run in FLASH */
|
||||
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
|
||||
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
|
||||
/* Run in RAM */
|
||||
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
|
||||
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash
|
||||
|
||||
.ilalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ilm_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.ialign :
|
||||
{
|
||||
PROVIDE( _ilm = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
|
||||
__rtmsymtab_start = .;
|
||||
KEEP(*(RTMSymTab))
|
||||
__rtmsymtab_end = .;
|
||||
} >flash AT>flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);/*0x80022c8*/
|
||||
PROVIDE (etext = .);/*0x80022c8*/
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash
|
||||
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800);
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . ); /*0X2000,0340*/
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram
|
||||
}
|
||||
@@ -0,0 +1,182 @@
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Run in FLASH */
|
||||
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
|
||||
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
|
||||
/* Run in RAM */
|
||||
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
|
||||
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash
|
||||
|
||||
.ilalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ilm_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.ialign :
|
||||
{
|
||||
PROVIDE( _ilm = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.PrgData ALIGN(0x08004000,4) : AT(ALIGN(0x08004000,4))
|
||||
{
|
||||
KEEP(*(.PrgData))
|
||||
}
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.sdata2 .sdata2. *)
|
||||
} >flash AT>flash
|
||||
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);/*0x80022c8*/
|
||||
PROVIDE (etext = .);/*0x80022c8*/
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _eilm = . );
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash
|
||||
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800);
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . ); /*0X2000,0340*/
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,24 @@
|
||||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
#include "riscv_encoding.h"
|
||||
#include "n22_func.h"
|
||||
__attribute__((weak)) uintptr_t handle_nmi() {
|
||||
write(1, "nmi\n", 5);
|
||||
_exit(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp) {
|
||||
if (mcause == 0xFFF) {
|
||||
handle_nmi();
|
||||
}
|
||||
write(1, "trap\n", 5);
|
||||
printf("In trap handler, the mcause is %d\n", mcause);
|
||||
printf("In trap handler, the mepc is 0x%x\n", read_csr(mepc));
|
||||
printf("In trap handler, the mtval is 0x%x\n", read_csr(mbadaddr));
|
||||
_exit(mcause);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
//See LICENSE for license details.
|
||||
#include <gd32vf103.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
#include "riscv_encoding.h"
|
||||
#include "n22_func.h"
|
||||
|
||||
void _init() {
|
||||
SystemInit();
|
||||
|
||||
//ECLIC init
|
||||
eclic_init(ECLIC_NUM_INTERRUPTS);
|
||||
eclic_mode_enable();
|
||||
set_csr(mstatus, MSTATUS_MIE);
|
||||
|
||||
//printf("After ECLIC mode enabled, the mtvec value is %x \n\n\r", read_csr(mtvec));
|
||||
|
||||
// // It must be NOTED:
|
||||
// // * In the RISC-V arch, if user mode and PMP supported, then by default if PMP is not configured
|
||||
// // with valid entries, then user mode cannot access any memory, and cannot execute any instructions.
|
||||
// // * So if switch to user-mode and still want to continue, then you must configure PMP first
|
||||
//pmp_open_all_space();
|
||||
//switch_m2u_mode();
|
||||
}
|
||||
|
||||
void _fini() {
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,17 @@
|
||||
/* See LICENSE of license details. */
|
||||
|
||||
#include <unistd.h>
|
||||
|
||||
#include "stub.h"
|
||||
|
||||
|
||||
void _exit(int code)
|
||||
{
|
||||
const char message[] = "\nProgram has exited with code:";
|
||||
|
||||
write(STDERR_FILENO, message, sizeof(message) - 1);
|
||||
// write_hex(STDERR_FILENO, code);
|
||||
// write(STDERR_FILENO, "\n", 1);
|
||||
|
||||
for (;;);
|
||||
}
|
||||
@@ -0,0 +1,8 @@
|
||||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
|
||||
int _close(int fd) {
|
||||
return _stub(EBADF);
|
||||
}
|
||||
@@ -0,0 +1,16 @@
|
||||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
#include "stub.h"
|
||||
|
||||
int _fstat(int fd, struct stat* st)
|
||||
{
|
||||
if (isatty(fd)) {
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
/* See LICENSE of license details. */
|
||||
|
||||
#include <unistd.h>
|
||||
|
||||
int _isatty(int fd) {
|
||||
if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
/* See LICENSE of license details. */
|
||||
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include "stub.h"
|
||||
|
||||
off_t _lseek(int fd, off_t ptr, int dir) {
|
||||
if (isatty(fd))
|
||||
return 0;
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "stub.h"
|
||||
|
||||
ssize_t _read(int fd, void* ptr, size_t len)
|
||||
{
|
||||
// The below code was copied from freedom-e-sdk, but seems it is definitely wrong, so just comment it out
|
||||
// Need to implement this function in the future, otherwise cannot use the C scanf function
|
||||
//uint8_t * current = (uint8_t *)ptr;
|
||||
//volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
|
||||
//volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
|
||||
|
||||
//ssize_t result = 0;
|
||||
|
||||
//if (isatty(fd)) {
|
||||
// for (current = (uint8_t *)ptr;
|
||||
// (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
|
||||
// current ++) {
|
||||
// *current = *uart_rx;
|
||||
// result++;
|
||||
// }
|
||||
// return result;
|
||||
//}
|
||||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
Loaded 100 of 241 files, more files were not shown because too many files have changed in this diff.
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