Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-02-08 11:54:50 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

add GD32H7xx library

Browse Source
This commit is contained in:
wirano
2024-07-24 16:31:36 +08:00
committed by Rbb666
parent 8762b2e02e
commit 36dd0b74c8
202 changed files with 103549 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

406
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Include/gd32h7xx.h Normal file
View File

@@ -0,0 +1,406 @@
/*!
\file gd32h7xx.h
\brief general definitions for GD32H7xx
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2024, GigaDevice Semiconductor Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef GD32H7XX_H
#define GD32H7XX_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (GD32H7XX)
#error "Please select the target GD32H7XX device used in your application (in gd32h7xx.h file)"
#endif /* undefine GD32H7XX tip */
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined (HXTAL_VALUE)
#define HXTAL_VALUE ((uint32_t)25000000)
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined (HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 64MHz RC oscillator (IRC64M) in Hz */
#if !defined (IRC64M_VALUE)
#define IRC64M_VALUE ((uint32_t)64000000)
#endif /* internal 64MHz RC oscillator value */
/* define startup timeout value of internal 64MHz RC oscillator (IRC64M) */
#if !defined (IRC64M_STARTUP_TIMEOUT)
#define IRC64M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 64MHz RC oscillator startup timeout */
/* define value of Low Power Internal 4Mhz RC oscillator (LPIRC4M) in Hz */
#if !defined (LPIRC4M_VALUE)
#define LPIRC4M_VALUE ((uint32_t)4000000)
#endif /* Low Power Internal 4Mhz RC oscillator value */
/* define startup timeout value of internal Low Power Internal 4Mhz RC oscillator (LPIRC4M) */
#if !defined (LPIRC4M_STARTUP_TIMEOUT)
#define LPIRC4M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* Low Power Internal 4Mhz RC oscillator startup timeout */
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
#if !defined (IRC48M_VALUE)
#define IRC48M_VALUE ((uint32_t)48000000)
#endif /* internal 48MHz RC oscillator value */
/* define startup timeout value of internal 48MHz RC oscillator (IRC48M) */
#if !defined (IRC48M_STARTUP_TIMEOUT)
#define IRC48M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 48MHz RC oscillator startup timeout */
/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
#if !defined (IRC32K_VALUE)
#define IRC32K_VALUE ((uint32_t)32000)
#endif /* internal 32KHz RC oscillator value */
/* define startup timeout value of internal 32KHz RC oscillator (IRC32K) */
#if !defined (IRC32K_STARTUP_TIMEOUT)
#define IRC32K_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 32KHz RC oscillator startup timeout */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined (LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* define startup timeout value of low speed crystal oscillator (LXTAL) */
#if !defined (LXTAL_STARTUP_TIMEOUT)
#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0FFFFFFF)
#endif /* low speed crystal oscillator startup timeout */
/* GD32H7xx firmware library version number V1.0 */
#define __GD32H7XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __GD32H7XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __GD32H7XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __GD32H7XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __GD32H7XX_STDPERIPH_VERSION ((__GD32H7XX_STDPERIPH_VERSION_MAIN << 24)\
|(__GD32H7XX_STDPERIPH_VERSION_SUB1 << 16)\
|(__GD32H7XX_STDPERIPH_VERSION_SUB2 << 8)\
|(__GD32H7XX_STDPERIPH_VERSION_RC))
/* configuration of the Cortex-M7 processor and core peripherals */
#define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
/* define interrupt number */
typedef enum IRQn {
/* Cortex-M7 processor exceptions numbers */
NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */
HardFault_IRQn = -13, /*!< hard-fault interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M7 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M7 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M7 sv call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M7 pend sv interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M7 system tick interrupt */
/* interruput numbers */
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
AVD_LVD_OVD_IRQn = 1, /*!< AVD/LVD/OVD through EXTI line detect interrupt */
TAMPER_STAMP_LXTAL_IRQn = 2, /*!< RTC tamper and timestamp interrupt/LXTAL clock stuck interrupt */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt */
FMC_IRQn = 4, /*!< FMC interrupt */
RCU_IRQn = 5, /*!< RCU interrupt */
EXTI0_IRQn = 6, /*!< EXTI line 0 */
EXTI1_IRQn = 7, /*!< EXTI line 1 */
EXTI2_IRQn = 8, /*!< EXTI line 2 */
EXTI3_IRQn = 9, /*!< EXTI line 3 */
EXTI4_IRQn = 10, /*!< EXTI line 4 */
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel 0 interrupt */
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel 1 interrupt */
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel 2 interrupt */
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel 3 interrupt */
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel 4 interrupt */
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel 5 interrupt */
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel 6 interrupt */
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 */
EXTI5_9_IRQn = 23, /*!< EXTI line 5 to 9 */
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger/commutation interrupt */
TIMER0_Channel_IRQn = 27, /*!< TIMER0 capture/compare interrupt */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 global and wakeup interrupt */
USART1_IRQn = 38, /*!< USART1 global and wakeup interrupt */
USART2_IRQn = 39, /*!< USART2 global and wakeup interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI line 10 to 15 */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */
TIMER7_BRK_IRQn = 43, /*!< TIMER7 Break global interrupt */
TIMER7_UP_IRQn = 44, /*!< TIMER7 Update global interrupt */
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 Trigger and Commutation global interrupt */
TIMER7_Channel_IRQn = 46, /*!< TIMER7 Capture Compare interrupt */
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel 7 interrupt */
EXMC_IRQn = 48, /*!< EXMC interrupt */
SDIO0_IRQn = 49, /*!< SDMMC0 interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
SPI2_IRQn = 51, /*!< SPI2 interrupt */
UART3_IRQn = 52, /*!< UART3 interrupt */
UART4_IRQn = 53, /*!< UART4 interrupt */
TIMER5_DAC_UDR_IRQn = 54, /*!< TIMER5 global interrupt and DAC1/DAC0 underrun */
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
ENET0_IRQn = 61, /*!< ENET 0 interrupt */
ENET0_WKUP_IRQn = 62, /*!< ENET 0 wakeup through EXTI line interrupt */
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel 5 interrupt */
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel 6 interrupt */
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel 7 interrupt */
USART5_IRQn = 71, /*!< UART5 global and wakeup interrupt */
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
USBHS0_EP1_OUT_IRQn = 74, /*!< USBHS0 endpoint 1 out interrupt */
USBHS0_EP1_IN_IRQn = 75, /*!< USBHS0 endpoint 1 in interrupt */
USBHS0_WKUP_IRQn = 76, /*!< USBHS0 wakeup through EXTI line interrupt */
USBHS0_IRQn = 77, /*!< USBHS0 interrupt */
DCI_IRQn = 78, /*!< DCI interrupt */
CAU_IRQn = 79, /*!< CAU interrupt */
HAU_TRNG_IRQn = 80, /*!< HAU and TRNG interrupt */
FPU_IRQn = 81, /*!< FPU interrupt */
UART6_IRQn = 82, /*!< UART6 interrupt */
UART7_IRQn = 83, /*!< UART7 interrupt */
SPI3_IRQn = 84, /*!< SPI3 interrupt */
SPI4_IRQn = 85, /*!< SPI4 interrupt */
SPI5_IRQn = 86, /*!< SPI5 interrupt */
SAI0_IRQn = 87, /*!< SAI0 interrupt */
TLI_IRQn = 88, /*!< TLI interrupt */
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
IPA_IRQn = 90, /*!< IPA interrupt */
SAI1_IRQn = 91, /*!< SAI1 interrupt */
OSPI0_IRQn = 92, /*!< OSPI0 global interrupt */
I2C3_EV_IRQn = 95, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 96, /*!< I2C3 error interrupt */
RSPDIF_IRQn = 97, /*!< RSPDIF global interrupt */
DMAMUX_OVR_IRQn = 102, /*!< DMAMUX overrun interrupt */
HPDF_INT0_IRQn = 110, /*!< HPDF filiter 0 interrupt */
HPDF_INT1_IRQn = 111, /*!< HPDF filiter 1 interrupt */
HPDF_INT2_IRQn = 112, /*!< HPDF filiter 2 interrupt */
HPDF_INT3_IRQn = 113, /*!< HPDF filiter 3 interrupt */
SAI2_IRQn = 114, /*!< SAI2 interrupt */
TIMER14_IRQn = 116, /*!< TIMER14 interrupt */
TIMER15_IRQn = 117, /*!< TIMER15 interrupt */
TIMER16_IRQn = 118, /*!< TIMER16 interrupt */
MDIO_IRQn = 120, /*!< MDIO interrupt */
MDMA_IRQn = 122, /*!< MDMA interrupt */
SDIO1_IRQn = 124, /*!< SDIO1 interrupt */
HWSEM_IRQn = 125, /*!< HWSEM interrupt */
ADC2_IRQn = 127, /*!< ADC2 interrupt */
CMP0_1_IRQn = 137, /*!< CMP0 and CMP1 interrupt */
CTC_IRQn = 144, /*!< CTC interrupt */
RAMECCMU_IRQn = 145, /*!< RAMECCMU interrupt */
OSPI1_IRQn = 150, /*!< OSPI1 interrupt */
RTDEC0_IRQn = 151, /*!< RTDEC0 interrupt */
RTDEC1_IRQn = 152, /*!< RTDEC1 interrupt */
FAC_IRQn = 153, /*!< FAC interrupt */
TMU_IRQn = 154, /*!< TMU interrupt */
TIMER22_IRQn = 161, /*!< TIMER22 interrupt */
TIMER23_IRQn = 162, /*!< TIMER23 interrupt */
TIMER30_IRQn = 163, /*!< TIMER30 interrupt */
TIMER31_IRQn = 164, /*!< TIMER31 interrupt */
TIMER40_IRQn = 165, /*!< TIMER40 interrupt */
TIMER41_IRQn = 166, /*!< TIMER41 interrupt */
TIMER42_IRQn = 167, /*!< TIMER42 interrupt */
TIMER43_IRQn = 168, /*!< TIMER43 interrupt */
TIMER44_IRQn = 169, /*!< TIMER44 interrupt */
TIMER50_IRQn = 170, /*!< TIMER50 interrupt */
TIMER51_IRQn = 171, /*!< TIMER51 interrupt */
USBHS1_EP1_OUT_IRQn = 172, /*!< USBHS1 endpoint 1 out interrupt */
USBHS1_EP1_IN_IRQn = 173, /*!< USBHS1 endpoint 1 in interrupt */
USBHS1_WKUP_IRQn = 174, /*!< USBHS1 wakeup through EXTI line interrupt */
USBHS1_IRQn = 175, /*!< USBHS1 interrupt */
ENET1_IRQn = 176, /*!< ENET1 interrupt */
ENET1_WKUP_IRQn = 177, /*!< ENET1 wakeup through EXTI line interrupt */
CAN0_WKUP_IRQn = 179, /*!< CAN 0 wakeup through EXTI line interrupt */
CAN0_Message_IRQn = 180, /*!< CAN 0 message buffer interrupt */
CAN0_Busoff_IRQn = 181, /*!< CAN 0 bus off / bus off done interrupt */
CAN0_Error_IRQn = 182, /*!< CAN 0 error interrupt */
CAN0_FastError_IRQn = 183, /*!< CAN 0 error in fast transmission interrupt */
CAN0_TEC_IRQn = 184, /*!< CAN 0 transmit warning interrupt */
CAN0_REC_IRQn = 185, /*!< CAN 0 receive warning interrupt */
CAN1_WKUP_IRQn = 186, /*!< CAN 1 wakeup through EXTI line interrupt */
CAN1_Message_IRQn = 187, /*!< CAN 1 message buffer interrupt */
CAN1_Busoff_IRQn = 188, /*!< CAN 1 bus off / bus off done interrupt */
CAN1_Error_IRQn = 189, /*!< CAN 1 error interrupt */
CAN1_FastError_IRQn = 190, /*!< CAN 1 error in fast transmission interrupt */
CAN1_TEC_IRQn = 191, /*!< CAN 1 transmit warning interrupt */
CAN1_REC_IRQn = 192, /*!< CAN 1 receive warning interrupt */
CAN2_WKUP_IRQn = 193, /*!< CAN 2 wakeup through EXTI line interrupt */
CAN2_Message_IRQn = 194, /*!< CAN 2 message buffer interrupt */
CAN2_Busoff_IRQn = 195, /*!< CAN 2 bus off / bus off done interrupt */
CAN2_Error_IRQn = 196, /*!< CAN 2 error interrupt */
CAN2_FastError_IRQn = 197, /*!< CAN 2 error in fast transmission interrupt */
CAN2_TEC_IRQn = 198, /*!< CAN 2 transmit warning interrupt */
CAN2_REC_IRQn = 199, /*!< CAN 2 receive warning interrupt */
EFUSE_IRQn = 200, /*!< EFUSE interrupt */
I2C0_WKUP_IRQn = 201, /*!< I2C 0 wakeup through EXTI line interrupt */
I2C1_WKUP_IRQn = 202, /*!< I2C 1 wakeup through EXTI line interrupt */
I2C2_WKUP_IRQn = 203, /*!< I2C 2 wakeup through EXTI line interrupt */
I2C3_WKUP_IRQn = 204, /*!< I2C 3 wakeup through EXTI line interrupt */
LPDTS_IRQn = 205, /*!< LPDTS interrupt */
LPDTS_WKUP_IRQn = 206, /*!< LPDTS wakeup through EXTI line interrupt */
TIMER0_DEC_IRQn = 207, /*!< TIMER0 DEC interrupt */
TIMER7_DEC_IRQn = 208, /*!< TIMER7 DEC interrupt */
TIMER1_DEC_IRQn = 209, /*!< TIMER1 DEC interrupt */
TIMER2_DEC_IRQn = 210, /*!< TIMER2 DEC interrupt */
TIMER3_DEC_IRQn = 211, /*!< TIMER3 DEC interrupt */
TIMER4_DEC_IRQn = 212, /*!< TIMER4 DEC interrupt */
TIMER22_DEC_IRQn = 213, /*!< TIMER22 DEC interrupt */
TIMER23_DEC_IRQn = 214, /*!< TIMER23 DEC interrupt */
TIMER30_DEC_IRQn = 215, /*!< TIMER30 DEC interrupt */
TIMER31_DEC_IRQn = 216, /*!< TIMER31 DEC interrupt */
} IRQn_Type;
/* includes */
#include "core_cm7.h"
#include "system_gd32h7xx.h"
#include <stdint.h>
/* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */
#define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr))
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U << (x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x24000000U) /*!< SRAM base address */
/* SRAM and peripheral base bit-band region */
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define APB3_BUS_BASE ((uint32_t)0x50000000U) /*!< apb3 base address */
#define APB4_BUS_BASE ((uint32_t)0x58000000U) /*!< apb4 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
#define AHB3_BUS_BASE ((uint32_t)0x51000000U) /*!< ahb3 base address */
#define AHB4_BUS_BASE ((uint32_t)0x58020000U) /*!< ahb4 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define RSPDIF_BASE (APB1_BUS_BASE + 0x00004000U) /*!< RSPDIF base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
#define CTC_BASE (APB1_BUS_BASE + 0x00008400U) /*!< CTC base address */
#define MDIO_BASE (APB1_BUS_BASE + 0x00009400U) /*!< MDIO base address */
/* advanced peripheral bus 2 memory map */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
#define SAI_BASE (APB2_BUS_BASE + 0x00005800U) /*!< SAI base address */
#define HPDF_BASE (APB2_BUS_BASE + 0x00007000U) /*!< HPDF base address */
#define TRIGSEL_BASE (APB2_BUS_BASE + 0x00008400U) /*!< TRIGSEL base address */
#define EDOUT_BASE (APB2_BUS_BASE + 0x00008800U) /*!< EDOUT base address */
#define CAN_BASE (APB2_BUS_BASE + 0x0000A000U) /*!< CAN base address */
/* advanced peripheral bus 3 memory map */
#define TLI_BASE (APB3_BUS_BASE + 0x00001000U) /*!< TLI base address */
#define WWDGT_BASE (APB3_BUS_BASE + 0x00003000U) /*!< WWDGT base address */
/* advanced peripheral bus 4 memory map */
#define EXTI_BASE (APB4_BUS_BASE + 0x00000000U) /*!< EXTI base address */
#define SYSCFG_BASE (APB4_BUS_BASE + 0x00000400U) /*!< SYSCFG base address */
#define CMP_BASE (APB4_BUS_BASE + 0x00003800U) /*!< CMP base address */
#define VREF_BASE (APB4_BUS_BASE + 0x00003C00U) /*!< VREF base address */
#define RTC_BASE (APB4_BUS_BASE + 0x00004000U) /*!< CMP base address */
#define FWDGT_BASE (APB4_BUS_BASE + 0x00004800U) /*!< FWDGT base address */
#define PMU_BASE (APB4_BUS_BASE + 0x00005800U) /*!< PMU base address */
#define LPDTS_BASE (APB4_BUS_BASE + 0x00006800U) /*!< LPDTS base address */
/* advanced high performance bus 1 memory map */
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
#define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMAMUX base address */
#define EFUSE_BASE (AHB1_BUS_BASE + 0x00002800U) /*!< EFUSE base address */
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
/* advanced high performance bus 2 memory map */
#define DCI_BASE (AHB2_BUS_BASE + 0x00020000U) /*!< DCI base address */
#define CAU_BASE (AHB2_BUS_BASE + 0x00021000U) /*!< CAU base address */
#define HAU_BASE (AHB2_BUS_BASE + 0x00021400U) /*!< HAU base address */
#define TRNG_BASE (AHB2_BUS_BASE + 0x00021800U) /*!< TRNG base address */
#define SDIO_BASE (AHB2_BUS_BASE + 0x00022400U) /*!< SDIO base address */
#define CPDM_BASE (AHB2_BUS_BASE + 0x00022800U) /*!< CPDM base address */
#define RAMECCMU_BASE (AHB2_BUS_BASE + 0x00023000U) /*!< RAMECCMU base address */
#define TMU_BASE (AHB2_BUS_BASE + 0x00024400U) /*!< TMU base address */
#define FAC_BASE (AHB2_BUS_BASE + 0x00024800U) /*!< FAC base address */
/* advanced high performance bus 3 memory map */
#define AXIM_BASE (AHB3_BUS_BASE + 0x00000000U) /*!< AXIM base address */
#define MDMA_BASE (AHB3_BUS_BASE + 0x01000000U) /*!< MDMA base address */
#define IPA_BASE (AHB3_BUS_BASE + 0x01001000U) /*!< IPA base address */
#define FMC_BASE (AHB3_BUS_BASE + 0x01002000U) /*!< FMC base address */
#define FLEXRAMC_BASE (AHB3_BUS_BASE + 0x01003000U) /*!< FLEXRAMC base address */
#define EXMC_BASE (AHB3_BUS_BASE + 0x01004000U) /*!< EXMC base address */
#define OSPI_BASE (AHB3_BUS_BASE + 0x01005000U) /*!< OSPI base address */
#define OSPM_BASE (AHB3_BUS_BASE + 0x0100B400U) /*!< OSPM base address */
#define RTDEC_BASE (AHB3_BUS_BASE + 0x0100B800U) /*!< RTDEC base address */
/* advanced high performance bus 4 memory map */
#define GPIO_BASE (AHB4_BUS_BASE + 0x00000000U) /*!< GPIO base address */
#define RCU_BASE (AHB4_BUS_BASE + 0x00004400U) /*!< RCU base address */
#define CRC_BASE (AHB4_BUS_BASE + 0x00004C00U) /*!< CRC base address */
#define HWSEM_BASE (AHB4_BUS_BASE + 0x00006400U) /*!< HWSEM base address */
/* option byte and debug memory map */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0xE00E1000U) /*!< DBG base address */
/* define marco USE_STDPERIPH_DRIVER */
#if !defined USE_STDPERIPH_DRIVER
#define USE_STDPERIPH_DRIVER
#endif
#ifdef USE_STDPERIPH_DRIVER
#include "gd32h7xx_libopt.h"
#endif /* USE_STDPERIPH_DRIVER */
#ifdef __cplusplus
}
#endif
#endif /* GD32H7XX_H */

50
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Include/system_gd32h7xx.h Normal file
View File

@@ -0,0 +1,50 @@
/*!
\file system_gd32h7xx.h
\brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File for
gd32h7xx Device Series
*/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2024, GigaDevice Semiconductor Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32H7XX_H
#define SYSTEM_GD32H7XX_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32H7XX_H */

729
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/ARM/startup_gd32h7xx.s Normal file
View File

File diff suppressed because it is too large Load Diff

517
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/GCC/startup_gd32h7xx.s Normal file
View File

File diff suppressed because it is too large Load Diff

1158
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/IAR/startup_gd32h7xx.s Normal file
View File

File diff suppressed because it is too large Load Diff

716
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/system_gd32h7xx.c Normal file
View File

File diff suppressed because it is too large Load Diff

201
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/LICENSE.TXT Normal file
View File

@@ -0,0 +1,201 @@
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition,
"control" means (i) the power, direct or indirect, to cause the
direction or management of such entity, whether by contract or
otherwise, or (ii) ownership of fifty percent (50%) or more of the
outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity
exercising permissions granted by this License.
"Source" form shall mean the preferred form for making modifications,
including but not limited to software source code, documentation
source, and configuration files.
"Object" form shall mean any form resulting from mechanical
transformation or translation of a Source form, including but
not limited to compiled object code, generated documentation,
and conversions to other media types.
"Work" shall mean the work of authorship, whether in Source or
Object form, made available under the License, as indicated by a
copyright notice that is included in or attached to the work
(an example is provided in the Appendix below).
"Derivative Works" shall mean any work, whether in Source or Object
form, that is based on (or derived from) the Work and for which the
editorial revisions, annotations, elaborations, or other modifications
represent, as a whole, an original work of authorship. For the purposes
of this License, Derivative Works shall not include works that remain
separable from, or merely link (or bind by name) to the interfaces of,
the Work and Derivative Works thereof.
"Contribution" shall mean any work of authorship, including
the original version of the Work and any modifications or additions
to that Work or Derivative Works thereof, that is intentionally
submitted to Licensor for inclusion in the Work by the copyright owner
or by an individual or Legal Entity authorized to submit on behalf of
the copyright owner. For the purposes of this definition, "submitted"
means any form of electronic, verbal, or written communication sent
to the Licensor or its representatives, including but not limited to
communication on electronic mailing lists, source code control systems,
and issue tracking systems that are managed by, or on behalf of, the
Licensor for the purpose of discussing and improving the Work, but
excluding communication that is conspicuously marked or otherwise
designated in writing by the copyright owner as "Not a Contribution."
"Contributor" shall mean Licensor and any individual or Legal Entity
on behalf of whom a Contribution has been received by Licensor and
subsequently incorporated within the Work.
2. Grant of Copyright License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
copyright license to reproduce, prepare Derivative Works of,
publicly display, publicly perform, sublicense, and distribute the
Work and such Derivative Works in Source or Object form.
3. Grant of Patent License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
(except as stated in this section) patent license to make, have made,
use, offer to sell, sell, import, and otherwise transfer the Work,
where such license applies only to those patent claims licensable
by such Contributor that are necessarily infringed by their
Contribution(s) alone or by combination of their Contribution(s)
with the Work to which such Contribution(s) was submitted. If You
institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the Work
or a Contribution incorporated within the Work constitutes direct
or contributory patent infringement, then any patent licenses
granted to You under this License for that Work shall terminate
as of the date such litigation is filed.
4. Redistribution. You may reproduce and distribute copies of the
Work or Derivative Works thereof in any medium, with or without
modifications, and in Source or Object form, provided that You
meet the following conditions:
(a) You must give any other recipients of the Work or
Derivative Works a copy of this License; and
(b) You must cause any modified files to carry prominent notices
stating that You changed the files; and
(c) You must retain, in the Source form of any Derivative Works
that You distribute, all copyright, patent, trademark, and
attribution notices from the Source form of the Work,
excluding those notices that do not pertain to any part of
the Derivative Works; and
(d) If the Work includes a "NOTICE" text file as part of its
distribution, then any Derivative Works that You distribute must
include a readable copy of the attribution notices contained
within such NOTICE file, excluding those notices that do not
pertain to any part of the Derivative Works, in at least one
of the following places: within a NOTICE text file distributed
as part of the Derivative Works; within the Source form or
documentation, if provided along with the Derivative Works; or,
within a display generated by the Derivative Works, if and
wherever such third-party notices normally appear. The contents
of the NOTICE file are for informational purposes only and
do not modify the License. You may add Your own attribution
notices within Derivative Works that You distribute, alongside
or as an addendum to the NOTICE text from the Work, provided
that such additional attribution notices cannot be construed
as modifying the License.
You may add Your own copyright statement to Your modifications and
may provide additional or different license terms and conditions
for use, reproduction, or distribution of Your modifications, or
for any such Derivative Works as a whole, provided Your use,
reproduction, and distribution of the Work otherwise complies with
the conditions stated in this License.
5. Submission of Contributions. Unless You explicitly state otherwise,
any Contribution intentionally submitted for inclusion in the Work
by You to the Licensor shall be under the terms and conditions of
this License, without any additional terms or conditions.
Notwithstanding the above, nothing herein shall supersede or modify
the terms of any separate license agreement you may have executed
with Licensor regarding such Contributions.
6. Trademarks. This License does not grant permission to use the trade
names, trademarks, service marks, or product names of the Licensor,
except as required for reasonable and customary use in describing the
origin of the Work and reproducing the content of the NOTICE file.
7. Disclaimer of Warranty. Unless required by applicable law or
agreed to in writing, Licensor provides the Work (and each
Contributor provides its Contributions) on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied, including, without limitation, any warranties or conditions
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
PARTICULAR PURPOSE. You are solely responsible for determining the
appropriateness of using or redistributing the Work and assume any
risks associated with Your exercise of permissions under this License.
8. Limitation of Liability. In no event and under no legal theory,
whether in tort (including negligence), contract, or otherwise,
unless required by applicable law (such as deliberate and grossly
negligent acts) or agreed to in writing, shall any Contributor be
liable to You for damages, including any direct, indirect, special,
incidental, or consequential damages of any character arising as a
result of this License or out of the use or inability to use the
Work (including but not limited to damages for loss of goodwill,
work stoppage, computer failure or malfunction, or any and all
other commercial damages or losses), even if such Contributor
has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability. While redistributing
the Work or Derivative Works thereof, You may choose to offer,
and charge a fee for, acceptance of support, warranty, indemnity,
or other liability obligations and/or rights consistent with this
License. However, in accepting such obligations, You may act only
on Your own behalf and on Your sole responsibility, not on behalf
of any other Contributor, and only if You agree to indemnify,
defend, and hold each Contributor harmless for any liability
incurred by, or claims asserted against, such Contributor by reason
of your accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
APPENDIX: How to apply the Apache License to your work.
To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "{}"
replaced with your own identifying information. (Don't include
the brackets!) The text should be enclosed in the appropriate
comment syntax for the file format. We also recommend that a
file or class name and description of purpose be included on the
same "printed page" as the copyright notice for easier
identification within third-party archives.
Copyright {yyyy} {name of copyright owner}
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

441
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cachel1_armv7.h Normal file
View File

@@ -0,0 +1,441 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.3
* @date 17. March 2023
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
struct {
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
} locals
#if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
__ALIGNED(__SCB_DCACHE_LINE_SIZE)
#endif
;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
#if !defined(__OPTIMIZE__)
/*
* For the endless loop issue with no optimization builds.
* More details, see https://github.com/ARM-software/CMSIS_5/issues/620
*
* The issue only happens when local variables are in stack. If
* local variables are saved in general purpose register, then the function
* is OK.
*
* When local variables are in stack, after disabling the cache, flush the
* local variables cache line for data consistency.
*/
/* Clean and invalidate the local variable cache. */
#if defined(__ICCARM__)
/* As we can't align the stack to the cache line size, invalidate each of the variables */
SCB->DCCIMVAC = (uint32_t)&locals.sets;
SCB->DCCIMVAC = (uint32_t)&locals.ways;
SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
#else
SCB->DCCIMVAC = (uint32_t)&locals;
#endif
__DSB();
__ISB();
#endif
locals.ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
do {
locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
do {
SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (locals.ways-- != 0U);
} while(locals.sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */

894
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armcc.h Normal file
View File

File diff suppressed because it is too large Load Diff

1510
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang.h Normal file
View File

File diff suppressed because it is too large Load Diff

1934
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang_ltm.h Normal file
View File

File diff suppressed because it is too large Load Diff

303
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_compiler.h Normal file
View File

@@ -0,0 +1,303 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.3.0
* @date 04. April 2023
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* TI Arm Clang Compiler (tiarmclang)
*/
#elif defined (__ti__)
#include "cmsis_tiarmclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler (armcl)
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

2217
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_gcc.h Normal file
View File

File diff suppressed because it is too large Load Diff

39
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_version.h Normal file
View File

@@ -0,0 +1,39 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.5
* @date 02. February 2022
******************************************************************************/
/*
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

2407
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/core_cm7.h Normal file
View File

File diff suppressed because it is too large Load Diff

275
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/mpu_armv7.h Normal file
View File

@@ -0,0 +1,275 @@
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.2
* @date 25. May 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

623
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_adc.h Normal file
View File

File diff suppressed because it is too large Load Diff

226
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_axiim.h Normal file
View File

@@ -0,0 +1,226 @@
/*!
\file gd32h7xx_axiim.h
\brief definitions for AXIIM(AXI interconnect matrix)
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_AXIIM_H
#define GD32H7XX_AXIIM_H
#include "gd32h7xx.h"
/* AXI interconnect matrix definitions */
#define AXIIM_BASE ((uint32_t)0x51000000U) /*!< AXI interconnect matrix base address */
#define AXIIM AXIIM_BASE /*!< AXI interconnect matrix definition */
/* registers definitions */
#define AXI_PERIPH_ID4 REG32(AXIIM + 0x00001FD0U) /*!< AXI peripheral ID4 register */
#define AXI_PERIPH_ID0 REG32(AXIIM + 0x00001FE0U) /*!< AXI peripheral ID0 register */
#define AXI_PERIPH_ID1 REG32(AXIIM + 0x00001FE4U) /*!< AXI peripheral ID1 register */
#define AXI_PERIPH_ID2 REG32(AXIIM + 0x00001FE8U) /*!< AXI peripheral ID2 register */
#define AXI_PERIPH_ID3 REG32(AXIIM + 0x00001FECU) /*!< AXI peripheral ID3 register */
#define AXI_COMP_ID0 REG32(AXIIM + 0x00001FF0U) /*!< AXI componet ID0 register */
#define AXI_COMP_ID1 REG32(AXIIM + 0x00001FF4U) /*!< AXI componet ID1 register */
#define AXI_COMP_ID2 REG32(AXIIM + 0x00001FF8U) /*!< AXI componet ID2 register */
#define AXI_COMP_ID3 REG32(AXIIM + 0x00001FFCU) /*!< AXI componet ID3 register */
#define AXI_MPXBM_ISS_CTL(mportx) REG32(AXIIM + 0x00002008U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix issuing functionality control register */
#define AXI_MP0BM_ISS_CTL REG32(AXIIM + 0x00002008U) /*!< AXI master port 0 bus matrix issuing functionality control register */
#define AXI_MP1BM_ISS_CTL REG32(AXIIM + 0x00003008U) /*!< AXI master port 1 bus matrix issuing functionality control register */
#define AXI_MP2BM_ISS_CTL REG32(AXIIM + 0x00004008U) /*!< AXI master port 2 bus matrix issuing functionality control register */
#define AXI_MP3BM_ISS_CTL REG32(AXIIM + 0x00005008U) /*!< AXI master port 3 bus matrix issuing functionality control register */
#define AXI_MP4BM_ISS_CTL REG32(AXIIM + 0x00006008U) /*!< AXI master port 4 bus matrix issuing functionality control register */
#define AXI_MP5BM_ISS_CTL REG32(AXIIM + 0x00007008U) /*!< AXI master port 5 bus matrix issuing functionality control register */
#define AXI_MP6BM_ISS_CTL REG32(AXIIM + 0x00008008U) /*!< AXI master port 6 bus matrix issuing functionality control register */
#define AXI_MP7BM_ISS_CTL REG32(AXIIM + 0x00009008U) /*!< AXI master port 7 bus matrix issuing functionality control register */
#define AXI_MPXBM_CTL(mportx) REG32(AXIIM + 0x00002024U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix functionality control register */
#define AXI_MP0BM_CTL REG32(AXIIM + 0x00002024U) /*!< AXI master port 0 bus matrix functionality control register */
#define AXI_MP1BM_CTL REG32(AXIIM + 0x00003024U) /*!< AXI master port 1 bus matrix functionality control register */
#define AXI_MP6BM_CTL REG32(AXIIM + 0x00008024U) /*!< AXI master port 6 bus matrix functionality control register */
#define AXI_MP7BM_CTL REG32(AXIIM + 0x00009024U) /*!< AXI master port 7 bus matrix functionality control register */
#define AXI_MPX_LB_CTL(mportx) REG32(AXIIM + 0x0000202CU + 0x00001000U * (mportx)) /*!< AXI master port x long burst functionality control register */
#define AXI_MP0_LB_CTL REG32(AXIIM + 0x0000202CU) /*!< AXI master port 0 long burst functionality control register */
#define AXI_MP1_LB_CTL REG32(AXIIM + 0x0000302CU) /*!< AXI master port 1 long burst functionality control register */
#define AXI_MPX_ISS_CTL(mportx) REG32(AXIIM + 0x00002108U + 0x00001000U * (mportx)) /*!< AXI master port x issuing functionality control register */
#define AXI_MP0_ISS_CTL REG32(AXIIM + 0x00002108U) /*!< AXI master port 0 issuing functionality control register */
#define AXI_MP1_ISS_CTL REG32(AXIIM + 0x00003108U) /*!< AXI master port 1 issuing functionality control register */
#define AXI_MP6_ISS_CTL REG32(AXIIM + 0x00008108U) /*!< AXI master port 6 issuing functionality control register */
#define AXI_MP7_ISS_CTL REG32(AXIIM + 0x00009108U) /*!< AXI master port 7 issuing functionality control register */
#define AXI_SPX_CTL(sportx) REG32(AXIIM + 0x00042024U + 0x00001000U * (sportx)) /*!< AXI slave port x functionality control register */
#define AXI_SP0_CTL REG32(AXIIM + 0x00042024U) /*!< AXI slave port 0 functionality control register */
#define AXI_SP2_CTL REG32(AXIIM + 0x00044024U) /*!< AXI slave port 2 functionality control register */
#define AXI_SPX_AHBISS_CTL(sportx) REG32(AXIIM + 0x00042028U + 0x00001000U * (sportx)) /*!< AXI slave port x AHB issuing functionality control register */
#define AXI_SP0_AHBISS_CTL REG32(AXIIM + 0x00042028U) /*!< AXI slave port 0 AHB issuing functionality control register */
#define AXI_SP2_AHBISS_CTL REG32(AXIIM + 0x00044028U) /*!< AXI slave port 2 AHB issuing functionality control register */
/* AXI slave port x = 0 to 5 */
#define AXI_SPX_RDQOS_CTL(sportx) REG32(AXIIM + 0x00042100U + 0x00001000U * (sportx)) /*!< AXI slave port x read QOS control register */
#define AXI_SPX_WRQOS_CTL(sportx) REG32(AXIIM + 0x00042104U + 0x00001000U * (sportx)) /*!< AXI slave port x write QOS control register */
#define AXI_SPX_ISS_CTL(sportx) REG32(AXIIM + 0x00042108U + 0x00001000U * (sportx)) /*!< AXI slave port x issuing functionality control register */
#define AXI_PERIPH_ID4_JEP106CCODE BITS(0,3) /*!< JEP106 continuation code */
#define AXI_PERIPH_ID4_4KBCNT BITS(4,7) /*!< register file size */
#define AXI_PERIPH_ID0_PARTNUM BITS(0,7) /*!< part number bit[7:0] */
#define AXI_PERIPH_ID1_PARTNUM BITS(0,3) /*!< part number bit[11:8] */
#define AXI_PERIPH_ID1_JEP106ID BITS(4,7) /*!< JEP106 identity[3:0] */
#define AXI_PERIPH_ID2_JEP106ID BITS(0,2) /*!< JEP106 identity[6:4] */
#define AXI_PERIPH_ID2_JEP106CF BIT(3) /*!< JEP106 code flag */
#define AXI_PERIPH_ID2_PARTREV BITS(4,7) /*!< part revision */
#define AXI_PERIPH_ID3_CUSTMOD BITS(0,3) /*!< customer modification[3:0] */
#define AXI_PERIPH_ID3_CUSTREV BITS(4,7) /*!< customer version */
#define AXI_COMP_ID0_PREAMB BITS(0,7) /*!< preamble bits[7:0] */
#define AXI_COMP_ID1_PREAMB BITS(0,3) /*!< preamble bits[11:8] */
#define AXI_COMP_ID1_CLASS BITS(4,7) /*!< component class */
#define AXI_COMP_ID2_PREAMB BITS(0,7) /*!< preamble bits[19:12] */
#define AXI_COMP_ID3_PREAMB BITS(0,7) /*!< preamble bits[27:20] */
#define AXI_MPXBM_ISS_CTL_RD_ISSOV BIT(0) /*!< override target read issuing function */
#define AXI_MPXBM_ISS_CTL_WR_ISSOV BIT(1) /*!< override target write issuing function */
#define AXI_MPXBM_CTL_BPDIS BIT(0) /*!< beats packing function disable configure */
#define AXI_MPX_LB_CTL_LBEN BIT(0) /*!< control long burst function */
#define AXI_MPX_ISS_CTL_RD_ISSOV BIT(0) /*!< override AMIB read issuing function */
#define AXI_MPX_ISS_CTL_WR_ISSOV BIT(1) /*!< override AMIB write issuing function */
#define AXI_SPX_CTL_TRANSALT BIT(0) /*!< slave port transaction alteration configure bit */
#define AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV BIT(0) /*!< converts AHB-Lite write transaction to single beat AXI transaction */
#define AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV BIT(1) /*!< converts AHB-Lite read transaction to single beat AXI transaction */
#define AXI_SPX_RDQOS_CTL_RDQOS BITS(0,3) /*!< slave port read channel QoS configure bits */
#define AXI_SPX_WRQOS_CTL_WRQOS BITS(0,3) /*!< slave port write channel QoS configure bits */
#define AXI_SPX_ISS_CTL_RD_ISSOV BIT(0) /*!< slave port override ASIB read issuing control bit */
#define AXI_SPX_ISS_CTL_WR_ISSOV BIT(1) /*!< slave port override ASIB write issuing control bit */
/* AXI master port select */
typedef enum
{
MASTER_PORT0 = 0U, /*!< AXI master port 0 */
MASTER_PORT1, /*!< AXI master port 1 */
MASTER_PORT2, /*!< AXI master port 2 */
MASTER_PORT3, /*!< AXI master port 3 */
MASTER_PORT4, /*!< AXI master port 4 */
MASTER_PORT5, /*!< AXI master port 5 */
MASTER_PORT6, /*!< AXI master port 6 */
MASTER_PORT7 /*!< AXI master port 7 */
} master_port_enum;
/* AXI slave port select */
typedef enum
{
SLAVE_PORT0 = 0U, /*!< AXI slave port 0 */
SLAVE_PORT1, /*!< AXI slave port 1 */
SLAVE_PORT2, /*!< AXI slave port 2 */
SLAVE_PORT3, /*!< AXI slave port 3 */
SLAVE_PORT4, /*!< AXI slave port 4 */
SLAVE_PORT5 /*!< AXI slave port 5 */
} slave_port_enum;
/* AXI master port x bus mutrix read issuing capability is set to 1, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_READ_ISSOV_ENABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) |= AXI_MPXBM_ISS_CTL_RD_ISSOV}
/* AXI master port x bus mutrix read issuing capability is normal, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_READ_ISSOV_DISABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) &= ~AXI_MPXBM_ISS_CTL_RD_ISSOV}
/* AXI master port x bus mutrix write issuing capability is set to 1, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_WRITE_ISSOV_ENABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) |= AXI_MPXBM_ISS_CTL_WR_ISSOV}
/* AXI master port x bus mutrix write issuing capability is normal, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_WRITE_ISSOV_DISABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) &= ~AXI_MPXBM_ISS_CTL_WR_ISSOV}
/* enable AXI master port x beats packing function, mportx: MASTER_PORTx (x=0,1,6,7) */
#define __AXI_MPXBM_BEATS_PACKING_ENABLE(mportx) {AXI_MPXBM_CTL(mportx) &= ~AXI_MPXBM_CTL_BPDIS}
/* disable AXI master port x beats packing function, mportx: MASTER_PORTx (x=0,1,6,7) */
#define __AXI_MPXBM_BEATS_PACKING_DISABLE(mportx) {AXI_MPXBM_CTL(mportx) |= AXI_MPXBM_CTL_BPDIS}
/* enable AXI master port long burst function, mportx: MASTER_PORTx (x=0,1) */
#define __AXI_MPX_LONG_BURST_ENABLE(mportx) {AXI_MPX_LB_CTL(mportx) |= AXI_MPX_LB_CTL_LBEN}
/* disable AXI master port x long burst function, mportx: MASTER_PORTx (x=0,1) */
#define __AXI_MPX_LONG_BURST_DISABLE(mportx) {AXI_MPX_LB_CTL(mportx) &= ~AXI_MPX_LB_CTL_LBEN}
/* force AMIB read issuing capability to 1, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_READ_ISSOV_ENABLE(mportx) {AXI_MPX_ISS_CTL(mportx) |= AXI_MPX_ISS_CTL_RD_ISSOV}
/* AMIB read issuing capability is normal, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_READ_ISSOV_DISABLE(mportx) {AXI_MPX_ISS_CTL(mportx) &= ~AXI_MPX_ISS_CTL_RD_ISSOV}
/* force AMIB write issuing capability to 1, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_WRITE_ISSOV_ENABLE(mportx) {AXI_MPX_ISS_CTL(mportx) |= AXI_MPX_ISS_CTL_WR_ISSOV}
/* AMIB write issuing capability is normal, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_WRITE_ISSOV_DISABLE(mportx) {AXI_MPX_ISS_CTL(mportx) &= ~AXI_MPX_ISS_CTL_WR_ISSOV}
/* enable AXI slave port transaction alteration function, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_TRANSACTION_ALTER_ENABLE(sportx) {AXI_SPX_CTL(sportx) |= AXI_SPX_CTL_TRANSALT}
/* AXI slave port transaction alteration function in normal operation, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_TRANSACTION_ALTER_DISABLE(sportx) {AXI_SPX_CTL(sportx) &= ~AXI_SPX_CTL_TRANSALT}
/* enable convert AHB-Lite write transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_WR_TO_SINGLE_BEAT_TRANS_ENABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) |= AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV}
/* disable convert AHB-Lite write transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_WR_TO_SINGLE_BEAT_TRANS_DISABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) &= ~AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV}
/* enable convert AHB-Lite read transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_RD_TO_SINGLE_BEAT_TRANS_ENABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) |= AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV}
/* disable convert AHB-Lite read transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_RD_TO_SINGLE_BEAT_TRANS_DISABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) &= ~AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV}
/* configure slave port read channel QoS, sportx: SLAVE_PORTx (x=0..5), priority: 0x0~0xF */
#define __AXI_SPX_READ_QOS_SET(sportx, priority) {AXI_SPX_RDQOS_CTL(sportx) |= ( (priority) & AXI_SPX_RDQOS_CTL_RDQOS)}
/* configure slave port write channel QoS, sportx: SLAVE_PORTx (x=0..5), priority: 0x0~0xF */
#define __AXI_SPX_WRITE_QOS_SET(sportx, priority) {AXI_SPX_WRQOS_CTL(sportx) |= ( (priority) & AXI_SPX_WRQOS_CTL_WRQOS)}
/* force ASIB read issuing capability to 1, sportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_READ_ISSOV_ENABLE(sportx) {AXI_SPX_ISS_CTL(sportx) |= AXI_SPX_ISS_CTL_RD_ISSOV}
/* ASIB read issuing capability in normal operation, mportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_READ_ISSOV_DISABLE(sportx) {AXI_SPX_ISS_CTL(sportx) &= ~AXI_SPX_ISS_CTL_RD_ISSOV}
/* force ASIB write issuing capability to 1, sportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_WRITE_ISSOV_ENABLE(sportx) {AXI_SPX_ISS_CTL(sportx) |= AXI_SPX_ISS_CTL_WD_ISSOV}
/* ASIB write issuing capability in normal operation, mportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_WRITE_ISSOV_DISABLE(sportx) {AXI_SPX_ISS_CTL(sportx) &= ~AXI_SPX_ISS_CTL_WD_ISSOV}
#endif /* GD32H7XX_AXIIM_H */

1278
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_can.h Normal file
View File

File diff suppressed because it is too large Load Diff

322
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cau.h Normal file
View File

@@ -0,0 +1,322 @@
/*!
\file gd32h7xx_cau.h
\brief definitions for the CAU
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_CAU_H
#define GD32H7XX_CAU_H
#include "gd32h7xx.h"
/* CAU definitions */
#define CAU CAU_BASE /*!< CAU base address */
/* registers definitions */
#define CAU_CTL REG32(CAU + 0x00000000U) /*!< control register */
#define CAU_STAT0 REG32(CAU + 0x00000004U) /*!< status register 0 */
#define CAU_DI REG32(CAU + 0x00000008U) /*!< data input register */
#define CAU_DO REG32(CAU + 0x0000000CU) /*!< data output register */
#define CAU_DMAEN REG32(CAU + 0x00000010U) /*!< DMA enable register */
#define CAU_INTEN REG32(CAU + 0x00000014U) /*!< interrupt enable register */
#define CAU_STAT1 REG32(CAU + 0x00000018U) /*!< status register 1 */
#define CAU_INTF REG32(CAU + 0x0000001CU) /*!< interrupt flag register */
#define CAU_KEY0H REG32(CAU + 0x00000020U) /*!< key 0 high register */
#define CAU_KEY0L REG32(CAU + 0x00000024U) /*!< key 0 low register */
#define CAU_KEY1H REG32(CAU + 0x00000028U) /*!< key 1 high register */
#define CAU_KEY1L REG32(CAU + 0x0000002CU) /*!< key 1 low register */
#define CAU_KEY2H REG32(CAU + 0x00000030U) /*!< key 2 high register */
#define CAU_KEY2L REG32(CAU + 0x00000034U) /*!< key 2 low register */
#define CAU_KEY3H REG32(CAU + 0x00000038U) /*!< key 3 high register */
#define CAU_KEY3L REG32(CAU + 0x0000003CU) /*!< key 3 low register */
#define CAU_IV0H REG32(CAU + 0x00000040U) /*!< initial vector 0 high register */
#define CAU_IV0L REG32(CAU + 0x00000044U) /*!< initial vector 0 low register */
#define CAU_IV1H REG32(CAU + 0x00000048U) /*!< initial vector 1 high register */
#define CAU_IV1L REG32(CAU + 0x0000004CU) /*!< initial vector 1 low register */
#define CAU_GCMCCMCTXSx(x) REG32(CAU + 0x00000050U + (uint32_t)(4U * (x))) /*!< GCM or CCM mode context switch register, x = 0...7 */
#define CAU_GCMCTXSx(x) REG32(CAU + 0x00000070U + (uint32_t)(4U * (x))) /*!< GCM mode context switch register, x = 0...7 */
/* bits definitions */
/* CAU_CTL */
#define CAU_CTL_KEY_SEL BIT(0) /*!< key select */
#define CAU_CTL_CAUDIR BIT(2) /*!< algorithm direction */
#define CAU_CTL_ALGM (BITS(3,5) | BIT(19)) /*!< cryptographic algorithm mode */
#define CAU_CTL_DATAM BITS(6,7) /*!< data swapping selection */
#define CAU_CTL_KEYM BITS(8,9) /*!< key length selection when aes mode */
#define CAU_CTL_FFLUSH BIT(14) /*!< FIFO flush */
#define CAU_CTL_CAUEN BIT(15) /*!< cryptographic module enable */
#define CAU_CTL_GCM_CCMPH BITS(16,17) /*!< GCM CCM phase */
#define CAU_CTL_NBPILB BITS(20,23) /*!< number of bytes padding in last block */
/* CAU_STAT0 */
#define CAU_STAT0_IEM BIT(0) /*!< IN FIFO empty flag */
#define CAU_STAT0_INF BIT(1) /*!< IN FIFO not full flag */
#define CAU_STAT0_ONE BIT(2) /*!< OUT FIFO not empty flag */
#define CAU_STAT0_OFU BIT(3) /*!< OUT FIFO full flag */
#define CAU_STAT0_BUSY BIT(4) /*!< busy flag */
/* CAU_DI */
#define CAU_DI_DI BITS(0,31) /*!< data input */
/* CAU_DO */
#define CAU_DO_DO BITS(0,31) /*!< data output */
/* CAU_DMAEN */
#define CAU_DMAEN_DMAIEN BIT(0) /*!< IN FIFO DMA enable */
#define CAU_DMAEN_DMAOEN BIT(1) /*!< OUT FIFO DMA enable */
/* CAU_INTEN */
#define CAU_INTEN_IINTEN BIT(0) /*!< IN FIFO interrupt enable */
#define CAU_INTEN_OINTEN BIT(1) /*!< OUT FIFO interrupt enable */
/* CAU_STAT1 */
#define CAU_STAT1_ISTA BIT(0) /*!< flag set when there is less than 4 words in IN FIFO */
#define CAU_STAT1_OSTA BIT(1) /*!< flag set when there is one or more word in OUT FIFO */
/* CAU_INTF */
#define CAU_INTF_IINTF BIT(0) /*!< IN FIFO interrupt flag */
#define CAU_INTF_OINTF BIT(1) /*!< OUT FIFO interrupt flag */
/* CAU_KEYxH x=0..3 */
#define CAU_KEYXH_KEYXH BITS(0,31) /*!< the key for des, tdes, aes */
/* CAU_KEYxL x=0..3 */
#define CAU_KEYXL_KEYXL BITS(0,31) /*!< the key for des, tdes, aes */
/* CAU_IVxH x=0..1 */
#define CAU_IVXH_IVXH BITS(0,31) /*!< the initialization vector for des, tdes, aes */
/* CAU_IVxL x=0..1 */
#define CAU_IVXL_IVXL BITS(0,31) /*!< the initialization vector for des, tdes, aes */
/* constants definitions */
/* structure for keys initialization of the cau */
typedef struct {
uint32_t key_0_high; /*!< key 0 high */
uint32_t key_0_low; /*!< key 0 low */
uint32_t key_1_high; /*!< key 1 high */
uint32_t key_1_low; /*!< key 1 low */
uint32_t key_2_high; /*!< key 2 high */
uint32_t key_2_low; /*!< key 2 low */
uint32_t key_3_high; /*!< key 3 high */
uint32_t key_3_low; /*!< key 3 low */
} cau_key_parameter_struct;
/* structure for vectors initialization of the cau */
typedef struct {
uint32_t iv_0_high; /*!< init vector 0 high */
uint32_t iv_0_low; /*!< init vector 0 low */
uint32_t iv_1_high; /*!< init vector 1 high */
uint32_t iv_1_low; /*!< init vector 1 low */
} cau_iv_parameter_struct;
/* structure for cau context swapping */
typedef struct {
uint32_t ctl_config; /*!< current configuration */
uint32_t iv_0_high; /*!< init vector 0 high */
uint32_t iv_0_low; /*!< init vector 0 low */
uint32_t iv_1_high; /*!< init vector 1 high */
uint32_t iv_1_low; /*!< init vector 1 low */
uint32_t key_0_high; /*!< key 0 high */
uint32_t key_0_low; /*!< key 0 low */
uint32_t key_1_high; /*!< key 1 high */
uint32_t key_1_low; /*!< key 1 low */
uint32_t key_2_high; /*!< key 2 high */
uint32_t key_2_low; /*!< key 2 low */
uint32_t key_3_high; /*!< key 3 high */
uint32_t key_3_low; /*!< key 3 low */
uint32_t gcmccmctxs[8]; /*!< GCM or CCM mode context switch */
uint32_t gcmctxs[8]; /*!< GCM mode context switch */
} cau_context_parameter_struct;
/* structure for encrypt and decrypt parameters */
typedef struct {
uint32_t alg_dir; /*!< algorithm directory */
uint8_t *key; /*!< key */
uint32_t key_size; /*!< key size in bytes */
uint8_t *iv; /*!< initialization vector */
uint32_t iv_size; /*!< iv size in bytes */
uint8_t *input; /*!< input data */
uint32_t in_length; /*!< input data length in bytes */
uint8_t *aad; /*!< additional authentication data */
uint32_t aad_size; /*!< aad size */
} cau_parameter_struct;
/* cau_ctl register value */
#define CAU_ENCRYPT ((uint32_t)0x00000000U) /*!< encrypt */
#define CAU_DECRYPT CAU_CTL_CAUDIR /*!< decrypt */
#define CTL_ALGM(regval) ((BITS(3,5) & ((uint32_t)(regval) << 3U)) | \
(BIT(19) & ((uint32_t)(regval) << 16U))) /*!< write value to CAU_CTL_ALGM bit field */
#define CAU_MODE_TDES_ECB CTL_ALGM(0) /*!< TDES-ECB (3DES Electronic codebook) */
#define CAU_MODE_TDES_CBC CTL_ALGM(1) /*!< TDES-CBC (3DES Cipher block chaining) */
#define CAU_MODE_DES_ECB CTL_ALGM(2) /*!< DES-ECB (simple DES Electronic codebook) */
#define CAU_MODE_DES_CBC CTL_ALGM(3) /*!< DES-CBC (simple DES Cipher block chaining) */
#define CAU_MODE_AES_ECB CTL_ALGM(4) /*!< AES-ECB (AES Electronic codebook) */
#define CAU_MODE_AES_CBC CTL_ALGM(5) /*!< AES-CBC (AES Cipher block chaining) */
#define CAU_MODE_AES_CTR CTL_ALGM(6) /*!< AES-CTR (AES counter mode) */
#define CAU_MODE_AES_KEY CTL_ALGM(7) /*!< AES decryption key preparation mode */
#define CAU_MODE_AES_GCM CTL_ALGM(8) /*!< AES-GCM (AES Galois/counter mode) */
#define CAU_MODE_AES_CCM CTL_ALGM(9) /*!< AES-CCM (AES combined cipher machine mode) */
#define CAU_MODE_AES_CFB CTL_ALGM(10) /*!< AES-CFB (cipher feedback mode) */
#define CAU_MODE_AES_OFB CTL_ALGM(11) /*!< AES-OFB (output feedback mode) */
#define CTL_DATAM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) /*!< write value to CAU_CTL_DATAM bit field */
#define CAU_SWAPPING_32BIT CTL_DATAM(0) /*!< no swapping */
#define CAU_SWAPPING_16BIT CTL_DATAM(1) /*!< half-word swapping */
#define CAU_SWAPPING_8BIT CTL_DATAM(2) /*!< bytes swapping */
#define CAU_SWAPPING_1BIT CTL_DATAM(3) /*!< bit swapping */
#define CAU_KEY 0x00000000U /*!< use the key from CAU register */
#define CAU_EFUSE_KEY 0x00000001U /*!< use the key from EFUSE */
#define CTL_KEYM(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U)) /*!< write value to CAU_CTL_KEYM bit field */
#define CAU_KEYSIZE_128BIT CTL_KEYM(0) /*!< 128 bit key length */
#define CAU_KEYSIZE_192BIT CTL_KEYM(1) /*!< 192 bit key length */
#define CAU_KEYSIZE_256BIT CTL_KEYM(2) /*!< 256 bit key length */
#define CTL_GCM_CCMPH(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) /*!< write value to CAU_CTL_GCM_CCMPH bit field */
#define CAU_PREPARE_PHASE CTL_GCM_CCMPH(0) /*!< prepare phase */
#define CAU_AAD_PHASE CTL_GCM_CCMPH(1) /*!< AAD phase */
#define CAU_ENCRYPT_DECRYPT_PHASE CTL_GCM_CCMPH(2) /*!< encryption/decryption phase */
#define CAU_TAG_PHASE CTL_GCM_CCMPH(3) /*!< tag phase */
#define CAU_PADDING_BYTES(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20U))
/* cau_stat0 register value */
#define CAU_FLAG_INFIFO_EMPTY CAU_STAT0_IEM /*!< IN FIFO empty */
#define CAU_FLAG_INFIFO_NO_FULL CAU_STAT0_INF /*!< IN FIFO is not full */
#define CAU_FLAG_OUTFIFO_NO_EMPTY CAU_STAT0_ONE /*!< OUT FIFO not empty */
#define CAU_FLAG_OUTFIFO_FULL CAU_STAT0_OFU /*!< OUT FIFO is full */
#define CAU_FLAG_BUSY CAU_STAT0_BUSY /*!< the CAU core is busy */
/* cau_dmaen register value */
#define CAU_DMA_INFIFO CAU_DMAEN_DMAIEN /*!< DMA input enable */
#define CAU_DMA_OUTFIFO CAU_DMAEN_DMAOEN /*!< DMA output enable */
/* cau_inten register value */
#define CAU_INT_INFIFO CAU_INTEN_IINTEN /*!< IN FIFO Interrupt */
#define CAU_INT_OUTFIFO CAU_INTEN_OINTEN /*!< OUT FIFO Interrupt */
/* cau_stat1 register value */
#define CAU_FLAG_INFIFO CAU_STAT1_ISTA /*!< IN FIFO flag status */
#define CAU_FLAG_OUTFIFO CAU_STAT1_OSTA /*!< OUT FIFO flag status */
/* cau_intf register value */
#define CAU_INT_FLAG_INFIFO CAU_INTF_IINTF /*!< IN FIFO interrupt status */
#define CAU_INT_FLAG_OUTFIFO CAU_INTF_OINTF /*!< OUT FIFO interrupt status */
/* function declarations */
/* initialization functions */
/* reset the CAU peripheral */
void cau_deinit(void);
/* initialize the CAU encrypt and decrypt parameter struct with the default values */
void cau_struct_para_init(cau_parameter_struct *cau_parameter);
/* initialize the key parameter struct with the default values */
void cau_key_struct_para_init(cau_key_parameter_struct *key_initpara);
/* initialize the vectors parameter struct with the default values */
void cau_iv_struct_para_init(cau_iv_parameter_struct *iv_initpara);
/* initialize the context parameter struct with the default values */
void cau_context_struct_para_init(cau_context_parameter_struct *cau_context);
/* configuration functions */
/* enable the CAU peripheral */
void cau_enable(void);
/* disable the CAU peripheral */
void cau_disable(void);
/* enable the CAU DMA interface */
void cau_dma_enable(uint32_t dma_req);
/* disable the CAU DMA interface */
void cau_dma_disable(uint32_t dma_req);
/* initialize the CAU peripheral */
void cau_init(uint32_t alg_dir, uint32_t algo_mode, uint32_t swapping);
/* configure key selection */
void cau_aes_key_select(uint32_t key_selection);
/* configure key size if use AES algorithm */
void cau_aes_keysize_config(uint32_t key_size);
/* initialize the key parameters */
void cau_key_init(cau_key_parameter_struct *key_initpara);
/* initialize the vectors parameters */
void cau_iv_init(cau_iv_parameter_struct *iv_initpara);
/* configure phase */
void cau_phase_config(uint32_t phase);
/* flush the IN and OUT FIFOs */
void cau_fifo_flush(void);
/* return whether CAU peripheral is enabled or disabled */
ControlStatus cau_enable_state_get(void);
/* read and write functions */
/* write data to the IN FIFO */
void cau_data_write(uint32_t data);
/* return the last data entered into the output FIFO */
uint32_t cau_data_read(void);
/* context switch functions */
/* save context before context switching */
void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_parameter_struct *key_initpara);
/* restore context after context switching */
void cau_context_restore(cau_context_parameter_struct *cau_context);
/* encrypt and decrypt functions */
/* encrypt and decrypt using AES in ECB mode */
ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using AES in CBC mode */
ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using AES in CTR mode */
ErrStatus cau_aes_ctr(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using AES in CFB mode */
ErrStatus cau_aes_cfb(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using AES in OFB mode */
ErrStatus cau_aes_ofb(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using AES in GCM mode */
ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint8_t *tag);
/* encrypt and decrypt using AES in CCM mode */
ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint8_t tag[], uint32_t tag_size, uint8_t aad_buf[]);
/* encrypt and decrypt using TDES in ECB mode */
ErrStatus cau_tdes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using TDES in CBC mode */
ErrStatus cau_tdes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using DES in ECB mode */
ErrStatus cau_des_ecb(cau_parameter_struct *cau_parameter, uint8_t *output);
/* encrypt and decrypt using DES in CBC mode */
ErrStatus cau_des_cbc(cau_parameter_struct *cau_parameter, uint8_t *output);
/* interrupt & flag functions */
/* get the CAU flag status */
FlagStatus cau_flag_get(uint32_t flag);
/* enable the CAU interrupts */
void cau_interrupt_enable(uint32_t interrupt);
/* disable the CAU interrupts */
void cau_interrupt_disable(uint32_t interrupt);
/* get the interrupt flag */
FlagStatus cau_interrupt_flag_get(uint32_t int_flag);
#endif /* GD32H7XX_CAU_H */

220
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cmp.h Normal file
View File

@@ -0,0 +1,220 @@
/*!
\file gd32h7xx_cmp.h
\brief definitions for the CMP
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_CMP_H
#define GD32H7XX_CMP_H
#include "gd32h7xx.h"
/* CMP definitions */
#define CMP CMP_BASE /*!< CMP base address */
/* registers definitions */
#define CMP_STAT REG32((CMP) + 0x00000000U) /*!< CMP status register */
#define CMP_IFC REG32((CMP) + 0x00000004U) /*!< CMP interrupt flag clear register */
#define CMP_SR REG32((CMP) + 0x00000008U) /*!< CMP alternate select register */
#define CMP0_CS REG32((CMP) + 0x0000000CU) /*!< CMP0 control and status register */
#define CMP1_CS REG32((CMP) + 0x00000010U) /*!< CMP1 control and status register */
/* bits definitions */
/* CMP_STAT */
#define CMP_STAT_CMP0O BIT(0) /*!< CMP0 output */
#define CMP_STAT_CMP1O BIT(1) /*!< CMP1 output */
#define CMP_STAT_CMP0IF BIT(16) /*!< CMP0 interrupt flag */
#define CMP_STAT_CMP1IF BIT(17) /*!< CMP1 interrupt flag */
/* CMP_IFC */
#define CMP_IFC_CMP0IC BIT(16) /*!< CMP0 interrupt flag clear */
#define CMP_IFC_CMP1IC BIT(17) /*!< CMP1 interrupt flag clear */
/* CMP_SR */
#define CMP_SR_AFSE_PA6 BITS(0,10) /*!< CMP selects alternate output ports PA6 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PA8 BIT(1) /*!< PA8 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PB12 BIT(2) /*!< PB12 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PE6 BIT(3) /*!< PE6 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PE15 BIT(4) /*!< PE15 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG2 BIT(5) /*!< PG2 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG3 BIT(6) /*!< PG3 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG4 BIT(7) /*!< PG4 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK0 BIT(8) /*!< PK0 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK1 BIT(9) /*!< PK1 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK2 BIT(10) /*!< PK2 alternate function select for CMPx_OUT */
/* CMPx_CS */
#define CMP_CS_CMPXEN BIT(0) /*!< CMPx enable */
#define CMP_CS_CMPXBEN BIT(1) /*!< CMPx scaler bridge enable bit */
#define CMP_CS_CMPXSEN BIT(2) /*!< CMPx voltage scaler enable bit */
#define CMP_CS_CMPXPL BIT(3) /*!< CMPx output polarity */
#define CMP_CS_WNDEN BIT(4) /*!< CMP Window mode enable */
#define CMP_CS_CMPXINTEN BIT(6) /*!< CMPx interrupt enable */
#define CMP_CS_CMPXHST BITS(8,9) /*!< CMPx hysteresis */
#define CMP_CS_CMPXM BITS(12,13) /*!< CMPx mode */
#define CMP_CS_CMPXMISEL BITS(16,18) /*!< CMP_IM input selection */
#define CMP_CS_CMPXPSEL BIT(20) /*!< CMP_IP input selection */
#define CMP_CS_CMPXBLK BITS(24,27) /*!< CMPx output blanking source */
#define CMP_CS_CMPXLK BIT(31) /*!< CMPx lock */
/* constants definitions */
/* CMP units */
typedef enum{
CMP0, /*!< comparator 0 */
CMP1 /*!< comparator 1 */
}cmp_enum;
/* CMP operating mode */
#define CS_CMPXM(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */
#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */
#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */
/* CMP hysteresis */
#define CS_CMPXHST(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U))
#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */
#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */
#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */
#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */
/* CMP inverting input */
#define CS_CMPXMSEL(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */
#define CMP_INVERTING_INPUT_PA4 CS_CMPXMSEL(4) /*!< CMP inverting input DAC0_OUT0 */
#define CMP_INVERTING_INPUT_PA5 CS_CMPXMSEL(5) /*!< CMP inverting input DAC0_OUT1 */
#define CMP_INVERTING_INPUT_PB1_PE10 CS_CMPXMSEL(6) /*!< CMP inverting input PB1 for CMP0 or PE10 for CMP1 */
#define CMP_INVERTING_INPUT_PC4_PE7 CS_CMPXMSEL(7) /*!< CMP inverting input PC4 for CMP0 or PE7 for CMP1 */
/* CMP noninverting input*/
#define CS_CMPXPSEL(regval) (BIT(20) & ((uint32_t)(regval) << 20U))
#define CMP_NONINVERTING_INPUT_PB0_PE9 CS_CMPXPSEL(0) /*!< CMP noninverting input PB0 for CMP0 or PE9 for CMP1 */
#define CMP_NONINVERTING_INPUT_PB2_PE11 CS_CMPXPSEL(1) /*!< CMP noninverting input PB2 for CMP0 or PE11 for CMP1 */
/* CMP output polarity*/
#define CS_CMPXPL(regval) (BIT(3) & ((uint32_t)(regval) << 3U))
#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */
#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */
/* CMP blanking suorce */
#define CS_CMPXBLK(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
#define CMP_BLANKING_NONE CS_CMPXBLK(0) /*!< CMP no blanking source */
#define CMP_BLANKING_TIMER0_OC0 CS_CMPXBLK(1) /*!< CMP TIMER0_CH0 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER1_OC2 CS_CMPXBLK(2) /*!< CMP TIMER1_CH2 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER2_OC2 CS_CMPXBLK(3) /*!< CMP TIMER2_CH2 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER2_OC3 CS_CMPXBLK(4) /*!< CMP TIMER2_CH3 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER7_OC4 CS_CMPXBLK(5) /*!< CMP TIMER7_CH0 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER14_OC0 CS_CMPXBLK(6) /*!< CMP TIMER14_CH0 output compare signal selected as blanking source */
/* comparator output level */
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< comparator output high */
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< comparator output low */
/* CMP alternate output ports */
#define SR_AFSE(regval) (BITS(0,10) & ((uint32_t)(regval) << 0U))
#define CMP_AFSE_GPIO_PA6 SR_AFSE(0) /*!< CMP alternate GPIO PA6 */
#define CMP_AFSE_GPIO_PA8 SR_AFSE(1) /*!< CMP alternate GPIO PA8 */
#define CMP_AFSE_GPIO_PB12 SR_AFSE(2) /*!< CMP alternate GPIO PB12 */
#define CMP_AFSE_GPIO_PE6 SR_AFSE(3) /*!< CMP alternate GPIO PE6 */
#define CMP_AFSE_GPIO_PE15 SR_AFSE(4) /*!< CMP alternate GPIO PE15 */
#define CMP_AFSE_GPIO_PG2 SR_AFSE(5) /*!< CMP alternate GPIO PG2 */
#define CMP_AFSE_GPIO_PG3 SR_AFSE(6) /*!< CMP alternate GPIO PG3 */
#define CMP_AFSE_GPIO_PG4 SR_AFSE(7) /*!< CMP alternate GPIO PG4 */
#define CMP_AFSE_GPIO_PK0 SR_AFSE(8) /*!< CMP alternate GPIO PK0 */
#define CMP_AFSE_GPIO_PK1 SR_AFSE(9) /*!< CMP alternate GPIO PK1*/
#define CMP_AFSE_GPIO_PK2 SR_AFSE(10) /*!< CMP alternate GPIO PK2 */
/* CMP flag definitions */
#define CMP_FLAG_COMPARE CMP_STAT_CMP0IF /*!< CMP compare flag */
/* CMP interrupt definitions */
#define CMP_INT_COMPARE CMP_CS_CMPXINTEN /*!< CMP compare interrupt */
/* CMP interrupt flag */
#define CMP_INT_FLAG_COMPARE CMP_STAT_CMP0IF /*!< CMP interrupt flag */
/* function declarations */
/* initialization functions */
/* CMP deinit */
void cmp_deinit(cmp_enum cmp_periph);
/* CMP mode init */
void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis);
/* CMP noninverting input select */
void cmp_noninverting_input_select(cmp_enum cmp_periph, uint32_t noninverting_input);
/* CMP output init */
void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity);
/* config comparator output port */
void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel);
/* CMP output blanking function init */
void cmp_blanking_init(cmp_enum cmp_periph,uint32_t blanking_source_selection);
/* enable functions */
/* enable CMP */
void cmp_enable(cmp_enum cmp_periph);
/* disable CMP */
void cmp_disable(cmp_enum cmp_periph);
/* enable the window mode */
void cmp_window_enable(void);
/* disable the window mode */
void cmp_window_disable(void);
/* lock the CMP */
void cmp_lock_enable(cmp_enum cmp_periph);
/* enable the voltage scaler */
void cmp_voltage_scaler_enable(cmp_enum cmp_periph);
/* disable the voltage scaler */
void cmp_voltage_scaler_disable(cmp_enum cmp_periph);
/* enable the scaler bridge */
void cmp_scaler_bridge_enable(cmp_enum cmp_periph);
/* disable the scaler bridge */
void cmp_scaler_bridge_disable(cmp_enum cmp_periph);
/* get state related functions */
/* get output level */
uint32_t cmp_output_level_get(cmp_enum cmp_periph);
/* flag and interrupt functions */
/* get CMP flag */
FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag);
/* clear CMP flag */
void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag);
/* enable CMP interrupt */
void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt);
/* disable CMP interrupt */
void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt);
/* get CMP interrupt flag */
FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag);
/* clear CMP interrupt flag */
void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag);
#endif /* GD32H7XX_CMP_H */

104
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cpdm.h Normal file
View File

@@ -0,0 +1,104 @@
/*!
\file gd32h7xx_cpdm.h
\brief definitions for the CPDM
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_CPDM_H
#define GD32H7XX_CPDM_H
#include "gd32h7xx.h"
/* CPDM definitions */
#define CPDM_SDIO0 (SDIO0 + 0x00001000U) /*!< SDIO0 CPDM base address */
#define CPDM_SDIO1 (SDIO1 + 0x00000400U) /*!< SDIO1 CPDM base address */
/* registers definitions */
#define CPDM_CTL(cpdmx) REG32((cpdmx) + 0x00000000U) /*!< CPDM control register */
#define CPDM_CFG(cpdmx) REG32((cpdmx) + 0x00000004U) /*!< CPDM configuration register */
/* bits definitions */
/* CPDM_CTL */
#define CPDM_CTL_CPDMEN BIT(0) /*!< CPDM enable */
#define CPDM_CTL_DLSEN BIT(1) /*!< CPDM delay line sample module enable */
/* CPDM_CFG */
#define CPDM_CFG_CPSEL BITS(0,3) /*!< select the phase of the output clock */
#define CPDM_CFG_DLSTCNT BITS(8,14) /*!< define a delay step count for a unit delay UNIT */
#define CPDM_CFG_DLLEN BITS(16,27) /*!< delay line length */
#define CPDM_CFG_DLLENF BIT(31) /*!< valid mark of delay line length */
/* constants definitions */
/* output clock phase selection enum definition */
typedef enum
{
CPDM_OUTPUT_PHASE_SELECTION_0 = 0, /*!< output clock phase = input clock */
CPDM_OUTPUT_PHASE_SELECTION_1, /*!< output clock phase = input clock + 1 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_2, /*!< output clock phase = input clock + 2 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_3, /*!< output clock phase = input clock + 3 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_4, /*!< output clock phase = input clock + 4 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_5, /*!< output clock phase = input clock + 5 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_6, /*!< output clock phase = input clock + 6 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_7, /*!< output clock phase = input clock + 7 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_8, /*!< output clock phase = input clock + 8 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_9, /*!< output clock phase = input clock + 9 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_10, /*!< output clock phase = input clock + 10 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_11, /*!< output clock phase = input clock + 11 * UNIT delay */
CPDM_OUTPUT_PHASE_SELECTION_12, /*!< output clock phase = input clock + 12 * UNIT delay */
}cpdm_output_phase_enum;
#define CPDM_MAX_DELAY_STEP_COUNT ((uint32_t)0x0000007FU) /*!< max UNIT value */
#define CPDM_MAX_PHASE ((uint32_t)0x0000000CU) /*!< max select value of the phase */
/* function declarations */
/* deinitialization and initialization functions */
/* enable CPDM */
void cpdm_enable(uint32_t cpdm_periph);
/* disable CPDM */
void cpdm_disable(uint32_t cpdm_periph);
/* enable CPDM delay line sample module */
void cpdm_delayline_sample_enable(uint32_t cpdm_periph);
/* disable CPDM delay line sample module */
void cpdm_delayline_sample_disable(uint32_t cpdm_periph);
/* output clock configuration functions */
/* select CPDM output clock phase */
void cpdm_output_clock_phase_select(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase);
/* get delay line length valid flag */
FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph);
/* get delay line length */
uint16_t cpdm_delayline_length_get(uint32_t cpdm_periph);
/* clock output function */
/* configure CPDM clock output */
void cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase);
#endif /* GD32H7XX_CPDM_H */

122
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_crc.h Normal file
View File

@@ -0,0 +1,122 @@
/*!
\file gd32h7xx_crc.h
\brief definitions for the CRC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_CRC_H
#define GD32H7XX_CRC_H
#include "gd32h7xx.h"
/* CRC definitions */
#define CRC CRC_BASE /*!< CRC bsae address */
/* registers definitions */
#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
/* CRC_INIT */
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
/* CRC_POLY */
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
/* constants definitions */
/* size of polynomial function */
#define CTL_PS(regval) (BITS(3,4) & ((regval) << 3U))
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
/* input data reverse function */
#define CTL_REV_I(regval) (BITS(5,6) & ((regval) << 5U))
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
/* input data format */
#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* enable the reverse operation of output data */
void crc_reverse_output_data_enable(void);
/* disable the reverse operation of output data */
void crc_reverse_output_data_disable(void);
/* reset data register to the value of initialization data register */
void crc_data_register_reset(void);
/* read the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* write the initial value register */
void crc_init_data_register_write(uint32_t init_data);
/* configure the CRC input data function */
void crc_input_data_reverse_config(uint32_t data_reverse);
/* configure the CRC size of polynomial function */
void crc_polynomial_size_set(uint32_t poly_size);
/* configure the CRC polynomial value function */
void crc_polynomial_set(uint32_t poly);
/* CRC calculate single data */
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
/* CRC calculate a data array */
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
#endif /* GD32H7XX_CRC_H */

184
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ctc.h Normal file
View File

@@ -0,0 +1,184 @@
/*!
\file gd32h7xx_ctc.h
\brief definitions for the CTC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_CTC_H
#define GD32H7XX_CTC_H
#include "gd32h7xx.h"
/* CTC definitions */
#define CTC CTC_BASE
/* registers definitions */
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/* bits definitions */
/* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
/* CTC_CTL1 */
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
/* CTC_STAT */
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
/* CTC_INTC */
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
/* constants definitions */
/* hardware automatically trim mode definitions */
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
/* reference signal source polarity definitions */
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
/* reference signal source selection definitions */
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
/* reference signal source prescaler definitions */
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
/* CTC interrupt enable definitions */
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
/* CTC interrupt source definitions */
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
/* CTC flag definitions */
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
/* function declarations */
/* reset ctc clock trim controller */
void ctc_deinit(void);
/* enable CTC trim counter */
void ctc_counter_enable(void);
/* disable CTC trim counter */
void ctc_counter_disable(void);
/* configure the IRC48M trim value */
void ctc_irc48m_trim_value_config(uint8_t trim_value);
/* generate software reference source sync pulse */
void ctc_software_refsource_pulse_generate(void);
/* configure hardware automatically trim mode */
void ctc_hardware_trim_mode_config(uint32_t hardmode);
/* configure reference signal source polarity */
void ctc_refsource_polarity_config(uint32_t polarity);
/* select reference signal source */
void ctc_refsource_signal_select(uint32_t refs);
/* configure reference signal source prescaler */
void ctc_refsource_prescaler_config(uint32_t prescaler);
/* configure clock trim base limit value */
void ctc_clock_limit_value_config(uint8_t limit_value);
/* configure CTC counter reload value */
void ctc_counter_reload_value_config(uint16_t reload_value);
/* read CTC counter capture value when reference sync pulse occurred */
uint16_t ctc_counter_capture_value_read(void);
/* read CTC trim counter direction when reference sync pulse occurred */
FlagStatus ctc_counter_direction_read(void);
/* read CTC counter reload value */
uint16_t ctc_counter_reload_value_read(void);
/* read the IRC48M trim value */
uint8_t ctc_irc48m_trim_value_read(void);
/* interrupt & flag functions */
/* get CTC flag */
FlagStatus ctc_flag_get(uint32_t flag);
/* clear CTC flag */
void ctc_flag_clear(uint32_t flag);
/* enable the CTC interrupt */
void ctc_interrupt_enable(uint32_t interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H7XX_CTC_H */

321
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dac.h Normal file
View File

@@ -0,0 +1,321 @@
/*!
\file gd32h7xx_dac.h
\brief definitions for the DAC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_DAC_H
#define GD32H7XX_DAC_H
#include "gd32h7xx.h"
/* DACx(x=0) definitions */
#define DAC0 (DAC_BASE)
/* registers definitions */
#define DAC_CTL0(dacx) REG32((dacx) + 0x00000000U) /*!< DACx control register 0 */
#define DAC_SWT(dacx) REG32((dacx) + 0x00000004U) /*!< DACx software trigger register */
#define DAC_OUT0_R12DH(dacx) REG32((dacx) + 0x00000008U) /*!< DACx_OUT0 12-bit right-aligned data holding register */
#define DAC_OUT0_L12DH(dacx) REG32((dacx) + 0x0000000CU) /*!< DACx_OUT0 12-bit left-aligned data holding register */
#define DAC_OUT0_R8DH(dacx) REG32((dacx) + 0x00000010U) /*!< DACx_OUT0 8-bit right-aligned data holding register */
#define DAC_OUT1_R12DH(dacx) REG32((dacx) + 0x00000014U) /*!< DACx_OUT1 12-bit right-aligned data holding register */
#define DAC_OUT1_L12DH(dacx) REG32((dacx) + 0x00000018U) /*!< DACx_OUT1 12-bit left-aligned data holding register */
#define DAC_OUT1_R8DH(dacx) REG32((dacx) + 0x0000001CU) /*!< DACx_OUT1 8-bit right-aligned data holding register */
#define DACC_R12DH(dacx) REG32((dacx) + 0x00000020U) /*!< DACx concurrent mode 12-bit right-aligned data holding register */
#define DACC_L12DH(dacx) REG32((dacx) + 0x00000024U) /*!< DACx concurrent mode 12-bit left-aligned data holding register */
#define DACC_R8DH(dacx) REG32((dacx) + 0x00000028U) /*!< DACx concurrent mode 8-bit right-aligned data holding register */
#define DAC_OUT0_DO(dacx) REG32((dacx) + 0x0000002CU) /*!< DACx_OUT0 data output register */
#define DAC_OUT1_DO(dacx) REG32((dacx) + 0x00000030U) /*!< DACx_OUT1 data output register */
#define DAC_STAT0(dacx) REG32((dacx) + 0x00000034U) /*!< DACx status register 0 */
#define DAC_CALR(dacx) REG32((dacx) + 0x00000038U) /*!< DACx calibration register */
#define DAC_MDCR(dacx) REG32((dacx) + 0x0000003CU) /*!< DACx mode control register */
#define DAC_SKSTR0(dacx) REG32((dacx) + 0x00000040U) /*!< DACx sample and keep sample time register 0 */
#define DAC_SKSTR1(dacx) REG32((dacx) + 0x00000044U) /*!< DACx sample and keep sample time register 1 */
#define DAC_SKKTR(dacx) REG32((dacx) + 0x00000048U) /*!< DACx sample and keep keep time register */
#define DAC_SKRTR(dacx) REG32((dacx) + 0x0000004CU) /*!< DACx sample and keep refresh time register */
/* bits definitions */
/* DAC_CTL0 */
#define DAC_CTL0_DEN0 BIT(0) /*!< DACx_OUT0 enable */
#define DAC_CTL0_DTEN0 BIT(1) /*!< DACx_OUT0 trigger enable */
#define DAC_CTL0_DTSEL0 BITS(2,3) /*!< DACx_OUT0 trigger selection */
#define DAC_CTL0_DWM0 BITS(6,7) /*!< DACx_OUT0 noise wave mode */
#define DAC_CTL0_DWBW0 BITS(8,11) /*!< DACx_OUT0 noise wave bit width */
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
#define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DACx_OUT0 DMA underrun interrupt enable */
#define DAC_CTL0_CALEN0 BIT(14) /*!< DACx_OUT0 calibration enable */
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable bit */
#define DAC_CTL0_DTEN1 BIT(17) /*!< DACx_OUT1 trigger enable */
#define DAC_CTL0_DTSEL1 BITS(18,19) /*!< DACx_OUT1 trigger selection */
#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */
#define DAC_CTL0_DWBW1 BITS(24,27) /*!< DACx_OUT1 noise wave bit width */
#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DACx_OUT1 DMA enable */
#define DAC_CTL0_DDUDRIE1 BIT(29) /*!< DACx_OUT1 DMA underrun interrupt enable */
#define DAC_CTL0_CALEN1 BIT(30) /*!< DACx_OUT1 calibration enable */
/* DAC_SWT */
#define DAC_SWT_SWTR0 BIT(0) /*!< DACx_OUT0 software trigger */
#define DAC_SWT_SWTR1 BIT(1) /*!< DACx_OUT1 software trigger */
/* DAC0_R12DH */
#define DAC_OUT0_DH_R12 BITS(0,11) /*!< DACx_OUT0 12-bit right-aligned data */
/* DAC0_L12DH */
#define DAC_OUT0_DH_L12 BITS(4,15) /*!< DACx_OUT0 12-bit left-aligned data */
/* DAC0_R8DH */
#define DAC_OUT0_DH_R8DH BITS(0,7) /*!< DACx_OUT0 8-bit right-aligned data */
/* DAC1_R12DH */
#define DAC_OUT1_DH_R12 BITS(0,11) /*!< DACx_OUT1 12-bit right-aligned data */
/* DAC1_L12DH */
#define DAC_OUT1_DH_L12 BITS(4,15) /*!< DACx_OUT1 12-bit left-aligned data */
/* DAC1_R8DH */
#define DAC_OUT1_DH_R8 BITS(0,7) /*!< DACx_OUT1 8-bit right-aligned data */
/* DACC_R12DH */
#define DACC_OUT0_DH_R12 BITS(0,11) /*!< DAC concurrent mode DACx_OUT0 12-bit right-aligned data */
#define DACC_OUT1_DH_R12 BITS(16,27) /*!< DAC concurrent mode DACx_OUT1 12-bit right-aligned data */
/* DACC_L12DH */
#define DACC_OUT0_DH_L12 BITS(4,15) /*!< DAC concurrent mode DACx_OUT0 12-bit left-aligned data */
#define DACC_OUT1_DH_L12 BITS(20,31) /*!< DAC concurrent mode DACx_OUT1 12-bit left-aligned data */
/* DACC_R8DH */
#define DACC_OUT0_DH_R8 BITS(0,7) /*!< DAC concurrent mode DACx_OUT0 8-bit right-aligned data */
#define DACC_OUT1_DH_R8 BITS(8,15) /*!< DAC concurrent mode DACx_OUT1 8-bit right-aligned data */
/* DAC0_DO */
#define DAC_OUT0_DO_BITS BITS(0,11) /*!< DACx_OUT0 12-bit output data */
/* DAC1_DO */
#define DAC_OUT1_DO_BITS BITS(0,11) /*!< DACx_OUT1 12-bit output data */
/* DAC_STAT0 */
#define DAC_STAT0_DDUDR0 BIT(13) /*!< DACx_OUT0 DMA underrun flag */
#define DAC_STAT0_CALF0 BIT(14) /*!< DACx_OUT0 calibration offset flag */
#define DAC_STAT0_BWT0 BIT(15) /*!< DACx_OUT0 SKSTR0 writing flag */
#define DAC_STAT0_DDUDR1 BIT(29) /*!< DACx_OUT1 DMA underrun flag */
#define DAC_STAT0_CALF1 BIT(30) /*!< DACx_OUT1 calibration offset flag */
#define DAC_STAT0_BWT1 BIT(31) /*!< DACx_OUT1 SKSTR1 writing flag */
/* DAC_CALR */
#define DAC_CALR_OTV0 BITS(0,4) /*!< DACx_OUT0 offset calibration value */
#define DAC_CALR_OTV1 BITS(16,20) /*!< DACx_OUT1 offset calibration value */
/* DAC_MDCR */
#define DAC_MDCR_MODE0 BITS(0,2) /*!< DACx_OUT0 mode */
#define DAC_MDCR_MODE1 BITS(16,18) /*!< DACx_OUT1 mode */
/* DAC_SKSTR0 */
#define DAC_SKSTR0_TSAMP0 BITS(0,9) /*!< DACx_OUT0 sample time */
/* DAC_SKSTR1 */
#define DAC_SKSTR1_TSAMP1 BITS(0,9) /*!< DACx_OUT1 sample time */
/* DAC_SKKTR */
#define DAC_SKKTR_TKEEP0 BITS(0,9) /*!< DACx_OUT0 keep time */
#define DAC_SKKTR_TKEEP1 BITS(16,25) /*!< DACx_OUT1 keep time */
/* DAC_SKRTR */
#define DAC_SKRTR_TREF0 BITS(0,7) /*!< DACx_OUT0 refresh time */
#define DAC_SKRTR_TREF1 BITS(16,23) /*!< DACx_OUT1 refresh time */
/* constants definitions */
/* DAC trigger source */
#define CTL0_DTSEL(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U))
#define DAC_TRIGGER_EXTERNAL CTL0_DTSEL(0) /*!< external trigger selected from TRIGSEL */
#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(1) /*!< software trigger */
/* DAC noise wave mode */
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disabled */
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
/* DAC noise wave bit width */
#define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8))
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
/* unmask LFSR bits in DAC LFSR noise mode */
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
/* triangle amplitude in DAC triangle noise mode */
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
/* DAC data alignment */
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */
/* DAC mode */
#define MODE(regval) (BITS(0,2) & ((uint32_t)(regval)))
#define NORMAL_PIN_BUFFON MODE(0) /*!< DACx_OUTy work in normal mode and connect to external pin with buffer enable */
#define NORMAL_PIN_PERIPH_BUFFON MODE(1) /*!< DACx_OUTy work in normal mode and connect to external pin and on chip peripherals with buffer enable */
#define NORMAL_PIN_BUFFOFF MODE(2) /*!< DACx_OUTy work in normal mode and connect to external pin with buffer disable */
#define NORMAL_PIN_PERIPH_BUFFOFF MODE(3) /*!< DACx_OUTy work in normal mode and connect to on chip peripherals with buffer disable */
#define SAMPLEKEEP_PIN_BUFFON MODE(4) /*!< DACx_OUTy work in sample and keep mode and connect to external pin with buffer enable */
#define SAMPLEKEEP_PIN_PERIPH_BUFFON MODE(5) /*!< DACx_OUTy work in sample and keep mode and connect to external pin and on chip peripherals with buffer enable */
#define SAMPLEKEEP_PIN_BUFFOFF MODE(6) /*!< DACx_OUTy work in sample and keep mode and connect to external pin and on chip peripherals with buffer disable */
#define SAMPLEKEEP_PIN_PERIPH_BUFFOFF MODE(7) /*!< DACx_OUTy work in sample and keep mode and connect to on chip peripherals with buffer disable */
/* DAC output channel definitions */
#define DAC_OUT0 ((uint8_t)0x00U) /*!< DACx_OUT0 channel */
#define DAC_OUT1 ((uint8_t)0x01U) /*!< DACx_OUT1 channel */
/* DAC interrupt */
#define DAC_INT_DDUDR0 DAC_CTL0_DDUDRIE0 /*!< DACx_OUT0 DMA underrun interrupt enable */
#define DAC_INT_DDUDR1 DAC_CTL0_DDUDRIE1 /*!< DACx_OUT1 DMA underrun interrupt enable */
/* DAC interrupt flag */
#define DAC_INT_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DACx_OUT0 DMA underrun interrupt flag */
#define DAC_INT_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DACx_OUT1 DMA underrun interrupt flag */
/* DAC flags */
#define DAC_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DACx_OUT0 DMA underrun flag */
#define DAC_FLAG_CALF0 DAC_STAT0_CALF0 /*!< DACx_OUT0 calibration offset flag */
#define DAC_FLAG_BWT0 DAC_STAT0_BWT0 /*!< DACx_OUT0 sample and keep wtire enable flag */
#define DAC_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DACx_OUT1 DMA underrun flag */
#define DAC_FLAG_CALF1 DAC_STAT0_CALF1 /*!< DACx_OUT1 calibration offset flag */
#define DAC_FLAG_BWT1 DAC_STAT0_BWT1 /*!< DACx_OUT1 sample and keep wtire enable flag */
/* function declarations */
/* DAC initialization functions */
/* deinitialize DAC */
void dac_deinit(uint32_t dac_periph);
/* enable DAC */
void dac_enable(uint32_t dac_periph, uint8_t dac_out);
/* disable DAC */
void dac_disable(uint32_t dac_periph, uint8_t dac_out);
/* enable DAC DMA function */
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out);
/* disable DAC DMA function */
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out);
/* DAC buffer functions */
/* configure DAC mode */
void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode);
/* get the DACx trimming value */
uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out);
/* set the DACx trimming value */
void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim_value);
/* enable the DACx trimming */
void dac_trimming_enable(uint32_t dac_periph, uint32_t dac_out);
/* read and write operation functions */
/* get DAC output value */
uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out);
/* set DAC data holding register value */
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data);
/* DAC trigger configuration */
/* enable DAC trigger */
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
/* disable DAC trigger */
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out);
/* configure DAC trigger source */
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource);
/* enable DAC software trigger */
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
/* DAC wave mode configuration */
/* configure DAC wave mode */
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode);
/* configure DAC LFSR noise mode */
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits);
/* configure DAC triangle noise mode */
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude);
/* DAC concurrent mode configuration */
/* enable DAC concurrent mode */
void dac_concurrent_enable(uint32_t dac_periph);
/* disable DAC concurrent mode */
void dac_concurrent_disable(uint32_t dac_periph);
/* enable DAC concurrent software trigger */
void dac_concurrent_software_trigger_enable(uint32_t dac_periph);
/* set DAC concurrent mode data holding register value */
void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1);
/* DAC sample and keep functions */
/* DAC sample and keep mode config */
void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t sample_time, uint32_t keep_time, uint32_t refresh_time);
/* DAC interrupt and flag functions */
/* get DAC flag */
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag);
/* clear DAC flag */
void dac_flag_clear(uint32_t dac_periph, uint32_t flag);
/* enable DAC interrupt */
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt);
/* disable DAC interrupt */
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt);
/* get DAC interrupt flag */
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag);
/* clear DAC interrupt flag */
void dac_interrupt_flag_clear(uint32_t dac_periph, uint32_t int_flag);
#endif /* GD32H7XX_DAC_H */

187
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dbg.h Normal file
View File

@@ -0,0 +1,187 @@
/*!
\file gd32h7xx_dbg.h
\brief definitions for the DBG
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_DBG_H
#define GD32H7XX_DBG_H
#include "gd32h7xx.h"
/* DBG definitions */
#define DBG DBG_BASE /*!< DBG base address */
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */
#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */
#define DBG_CTL1 REG32(DBG + 0x00000034U) /*!< DBG control register 1 */
#define DBG_CTL2 REG32(DBG + 0x0000003CU) /*!< DBG control register 2 */
#define DBG_CTL3 REG32(DBG + 0x0000004CU) /*!< DBG control register 3 */
#define DBG_CTL4 REG32(DBG + 0x00000054U) /*!< DBG control register 4 */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
/* DBG_CTL0 */
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL0_TRACE_MODE BITS(18,19) /*!< trace pin mode selection */
#define DBG_CTL0_TRACECLKEN BIT(20) /*!< enable trace pin assignment */
/* DBG_CTL1 */
#define DBG_CTL1_WWDGT_HOLD BIT(6) /*!< debug WWDGT kept when core is halted */
/* DBG_CTL2 */
#define DBG_CTL2_TIMER1_HOLD BIT(0) /*!< debug TIMER1 kept when core is halted */
#define DBG_CTL2_TIMER2_HOLD BIT(1) /*!< debug TIMER2 kept when core is halted */
#define DBG_CTL2_TIMER3_HOLD BIT(2) /*!< debug TIMER3 kept when core is halted */
#define DBG_CTL2_TIMER4_HOLD BIT(3) /*!< debug TIMER4 kept when core is halted */
#define DBG_CTL2_TIMER5_HOLD BIT(4) /*!< debug TIMER5 kept when core is halted */
#define DBG_CTL2_TIMER6_HOLD BIT(5) /*!< debug TIMER6 kept when core is halted */
#define DBG_CTL2_TIMER22_HOLD BIT(6) /*!< debug TIMER22 kept when core is halted */
#define DBG_CTL2_TIMER23_HOLD BIT(7) /*!< debug TIMER23 kept when core is halted */
#define DBG_CTL2_TIMER30_HOLD BIT(8) /*!< debug TIMER30 kept when core is halted */
#define DBG_CTL2_TIMER31_HOLD BIT(9) /*!< debug TIMER31 kept when core is halted */
#define DBG_CTL2_TIMER50_HOLD BIT(10) /*!< debug TIMER50 kept when core is halted */
#define DBG_CTL2_TIMER51_HOLD BIT(11) /*!< debug TIMER51 kept when core is halted */
#define DBG_CTL2_I2C0_HOLD BIT(21) /*!< debug I2C0 kept when core is halted */
#define DBG_CTL2_I2C1_HOLD BIT(22) /*!< debug I2C1 kept when core is halted */
#define DBG_CTL2_I2C2_HOLD BIT(23) /*!< debug I2C2 kept when core is halted */
#define DBG_CTL2_I2C3_HOLD BIT(24) /*!< debug I2C3 kept when core is halted */
/* DBG_CTL3 */
#define DBG_CTL3_TIMER0_HOLD BIT(0) /*!< debug TIMER0 kept when core is halted */
#define DBG_CTL3_TIMER7_HOLD BIT(1) /*!< debug TIMER7 kept when core is halted */
#define DBG_CTL3_CAN0_HOLD BIT(2) /*!< debug CAN0 kept when core is halted */
#define DBG_CTL3_CAN1_HOLD BIT(3) /*!< debug CAN1 kept when core is halted */
#define DBG_CTL3_CAN2_HOLD BIT(4) /*!< debug CAN2 kept when core is halted */
#define DBG_CTL3_TIMER14_HOLD BIT(16) /*!< debug TIMER14 kept when core is halted */
#define DBG_CTL3_TIMER15_HOLD BIT(17) /*!< debug TIMER15 kept when core is halted */
#define DBG_CTL3_TIMER16_HOLD BIT(18) /*!< debug TIMER16 kept when core is halted */
#define DBG_CTL3_TIMER40_HOLD BIT(19) /*!< debug TIMER40 kept when core is halted */
#define DBG_CTL3_TIMER41_HOLD BIT(20) /*!< debug TIMER41 kept when core is halted */
#define DBG_CTL3_TIMER42_HOLD BIT(21) /*!< debug TIMER42 kept when core is halted */
#define DBG_CTL3_TIMER43_HOLD BIT(22) /*!< debug TIMER43 kept when core is halted */
#define DBG_CTL3_TIMER44_HOLD BIT(23) /*!< debug TIMER44 kept when core is halted */
/* DBG_CTL4 */
#define DBG_CTL4_RTC_HOLD BIT(16) /*!< debug RTC kept when core is halted */
#define DBG_CTL4_FWDGT_HOLD BIT(18) /*!< debug FWDGT kept when core is halted */
/* constants definitions */
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
/* define the peripheral debug hold bit position and its register index offset */
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
/* register index */
typedef enum
{
DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */
DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */
DBG_IDX_CTL3 = 0x4CU, /*!< DBG control register 3 offset */
DBG_IDX_CTL4 = 0x54U /*!< DBG control register 4 offset */
}dbg_reg_idx;
/* peripherals hold bit */
typedef enum
{
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< debug WWDGT kept when core is halted */
DBG_I2C3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 24U), /*!< debug I2C3 kept when core is halted */
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 23U), /*!< debug I2C2 kept when core is halted */
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 22U), /*!< debug I2C1 kept when core is halted */
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 21U), /*!< debug I2C0 kept when core is halted */
DBG_TIMER51_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 11U), /*!< debug TIMER51 kept when core is halted */
DBG_TIMER50_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 10U), /*!< debug TIMER50 kept when core is halted */
DBG_TIMER31_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 9U), /*!< debug TIMER31 kept when core is halted */
DBG_TIMER30_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 8U), /*!< debug TIMER30 kept when core is halted */
DBG_TIMER23_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 7U), /*!< debug TIMER23 kept when core is halted */
DBG_TIMER22_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 6U), /*!< debug TIMER22 kept when core is halted */
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 5U), /*!< debug TIMER6 kept when core is halted */
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 4U), /*!< debug TIMER5 kept when core is halted */
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 3U), /*!< debug TIMER4 kept when core is halted */
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 2U), /*!< debug TIMER3 kept when core is halted */
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< debug TIMER2 kept when core is halted */
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< debug TIMER1 kept when core is halted */
DBG_TIMER44_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 23U), /*!< debug TIMER44 kept when core is halted */
DBG_TIMER43_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 22U), /*!< debug TIMER43 kept when core is halted */
DBG_TIMER42_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 21U), /*!< debug TIMER42 kept when core is halted */
DBG_TIMER41_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 20U), /*!< debug TIMER41 kept when core is halted */
DBG_TIMER40_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 19U), /*!< debug TIMER40 kept when core is halted */
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 18U), /*!< debug TIMER16 kept when core is halted */
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */
DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 18U), /*!< debug FWDGT kept when core is halted */
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 16U) /*!< debug RTC kept when core is halted */
}dbg_periph_enum;
#define CTL0_TRACE_MODE(regval) (BITS(18,19) & ((uint32_t)(regval) << 18U))
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
/* function declarations */
/* deinitialize the DBG */
void dbg_deinit(void);
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/*enable low power behavior when the mcu is in debug mode*/
void dbg_low_power_enable(uint32_t dbg_low_power);
/*disable low power behavior when the mcu is in debug mode*/
void dbg_low_power_disable(uint32_t dbg_low_power);
/*enable trace pin assignment*/
void dbg_trace_pin_enable(void);
/*disable trace pin assignment*/
void dbg_trace_pin_disable(void);
/* set trace pin mode */
void dbg_trace_pin_mode_set(uint32_t trace_mode);
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
#endif /* GD32H7XX_DBG_H */

276
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dci.h Normal file
View File

@@ -0,0 +1,276 @@
/*!
\file gd32h7xx_dci.h
\brief definitions for the DCI
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_DCI_H
#define GD32H7XX_DCI_H
#include "gd32h7xx.h"
/* DCI definitions */
#define DCI DCI_BASE
/* registers definitions */
#define DCI_CTL REG32(DCI + 0x00000000U) /*!< DCI control register */
#define DCI_STAT0 REG32(DCI + 0x00000004U) /*!< DCI status register 0 */
#define DCI_STAT1 REG32(DCI + 0x00000008U) /*!< DCI status register 1 */
#define DCI_INTEN REG32(DCI + 0x0000000CU) /*!< DCI interrupt enable register */
#define DCI_INTF REG32(DCI + 0x00000010U) /*!< DCI interrupt flag register */
#define DCI_INTC REG32(DCI + 0x00000014U) /*!< DCI interrupt clear register */
#define DCI_SC REG32(DCI + 0x00000018U) /*!< DCI synchronization codes register */
#define DCI_SCUMSK REG32(DCI + 0x0000001CU) /*!< DCI synchronization codes unmask register */
#define DCI_CWSPOS REG32(DCI + 0x00000020U) /*!< DCI cropping window start position register */
#define DCI_CWSZ REG32(DCI + 0x00000024U) /*!< DCI cropping window size register */
#define DCI_DATA REG32(DCI + 0x00000028U) /*!< DCI data register */
/* bits definitions */
/* DCI_CTL */
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
#define DCI_CTL_JM BIT(3) /*!< JPEG mode */
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
#define DCI_CTL_CCEN BIT(12) /*!< CCIR enable */
#define DCI_CTL_CCMOD BIT(13) /*!< CCIR mode select */
#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */
#define DCI_CTL_AECEN BIT(15) /*!< automatic error correction enable, 1bit correction */
#define DCI_CTL_EVSEN BIT(16) /*!< external vsync enable */
/* DCI_STAT0 */
#define DCI_STAT0_HS BIT(0) /*!< HS line status */
#define DCI_STAT0_VS BIT(1) /*!< VS line status */
#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */
/* DCI_STAT1 */
#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */
#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */
#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */
#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */
#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */
#define DCI_STAT1_F0F BIT(5) /*!< CCIR field 0 */
#define DCI_STAT1_F1F BIT(6) /*!< CCIR field 1 */
#define DCI_STAT1_COFF BIT(7) /*!< CCIR change of field flag */
#define DCI_STAT1_CCEF BIT(8) /*!< CCIR error flag */
/* DCI_INTEN */
#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */
#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */
#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */
#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */
#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */
#define DCI_INTEN_F0IE BIT(5) /*!< CCIR field 0 interrupt enable */
#define DCI_INTEN_F1IE BIT(6) /*!< CCIR field 1 interrupt enable */
#define DCI_INTEN_COFIE BIT(7) /*!< CCIR change of field interrupt enable */
#define DCI_INTEN_CCEIE BIT(8) /*!< CCIR error interrupt enable */
/* DCI_INTF */
#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */
#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */
#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */
#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */
#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */
#define DCI_INTF_F0IF BIT(5) /*!< CCIR field 0 interrupt flag */
#define DCI_INTF_F1IF BIT(6) /*!< CCIR field 1 interrupt flag */
#define DCI_INTF_COFIF BIT(7) /*!< CCIR change of field interrupt flag */
#define DCI_INTF_CCEIF BIT(8) /*!< CCIR error interrupt flag */
/* DCI_INTC */
#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */
#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */
#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */
#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */
#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */
#define DCI_INTC_F0FC BIT(5) /*!< CCIR field 0 interrupt flag clear */
#define DCI_INTC_F1FC BIT(6) /*!< CCIR field 1 interrupt flag clear */
#define DCI_INTC_COFFC BIT(7) /*!< CCIR change of field flag clear */
#define DCI_INTC_CCEFC BIT(8) /*!< CCIR error flag clear */
/* DCI_SC */
#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */
#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */
#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */
#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */
/* DCI_SCUNMSK */
#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */
#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */
#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */
#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */
/* DCI_CWSPOS */
#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */
#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */
/* DCI_CWSZ */
#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */
#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
/* constants definitions */
/* DCI parameter structure definitions */
typedef struct {
uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
uint32_t clock_polarity; /*!< clock polarity selection */
uint32_t hsync_polarity; /*!< horizontal polarity selection */
uint32_t vsync_polarity; /*!< vertical polarity selection */
uint32_t frame_rate; /*!< frame capture rate */
uint32_t interface_format; /*!< digital camera interface format */
} dci_parameter_struct;
#define CCIR_PROGRESSIVE_MODE ((uint32_t)0x00000000U) /*!< CCIR progressive mode */
#define CCIR_INTERLACE_MODE DCI_CTL_CCMOD /*!< CCIR interlace mode */
#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */
#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */
#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */
#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8))
#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10))
#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
/* DCI interrupt constants definitions */
#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */
#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */
#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */
#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */
#define DCI_INT_EL BIT(4) /*!< end of line interrupt */
#define DCI_INT_F0 BIT(5) /*!< CCIR field 0 interrupt */
#define DCI_INT_F1 BIT(6) /*!< CCIR field 1 interrupt */
#define DCI_INT_COF BIT(7) /*!< CCIR change of field interrupt */
#define DCI_INT_CCE BIT(8) /*!< CCIR error interrupt */
/* DCI interrupt flag definitions */
#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */
#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */
#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */
#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */
#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */
#define DCI_INT_FLAG_F0 BIT(5) /*!< CCIR field 0 interrupt flag */
#define DCI_INT_FLAG_F1 BIT(6) /*!< CCIR field 1 interrupt flag */
#define DCI_INT_FLAG_COF BIT(7) /*!< CCIR change of field interrupt flag */
#define DCI_INT_FLAG_CCE BIT(8) /*!< CCIR error interrupt flag */
/* DCI flag definitions */
#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */
#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */
#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */
#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */
#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */
#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */
#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */
#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */
/* function declarations */
/* initialization functions */
/* DCI deinit */
void dci_deinit(void);
/* initialize DCI registers */
void dci_init(dci_parameter_struct *dci_struct);
/* enable DCI function */
void dci_enable(void);
/* disable DCI function */
void dci_disable(void);
/* enable DCI capture */
void dci_capture_enable(void);
/* disable DCI capture */
void dci_capture_disable(void);
/* enable DCI external vsync in CCIR progressive mode */
void dci_external_vsync_enable(void);
/* disable DCI external vsync in CCIR progressive mode */
void dci_external_vsync_disable(void);
/* enable DCI automatic error correction in CCIR interlaced mode */
void dci_automatic_error_correction_enable(void);
/* disable DCI automatic error correction in CCIR interlaced mode */
void dci_automatic_error_correction_disable(void);
/* enable DCI jpeg mode */
void dci_jpeg_enable(void);
/* disable DCI jpeg mode */
void dci_jpeg_disable(void);
/* function configuration */
/* enable cropping window function */
void dci_crop_window_enable(void);
/* disable cropping window function */
void dci_crop_window_disable(void);
/* CCIR enable */
void dci_ccir_enable(void);
/* CCIR disable */
void dci_ccir_disable(void);
/* CCIR mode select */
void dci_ccir_mode_select(uint32_t ccir_mode);
/* configure DCI cropping window */
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
/* enable embedded synchronous mode */
void dci_embedded_sync_enable(void);
/* disable embedded synchronous mode */
void dci_embedded_sync_disable(void);
/* configure synchronous codes in embedded synchronous mode */
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
/* configure synchronous codes unmask in embedded synchronous mode */
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
/* read DCI data register */
uint32_t dci_data_read(void);
/* interrupt & flag functions */
/* get specified flag */
FlagStatus dci_flag_get(uint32_t flag);
/* enable specified DCI interrupt */
void dci_interrupt_enable(uint32_t interrupt);
/* disable specified DCI interrupt */
void dci_interrupt_disable(uint32_t interrupt);
/* get specified interrupt flag */
FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
/* clear specified interrupt flag */
void dci_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H7XX_DCI_H */

1015
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dma.h Normal file
View File

File diff suppressed because it is too large Load Diff

110
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_edout.h Normal file
View File

@@ -0,0 +1,110 @@
/*!
\file gd32h7xx_edout.c
\brief definitions for the EDOUT
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_EDOUT_H
#define GD32H7XX_EDOUT_H
#include "gd32h7xx.h"
/* EDOUT definition */
#define EDOUT EDOUT_BASE /*!< EDOUT base address */
/* registers definitions */
#define EDOUT_CTL REG32((EDOUT) + 0x00000000U) /*!< EDOUT control register */
#define EDOUT_ENABLE REG32((EDOUT) + 0x00000004U) /*!< EDOUT enable register */
#define EDOUT_LOC REG32((EDOUT) + 0x00000008U) /*!< EDOUT location register */
#define EDOUT_OCNT REG32((EDOUT) + 0x0000000CU) /*!< EDOUT output counter register */
#define EDOUT_LCNT REG32((EDOUT) + 0x00000010U) /*!< EDOUT location counter register */
#define EDOUT_ZCR REG32((EDOUT) + 0x00000014U) /*!< EDOUT Z-phase configure register */
/* bits definitions */
/* EDOUT_CTL */
#define EDOUT_CTL_POL BIT(0) /*!< active polarity of the B-phase output signal selection */
/* EDOUT_ENABLE */
#define EDOUT_ENABLE_EDOUTEN BIT(0) /*!< EDOUT enable bit */
/* EDOUT_LOC */
#define EDOUT_LOC_LOCMAX BITS(0,15) /*!< maximum location value for one rotation */
/* EDOUT_OCNT */
#define EDOUT_OCNT_EDGC BITS(0,15) /*!< number of edges of the A-phase and the B-phase signal for the next update period */
#define EDOUT_OCNT_PDC BITS(16,31) /*!< phase difference between the A-phase and the B-phase signal for the next update period */
/* EDOUT_LCNT */
#define EDOUT_LCNT_LOCCNT BITS(0,15) /*!< current location value */
/* EDOUT_ZCR */
#define EDOUT_ZCR_ZOSP BITS(0,15) /*!< Z-phase output start location */
#define EDOUT_ZCR_ZOWH BITS(16,23) /*!< Z-phase output width */
#define EDOUT_ZCR_ZOMD BIT(24) /*!< Z-phase output mode */
/* constants definitions */
/* EDOUT_CTL */
#define EDOUT_POL_POSITIVE ((uint32_t)0x00000000U) /*!< active polarity is positive */
#define EDOUT_POL_NEGATIVE EDOUT_CTL_POL /*!< active polarity is negative */
/* EDOUT_ENABLE */
#define EDOUT_STATE_DISABLE ((uint32_t)0x00000000U) /*!< disable EDOUT */
#define EDOUT_STATE_ENABLE EDOUT_ENABLE_EDOUTEN /*!< enable EDOUT */
/* EDOUT_ZCR */
#define EDOUT_Z_OUTPUT_MODE0 ((uint32_t)0x00000000U) /*!< Z-phase output according to the current location */
#define EDOUT_Z_OUTPUT_MODE1 EDOUT_ZCR_ZOMD /*!< Z-phase output according to the number of edges */
/* function declarations */
/* deinitialize EDOUT */
void edout_deinit(void);
/* initialize EDOUT */
void edout_init(uint32_t pol, uint32_t max_loc, uint32_t cur_loc);
/* enable EDOUT */
void edout_enable(void);
/* disable EDOUT */
void edout_disable(void);
/* set B-phase active polarity */
void edout_polarity_config(uint32_t pol);
/* set the maximum location value for one rotation */
void edout_max_location_value_config(uint32_t max_loc);
/* update the output counter, used to set the phase difference and the number of edges for the next update period */
void edout_output_counter_update(int16_t num_edges, uint16_t phase_diff);
/* set the current location value */
void edout_current_location_config(uint32_t cur_loc);
/* get the current location value */
uint16_t edout_current_location_get(void);
/* configure Z-phase output mode */
void edout_z_output_mode_config(uint32_t mode);
/* configure Z-phase output start location and width */
void edout_z_output_start_loc_and_width_config(uint32_t start_loc, uint32_t width);
#endif /* GD32H7XX_EDOUT_H */

259
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_efuse.h Normal file
View File

@@ -0,0 +1,259 @@
/*!
\file gd32h7xx_efuse.h
\brief definitions for the EFUSE
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_EFUSE_H
#define GD32H7XX_EFUSE_H
#include "gd32h7xx.h"
/* EFUSE definitions */
#define EFUSE EFUSE_BASE /*!< EFUSE base address */
/* registers definitions */
#define EFUSE_CTL REG32(EFUSE + 0x00000000U) /*!< EFUSE control register */
#define EFUSE_ADDR REG32(EFUSE + 0x00000004U) /*!< EFUSE address register */
#define EFUSE_STAT REG32(EFUSE + 0x0000000CU) /*!< EFUSE status register */
#define EFUSE_STATC REG32(EFUSE + 0x00000010U) /*!< EFUSE status clear register */
#define EFUSE_USER_CTL REG32(EFUSE + 0x00000014U) /*!< EFUSE user control register */
#define EFUSE_MCU_RSV REG32(EFUSE + 0x00000018U) /*!< EFUSE MCU reserved register */
#define EFUSE_DP0 REG32(EFUSE + 0x0000001CU) /*!< EFUSE debug password register 0 */
#define EFUSE_DP1 REG32(EFUSE + 0x00000020U) /*!< EFUSE debug password register 1 */
#define EFUSE_AES_KEY0 REG32(EFUSE + 0x00000024U) /*!< EFUSE firmware AES key register 0 */
#define EFUSE_AES_KEY1 REG32(EFUSE + 0x00000028U) /*!< EFUSE firmware AES key register 1 */
#define EFUSE_AES_KEY2 REG32(EFUSE + 0x0000002CU) /*!< EFUSE firmware AES key register 2 */
#define EFUSE_AES_KEY3 REG32(EFUSE + 0x00000030U) /*!< EFUSE firmware AES key register3 */
#define EFUSE_USER_DATA0 REG32(EFUSE + 0x00000034U) /*!< EFUSE user data register 0 */
#define EFUSE_USER_DATA1 REG32(EFUSE + 0x00000038U) /*!< EFUSE user data register 1 */
#define EFUSE_USER_DATA2 REG32(EFUSE + 0x0000003CU) /*!< EFUSE user data register 2 */
#define EFUSE_USER_DATA3 REG32(EFUSE + 0x00000040U) /*!< EFUSE user data register 3 */
/* bits definitions */
/* EFUSE_CTL */
#define EFUSE_CTL_EFSTR BIT(0) /*!< start EFUSE operation */
#define EFUSE_CTL_EFRW BIT(1) /*!< selection of EFUSE operation */
#define EFUSE_CTL_MPVEN BIT(15) /*!< enable bit for program-voltage monitoring function */
#define EFUSE_CTL_IAERRIE BIT(16) /*!< enable bit for illegal access error interrupt */
#define EFUSE_CTL_PGIE BIT(17) /*!< enable bit for program complete interrupt */
#define EFUSE_CTL_RDIE BIT(18) /*!< enable bit for read complete interrupt */
#define EFUSE_CTL_PVIE BIT(19) /*!< enable bit for program voltage setting error interrupt */
#define EFUSE_CTL_AES_KEY_CRC BITS(24,31) /*!< 8-bits CRC calculation result value of AES key bits */
/* EFUSE_ADDR */
#define EFUSE_ADDR_EFADDR BITS(0,9) /*!< read or write EFUSE data start address */
#define EFUSE_ADDR_EFSIZE BITS(10,14) /*!< read or write EFUSE data size */
/* EFUSE_STAT */
#define EFUSE_STAT_IAERRIF BIT(0) /*!< illegal access error flag */
#define EFUSE_STAT_PGIF BIT(1) /*!< program complete flag */
#define EFUSE_STAT_RDIF BIT(2) /*!< read complete flag */
#define EFUSE_STAT_PVIF BIT(3) /*!< program voltage setting error flag */
#define EFUSE_STAT_LDO_RDY BIT(4) /*!< EFUSE LDO ready signal */
/* EFUSE_STATC */
#define EFUSE_STATC_IAERRIC BIT(0) /*!< clear bit for illegal access error interrupt */
#define EFUSE_STATC_PGIC BIT(1) /*!< clear bit for program complete interrupt flag */
#define EFUSE_STATC_RDIC BIT(2) /*!< clear bit for read complete interrupt flag */
#define EFUSE_STATC_PVIC BIT(3) /*!< clear bit for program voltage setting error interrupt flag */
/* EFUSE_USER_CTL */
#define EFUSE_USER_CTL_DPLK BIT(0) /*!< EFUSE_DP register lock bit */
#define EFUSE_USER_CTL_SCRLK BIT(1) /*!< secure-access area start/end address lock bit */
#define EFUSE_USER_CTL_UCLK BIT(2) /*!< low 16 bits of EFUSE_USER_CTL register lock bit */
#define EFUSE_USER_CTL_AESEN BIT(3) /*!< lock EFUSE_AES_KEY register and enable AES decrypt function */
#define EFUSE_USER_CTL_UDLK BIT(4) /*!< EFUSE_USER_DATA register lock bit */
#define EFUSE_USER_CTL_NDBG BITS(8,9) /*!< debug mode setting bit */
#define EFUSE_USER_CTL_JTAGNSW BIT(10) /*!< debugger select bit */
#define EFUSE_USER_CTL_SPC_L BIT(11) /*!< low security protection */
#define EFUSE_USER_CTL_SPC_H BIT(12) /*!< high security protection */
#define EFUSE_USER_CTL_SCR BIT(13) /*!< secure access mode enable bit */
#define EFUSE_USER_CTL_ESPI_START_MODE BITS(14,15) /*!< external SPI start mode */
#define EFUSE_USER_CTL_SCR_AREA_START BITS(16,23) /*!< secure-access area start address */
#define EFUSE_USER_CTL_SCR_AREA_END BITS(24,31) /*!< secure-access area end address */
/* EFUSE_MCU_RSV */
#define EFUSE_MCU_RSV_AESNCAU BIT(0) /*!< AES key available for CAU */
#define EFUSE_MCU_RSV_DISLFI BIT(6) /*!< disable bit for licensed firmware install (LFI) */
#define EFUSE_MCU_RSV_VFIMG BIT(7) /*!< enable bit for verify firmware image */
#define EFUSE_MCU_RSV_MCURSVLK BIT(8) /*!< lock bit for low 16 bits of EFUSE_MCU_RSV register */
#define EFUSE_MCU_RSV_DCRPLK BIT(9) /*!< lock bit for DCRP area start/end address */
#define EFUSE_MCU_RSV_MCU_RSV BITS(10,15) /*!< MCU reserved value */
#define EFUSE_MCU_RSV_DCRP_AREA_START BITS(16,23) /*!< DCRP area start address */
#define EFUSE_MCU_RSV_DCRP_AREA_END BITS(24,31) /*!< DCRP area end address */
/* EFUSE_DP */
#define EFUSE_DP_DP BITS(0,31) /*!< EFUSE Debug password value */
/* EFUSE_AES_KEY */
#define EFUSE_AES_KEY_AESKEY BITS(0,31) /*!< EFUSE AES key value */
/* EFUSE_USER_DATA */
#define EFUSE_USER_DATA_USERDATA BITS(0,31) /*!< EFUSE USER_DATA value */
/* constants definitions */
/* define the EFUSE bit position and its register index offset */
#define EFUSE_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define EFUSE_REG_VAL(offset) (REG32(EFUSE + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define EFUSE_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define EFUSE_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define EFUSE_REG_VAL2(offset) (REG32(EFUSE + ((uint32_t)(offset) >> 22)))
#define EFUSE_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define EFUSE_CTL_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
#define EFUSE_STAT_REG_OFFSET ((uint32_t)0x0000000CU) /*!< STAT register offset */
#define EFUSE_STATC_REG_OFFSET ((uint32_t)0x00000010U) /*!< STATC register offset */
/* EFUSE interrupt flags */
typedef enum {
EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 16U, EFUSE_STAT_REG_OFFSET, 0U), /*!< illegal access error interrupt flag */
EFUSE_INT_FLAG_PROGRAM_COMPLETE = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 17U, EFUSE_STAT_REG_OFFSET, 1U), /*!< programming operation completion interrupt flag */
EFUSE_INT_FLAG_READ_COMPLETE = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 18U, EFUSE_STAT_REG_OFFSET, 2U), /*!< read operation completion interrupt flag */
EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 19U, EFUSE_STAT_REG_OFFSET, 3U), /*!< program voltage setting error flag */
} efuse_interrupt_flag_enum;
/* EFUSE flag */
#define EFUSE_FLAG_LDO_READY EFUSE_STAT_LDO_RDY /*!< EFUSE LDO ready signal flag */
#define EFUSE_FLAG_ILLEGAL_ACCESS_ERR EFUSE_STAT_IAERRIF /*!< illegal access error flag */
#define EFUSE_FLAG_PROGRAM_COMPLETE EFUSE_STAT_PGIF /*!< programming operation completion flag */
#define EFUSE_FLAG_READ_COMPLETE EFUSE_STAT_RDIF /*!< read operation completion flag */
#define EFUSE_FLAG_PROGRAM_VOLTAGE_ERR EFUSE_STAT_PVIF /*!< program voltage setting error flag */
/* EFUSE flag clear */
#define EFUSE_FLAG_ILLEGAL_ACCESS_ERR_CLR EFUSE_STATC_IAERRIC /*!< clear illegal access error flag */
#define EFUSE_FLAG_PROGRAM_COMPLETE_CLR EFUSE_STATC_PGIC /*!< clear programming operation completion flag */
#define EFUSE_FLAG_READ_COMPLETE_CLR EFUSE_STATC_RDIC /*!< clear read operation completion flag */
#define EFUSE_FLAG_PROGRAM_VOLTAGE_ERR_CLR EFUSE_STATC_PVIC /*!< clear program voltage setting error interrupt flag */
/* EFUSE interrupt enable */
#define EFUSE_INT_ILLEGAL_ACCESS_ERR EFUSE_CTL_IAERRIE /*!< illegal access error interrupt enable */
#define EFUSE_INT_PROGRAM_COMPLETE EFUSE_CTL_PGIE /*!< programming operation completion interrupt enable */
#define EFUSE_INT_READ_COMPLETE EFUSE_CTL_RDIE /*!< read operation completion interrupt enable */
#define EFUSE_INT_PROGRAM_VOLTAGE_ERR EFUSE_CTL_PVIE /*!< program voltage setting error interrupt enable */
/* EFUSE interrupt flag clear */
#define EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR_CLR EFUSE_STATC_IAERRIC /*!< clear illegal access error interrupt flag */
#define EFUSE_INT_FLAG_PROGRAM_COMPLETE_CLR EFUSE_STATC_PGIC /*!< clear programming operation completion interrupt flag */
#define EFUSE_INT_FLAG_READ_COMPLETE_CLR EFUSE_STATC_RDIC /*!< clear read operation completion interrupt flag */
#define EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR_CLR EFUSE_STATC_PVIC /*!< clear program voltage setting error interrupt flag */
/* EFUSE system parameter size enum, in byte unit */
typedef enum {
USER_CTL_SIZE = 4U, /*!< user control parameter size */
MCU_RESERVED_SIZE = 4U, /*!< MCU reserved parameter size */
DP_SIZE = 8U, /*!< debug password parameter size */
AES_KEY_SIZE = 16U, /*!< AES key parameter size */
USER_DATA_SIZE = 16U, /*!< user data parameter size */
} efuse_system_para_size_enum;
/* EFUSE system parameter index */
typedef enum {
USER_CTL_IDX = 0U, /*!< index of user control parameter */
MCU_RESERVED_IDX = 1U, /*!< index of MCU reserved parameter */
DP_IDX = 2U, /*!< index of debug password parameter */
AES_KEY_IDX = 3U, /*!< index of AES key parameter */
USER_DATA_IDX = 4U, /*!< index of user data parameter */
} efuse_system_para_index_enum;
/* EFUSE state */
typedef enum {
EFUSE_READY = 0U, /*!< operation has been completed */
EFUSE_BUSY, /*!< operation is in progress */
EFUSE_IAERR, /*!< illegal access error */
EFUSE_PVERR, /*!< program voltage setting error */
EFUSE_TOERR, /*!< timeout error */
} efuse_state_enum;
/* EFADDR of EFUSE system parameters */
#define USER_CTL_EFADDR ((uint32_t)0x00000000U) /*!< user control parameter start address */
#define MCU_RESERVED_EFADDR ((uint32_t)0x00000020U) /*!< MCU reserved parameter start address */
#define DP_EFADDR ((uint32_t)0x00000040U) /*!< debug password parameter start address */
#define AES_KEY_EFADDR ((uint32_t)0x00000080U) /*!< AES key parameter start address */
#define USER_DATA_EFADDR ((uint32_t)0x00000100U) /*!< user data parameter start address */
#define MAX_EFADDR ((uint32_t)0x0000017FU) /*!< max efuse address */
#define EFUSE_PARA_CNT ((uint32_t)0x00000005U) /*!< the count of system parameters in EFUSE */
/* EFUSE parameters' register address */
#define EFUSE_USER_CTL_REG_ADDR (EFUSE + 0x00000014U) /*!< user control register address */
#define EFUSE_MCU_RSV_REG_ADDR (EFUSE + 0x00000018U) /*!< MCU reserved register address */
#define EFUSE_DP_REG_ADDR (EFUSE + 0x0000001CU) /*!< debug password register address */
#define EFUSE_AES_KEY_REG_ADDR (EFUSE + 0x00000024U) /*!< AES key register address */
#define EFUSE_USER_DATA_REG_ADDR (EFUSE + 0x00000034U) /*!< user data register address */
/* function declarations */
/* EFUSE operation functions */
/* read system parameters from EFUSE macro to registers */
ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[]);
/* program register values to EFUSE macro system parameters */
ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf);
/* program all user control parameters */
ErrStatus efuse_user_control_write(uint8_t *buf);
/* program all MCU reserved parameters */
ErrStatus efuse_mcu_reserved_write(uint8_t *buf);
/* program all debug password parameters */
ErrStatus efuse_dp_write(uint8_t *buf);
/* program all AES key parameters */
ErrStatus efuse_aes_key_write(uint8_t *buf);
/* program all user data parameters */
ErrStatus efuse_user_data_write(uint8_t *buf);
/* FMC universal functions */
/* get 8-bits CRC calculation result value of AES key */
uint8_t efuse_aes_key_crc_get(void);
/* enable monitor program voltage function */
void efuse_monitor_program_voltage_enable(void);
/* disable monitor program voltage function */
void efuse_monitor_program_voltage_disable(void);
/* get monitor program voltage function */
FlagStatus efuse_monitor_program_voltage_get(void);
/* get ldo ready signal */
FlagStatus efuse_ldo_ready_get(void);
/* flag and interrupt functions */
/* check EFUSE flag is set or not */
FlagStatus efuse_flag_get(uint32_t flag);
/* clear EFUSE pending flag */
void efuse_flag_clear(uint32_t flag);
/* enable EFUSE interrupt */
void efuse_interrupt_enable(uint32_t interrupt);
/* disable EFUSE interrupt */
void efuse_interrupt_disable(uint32_t interrupt);
/* check EFUSE interrupt flag is set or not */
FlagStatus efuse_interrupt_flag_get(uint32_t int_flag);
/* clear EFUSE pending interrupt flag */
void efuse_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H7XX_EFUSE_H */

1677
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_enet.h Normal file
View File

File diff suppressed because it is too large Load Diff

638
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_exmc.h Normal file
View File

File diff suppressed because it is too large Load Diff

413
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_exti.h Normal file
View File

@@ -0,0 +1,413 @@
/*!
\file gd32h7xx_exti.h
\brief definitions for the EXTI
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_EXTI_H
#define GD32H7XX_EXTI_H
#include "gd32h7xx.h"
/* EXTI definition */
#define EXTI EXTI_BASE /*!< EXTI base address */
/* registers definitions */
#define EXTI_INTEN0 REG32(EXTI + 0x00000000U) /*!< interrupt enable register 0 */
#define EXTI_EVEN0 REG32(EXTI + 0x00000004U) /*!< event enable register 0 */
#define EXTI_RTEN0 REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register 0 */
#define EXTI_FTEN0 REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register 0 */
#define EXTI_SWIEV0 REG32(EXTI + 0x00000010U) /*!< software interrupt event register 0 */
#define EXTI_PD0 REG32(EXTI + 0x00000014U) /*!< pending register 0 */
#define EXTI_INTEN1 REG32(EXTI + 0x00000018U) /*!< interrupt enable register 1 */
#define EXTI_EVEN1 REG32(EXTI + 0x0000001CU) /*!< event enable register 1 */
#define EXTI_RTEN1 REG32(EXTI + 0x00000020U) /*!< rising edge trigger enable register 1 */
#define EXTI_FTEN1 REG32(EXTI + 0x00000024U) /*!< falling edge trigger enable register 1 */
#define EXTI_SWIEV1 REG32(EXTI + 0x00000028U) /*!< software interrupt event register 1 */
#define EXTI_PD1 REG32(EXTI + 0x0000002CU) /*!< pending register 1 */
/* bits definitions */
/* EXTI_INTEN0 */
#define EXTI_INTEN0_INTEN0 BIT(0) /*!< interrupt from line 0 */
#define EXTI_INTEN0_INTEN1 BIT(1) /*!< interrupt from line 1 */
#define EXTI_INTEN0_INTEN2 BIT(2) /*!< interrupt from line 2 */
#define EXTI_INTEN0_INTEN3 BIT(3) /*!< interrupt from line 3 */
#define EXTI_INTEN0_INTEN4 BIT(4) /*!< interrupt from line 4 */
#define EXTI_INTEN0_INTEN5 BIT(5) /*!< interrupt from line 5 */
#define EXTI_INTEN0_INTEN6 BIT(6) /*!< interrupt from line 6 */
#define EXTI_INTEN0_INTEN7 BIT(7) /*!< interrupt from line 7 */
#define EXTI_INTEN0_INTEN8 BIT(8) /*!< interrupt from line 8 */
#define EXTI_INTEN0_INTEN9 BIT(9) /*!< interrupt from line 9 */
#define EXTI_INTEN0_INTEN10 BIT(10) /*!< interrupt from line 10 */
#define EXTI_INTEN0_INTEN11 BIT(11) /*!< interrupt from line 11 */
#define EXTI_INTEN0_INTEN12 BIT(12) /*!< interrupt from line 12 */
#define EXTI_INTEN0_INTEN13 BIT(13) /*!< interrupt from line 13 */
#define EXTI_INTEN0_INTEN14 BIT(14) /*!< interrupt from line 14 */
#define EXTI_INTEN0_INTEN15 BIT(15) /*!< interrupt from line 15 */
#define EXTI_INTEN0_INTEN16 BIT(16) /*!< interrupt from line 16 */
#define EXTI_INTEN0_INTEN17 BIT(17) /*!< interrupt from line 17 */
#define EXTI_INTEN0_INTEN18 BIT(18) /*!< interrupt from line 18 */
#define EXTI_INTEN0_INTEN19 BIT(19) /*!< interrupt from line 19 */
#define EXTI_INTEN0_INTEN20 BIT(20) /*!< interrupt from line 20 */
#define EXTI_INTEN0_INTEN21 BIT(21) /*!< interrupt from line 21 */
#define EXTI_INTEN0_INTEN22 BIT(22) /*!< interrupt from line 22 */
#define EXTI_INTEN0_INTEN23 BIT(23) /*!< interrupt from line 23 */
#define EXTI_INTEN0_INTEN24 BIT(24) /*!< interrupt from line 24 */
#define EXTI_INTEN0_INTEN25 BIT(25) /*!< interrupt from line 25 */
#define EXTI_INTEN0_INTEN26 BIT(26) /*!< interrupt from line 26 */
#define EXTI_INTEN0_INTEN27 BIT(27) /*!< interrupt from line 27 */
#define EXTI_INTEN0_INTEN28 BIT(28) /*!< interrupt from line 28 */
#define EXTI_INTEN0_INTEN29 BIT(29) /*!< interrupt from line 29 */
#define EXTI_INTEN0_INTEN30 BIT(30) /*!< interrupt from line 30 */
#define EXTI_INTEN0_INTEN31 BIT(31) /*!< interrupt from line 31 */
/* EXTI_EVEN0 */
#define EXTI_EVEN0_EVEN0 BIT(0) /*!< event from line 0 */
#define EXTI_EVEN0_EVEN1 BIT(1) /*!< event from line 1 */
#define EXTI_EVEN0_EVEN2 BIT(2) /*!< event from line 2 */
#define EXTI_EVEN0_EVEN3 BIT(3) /*!< event from line 3 */
#define EXTI_EVEN0_EVEN4 BIT(4) /*!< event from line 4 */
#define EXTI_EVEN0_EVEN5 BIT(5) /*!< event from line 5 */
#define EXTI_EVEN0_EVEN6 BIT(6) /*!< event from line 6 */
#define EXTI_EVEN0_EVEN7 BIT(7) /*!< event from line 7 */
#define EXTI_EVEN0_EVEN8 BIT(8) /*!< event from line 8 */
#define EXTI_EVEN0_EVEN9 BIT(9) /*!< event from line 9 */
#define EXTI_EVEN0_EVEN10 BIT(10) /*!< event from line 10 */
#define EXTI_EVEN0_EVEN11 BIT(11) /*!< event from line 11 */
#define EXTI_EVEN0_EVEN12 BIT(12) /*!< event from line 12 */
#define EXTI_EVEN0_EVEN13 BIT(13) /*!< event from line 13 */
#define EXTI_EVEN0_EVEN14 BIT(14) /*!< event from line 14 */
#define EXTI_EVEN0_EVEN15 BIT(15) /*!< event from line 15 */
#define EXTI_EVEN0_EVEN16 BIT(16) /*!< event from line 16 */
#define EXTI_EVEN0_EVEN17 BIT(17) /*!< event from line 17 */
#define EXTI_EVEN0_EVEN18 BIT(18) /*!< event from line 18 */
#define EXTI_EVEN0_EVEN19 BIT(19) /*!< event from line 19 */
#define EXTI_EVEN0_EVEN20 BIT(20) /*!< event from line 20 */
#define EXTI_EVEN0_EVEN21 BIT(21) /*!< event from line 21 */
#define EXTI_EVEN0_EVEN22 BIT(22) /*!< event from line 22 */
#define EXTI_EVEN0_EVEN23 BIT(23) /*!< event from line 23 */
#define EXTI_EVEN0_EVEN24 BIT(24) /*!< event from line 24 */
#define EXTI_EVEN0_EVEN25 BIT(25) /*!< event from line 25 */
#define EXTI_EVEN0_EVEN26 BIT(26) /*!< event from line 26 */
#define EXTI_EVEN0_EVEN27 BIT(27) /*!< event from line 27 */
#define EXTI_EVEN0_EVEN28 BIT(28) /*!< event from line 28 */
#define EXTI_EVEN0_EVEN29 BIT(29) /*!< event from line 29 */
#define EXTI_EVEN0_EVEN30 BIT(30) /*!< event from line 30 */
#define EXTI_EVEN0_EVEN31 BIT(31) /*!< event from line 31 */
/* EXTI_RTEN0 */
#define EXTI_RTEN0_RTEN0 BIT(0) /*!< rising edge from line 0 */
#define EXTI_RTEN0_RTEN1 BIT(1) /*!< rising edge from line 1 */
#define EXTI_RTEN0_RTEN2 BIT(2) /*!< rising edge from line 2 */
#define EXTI_RTEN0_RTEN3 BIT(3) /*!< rising edge from line 3 */
#define EXTI_RTEN0_RTEN4 BIT(4) /*!< rising edge from line 4 */
#define EXTI_RTEN0_RTEN5 BIT(5) /*!< rising edge from line 5 */
#define EXTI_RTEN0_RTEN6 BIT(6) /*!< rising edge from line 6 */
#define EXTI_RTEN0_RTEN7 BIT(7) /*!< rising edge from line 7 */
#define EXTI_RTEN0_RTEN8 BIT(8) /*!< rising edge from line 8 */
#define EXTI_RTEN0_RTEN9 BIT(9) /*!< rising edge from line 9 */
#define EXTI_RTEN0_RTEN10 BIT(10) /*!< rising edge from line 10 */
#define EXTI_RTEN0_RTEN11 BIT(11) /*!< rising edge from line 11 */
#define EXTI_RTEN0_RTEN12 BIT(12) /*!< rising edge from line 12 */
#define EXTI_RTEN0_RTEN13 BIT(13) /*!< rising edge from line 13 */
#define EXTI_RTEN0_RTEN14 BIT(14) /*!< rising edge from line 14 */
#define EXTI_RTEN0_RTEN15 BIT(15) /*!< rising edge from line 15 */
#define EXTI_RTEN0_RTEN16 BIT(16) /*!< rising edge from line 16 */
#define EXTI_RTEN0_RTEN17 BIT(17) /*!< rising edge from line 17 */
#define EXTI_RTEN0_RTEN18 BIT(18) /*!< rising edge from line 18 */
#define EXTI_RTEN0_RTEN19 BIT(19) /*!< rising edge from line 19 */
#define EXTI_RTEN0_RTEN20 BIT(20) /*!< rising edge from line 20 */
#define EXTI_RTEN0_RTEN21 BIT(21) /*!< rising edge from line 21 */
#define EXTI_RTEN0_RTEN22 BIT(22) /*!< rising edge from line 22 */
#define EXTI_RTEN0_RTEN23 BIT(23) /*!< rising edge from line 23 */
#define EXTI_RTEN0_RTEN24 BIT(24) /*!< rising edge from line 24 */
#define EXTI_RTEN0_RTEN25 BIT(25) /*!< rising edge from line 25 */
#define EXTI_RTEN0_RTEN26 BIT(26) /*!< rising edge from line 26 */
#define EXTI_RTEN0_RTEN27 BIT(27) /*!< rising edge from line 27 */
#define EXTI_RTEN0_RTEN28 BIT(28) /*!< rising edge from line 28 */
#define EXTI_RTEN0_RTEN29 BIT(29) /*!< rising edge from line 29 */
#define EXTI_RTEN0_RTEN30 BIT(30) /*!< rising edge from line 30 */
#define EXTI_RTEN0_RTEN31 BIT(31) /*!< rising edge from line 31 */
/* EXTI_FTEN0 */
#define EXTI_FTEN0_FTEN0 BIT(0) /*!< falling edge from line 0 */
#define EXTI_FTEN0_FTEN1 BIT(1) /*!< falling edge from line 1 */
#define EXTI_FTEN0_FTEN2 BIT(2) /*!< falling edge from line 2 */
#define EXTI_FTEN0_FTEN3 BIT(3) /*!< falling edge from line 3 */
#define EXTI_FTEN0_FTEN4 BIT(4) /*!< falling edge from line 4 */
#define EXTI_FTEN0_FTEN5 BIT(5) /*!< falling edge from line 5 */
#define EXTI_FTEN0_FTEN6 BIT(6) /*!< falling edge from line 6 */
#define EXTI_FTEN0_FTEN7 BIT(7) /*!< falling edge from line 7 */
#define EXTI_FTEN0_FTEN8 BIT(8) /*!< falling edge from line 8 */
#define EXTI_FTEN0_FTEN9 BIT(9) /*!< falling edge from line 9 */
#define EXTI_FTEN0_FTEN10 BIT(10) /*!< falling edge from line 10 */
#define EXTI_FTEN0_FTEN11 BIT(11) /*!< falling edge from line 11 */
#define EXTI_FTEN0_FTEN12 BIT(12) /*!< falling edge from line 12 */
#define EXTI_FTEN0_FTEN13 BIT(13) /*!< falling edge from line 13 */
#define EXTI_FTEN0_FTEN14 BIT(14) /*!< falling edge from line 14 */
#define EXTI_FTEN0_FTEN15 BIT(15) /*!< falling edge from line 15 */
#define EXTI_FTEN0_FTEN16 BIT(16) /*!< falling edge from line 16 */
#define EXTI_FTEN0_FTEN17 BIT(17) /*!< falling edge from line 17 */
#define EXTI_FTEN0_FTEN18 BIT(18) /*!< falling edge from line 18 */
#define EXTI_FTEN0_FTEN19 BIT(19) /*!< falling edge from line 19 */
#define EXTI_FTEN0_FTEN20 BIT(20) /*!< falling edge from line 20 */
#define EXTI_FTEN0_FTEN21 BIT(21) /*!< falling edge from line 21 */
#define EXTI_FTEN0_FTEN22 BIT(22) /*!< falling edge from line 22 */
#define EXTI_FTEN0_FTEN23 BIT(23) /*!< falling edge from line 23 */
#define EXTI_FTEN0_FTEN24 BIT(24) /*!< falling edge from line 24 */
#define EXTI_FTEN0_FTEN25 BIT(25) /*!< falling edge from line 25 */
#define EXTI_FTEN0_FTEN26 BIT(26) /*!< falling edge from line 26 */
#define EXTI_FTEN0_FTEN27 BIT(27) /*!< falling edge from line 27 */
#define EXTI_FTEN0_FTEN28 BIT(28) /*!< falling edge from line 28 */
#define EXTI_FTEN0_FTEN29 BIT(29) /*!< falling edge from line 29 */
#define EXTI_FTEN0_FTEN30 BIT(30) /*!< falling edge from line 30 */
#define EXTI_FTEN0_FTEN31 BIT(31) /*!< falling edge from line 31 */
/* EXTI_SWIEV0 */
#define EXTI_SWIEV0_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
#define EXTI_SWIEV0_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
#define EXTI_SWIEV0_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
#define EXTI_SWIEV0_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
#define EXTI_SWIEV0_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
#define EXTI_SWIEV0_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
#define EXTI_SWIEV0_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
#define EXTI_SWIEV0_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
#define EXTI_SWIEV0_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
#define EXTI_SWIEV0_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
#define EXTI_SWIEV0_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
#define EXTI_SWIEV0_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
#define EXTI_SWIEV0_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
#define EXTI_SWIEV0_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
#define EXTI_SWIEV0_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
#define EXTI_SWIEV0_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
#define EXTI_SWIEV0_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
#define EXTI_SWIEV0_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
#define EXTI_SWIEV0_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
#define EXTI_SWIEV0_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
#define EXTI_SWIEV0_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */
#define EXTI_SWIEV0_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
#define EXTI_SWIEV0_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
#define EXTI_SWIEV0_SWIEV23 BIT(23) /*!< software interrupt/event request from line 23 */
#define EXTI_SWIEV0_SWIEV24 BIT(24) /*!< software interrupt/event request from line 24 */
#define EXTI_SWIEV0_SWIEV25 BIT(25) /*!< software interrupt/event request from line 25 */
#define EXTI_SWIEV0_SWIEV26 BIT(26) /*!< software interrupt/event request from line 26 */
#define EXTI_SWIEV0_SWIEV27 BIT(27) /*!< software interrupt/event request from line 27 */
#define EXTI_SWIEV0_SWIEV28 BIT(28) /*!< software interrupt/event request from line 28 */
#define EXTI_SWIEV0_SWIEV29 BIT(29) /*!< software interrupt/event request from line 29 */
#define EXTI_SWIEV0_SWIEV30 BIT(30) /*!< software interrupt/event request from line 30 */
#define EXTI_SWIEV0_SWIEV31 BIT(31) /*!< software interrupt/event request from line 31 */
/* EXTI_PD0 */
#define EXTI_PD0_PD0 BIT(0) /*!< interrupt pending status from line 0 */
#define EXTI_PD0_PD1 BIT(1) /*!< interrupt pending status from line 1 */
#define EXTI_PD0_PD2 BIT(2) /*!< interrupt pending status from line 2 */
#define EXTI_PD0_PD3 BIT(3) /*!< interrupt pending status from line 3 */
#define EXTI_PD0_PD4 BIT(4) /*!< interrupt pending status from line 4 */
#define EXTI_PD0_PD5 BIT(5) /*!< interrupt pending status from line 5 */
#define EXTI_PD0_PD6 BIT(6) /*!< interrupt pending status from line 6 */
#define EXTI_PD0_PD7 BIT(7) /*!< interrupt pending status from line 7 */
#define EXTI_PD0_PD8 BIT(8) /*!< interrupt pending status from line 8 */
#define EXTI_PD0_PD9 BIT(9) /*!< interrupt pending status from line 9 */
#define EXTI_PD0_PD10 BIT(10) /*!< interrupt pending status from line 10 */
#define EXTI_PD0_PD11 BIT(11) /*!< interrupt pending status from line 11 */
#define EXTI_PD0_PD12 BIT(12) /*!< interrupt pending status from line 12 */
#define EXTI_PD0_PD13 BIT(13) /*!< interrupt pending status from line 13 */
#define EXTI_PD0_PD14 BIT(14) /*!< interrupt pending status from line 14 */
#define EXTI_PD0_PD15 BIT(15) /*!< interrupt pending status from line 15 */
#define EXTI_PD0_PD16 BIT(16) /*!< interrupt pending status from line 16 */
#define EXTI_PD0_PD17 BIT(17) /*!< interrupt pending status from line 17 */
#define EXTI_PD0_PD18 BIT(18) /*!< interrupt pending status from line 18 */
#define EXTI_PD0_PD19 BIT(19) /*!< interrupt pending status from line 19 */
#define EXTI_PD0_PD20 BIT(20) /*!< interrupt pending status from line 20 */
#define EXTI_PD0_PD21 BIT(21) /*!< interrupt pending status from line 21 */
#define EXTI_PD0_PD22 BIT(22) /*!< interrupt pending status from line 22 */
#define EXTI_PD0_PD23 BIT(23) /*!< interrupt pending status from line 23 */
#define EXTI_PD0_PD24 BIT(24) /*!< interrupt pending status from line 24 */
#define EXTI_PD0_PD25 BIT(25) /*!< interrupt pending status from line 25 */
#define EXTI_PD0_PD26 BIT(26) /*!< interrupt pending status from line 26 */
#define EXTI_PD0_PD27 BIT(27) /*!< interrupt pending status from line 27 */
#define EXTI_PD0_PD28 BIT(28) /*!< interrupt pending status from line 28 */
#define EXTI_PD0_PD29 BIT(29) /*!< interrupt pending status from line 29 */
#define EXTI_PD0_PD30 BIT(30) /*!< interrupt pending status from line 30 */
#define EXTI_PD0_PD31 BIT(31) /*!< interrupt pending status from line 31 */
/* EXTI_INTEN1 */
#define EXTI_INTEN1_INTEN32 BIT(0) /*!< interrupt from line 32 */
#define EXTI_INTEN1_INTEN33 BIT(1) /*!< interrupt from line 33 */
#define EXTI_INTEN1_INTEN34 BIT(2) /*!< interrupt from line 34 */
#define EXTI_INTEN1_INTEN35 BIT(3) /*!< interrupt from line 35 */
#define EXTI_INTEN1_INTEN36 BIT(4) /*!< interrupt from line 36 */
#define EXTI_INTEN1_INTEN37 BIT(5) /*!< interrupt from line 37 */
/* EXTI_EVEN1 */
#define EXTI_EVEN1_EVEN32 BIT(0) /*!< event from line 32 */
#define EXTI_EVEN1_EVEN33 BIT(1) /*!< event from line 33 */
#define EXTI_EVEN1_EVEN34 BIT(2) /*!< event from line 34 */
#define EXTI_EVEN1_EVEN35 BIT(3) /*!< event from line 35 */
#define EXTI_EVEN1_EVEN36 BIT(4) /*!< event from line 36 */
#define EXTI_EVEN1_EVEN37 BIT(5) /*!< event from line 37 */
/* EXTI_RTEN1 */
#define EXTI_RTEN1_RTEN32 BIT(0) /*!< rising edge from line 32 */
#define EXTI_RTEN1_RTEN33 BIT(1) /*!< rising edge from line 33 */
#define EXTI_RTEN1_RTEN34 BIT(2) /*!< rising edge from line 34 */
#define EXTI_RTEN1_RTEN35 BIT(3) /*!< rising edge from line 35 */
#define EXTI_RTEN1_RTEN36 BIT(4) /*!< rising edge from line 36 */
#define EXTI_RTEN1_RTEN37 BIT(5) /*!< rising edge from line 37 */
/* EXTI_FTEN1 */
#define EXTI_FTEN1_FTEN32 BIT(0) /*!< falling edge from line 32 */
#define EXTI_FTEN1_FTEN33 BIT(1) /*!< falling edge from line 33 */
#define EXTI_FTEN1_FTEN34 BIT(2) /*!< falling edge from line 34 */
#define EXTI_FTEN1_FTEN35 BIT(3) /*!< falling edge from line 35 */
#define EXTI_FTEN1_FTEN36 BIT(4) /*!< falling edge from line 36 */
#define EXTI_FTEN1_FTEN37 BIT(5) /*!< falling edge from line 37 */
/* EXTI_SWIEV1 */
#define EXTI_SWIEV1_SWIEV32 BIT(0) /*!< software interrupt/event request from line 32 */
#define EXTI_SWIEV1_SWIEV33 BIT(1) /*!< software interrupt/event request from line 33 */
#define EXTI_SWIEV1_SWIEV34 BIT(2) /*!< software interrupt/event request from line 34 */
#define EXTI_SWIEV1_SWIEV35 BIT(3) /*!< software interrupt/event request from line 35 */
#define EXTI_SWIEV1_SWIEV36 BIT(4) /*!< software interrupt/event request from line 36 */
#define EXTI_SWIEV1_SWIEV37 BIT(5) /*!< software interrupt/event request from line 37 */
/* EXTI_PD1 */
#define EXTI_PD1_PD32 BIT(0) /*!< interrupt pending status from line 32 */
#define EXTI_PD1_PD33 BIT(1) /*!< interrupt pending status from line 33 */
#define EXTI_PD1_PD34 BIT(2) /*!< interrupt pending status from line 34 */
#define EXTI_PD1_PD35 BIT(3) /*!< interrupt pending status from line 35 */
#define EXTI_PD1_PD36 BIT(4) /*!< interrupt pending status from line 36 */
#define EXTI_PD1_PD37 BIT(5) /*!< interrupt pending status from line 37 */
/* constants definitions */
/* define the EXTI bit position and its register group index offset */
#define EXTI_GROUPIDX_BIT(groupidx, bitpos) (((uint32_t)(groupidx) << 8U) | (uint32_t)(bitpos))
#define EXTI_REG_VAL(linex) (EXTI + ((uint32_t)(linex) >> 8U))
#define EXTI_BIT_POS(linex) BIT((uint32_t)(linex) & 0x1FU)
/* define the EXTI register groups*/
#define EXTI_GROUP0_OFFSET 0x00000000U /*!< the index offset of EXTI group0 */
#define EXTI_GROUP1_OFFSET 0x00000018U /*!< the index offset of EXTI group1 */
/* define the registers in the group*/
#define EXTI_INTEN(exti_group) REG32((uint32_t)(exti_group) + 0x00000000U) /*!< the index offset of register INTEN in the registe group */
#define EXTI_EVEN(exti_group) REG32((uint32_t)(exti_group) + 0x00000004U) /*!< the index offset of register EVEN in the registe group */
#define EXTI_RTEN(exti_group) REG32((uint32_t)(exti_group) + 0x00000008U) /*!< the index offset of register RTEN in the registe group */
#define EXTI_FTEN(exti_group) REG32((uint32_t)(exti_group) + 0x0000000CU) /*!< the index offset of register FTEN in the registe group */
#define EXTI_SWIEV(exti_group) REG32((uint32_t)(exti_group) + 0x00000010U) /*!< the index offset of register SWIEV in the registe group */
#define EXTI_PD(exti_group) REG32((uint32_t)(exti_group) + 0x00000014U) /*!< the index offset of register PD in the registe group */
/* EXTI line number */
typedef enum {
EXTI_0 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 0U), /*!< EXTI line 0 */
EXTI_1 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 1U), /*!< EXTI line 1 */
EXTI_2 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 2U), /*!< EXTI line 2 */
EXTI_3 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 3U), /*!< EXTI line 3 */
EXTI_4 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 4U), /*!< EXTI line 4 */
EXTI_5 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 5U), /*!< EXTI line 5 */
EXTI_6 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 6U), /*!< EXTI line 6 */
EXTI_7 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 7U), /*!< EXTI line 7 */
EXTI_8 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 8U), /*!< EXTI line 8 */
EXTI_9 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 9U), /*!< EXTI line 9 */
EXTI_10 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 10U), /*!< EXTI line 10 */
EXTI_11 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 11U), /*!< EXTI line 11 */
EXTI_12 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 12U), /*!< EXTI line 12 */
EXTI_13 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 13U), /*!< EXTI line 13 */
EXTI_14 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 14U), /*!< EXTI line 14 */
EXTI_15 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 15U), /*!< EXTI line 15 */
EXTI_16 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 16U), /*!< EXTI line 16 */
EXTI_17 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 17U), /*!< EXTI line 17 */
EXTI_18 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 18U), /*!< EXTI line 18 */
EXTI_19 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 19U), /*!< EXTI line 19 */
EXTI_20 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 20U), /*!< EXTI line 20 */
EXTI_21 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 21U), /*!< EXTI line 21 */
EXTI_22 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 22U), /*!< EXTI line 22 */
EXTI_23 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 23U), /*!< EXTI line 23 */
EXTI_24 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 24U), /*!< EXTI line 24 */
EXTI_25 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 25U), /*!< EXTI line 25 */
EXTI_26 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 26U), /*!< EXTI line 26 */
EXTI_27 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 27U), /*!< EXTI line 27 */
EXTI_28 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 28U), /*!< EXTI line 28 */
EXTI_29 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 29U), /*!< EXTI line 29 */
EXTI_30 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 30U), /*!< EXTI line 30 */
EXTI_31 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 31U), /*!< EXTI line 31 */
EXTI_32 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 32U), /*!< EXTI line 32 */
EXTI_33 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 33U), /*!< EXTI line 33 */
EXTI_34 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 34U), /*!< EXTI line 34 */
EXTI_35 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 35U), /*!< EXTI line 35 */
EXTI_36 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 36U), /*!< EXTI line 36 */
EXTI_37 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 37U) /*!< EXTI line 37 */
} exti_line_enum;
/* external interrupt and event */
typedef enum {
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */
} exti_mode_enum;
/* interrupt and event trigger mode */
typedef enum {
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
} exti_trig_type_enum;
/* function declarations */
/* initialization, EXTI lines configuration functions */
/* deinitialize the EXTI */
void exti_deinit(void);
/* initialize the EXTI line x */
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
/* enable the interrupts from EXTI line x */
void exti_interrupt_enable(exti_line_enum linex);
/* disable the interrupts from EXTI line x */
void exti_interrupt_disable(exti_line_enum linex);
/* enable the events from EXTI line x */
void exti_event_enable(exti_line_enum linex);
/* disable the events from EXTI line x */
void exti_event_disable(exti_line_enum linex);
/* enable the software interrupt event from EXTI line x */
void exti_software_interrupt_enable(exti_line_enum linex);
/* disable the software interrupt event from EXTI line x */
void exti_software_interrupt_disable(exti_line_enum linex);
/* interrupt & flag functions */
/* get EXTI line x interrupt pending flag */
FlagStatus exti_flag_get(exti_line_enum linex);
/* clear EXTI line x interrupt pending flag */
void exti_flag_clear(exti_line_enum linex);
/* get EXTI line x interrupt pending flag */
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
/* clear EXTI line x interrupt pending flag */
void exti_interrupt_flag_clear(exti_line_enum linex);
#endif /* GD32H7XX_EXTI_H */

268
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fac.h Normal file
View File

@@ -0,0 +1,268 @@
/*!
\file gd32h7xx_fac.c
\brief definitions for the FAC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_FAC_H
#define GD32H7XX_FAC_H
#include "gd32h7xx.h"
/* FAC definitions */
#define FAC FAC_BASE /*!< FAC base address */
#define REG16_INT(addr) (*(volatile int16_t *)(uint32_t)(addr))
#define REG32_FLOAT(addr) (*(volatile float *)(uint32_t)(addr))
/* registers definitions */
#define FAC_X0BCFG REG32((FAC) + 0x00000000U) /*!< FAC X0 buffer configure register */
#define FAC_X1BCFG REG32((FAC) + 0x00000004U) /*!< FAC X1 buffer configure register */
#define FAC_YBCFG REG32((FAC) + 0x00000008U) /*!< FAC Y buffer configure register */
#define FAC_PARACFG REG32((FAC) + 0x0000000CU) /*!< FAC Parameter configure register */
#define FAC_CTL REG32((FAC) + 0x00000010U) /*!< FAC Control register */
#define FAC_STAT REG32((FAC) + 0x00000014U) /*!< FAC Status register */
#define FAC_WDATA REG32((FAC) + 0x00000018U) /*!< FAC write data register */
#define FAC_RDATA REG32((FAC) + 0x0000001CU) /*!< FAC read data register */
#define FAC_WDATA_INT REG16_INT((FAC) + 0x00000018U) /*!< FAC write data register */
#define FAC_WDATA_FLOAT REG32_FLOAT((FAC) + 0x00000018U)/*!< FAC write data register */
#define FAC_RDATA_INT REG16_INT((FAC) + 0x0000001CU) /*!< FAC read data register */
#define FAC_RDATA_FLOAT REG32_FLOAT((FAC) + 0x0000001CU)/*!< FAC read data register */
/* bits definitions */
/* FAC_X0BCFG */
#define FAC_X0BCFG_X0B_ADDR BITS(0,7) /*!< X0 buffer base address */
#define FAC_X0BCFG_X0B_SIZE BITS(8,15) /*!< X0 buffer allocated size */
#define FAC_X0BCFG_X0_WBFF BITS(24,25) /*!< watermark for buffer full flag */
/* FAC_X1BCFG */
#define FAC_X1BCFG_X1B_ADDR BITS(0,7) /*!< X1 buffer base address */
#define FAC_X1BCFG_X1B_SIZE BITS(8,15) /*!< X1 buffer allocated size */
/* FAC_YBCFG */
#define FAC_YBCFG_YB_ADDR BITS(0,7) /*!< Y buffer base address */
#define FAC_YBCFG_YB_SIZE BITS(8,15) /*!< Y buffer allocated size */
#define FAC_YBCFG_Y_WBEF BITS(24,25) /*!< watermark for buffer empty flag */
/* FAC_PARACFG */
#define FAC_PARACFG_IPP BITS(0,7) /*!< input parameter IPP */
#define FAC_PARACFG_IPQ BITS(8,15) /*!< input parameter IPQ */
#define FAC_PARACFG_IPR BITS(16,23) /*!< input parameter IPR */
#define FAC_PARACFG_FUN BITS(24,30) /*!< function */
#define FAC_PARACFG_EXE BIT(31) /*!< execution */
/* FAC_CTL */
#define FAC_CTL_RIE BIT(0) /*!< read interrupt enable */
#define FAC_CTL_WIE BIT(1) /*!< write interrupt enable */
#define FAC_CTL_OFEIE BIT(2) /*!< overflow error interrupt enable */
#define FAC_CTL_UFEIE BIT(3) /*!< underflow error interrupt enable */
#define FAC_CTL_STEIE BIT(4) /*!< saturation error interrupt enable */
#define FAC_CTL_GSTEIE BIT(5) /*!< gain saturation error interrupt enable */
#define FAC_CTL_DREN BIT(8) /*!< DMA read channel enable */
#define FAC_CTL_DWEN BIT(9) /*!< DMA write channel enable */
#define FAC_CTL_FLTEN BIT(14) /*!< floating point format enable */
#define FAC_CTL_CPEN BIT(15) /*!< clipping enable */
#define FAC_CTL_RST BIT(16) /*!< reset FAC unit */
/* FAC_STAT */
#define FAC_STAT_YBEF BIT(0) /*!< Y buffer empty flag */
#define FAC_STAT_X0BFF BIT(1) /*!< X0 buffer full flag */
#define FAC_STAT_OFEF BIT(8) /*!< overflow error flag */
#define FAC_STAT_UFEF BIT(9) /*!< underflow error flag */
#define FAC_STAT_STEF BIT(10) /*!< saturation error flag */
#define FAC_STAT_GSTEF BIT(11) /*!< gain saturation error flag */
/* FAC_WDATA */
#define FAC_WDATA_WDATA BITS(0,15) /*!< Write data */
/* FAC_RDATA */
#define FAC_RDATA_RDATA BITS(0,15) /*!< Read data */
/* constants definitions */
/* structure for fac filter parameters */
typedef struct
{
uint8_t input_addr; /*!< base address of the input buffer (X0) */
uint8_t input_size; /*!< size of input buffer */
uint8_t coeff_addr; /*!< base address of the coefficient buffer (X1) */
uint8_t coeff_size; /*!< size of coefficient buffer */
uint8_t output_addr; /*!< base address of the output buffer (Y) */
uint8_t output_size; /*!< size of output buffer */
uint8_t ipp; /*!< value P (vector length, number of filter taps, etc.) */
uint8_t ipq; /*!< value Q (vector length, etc.) */
uint8_t ipr; /*!< value R (gain, etc.) */
uint32_t input_threshold; /*!< threshold of input buffer full */
uint32_t output_threshold; /*!< threshold of output buffer empty */
uint32_t clip; /*!< enable or disable the clipping feature */
uint32_t func; /*!< FAC functions select */
}fac_parameter_struct;
/* structure for fac fixed data preload parameters */
typedef struct
{
uint8_t coeffa_size; /*!< size of the coefficient vector A */
int16_t *coeffa_ctx; /*!< [IIR only] content of the coefficient vector A */
uint8_t coeffb_size; /*!< size of the coefficient vector B */
int16_t *coeffb_ctx; /*!< content of the coefficient vector B */
uint8_t input_size; /*!< Size of the input data */
int16_t *input_ctx; /*!< content of the input data */
uint8_t output_size; /*!< size of the output data */
int16_t *output_ctx; /*!< content of the output data */
}fac_fixed_data_preload_struct;
/* structure for fac float data preload parameters */
typedef struct
{
uint8_t coeffa_size; /*!< size of the coefficient vector A */
float *coeffa_ctx; /*!< [IIR only] content of the coefficient vector A */
uint8_t coeffb_size; /*!< size of the coefficient vector B */
float *coeffb_ctx; /*!< content of the coefficient vector B */
uint8_t input_size; /*!< size of the input data */
float *input_ctx; /*!< content of the input data */
uint8_t output_size; /*!< size of the output data */
float *output_ctx; /*!< content of the output data */
}fac_float_data_preload_struct;
/* FAC function select definitions */
#define PARACFG_FUN(regval) (FAC_PARACFG_FUN & ((uint32_t)(regval) << 24))
#define FUNC_LOAD_X0 PARACFG_FUN(1) /*!< load_X0_buffer */
#define FUNC_LOAD_X1 PARACFG_FUN(2) /*!< load_X1_buffer */
#define FUNC_LOAD_Y PARACFG_FUN(3) /*!< load_Y_buffer */
#define FUNC_CONVO_FIR PARACFG_FUN(8) /*!< convolution (FIR filter) */
#define FUNC_IIR_DIRECT_FORM_1 PARACFG_FUN(9) /*!< IIR filter (direct form 1) */
/* FAC watermark setting definitions */
#define X0BCFG_X0_WBFF(regval) (FAC_X0BCFG_X0_WBFF & ((uint32_t)(regval) << 24))
#define FAC_THRESHOLD_1 X0BCFG_X0_WBFF(0) /*!< full/empty flag when buffer less than 1 */
#define FAC_THRESHOLD_2 X0BCFG_X0_WBFF(1) /*!< full/empty flag when buffer less than 2 */
#define FAC_THRESHOLD_4 X0BCFG_X0_WBFF(2) /*!< full/empty flag when buffer less than 4 */
#define FAC_THRESHOLD_8 X0BCFG_X0_WBFF(3) /*!< full/empty flag when buffer less than 8 */
/* FAC clip function definitions */
#define FAC_CP_DISABLE ((uint8_t)0x00U) /*!< clipping disabled */
#define FAC_CP_ENABLE ((uint8_t)0x01U) /*!< clipping enabled */
/* FAC function execution definitions */
#define PARACFG_EXE(regval) (FAC_PARACFG_EXE & ((uint32_t)(regval) << 31))
#define FAC_FUNC_START PARACFG_EXE(0) /*!< start execution function */
#define FAC_FUNC_STOP PARACFG_EXE(1) /*!< stop execution function */
/* FAC DMA mdoe definitions */
#define FAC_DMA_READ FAC_CTL_DREN /*!< enable dma read */
#define FAC_DMA_WRITE FAC_CTL_DWEN /*!< enable dma write */
/* FAC interrupt flag definitions */
#define FAC_INT_FLAG_YBEF ((uint8_t)0x00U) /*!< Y buffer empty interrupt flag */
#define FAC_INT_FLAG_X0BFF ((uint8_t)0x01U) /*!< X0 buffer full interrupt flag */
#define FAC_INT_FLAG_OFEF ((uint8_t)0x02U) /*!< Overflow error interrupt flag */
#define FAC_INT_FLAG_UFEF ((uint8_t)0x03U) /*!< underflow error interrupt flag */
#define FAC_INT_FLAG_STEF ((uint8_t)0x04U) /*!< saturation error interrupt flag */
#define FAC_INT_FLAG_GSTEF ((uint8_t)0x05U) /*!< gain saturation error interrupt flag */
/* FAC flag definitions */
#define FAC_FLAG_YBEF FAC_STAT_YBEF /*!< Y buffer empty flag */
#define FAC_FLAG_X0BFF FAC_STAT_X0BFF /*!< X0 buffer full flag */
#define FAC_FLAG_OFEF FAC_STAT_OFEF /*!< overflow error flag */
#define FAC_FLAG_UFEF FAC_STAT_UFEF /*!< underflow error flag */
#define FAC_FLAG_STEF FAC_STAT_STEF /*!< saturation error flag */
#define FAC_FLAG_GSTEF FAC_STAT_GSTEF /*!< gain saturation error flag */
/* FAC function declarations */
/* initialization functions */
/* reset the FAC peripheral */
void fac_deinit(void);
/* initialize the FAC filter parameter struct with the default values */
void fac_struct_para_init(fac_parameter_struct* fac_parameter);
/* initialize the FAC fixed data preload parameter struct with the default values */
void fac_fixed_data_preload_init(fac_fixed_data_preload_struct *init_struct);
/* initialize the FAC float data preload parameter struct with the default values */
void fac_float_data_preload_init(fac_float_data_preload_struct *init_struct);
/* initialize the FAC peripheral */
void fac_init(fac_parameter_struct* fac_parameter);
/* FAC preload X0 X1 Y fixed buffer */
void fac_fixed_buffer_preload(fac_fixed_data_preload_struct* init_struct);
/* FAC preload X0 X1 Y float buffer*/
void fac_float_buffer_preload(fac_float_data_preload_struct* init_struct);
/* FAC preload data */
void fac_fixed_data_preload(uint8_t size, int16_t array[]);
/* FAC preload float data */
void fac_float_data_preload(uint8_t size, float array[]);
/* configuration functions */
/* FAC reset write and read pointers */
void fac_reset(void);
/* config the FAC clip feature */
void fac_clip_config(uint8_t cpmod);
/* enable FAC float point format */
void fac_float_enable(void);
/* disable FAC float point format */
void fac_float_disable(void);
/* enable the FAC dma */
void fac_dma_enable(uint32_t dma_req);
/* disable the FAC dma */
void fac_dma_disable(uint32_t dma_req);
/* FAC config input buffer */
void fac_x0_config(uint32_t watermark, uint8_t baseaddr, uint8_t bufsize);
/* FAC config coefficient buffer */
void fac_x1_config(uint8_t baseaddr, uint8_t bufsize);
/* FAC config output buffer */
void fac_y_config(uint32_t watermark, uint8_t baseaddr, uint8_t bufsize);
/* FAC config function execute */
void fac_function_config(fac_parameter_struct* fac_parameter);
/* start the FAC */
void fac_start(void);
/* stop the FAC */
void fac_stop(void);
/* finish the filter calculate */
void fac_finish_calculate(void);
/* FAC data write and read */
/* FAC write data with fixed ponit format */
void fac_fixed_data_write(int16_t data);
/* FAC read data with fixed point format */
int16_t fac_fixed_data_read(void);
/* FAC write data with float ponit format */
void fac_float_data_write(float data);
/* FAC read data with fixed point format */
float fac_float_data_read(void);
/* interrupt & flag functions */
/* enable the FAC interrupt */
void fac_interrupt_enable(uint32_t interrupt);
/* disable the FAC interrupt */
void fac_interrupt_disable(uint32_t interrupt);
/* get the FAC interrupt flag status */
FlagStatus fac_interrupt_flag_get(uint8_t interrupt);
/* get the FAC flag status */
FlagStatus fac_flag_get(uint32_t flag);
#endif /* GD32H7XX_FAC_H */

534
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fmc.h Normal file
View File

File diff suppressed because it is too large Load Diff

117
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fwdgt.h Normal file
View File

@@ -0,0 +1,117 @@
/*!
\file gd32h7xx_fwdgt.h
\brief definitions for the FWDGT
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_FWDGT_H
#define GD32H7XX_FWDGT_H
#include "gd32h7xx.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
/* FWDGT_WND */
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
/* constants definitions */
/* FWDGT_PSC register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
/* function declarations */
/* enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */
void fwdgt_write_enable(void);
/* disable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */
void fwdgt_write_disable(void);
/* start the FWDGT counter */
void fwdgt_enable(void);
/* configure the FWDGT counter prescaler value */
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
/* configure the FWDGT counter reload value */
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
/* configure the FWDGT counter window value */
ErrStatus fwdgt_window_value_config(uint16_t window_value);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32H7XX_FWDGT_H */

442
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_gpio.h Normal file
View File

@@ -0,0 +1,442 @@
/*!
\file gd32h7xx_gpio.h
\brief definitions for the GPIO
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_GPIO_H
#define GD32H7XX_GPIO_H
#include "gd32h7xx.h"
/* GPIOx(x = A,B,C,D,E,F,G,H,J,K) definitions */
#define GPIOA (GPIO_BASE + 0x00000000U)
#define GPIOB (GPIO_BASE + 0x00000400U)
#define GPIOC (GPIO_BASE + 0x00000800U)
#define GPIOD (GPIO_BASE + 0x00000C00U)
#define GPIOE (GPIO_BASE + 0x00001000U)
#define GPIOF (GPIO_BASE + 0x00001400U)
#define GPIOG (GPIO_BASE + 0x00001800U)
#define GPIOH (GPIO_BASE + 0x00001C00U)
#define GPIOJ (GPIO_BASE + 0x00002400U)
#define GPIOK (GPIO_BASE + 0x00002800U)
/* registers definitions */
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register */
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */
#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */
#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */
#define GPIO_IFL(gpiox) REG32((gpiox) + 0x00000030U) /*!< GPIO input filtering register */
#define GPIO_IFTP(gpiox) REG32((gpiox) + 0x00000034U) /*!< GPIO input filtering type register */
/* bits definitions */
/* GPIO_CTL */
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
/* GPIO_OMODE */
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
/* GPIO_OSPD */
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
/* GPIO_PUD */
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
/* GPIO_ISTAT */
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
/* GPIO_OCTL */
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
/* GPIO_BOP */
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
/* GPIO_LOCK */
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
/* GPIO_AFSEL0 */
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
/* GPIO_AFSEL1 */
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
/* GPIO_BC */
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
/* GPIO_TG */
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
/* GPIO_IFL */
#define GPIO_IFL_FLPRD0 BITS(0,7) /*!< filter sampling period for GPIO1 to GPIO7 */
#define GPIO_IFL_FLPRD1 BITS(8,15) /*!< filter sampling period for GPIO8 to GPIO15 */
/* GPIO_IFTP */
#define GPIO_IFTP_IFTP0 BITS(0,1) /*!< pin 0 input filtering type bits */
#define GPIO_IFTP_IFTP1 BITS(2,3) /*!< pin 1 input filtering type bits */
#define GPIO_IFTP_IFTP2 BITS(4,5) /*!< pin 2 input filtering type bits */
#define GPIO_IFTP_IFTP3 BITS(6,7) /*!< pin 3 input filtering type bits */
#define GPIO_IFTP_IFTP4 BITS(8,9) /*!< pin 4 input filtering type bits */
#define GPIO_IFTP_IFTP5 BITS(10,11) /*!< pin 5 input filtering type bits */
#define GPIO_IFTP_IFTP6 BITS(12,13) /*!< pin 6 input filtering type bits */
#define GPIO_IFTP_IFTP7 BITS(14,15) /*!< pin 7 input filtering type bits */
#define GPIO_IFTP_IFTP8 BITS(16,17) /*!< pin 8 input filtering type bits */
#define GPIO_IFTP_IFTP9 BITS(18,19) /*!< pin 9 input filtering type bits */
#define GPIO_IFTP_IFTP10 BITS(20,21) /*!< pin 10 input filtering type bits */
#define GPIO_IFTP_IFTP11 BITS(22,23) /*!< pin 11 input filtering type bits */
#define GPIO_IFTP_IFTP12 BITS(24,25) /*!< pin 12 input filtering type bits */
#define GPIO_IFTP_IFTP13 BITS(26,27) /*!< pin 13 input filtering type bits */
#define GPIO_IFTP_IFTP14 BITS(28,29) /*!< pin 14 input filtering type bits */
#define GPIO_IFTP_IFTP15 BITS(30,31) /*!< pin 15 input filtering type bits */
/* constants definitions */
typedef FlagStatus bit_status;
/* output mode definitions */
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
/* pull-up/pull-down definitions */
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
/* GPIO pin definitions */
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
/* GPIO mode configuration values */
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
/* GPIO pull-up/pull-down values */
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
/* GPIO output speed values */
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
/* GPIO output type */
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
/* GPIO output max speed value */
#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_OSPEED_12MHZ OSPD_OSPD0(0) /*!< output max speed 12MHz */
#define GPIO_OSPEED_60MHZ OSPD_OSPD0(1) /*!< output max speed 60MHz */
#define GPIO_OSPEED_85MHZ OSPD_OSPD0(2) /*!< output max speed 85MHz */
#define GPIO_OSPEED_100_220MHZ OSPD_OSPD0(3) /*!< output max speed 100/220MHz */
/* GPIO input filter type values */
#define GPIO_IFTYPE_SET(n, type) ((uint32_t)((uint32_t)(type) << (2U * (n))))
#define GPIO_IFTYPE_MASK(n) (0x3U << (2U * (n)))
/* GPIO input filter sample period */
#define IFL_FLPRD0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define GPIO_ISPERIOD(vle) IFL_FLPRD0(vle) /*!< input filter sample period */
/* GPIO input filtering type */
#define IFTYPE_IFTP0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_IFTYPE_SYNC IFTYPE_IFTP0(0) /*!< input filter type synchronization */
#define GPIO_IFTYPE_3_SAMPLE IFTYPE_IFTP0(1) /*!< input filter type filter 3 samples */
#define GPIO_IFTYPE_6_SAMPLE IFTYPE_IFTP0(2) /*!< input filter type filter 6 samples */
#define GPIO_IFTYPE_ASYNC IFTYPE_IFTP0(3) /*!< input filter type asynchronous */
/* GPIO alternate function values */
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
/* GPIO alternate function */
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */
#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */
#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */
#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */
#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */
#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */
#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */
#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */
#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */
/* function declarations */
/* reset GPIO port */
void gpio_deinit(uint32_t gpio_periph);
/* set GPIO mode */
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
/* set GPIO output type and speed */
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
/* set GPIO pin bit */
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
/* reset GPIO pin bit */
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
/* write data to the specified GPIO pin */
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
/* write data to the specified GPIO port */
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
/* set GPIO input filter */
void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftype, uint32_t pin);
/* get GPIO pin input status */
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
/* get GPIO port input status */
uint16_t gpio_input_port_get(uint32_t gpio_periph);
/* get GPIO pin output status */
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
/* get GPIO port output status */
uint16_t gpio_output_port_get(uint32_t gpio_periph);
/* set GPIO alternate function */
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin);
/* lock GPIO pin bit */
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
/* toggle GPIO pin status */
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
/* toggle GPIO port status */
void gpio_port_toggle(uint32_t gpio_periph);
#endif /* GD32H7XX_GPIO_H */

223
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_hau.h Normal file
View File

@@ -0,0 +1,223 @@
/*!
\file gd32h7xx_hau.h
\brief definitions for the HAU
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_HAU_H
#define GD32H7XX_HAU_H
#include "gd32h7xx.h"
/* HAU definitions */
#define HAU HAU_BASE
/* registers definitions */
#define HAU_CTL REG32(HAU + 0x00000000U) /*!< control register */
#define HAU_DI REG32(HAU + 0x00000004U) /*!< data input register */
#define HAU_CFG REG32(HAU + 0x00000008U) /*!< configuration register */
#define HAU_DO0 REG32(HAU + 0x0000000CU) /*!< data output register 0 */
#define HAU_DO1 REG32(HAU + 0x00000010U) /*!< data output register 1 */
#define HAU_DO2 REG32(HAU + 0x00000014U) /*!< data output register 2 */
#define HAU_DO3 REG32(HAU + 0x00000018U) /*!< data output register 3 */
#define HAU_DO4 REG32(HAU + 0x0000001CU) /*!< data output register 4 */
#define HAU_DO5 REG32(HAU + 0x00000324U) /*!< data output register 5 */
#define HAU_DO6 REG32(HAU + 0x00000328U) /*!< data output register 6 */
#define HAU_DO7 REG32(HAU + 0x0000032CU) /*!< data output register 7 */
#define HAU_INTEN REG32(HAU + 0x00000020U) /*!< interrupt enable register */
#define HAU_STAT REG32(HAU + 0x00000024U) /*!< status and interrupt flag register */
#define HAU_CTXS(x) REG32(HAU + 0x000000F8U + 0x04U * (x)) /*!< context switch register x, x <= 53 */
/* bits definitions */
/* HAU_CTL */
#define HAU_CTL_START BIT(2) /*!< set to 1 to reset the HAU processor core, so that it is ready to start the digest calculation */
#define HAU_CTL_DMAE BIT(3) /*!< DMA enable */
#define HAU_CTL_DATAM BITS(4,5) /*!< data type mode */
#define HAU_CTL_HMS BIT(6) /*!< HAU mode selection */
#define HAU_CTL_ALGM_0 BIT(7) /*!< algorithm selection bit 0 */
#define HAU_CTL_NWIF BITS(8,11) /*!< number of words in the input FIFO */
#define HAU_CTL_DINE BIT(12) /*!< DI register not empty */
#define HAU_CTL_MDS BIT(13) /*!< multiple DMA selection */
#define HAU_CTL_KLM BIT(16) /*!< key length mode */
#define HAU_CTL_ALGM_1 BIT(18) /*!< algorithm selection bit 1 */
/* HAU_DI */
#define HAU_DI_DI BITS(0,31) /*!< message data input */
/* HAU_CFG */
#define HAU_CFG_VBL BITS(0,4) /*!< valid bits length in the last word */
#define HAU_CFG_CALEN BIT(8) /*!< digest calculation enable */
/* HAU_DOx x=0..7 */
#define HAU_DOX_DOX BITS(0,31) /*!< message digest result of hash algorithm */
/* HAU_INTEN */
#define HAU_INTEN_DIIE BIT(0) /*!< data input interrupt enable */
#define HAU_INTEN_CCIE BIT(1) /*!< calculation completion interrupt enable */
/* HAU_STAT */
#define HAU_STAT_DIF BIT(0) /*!< data input interrupt flag */
#define HAU_STAT_CCF BIT(1) /*!< digest calculation completion interrupt flag */
#define HAU_STAT_DMAS BIT(2) /*!< DMA status */
#define HAU_STAT_BUSY BIT(3) /*!< busy bit */
/* constants definitions */
/* structure for initialization of the hau */
typedef struct
{
uint32_t algo; /*!< algorithm selection */
uint32_t mode; /*!< HAU mode selection */
uint32_t datatype; /*!< data type mode */
uint32_t keytype; /*!< key length mode */
}hau_init_parameter_struct;
/* structure for message digest result of the hau */
typedef struct
{
uint32_t out[8]; /*!< message digest result 0-7 */
}hau_digest_parameter_struct;
/* structure for context switch */
typedef struct
{
uint32_t hau_ctl_bak; /*!< backup of HAU_CTL register */
uint32_t hau_cfg_bak; /*!< backup of HAU_CFG register */
uint32_t hau_inten_bak; /*!< backup of HAU_INTEN register */
uint32_t hau_ctxs_bak[54]; /*!< backup of HAU_CTXSx registers */
}hau_context_parameter_struct;
/* hau_ctl register value */
#define HAU_ALGO_SHA1 ((uint32_t)0x00000000U) /*!< HAU function is SHA1 */
#define HAU_ALGO_SHA224 HAU_CTL_ALGM_1 /*!< HAU function is SHA224 */
#define HAU_ALGO_SHA256 (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0) /*!< HAU function is SHA256 */
#define HAU_ALGO_MD5 HAU_CTL_ALGM_0 /*!< HAU function is MD5 */
#define HAU_MODE_HASH ((uint32_t)0x00000000U) /*!< HAU mode is HASH */
#define HAU_MODE_HMAC HAU_CTL_HMS /*!< HAU mode is HMAC */
#define CTL_DATAM_1(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< write value to HAU_CTL_DATAM bit field */
#define HAU_SWAPPING_32BIT CTL_DATAM_1(0) /*!< no swapping */
#define HAU_SWAPPING_16BIT CTL_DATAM_1(1) /*!< half-word swapping */
#define HAU_SWAPPING_8BIT CTL_DATAM_1(2) /*!< bytes swapping */
#define HAU_SWAPPING_1BIT CTL_DATAM_1(3) /*!< bit swapping */
#define HAU_KEY_SHORTER_64 ((uint32_t)0x00000000U) /*!< HMAC key is <= 64 bytes */
#define HAU_KEY_LONGGER_64 HAU_CTL_KLM /*!< HMAC key is > 64 bytes */
#define GET_CTL_NWIF(regval) GET_BITS((regval),8,11) /*!< get value of HAU_CTL_NWIF bit field */
#define SINGLE_DMA_AUTO_DIGEST ((uint32_t)0x00000000U) /*!< message padding and message digest calculation at the end of a DMA transfer */
#define MULTIPLE_DMA_NO_DIGEST HAU_CTL_MDS /*!< multiple DMA transfers needed and CALEN bit is not automatically set at the end of a DMA transfer */
/* hau_cfg register value */
#define CFG_VBL(regval) (BITS(0,4) & (((uint32_t)(regval)))) /*!< write value to HAU_CFG_VBL bit field */
/* hau_inten register value */
#define HAU_INT_DATA_INPUT HAU_INTEN_DIIE /*!< a new block can be entered into the IN buffer */
#define HAU_INT_CALCULATION_COMPLETE HAU_INTEN_CCIE /*!< calculation complete */
#define HAU_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */
#define HAU_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */
#define HAU_FLAG_DMA HAU_STAT_DMAS /*!< DMA is enabled (DMAE =1) or a transfer is processing */
#define HAU_FLAG_BUSY HAU_STAT_BUSY /*!< data block is in process */
#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */
#define HAU_INT_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */
#define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */
/* function declarations */
/* initialization functions */
/* reset the HAU peripheral */
void hau_deinit(void);
/* initialize the HAU peripheral parameters */
void hau_init(hau_init_parameter_struct* initpara);
/* initialize the structure hau_initpara with default value */
void hau_init_struct_para_init(hau_init_parameter_struct* initpara);
/* reset the HAU processor core */
void hau_reset(void);
/* configure the number of valid bits in last word of the message */
void hau_last_word_validbits_num_config(uint32_t valid_num);
/* write data to the IN FIFO */
void hau_data_write(uint32_t data);
/* return the number of words already written into the IN FIFO */
uint32_t hau_infifo_words_num_get(void);
/* read the message digest result */
void hau_digest_read(hau_digest_parameter_struct* digestpara);
/* enable digest calculation */
void hau_digest_calculation_enable(void);
/* configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not */
void hau_multiple_single_dma_config(uint32_t multi_single);
/* enable the HAU DMA interface */
void hau_dma_enable(void);
/* disable the HAU DMA interface */
void hau_dma_disable(void);
/* context swapping functions */
/* initialize the struct context */
void hau_context_struct_para_init(hau_context_parameter_struct* context);
/* save the HAU peripheral context */
void hau_context_save(hau_context_parameter_struct* context_save);
/* restore the HAU peripheral context */
void hau_context_restore(hau_context_parameter_struct* context_restore);
/* calculate digest in HASH mode */
/* calculate digest using SHA1 in HASH mode */
ErrStatus hau_hash_sha_1(uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using SHA1 in HMAC mode */
ErrStatus hau_hmac_sha_1(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using SHA224 in HASH mode */
ErrStatus hau_hash_sha_224(uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using SHA224 in HMAC mode */
ErrStatus hau_hmac_sha_224(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using SHA256 in HASH mode */
ErrStatus hau_hash_sha_256(uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using SHA256 in HMAC mode */
ErrStatus hau_hmac_sha_256(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using MD5 in HASH mode */
ErrStatus hau_hash_md5(uint8_t input[], uint32_t in_length, uint8_t output[]);
/* calculate digest using MD5 in HMAC mode */
ErrStatus hau_hmac_md5(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
/* interrupt & flag functions */
/* get the HAU flag status */
FlagStatus hau_flag_get(uint32_t flag);
/* clear the HAU flag status */
void hau_flag_clear(uint32_t flag);
/* enable the HAU interrupts */
void hau_interrupt_enable(uint32_t interrupt);
/* disable the HAU interrupts */
void hau_interrupt_disable(uint32_t interrupt);
/* get the HAU interrupt flag status */
FlagStatus hau_interrupt_flag_get(uint32_t int_flag);
/* clear the HAU interrupt flag status */
void hau_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H7XX_HAU_H */

760
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_hpdf.h Normal file
View File

File diff suppressed because it is too large Load Diff

365
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_hwsem.h Normal file
View File

@@ -0,0 +1,365 @@
/*!
\file gd32h7xx_hwsem.h
\brief definitions for the HWSEM
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_HWSEM_H
#define GD32H7XX_HWSEM_H
#include "gd32h7xx.h"
/* HWSEM definitions */
#define HWSEM HWSEM_BASE /*!< HWSEM base address */
/* registers definitions */
#define HWSEM_CTL0 REG32(HWSEM + 0x00000000U) /*!< HWSEM control register 0 */
#define HWSEM_CTL1 REG32(HWSEM + 0x00000004U) /*!< HWSEM control register 1 */
#define HWSEM_CTL2 REG32(HWSEM + 0x00000008U) /*!< HWSEM control register 2 */
#define HWSEM_CTL3 REG32(HWSEM + 0x0000000CU) /*!< HWSEM control register 3 */
#define HWSEM_CTL4 REG32(HWSEM + 0x00000010U) /*!< HWSEM control register 4 */
#define HWSEM_CTL5 REG32(HWSEM + 0x00000014U) /*!< HWSEM control register 5 */
#define HWSEM_CTL6 REG32(HWSEM + 0x00000018U) /*!< HWSEM control register 6 */
#define HWSEM_CTL7 REG32(HWSEM + 0x0000001CU) /*!< HWSEM control register 7 */
#define HWSEM_CTL8 REG32(HWSEM + 0x00000020U) /*!< HWSEM control register 8 */
#define HWSEM_CTL9 REG32(HWSEM + 0x00000024U) /*!< HWSEM control register 9 */
#define HWSEM_CTL10 REG32(HWSEM + 0x00000028U) /*!< HWSEM control register 10 */
#define HWSEM_CTL11 REG32(HWSEM + 0x0000002CU) /*!< HWSEM control register 11 */
#define HWSEM_CTL12 REG32(HWSEM + 0x00000030U) /*!< HWSEM control register 12 */
#define HWSEM_CTL13 REG32(HWSEM + 0x00000034U) /*!< HWSEM control register 13 */
#define HWSEM_CTL14 REG32(HWSEM + 0x00000038U) /*!< HWSEM control register 14 */
#define HWSEM_CTL15 REG32(HWSEM + 0x0000003CU) /*!< HWSEM control register 15 */
#define HWSEM_CTL16 REG32(HWSEM + 0x00000040U) /*!< HWSEM control register 16 */
#define HWSEM_CTL17 REG32(HWSEM + 0x00000044U) /*!< HWSEM control register 17 */
#define HWSEM_CTL18 REG32(HWSEM + 0x00000048U) /*!< HWSEM control register 18 */
#define HWSEM_CTL19 REG32(HWSEM + 0x0000004CU) /*!< HWSEM control register 19 */
#define HWSEM_CTL20 REG32(HWSEM + 0x00000050U) /*!< HWSEM control register 20 */
#define HWSEM_CTL21 REG32(HWSEM + 0x00000054U) /*!< HWSEM control register 21 */
#define HWSEM_CTL22 REG32(HWSEM + 0x00000058U) /*!< HWSEM control register 22 */
#define HWSEM_CTL23 REG32(HWSEM + 0x0000005CU) /*!< HWSEM control register 23 */
#define HWSEM_CTL24 REG32(HWSEM + 0x00000060U) /*!< HWSEM control register 24 */
#define HWSEM_CTL25 REG32(HWSEM + 0x00000064U) /*!< HWSEM control register 25 */
#define HWSEM_CTL26 REG32(HWSEM + 0x00000068U) /*!< HWSEM control register 26 */
#define HWSEM_CTL27 REG32(HWSEM + 0x0000006CU) /*!< HWSEM control register 27 */
#define HWSEM_CTL28 REG32(HWSEM + 0x00000070U) /*!< HWSEM control register 28 */
#define HWSEM_CTL29 REG32(HWSEM + 0x00000074U) /*!< HWSEM control register 29 */
#define HWSEM_CTL30 REG32(HWSEM + 0x00000078U) /*!< HWSEM control register 30 */
#define HWSEM_CTL31 REG32(HWSEM + 0x0000007CU) /*!< HWSEM control register 31 */
#define HWSEM_RLK0 REG32(HWSEM + 0x00000080U) /*!< HWSEM read lock register 0 */
#define HWSEM_RLK1 REG32(HWSEM + 0x00000084U) /*!< HWSEM read lock register 1 */
#define HWSEM_RLK2 REG32(HWSEM + 0x00000088U) /*!< HWSEM read lock register 2 */
#define HWSEM_RLK3 REG32(HWSEM + 0x0000008CU) /*!< HWSEM read lock register 3 */
#define HWSEM_RLK4 REG32(HWSEM + 0x00000090U) /*!< HWSEM read lock register 4 */
#define HWSEM_RLK5 REG32(HWSEM + 0x00000094U) /*!< HWSEM read lock register 5 */
#define HWSEM_RLK6 REG32(HWSEM + 0x00000098U) /*!< HWSEM read lock register 6 */
#define HWSEM_RLK7 REG32(HWSEM + 0x0000009CU) /*!< HWSEM read lock register 7 */
#define HWSEM_RLK8 REG32(HWSEM + 0x000000A0U) /*!< HWSEM read lock register 8 */
#define HWSEM_RLK9 REG32(HWSEM + 0x000000A4U) /*!< HWSEM read lock register 9 */
#define HWSEM_RLK10 REG32(HWSEM + 0x000000A8U) /*!< HWSEM read lock register 10 */
#define HWSEM_RLK11 REG32(HWSEM + 0x000000ACU) /*!< HWSEM read lock register 11 */
#define HWSEM_RLK12 REG32(HWSEM + 0x000000B0U) /*!< HWSEM read lock register 12 */
#define HWSEM_RLK13 REG32(HWSEM + 0x000000B4U) /*!< HWSEM read lock register 13 */
#define HWSEM_RLK14 REG32(HWSEM + 0x000000B8U) /*!< HWSEM read lock register 14 */
#define HWSEM_RLK15 REG32(HWSEM + 0x000000BCU) /*!< HWSEM read lock register 15 */
#define HWSEM_RLK16 REG32(HWSEM + 0x000000C0U) /*!< HWSEM read lock register 16 */
#define HWSEM_RLK17 REG32(HWSEM + 0x000000C4U) /*!< HWSEM read lock register 17 */
#define HWSEM_RLK18 REG32(HWSEM + 0x000000C8U) /*!< HWSEM read lock register 18 */
#define HWSEM_RLK19 REG32(HWSEM + 0x000000CCU) /*!< HWSEM read lock register 19 */
#define HWSEM_RLK20 REG32(HWSEM + 0x000000D0U) /*!< HWSEM read lock register 20 */
#define HWSEM_RLK21 REG32(HWSEM + 0x000000D4U) /*!< HWSEM read lock register 21 */
#define HWSEM_RLK22 REG32(HWSEM + 0x000000D8U) /*!< HWSEM read lock register 22 */
#define HWSEM_RLK23 REG32(HWSEM + 0x000000DCU) /*!< HWSEM read lock register 23 */
#define HWSEM_RLK24 REG32(HWSEM + 0x000000E0U) /*!< HWSEM read lock register 24 */
#define HWSEM_RLK25 REG32(HWSEM + 0x000000E4U) /*!< HWSEM read lock register 25 */
#define HWSEM_RLK26 REG32(HWSEM + 0x000000E8U) /*!< HWSEM read lock register 26 */
#define HWSEM_RLK27 REG32(HWSEM + 0x000000ECU) /*!< HWSEM read lock register 27 */
#define HWSEM_RLK28 REG32(HWSEM + 0x000000F0U) /*!< HWSEM read lock register 28 */
#define HWSEM_RLK29 REG32(HWSEM + 0x000000F4U) /*!< HWSEM read lock register 29 */
#define HWSEM_RLK30 REG32(HWSEM + 0x000000F8U) /*!< HWSEM read lock register 30 */
#define HWSEM_RLK31 REG32(HWSEM + 0x000000FCU) /*!< HWSEM read lock register 31 */
#define HWSEM_INTEN REG32(HWSEM + 0x00000100U) /*!< HWSEM interrupt enable register */
#define HWSEM_INTC REG32(HWSEM + 0x00000104U) /*!< HWSEM interrupt flag clear register */
#define HWSEM_STAT REG32(HWSEM + 0x00000108U) /*!< HWSEM status register */
#define HWSEM_INTF REG32(HWSEM + 0x0000010CU) /*!< HWSEM interrupt flag register */
#define HWSEM_UNLK REG32(HWSEM + 0x00000140U) /*!< HWSEM unlock register */
#define HWSEM_KEY REG32(HWSEM + 0x00000144U) /*!< HWSEM key register */
/* bits definitions */
/* HWSEM_CTLx, x=0..31 */
#define HWSEM_CTL_PID BITS(0,7) /*!< HWSEM process ID */
#define HWSEM_CTL_MID BITS(8,11) /*!< HWSEM master ID */
#define HWSEM_CTL_LK BIT(31) /*!< HWSEM lock */
/* HWSEM_RLKx, x=0..31 */
#define HWSEM_RLK_PID BITS(0,7) /*!< HWSEM read lock register process ID */
#define HWSEM_RLK_MID BITS(8,11) /*!< HWSEM read lock register master ID */
#define HWSEM_RLK_LK BIT(31) /*!< HWSEM read lock register lock */
/* HWSEM_INTEN */
#define HWSEM_INTEN_SIE0 BIT(0) /*!< enable HWSEM interrupt for semaphore 0 */
#define HWSEM_INTEN_SIE1 BIT(1) /*!< enable HWSEM interrupt for semaphore 1 */
#define HWSEM_INTEN_SIE2 BIT(2) /*!< enable HWSEM interrupt for semaphore 2 */
#define HWSEM_INTEN_SIE3 BIT(3) /*!< enable HWSEM interrupt for semaphore 3 */
#define HWSEM_INTEN_SIE4 BIT(4) /*!< enable HWSEM interrupt for semaphore 4 */
#define HWSEM_INTEN_SIE5 BIT(5) /*!< enable HWSEM interrupt for semaphore 5 */
#define HWSEM_INTEN_SIE6 BIT(6) /*!< enable HWSEM interrupt for semaphore 6 */
#define HWSEM_INTEN_SIE7 BIT(7) /*!< enable HWSEM interrupt for semaphore 7 */
#define HWSEM_INTEN_SIE8 BIT(8) /*!< enable HWSEM interrupt for semaphore 8 */
#define HWSEM_INTEN_SIE9 BIT(9) /*!< enable HWSEM interrupt for semaphore 9 */
#define HWSEM_INTEN_SIE10 BIT(10) /*!< enable HWSEM interrupt for semaphore 10 */
#define HWSEM_INTEN_SIE11 BIT(11) /*!< enable HWSEM interrupt for semaphore 11 */
#define HWSEM_INTEN_SIE12 BIT(12) /*!< enable HWSEM interrupt for semaphore 12 */
#define HWSEM_INTEN_SIE13 BIT(13) /*!< enable HWSEM interrupt for semaphore 13 */
#define HWSEM_INTEN_SIE14 BIT(14) /*!< enable HWSEM interrupt for semaphore 14 */
#define HWSEM_INTEN_SIE15 BIT(15) /*!< enable HWSEM interrupt for semaphore 15 */
#define HWSEM_INTEN_SIE16 BIT(16) /*!< enable HWSEM interrupt for semaphore 16 */
#define HWSEM_INTEN_SIE17 BIT(17) /*!< enable HWSEM interrupt for semaphore 17 */
#define HWSEM_INTEN_SIE18 BIT(18) /*!< enable HWSEM interrupt for semaphore 18 */
#define HWSEM_INTEN_SIE19 BIT(19) /*!< enable HWSEM interrupt for semaphore 19 */
#define HWSEM_INTEN_SIE20 BIT(20) /*!< enable HWSEM interrupt for semaphore 20 */
#define HWSEM_INTEN_SIE21 BIT(21) /*!< enable HWSEM interrupt for semaphore 21 */
#define HWSEM_INTEN_SIE22 BIT(22) /*!< enable HWSEM interrupt for semaphore 22 */
#define HWSEM_INTEN_SIE23 BIT(23) /*!< enable HWSEM interrupt for semaphore 23 */
#define HWSEM_INTEN_SIE24 BIT(24) /*!< enable HWSEM interrupt for semaphore 24 */
#define HWSEM_INTEN_SIE25 BIT(25) /*!< enable HWSEM interrupt for semaphore 25 */
#define HWSEM_INTEN_SIE26 BIT(26) /*!< enable HWSEM interrupt for semaphore 26 */
#define HWSEM_INTEN_SIE27 BIT(27) /*!< enable HWSEM interrupt for semaphore 27 */
#define HWSEM_INTEN_SIE28 BIT(28) /*!< enable HWSEM interrupt for semaphore 28 */
#define HWSEM_INTEN_SIE29 BIT(29) /*!< enable HWSEM interrupt for semaphore 29 */
#define HWSEM_INTEN_SIE30 BIT(30) /*!< enable HWSEM interrupt for semaphore 30 */
#define HWSEM_INTEN_SIE31 BIT(31) /*!< enable HWSEM interrupt for semaphore 31 */
/* HWSEM_INTC */
#define HWSEM_INTC_SIFC0 BIT(0) /*!< clear semaphore 0 flag and interrupt flag */
#define HWSEM_INTC_SIFC1 BIT(1) /*!< clear semaphore 1 flag and interrupt flag */
#define HWSEM_INTC_SIFC2 BIT(2) /*!< clear semaphore 2 flag and interrupt flag */
#define HWSEM_INTC_SIFC3 BIT(3) /*!< clear semaphore 3 flag and interrupt flag */
#define HWSEM_INTC_SIFC4 BIT(4) /*!< clear semaphore 4 flag and interrupt flag */
#define HWSEM_INTC_SIFC5 BIT(5) /*!< clear semaphore 5 flag and interrupt flag */
#define HWSEM_INTC_SIFC6 BIT(6) /*!< clear semaphore 6 flag and interrupt flag */
#define HWSEM_INTC_SIFC7 BIT(7) /*!< clear semaphore 7 flag and interrupt flag */
#define HWSEM_INTC_SIFC8 BIT(8) /*!< clear semaphore 8 flag and interrupt flag */
#define HWSEM_INTC_SIFC9 BIT(9) /*!< clear semaphore 9 flag and interrupt flag */
#define HWSEM_INTC_SIFC10 BIT(10) /*!< clear semaphore 10 flag and interrupt flag */
#define HWSEM_INTC_SIFC11 BIT(11) /*!< clear semaphore 11 flag and interrupt flag */
#define HWSEM_INTC_SIFC12 BIT(12) /*!< clear semaphore 12 flag and interrupt flag */
#define HWSEM_INTC_SIFC13 BIT(13) /*!< clear semaphore 13 flag and interrupt flag */
#define HWSEM_INTC_SIFC14 BIT(14) /*!< clear semaphore 14 flag and interrupt flag */
#define HWSEM_INTC_SIFC15 BIT(15) /*!< clear semaphore 15 flag and interrupt flag */
#define HWSEM_INTC_SIFC16 BIT(16) /*!< clear semaphore 16 flag and interrupt flag */
#define HWSEM_INTC_SIFC17 BIT(17) /*!< clear semaphore 17 flag and interrupt flag */
#define HWSEM_INTC_SIFC18 BIT(18) /*!< clear semaphore 18 flag and interrupt flag */
#define HWSEM_INTC_SIFC19 BIT(19) /*!< clear semaphore 19 flag and interrupt flag */
#define HWSEM_INTC_SIFC20 BIT(20) /*!< clear semaphore 20 flag and interrupt flag */
#define HWSEM_INTC_SIFC21 BIT(21) /*!< clear semaphore 21 flag and interrupt flag */
#define HWSEM_INTC_SIFC22 BIT(22) /*!< clear semaphore 22 flag and interrupt flag */
#define HWSEM_INTC_SIFC23 BIT(23) /*!< clear semaphore 23 flag and interrupt flag */
#define HWSEM_INTC_SIFC24 BIT(24) /*!< clear semaphore 24 flag and interrupt flag */
#define HWSEM_INTC_SIFC25 BIT(25) /*!< clear semaphore 25 flag and interrupt flag */
#define HWSEM_INTC_SIFC26 BIT(26) /*!< clear semaphore 26 flag and interrupt flag */
#define HWSEM_INTC_SIFC27 BIT(27) /*!< clear semaphore 27 flag and interrupt flag */
#define HWSEM_INTC_SIFC28 BIT(28) /*!< clear semaphore 28 flag and interrupt flag */
#define HWSEM_INTC_SIFC29 BIT(29) /*!< clear semaphore 29 flag and interrupt flag */
#define HWSEM_INTC_SIFC30 BIT(30) /*!< clear semaphore 30 flag and interrupt flag */
#define HWSEM_INTC_SIFC31 BIT(31) /*!< clear semaphore 31 flag and interrupt flag */
/* HWSEM_STAT */
#define HWSEM_STAT_SF0 BIT(0) /*!< semaphore 0 unlock event occurs */
#define HWSEM_STAT_SF1 BIT(1) /*!< semaphore 1 unlock event occurs */
#define HWSEM_STAT_SF2 BIT(2) /*!< semaphore 2 unlock event occurs */
#define HWSEM_STAT_SF3 BIT(3) /*!< semaphore 3 unlock event occurs */
#define HWSEM_STAT_SF4 BIT(4) /*!< semaphore 4 unlock event occurs */
#define HWSEM_STAT_SF5 BIT(5) /*!< semaphore 5 unlock event occurs */
#define HWSEM_STAT_SF6 BIT(6) /*!< semaphore 6 unlock event occurs */
#define HWSEM_STAT_SF7 BIT(7) /*!< semaphore 7 unlock event occurs */
#define HWSEM_STAT_SF8 BIT(8) /*!< semaphore 8 unlock event occurs */
#define HWSEM_STAT_SF9 BIT(9) /*!< semaphore 9 unlock event occurs */
#define HWSEM_STAT_SF10 BIT(10) /*!< semaphore 10 unlock event occurs */
#define HWSEM_STAT_SF11 BIT(11) /*!< semaphore 11 unlock event occurs */
#define HWSEM_STAT_SF12 BIT(12) /*!< semaphore 12 unlock event occurs */
#define HWSEM_STAT_SF13 BIT(13) /*!< semaphore 13 unlock event occurs */
#define HWSEM_STAT_SF14 BIT(14) /*!< semaphore 14 unlock event occurs */
#define HWSEM_STAT_SF15 BIT(15) /*!< semaphore 15 unlock event occurs */
#define HWSEM_STAT_SF16 BIT(16) /*!< semaphore 16 unlock event occurs */
#define HWSEM_STAT_SF17 BIT(17) /*!< semaphore 17 unlock event occurs */
#define HWSEM_STAT_SF18 BIT(18) /*!< semaphore 18 unlock event occurs */
#define HWSEM_STAT_SF19 BIT(19) /*!< semaphore 19 unlock event occurs */
#define HWSEM_STAT_SF20 BIT(20) /*!< semaphore 20 unlock event occurs */
#define HWSEM_STAT_SF21 BIT(21) /*!< semaphore 21 unlock event occurs */
#define HWSEM_STAT_SF22 BIT(22) /*!< semaphore 22 unlock event occurs */
#define HWSEM_STAT_SF23 BIT(23) /*!< semaphore 23 unlock event occurs */
#define HWSEM_STAT_SF24 BIT(24) /*!< semaphore 24 unlock event occurs */
#define HWSEM_STAT_SF25 BIT(25) /*!< semaphore 25 unlock event occurs */
#define HWSEM_STAT_SF26 BIT(26) /*!< semaphore 26 unlock event occurs */
#define HWSEM_STAT_SF27 BIT(27) /*!< semaphore 27 unlock event occurs */
#define HWSEM_STAT_SF28 BIT(28) /*!< semaphore 28 unlock event occurs */
#define HWSEM_STAT_SF29 BIT(29) /*!< semaphore 29 unlock event occurs */
#define HWSEM_STAT_SF30 BIT(30) /*!< semaphore 30 unlock event occurs */
#define HWSEM_STAT_SF31 BIT(31) /*!< semaphore 31 unlock event occurs */
/* HWSEM_INTF */
#define HWSEM_INTF_SIF0 BIT(0) /*!< semaphore 00 interrupt is pending */
#define HWSEM_INTF_SIF1 BIT(1) /*!< semaphore 01 interrupt is pending */
#define HWSEM_INTF_SIF2 BIT(2) /*!< semaphore 02 interrupt is pending */
#define HWSEM_INTF_SIF3 BIT(3) /*!< semaphore 03 interrupt is pending */
#define HWSEM_INTF_SIF4 BIT(4) /*!< semaphore 04 interrupt is pending */
#define HWSEM_INTF_SIF5 BIT(5) /*!< semaphore 05 interrupt is pending */
#define HWSEM_INTF_SIF6 BIT(6) /*!< semaphore 06 interrupt is pending */
#define HWSEM_INTF_SIF7 BIT(7) /*!< semaphore 07 interrupt is pending */
#define HWSEM_INTF_SIF8 BIT(8) /*!< semaphore 08 interrupt is pending */
#define HWSEM_INTF_SIF9 BIT(9) /*!< semaphore 09 interrupt is pending */
#define HWSEM_INTF_SIF10 BIT(10) /*!< semaphore 10 interrupt is pending */
#define HWSEM_INTF_SIF11 BIT(11) /*!< semaphore 11 interrupt is pending */
#define HWSEM_INTF_SIF12 BIT(12) /*!< semaphore 12 interrupt is pending */
#define HWSEM_INTF_SIF13 BIT(13) /*!< semaphore 13 interrupt is pending */
#define HWSEM_INTF_SIF14 BIT(14) /*!< semaphore 14 interrupt is pending */
#define HWSEM_INTF_SIF15 BIT(15) /*!< semaphore 15 interrupt is pending */
#define HWSEM_INTF_SIF16 BIT(16) /*!< semaphore 16 interrupt is pending */
#define HWSEM_INTF_SIF17 BIT(17) /*!< semaphore 17 interrupt is pending */
#define HWSEM_INTF_SIF18 BIT(18) /*!< semaphore 18 interrupt is pending */
#define HWSEM_INTF_SIF19 BIT(19) /*!< semaphore 19 interrupt is pending */
#define HWSEM_INTF_SIF20 BIT(20) /*!< semaphore 20 interrupt is pending */
#define HWSEM_INTF_SIF21 BIT(21) /*!< semaphore 21 interrupt is pending */
#define HWSEM_INTF_SIF22 BIT(22) /*!< semaphore 22 interrupt is pending */
#define HWSEM_INTF_SIF23 BIT(23) /*!< semaphore 23 interrupt is pending */
#define HWSEM_INTF_SIF24 BIT(24) /*!< semaphore 24 interrupt is pending */
#define HWSEM_INTF_SIF25 BIT(25) /*!< semaphore 25 interrupt is pending */
#define HWSEM_INTF_SIF26 BIT(26) /*!< semaphore 26 interrupt is pending */
#define HWSEM_INTF_SIF27 BIT(27) /*!< semaphore 27 interrupt is pending */
#define HWSEM_INTF_SIF28 BIT(28) /*!< semaphore 28 interrupt is pending */
#define HWSEM_INTF_SIF29 BIT(29) /*!< semaphore 29 interrupt is pending */
#define HWSEM_INTF_SIF30 BIT(30) /*!< semaphore 30 interrupt is pending */
#define HWSEM_INTF_SIF31 BIT(31) /*!< semaphore 31 interrupt is pending */
/* HWSEM_UNLK */
#define HWSEM_UNLK_MID BITS(8,11) /*!< bus master ID to clear */
#define HWSEM_UNLK_KEY BITS(16,31) /*!< HWSEM semaphore unlock key */
/* HWSEM_KEY */
#define HWSEM_KEY_KEY BITS(16,31) /*!< key for unlocking all semaphores of a bus master */
/* constants definitions */
/* HWSEM register address */
#define HWSEM_CTL(sem) REG32(((HWSEM) + 0x0U) + 0x4U * (sem)) /*!< the address of HWSEM semaphore control register */
#define HWSEM_RLK(sem) REG32(((HWSEM) + 0x80U) + 0x4U * (sem)) /*!< the address of HWSEM semaphore read lock register */
/* semaphore index */
typedef enum {
SEM0 = 0U, /*!< semaphore 0 */
SEM1, /*!< semaphore 1 */
SEM2, /*!< semaphore 2 */
SEM3, /*!< semaphore 3 */
SEM4, /*!< semaphore 4 */
SEM5, /*!< semaphore 5 */
SEM6, /*!< semaphore 6 */
SEM7, /*!< semaphore 7 */
SEM8, /*!< semaphore 8 */
SEM9, /*!< semaphore 9 */
SEM10, /*!< semaphore 10 */
SEM11, /*!< semaphore 11 */
SEM12, /*!< semaphore 12 */
SEM13, /*!< semaphore 13 */
SEM14, /*!< semaphore 14 */
SEM15, /*!< semaphore 15 */
SEM16, /*!< semaphore 16 */
SEM17, /*!< semaphore 17 */
SEM18, /*!< semaphore 18 */
SEM19, /*!< semaphore 19 */
SEM20, /*!< semaphore 20 */
SEM21, /*!< semaphore 21 */
SEM22, /*!< semaphore 22 */
SEM23, /*!< semaphore 23 */
SEM24, /*!< semaphore 24 */
SEM25, /*!< semaphore 25 */
SEM26, /*!< semaphore 26 */
SEM27, /*!< semaphore 27 */
SEM28, /*!< semaphore 28 */
SEM29, /*!< semaphore 29 */
SEM30, /*!< semaphore 30 */
SEM31 /*!< semaphore 31 */
} hwsem_semaphore_enum;
/* hwsem_ctlx register */
#define CTL_PID(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to HWSEM_CTL_PID bit field */
#define GET_CTL_PID(regval) GET_BITS((regval),0,7) /*!< get value of HWSEM_CTL_PID bit field */
#define CTL_MID(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to HWSEM_CTL_MID bit field */
#define GET_CTL_MID(regval) GET_BITS((regval),8,11) /*!< get value of HWSEM_CTL_MID bit field */
#define HWSEM_LOCK HWSEM_CTL_LK /*!< HWSEM semaphore locked */
/* hwsem_unlk register */
#define UNLK_MID(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to HWSEM_CTL_PID bit field */
#define UNLK_KEY(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))/*!< write value to HWSEM_CTL_PID bit field */
/* hwsem_key register */
#define KEY_KEY(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))/*!< write value to HWSEM_CTL_PID bit field */
#define GET_KEY_KEY(regval) GET_BITS((regval),16,31) /*!< get value of HWSEM_CTL_PID bit field */
/* AHB bus master ID */
#define HWSEM_MASTER_ID 0x0BU /*!< core CM7 master ID */
/* function declarations */
/* lock & unlock functions */
/* try to lock the specific semaphore by writing process ID */
ErrStatus hwsem_lock_set(hwsem_semaphore_enum semaphore, uint8_t process);
/* try to release the lock of the semaphore by writing process ID */
ErrStatus hwsem_lock_release(hwsem_semaphore_enum semaphore, uint8_t process);
/* try to lock the semaphore by reading */
ErrStatus hwsem_lock_by_reading(hwsem_semaphore_enum semaphore);
/* unlock all semaphores of the master ID */
ErrStatus hwsem_unlock_all(uint16_t key);
/* others */
/* get process ID of the specific semaphore */
uint32_t hwsem_process_id_get(hwsem_semaphore_enum semaphore);
/* get master ID of the specific semaphore */
uint32_t hwsem_master_id_get(hwsem_semaphore_enum semaphore);
/* get the lock status of the semaphore */
FlagStatus hwsem_lock_status_get(hwsem_semaphore_enum semaphore);
/* set the key */
void hwsem_key_set(uint16_t key);
/* get the key */
uint16_t hwsem_key_get(void);
/* flag and interrupt functions */
/* get the HWSEM flag status */
FlagStatus hwsem_flag_get(hwsem_semaphore_enum semaphore);
/* clear HWSEM flag status */
void hwsem_flag_clear(hwsem_semaphore_enum semaphore);
/* get HWSEM interrupt flag status */
FlagStatus hwsem_interrupt_flag_get(hwsem_semaphore_enum semaphore);
/* clear HWSEM interrupt flag */
void hwsem_interrupt_flag_clear(hwsem_semaphore_enum semaphore);
/* enable HWSEM interrupt */
void hwsem_interrupt_enable(hwsem_semaphore_enum semaphore);
/* disable HWSEM interrupt */
void hwsem_interrupt_disable(hwsem_semaphore_enum semaphore);
#endif /* GD32H7XX_HWSEM_H */

408
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_i2c.h Normal file
View File

@@ -0,0 +1,408 @@
/*!
\file gd32h7xx_i2c.h
\brief definitions for the I2C
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_I2C_H
#define GD32H7XX_I2C_H
#include "gd32h7xx.h"
/* I2Cx(x=0,1,2,3) definitions */
#define I2C0 I2C_BASE /*!< I2C0 base address */
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
#define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */
#define I2C3 (I2C_BASE + 0x00000800U) /*!< I2C3 base address */
/* registers definitions */
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
#define I2C_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */
#define I2C_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */
#define I2C_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */
#define I2C_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear register */
#define I2C_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */
#define I2C_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data register */
#define I2C_TDATA(i2cx) REG32((i2cx) + 0x00000028U) /*!< I2C transmit data register */
#define I2C_CTL2(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C control register 2 */
/* bits definitions */
/* I2Cx_CTL0 */
#define I2C_CTL0_I2CEN BIT(0) /*!< I2C peripheral enable */
#define I2C_CTL0_TIE BIT(1) /*!< transmit interrupt enable */
#define I2C_CTL0_RBNEIE BIT(2) /*!< receive interrupt enable */
#define I2C_CTL0_ADDMIE BIT(3) /*!< address match interrupt enable in slave mode */
#define I2C_CTL0_NACKIE BIT(4) /*!< not acknowledge received interrupt enable */
#define I2C_CTL0_STPDETIE BIT(5) /*!< stop detection interrupt enable */
#define I2C_CTL0_TCIE BIT(6) /*!< transfer complete interrupt enable */
#define I2C_CTL0_ERRIE BIT(7) /*!< error interrupt enable */
#define I2C_CTL0_DNF BITS(8,11) /*!< digital noise filter */
#define I2C_CTL0_ANOFF BIT(12) /*!< analog noise filter */
#define I2C_CTL0_DENT BIT(14) /*!< DMA enable for transmission */
#define I2C_CTL0_DENR BIT(15) /*!< DMA enable for reception */
#define I2C_CTL0_SBCTL BIT(16) /*!< slave byte control */
#define I2C_CTL0_SS BIT(17) /*!< whether to stretch SCL low when data is not ready in slave mode */
#define I2C_CTL0_WUEN BIT(18) /*!< wakeup from deep-sleep mode enable */
#define I2C_CTL0_GCEN BIT(19) /*!< whether or not to response to a general call (0x00) */
#define I2C_CTL0_SMBHAEN BIT(20) /*!< SMBus host address enable */
#define I2C_CTL0_SMBDAEN BIT(21) /*!< SMBus device default address enable */
#define I2C_CTL0_SMBALTEN BIT(22) /*!< SMBus alert enable */
#define I2C_CTL0_PECEN BIT(23) /*!< PEC calculation switch */
/* I2Cx_CTL1 */
#define I2C_CTL1_SADDRESS BITS(0,9) /*!< slave address to be sent */
#define I2C_CTL1_TRDIR BIT(10) /*!< transfer direction in master mode */
#define I2C_CTL1_ADD10EN BIT(11) /*!< 10-bit addressing mode enable in master mode */
#define I2C_CTL1_HEAD10R BIT(12) /*!< 10-bit address header executes read direction only in master receive mode */
#define I2C_CTL1_START BIT(13) /*!< generate a START condition on I2C bus */
#define I2C_CTL1_STOP BIT(14) /*!< generate a STOP condition on I2C bus */
#define I2C_CTL1_NACKEN BIT(15) /*!< generate NACK in slave mode */
#define I2C_CTL1_BYTENUM BITS(16,23) /*!< number of bytes to be transferred */
#define I2C_CTL1_RELOAD BIT(24) /*!< reload mode enable */
#define I2C_CTL1_AUTOEND BIT(25) /*!< automatic end mode in master mode */
#define I2C_CTL1_PECTRANS BIT(26) /*!< PEC transfer */
/* I2Cx_SADDR0 */
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
#define I2C_SADDR0_ADDFORMAT BIT(10) /*!< address mode for the I2C slave */
#define I2C_SADDR0_ADDRESSEN BIT(15) /*!< I2C address enable */
/* I2Cx_SADDR1 */
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave */
#define I2C_SADDR1_ADDMSK2 BITS(8,10) /*!< ADDRESS2[7:1] mask */
#define I2C_SADDR1_ADDRESS2EN BIT(15) /*!< second I2C address enable */
/* I2Cx_TIMING */
#define I2C_TIMING_SCLL BITS(0,7) /*!< SCL low period */
#define I2C_TIMING_SCLH BITS(8,15) /*!< SCL high period */
#define I2C_TIMING_SDADELY BITS(16,19) /*!< data hold time */
#define I2C_TIMING_SCLDELY BITS(20,23) /*!< data setup time */
#define I2C_TIMING_PSC BITS(28,31) /*!< timing prescaler */
/* I2Cx_TIMEOUT */
#define I2C_TIMEOUT_BUSTOA BITS(0,11) /*!< bus timeout A */
#define I2C_TIMEOUT_TOIDLE BIT(12) /*!< idle clock timeout detection */
#define I2C_TIMEOUT_TOEN BIT(15) /*!< clock timeout detection enable */
#define I2C_TIMEOUT_BUSTOB BITS(16,27) /*!< bus timeout B */
#define I2C_TIMEOUT_EXTOEN BIT(31) /*!< extended clock timeout detection enable */
/* I2Cx_STAT */
#define I2C_STAT_TBE BIT(0) /*!< I2C_TDATA is empty during transmitting */
#define I2C_STAT_TI BIT(1) /*!< transmit interrupt */
#define I2C_STAT_RBNE BIT(2) /*!< I2C_RDATA is not empty during receiving */
#define I2C_STAT_ADDSEND BIT(3) /*!< address received matches in slave mode */
#define I2C_STAT_NACK BIT(4) /*!< not acknowledge flag */
#define I2C_STAT_STPDET BIT(5) /*!< STOP condition detected in slave mode */
#define I2C_STAT_TC BIT(6) /*!< transfer complete in master mode */
#define I2C_STAT_TCR BIT(7) /*!< transfer complete reload */
#define I2C_STAT_BERR BIT(8) /*!< bus error */
#define I2C_STAT_LOSTARB BIT(9) /*!< arbitration lost */
#define I2C_STAT_OUERR BIT(10) /*!< overrun/underrun error in slave mode */
#define I2C_STAT_PECERR BIT(11) /*!< PEC error */
#define I2C_STAT_TIMEOUT BIT(12) /*!< timeout flag */
#define I2C_STAT_SMBALT BIT(13) /*!< SMBus alert */
#define I2C_STAT_I2CBSY BIT(15) /*!< busy flag */
#define I2C_STAT_TR BIT(16) /*!< whether the I2C is a transmitter or a receiver in slave mode */
#define I2C_STAT_READDR BITS(17,23) /*!< received match address in slave mode */
/* I2Cx_STATC */
#define I2C_STATC_ADDSENDC BIT(3) /*!< ADDSEND flag clear */
#define I2C_STATC_NACKC BIT(4) /*!< not acknowledge flag clear */
#define I2C_STATC_STPDETC BIT(5) /*!< STPDET flag clear */
#define I2C_STATC_BERRC BIT(8) /*!< bus error flag clear */
#define I2C_STATC_LOSTARBC BIT(9) /*!< arbitration Lost flag clear */
#define I2C_STATC_OUERRC BIT(10) /*!< overrun/underrun flag clear */
#define I2C_STATC_PECERRC BIT(11) /*!< PEC error flag clear */
#define I2C_STATC_TIMEOUTC BIT(12) /*!< TIMEOUT flag clear */
#define I2C_STATC_SMBALTC BIT(13) /*!< SMBus alert flag clear */
/* I2Cx_PEC */
#define I2C_PEC_PECV BITS(0,7) /*!< Packet Error Checking Value that calculated by hardware when PEC is enabled */
/* I2Cx_RDATA */
#define I2C_RDATA_RDATA BITS(0,7) /*!< receive data value */
/* I2Cx_TDATA */
#define I2C_TDATA_TDATA BITS(0,7) /*!< transmit data value */
/* I2Cx_CTL2 */
#define I2C_CTL2_ADDM BITS(9,15) /*!< address bits compare select */
/* constants definitions */
/* define the I2C bit position and its register index offset */
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define I2C_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
#define I2C_STAT_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT register offset */
/* I2C interrupt flags */
typedef enum {
I2C_INT_FLAG_TI = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 1U, I2C_STAT_REG_OFFSET, 1U), /*!< transmit interrupt flag */
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 2U, I2C_STAT_REG_OFFSET, 2U), /*!< I2C_RDATA is not empty during receiving interrupt flag */
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 3U, I2C_STAT_REG_OFFSET, 3U), /*!< address received matches in slave mode interrupt flag */
I2C_INT_FLAG_NACK = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 4U, I2C_STAT_REG_OFFSET, 4U), /*!< not acknowledge interrupt flag */
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 5U, I2C_STAT_REG_OFFSET, 5U), /*!< stop condition detected in slave mode interrupt flag */
I2C_INT_FLAG_TC = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 6U), /*!< transfer complete in master mode interrupt flag */
I2C_INT_FLAG_TCR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 7U), /*!< transfer complete reload interrupt flag */
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 8U), /*!< bus error interrupt flag */
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 9U), /*!< arbitration lost interrupt flag */
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 10U), /*!< overrun/underrun error in slave mode interrupt flag */
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 11U), /*!< PEC error interrupt flag */
I2C_INT_FLAG_TIMEOUT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 12U), /*!< timeout interrupt flag */
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 13U) /*!< SMBus Alert interrupt flag */
} i2c_interrupt_flag_enum;
/* I2C DMA constants definitions */
#define I2C_DMA_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C transmit data use DMA */
#define I2C_DMA_RECEIVE ((uint32_t)0x00000001U) /*!< I2C receive data use DMA */
/* I2C interrupt enable or disable */
#define I2C_INT_ERR I2C_CTL0_ERRIE /*!< error interrupt enable */
#define I2C_INT_TC I2C_CTL0_TCIE /*!< transfer complete interrupt enable */
#define I2C_INT_STPDET I2C_CTL0_STPDETIE /*!< stop detection interrupt enable */
#define I2C_INT_NACK I2C_CTL0_NACKIE /*!< not acknowledge received interrupt enable */
#define I2C_INT_ADDM I2C_CTL0_ADDMIE /*!< address match interrupt enable */
#define I2C_INT_RBNE I2C_CTL0_RBNEIE /*!< receive interrupt enable */
#define I2C_INT_TI I2C_CTL0_TIE /*!< transmit interrupt enable */
/* I2C transfer direction in master mode */
#define I2C_MASTER_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C master transmit */
#define I2C_MASTER_RECEIVE I2C_CTL1_TRDIR /*!< I2C master receive */
/* address mode for the I2C slave */
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
/* the length of filter spikes */
#define FILTER_DISABLE ((uint32_t)0x00000000U) /*!< digital filter is disabled */
#define FILTER_LENGTH_1 ((uint32_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK */
#define FILTER_LENGTH_2 ((uint32_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK */
#define FILTER_LENGTH_3 ((uint32_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK */
#define FILTER_LENGTH_4 ((uint32_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK */
#define FILTER_LENGTH_5 ((uint32_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK */
#define FILTER_LENGTH_6 ((uint32_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK */
#define FILTER_LENGTH_7 ((uint32_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK */
#define FILTER_LENGTH_8 ((uint32_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK */
#define FILTER_LENGTH_9 ((uint32_t)0x00000009U) /*!< digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK */
#define FILTER_LENGTH_10 ((uint32_t)0x0000000AU) /*!< digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK */
#define FILTER_LENGTH_11 ((uint32_t)0x0000000BU) /*!< digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK */
#define FILTER_LENGTH_12 ((uint32_t)0x0000000CU) /*!< digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK */
#define FILTER_LENGTH_13 ((uint32_t)0x0000000DU) /*!< digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK */
#define FILTER_LENGTH_14 ((uint32_t)0x0000000EU) /*!< digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK */
#define FILTER_LENGTH_15 ((uint32_t)0x0000000FU) /*!< digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK */
/* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */
#define ADDRESS_BIT1_COMPARE ((uint32_t)0x00000200U) /*!< address bit1 needs compare */
#define ADDRESS_BIT2_COMPARE ((uint32_t)0x00000400U) /*!< address bit2 needs compare */
#define ADDRESS_BIT3_COMPARE ((uint32_t)0x00000800U) /*!< address bit3 needs compare */
#define ADDRESS_BIT4_COMPARE ((uint32_t)0x00001000U) /*!< address bit4 needs compare */
#define ADDRESS_BIT5_COMPARE ((uint32_t)0x00002000U) /*!< address bit5 needs compare */
#define ADDRESS_BIT6_COMPARE ((uint32_t)0x00004000U) /*!< address bit6 needs compare */
#define ADDRESS_BIT7_COMPARE ((uint32_t)0x00008000U) /*!< address bit7 needs compare */
/* defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (do not care) */
#define ADDRESS2_NO_MASK ((uint32_t)0x00000000U) /*!< no mask, all the bits must be compared */
#define ADDRESS2_MASK_BIT1 ((uint32_t)0x00000001U) /*!< ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared */
#define ADDRESS2_MASK_BIT1_2 ((uint32_t)0x00000002U) /*!< ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared */
#define ADDRESS2_MASK_BIT1_3 ((uint32_t)0x00000003U) /*!< ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared */
#define ADDRESS2_MASK_BIT1_4 ((uint32_t)0x00000004U) /*!< ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared */
#define ADDRESS2_MASK_BIT1_5 ((uint32_t)0x00000005U) /*!< ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared */
#define ADDRESS2_MASK_BIT1_6 ((uint32_t)0x00000006U) /*!< ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared */
#define ADDRESS2_MASK_ALL ((uint32_t)0x00000007U) /*!< all the ADDRESS2[7:1] bits are masked */
/* idle clock timeout detection */
#define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */
#define BUSTOA_DETECT_IDLE I2C_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */
/* I2C flag definitions */
#define I2C_FLAG_TBE I2C_STAT_TBE /*!< I2C_TDATA is empty during transmitting */
#define I2C_FLAG_TI I2C_STAT_TI /*!< transmit interrupt */
#define I2C_FLAG_RBNE I2C_STAT_RBNE /*!< I2C_RDATA is not empty during receiving */
#define I2C_FLAG_ADDSEND I2C_STAT_ADDSEND /*!< address received matches in slave mode */
#define I2C_FLAG_NACK I2C_STAT_NACK /*!< not acknowledge flag */
#define I2C_FLAG_STPDET I2C_STAT_STPDET /*!< STOP condition detected in slave mode */
#define I2C_FLAG_TC I2C_STAT_TC /*!< transfer complete in master mode */
#define I2C_FLAG_TCR I2C_STAT_TCR /*!< transfer complete reload */
#define I2C_FLAG_BERR I2C_STAT_BERR /*!< bus error */
#define I2C_FLAG_LOSTARB I2C_STAT_LOSTARB /*!< arbitration lost */
#define I2C_FLAG_OUERR I2C_STAT_OUERR /*!< overrun/underrun error in slave mode */
#define I2C_FLAG_PECERR I2C_STAT_PECERR /*!< PEC error */
#define I2C_FLAG_TIMEOUT I2C_STAT_TIMEOUT /*!< timeout flag */
#define I2C_FLAG_SMBALT I2C_STAT_SMBALT /*!< SMBus Alert */
#define I2C_FLAG_I2CBSY I2C_STAT_I2CBSY /*!< busy flag */
#define I2C_FLAG_TR I2C_STAT_TR /*!< whether the I2C is a transmitter or a receiver in slave mode */
/* function declarations */
/* initialization functions */
/* reset I2C */
void i2c_deinit(uint32_t i2c_periph);
/* configure the timing parameters */
void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely);
/* configure digital noise filter */
void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length);
/* enable analog noise filter */
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
/* disable analog noise filter */
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
/* configure the SCL high and low period of clock in master mode */
void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll);
/* configure I2C slave address and transfer direction in master mode */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction);
/* application function declarations */
/* 10-bit address header executes read direction only in master receive mode */
void i2c_address10_header_enable(uint32_t i2c_periph);
/* 10-bit address header executes complete sequence in master receive mode */
void i2c_address10_header_disable(uint32_t i2c_periph);
/* enable 10-bit addressing mode in master mode */
void i2c_address10_enable(uint32_t i2c_periph);
/* disable 10-bit addressing mode in master mode */
void i2c_address10_disable(uint32_t i2c_periph);
/* enable I2C automatic end mode in master mode */
void i2c_automatic_end_enable(uint32_t i2c_periph);
/* disable I2C automatic end mode in master mode */
void i2c_automatic_end_disable(uint32_t i2c_periph);
/* enable the response to a general call */
void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph);
/* disable the response to a general call */
void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph);
/* enable to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_enable(uint32_t i2c_periph);
/* disable to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_disable(uint32_t i2c_periph);
/* configure I2C slave address */
void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format);
/* define which bits of ADDRESS[7:1] need to compare with the incoming address byte */
void i2c_address_bit_compare_config(uint32_t i2c_periph, uint32_t compare_bits);
/* disable I2C address in slave mode */
void i2c_address_disable(uint32_t i2c_periph);
/* configure I2C second slave address */
void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask);
/* disable I2C second address in slave mode */
void i2c_second_address_disable(uint32_t i2c_periph);
/* get received match address in slave mode */
uint32_t i2c_recevied_address_get(uint32_t i2c_periph);
/* enable slave byte control */
void i2c_slave_byte_control_enable(uint32_t i2c_periph);
/* disable slave byte control */
void i2c_slave_byte_control_disable(uint32_t i2c_periph);
/* generate a NACK in slave mode */
void i2c_nack_enable(uint32_t i2c_periph);
/* generate an ACK in slave mode */
void i2c_nack_disable(uint32_t i2c_periph);
/* enable wakeup from deep-sleep mode */
void i2c_wakeup_from_deepsleep_enable(uint32_t i2c_periph);
/* disable wakeup from deep-sleep mode */
void i2c_wakeup_from_deepsleep_disable(uint32_t i2c_periph);
/* enable I2C */
void i2c_enable(uint32_t i2c_periph);
/* disable I2C */
void i2c_disable(uint32_t i2c_periph);
/* generate a START condition on I2C bus */
void i2c_start_on_bus(uint32_t i2c_periph);
/* generate a STOP condition on I2C bus */
void i2c_stop_on_bus(uint32_t i2c_periph);
/* I2C transmit data */
void i2c_data_transmit(uint32_t i2c_periph, uint32_t data);
/* I2C receive data */
uint32_t i2c_data_receive(uint32_t i2c_periph);
/* enable I2C reload mode */
void i2c_reload_enable(uint32_t i2c_periph);
/* disable I2C reload mode */
void i2c_reload_disable(uint32_t i2c_periph);
/* configure number of bytes to be transferred */
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number);
/* enable I2C DMA for transmission or reception */
void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma);
/* disable I2C DMA for transmission or reception */
void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma);
/* I2C transfers PEC value */
void i2c_pec_transfer(uint32_t i2c_periph);
/* enable I2C PEC calculation */
void i2c_pec_enable(uint32_t i2c_periph);
/* disable I2C PEC calculation */
void i2c_pec_disable(uint32_t i2c_periph);
/* get packet error checking value */
uint32_t i2c_pec_value_get(uint32_t i2c_periph);
/* enable SMBus alert */
void i2c_smbus_alert_enable(uint32_t i2c_periph);
/* disable SMBus alert */
void i2c_smbus_alert_disable(uint32_t i2c_periph);
/* enable SMBus device default address */
void i2c_smbus_default_addr_enable(uint32_t i2c_periph);
/* disable SMBus device default address */
void i2c_smbus_default_addr_disable(uint32_t i2c_periph);
/* enable SMBus host address */
void i2c_smbus_host_addr_enable(uint32_t i2c_periph);
/* disable SMBus host address */
void i2c_smbus_host_addr_disable(uint32_t i2c_periph);
/* enable extended clock timeout detection */
void i2c_extented_clock_timeout_enable(uint32_t i2c_periph);
/* disable extended clock timeout detection */
void i2c_extented_clock_timeout_disable(uint32_t i2c_periph);
/* enable clock timeout detection */
void i2c_clock_timeout_enable(uint32_t i2c_periph);
/* disable clock timeout detection */
void i2c_clock_timeout_disable(uint32_t i2c_periph);
/* configure bus timeout B */
void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout);
/* configure bus timeout A */
void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout);
/* configure idle clock timeout detection */
void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout);
/* interrupt & flag functions */
/* get I2C flag status */
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag);
/* clear I2C flag status */
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag);
/* enable I2C interrupt */
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt);
/* disable I2C interrupt */
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt);
/* get I2C interrupt flag status */
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
/* clear I2C interrupt flag status */
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
#endif /* GD32H7XX_I2C_H */

479
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ipa.h Normal file
View File

@@ -0,0 +1,479 @@
/*!
\file gd32h7xx_ipa.h
\brief definitions for the IPA
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_IPA_H
#define GD32H7XX_IPA_H
#include "gd32h7xx.h"
/* IPA definitions */
#define IPA IPA_BASE /*!< IPA base address */
/* bits definitions */
/* registers definitions */
#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */
#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */
#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */
#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */
#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */
#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */
#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */
#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */
#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */
#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */
#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */
#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */
#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */
#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */
#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */
#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */
#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */
#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */
#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */
#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */
#define IPA_BSCTL REG32(IPA + 0x00000050U) /*!< IPA bilinear scaling control register */
#define IPA_DIMS REG32(IPA + 0x00000054U) /*!< IPA scaling image size register */
#define IPA_EF_UV_MADDR REG32(IPA + 0x0000005CU) /*!< IPA foreground even frame/UV memory base address register */
#define IPA_CSCC_CFG0 REG32(IPA + 0x00000060U) /*!< IPA color space conversion coefficient 0 */
#define IPA_CSCC_CFG1 REG32(IPA + 0x00000064U) /*!< IPA color space conversion coefficient 1 */
#define IPA_CSCC_CFG2 REG32(IPA + 0x00000068U) /*!< IPA color space conversion coefficient 2 */
/* IPA_CTL */
#define IPA_CTL_TEN BIT(0) /*!< transfer enable */
#define IPA_CTL_THU BIT(1) /*!< transfer hang up */
#define IPA_CTL_TST BIT(2) /*!< transfer stop */
#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */
#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */
#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */
#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */
#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */
#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */
#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */
/* IPA_INTF */
#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */
#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */
#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */
#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */
#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */
#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */
/* IPA_INTC */
#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */
#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */
#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */
#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */
#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */
#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */
/* IPA_FMADDR */
#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */
/* IPA_FLOFF */
#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */
/* IPA_BMADDR */
#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */
/* IPA_BLOFF */
#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */
/* IPA_FPCTL */
#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */
#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */
#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */
#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */
#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */
#define IPA_FPCTL_FIIMEN BIT(23) /*!< foreground input interlace mode enable */
#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre-defined alpha value */
/* IPA_FPV */
#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */
#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */
#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */
/* IPA_BPCTL */
#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */
#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */
#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */
#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */
#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */
#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre-defined alpha value */
/* IPA_BPV */
#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */
#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */
#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */
/* IPA_FLMADDR */
#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */
/* IPA_BLMADDR */
#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */
/* IPA_DPCTL */
#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */
#define IPA_DPCTL_ROT BITS(8,9) /*!< destination image rotation angle */
#define IPA_DPCTL_HORDEC BITS(16,17) /*!< destination horizontal pre decimation filter control */
#define IPA_DPCTL_VERDEC BITS(18,19) /*!< destination verticle pre decimation filter control */
/* IPA_DPV */
/* destination pixel format ARGB8888 */
#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */
#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */
#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */
#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */
/* destination pixel format RGB888 */
#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */
#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */
#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */
/* destination pixel format RGB565 */
#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */
#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */
#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */
/* destination pixel format ARGB1555 */
#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */
#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */
#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */
#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */
/* destination pixel format ARGB4444 */
#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */
#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */
#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */
#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */
/* IPA_DMADDR */
#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */
/* IPA_DLOFF */
#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */
/* IPA_IMS */
#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */
#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */
/* IPA_LM */
#define IPA_LM_LM BITS(0,15) /*!< line mark */
/* IPA_ITCTL */
#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */
#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */
/* IPA_BSCTL */
#define IPA_BSCTL_XSCALE BITS(0,13) /*!< foreground X scaling factor */
#define IPA_BSCTL_YSCALE BITS(16,29) /*!< foreground Y scaling factor */
/* IPA_DIMS */
#define IPA_DIMS_DHEIGHT BITS(0,15) /*!< destination height after scaling */
#define IPA_DIMS_DWIDTH BITS(16,29) /*!< destination width after scaling */
/* IPA_EF_UV_MADDR */
#define IPA_EF_UV_MADDR_EFUVMADDR BITS(0,31) /*!< foreground even frame/UV memory base address */
/* IPA_CSCC_CFG0 */
#define IPA_CSCC_CFG0_YOFF BITS(0,8) /*!< offset implicit in the Y data */
#define IPA_CSCC_CFG0_UVOFF BITS(9,17) /*!< offset implicit in the UV data */
#define IPA_CSCC_CFG0_C0 BITS(18,28) /*!< Y multiplier coefficient */
#define IPA_CSCC_CFG0_CONVMOD BIT(31) /*!< color space convert mode */
/* IPA_CSCC_CFG1 */
#define IPA_CSCC_CFG1_C4 BITS(0,10) /*!< blue U/Cb multiplier coefficient */
#define IPA_CSCC_CFG1_C1 BITS(16,26) /*!< red V/Cr multiplier coefficient */
/* IPA_CSCC_CFG2 */
#define IPA_CSCC_CFG2_C3 BITS(0,10) /*!< green U/Cb multiplier coefficient */
#define IPA_CSCC_CFG2_C2 BITS(16,26) /*!< green V/Cr multiplier coefficient */
/* constants definitions */
/* IPA foreground parameter struct definitions */
typedef struct {
uint32_t foreground_memaddr; /*!< foreground memory base address */
uint32_t foreground_lineoff; /*!< foreground line offset */
uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */
uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */
uint32_t foreground_pf; /*!< foreground pixel format */
uint32_t foreground_prered; /*!< foreground pre-defined red value */
uint32_t foreground_pregreen; /*!< foreground pre-defined green value */
uint32_t foreground_preblue; /*!< foreground pre-defined blue value */
uint32_t foreground_interlace_mode; /*!< foreground input interlace mode enable */
uint32_t foreground_efuv_memaddr; /*!< foreground even frame / UV memory base address */
} ipa_foreground_parameter_struct;
/* IPA background parameter struct definitions */
typedef struct {
uint32_t background_memaddr; /*!< background memory base address */
uint32_t background_lineoff; /*!< background line offset */
uint32_t background_prealpha; /*!< background pre-defined alpha value */
uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */
uint32_t background_pf; /*!< background pixel format */
uint32_t background_prered; /*!< background pre-defined red value */
uint32_t background_pregreen; /*!< background pre-defined green value */
uint32_t background_preblue; /*!< background pre-defined blue value */
} ipa_background_parameter_struct;
/* IPA destination parameter struct definitions */
typedef struct {
uint32_t destination_memaddr; /*!< destination memory base address */
uint32_t destination_lineoff; /*!< destination line offset */
uint32_t destination_prealpha; /*!< destination pre-defined alpha value */
uint32_t destination_pf; /*!< destination pixel format */
uint32_t destination_prered; /*!< destination pre-defined red value */
uint32_t destination_pregreen; /*!< destination pre-defined green value */
uint32_t destination_preblue; /*!< destination pre-defined blue value */
uint32_t image_width; /*!< width of the image to be processed */
uint32_t image_height; /*!< height of the image to be processed */
uint32_t image_rotate; /*!< angle of image rotation */
uint32_t image_hor_decimation; /*!< image horizontal pre-decimation in width */
uint32_t image_ver_decimation; /*!< image vertical pre-decimation in height */
uint32_t image_bilinear_xscale; /*!< bilinear scaling x factor */
uint32_t image_bilinear_yscale; /*!< bilinear scaling y factor */
uint32_t image_scaling_width; /*!< width of the image after scaling */
uint32_t image_scaling_height; /*!< height of the image after scaling */
} ipa_destination_parameter_struct;
/* destination pixel format */
typedef enum {
IPA_DPF_ARGB8888 = 0U, /*!< destination pixel format ARGB8888 */
IPA_DPF_RGB888, /*!< destination pixel format RGB888 */
IPA_DPF_RGB565, /*!< destination pixel format RGB565 */
IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */
IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */
} ipa_dpf_enum;
/* IPA color conversion parameter struct definitions */
typedef struct {
uint32_t color_space; /*!< color space convert mode */
uint32_t y_offset; /*!< offset implicit in the Y data */
uint32_t uv_offset; /*!< offset implicit in the UV data */
uint32_t coef_c0; /*!< Y multiplier coefficient */
uint32_t coef_c1; /*!< V/Cr red multiplier coefficient */
uint32_t coef_c2; /*!< V/Cr green multiplier coefficient */
uint32_t coef_c3; /*!< U/Cb green multiplier coefficient */
uint32_t coef_c4; /*!< U/Cb blue multiplier coefficient */
} ipa_conversion_parameter_struct;
/* destination pixel format */
typedef enum {
IPA_COLORSPACE_YUV = 0U, /*!< IPA color conversion using YUV parameter */
IPA_COLORSPACE_YCBCR /*!< IPA color conversion using YCbCr parameter */
} ipa_colorspace_enum;
/* LUT pixel format */
#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */
#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */
/* Inter-timer */
#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */
#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */
/* IPA pixel format convert mode */
#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U))
#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */
#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */
#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */
#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */
/* foreground alpha value calculation algorithm */
#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U))
#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */
#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */
#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */
/* background alpha value calculation algorithm */
#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U))
#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */
#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */
#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */
/* foreground pixel format */
#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */
#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */
#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */
#define FOREGROUND_PPF_ARGB1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */
#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */
#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */
#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */
#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */
#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */
#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */
#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */
#define FOREGROUND_PPF_YUV444_1P FPCTL_PPF(11) /*!< foreground pixel format YUV444 */
#define FOREGROUND_PPF_UYVY422_1P FPCTL_PPF(12) /*!< foreground pixel format UYVY422 1 plane */
#define FOREGROUND_PPF_VYUY422_1P FPCTL_PPF(13) /*!< foreground pixel format VYUY422 1 plane */
#define FOREGROUND_PPF_YUV420_2P FPCTL_PPF(14) /*!< foreground pixel format YUV420 2 plane */
#define FOREGROUND_PPF_YVU420_2P FPCTL_PPF(15) /*!< foreground pixel format YVU420 2 plane */
/* background pixel format */
#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */
#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */
#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */
#define BACKGROUND_PPF_ARGB1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */
#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */
#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */
#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */
#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */
#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */
#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */
#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */
/* rotation angle */
#define DPCTL_ROT(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U))
#define DESTINATION_ROTATE_0 DPCTL_ROT(0) /*!< destination rotate 0 degree */
#define DESTINATION_ROTATE_90 DPCTL_ROT(1) /*!< destination rotate 90 degree */
#define DESTINATION_ROTATE_180 DPCTL_ROT(2) /*!< destination rotate 180 degree */
#define DESTINATION_ROTATE_270 DPCTL_ROT(3) /*!< destination rotate 270 degree */
/* vertical pre-decimation filter control */
#define DPCTL_HORDEC(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U))
#define DESTINATION_HORDECIMATE_DISABLE DPCTL_HORDEC(0) /*!< disable horizontal decimate */
#define DESTINATION_HORDECIMATE_2 DPCTL_HORDEC(1) /*!< horizontal decimated by 2 */
#define DESTINATION_HORDECIMATE_4 DPCTL_HORDEC(2) /*!< horizontal decimated by 4 */
#define DESTINATION_HORDECIMATE_8 DPCTL_HORDEC(3) /*!< horizontal decimated by 8 */
/* horizontal pre-decimation filter control */
#define DPCTL_VERDEC(regval) (BITS(18,19) & ((uint32_t)(regval) << 18U))
#define DESTINATION_VERDECIMATE_DISABLE DPCTL_VERDEC(0) /*!< disable verticle decimate */
#define DESTINATION_VERDECIMATE_2 DPCTL_VERDEC(1) /*!< verticle decimated by 2 */
#define DESTINATION_VERDECIMATE_4 DPCTL_VERDEC(2) /*!< verticle decimated by 4 */
#define DESTINATION_VERDECIMATE_8 DPCTL_VERDEC(3) /*!< verticle decimated by 8 */
/* IPA flags */
#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
/* IPA interrupt enable or disable */
#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */
#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */
#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */
#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */
#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */
#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */
/* IPA interrupt flags */
#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
/* function declarations */
/* functions enable or disable, pixel format convert mode set */
/* deinitialize IPA registers */
void ipa_deinit(void);
/* enable IPA transfer */
void ipa_transfer_enable(void);
/* enable IPA transfer hang up */
void ipa_transfer_hangup_enable(void);
/* disable IPA transfer hang up */
void ipa_transfer_hangup_disable(void);
/* enable IPA transfer stop */
void ipa_transfer_stop_enable(void);
/* disable IPA transfer stop */
void ipa_transfer_stop_disable(void);
/* enable IPA foreground LUT loading */
void ipa_foreground_lut_loading_enable(void);
/* enable IPA background LUT loading */
void ipa_background_lut_loading_enable(void);
/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */
void ipa_pixel_format_convert_mode_set(uint32_t pfcm);
/* enable foreground interlace mode */
void ipa_foreground_interlace_mode_enable(void);
/* disable foreground interlace mode */
void ipa_foreground_interlace_mode_disable(void);
/* structure initialization, foreground, background, destination and LUT initialization */
/* initialize the structure of IPA foreground parameter struct with the default values, it is
suggested that call this function after an ipa_foreground_parameter_struct structure is defined */
void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct);
/* initialize foreground parameters */
void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct);
/* initialize the structure of IPA background parameter struct with the default values, it is
suggested that call this function after an ipa_background_parameter_struct structure is defined */
void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct);
/* initialize background parameters */
void ipa_background_init(ipa_background_parameter_struct *background_struct);
/* initialize the structure of IPA destination parameter struct with the default values, it is
suggested that call this function after an ipa_destination_parameter_struct structure is defined */
void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct);
/* initialize destination parameters */
void ipa_destination_init(ipa_destination_parameter_struct *destination_struct);
/* initialize IPA foreground LUT parameters */
void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr);
/* initialize IPA background LUT parameters */
void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr);
/* configuration functions */
/* configure IPA line mark */
void ipa_line_mark_config(uint16_t line_num);
/* inter-timer enable or disable */
void ipa_inter_timer_config(uint8_t timer_cfg);
/* configure the number of clock cycles interval */
void ipa_interval_clock_num_config(uint8_t clk_num);
/* initialize the structure of IPA color conversion parameter struct with the YUV or YCbCr conversion parameter,
it is suggested that call this function after an ipa_conversion_parameter_struct structure is defined */
void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct *conversion_struct, ipa_colorspace_enum colorspace);
/* configure the color space conversion parameter */
void ipa_color_conversion_config(ipa_conversion_parameter_struct *conversion_struct);
/* configure IPA foreground scaling, including horizontal/vertical pre-decimation factors and X/Y scaling factors */
void ipa_foreground_scaling_config(uint32_t horizontal_decimation, uint32_t vertical_decimation, uint32_t image_scaling_width,
uint32_t image_scaling_height);
/* configure IPA destination scaling, including width/height of image to be processed */
void ipa_destination_scaling_config(uint32_t dest_scaling_width, uint32_t dest_scaling_height);
/* flag and interrupt functions */
/* get IPA flag status in IPA_INTF register */
FlagStatus ipa_flag_get(uint32_t flag);
/* clear IPA flag in IPA_INTF register */
void ipa_flag_clear(uint32_t flag);
/* enable IPA interrupt */
void ipa_interrupt_enable(uint32_t int_flag);
/* disable IPA interrupt */
void ipa_interrupt_disable(uint32_t int_flag);
/* get IPA interrupt flag */
FlagStatus ipa_interrupt_flag_get(uint32_t int_flag);
/* clear IPA interrupt flag */
void ipa_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H7XX_IPA_H */

195
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_lpdts.h Normal file
View File

@@ -0,0 +1,195 @@
/*!
\file gd32h7xx_lpdts.h
\brief definitions for the LPDTS
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_LPDTS_H
#define GD32H7XX_LPDTS_H
#include "gd32h7xx.h"
/* LPDTS definitions */
#define LPDTS LPDTS_BASE
/* registers definitions */
#define LPDTS_CFG REG32(LPDTS + 0x00000000U) /*!< LPDTS configuration register */
#define LPDTS_SDATA REG32(LPDTS + 0x00000008U) /*!< LPDTS sensor T0 data register */
#define LPDTS_RDATA REG32(LPDTS + 0x00000010U) /*!< LPDTS ramp data register */
#define LPDTS_IT REG32(LPDTS + 0x00000014U) /*!< LPDTS interrupt threshold register */
#define LPDTS_DATA REG32(LPDTS + 0x0000001CU) /*!< LPDTS temperature data register */
#define LPDTS_STAT REG32(LPDTS + 0x00000020U) /*!< LPDTS temperature sensor status register */
#define LPDTS_INTEN REG32(LPDTS + 0x00000024U) /*!< LPDTS interrupt enable register */
#define LPDTS_INTC REG32(LPDTS + 0x00000028U) /*!< LPDTS interrupt clear flag register */
#define LPDTS_OP REG32(LPDTS + 0x0000002CU) /*!< LPDTS option register */
/* bits definitions */
/* LPDTS_CFG */
#define LPDTS_CFG_TSEN BIT(0) /*!< temperature sensor enable */
#define LPDTS_CFG_TRGS BIT(4) /*!< software trigger */
#define LPDTS_CFG_ITSEL BITS(8,11) /*!< input trigger selection */
#define LPDTS_CFG_SPT BITS(16,19) /*!< sampling time */
#define LPDTS_CFG_REFSEL BIT(20) /*!< reference clock selection */
/* LPDTS_SDATA */
#define LPDTS_SDATA_FREQ BITS(0,15) /*!< frequency value at temperature T0 */
#define LPDTS_SDATA_VAL BITS(16,17) /*!< temperature T0 */
/* LPDTS_RDATA */
#define LPDTS_RDATA_RCVAL BITS(0,15) /*!< ramp coefficient */
/* LPDTS_IT */
#define LPDTS_IT_INTLT BITS(0,15) /*!< interrupt low threshold */
#define LPDTS_IT_INTHT BITS(16,31) /*!< interrupt high threshold */
/* LPDTS_DATA */
#define LPDTS_DATA_COVAL BITS(0,15) /*!< value of the counter output */
/* LPDTS_STAT */
#define LPDTS_STAT_EMIF BIT(0) /*!< end of measurement interrupt flag */
#define LPDTS_STAT_LTIF BIT(1) /*!< low threshold interrupt flag */
#define LPDTS_STAT_HTIF BIT(2) /*!< high threshold interrupt flag */
#define LPDTS_STAT_EMAIF BIT(4) /*!< end of measurement asynchronous interrupt flag */
#define LPDTS_STAT_LTAIF BIT(5) /*!< low threshold asynchronous interrupt flag */
#define LPDTS_STAT_HTAIF BIT(6) /*!< high threshold asynchronous interrupt flag */
#define LPDTS_STAT_TSRF BIT(15) /*!< temperature sensor ready flag */
/* LPDTS_INTEN */
#define LPDTS_INTEN_EMIE BIT(0) /*!< end of measurement interrupt enable */
#define LPDTS_INTEN_LTIE BIT(1) /*!< low threshold interrupt enable */
#define LPDTS_INTEN_HTIE BIT(2) /*!< high threshold interrupt enable */
#define LPDTS_INTEN_EMAIE BIT(4) /*!< end of measurement asynchronous interrupt enable */
#define LPDTS_INTEN_LTAIE BIT(5) /*!< low threshold asynchronous interrupt enable */
#define LPDTS_INTEN_HTAIE BIT(6) /*!< high threshold asynchronous interrupt enable */
/* LPDTS_INTC */
#define LPDTS_INTC_EMIC BIT(0) /*!< end of measurement interrupt clear */
#define LPDTS_INTC_LTIC BIT(1) /*!< low threshold interrupt clear */
#define LPDTS_INTC_HTIC BIT(2) /*!< high threshold interrupt clear */
#define LPDTS_INTC_EMAIC BIT(4) /*!< end of measure asynchronous interrupt clear */
#define LPDTS_INTC_LTAIC BIT(5) /*!< low threshold asynchronous interrupt clear */
#define LPDTS_INTC_HTAIC BIT(6) /*!< high threshold asynchronous interrupt clear */
/* LPDTS_OP */
#define LPDTS_OP_OP BITS(0,31) /*!< general purpose option */
/* constants definitions */
/* parameter struct definitions */
typedef struct {
uint32_t ref_clock; /*!< reference clock selection */
uint32_t trigger_input; /*!< input trigger selection */
uint32_t sampling_time; /*!< sampling time */
} lpdts_parameter_struct;
/* reference clock definitions */
#define REF_PCLK ((uint32_t)0x00000000U) /*!< high speed reference clock (PCLK) */
#define REF_LXTAL LPDTS_CFG_REFSEL /*!< low speed reference clock (LXTAL) */
/* input trigger selection definitions */
#define TRIGGER_SEL(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
#define NO_HARDWARE_TRIGGER TRIGGER_SEL(0) /*!< no hardware trigger signal */
#define LPDTS_TRG TRIGGER_SEL(4) /*!< select LPDTS_TRG as trigger signal */
/* sampling time definitions */
#define SMP_TIME(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
#define SPT_CLOCK_1 SMP_TIME(1) /*!< 1 LXTAL or FM(T) clocks */
#define SPT_CLOCK_2 SMP_TIME(2) /*!< 2 LXTAL or FM(T) clocks */
#define SPT_CLOCK_3 SMP_TIME(3) /*!< 3 LXTAL or FM(T) clocks */
#define SPT_CLOCK_4 SMP_TIME(4) /*!< 4 LXTAL or FM(T) clocks */
#define SPT_CLOCK_5 SMP_TIME(5) /*!< 5 LXTAL or FM(T) clocks */
#define SPT_CLOCK_6 SMP_TIME(6) /*!< 6 LXTAL or FM(T) clocks */
#define SPT_CLOCK_7 SMP_TIME(7) /*!< 7 LXTAL or FM(T) clocks */
#define SPT_CLOCK_8 SMP_TIME(8) /*!< 8 LXTAL or FM(T) clocks */
#define SPT_CLOCK_9 SMP_TIME(9) /*!< 9 LXTAL or FM(T) clocks */
#define SPT_CLOCK_10 SMP_TIME(10) /*!< 10 LXTAL or FM(T) clocks */
#define SPT_CLOCK_11 SMP_TIME(11) /*!< 11 LXTAL or FM(T) clocks */
#define SPT_CLOCK_12 SMP_TIME(12) /*!< 12 LXTAL or FM(T) clocks */
#define SPT_CLOCK_13 SMP_TIME(13) /*!< 13 LXTAL or FM(T) clocks */
#define SPT_CLOCK_14 SMP_TIME(14) /*!< 14 LXTAL or FM(T) clocks */
#define SPT_CLOCK_15 SMP_TIME(15) /*!< 15 LXTAL or FM(T) clocks */
/* LPDTS flags */
#define LPDTS_FLAG_TSR LPDTS_STAT_TSRF /*!< temperature sensor ready flag */
#define LPDTS_INT_FLAG_EM LPDTS_STAT_EMIF /*!< end of measurement interrupt flag */
#define LPDTS_INT_FLAG_LT LPDTS_STAT_LTIF /*!< low threshold interrupt flag */
#define LPDTS_INT_FLAG_HT LPDTS_STAT_HTIF /*!< high threshold interrupt flag */
#define LPDTS_INT_FLAG_EMA LPDTS_STAT_EMAIF /*!< end of measurement asynchronous interrupt flag */
#define LPDTS_INT_FLAG_LTA LPDTS_STAT_LTAIF /*!< low threshold asynchronous interrupt flag */
#define LPDTS_INT_FLAG_HTA LPDTS_STAT_HTAIF /*!< high threshold asynchronous interrupt flag */
/* LPDTS interrupt enable */
#define LPDTS_INT_EM LPDTS_INTEN_EMIE /*!< end of measurement interrupt enable */
#define LPDTS_INT_LT LPDTS_INTEN_LTIE /*!< low threshold interrupt enable */
#define LPDTS_INT_HT LPDTS_INTEN_HTIE /*!< high threshold interrupt enable */
#define LPDTS_INT_EMA LPDTS_INTEN_EMAIE /*!< end of measurement asynchronous interrupt enable */
#define LPDTS_INT_LTA LPDTS_INTEN_LTAIE /*!< low threshold asynchronous interrupt enable */
#define LPDTS_INT_HTA LPDTS_INTEN_HTAIE /*!< high threshold asynchronous interrupt enable */
/* function declarations */
/* initialization functions */
/* reset the LPDTS registers */
void lpdts_deinit(void);
/* initialize the parameters of LPDTS struct with the default values */
void lpdts_struct_para_init(lpdts_parameter_struct *init_struct);
/* initialize the LPDTS */
void lpdts_init(lpdts_parameter_struct *init_struct);
/* configuration functions */
/* enable LPDTS temperature sensor */
void lpdts_enable(void);
/* disable LPDTS temperature sensor */
void lpdts_disable(void);
/* enable LPDTS software trigger */
void lpdts_soft_trigger_enable(void);
/* disable LPDTS software trigger */
void lpdts_soft_trigger_disable(void);
/* configure LPDTS high threshold value */
void lpdts_high_threshold_set(uint16_t value);
/* configure LPDTS low threshold value */
void lpdts_low_threshold_set(uint16_t value);
/* configure LPDTS reference clock selection */
void lpdts_ref_clock_source_config(uint32_t source);
/* get temperature from LPDTS */
int32_t lpdts_temperature_get(void);
/* flag and interrupt functions */
/* get LPDTS flag */
FlagStatus lpdts_flag_get(uint32_t flag);
/* enable LPDTS interrupt */
void lpdts_interrupt_enable(uint32_t interrupt);
/* disable LPDTS interrupt */
void lpdts_interrupt_disable(uint32_t interrupt);
/* get LPDTS interrupt flag */
FlagStatus lpdts_interrupt_flag_get(uint32_t flag);
/* clear the LPDTS interrupt flag */
void lpdts_interrupt_flag_clear(uint32_t flag);
#endif /* GD32H7XX_LPDTS_H */

236
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_mdio.h Normal file
View File

@@ -0,0 +1,236 @@
/*!
\file gd32h7xx_mdio.h
\brief definitions for the MDIO
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_MDIO_H
#define GD32H7XX_MDIO_H
#include "gd32h7xx.h"
/* MDIO definitions */
#define MDIO MDIO_BASE /*!< MDIO base address */
/* registers definitions */
#define MDIO_CTL REG32((MDIO) + 0x00000000U) /*!< MDIO control register */
#define MDIO_RFRM REG32((MDIO) + 0x00000004U) /*!< MDIO received frame information register */
#define MDIO_RDATA REG32((MDIO) + 0x00000008U) /*!< MDIO received data register */
#define MDIO_RADDR REG32((MDIO) + 0x0000000CU) /*!< MDIO received address register */
#define MDIO_TDATA REG32((MDIO) + 0x00000010U) /*!< MDIO transfer data register */
#define MDIO_CFG REG32((MDIO) + 0x00000014U) /*!< MDIO configuration register */
#define MDIO_STAT REG32((MDIO) + 0x00000018U) /*!< MDIO status register */
#define MDIO_INTEN REG32((MDIO) + 0x0000001CU) /*!< MDIO interrupt enable register */
#define MDIO_PIN REG32((MDIO) + 0x00000020U) /*!< MDIO pin value register */
#define MDIO_TO REG32((MDIO) + 0x00000024U) /*!< MDIO timeout register */
/* bits definitions */
/* MDIO_CTL */
#define MDIO_CTL_SWRST BIT(0) /*!< reset MDIO block */
#define MDIO_CTL_PHYB BIT(1) /*!< MDIO PHY bit length */
/* MDIO_RFRM */
#define MDIO_RFRM_ROP BITS(0,1) /*!< received frame field OP */
#define MDIO_RFRM_RPHY BITS(2,6) /*!< received frame field PHYADR */
#define MDIO_RFRM_RDEV BITS(7,11) /*!< received frame field DEVADD */
#define MDIO_RFRM_RTA BITS(12,13) /*!< received frame field TA */
/* MDIO_RDATA */
#define MDIO_RDATA_RDATA BITS(0,15) /*!< received frame field DATA */
/* MDIO_RADDR */
#define MDIO_RADDR_RADDR BITS(0,15) /*!< received frame field ADDRESS */
/* MDIO_TDATA */
#define MDIO_TDATA_TDATA BITS(0,15) /*!< data that is transmitted */
/* MDIO_CFG */
#define MDIO_CFG_PHYSW BITS(0,4) /*!< software provided PHYADR */
#define MDIO_CFG_EPHYSEL BITS(5,9) /*!< selects expected PHYADR */
#define MDIO_CFG_EDEVADD BITS(10,14) /*!< expected DEVADD */
/* MDIO_STAT */
#define MDIO_STAT_WRFRM BIT(0) /*!< set at end bit of a write data frame if DEVADD and PHYADR both match */
#define MDIO_STAT_ADDRFRM BIT(1) /*!< set at end bit of an address frame if DEVADD and PHYADR both match */
#define MDIO_STAT_RDINCFRM BIT(2) /*!< set at end bit of a post read increment address frame if DEVADD and PHYADR both match */
#define MDIO_STAT_RDFRM BIT(3) /*!< set at end bit of a read data frame if DEVADD and PHYADR both match */
#define MDIO_STAT_DEVM BIT(4) /*!< set at end bit of DEVADD if DEVADD matches */
#define MDIO_STAT_DEVNM BIT(5) /*!< set at end bit of DEVADD if DEVADD nonmatches */
#define MDIO_STAT_PHYM BIT(6) /*!< set at end bit of PHYADR if PHYADR matches */
#define MDIO_STAT_PHYNM BIT(7) /*!< set at end bit of PHYADR if PHYADR nonmatches */
#define MDIO_STAT_TANM BIT(8) /*!< set at end bit of TA of a write frame if the received TA nonmatches expected <20><>10<31><30> */
#define MDIO_STAT_TO BIT(9) /*!< timeout flag */
#define MDIO_STAT_UDR BIT(10) /*!< transmit underrun flag */
#define MDIO_STAT_OVR BIT(11) /*!< receive overrun flag */
#define MDIO_STAT_RBNE BIT(13) /*!< read data buffer not empty flag */
/* MDIO_INTEN */
#define MDIO_INTEN_WRFRMIE BIT(0) /*!< interrupt requested when WRFRM bit becomes active */
#define MDIO_INTEN_ADDRFRMIE BIT(1) /*!< interrupt requested when ADDRFRM bit becomes active */
#define MDIO_INTEN_RDINCFRMIE BIT(2) /*!< interrupt requested when RDINCFRM bit becomes active */
#define MDIO_INTEN_RDFRMIE BIT(3) /*!< interrupt requested when RDFRM bit becomes active */
#define MDIO_INTEN_DEVMIE BIT(4) /*!< interrupt requested when DEVM bit becomes active */
#define MDIO_INTEN_DEVNMIE BIT(5) /*!< interrupt requested when DEVNM bit becomes active */
#define MDIO_INTEN_PHYMIE BIT(6) /*!< interrupt requested when PHYM bit becomes active */
#define MDIO_INTEN_PHYNMIE BIT(7) /*!< interrupt requested when PHYNM bit becomes active */
#define MDIO_INTEN_TANMIE BIT(8) /*!< interrupt requested when TANM bit becomes active */
#define MDIO_INTEN_TOIE BIT(9) /*!< interrupt requested when TO bit becomes active */
#define MDIO_INTEN_UDRIE BIT(10) /*!< interrupt requested when UDR bit becomes active */
#define MDIO_INTEN_OVRIE BIT(11) /*!< interrupt requested when OVR bit becomes active */
#define MDIO_INTEN_RBNEIE BIT(13) /*!< interrupt requested when RBNE bit becomes active */
/* MDIO_PIN */
#define MDIO_PIN_PHYPIN BITS(0,4) /*!< pin value read from hardware PRTADR[4:0] pins */
/* MDIO_TO */
#define MDIO_TO_TOEN BIT(0) /*!< timeout enable */
#define MDIO_TO_TOCNT BITS(1,16) /*!< timeout counter */
/* constants definitions */
/* MDIO PHY bit length definitions */
#define MDIO_PHY_BITS_3 MDIO_CTL_PHYB /*!< MDIO PHY uses 3 bits */
#define MDIO_PHY_BITS_5 ((uint32_t)0x00000000U) /*!< MDIO PHY uses 5 bits */
/* software provided PHYADR configuration definitions */
#define CFG_PHYSW(regval) (BITS(0,4)&((uint32_t)(regval) << 0U))
/* expected PHYADR selection definitions */
#define CFG_EPHYSEL(regval) (BITS(5,9)&((uint32_t)(regval) << 5U))
#define MDIO_PHYADR_HARDWARE ((uint32_t)0x00000000U) /*!< sets expected PHYADR = PHYPIN[4:0] */
#define MDIO_PHYADR_SOFTWARE ((uint32_t)0x0000001FU) /*!< sets expected PHYADR = PHYSW[4:0] */
#define MDIO_PHYADR_HW_SW_MIX(regval) (BITS(0,4)&((uint32_t)(regval)))/*!< software PHYADR bit select */
/* expected DEVADD configuration definitions */
#define CFG_EDEVADD(regval) (BITS(10,14)&((uint32_t)(regval) << 10U))
/* get value of register bit field */
#define GET_RFRM_ROP(regval) GET_BITS((regval),0,1) /*!< get value of MDIO_RFRM_ROP bit field */
#define GET_RFRM_RPHY(regval) GET_BITS((regval),2,6) /*!< get value of MDIO_RFRM_RPHY bit field */
#define GET_RFRM_RDEV(regval) GET_BITS((regval),7,11) /*!< get value of MDIO_RFRM_RDEV bit field */
#define GET_RFRM_RTA(regval) GET_BITS((regval),12,13) /*!< get value of MDIO_RFRM_RTA bit field */
#define GET_RDATA_RDATA(regval) GET_BITS((regval),0,15) /*!< get value of MDIO_RDATA_RDATA bit field */
#define GET_RADDR_RADDR(regval) GET_BITS((regval),0,15) /*!< get value of MDIO_RADDR_RADDR bit field */
#define GET_PIN_PHYPIN(regval) GET_BITS((regval),0,4) /*!< get value of MDIO_PIN_PHYPIN bit field */
/* expected timeout configuration definitions */
#define TO_TOCNT(regval) (BITS(1,16)&((uint32_t)(regval) << 1U))
/* MDIO flag definitions */
#define MDIO_FLAG_WRFRM MDIO_STAT_WRFRM /*!< a write data frame flag status */
#define MDIO_FLAG_ADDRFRM MDIO_STAT_ADDRFRM /*!< an address frame flag status */
#define MDIO_FLAG_RDINCFRM MDIO_STAT_RDINCFRM /*!< a post read increment address frame flag status */
#define MDIO_FLAG_RDFRM MDIO_STAT_RDFRM /*!< a read data frame flag status */
#define MDIO_FLAG_DEVM MDIO_STAT_DEVM /*!< a DEVADD match frame flag status */
#define MDIO_FLAG_DEVNM MDIO_STAT_DEVNM /*!< a DEVADD nonmatch frame flag status */
#define MDIO_FLAG_PHYM MDIO_STAT_PHYM /*!< a PHYADR match frame flag status */
#define MDIO_FLAG_PHYNM MDIO_STAT_PHYNM /*!< a PHYADR nonmatch frame flag status */
#define MDIO_FLAG_TANM MDIO_STAT_TANM /*!< a TA nonmatch frame flag status */
#define MDIO_FLAG_TIMEOUT MDIO_STAT_TO /*!< timeout flag */
#define MDIO_FLAG_TX_UNDERRUN MDIO_STAT_UDR /*!< transmit underrun flag */
#define MDIO_FLAG_RX_OVERRUN MDIO_STAT_OVR /*!< receive overrun flag */
#define MDIO_FLAG_RBNE MDIO_STAT_RBNE /*!< read data buffer not empty flag */
/* MDIO interrupt definitions */
#define MDIO_INT_WRFRM MDIO_INTEN_WRFRMIE /*!< a write data frame interrupt */
#define MDIO_INT_ADDRFRM MDIO_INTEN_ADDRFRMIE /*!< an address frame interrupt */
#define MDIO_INT_RDINCFRM MDIO_INTEN_RDINCFRMIE /*!< a post read increment address frame interrupt */
#define MDIO_INT_RDFRM MDIO_INTEN_RDFRMIE /*!< a read data frame interrupt */
#define MDIO_INT_DEVM MDIO_INTEN_DEVMIE /*!< a DEVADD match frame interrupt */
#define MDIO_INT_DEVNM MDIO_INTEN_DEVNMIE /*!< a DEVADD nonmatch frame interrupt */
#define MDIO_INT_PHYM MDIO_INTEN_PHYMIE /*!< a PHYADR match frame interrupt */
#define MDIO_INT_PHYNM MDIO_INTEN_PHYNMIE /*!< a PHYADR nonmatch frame interrupt */
#define MDIO_INT_TANM MDIO_INTEN_TANMIE /*!< a TA nonmatch frame interrupt */
#define MDIO_INT_TIMEOUT MDIO_INTEN_TOIE /*!< a timeout interrupt */
#define MDIO_INT_TX_UNDERRUN MDIO_INTEN_UDRIE /*!< a transmit underrun interrupt */
#define MDIO_INT_RX_OVERRUN MDIO_INTEN_OVRIE /*!< a receive overrun interrupt */
#define MDIO_INT_RBNE MDIO_INTEN_RBNEIE /*!< a read data buffer not empty interrupt */
/* device type definitions */
#define DEVADD_PMA_PMD ((uint16_t)0x0001U) /*!< device type PMA/PMD */
#define DEVADD_WIS ((uint16_t)0x0002U) /*!< device type WIS */
#define DEVADD_PCS ((uint16_t)0x0003U) /*!< device type PCS */
#define DEVADD_PHY_XS ((uint16_t)0x0004U) /*!< device type PHY XS */
#define DEVADD_DTE_XS ((uint16_t)0x0005U) /*!< device type DTE XS */
/* function declarations */
/* reset functions */
/* reset MDIO */
void mdio_deinit(void);
/* reset MDIO block */
void mdio_software_reset(void);
/* fuction configuration */
/* initialize MDIO for communication */
uint32_t mdio_init(uint32_t phy_size, uint32_t phy_softaddr, uint32_t phy_sel, uint16_t devadd);
/* configure MDIO phy bit length */
void mdio_phy_length_config(uint32_t phy_bit);
/* set the software PHYADR value */
void mdio_soft_phyadr_set(uint32_t phy_soft);
/* select the expected frame field PHYADR */
void mdio_framefield_phyadr_config(uint32_t phy_sel);
/* configure the expected frame field DEVADD */
void mdio_framefield_devadd_config(uint16_t type);
/* read the hardware PRTADR[4:0] value */
uint32_t mdio_phy_pin_read(void);
/* configure the expected frame bit timeout */
void mdio_timeout_config(uint16_t timeout);
/* enable MDIO frame bit timeout */
void mdio_timeout_enable(void);
/* disable MDIO frame bit timeout */
void mdio_timeout_disable(void);
/* rx & tx functions */
/* read the received frame field OP */
uint16_t mdio_op_receive(void);
/* read the received frame field PHYADR */
uint16_t mdio_phyadr_receive(void);
/* read the received frame field DEVADD */
uint16_t mdio_devadd_receive(void);
/* read the received frame field TA */
uint16_t mdio_ta_receive(void);
/* read the received frame field DATA */
uint16_t mdio_data_receive(void);
/* read the received frame field ADDRESS */
uint16_t mdio_address_receive(void);
/* transmit the frame field DATA */
void mdio_data_transmit(uint16_t data);
/* interrupt & flag functions */
/* get the flag status of the frame */
FlagStatus mdio_flag_get(uint32_t flag);
/* clear MDIO flag status */
void mdio_flag_clear(uint32_t flag);
/* enable MDIO interrupt */
void mdio_interrupt_enable(uint32_t interrupt);
/* disable MDIO interrupt */
void mdio_interrupt_disable(uint32_t interrupt);
#endif /* GD32H7XX_MDIO_H */

480
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_mdma.h Normal file
View File

@@ -0,0 +1,480 @@
/*!
\file gd32h7xx_mdma.h
\brief definitions for the MDMA
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_MDMA_H
#define GD32H7XX_MDMA_H
#include "gd32h7xx.h"
/* MDMA definitions */
#define MDMA (MDMA_BASE) /*!< MDMA base address */
/* registers definitions */
#define MDMA_GINTF REG32(MDMA + 0x00000000U) /*!< MDMA global interrupt flag register */
#define MDMA_CHXSTAT0(mdma_chx) REG32(MDMA + 0x00000040U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 0 */
#define MDMA_CHXSTATC(mdma_chx) REG32(MDMA + 0x00000044U + (0x40U * (mdma_chx))) /*!< MDMA channel x status clear register */
#define MDMA_CHXSTAT1(mdma_chx) REG32(MDMA + 0x00000048U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 1*/
#define MDMA_CHXCTL0(mdma_chx) REG32(MDMA + 0x0000004CU + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 0 */
#define MDMA_CHXCFG(mdma_chx) REG32(MDMA + 0x00000050U + (0x40U * (mdma_chx))) /*!< MDMA channel x configure register */
#define MDMA_CHXBTCFG(mdma_chx) REG32(MDMA + 0x00000054U + (0x40U * (mdma_chx))) /*!< MDMA channel x block transfer configure register */
#define MDMA_CHXSADDR(mdma_chx) REG32(MDMA + 0x00000058U + (0x40U * (mdma_chx))) /*!< MDMA channel x source address register */
#define MDMA_CHXDADDR(mdma_chx) REG32(MDMA + 0x0000005CU + (0x40U * (mdma_chx))) /*!< MDMA channel x destination address register */
#define MDMA_CHXMBADDRU(mdma_chx) REG32(MDMA + 0x00000060U + (0x40U * (mdma_chx))) /*!< MDMA channel x multi-block address update register */
#define MDMA_CHXLADDR(mdma_chx) REG32(MDMA + 0x00000064U + (0x40U * (mdma_chx))) /*!< MDMA channel x link address register */
#define MDMA_CHXCTL1(mdma_chx) REG32(MDMA + 0x00000068U + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 1 */
#define MDMA_CHXMADDR(mdma_chx) REG32(MDMA + 0x00000070U + (0x40U * (mdma_chx))) /*!< MDMA channel x mask address register */
#define MDMA_CHXMDATA(mdma_chx) REG32(MDMA + 0x00000074U + (0x40U * (mdma_chx))) /*!< MDMA channel x mask data register */
/* bits definitions */
/* MDMA_GINTF */
#define MDMA_GINTF_GIF0 BIT(0) /*!< global interrupt flag of channel 0 */
#define MDMA_GINTF_GIF1 BIT(1) /*!< global interrupt flag of channel 1 */
#define MDMA_GINTF_GIF2 BIT(2) /*!< global interrupt flag of channel 2 */
#define MDMA_GINTF_GIF3 BIT(3) /*!< global interrupt flag of channel 3 */
#define MDMA_GINTF_GIF4 BIT(4) /*!< global interrupt flag of channel 4 */
#define MDMA_GINTF_GIF5 BIT(5) /*!< global interrupt flag of channel 5 */
#define MDMA_GINTF_GIF6 BIT(6) /*!< global interrupt flag of channel 6 */
#define MDMA_GINTF_GIF7 BIT(7) /*!< global interrupt flag of channel 7 */
#define MDMA_GINTF_GIF8 BIT(8) /*!< global interrupt flag of channel 8 */
#define MDMA_GINTF_GIF9 BIT(9) /*!< global interrupt flag of channel 9 */
#define MDMA_GINTF_GIF10 BIT(10) /*!< global interrupt flag of channel 10 */
#define MDMA_GINTF_GIF11 BIT(11) /*!< global interrupt flag of channel 11 */
#define MDMA_GINTF_GIF12 BIT(12) /*!< global interrupt flag of channel 12 */
#define MDMA_GINTF_GIF13 BIT(13) /*!< global interrupt flag of channel 13 */
#define MDMA_GINTF_GIF14 BIT(14) /*!< global interrupt flag of channel 14 */
#define MDMA_GINTF_GIF15 BIT(15) /*!< global interrupt flag of channel 15 */
/* MDMA_CHxSTAT0,x=0..15 */
#define MDMA_CHXSTAT0_ERR BIT(0) /*!< channel x transfer error flag */
#define MDMA_CHXSTAT0_CHTCF BIT(1) /*!< channel x channel transfer complete flag */
#define MDMA_CHXSTAT0_MBTCF BIT(2) /*!< channel x multi-block transfer complete flag */
#define MDMA_CHXSTAT0_BTCF BIT(3) /*!< channel x block transfer complete flag */
#define MDMA_CHXSTAT0_TCF BIT(4) /*!< channel x buffer transfer complete flag */
#define MDMA_CHXSTAT0_REQAF BIT(16) /*!< channel x request active flag */
/* MDMA_CHxSTATC,x=0..15 */
#define MDMA_CHXSTATC_ERRC BIT(0) /*!< channel x transfer error flag clear */
#define MDMA_CHXSTATC_CHTCFC BIT(1) /*!< channel x channel transfer complete flag clear */
#define MDMA_CHXSTATC_MBTCFC BIT(2) /*!< channel x multi-block transfer complete flag clear */
#define MDMA_CHXSTATC_BTCFC BIT(3) /*!< channel x block transfer complete flag clear */
#define MDMA_CHXSTATC_TCFC BIT(4) /*!< channel x buffer transfer complete flag clear */
/* MDMA_CHxSTAT1,x=0..15 */
#define MDMA_CHXSTAT1_ERRADDR BITS(0,6) /*!< transfer error address */
#define MDMA_CHXSTAT1_TERRD BIT(7) /*!< transfer error direction */
#define MDMA_CHXSTAT1_LDTERR BIT(8) /*!< link data transfer error flag in the last transfer of the channel */
#define MDMA_CHXSTAT1_MDTERR BIT(9) /*!< mask data error flag */
#define MDMA_CHXSTAT1_ASERR BIT(10) /*!< address and size error flag */
#define MDMA_CHXSTAT1_BZERR BIT(11) /*!< block size error flag */
/* MDMA_CHxCTL0,x=0..15 */
#define MDMA_CHXCTL0_CHEN BIT(0) /*!< channel enable */
#define MDMA_CHXCTL0_ERRIE BIT(1) /*!< transfer error interrupt enable */
#define MDMA_CHXCTL0_CHTCIE BIT(2) /*!< channel transfer complete interrupt enable */
#define MDMA_CHXCTL0_MBTCIE BIT(3) /*!< multi-block transfer complete interrupt enable */
#define MDMA_CHXCTL0_BTCIE BIT(4) /*!< block transfer complete interrupt enable */
#define MDMA_CHXCTL0_TCIE BIT(5) /*!< buffer transfer complete interrupt enable */
#define MDMA_CHXCTL0_PRIO BITS(6,7) /*!< priority level */
#define MDMA_CHXCTL0_SMODEN BIT(8) /*!< secure mode enable */
#define MDMA_CHXCTL0_BES BIT(12) /*!< byte endianess swapping in half word */
#define MDMA_CHXCTL0_HWES BIT(13) /*!< half word endianess swapping in word */
#define MDMA_CHXCTL0_WES BIT(14) /*!< word endianess swapping in double word */
#define MDMA_CHXCTL0_SWREQ BIT(16) /*!< software request */
/* MDMA_CHxCFG,x=0..15 */
#define MDMA_CHXCFG_SIMOD BITS(0,1) /*!< source increment mode */
#define MDMA_CHXCFG_DIMOD BITS(2,3) /*!< destination increment mode */
#define MDMA_CHXCFG_SWIDTH BITS(4,5) /*!< data size of source */
#define MDMA_CHXCFG_DWIDTH BITS(6,7) /*!< data size of destination */
#define MDMA_CHXCFG_SIOS BITS(8,9) /*!< offset size of source increment */
#define MDMA_CHXCFG_DIOS BITS(10,11) /*!< offset size of destination increment */
#define MDMA_CHXCFG_SBURST BITS(12,14) /*!< transfer burst type of source */
#define MDMA_CHXCFG_DBURST BITS(15,17) /*!< transfer burst type of destination */
#define MDMA_CHXCFG_BTLEN BITS(18,24) /*!< buffer transfer length */
#define MDMA_CHXCFG_PKEN BIT(25) /*!< pack enable */
#define MDMA_CHXCFG_PAMOD BITS(26,27) /*!< padding and alignement mode */
#define MDMA_CHXCFG_TRIGMOD BITS(28,29) /*!< trigger mode */
#define MDMA_CHXCFG_SWREQMOD BIT(30) /*!< software request mode */
#define MDMA_CHXCFG_BWMOD BIT(31) /*!< bufferable write mode */
/* MDMA_CHxBTCFG,x=0..15 */
#define MDMA_CHXBTCFG_TBNUM BITS(0,16) /*!< transfer byte number in block */
#define MDMA_CHXBTCFG_SADDRUM BIT(18) /*!< multi-block source address update mode */
#define MDMA_CHXBTCFG_DADDRUM BIT(19) /*!< multi-block destination address update mode */
#define MDMA_CHXBTCFG_BRNUM BITS(20,31) /*!< multi-block number */
/* MDMA_CHxSADDR,x=0..15 */
#define MDMA_CHXSADDR_SADDR BITS(0,31) /*!< source address */
/* MDMA_CHxDADDR,x=0..15 */
#define MDMA_CHXDADDR_DADDR BITS(0,31) /*!< destination address */
/* MDMA_CHxMBADDRU,x=0..15 */
#define MDMA_CHXMBADDRU_SADDRUV BITS(0,15) /*!< source address update value */
#define MDMA_CHXMBADDRU_DADDRUV BITS(16,31) /*!< destination address update value */
/* MDMA_CHxLADDR,x=0..15 */
#define MDMA_CHXLADDR_LADDR BITS(0,31) /*!< link address */
/* MDMA_CHxCTL1,x=0..15 */
#define MDMA_CHXCTL1_TRIGSEL BITS(0,5) /*!< trigger select */
#define MDMA_CHXCTL1_SBSEL BIT(16) /*!< source bus select */
#define MDMA_CHXCTL1_DBSEL BIT(17) /*!< destination bus select */
/* MDMA_CHxMADDR,x=0..15 */
#define MDMA_CHXMADDR_MADDR BITS(0,31) /*!< mask address */
/* MDMA_CHxMDATA,x=0..15 */
#define MDMA_CHXMDATA_MDATA BITS(0,31) /*!< mask data */
/* constants definitions */
/* MDMA configuration structure definition */
typedef struct {
uint32_t request; /*!< specifies the MDMA request */
uint32_t trans_trig_mode; /*!< specifies the trigger transfer mode */
uint32_t priority; /*!< specifies the software priority for the MDMA channelx */
uint32_t endianness; /*!< specifies if the MDMA transactions preserve the little endianness */
uint32_t source_inc; /*!< specifies the source increment mode */
uint32_t dest_inc; /*!< specifies the destination increment mode */
uint32_t source_data_size; /*!< specifies the source data size */
uint32_t dest_data_dize; /*!< specifies the destination data size */
uint32_t data_alignment; /*!< specifies the source to destination memory data packing/padding mode */
uint32_t buff_trans_len; /*!< specifies the buffer transfer length (number of bytes) */
uint32_t source_burst; /*!< specifies the burst transfer configuration for the source memory transfers */
uint32_t dest_burst; /*!< specifies the burst transfer configuration for the destination memory transfers */
uint32_t mask_addr; /*!< mask address */
uint32_t mask_data; /*!< mask data */
uint32_t source_addr; /*!< specifies the source address */
uint32_t destination_addr; /*!< specifies the destination address */
uint32_t tbytes_num_in_block; /*!< specifies the transfer bytes number in a buffer or block transfer */
uint32_t source_bus; /*!< specifies the source bus */
uint32_t destination_bus; /*!< specifies the destination bus */
uint32_t bufferable_write_mode; /*!< specifies the bufferable write mode */
} mdma_parameter_struct;
/* MDMA address update direction */
typedef enum {
UPDATE_DIR_INCREASE = 0, /*!< MDMA address update increase */
UPDATE_DIR_DECREASE = 1, /*!< MDMA address update decrease */
} mdma_add_update_dir_enum;
/* MDMA multi block transfer configuration structure definition */
typedef struct {
uint32_t block_num; /*!< multi-block number */
uint16_t saddr_update_val; /*!< source address update value */
uint16_t dstaddr_update_val; /*!< destination address update value */
mdma_add_update_dir_enum saddr_update_dir; /*!< source address update direction */
mdma_add_update_dir_enum dstaddr_update_dir; /*!< destination address update direction */
} mdma_multi_block_parameter_struct;
/* MDMA link node configuration structure definition */
typedef struct {
__IO uint32_t chxcfg_reg; /*!< channel x configure register */
__IO uint32_t chxbtcfg_reg; /*!< channel x block transfer configure register */
__IO uint32_t chxsaddr_reg; /*!< channel x source address register */
__IO uint32_t chxdaddr_reg; /*!< channel x destination address register */
__IO uint32_t chxmbaddru_reg; /*!< channel x multi-block address update register */
__IO uint32_t chxladdr_reg; /*!< channel x link address register */
__IO uint32_t chxctl1_reg; /*!< channel x control register 1 */
__IO uint32_t reserved; /*!< channel x reserved register */
__IO uint32_t chxmaddr_reg; /*!< channel x mask address register */
__IO uint32_t chxmdata_reg; /*!< channel x mask data register */
} mdma_link_node_parameter_struct;
/* MDMA channel select */
typedef enum {
MDMA_CH0 = 0, /*!< MDMA channel 0 */
MDMA_CH1, /*!< MDMA channel 1 */
MDMA_CH2, /*!< MDMA channel 2 */
MDMA_CH3, /*!< MDMA channel 3 */
MDMA_CH4, /*!< MDMA channel 4 */
MDMA_CH5, /*!< MDMA channel 5 */
MDMA_CH6, /*!< MDMA channel 6 */
MDMA_CH7, /*!< MDMA channel 7 */
MDMA_CH8, /*!< MDMA channel 8 */
MDMA_CH9, /*!< MDMA channel 9 */
MDMA_CH10, /*!< MDMA channel 10 */
MDMA_CH11, /*!< MDMA channel 11 */
MDMA_CH12, /*!< MDMA channel 12 */
MDMA_CH13, /*!< MDMA channel 13 */
MDMA_CH14, /*!< MDMA channel 14 */
MDMA_CH15 /*!< MDMA channel 15 */
} mdma_channel_enum;
/* MDMA request selection */
#define CHXCTL1_TRIGSEL(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< trigger select */
#define MDMA_REQUEST_DMA0_CH0_FTFIF CHXCTL1_TRIGSEL(0) /*!< MDMA hardware request is DMA0 channel 0 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH1_FTFIF CHXCTL1_TRIGSEL(1) /*!< MDMA hardware request is DMA0 channel 1 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH2_FTFIF CHXCTL1_TRIGSEL(2) /*!< MDMA hardware request is DMA0 channel 2 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH3_FTFIF CHXCTL1_TRIGSEL(3) /*!< MDMA hardware request is DMA0 channel 3 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH4_FTFIF CHXCTL1_TRIGSEL(4) /*!< MDMA hardware request is DMA0 channel 4 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH5_FTFIF CHXCTL1_TRIGSEL(5) /*!< MDMA hardware request is DMA0 channel 5 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH6_FTFIF CHXCTL1_TRIGSEL(6) /*!< MDMA hardware request is DMA0 channel 6 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH7_FTFIF CHXCTL1_TRIGSEL(7) /*!< MDMA hardware request is DMA0 channel 7 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH0_FTFIF CHXCTL1_TRIGSEL(8) /*!< MDMA hardware request is DMA1 channel 0 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH1_FTFIF CHXCTL1_TRIGSEL(9) /*!< MDMA hardware request is DMA1 channel 1 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH2_FTFIF CHXCTL1_TRIGSEL(10) /*!< MDMA hardware request is DMA1 channel 2 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH3_FTFIF CHXCTL1_TRIGSEL(11) /*!< MDMA hardware request is DMA1 channel 3 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH4_FTFIF CHXCTL1_TRIGSEL(12) /*!< MDMA hardware request is DMA1 channel 4 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH5_FTFIF CHXCTL1_TRIGSEL(13) /*!< MDMA hardware request is DMA1 channel 5 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH6_FTFIF CHXCTL1_TRIGSEL(14) /*!< MDMA hardware request is DMA1 channel 6 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH7_FTFIF CHXCTL1_TRIGSEL(15) /*!< MDMA hardware request is DMA1 channel 7 transfer complete flag */
#define MDMA_REQUEST_TLI_INT CHXCTL1_TRIGSEL(16) /*!< MDMA hardware request is TLI interrupt flag */
#define MDMA_REQUEST_OSPI0_FT CHXCTL1_TRIGSEL(22) /*!< MDMA hardware request is OSPI0_FT */
#define MDMA_REQUEST_OSPI0_TC CHXCTL1_TRIGSEL(23) /*!< MDMA hardware request is OSPI0_TC */
#define MDMA_REQUEST_IPA_CLUT_TRIG CHXCTL1_TRIGSEL(24) /*!< MDMA hardware request is IPA_CLUT_TRIG */
#define MDMA_REQUEST_IPA_TC_TRIG CHXCTL1_TRIGSEL(25) /*!< MDMA hardware request is IPA_TC_TRIG */
#define MDMA_REQUEST_IPA_TWM_TRIG CHXCTL1_TRIGSEL(26) /*!< MDMA hardware request is IPA_TWM_TRIG */
#define MDMA_REQUEST_SDIO0_DATA_END CHXCTL1_TRIGSEL(29) /*!< MDMA hardware request is SDIO0_DATA_END signal */
#define MDMA_REQUEST_SDIO0_BUF_END CHXCTL1_TRIGSEL(30) /*!< MDMA hardware request is SDIO0_BUF_END signal */
#define MDMA_REQUEST_SDIO0_CMD_END CHXCTL1_TRIGSEL(31) /*!< MDMA hardware request is SDIO0_CMD_END signal */
#define MDMA_REQUEST_OSPI1_FT CHXCTL1_TRIGSEL(32) /*!< MDMA hardware request is OSPI1_FT */
#define MDMA_REQUEST_OSPI1_TC CHXCTL1_TRIGSEL(33) /*!< MDMA hardware request is OSPI1_TC */
#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA software request */
/* MDMA transfer trigger mode */
#define CHCFG_TRIGMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28U)) /*!< trigger mode */
#define MDMA_BUFFER_TRANSFER CHCFG_TRIGMOD(0) /*!< software request or hardware request triggers a buffer transfer */
#define MDMA_BLOCK_TRANSFER CHCFG_TRIGMOD(1) /*!< software request or hardware request triggers a block transfer */
#define MDMA_MULTI_BLOCK_TRANSFER CHCFG_TRIGMOD(2) /*!< software request or hardware request triggers a multi-block transfer */
#define MDMA_COMPLETE_TRANSFER CHCFG_TRIGMOD(3) /*!< software request or hardware request triggers a complete data transfer (for example, link mode) */
/* channel priority level */
#define CHCTL0_PRIO(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
#define MDMA_PRIORITY_LOW CHCTL0_PRIO(0) /*!< priority level: low */
#define MDMA_PRIORITY_MEDIUM CHCTL0_PRIO(1) /*!< priority level: medium */
#define MDMA_PRIORITY_HIGH CHCTL0_PRIO(2) /*!< priority level: high */
#define MDMA_PRIORITY_ULTRA_HIGH CHCTL0_PRIO(3) /*!< priority level: very high */
/* MDMA endianness */
#define MDMA_LITTLE_ENDIANNESS ((uint32_t)0x00000000U) /*!< little endianness preserve */
#define MDMA_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CHXCTL0_BES) /*!< exchange the order of the bytes in a half-word */
#define MDMA_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CHXCTL0_HWES) /*!< exchange the order of the half-words in a word */
#define MDMA_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CHXCTL0_WES) /*!< exchange the order of the words in a double word */
/* MDMA source adress increment mode */
#define CHCFG_SIMOD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) /*!< source increment mode */
#define CHCFG_SIOS(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U)) /*!< offset size of source increment */
#define MDMA_SOURCE_INCREASE_DISABLE CHCFG_SIMOD(0) /*!< no increment */
#define MDMA_SOURCE_INCREASE_8BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(0)) /*!< source address pointer is incremented by a byte (8 bits) */
#define MDMA_SOURCE_INCREASE_16BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(1)) /*!< source address pointer is incremented by a half word (16 bits) */
#define MDMA_SOURCE_INCREASE_32BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(2)) /*!< source address pointer is incremented by a word (32 bits) */
#define MDMA_SOURCE_INCREASE_64BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(3)) /*!< source address pointer is incremented by a double word (64 bits) */
#define MDMA_SOURCE_DECREASE_8BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(0)) /*!< source address pointer is decremented by a byte (8 bits) */
#define MDMA_SOURCE_DECREASE_16BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(1)) /*!< source address pointer is decremented by a half word (16 bits) */
#define MDMA_SOURCE_DECREASE_32BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(2)) /*!< source address pointer is decremented by a word (32 bits) */
#define MDMA_SOURCE_DECREASE_64BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(3)) /*!< source address pointer is decremented by a double word (64 bits) */
/* MDMA destination adress increment mode*/
#define CHCFG_DIMOD(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) /*!< destination increment mode */
#define CHCFG_DIOS(regval) (BITS(10,11) & ((uint32_t)(regval) << 10U)) /*!< offset size of destination increment */
#define MDMA_DESTINATION_INCREASE_DISABLE CHCFG_DIMOD(0) /*!< no increment */
#define MDMA_DESTINATION_INCREASE_8BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(0)) /*!< destination address pointer is incremented by a byte (8 bits) */
#define MDMA_DESTINATION_INCREASE_16BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(1)) /*!< destination address pointer is incremented by a half word (16 bits) */
#define MDMA_DESTINATION_INCREASE_32BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(2)) /*!< destination address pointer is incremented by a word (32 bits) */
#define MDMA_DESTINATION_INCREASE_64BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(3)) /*!< destination address pointer is incremented by a double word (64 bits) */
#define MDMA_DESTINATION_DECREASE_8BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(0)) /*!< destination address pointer is decremented by a byte (8 bits) */
#define MDMA_DESTINATION_DECREASE_16BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(1)) /*!< destination address pointer is decremented by a half word (16 bits) */
#define MDMA_DESTINATION_DECREASE_32BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(2)) /*!< destination address pointer is decremented by a word (32 bits) */
#define MDMA_DESTINATION_DECREASE_64BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(3)) /*!< destination address pointer is decremented by a double word (64 bits) */
/* MDMA source data size */
#define CHCFG_SWIDTH(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< data size of source */
#define MDMA_SOURCE_DATASIZE_8BIT CHCFG_SWIDTH(0) /*!< source data size is byte */
#define MDMA_SOURCE_DATASIZE_16BIT CHCFG_SWIDTH(1) /*!< source data size is half word */
#define MDMA_SOURCE_DATASIZE_32BIT CHCFG_SWIDTH(2) /*!< source data size is word */
#define MDMA_SOURCE_DATASIZE_64BIT CHCFG_SWIDTH(3) /*!< source data size is double word */
/* MDMA destination data size */
#define CHCFG_DWIDTH(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) /*!< data size of destination */
#define MDMA_DESTINATION_DATASIZE_8BIT CHCFG_DWIDTH(0) /*!< destination data size is byte */
#define MDMA_DESTINATION_DATASIZE_16BIT CHCFG_DWIDTH(1) /*!< destination data size is half word */
#define MDMA_DESTINATION_DATASIZE_32BIT CHCFG_DWIDTH(2) /*!< destination data size is word */
#define MDMA_DESTINATION_DATASIZE_64BIT CHCFG_DWIDTH(3) /*!< destination data size is double word */
/* MDMA data alignment */
#define CHCFG_PAMOD(regval) (BITS(26,27) & ((uint32_t)(regval) << 26U)) /*!< padding and alignement mode */
#define MDMA_DATAALIGN_PKEN ((uint32_t)MDMA_CHXCFG_PKEN) /*!< pack/unpack the source data to match the destination data size */
#define MDMA_DATAALIGN_RIGHT CHCFG_PAMOD(0) /*!< right aligned, padded with 0s (default) */
#define MDMA_DATAALIGN_RIGHT_SIGNED CHCFG_PAMOD(1) /*!< right aligned with sign extended, note: this mode is allowed only if the source data size is smaller than destination data size */
#define MDMA_DATAALIGN_LEFT CHCFG_PAMOD(2) /*!< left aligned, padded with 0s in low bytes position when source data size smaller than destination data size, and only high byte of source is written when source data size larger than destination data size */
/* MDMA source burst */
#define CHCFG_SBURST(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U)) /*!< transfer burst type of source */
#define MDMA_SOURCE_BURST_SINGLE CHCFG_SBURST(0) /*!< single transfer */
#define MDMA_SOURCE_BURST_2BEATS CHCFG_SBURST(1) /*!< burst 2 beats */
#define MDMA_SOURCE_BURST_4BEATS CHCFG_SBURST(2) /*!< burst 4 beats */
#define MDMA_SOURCE_BURST_8BEATS CHCFG_SBURST(3) /*!< burst 8 beats */
#define MDMA_SOURCE_BURST_16BEATS CHCFG_SBURST(4) /*!< burst 16 beats */
#define MDMA_SOURCE_BURST_32BEATS CHCFG_SBURST(5) /*!< burst 32 beats */
#define MDMA_SOURCE_BURST_64BEATS CHCFG_SBURST(6) /*!< burst 64 beats */
#define MDMA_SOURCE_BURST_128BEATS CHCFG_SBURST(7) /*!< burst 128 beats */
/* MDMA destination burst */
#define CHCFG_DBURST(regval) (BITS(15,17) & ((uint32_t)(regval) << 15U)) /*!< transfer burst type of destination */
#define MDMA_DESTINATION_BURST_SINGLE CHCFG_DBURST(0) /*!< single transfer */
#define MDMA_DESTINATION_BURST_2BEATS CHCFG_DBURST(1) /*!< burst 2 beats */
#define MDMA_DESTINATION_BURST_4BEATS CHCFG_DBURST(2) /*!< burst 4 beats */
#define MDMA_DESTINATION_BURST_8BEATS CHCFG_DBURST(3) /*!< burst 8 beats */
#define MDMA_DESTINATION_BURST_16BEATS CHCFG_DBURST(4) /*!< burst 16 beats */
#define MDMA_DESTINATION_BURST_32BEATS CHCFG_DBURST(5) /*!< burst 32 beats */
#define MDMA_DESTINATION_BURST_64BEATS CHCFG_DBURST(6) /*!< burst 64 beats */
#define MDMA_DESTINATION_BURST_128BEATS CHCFG_DBURST(7) /*!< burst 128 beats */
/* source bus select */
#define MDMA_SOURCE_AXI ((uint32_t)0x00000000U) /*!< source bus of channel x is the system bus or AXI bus */
#define MDMA_SOURCE_AHB_TCM MDMA_CHXCTL1_SBSEL /*!< source bus of channel x is AHB bus or TCM */
/* destination bus select */
#define MDMA_DESTINATION_AXI ((uint32_t)0x00000000U) /*!< destination bus of channel x is the system bus or AXI bus */
#define MDMA_DESTINATION_AHB_TCM MDMA_CHXCTL1_DBSEL /*!< destination bus of channel x is AHB bus or TCM */
/* MDMA access error direction */
#define MDMA_READ_ERROR ((uint32_t)0x00000000U) /*!< read access error */
#define MDMA_WRITE_ERROR MDMA_CHXSTAT1_TERRD /*!< write access error */
/* MDMA bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_DISABLE ((uint32_t)0x00000000U) /*!< diable bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_ENABLE MDMA_CHXCFG_BWMOD /*!< enable bufferable write mode */
/* MDMA flags */
#define STAT1_FLAG BIT(31) /*!< flag to indicate that flag is in STAT1 register */
#define MDMA_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< channel x transfer error flag */
#define MDMA_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel x channel transfer complete flag */
#define MDMA_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< channel x multi-block transfer complete flag */
#define MDMA_FLAG_BTCF MDMA_CHXSTAT0_BTCF /*!< channel x block transfer complete flag */
#define MDMA_FLAG_TCF MDMA_CHXSTAT0_TCF /*!< channel x buffer transfer complete flag */
#define MDMA_FLAG_REQAF MDMA_CHXSTAT0_REQAF /*!< channel x request active flag */
#define MDMA_FLAG_LDTERR (MDMA_CHXSTAT1_LDTERR | STAT1_FLAG) /*!< link data transfer error flag in the last transfer of the channel */
#define MDMA_FLAG_MDTERR (MDMA_CHXSTAT1_MDTERR | STAT1_FLAG) /*!< mask data error flag */
#define MDMA_FLAG_ASERR (MDMA_CHXSTAT1_ASERR | STAT1_FLAG) /*!< address and size error flag */
#define MDMA_FLAG_BZERR (MDMA_CHXSTAT1_BZERR | STAT1_FLAG) /*!< block size error flag */
/* MDMA interrupt */
#define MDMA_INT_ERR MDMA_CHXCTL0_ERRIE /*!< transfer error interrupt */
#define MDMA_INT_CHTC MDMA_CHXCTL0_CHTCIE /*!< channel transfer complete interrupt */
#define MDMA_INT_MBTC MDMA_CHXCTL0_MBTCIE /*!< multi-block transfer complete interrupt */
#define MDMA_INT_BTC MDMA_CHXCTL0_BTCIE /*!< block transfer complete interrupt */
#define MDMA_INT_TC MDMA_CHXCTL0_TCIE /*!< buffer transfer complete interrupt */
/* MDMA interrupt flags */
#define MDMA_INT_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< transfer error interrupt flag */
#define MDMA_INT_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel transfer complete interrupt flag */
#define MDMA_INT_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< multi-block transfer complete interrupt flag */
#define MDMA_INT_FLAG_BTCF MDMA_CHXSTAT0_BTCF /*!< block transfer complete interrupt flag */
#define MDMA_INT_FLAG_TCF MDMA_CHXSTAT0_TCF /*!< buffer transfer complete interrupt flag */
/* function declarations */
/* MDMA deinitialization and initialization functions */
/* deinitialize MDMA */
void mdma_deinit(void);
/* deinitialize MDMA registers of a channel */
void mdma_channel_deinit(mdma_channel_enum channelx);
/* initialize the MDMA parameters struct with the default values */
void mdma_para_struct_init(mdma_parameter_struct *init_struct);
/* initialize the MDMA multi block transfer mode parameters struct with the default values */
void mdma_multi_block_para_struct_init(mdma_multi_block_parameter_struct *block_init_struct);
/* initialize the MDMA link node configuration struct with the default values */
void mdma_link_node_para_struct_init(mdma_link_node_parameter_struct *node);
/* initialize MDMA channel with MDMA parameter structure */
void mdma_init(mdma_channel_enum channelx, mdma_parameter_struct *init_struct);
/* configure MDMA buffer/block transfer mode */
void mdma_buffer_block_mode_config(mdma_channel_enum channelx, uint32_t saddr, uint32_t daddr, uint32_t tbnum);
/* configure MDMA multi block transfer mode */
void mdma_multi_block_mode_config(mdma_channel_enum channelx, uint32_t tbnum, mdma_multi_block_parameter_struct *block_init_struct);
/* create MDMA link list node */
void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_parameter_struct *block_init_struct, mdma_parameter_struct *init_struct);
/* MDMA add node to link list */
void mdma_node_add(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *new_node);
/* MDMA disconnect link list node */
ErrStatus mdma_node_delete(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *unused_node);
/* MDMA configuration functions */
/* configure MDMA destination base address */
void mdma_destination_address_config(mdma_channel_enum channelx, uint32_t address);
/* configure MDMA source base address */
void mdma_source_address_config(mdma_channel_enum channelx, uint32_t address);
/* configure MDMA destination bus */
void mdma_destination_bus_config(mdma_channel_enum channelx, uint32_t bus);
/* configure MDMA source bus */
void mdma_source_bus_config(mdma_channel_enum channelx, uint32_t bus);
/* configure priority level of MDMA channel */
void mdma_priority_config(mdma_channel_enum channelx, uint32_t priority);
/* configure endianness of MDMA channel */
void mdma_endianness_config(mdma_channel_enum channelx, uint32_t endianness);
/* configure data alignment of MDMA channel */
void mdma_alignment_config(mdma_channel_enum channelx, uint32_t alignment);
/* configure transfer burst beats of source */
void mdma_source_burst_beats_config(mdma_channel_enum channelx, uint32_t sbeat);
/* configure transfer burst beats of destination */
void mdma_destination_burst_beats_config(mdma_channel_enum channelx, uint32_t dbeat);
/* configure data size of source */
void mdma_source_width_config(mdma_channel_enum channelx, uint32_t swidth);
/* configure data size of destination */
void mdma_destination_width_config(mdma_channel_enum channelx, uint32_t dwidth);
/* configure source adress increment mode */
void mdma_source_increment_config(mdma_channel_enum channelx, uint32_t sinc);
/* configure destination adress increment mode */
void mdma_destination_increment_config(mdma_channel_enum channelx, uint32_t dinc);
/* enable MDMA channel bufferable write mode */
void mdma_channel_bufferable_write_enable(mdma_channel_enum channelx);
/* disable MDMA channel bufferable write mode */
void mdma_channel_bufferable_write_disable(mdma_channel_enum channelx);
/* enable MDMA channel software request */
void mdma_channel_software_request_enable(mdma_channel_enum channelx);
/* enable MDMA channel */
void mdma_channel_enable(mdma_channel_enum channelx);
/* disable MDMA channel */
void mdma_channel_disable(mdma_channel_enum channelx);
/* get MDMA transfer error direction */
uint32_t mdma_transfer_error_direction_get(mdma_channel_enum channelx);
/* get MDMA transfer error address */
uint32_t mdma_transfer_error_address_get(mdma_channel_enum channelx);
/* interrupt & flag functions */
/* get MDMA flag */
FlagStatus mdma_flag_get(mdma_channel_enum channelx, uint32_t flag);
/* clear MDMA flag */
void mdma_flag_clear(mdma_channel_enum channelx, uint32_t flag);
/* enable MDMA interrupt */
void mdma_interrupt_enable(mdma_channel_enum channelx, uint32_t interrupt);
/* disable MDMA interrupt */
void mdma_interrupt_disable(mdma_channel_enum channelx, uint32_t interrupt);
/* get MDMA interrupt flag */
FlagStatus mdma_interrupt_flag_get(mdma_channel_enum channelx, uint32_t int_flag);
/* clear MDMA interrupt flag */
void mdma_interrupt_flag_clear(mdma_channel_enum channelx, uint32_t int_flag);
#endif /* GD32H7XX_MDMA_H */

200
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_misc.h Normal file
View File

@@ -0,0 +1,200 @@
/*!
\file gd32h7xx_misc.h
\brief definitions for the MISC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_MISC_H
#define GD32H7XX_MISC_H
#include "gd32h7xx.h"
#if (__MPU_PRESENT == 1)
/* MPU region init parameter struct definitions */
typedef struct
{
uint32_t region_base_address; /*!< region base address */
uint8_t region_number; /*!< region number */
uint8_t region_size; /*!< region size */
uint8_t subregion_disable; /*!< subregion disable */
uint8_t tex_type; /*!< tex type */
uint8_t access_permission; /*!< access permissions(AP) field */
uint8_t access_shareable; /*!< shareable */
uint8_t access_cacheable; /*!< cacheable */
uint8_t access_bufferable; /*!< bufferable */
uint8_t instruction_exec; /*!< execute never */
}mpu_region_init_struct;
#endif /* __MPU_PRESENT */
/* constants definitions */
/* set the RAM and FLASH base address */
#define NVIC_VECTTAB_RAM ((uint32_t)0x24000000U) /*!< RAM base address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
/* set the NVIC vector table offset mask */
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U)
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U)
/* priority group - define the pre-emption priority and the subpriority */
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700U) /*!< 0 bits for pre-emption priority, 4 bits for subpriority */
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600U) /*!< 1 bits for pre-emption priority, 3 bits for subpriority */
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500U) /*!< 2 bits for pre-emption priority, 2 bits for subpriority */
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400U) /*!< 3 bits for pre-emption priority, 1 bits for subpriority */
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300U) /*!< 4 bits for pre-emption priority, 0 bits for subpriority */
/* choose the method to enter or exit the low power mode */
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the system whether enter low power mode by exiting from ISR */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the system enter the DEEPSLEEP mode or SLEEP mode */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the low power mode */
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
/* choose the systick clock source */
#define SYSTICK_CLKSOURCE_CKSYS_DIV2 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from CK_SYS/2 */
#define SYSTICK_CLKSOURCE_CKSYS ((uint32_t)0x00000004U) /*!< systick clock source is from CK_SYS */
#if (__MPU_PRESENT == 1)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) /*!< MPU region number 0 */
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) /*!< MPU region number 1 */
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) /*!< MPU region number 2 */
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) /*!< MPU region number 3 */
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) /*!< MPU region number 4 */
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) /*!< MPU region number 5 */
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) /*!< MPU region number 6 */
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /*!< MPU region number 7 */
#define MPU_REGION_NUMBER8 ((uint8_t)0x08U) /*!< MPU region number 8 */
#define MPU_REGION_NUMBER9 ((uint8_t)0x09U) /*!< MPU region number 9 */
#define MPU_REGION_NUMBER10 ((uint8_t)0x0AU) /*!< MPU region number 10 */
#define MPU_REGION_NUMBER11 ((uint8_t)0x0BU) /*!< MPU region number 11 */
#define MPU_REGION_NUMBER12 ((uint8_t)0x0CU) /*!< MPU region number 12 */
#define MPU_REGION_NUMBER13 ((uint8_t)0x0DU) /*!< MPU region number 13 */
#define MPU_REGION_NUMBER14 ((uint8_t)0x0EU) /*!< MPU region number 14 */
#define MPU_REGION_NUMBER15 ((uint8_t)0x0FU) /*!< MPU region number 15 */
#define MPU_REGION_SIZE_32B ARM_MPU_REGION_SIZE_32B /*!< MPU region size is 32 bytes, the smallest supported region size is 32 bytes */
#define MPU_REGION_SIZE_64B ARM_MPU_REGION_SIZE_64B /*!< MPU region size is 64 bytes */
#define MPU_REGION_SIZE_128B ARM_MPU_REGION_SIZE_128B /*!< MPU region size is 128 bytes */
#define MPU_REGION_SIZE_256B ARM_MPU_REGION_SIZE_256B /*!< MPU region size is 256 bytes */
#define MPU_REGION_SIZE_512B ARM_MPU_REGION_SIZE_512B /*!< MPU region size is 512 bytes */
#define MPU_REGION_SIZE_1KB ARM_MPU_REGION_SIZE_1KB /*!< MPU region size is 1K bytes */
#define MPU_REGION_SIZE_2KB ARM_MPU_REGION_SIZE_2KB /*!< MPU region size is 2K bytes */
#define MPU_REGION_SIZE_4KB ARM_MPU_REGION_SIZE_4KB /*!< MPU region size is 4K bytes */
#define MPU_REGION_SIZE_8KB ARM_MPU_REGION_SIZE_8KB /*!< MPU region size is 8K bytes */
#define MPU_REGION_SIZE_16KB ARM_MPU_REGION_SIZE_16KB /*!< MPU region size is 16K bytes */
#define MPU_REGION_SIZE_32KB ARM_MPU_REGION_SIZE_32KB /*!< MPU region size is 32K bytes */
#define MPU_REGION_SIZE_64KB ARM_MPU_REGION_SIZE_64KB /*!< MPU region size is 64K bytes */
#define MPU_REGION_SIZE_128KB ARM_MPU_REGION_SIZE_128KB /*!< MPU region size is 128K bytes */
#define MPU_REGION_SIZE_256KB ARM_MPU_REGION_SIZE_256KB /*!< MPU region size is 256K bytes */
#define MPU_REGION_SIZE_512KB ARM_MPU_REGION_SIZE_512KB /*!< MPU region size is 512K bytes */
#define MPU_REGION_SIZE_1MB ARM_MPU_REGION_SIZE_1MB /*!< MPU region size is 1M bytes */
#define MPU_REGION_SIZE_2MB ARM_MPU_REGION_SIZE_2MB /*!< MPU region size is 2M bytes */
#define MPU_REGION_SIZE_4MB ARM_MPU_REGION_SIZE_4MB /*!< MPU region size is 4M bytes */
#define MPU_REGION_SIZE_8MB ARM_MPU_REGION_SIZE_8MB /*!< MPU region size is 8M bytes */
#define MPU_REGION_SIZE_16MB ARM_MPU_REGION_SIZE_16MB /*!< MPU region size is 16M bytes */
#define MPU_REGION_SIZE_32MB ARM_MPU_REGION_SIZE_32MB /*!< MPU region size is 32M bytes */
#define MPU_REGION_SIZE_64MB ARM_MPU_REGION_SIZE_64MB /*!< MPU region size is 64M bytes */
#define MPU_REGION_SIZE_128MB ARM_MPU_REGION_SIZE_128MB /*!< MPU region size is 128M bytes */
#define MPU_REGION_SIZE_256MB ARM_MPU_REGION_SIZE_256MB /*!< MPU region size is 256M bytes */
#define MPU_REGION_SIZE_512MB ARM_MPU_REGION_SIZE_512MB /*!< MPU region size is 512M bytes */
#define MPU_REGION_SIZE_1GB ARM_MPU_REGION_SIZE_1GB /*!< MPU region size is 1G bytes */
#define MPU_REGION_SIZE_2GB ARM_MPU_REGION_SIZE_2GB /*!< MPU region size is 2G bytes */
#define MPU_REGION_SIZE_4GB ARM_MPU_REGION_SIZE_4GB /*!< MPU region size is 4G bytes */
#define MPU_SUBREGION_ENABLE ((uint8_t)0x00U) /*!< Subregion enable */
#define MPU_SUBREGION_DISABLE ((uint8_t)0x01U) /*!< Subregion disable */
#define MPU_TEX_TYPE0 ((uint8_t)0x00U) /*!< MPU TEX type 0 */
#define MPU_TEX_TYPE1 ((uint8_t)0x01U) /*!< MPU TEX type 1 */
#define MPU_TEX_TYPE2 ((uint8_t)0x02U) /*!< MPU TEX type 2 */
#define MPU_AP_NO_ACCESS ARM_MPU_AP_NONE /*!< MPU access permission no access */
#define MPU_AP_PRIV_RW ARM_MPU_AP_PRIV /*!< MPU access permission privileged access only */
#define MPU_AP_PRIV_RW_UNPRIV_RO ARM_MPU_AP_URO /*!< MPU access permission unprivileged access read-only */
#define MPU_AP_FULL_ACCESS ARM_MPU_AP_FULL /*!< MPU access permission full access */
#define MPU_AP_PRIV_RO ARM_MPU_AP_PRO /*!< MPU access permission privileged access read-only */
#define MPU_AP_PRIV_UNPRIV_RO ARM_MPU_AP_RO /*!< MPU access permission privileged and unprivileged read-only access */
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) /*!< MPU access shareable */
#define MPU_ACCESS_NON_SHAREABLE ((uint8_t)0x00U) /*!< MPU access non-shareable */
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) /*!< MPU access cacheable */
#define MPU_ACCESS_NON_CACHEABLE ((uint8_t)0x00U) /*!< MPU access non-cacheable */
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) /*!< MPU access bufferable */
#define MPU_ACCESS_NON_BUFFERABLE ((uint8_t)0x00U) /*!< MPU access non-bufferable */
#define MPU_INSTRUCTION_EXEC_PERMIT ((uint8_t)0x00U) /*!< execution of an instruction fetched from this region permitted */
#define MPU_INSTRUCTION_EXEC_NOT_PERMIT ((uint8_t)0x01U) /*!< execution of an instruction fetched from this region not permitted */
#define MPU_MODE_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< HFNMIENA and PRIVDEFENA are 0 */
#define MPU_MODE_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< use the MPU for memory accesses by HardFault and NMI handlers only */
#define MPU_MODE_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< enables the default memory map as a background region for privileged access only */
#define MPU_MODE_HFNMI_PRIVDEF ((uint32_t)MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< HFNMIENA and PRIVDEFENA are 1 */
#endif /* __MPU_PRESENT */
/* function declarations */
/* set the priority group */
void nvic_priority_group_set(uint32_t nvic_prigroup);
/* enable NVIC interrupt request */
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC interrupt request */
void nvic_irq_disable(uint8_t nvic_irq);
/* set the NVIC vector table base address */
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
/* set the state of the low power mode */
void system_lowpower_set(uint8_t lowpower_mode);
/* reset the state of the low power mode */
void system_lowpower_reset(uint8_t lowpower_mode);
/* set the systick clock source */
void systick_clksource_set(uint32_t systick_clksource);
#if (__MPU_PRESENT == 1)
/* initialize mpu_region_init_struct with the default values */
void mpu_region_struct_para_init(mpu_region_init_struct *mpu_init_struct);
/* configure the MPU region */
void mpu_region_config(mpu_region_init_struct *mpu_init_struct);
/* enable the MPU region */
void mpu_region_enable(void);
#endif /* __MPU_PRESENT */
#endif /* GD32H7XX_MISC_H */

802
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ospi.h Normal file
View File

File diff suppressed because it is too large Load Diff

125
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ospim.h Normal file
View File

@@ -0,0 +1,125 @@
/*!
\file gd32h7xx_ospim.h
\brief definitions for the OSPIM
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_OSPIM_H
#define GD32H7XX_OSPIM_H
#include "gd32h7xx.h"
/* OSPIM definitions */
#define OSPIM OSPM_BASE
#define OSPIM_PCFG0 REG32(OSPIM + 0x00000004U) /*!< OSPI I/O manager port configuration register 0 */
#define OSPIM_PCFG1 REG32(OSPIM + 0x00000008U) /*!< OSPI I/O manager port configuration register 1 */
/* OSPIM_PCFG */
#define OSPIM_PCFG_SCKEN BIT(0) /*!< enable for sck of port n */
#define OSPIM_PCFG_SRCPCK BIT(1) /*!< source selection for sck of port n */
#define OSPIM_PCFG_NCSEN BIT(8) /*!< enable for csn of port n */
#define OSPIM_PCFG_SRCPCS BIT(9) /*!< source selection for csn of port n */
#define OSPIM_PCFG_POLEN BIT(16) /*!< enable for IO[3:0] of port n */
#define OSPIM_PCFG_SRCPLIO BITS(17,18) /*!< source selection for IO[3:0] of port n */
#define OSPIM_PCFG_POHEN BIT(24) /*!< enable for IO[7:4] of port n */
#define OSPIM_PCFG_SRCPHIO BITS(25,26) /*!< source selection for IO[7:4] of port n */
/* constants definitions */
/* ospi io manager configuration struct definitions */
/* ospim register address */
#define OSPIM_PCFG(regval) REG32(OSPIM + 0x4U * ((regval) + 1U)) /*!< the address of OSPI manager port configuration register */
/* ospim register address */
#define OSPIM_PORT0 0x00U /*!< OSPI manager port 0 */
#define OSPIM_PORT1 0x01U /*!< OSPI manager port 1 */
/* SCK of port */
#define OSPIM_PORT_SCK_DISABLE 0x00000000U /*!< disable SCK of port */
#define OSPIM_PORT_SCK_ENABLE OSPIM_PCFG_SCKEN /*!< disable SCK of port */
/* source selection for SCK of port */
#define OSPIM_SCK_SOURCE_OSPI0_SCK 0x00000000U /*!< the source of SCK is OSPI0_SCK */
#define OSPIM_SCK_SOURCE_OSPI1_SCK OSPIM_PCFG_SRCPCK /*!< the source of SCK is OSPI1_SCK */
/* CSN of port */
#define OSPIM_PORT_CSN_DISABLE 0x00000000U /*!< disable CSN of port */
#define OSPIM_PORT_CSN_ENABLE OSPIM_PCFG_NCSEN /*!< enable CSN of port */
/* source selection for CSN of port */
#define OSPIM_CSN_SOURCE_OSPI0_CSN 0x00000000U /*!< the source of CSN is OSPI0_CSN */
#define OSPIM_CSN_SOURCE_OSPI1_CSN OSPIM_PCFG_SRCPCS /*!< the source of CSN is OSPI1_CSN */
/* IO[3:0] of port */
#define OSPIM_IO_LOW_DISABLE 0x00000000U /*!< disable IO[3:0] of port */
#define OSPIM_IO_LOW_ENABLE OSPIM_PCFG_POLEN /*!< enable IO[3:0] of port */
/* source selection for IO[3:0] of port n */
#define OSPIM_SRCPLIO(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
#define OSPIM_SRCPLIO_OSPI0_IO_LOW OSPIM_SRCPLIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
#define OSPIM_SRCPLIO_OSPI0_IO_HIGH OSPIM_SRCPLIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
#define OSPIM_SRCPLIO_OSPI1_IO_LOW OSPIM_SRCPLIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
#define OSPIM_SRCPLIO_OSPI1_IO_HIGH OSPIM_SRCPLIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
/* IO[7:4] of port */
#define OSPIM_IO_HIGH_DISABLE 0x00000000U /*!< disable IO[7:4] of port */
#define OSPIM_IO_HIGH_ENABLE OSPIM_PCFG_POHEN /*!< enable IO[7:4] of port */
/* source selection for IO[7:4] of port n */
#define OSPIM_SRCPHIO(regval) (BITS(25,26) & ((uint32_t)(regval) << 25U))
#define OSPIM_SRCPHIO_OSPI0_IO_LOW OSPIM_SRCPHIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
#define OSPIM_SRCPHIO_OSPI0_IO_HIGH OSPIM_SRCPHIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
#define OSPIM_SRCPHIO_OSPI1_IO_LOW OSPIM_SRCPHIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
#define OSPIM_SRCPHIO_OSPI1_IO_HIGH OSPIM_SRCPHIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
/* function declarations */
/* reset the OSPIM peripheral */
void ospim_deinit(void);
/* ospim port configuration functions */
/* configurate SCK for port */
void ospim_port_sck_config(uint8_t port, uint32_t sckconfg);
/* select source of SCK for port */
void ospim_port_sck_source_select(uint8_t port, uint32_t sck_source);
/* configurate CSN for port */
void ospim_port_csn_config(uint8_t port, uint32_t csnconfig);
/* select source of CSN for port */
void ospim_port_csn_source_select(uint8_t port, uint32_t csn_source);
/* configurate IO[3:0] for port */
void ospim_port_io3_0_config(uint8_t port, uint32_t ioconfig);
/* select source of IO[3:0] for port */
void ospim_port_io3_0_source_select(uint8_t port, uint32_t io_source);
/* configurate IO[7:4] for port */
void ospim_port_io7_4_config(uint8_t port, uint32_t ioconfig);
/* select source of IO[7:4] for port */
void ospim_port_io7_4_source_select(uint8_t port, uint32_t io_source);
#endif /* GD32H7XX_OSPIM_H */

279
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_pmu.h Normal file
View File

@@ -0,0 +1,279 @@
/*!
\file gd32h7xx_pmu.h
\brief definitions for the PMU
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_PMU_H
#define GD32H7XX_PMU_H
#include "gd32h7xx.h"
/* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */
/* registers definitions */
#define PMU_CTL0 REG32((PMU) + 0x00000000U) /*!< PMU control register 0 */
#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
#define PMU_CTL1 REG32((PMU) + 0x00000008U) /*!< PMU control register 1 */
#define PMU_CTL2 REG32((PMU) + 0x00000010U) /*!< PMU control register 2 */
#define PMU_CTL3 REG32((PMU) + 0x00000014U) /*!< PMU control register 3 */
#define PMU_PAR REG32((PMU) + 0x00000018U) /*!< PMU parameter register */
/* bits definitions */
/* PMU_CTL0 */
#define PMU_CTL0_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL0_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL0_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL0_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL0_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL0_BKPWEN BIT(8) /*!< backup domain write enable */
#define PMU_CTL0_SLDOVS BITS(14,15) /*!< deep sleep mode mode LDO output voltage select */
#define PMU_CTL0_VAVDEN BIT(16) /*!< VDDA analog voltage detector enable */
#define PMU_CTL0_VAVDVC BITS(17,18) /*!< VDDA analog voltage detector level configure bits */
#define PMU_CTL0_VOVDEN BIT(19) /*!< peripheral voltage on V0.9V detector enable bit */
/* PMU_CS */
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS_STBF BIT(1) /*!< standby flag */
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin0(PA0) enable */
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin1(PA2) enable */
#define PMU_CS_WUPEN3 BIT(11) /*!< wakeup pin3(PC13) enable */
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin5(PC1) enable */
#define PMU_CS_VAVDF BIT(16) /*!< VDDA analog voltage detector voltage output on VDDA flag */
#define PMU_CS_VOVDF BIT(20) /*!< peripheral voltage on V0.9V detector flag bit */
/* PMU_CTL1 */
#define PMU_CTL1_BKPVSEN BIT(0) /*!< backup voltage stabilizer enable */
#define PMU_CTL1_VBTMEN BIT(4) /*!< VBAT and temperature monitoring enable */
#define PMU_CTL1_BKPVSRF BIT(16) /*!< backup regulator ready */
#define PMU_CTL1_VBATLF BIT(20) /*!< VBAT level monitoring versus low threshold */
#define PMU_CTL1_VBATHF BIT(21) /*!< VBAT level monitoring versus high threshold */
#define PMU_CTL1_TEMPLF BIT(22) /*!< temperature level monitoring versus low threshold */
#define PMU_CTL1_TEMPHF BIT(23) /*!< temperature level monitoring versus high threshold */
/* PMU_CTL2 */
#define PMU_CTL2_BYPASS BIT(0) /*!< power management unit bypass control bit */
#define PMU_CTL2_LDOEN BIT(1) /*!< Low drop-out voltage stabilizer enable bit */
#define PMU_CTL2_DVSEN BIT(2) /*!< step-down voltage stabilizer enable bit */
#define PMU_CTL2_DVSCFG BIT(3) /*!< SMPS step-down converter forced on and in high power MR mode */
#define PMU_CTL2_DVSVC BITS(4,5) /*!< SMPS step-down converter voltage output level selection */
#define PMU_CTL2_VCEN BIT(8) /*!< VBAT battery charging enable */
#define PMU_CTL2_VCRSEL BIT(9) /*!< VBAT battery charging resistor selection */
#define PMU_CTL2_DVSRF BIT(16) /*!< step-down voltage stabilizer ready flag bit */
#define PMU_CTL2_VUSB33DEN BIT(24) /*!< VDD33USB voltage level detector enable bit */
#define PMU_CTL2_USBSEN BIT(25) /*!< USB voltage stabilizer enable */
#define PMU_CTL2_USB33RF BIT(26) /*!< USB supply ready flag */
/* PMU_CTL3 */
#define PMU_CTL3_LDOVS BITS(12,14) /*!< voltage scaling selection according to performance */
#define PMU_CTL3_VOVRF BIT(16) /*!< V0.9V voltage ready bit */
/* PMU_PAR */
#define PMU_PAR_CNT BITS(0,11) /*!< exit deep-sleep mode wait time count configure bits */
#define PMU_PAR_TSW_IRCCNT BITS(16,20) /*!< when enter deep-sleep, switch to IRC wait clock */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL0_LVDT(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
#define PMU_LVDT_0 CTL0_LVDT(0) /*!< voltage threshold is 2.1V */
#define PMU_LVDT_1 CTL0_LVDT(1) /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2 CTL0_LVDT(2) /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3 CTL0_LVDT(3) /*!< voltage threshold is 2.6V */
#define PMU_LVDT_4 CTL0_LVDT(4) /*!< voltage threshold is 2.7V */
#define PMU_LVDT_5 CTL0_LVDT(5) /*!< voltage threshold is 2.9V */
#define PMU_LVDT_6 CTL0_LVDT(6) /*!< voltage threshold is 3.0V */
#define PMU_LVDT_7 CTL0_LVDT(7) /*!< input analog voltage on PB7 (compared with 0.8V) */
/* PMU deep-sleep mode voltage scaling selection */
#define CTL0_SLDOVS(regval) (BITS(14,15) & ((uint32_t)(regval) << 14U))
#define PMU_SLDOVS_0 CTL0_SLDOVS(0) /*!< SLDOVS scale 0.6V */
#define PMU_SLDOVS_1 CTL0_SLDOVS(1) /*!< SLDOVS scale 0.7V */
#define PMU_SLDOVS_2 CTL0_SLDOVS(2) /*!< SLDOVS scale 0.8V (default) */
#define PMU_SLDOVS_3 CTL0_SLDOVS(3) /*!< SLDOVS scale 0.9V */
/* PMU analog voltage detector threshold definitions */
#define CTL0_VAVDVC(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
#define PMU_VAVDVC_0 CTL0_VAVDVC(0) /*!< voltage threshold is 1.7V */
#define PMU_VAVDVC_1 CTL0_VAVDVC(1) /*!< voltage threshold is 2.1V */
#define PMU_VAVDVC_2 CTL0_VAVDVC(2) /*!< voltage threshold is 2.5V */
#define PMU_VAVDVC_3 CTL0_VAVDVC(3) /*!< voltage threshold is 2.8V */
/* PMU step-down voltage stabilizer output level definitions */
#define CTL2_DVSVC(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U))
#define PMU_STEPDOWNVOL_1P8 CTL2_DVSVC(1) /*!< SMPS step-down converter voltage output level 1.8V */
#define PMU_STEPDOWNVOL_2P5 CTL2_DVSVC(2) /*!< SMPS step-down converter voltage output level 2.5V */
/* PMU VBAT battery charging resistor selection */
#define CTL2_VCRSEL(regval) (BIT(9) & ((uint32_t)(regval) << 9U))
#define PMU_VCRSEL_5K CTL2_VCRSEL(0) /*!< 5 kOhms resistor is selected for charing VBAT battery */
#define PMU_VCRSEL_1P5K CTL2_VCRSEL(1) /*!< 1.5 kOhms resistor is selected for charing VBAT battery */
/* PMU LDO output voltage select definitions */
#define CTL3_LDOVS(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U))
#define PMU_LDOVS_0 CTL3_LDOVS(0) /*!< LDO output voltage 0.8V mode */
#define PMU_LDOVS_1 CTL3_LDOVS(1) /*!< LDO output voltage 0.85V mode */
#define PMU_LDOVS_2 CTL3_LDOVS(2) /*!< LDO output voltage 0.9V mode */
#define PMU_LDOVS_3 CTL3_LDOVS(3) /*!< LDO output voltage 0.95V mode */
#define PMU_LDOVS_4 CTL3_LDOVS(4) /*!< LDO output voltage 0.975V mode */
#define PMU_LDOVS_5 CTL3_LDOVS(5) /*!< LDO output voltage 1V mode */
/* PMU flag definitions */
#define PMU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define PMU_REG_VAL(periph) (REG32(PMU + ((uint32_t)(periph) >> 6U)))
#define PMU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define PMU_CTL0_OFFSET (0x00000000U) /*!< PMU control register 0 offset */
#define PMU_CS_OFFSET (0x00000004U) /*!< PMU control and status register offset */
#define PMU_CTL1_OFFSET (0x00000008U) /*!< PMU control register 1 offset */
#define PMU_CTL2_OFFSET (0x00000010U) /*!< PMU control register 2 offset */
#define PMU_CTL3_OFFSET (0x00000014U) /*!< PMU control register 3 offset */
#define PMU_PAR_OFFSET (0x00000018U) /*!< PMU parameter register offset */
#define PMU_FLAG_WAKEUP PMU_REGIDX_BIT(PMU_CS_OFFSET, 0) /*!< wakeup flag */
#define PMU_FLAG_STANDBY PMU_REGIDX_BIT(PMU_CS_OFFSET, 1) /*!< standby flag */
#define PMU_FLAG_LVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 2) /*!< low voltage detector status flag */
#define PMU_FLAG_VAVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 16) /*!< VDDA analog voltage detector voltage output on VDDA flag */
#define PMU_FLAG_VOVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 20) /*!< peripheral voltage on VDDA detector flag */
#define PMU_FLAG_BKPVSRF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 16) /*!< backup voltage stabilizer ready flag */
#define PMU_FLAG_VBATLF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 20) /*!< VBAT level monitoring versus low threshold */
#define PMU_FLAG_VBATHF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 21) /*!< VBAT level monitoring versus high threshold */
#define PMU_FLAG_TEMPLF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 22) /*!< temperature level monitoring versus low threshold */
#define PMU_FLAG_TEMPHF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 23) /*!< temperature level monitoring versus high threshold */
#define PMU_FLAG_DVSRF PMU_REGIDX_BIT(PMU_CTL2_OFFSET, 16) /*!< step-down voltage stabilizer ready flag bit */
#define PMU_FLAG_USB33RF PMU_REGIDX_BIT(PMU_CTL2_OFFSET, 26) /*!< USB supply ready flag bit */
#define PMU_FLAG_PWRRF PMU_REGIDX_BIT(PMU_CTL3_OFFSET, 16) /*!< Power Ready flag bit */
/* PMU wakeup pin definitions */
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< wakeup pin 0 */
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< wakeup pin 1 */
#define PMU_WAKEUP_PIN3 PMU_CS_WUPEN3 /*!< wakeup pin 3 */
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< wakeup pin 5 */
/* PMU SMPS LDO supply mode definitions */
#define PMU_LDO_SUPPLY PMU_CTL2_LDOEN /*!< V0.9V domains are suppplied from the LDO */
#define PMU_DIRECT_SMPS_SUPPLY PMU_CTL2_DVSEN /*!< V0.9V domains are suppplied from the SMPS only */
#define PMU_SMPS_1V8_SUPPLIES_LDO (PMU_STEPDOWNVOL_1P8 | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the V0.9V domains */
#define PMU_SMPS_2V5_SUPPLIES_LDO (PMU_STEPDOWNVOL_2P5 | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the V0.9V domains */
#define PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PMU_STEPDOWNVOL_1P8 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The V0.9V domains are suppplied from the LDO */
#define PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PMU_STEPDOWNVOL_2P5 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The V0.9V domains are suppplied from the LDO */
#define PMU_SMPS_1V8_SUPPLIES_EXT (PMU_STEPDOWNVOL_1P8 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the V0.9V domains */
#define PMU_SMPS_2V5_SUPPLIES_EXT (PMU_STEPDOWNVOL_2P5 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the V0.9V domains */
#define PMU_BYPASS PMU_CTL2_BYPASS /*!< The SMPS disabled and the LDO Bypass. The V0.9V domains are supplied from an external source */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
/* function declarations */
/* reset PMU registers */
void pmu_deinit(void);
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t lvdt_n);
/* enable PMU lvd */
void pmu_lvd_enable(void);
/* disable PMU lvd */
void pmu_lvd_disable(void);
/* select analog voltage detector threshold */
void pmu_avd_select(uint32_t avdt_n);
/* enable PMU analog voltage detector */
void pmu_avd_enable(void);
/* disable PMU analog voltage detector */
void pmu_avd_disable(void);
/* enable PMU core voltage detector */
void pmu_cvd_enable(void);
/* disable PMU V0.9V core voltage detector */
void pmu_cvd_disable(void);
/* control the V0.9V core voltage level */
void pmu_ldo_output_select(uint32_t ldo_n);
/* Deep-sleep mode V0.9V core voltage select */
void pmu_sldo_output_select(uint32_t sldo_n);
/* PMU VBAT battery charging resistor selection */
void pmu_vbat_charging_select(uint32_t resistor);
/* enable VBAT battery charging */
void pmu_vbat_charging_enable(void);
/* disable VBAT battery charging */
void pmu_vbat_charging_disable(void);
/* enable VBAT and temperature monitoring */
void pmu_vbat_temp_moniter_enable(void);
/* disable VBAT and temperature monitoring */
void pmu_vbat_temp_moniter_disable(void);
/* USB regulator */
/* enable USB regulator */
void pmu_usb_regulator_enable(void);
/* disable USB regulator */
void pmu_usb_regulator_disable(void);
/* enable VDD33USB voltage level detector */
void pmu_usb_voltage_detector_enable(void);
/* disable VDD33USB voltage level detector */
void pmu_usb_voltage_detector_disable(void);
/* power supply configurations */
void pmu_smps_ldo_supply_config(uint32_t smpsmode);
/* set PMU mode */
/* enter sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* enter deepsleep mode */
void pmu_to_deepsleepmode(uint8_t deepsleepmodecmd);
/* enter standby mode */
void pmu_to_standbymode(void);
/* enable PMU wakeup pin */
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
/* disable PMU wakeup pin */
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
/* backup related functions */
/* enable backup domain write */
void pmu_backup_write_enable(void);
/* disable backup domain write */
void pmu_backup_write_disable(void);
/* enable backup voltage stabilizer */
void pmu_backup_voltage_stabilizer_enable(void);
/* disable backup voltage stabilizer */
void pmu_backup_voltage_stabilizer_disable(void);
/* configure IRC counter before enter Deep-sleep mode */
void pmu_enter_deepsleep_wait_time_config(uint32_t wait_time);
/* configure IRC counter before exit Deep-sleep mode */
void pmu_exit_deepsleep_wait_time_config(uint32_t wait_time);
/* flag functions */
/* get flag state */
FlagStatus pmu_flag_get(uint32_t flag);
/* clear flag bit */
void pmu_flag_clear(uint32_t flag_reset);
#endif /* GD32H7XX_PMU_H */

181
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_rameccmu.h Normal file
View File

@@ -0,0 +1,181 @@
/*!
\file gd32h7xx_rameccmu.h
\brief definitions for the RAMECCMU
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H7XX_RAMECCMU_H
#define GD32H7XX_RAMECCMU_H
#include "gd32h7xx.h"
/* RAMECCMU definitions */
#define RAMECCMU0 (RAMECCMU_BASE + 0x09FE6000U) /*!< RAMECCMU for Region 0 */
#define RAMECCMU1 RAMECCMU_BASE /*!< RAMECCMU for Region 1 */
/* registers definitions */
#define RAMECCMU_INT(rameccmux) REG32((rameccmux) + 0x00000000U) /*!< RAMECCMU global interruput register */
#define RAMECCMU_M0CTL(rameccmux) REG32((rameccmux) + 0x00000020U) /*!< RAMECCMU monitor 0 control register */
#define RAMECCMU_M0STAT(rameccmux) REG32((rameccmux) + 0x00000024U) /*!< RAMECCMU monitor 0 status register */
#define RAMECCMU_M0FADDR(rameccmux) REG32((rameccmux) + 0x00000028U) /*!< RAMECCMU monitor 0 ECC failing address register */
#define RAMECCMU_M0FDL(rameccmux) REG32((rameccmux) + 0x0000002CU) /*!< RAMECCMU monitor 0 ECC failing data low register */
#define RAMECCMU_M0FDH(rameccmux) REG32((rameccmux) + 0x00000030U) /*!< RAMECCMU monitor 0 ECC failing data high register */
#define RAMECCMU_M0FECODE(rameccmux) REG32((rameccmux) + 0x00000034U) /*!< RAMECCMU monitor 0 failing ECC error code register */
#define RAMECCMU_M1CTL(rameccmux) REG32((rameccmux) + 0x00000040U) /*!< RAMECCMU monitor 1 control register */
#define RAMECCMU_M1STAT(rameccmux) REG32((rameccmux) + 0x00000044U) /*!< RAMECCMU monitor 1 status register */
#define RAMECCMU_M1FADDR(rameccmux) REG32((rameccmux) + 0x00000048U) /*!< RAMECCMU monitor 1 ECC failing address register */
#define RAMECCMU_M1FDL(rameccmux) REG32((rameccmux) + 0x0000004CU) /*!< RAMECCMU monitor 1 ECC failing data low register */
#define RAMECCMU_M1FDH(rameccmux) REG32((rameccmux) + 0x00000050U) /*!< RAMECCMU monitor 1 ECC failing data high register */
#define RAMECCMU_M1FECODE(rameccmux) REG32((rameccmux) + 0x00000054U) /*!< RAMECCMU monitor 1 failing ECC error code register */
#define RAMECCMU_M2CTL(rameccmux) REG32((rameccmux) + 0x00000060U) /*!< RAMECCMU monitor 2 control register */
#define RAMECCMU_M2STAT(rameccmux) REG32((rameccmux) + 0x00000064U) /*!< RAMECCMU monitor 2 status register */
#define RAMECCMU_M2FADDR(rameccmux) REG32((rameccmux) + 0x00000068U) /*!< RAMECCMU monitor 2 ECC failing address register */
#define RAMECCMU_M2FDL(rameccmux) REG32((rameccmux) + 0x0000006CU) /*!< RAMECCMU monitor 2 ECC failing data low register */
#define RAMECCMU_M2FDH(rameccmux) REG32((rameccmux) + 0x00000070U) /*!< RAMECCMU monitor 2 ECC failing data high register */
#define RAMECCMU_M2FECODE(rameccmux) REG32((rameccmux) + 0x00000074U) /*!< RAMECCMU monitor 2 failing ECC error code register */
#define RAMECCMU_M3CTL(rameccmux) REG32((rameccmux) + 0x00000080U) /*!< RAMECCMU monitor 3 control register */
#define RAMECCMU_M3STAT(rameccmux) REG32((rameccmux) + 0x00000084U) /*!< RAMECCMU monitor 3 status register */
#define RAMECCMU_M3FADDR(rameccmux) REG32((rameccmux) + 0x00000088U) /*!< RAMECCMU monitor 3 ECC failing address register */
#define RAMECCMU_M3FDL(rameccmux) REG32((rameccmux) + 0x0000008CU) /*!< RAMECCMU monitor 3 ECC failing data low register */
#define RAMECCMU_M3FDH(rameccmux) REG32((rameccmux) + 0x00000090U) /*!< RAMECCMU monitor 3 ECC failing data high register */
#define RAMECCMU_M3FECODE(rameccmux) REG32((rameccmux) + 0x00000094U) /*!< RAMECCMU monitor 3 failing ECC error code register */
#define RAMECCMU_M4CTL(rameccmux) REG32((rameccmux) + 0x000000A0U) /*!< RAMECCMU monitor 4 control register */
#define RAMECCMU_M4STAT(rameccmux) REG32((rameccmux) + 0x000000A4U) /*!< RAMECCMU monitor 4 status register */
#define RAMECCMU_M4FADDR(rameccmux) REG32((rameccmux) + 0x000000A8U) /*!< RAMECCMU monitor 4 ECC failing address register */
#define RAMECCMU_M4FDL(rameccmux) REG32((rameccmux) + 0x000000ACU) /*!< RAMECCMU monitor 4 ECC failing data low register */
#define RAMECCMU_M4FDH(rameccmux) REG32((rameccmux) + 0x000000B0U) /*!< RAMECCMU monitor 4 ECC failing data high register */
#define RAMECCMU_M4FECODE(rameccmux) REG32((rameccmux) + 0x000000B4U) /*!< RAMECCMU monitor 4 failing ECC error code register */
/* bits definitions */
/* RAMECCMU_INT */
#define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */
#define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */
#define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */
#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
/* RAMECCMU_MxCTL */
#define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */
#define RAMECCMU_MXCTL_ECCERRLATEN BIT(5) /*!< ECC error latching enable */
/* RAMECCMU_MxSTAT */
#define RAMECCMU_MXSTAT_ECCSERRDCF BIT(0) /*!< ECC single error detected and corrected flag */
#define RAMECCMU_MXSTAT_ECCDERRDF BIT(1) /*!< ECC double error detected flag */
#define RAMECCMU_MXSTAT_ECCDERRBWDF BIT(2) /*!< ECC double error on byte write detected flag */
/* RAMECCMU_MxFADDR */
#define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */
/* RAMECCMU_MxFDL */
#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
/* RAMECCMU_MxFDH */
#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
/* RAMECCMU_MxFECODE */
#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
/* constants definitions */
/* RAMECCMU monitor select */
typedef enum
{
RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */
RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */
RAMECCMU0_MONITOR2 = 0x02U, /*!< RAMECCMU0 monitor 2 */
RAMECCMU0_MONITOR3 = 0x03U, /*!< RAMECCMU0 monitor 3 */
RAMECCMU0_MONITOR4 = 0x04U, /*!< RAMECCMU0 monitor 4 */
RAMECCMU1_MONITOR0 = 0x10U, /*!< RAMECCMU1 monitor 0 */
RAMECCMU1_MONITOR1 = 0x11U, /*!< RAMECCMU1 monitor 1 */
RAMECCMU1_MONITOR2 = 0x12U /*!< RAMECCMU1 monitor 2 */
} rameccmu_monitor_enum;
/* RAMECCMUx monitor register address */
#define RAMECCMU_MXCTL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x20U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor control register */
#define RAMECCMU_MXSTAT(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x24U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor status register */
#define RAMECCMU_MXFADDR(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x28U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing address register */
#define RAMECCMU_MXFDL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x2CU + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data low register */
#define RAMECCMU_MXFDH(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x30U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data high register */
#define RAMECCMU_MXFECODE(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x34U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor failing ECC error code register */
#define RAMECCMU_INT_ECC_GLOBAL_ERROR BIT(0) /*!< ECC global error interrupt */
#define RAMECCMU_INT_ECC_SINGLE_ERROR BIT(1) /*!< ECC single error interrupt */
#define RAMECCMU_INT_ECC_DOUBLE_ERROR BIT(2) /*!< ECC double error interrupt */
#define RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE BIT(3) /*!< ECC double error on byte write interrupt */
#define RAMECCMU_INT_ECC_ERROR_LATCHING BIT(4) /*!< ECC error latching */
#define RAMECCMU_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
#define RAMECCMU_INT_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
/* function declarations */
/* deinit RAMECCMU unit */
void rameccmu_deinit(uint32_t rameccmu_periph);
/* RAMECCMU monitor ECC functions */
/* get RAMECCMU monitor ECC failing address */
uint32_t rameccmu_monitor_failing_address_get(rameccmu_monitor_enum rameccmu_monitor);
/* get RAMECCMU monitor ECC failing data low 32 bits */
uint32_t rameccmu_monitor_failing_data_low_bits_get(rameccmu_monitor_enum rameccmu_monitor);
/* get RAMECCMU monitor ECC failing data high 32 bits */
uint32_t rameccmu_monitor_failing_data_high_bits_get(rameccmu_monitor_enum rameccmu_monitor);
/* get RAMECCMU monitor failing ECC error code */
uint32_t rameccmu_monitor_failing_ecc_error_code_get(rameccmu_monitor_enum rameccmu_monitor);
/* interrupt & flag functions */
/* enable RAMECCMU global ECC interruput */
void rameccmu_global_interrupt_enable(uint32_t rameccmu_periph, uint32_t interrupt);
/* disable RAMECCMU global ECC interruput */
void rameccmu_global_interrupt_disable(uint32_t rameccmu_periph, uint32_t interrupt);
/* enable RAMECCMU monitor ECC error interruput */
void rameccmu_monitor_interrupt_enable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
/* disable RAMECCMU monitor ECC error interruput */
void rameccmu_monitor_interrupt_disable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
/* get RAMECCMU monitor ECC error flag */
FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
/* clear RAMECCMU monitor ECC error flag */
void rameccmu_monitor_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
/* get RAMECCMU monitor ECC interrupt error flag */
FlagStatus rameccmu_monitor_interrupt_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
/* clear RAMECCMU monitor interrupt ECC error flag */
void rameccmu_monitor_interrupt_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
#endif /* GD32H7XX_RAMECCMU_H */

Some files were not shown because too many files have changed in this diff Show More