mirror of
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add GD32H7xx library
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wirano
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/*!
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\file system_gd32h7xx.h
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\brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File for
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gd32h7xx Device Series
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*/
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/*
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* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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* Copyright (c) 2024, GigaDevice Semiconductor Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#ifndef SYSTEM_GD32H7XX_H
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#define SYSTEM_GD32H7XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/* system clock frequency (core clock) */
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extern uint32_t SystemCoreClock;
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/* function declarations */
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/* initialize the system and update the SystemCoreClock variable */
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extern void SystemInit (void);
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/* update the SystemCoreClock with current core clock retrieved from cpu registers */
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extern void SystemCoreClockUpdate (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYSTEM_GD32H7XX_H */
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/**************************************************************************//**
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* @file cmsis_version.h
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* @brief CMSIS Core(M) Version definitions
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* @version V5.0.5
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* @date 02. February 2022
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******************************************************************************/
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/*
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* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__clang__)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef __CMSIS_VERSION_H
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#define __CMSIS_VERSION_H
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/* CMSIS Version definitions */
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#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
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#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
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#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
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__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
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#endif
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/*!
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\file gd32h7xx_cpdm.h
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\brief definitions for the CPDM
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\version 2024-01-05, V1.2.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2024, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_CPDM_H
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#define GD32H7XX_CPDM_H
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#include "gd32h7xx.h"
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/* CPDM definitions */
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#define CPDM_SDIO0 (SDIO0 + 0x00001000U) /*!< SDIO0 CPDM base address */
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#define CPDM_SDIO1 (SDIO1 + 0x00000400U) /*!< SDIO1 CPDM base address */
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/* registers definitions */
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#define CPDM_CTL(cpdmx) REG32((cpdmx) + 0x00000000U) /*!< CPDM control register */
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#define CPDM_CFG(cpdmx) REG32((cpdmx) + 0x00000004U) /*!< CPDM configuration register */
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/* bits definitions */
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/* CPDM_CTL */
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#define CPDM_CTL_CPDMEN BIT(0) /*!< CPDM enable */
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#define CPDM_CTL_DLSEN BIT(1) /*!< CPDM delay line sample module enable */
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/* CPDM_CFG */
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#define CPDM_CFG_CPSEL BITS(0,3) /*!< select the phase of the output clock */
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#define CPDM_CFG_DLSTCNT BITS(8,14) /*!< define a delay step count for a unit delay UNIT */
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#define CPDM_CFG_DLLEN BITS(16,27) /*!< delay line length */
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#define CPDM_CFG_DLLENF BIT(31) /*!< valid mark of delay line length */
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/* constants definitions */
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/* output clock phase selection enum definition */
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typedef enum
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{
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CPDM_OUTPUT_PHASE_SELECTION_0 = 0, /*!< output clock phase = input clock */
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CPDM_OUTPUT_PHASE_SELECTION_1, /*!< output clock phase = input clock + 1 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_2, /*!< output clock phase = input clock + 2 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_3, /*!< output clock phase = input clock + 3 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_4, /*!< output clock phase = input clock + 4 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_5, /*!< output clock phase = input clock + 5 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_6, /*!< output clock phase = input clock + 6 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_7, /*!< output clock phase = input clock + 7 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_8, /*!< output clock phase = input clock + 8 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_9, /*!< output clock phase = input clock + 9 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_10, /*!< output clock phase = input clock + 10 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_11, /*!< output clock phase = input clock + 11 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_12, /*!< output clock phase = input clock + 12 * UNIT delay */
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}cpdm_output_phase_enum;
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#define CPDM_MAX_DELAY_STEP_COUNT ((uint32_t)0x0000007FU) /*!< max UNIT value */
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#define CPDM_MAX_PHASE ((uint32_t)0x0000000CU) /*!< max select value of the phase */
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/* function declarations */
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/* deinitialization and initialization functions */
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/* enable CPDM */
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void cpdm_enable(uint32_t cpdm_periph);
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/* disable CPDM */
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void cpdm_disable(uint32_t cpdm_periph);
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/* enable CPDM delay line sample module */
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void cpdm_delayline_sample_enable(uint32_t cpdm_periph);
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/* disable CPDM delay line sample module */
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void cpdm_delayline_sample_disable(uint32_t cpdm_periph);
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/* output clock configuration functions */
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/* select CPDM output clock phase */
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void cpdm_output_clock_phase_select(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase);
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/* get delay line length valid flag */
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FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph);
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/* get delay line length */
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uint16_t cpdm_delayline_length_get(uint32_t cpdm_periph);
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/* clock output function */
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/* configure CPDM clock output */
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void cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase);
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#endif /* GD32H7XX_CPDM_H */
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/*!
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\file gd32h7xx_crc.h
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\brief definitions for the CRC
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\version 2024-01-05, V1.2.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2024, GigaDevice Semiconductor Inc.
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||||
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||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_CRC_H
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#define GD32H7XX_CRC_H
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#include "gd32h7xx.h"
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/* CRC definitions */
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#define CRC CRC_BASE /*!< CRC bsae address */
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/* registers definitions */
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#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
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#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
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#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
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#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
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#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
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/* bits definitions */
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/* CRC_DATA */
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#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
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/* CRC_FDATA */
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#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
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/* CRC_CTL */
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#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
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#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
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#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
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#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
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/* CRC_INIT */
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#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
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/* CRC_POLY */
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#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
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/* constants definitions */
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/* size of polynomial function */
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#define CTL_PS(regval) (BITS(3,4) & ((regval) << 3U))
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#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
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#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
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#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
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#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
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/* input data reverse function */
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#define CTL_REV_I(regval) (BITS(5,6) & ((regval) << 5U))
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#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
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#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
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#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
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#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
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/* input data format */
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#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
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#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
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#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
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/* function declarations */
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/* deinit CRC calculation unit */
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void crc_deinit(void);
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/* enable the reverse operation of output data */
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void crc_reverse_output_data_enable(void);
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/* disable the reverse operation of output data */
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void crc_reverse_output_data_disable(void);
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/* reset data register to the value of initialization data register */
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void crc_data_register_reset(void);
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/* read the data register */
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uint32_t crc_data_register_read(void);
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/* read the free data register */
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uint8_t crc_free_data_register_read(void);
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/* write the free data register */
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void crc_free_data_register_write(uint8_t free_data);
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/* write the initial value register */
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void crc_init_data_register_write(uint32_t init_data);
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/* configure the CRC input data function */
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void crc_input_data_reverse_config(uint32_t data_reverse);
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/* configure the CRC size of polynomial function */
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void crc_polynomial_size_set(uint32_t poly_size);
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/* configure the CRC polynomial value function */
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void crc_polynomial_set(uint32_t poly);
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/* CRC calculate single data */
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uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
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/* CRC calculate a data array */
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uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
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#endif /* GD32H7XX_CRC_H */
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/*!
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\file gd32h7xx_ctc.h
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\brief definitions for the CTC
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\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_CTC_H
|
||||
#define GD32H7XX_CTC_H
|
||||
|
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#include "gd32h7xx.h"
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||||
|
||||
/* CTC definitions */
|
||||
#define CTC CTC_BASE
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||||
|
||||
/* registers definitions */
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||||
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
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||||
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
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||||
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
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||||
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CTC_CTL0 */
|
||||
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
|
||||
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
|
||||
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
|
||||
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
|
||||
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
|
||||
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
|
||||
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
|
||||
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
|
||||
|
||||
/* CTC_CTL1 */
|
||||
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
|
||||
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||
|
||||
/* CTC_STAT */
|
||||
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
|
||||
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
|
||||
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
|
||||
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
|
||||
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
|
||||
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
|
||||
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
|
||||
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
|
||||
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
|
||||
|
||||
/* CTC_INTC */
|
||||
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
|
||||
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
|
||||
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
|
||||
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* hardware automatically trim mode definitions */
|
||||
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
|
||||
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
|
||||
|
||||
/* reference signal source polarity definitions */
|
||||
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||
|
||||
/* reference signal source selection definitions */
|
||||
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
|
||||
|
||||
/* reference signal source prescaler definitions */
|
||||
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
|
||||
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
|
||||
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
|
||||
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
|
||||
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
|
||||
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
|
||||
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
|
||||
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
|
||||
|
||||
/* CTC interrupt enable definitions */
|
||||
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
|
||||
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
|
||||
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
|
||||
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
|
||||
|
||||
/* CTC interrupt source definitions */
|
||||
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
|
||||
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
|
||||
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
|
||||
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
|
||||
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
|
||||
|
||||
/* CTC flag definitions */
|
||||
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
|
||||
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
|
||||
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
|
||||
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
|
||||
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ctc clock trim controller */
|
||||
void ctc_deinit(void);
|
||||
|
||||
/* enable CTC trim counter */
|
||||
void ctc_counter_enable(void);
|
||||
/* disable CTC trim counter */
|
||||
void ctc_counter_disable(void);
|
||||
|
||||
/* configure the IRC48M trim value */
|
||||
void ctc_irc48m_trim_value_config(uint8_t trim_value);
|
||||
/* generate software reference source sync pulse */
|
||||
void ctc_software_refsource_pulse_generate(void);
|
||||
/* configure hardware automatically trim mode */
|
||||
void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||
|
||||
/* configure reference signal source polarity */
|
||||
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||
/* select reference signal source */
|
||||
void ctc_refsource_signal_select(uint32_t refs);
|
||||
/* configure reference signal source prescaler */
|
||||
void ctc_refsource_prescaler_config(uint32_t prescaler);
|
||||
/* configure clock trim base limit value */
|
||||
void ctc_clock_limit_value_config(uint8_t limit_value);
|
||||
/* configure CTC counter reload value */
|
||||
void ctc_counter_reload_value_config(uint16_t reload_value);
|
||||
|
||||
/* read CTC counter capture value when reference sync pulse occurred */
|
||||
uint16_t ctc_counter_capture_value_read(void);
|
||||
/* read CTC trim counter direction when reference sync pulse occurred */
|
||||
FlagStatus ctc_counter_direction_read(void);
|
||||
/* read CTC counter reload value */
|
||||
uint16_t ctc_counter_reload_value_read(void);
|
||||
/* read the IRC48M trim value */
|
||||
uint8_t ctc_irc48m_trim_value_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get CTC flag */
|
||||
FlagStatus ctc_flag_get(uint32_t flag);
|
||||
/* clear CTC flag */
|
||||
void ctc_flag_clear(uint32_t flag);
|
||||
/* enable the CTC interrupt */
|
||||
void ctc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable the CTC interrupt */
|
||||
void ctc_interrupt_disable(uint32_t interrupt);
|
||||
/* get CTC interrupt flag */
|
||||
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear CTC interrupt flag */
|
||||
void ctc_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
|
||||
#endif /* GD32H7XX_CTC_H */
|
||||
+321
File diff suppressed because it is too large
Load Diff
+187
@@ -0,0 +1,187 @@
|
||||
/*!
|
||||
\file gd32h7xx_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_DBG_H
|
||||
#define GD32H7XX_DBG_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE /*!< DBG base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x00000034U) /*!< DBG control register 1 */
|
||||
#define DBG_CTL2 REG32(DBG + 0x0000003CU) /*!< DBG control register 2 */
|
||||
#define DBG_CTL3 REG32(DBG + 0x0000004CU) /*!< DBG control register 3 */
|
||||
#define DBG_CTL4 REG32(DBG + 0x00000054U) /*!< DBG control register 4 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_TRACE_MODE BITS(18,19) /*!< trace pin mode selection */
|
||||
#define DBG_CTL0_TRACECLKEN BIT(20) /*!< enable trace pin assignment */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_WWDGT_HOLD BIT(6) /*!< debug WWDGT kept when core is halted */
|
||||
|
||||
/* DBG_CTL2 */
|
||||
#define DBG_CTL2_TIMER1_HOLD BIT(0) /*!< debug TIMER1 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER2_HOLD BIT(1) /*!< debug TIMER2 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER3_HOLD BIT(2) /*!< debug TIMER3 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER4_HOLD BIT(3) /*!< debug TIMER4 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER5_HOLD BIT(4) /*!< debug TIMER5 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER6_HOLD BIT(5) /*!< debug TIMER6 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER22_HOLD BIT(6) /*!< debug TIMER22 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER23_HOLD BIT(7) /*!< debug TIMER23 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER30_HOLD BIT(8) /*!< debug TIMER30 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER31_HOLD BIT(9) /*!< debug TIMER31 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER50_HOLD BIT(10) /*!< debug TIMER50 kept when core is halted */
|
||||
#define DBG_CTL2_TIMER51_HOLD BIT(11) /*!< debug TIMER51 kept when core is halted */
|
||||
#define DBG_CTL2_I2C0_HOLD BIT(21) /*!< debug I2C0 kept when core is halted */
|
||||
#define DBG_CTL2_I2C1_HOLD BIT(22) /*!< debug I2C1 kept when core is halted */
|
||||
#define DBG_CTL2_I2C2_HOLD BIT(23) /*!< debug I2C2 kept when core is halted */
|
||||
#define DBG_CTL2_I2C3_HOLD BIT(24) /*!< debug I2C3 kept when core is halted */
|
||||
|
||||
/* DBG_CTL3 */
|
||||
#define DBG_CTL3_TIMER0_HOLD BIT(0) /*!< debug TIMER0 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER7_HOLD BIT(1) /*!< debug TIMER7 kept when core is halted */
|
||||
#define DBG_CTL3_CAN0_HOLD BIT(2) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL3_CAN1_HOLD BIT(3) /*!< debug CAN1 kept when core is halted */
|
||||
#define DBG_CTL3_CAN2_HOLD BIT(4) /*!< debug CAN2 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER14_HOLD BIT(16) /*!< debug TIMER14 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER15_HOLD BIT(17) /*!< debug TIMER15 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER16_HOLD BIT(18) /*!< debug TIMER16 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER40_HOLD BIT(19) /*!< debug TIMER40 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER41_HOLD BIT(20) /*!< debug TIMER41 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER42_HOLD BIT(21) /*!< debug TIMER42 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER43_HOLD BIT(22) /*!< debug TIMER43 kept when core is halted */
|
||||
#define DBG_CTL3_TIMER44_HOLD BIT(23) /*!< debug TIMER44 kept when core is halted */
|
||||
|
||||
/* DBG_CTL4 */
|
||||
#define DBG_CTL4_RTC_HOLD BIT(16) /*!< debug RTC kept when core is halted */
|
||||
#define DBG_CTL4_FWDGT_HOLD BIT(18) /*!< debug FWDGT kept when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
|
||||
/* register index */
|
||||
typedef enum
|
||||
{
|
||||
DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */
|
||||
DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */
|
||||
DBG_IDX_CTL3 = 0x4CU, /*!< DBG control register 3 offset */
|
||||
DBG_IDX_CTL4 = 0x54U /*!< DBG control register 4 offset */
|
||||
}dbg_reg_idx;
|
||||
|
||||
/* peripherals hold bit */
|
||||
typedef enum
|
||||
{
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_I2C3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 24U), /*!< debug I2C3 kept when core is halted */
|
||||
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 23U), /*!< debug I2C2 kept when core is halted */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 22U), /*!< debug I2C1 kept when core is halted */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 21U), /*!< debug I2C0 kept when core is halted */
|
||||
DBG_TIMER51_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 11U), /*!< debug TIMER51 kept when core is halted */
|
||||
DBG_TIMER50_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 10U), /*!< debug TIMER50 kept when core is halted */
|
||||
DBG_TIMER31_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 9U), /*!< debug TIMER31 kept when core is halted */
|
||||
DBG_TIMER30_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 8U), /*!< debug TIMER30 kept when core is halted */
|
||||
DBG_TIMER23_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 7U), /*!< debug TIMER23 kept when core is halted */
|
||||
DBG_TIMER22_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 6U), /*!< debug TIMER22 kept when core is halted */
|
||||
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 5U), /*!< debug TIMER6 kept when core is halted */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 4U), /*!< debug TIMER5 kept when core is halted */
|
||||
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 3U), /*!< debug TIMER4 kept when core is halted */
|
||||
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 2U), /*!< debug TIMER3 kept when core is halted */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< debug TIMER2 kept when core is halted */
|
||||
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< debug TIMER1 kept when core is halted */
|
||||
DBG_TIMER44_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 23U), /*!< debug TIMER44 kept when core is halted */
|
||||
DBG_TIMER43_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 22U), /*!< debug TIMER43 kept when core is halted */
|
||||
DBG_TIMER42_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 21U), /*!< debug TIMER42 kept when core is halted */
|
||||
DBG_TIMER41_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 20U), /*!< debug TIMER41 kept when core is halted */
|
||||
DBG_TIMER40_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 19U), /*!< debug TIMER40 kept when core is halted */
|
||||
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 18U), /*!< debug TIMER16 kept when core is halted */
|
||||
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */
|
||||
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */
|
||||
DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */
|
||||
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
|
||||
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 18U), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 16U) /*!< debug RTC kept when core is halted */
|
||||
}dbg_periph_enum;
|
||||
|
||||
#define CTL0_TRACE_MODE(regval) (BITS(18,19) & ((uint32_t)(regval) << 18U))
|
||||
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/*enable low power behavior when the mcu is in debug mode*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/*disable low power behavior when the mcu is in debug mode*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/*enable trace pin assignment*/
|
||||
void dbg_trace_pin_enable(void);
|
||||
/*disable trace pin assignment*/
|
||||
void dbg_trace_pin_disable(void);
|
||||
/* set trace pin mode */
|
||||
void dbg_trace_pin_mode_set(uint32_t trace_mode);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32H7XX_DBG_H */
|
||||
+276
File diff suppressed because it is too large
Load Diff
+1015
File diff suppressed because it is too large
Load Diff
+110
@@ -0,0 +1,110 @@
|
||||
/*!
|
||||
\file gd32h7xx_edout.c
|
||||
\brief definitions for the EDOUT
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_EDOUT_H
|
||||
#define GD32H7XX_EDOUT_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* EDOUT definition */
|
||||
#define EDOUT EDOUT_BASE /*!< EDOUT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define EDOUT_CTL REG32((EDOUT) + 0x00000000U) /*!< EDOUT control register */
|
||||
#define EDOUT_ENABLE REG32((EDOUT) + 0x00000004U) /*!< EDOUT enable register */
|
||||
#define EDOUT_LOC REG32((EDOUT) + 0x00000008U) /*!< EDOUT location register */
|
||||
#define EDOUT_OCNT REG32((EDOUT) + 0x0000000CU) /*!< EDOUT output counter register */
|
||||
#define EDOUT_LCNT REG32((EDOUT) + 0x00000010U) /*!< EDOUT location counter register */
|
||||
#define EDOUT_ZCR REG32((EDOUT) + 0x00000014U) /*!< EDOUT Z-phase configure register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EDOUT_CTL */
|
||||
#define EDOUT_CTL_POL BIT(0) /*!< active polarity of the B-phase output signal selection */
|
||||
|
||||
/* EDOUT_ENABLE */
|
||||
#define EDOUT_ENABLE_EDOUTEN BIT(0) /*!< EDOUT enable bit */
|
||||
|
||||
/* EDOUT_LOC */
|
||||
#define EDOUT_LOC_LOCMAX BITS(0,15) /*!< maximum location value for one rotation */
|
||||
|
||||
/* EDOUT_OCNT */
|
||||
#define EDOUT_OCNT_EDGC BITS(0,15) /*!< number of edges of the A-phase and the B-phase signal for the next update period */
|
||||
#define EDOUT_OCNT_PDC BITS(16,31) /*!< phase difference between the A-phase and the B-phase signal for the next update period */
|
||||
|
||||
/* EDOUT_LCNT */
|
||||
#define EDOUT_LCNT_LOCCNT BITS(0,15) /*!< current location value */
|
||||
|
||||
/* EDOUT_ZCR */
|
||||
#define EDOUT_ZCR_ZOSP BITS(0,15) /*!< Z-phase output start location */
|
||||
#define EDOUT_ZCR_ZOWH BITS(16,23) /*!< Z-phase output width */
|
||||
#define EDOUT_ZCR_ZOMD BIT(24) /*!< Z-phase output mode */
|
||||
|
||||
/* constants definitions */
|
||||
/* EDOUT_CTL */
|
||||
#define EDOUT_POL_POSITIVE ((uint32_t)0x00000000U) /*!< active polarity is positive */
|
||||
#define EDOUT_POL_NEGATIVE EDOUT_CTL_POL /*!< active polarity is negative */
|
||||
|
||||
/* EDOUT_ENABLE */
|
||||
#define EDOUT_STATE_DISABLE ((uint32_t)0x00000000U) /*!< disable EDOUT */
|
||||
#define EDOUT_STATE_ENABLE EDOUT_ENABLE_EDOUTEN /*!< enable EDOUT */
|
||||
|
||||
/* EDOUT_ZCR */
|
||||
#define EDOUT_Z_OUTPUT_MODE0 ((uint32_t)0x00000000U) /*!< Z-phase output according to the current location */
|
||||
#define EDOUT_Z_OUTPUT_MODE1 EDOUT_ZCR_ZOMD /*!< Z-phase output according to the number of edges */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize EDOUT */
|
||||
void edout_deinit(void);
|
||||
/* initialize EDOUT */
|
||||
void edout_init(uint32_t pol, uint32_t max_loc, uint32_t cur_loc);
|
||||
/* enable EDOUT */
|
||||
void edout_enable(void);
|
||||
/* disable EDOUT */
|
||||
void edout_disable(void);
|
||||
/* set B-phase active polarity */
|
||||
void edout_polarity_config(uint32_t pol);
|
||||
/* set the maximum location value for one rotation */
|
||||
void edout_max_location_value_config(uint32_t max_loc);
|
||||
/* update the output counter, used to set the phase difference and the number of edges for the next update period */
|
||||
void edout_output_counter_update(int16_t num_edges, uint16_t phase_diff);
|
||||
/* set the current location value */
|
||||
void edout_current_location_config(uint32_t cur_loc);
|
||||
/* get the current location value */
|
||||
uint16_t edout_current_location_get(void);
|
||||
/* configure Z-phase output mode */
|
||||
void edout_z_output_mode_config(uint32_t mode);
|
||||
/* configure Z-phase output start location and width */
|
||||
void edout_z_output_start_loc_and_width_config(uint32_t start_loc, uint32_t width);
|
||||
|
||||
#endif /* GD32H7XX_EDOUT_H */
|
||||
+259
File diff suppressed because it is too large
Load Diff
+1677
File diff suppressed because it is too large
Load Diff
+638
File diff suppressed because it is too large
Load Diff
+413
File diff suppressed because it is too large
Load Diff
+268
File diff suppressed because it is too large
Load Diff
+534
File diff suppressed because it is too large
Load Diff
+117
@@ -0,0 +1,117 @@
|
||||
/*!
|
||||
\file gd32h7xx_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_FWDGT_H
|
||||
#define GD32H7XX_FWDGT_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
||||
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
|
||||
|
||||
/* FWDGT_WND */
|
||||
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
|
||||
|
||||
/* constants definitions */
|
||||
/* FWDGT_PSC register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
|
||||
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the FWDGT counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the FWDGT counter prescaler value */
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||
/* configure the FWDGT counter reload value */
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||
/* configure the FWDGT counter window value */
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32H7XX_FWDGT_H */
|
||||
+442
File diff suppressed because it is too large
Load Diff
+223
File diff suppressed because it is too large
Load Diff
+760
File diff suppressed because it is too large
Load Diff
+365
File diff suppressed because it is too large
Load Diff
+408
File diff suppressed because it is too large
Load Diff
+479
File diff suppressed because it is too large
Load Diff
+195
@@ -0,0 +1,195 @@
|
||||
/*!
|
||||
\file gd32h7xx_lpdts.h
|
||||
\brief definitions for the LPDTS
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_LPDTS_H
|
||||
#define GD32H7XX_LPDTS_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* LPDTS definitions */
|
||||
#define LPDTS LPDTS_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define LPDTS_CFG REG32(LPDTS + 0x00000000U) /*!< LPDTS configuration register */
|
||||
#define LPDTS_SDATA REG32(LPDTS + 0x00000008U) /*!< LPDTS sensor T0 data register */
|
||||
#define LPDTS_RDATA REG32(LPDTS + 0x00000010U) /*!< LPDTS ramp data register */
|
||||
#define LPDTS_IT REG32(LPDTS + 0x00000014U) /*!< LPDTS interrupt threshold register */
|
||||
#define LPDTS_DATA REG32(LPDTS + 0x0000001CU) /*!< LPDTS temperature data register */
|
||||
#define LPDTS_STAT REG32(LPDTS + 0x00000020U) /*!< LPDTS temperature sensor status register */
|
||||
#define LPDTS_INTEN REG32(LPDTS + 0x00000024U) /*!< LPDTS interrupt enable register */
|
||||
#define LPDTS_INTC REG32(LPDTS + 0x00000028U) /*!< LPDTS interrupt clear flag register */
|
||||
#define LPDTS_OP REG32(LPDTS + 0x0000002CU) /*!< LPDTS option register */
|
||||
|
||||
/* bits definitions */
|
||||
/* LPDTS_CFG */
|
||||
#define LPDTS_CFG_TSEN BIT(0) /*!< temperature sensor enable */
|
||||
#define LPDTS_CFG_TRGS BIT(4) /*!< software trigger */
|
||||
#define LPDTS_CFG_ITSEL BITS(8,11) /*!< input trigger selection */
|
||||
#define LPDTS_CFG_SPT BITS(16,19) /*!< sampling time */
|
||||
#define LPDTS_CFG_REFSEL BIT(20) /*!< reference clock selection */
|
||||
|
||||
/* LPDTS_SDATA */
|
||||
#define LPDTS_SDATA_FREQ BITS(0,15) /*!< frequency value at temperature T0 */
|
||||
#define LPDTS_SDATA_VAL BITS(16,17) /*!< temperature T0 */
|
||||
|
||||
/* LPDTS_RDATA */
|
||||
#define LPDTS_RDATA_RCVAL BITS(0,15) /*!< ramp coefficient */
|
||||
|
||||
/* LPDTS_IT */
|
||||
#define LPDTS_IT_INTLT BITS(0,15) /*!< interrupt low threshold */
|
||||
#define LPDTS_IT_INTHT BITS(16,31) /*!< interrupt high threshold */
|
||||
|
||||
/* LPDTS_DATA */
|
||||
#define LPDTS_DATA_COVAL BITS(0,15) /*!< value of the counter output */
|
||||
|
||||
/* LPDTS_STAT */
|
||||
#define LPDTS_STAT_EMIF BIT(0) /*!< end of measurement interrupt flag */
|
||||
#define LPDTS_STAT_LTIF BIT(1) /*!< low threshold interrupt flag */
|
||||
#define LPDTS_STAT_HTIF BIT(2) /*!< high threshold interrupt flag */
|
||||
#define LPDTS_STAT_EMAIF BIT(4) /*!< end of measurement asynchronous interrupt flag */
|
||||
#define LPDTS_STAT_LTAIF BIT(5) /*!< low threshold asynchronous interrupt flag */
|
||||
#define LPDTS_STAT_HTAIF BIT(6) /*!< high threshold asynchronous interrupt flag */
|
||||
#define LPDTS_STAT_TSRF BIT(15) /*!< temperature sensor ready flag */
|
||||
|
||||
/* LPDTS_INTEN */
|
||||
#define LPDTS_INTEN_EMIE BIT(0) /*!< end of measurement interrupt enable */
|
||||
#define LPDTS_INTEN_LTIE BIT(1) /*!< low threshold interrupt enable */
|
||||
#define LPDTS_INTEN_HTIE BIT(2) /*!< high threshold interrupt enable */
|
||||
#define LPDTS_INTEN_EMAIE BIT(4) /*!< end of measurement asynchronous interrupt enable */
|
||||
#define LPDTS_INTEN_LTAIE BIT(5) /*!< low threshold asynchronous interrupt enable */
|
||||
#define LPDTS_INTEN_HTAIE BIT(6) /*!< high threshold asynchronous interrupt enable */
|
||||
|
||||
/* LPDTS_INTC */
|
||||
#define LPDTS_INTC_EMIC BIT(0) /*!< end of measurement interrupt clear */
|
||||
#define LPDTS_INTC_LTIC BIT(1) /*!< low threshold interrupt clear */
|
||||
#define LPDTS_INTC_HTIC BIT(2) /*!< high threshold interrupt clear */
|
||||
#define LPDTS_INTC_EMAIC BIT(4) /*!< end of measure asynchronous interrupt clear */
|
||||
#define LPDTS_INTC_LTAIC BIT(5) /*!< low threshold asynchronous interrupt clear */
|
||||
#define LPDTS_INTC_HTAIC BIT(6) /*!< high threshold asynchronous interrupt clear */
|
||||
|
||||
/* LPDTS_OP */
|
||||
#define LPDTS_OP_OP BITS(0,31) /*!< general purpose option */
|
||||
|
||||
/* constants definitions */
|
||||
/* parameter struct definitions */
|
||||
typedef struct {
|
||||
uint32_t ref_clock; /*!< reference clock selection */
|
||||
uint32_t trigger_input; /*!< input trigger selection */
|
||||
uint32_t sampling_time; /*!< sampling time */
|
||||
} lpdts_parameter_struct;
|
||||
|
||||
/* reference clock definitions */
|
||||
#define REF_PCLK ((uint32_t)0x00000000U) /*!< high speed reference clock (PCLK) */
|
||||
#define REF_LXTAL LPDTS_CFG_REFSEL /*!< low speed reference clock (LXTAL) */
|
||||
|
||||
/* input trigger selection definitions */
|
||||
#define TRIGGER_SEL(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define NO_HARDWARE_TRIGGER TRIGGER_SEL(0) /*!< no hardware trigger signal */
|
||||
#define LPDTS_TRG TRIGGER_SEL(4) /*!< select LPDTS_TRG as trigger signal */
|
||||
|
||||
/* sampling time definitions */
|
||||
#define SMP_TIME(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||
#define SPT_CLOCK_1 SMP_TIME(1) /*!< 1 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_2 SMP_TIME(2) /*!< 2 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_3 SMP_TIME(3) /*!< 3 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_4 SMP_TIME(4) /*!< 4 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_5 SMP_TIME(5) /*!< 5 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_6 SMP_TIME(6) /*!< 6 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_7 SMP_TIME(7) /*!< 7 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_8 SMP_TIME(8) /*!< 8 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_9 SMP_TIME(9) /*!< 9 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_10 SMP_TIME(10) /*!< 10 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_11 SMP_TIME(11) /*!< 11 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_12 SMP_TIME(12) /*!< 12 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_13 SMP_TIME(13) /*!< 13 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_14 SMP_TIME(14) /*!< 14 LXTAL or FM(T) clocks */
|
||||
#define SPT_CLOCK_15 SMP_TIME(15) /*!< 15 LXTAL or FM(T) clocks */
|
||||
|
||||
/* LPDTS flags */
|
||||
#define LPDTS_FLAG_TSR LPDTS_STAT_TSRF /*!< temperature sensor ready flag */
|
||||
#define LPDTS_INT_FLAG_EM LPDTS_STAT_EMIF /*!< end of measurement interrupt flag */
|
||||
#define LPDTS_INT_FLAG_LT LPDTS_STAT_LTIF /*!< low threshold interrupt flag */
|
||||
#define LPDTS_INT_FLAG_HT LPDTS_STAT_HTIF /*!< high threshold interrupt flag */
|
||||
#define LPDTS_INT_FLAG_EMA LPDTS_STAT_EMAIF /*!< end of measurement asynchronous interrupt flag */
|
||||
#define LPDTS_INT_FLAG_LTA LPDTS_STAT_LTAIF /*!< low threshold asynchronous interrupt flag */
|
||||
#define LPDTS_INT_FLAG_HTA LPDTS_STAT_HTAIF /*!< high threshold asynchronous interrupt flag */
|
||||
|
||||
/* LPDTS interrupt enable */
|
||||
#define LPDTS_INT_EM LPDTS_INTEN_EMIE /*!< end of measurement interrupt enable */
|
||||
#define LPDTS_INT_LT LPDTS_INTEN_LTIE /*!< low threshold interrupt enable */
|
||||
#define LPDTS_INT_HT LPDTS_INTEN_HTIE /*!< high threshold interrupt enable */
|
||||
#define LPDTS_INT_EMA LPDTS_INTEN_EMAIE /*!< end of measurement asynchronous interrupt enable */
|
||||
#define LPDTS_INT_LTA LPDTS_INTEN_LTAIE /*!< low threshold asynchronous interrupt enable */
|
||||
#define LPDTS_INT_HTA LPDTS_INTEN_HTAIE /*!< high threshold asynchronous interrupt enable */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset the LPDTS registers */
|
||||
void lpdts_deinit(void);
|
||||
/* initialize the parameters of LPDTS struct with the default values */
|
||||
void lpdts_struct_para_init(lpdts_parameter_struct *init_struct);
|
||||
/* initialize the LPDTS */
|
||||
void lpdts_init(lpdts_parameter_struct *init_struct);
|
||||
|
||||
/* configuration functions */
|
||||
/* enable LPDTS temperature sensor */
|
||||
void lpdts_enable(void);
|
||||
/* disable LPDTS temperature sensor */
|
||||
void lpdts_disable(void);
|
||||
/* enable LPDTS software trigger */
|
||||
void lpdts_soft_trigger_enable(void);
|
||||
/* disable LPDTS software trigger */
|
||||
void lpdts_soft_trigger_disable(void);
|
||||
/* configure LPDTS high threshold value */
|
||||
void lpdts_high_threshold_set(uint16_t value);
|
||||
/* configure LPDTS low threshold value */
|
||||
void lpdts_low_threshold_set(uint16_t value);
|
||||
/* configure LPDTS reference clock selection */
|
||||
void lpdts_ref_clock_source_config(uint32_t source);
|
||||
/* get temperature from LPDTS */
|
||||
int32_t lpdts_temperature_get(void);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get LPDTS flag */
|
||||
FlagStatus lpdts_flag_get(uint32_t flag);
|
||||
/* enable LPDTS interrupt */
|
||||
void lpdts_interrupt_enable(uint32_t interrupt);
|
||||
/* disable LPDTS interrupt */
|
||||
void lpdts_interrupt_disable(uint32_t interrupt);
|
||||
/* get LPDTS interrupt flag */
|
||||
FlagStatus lpdts_interrupt_flag_get(uint32_t flag);
|
||||
/* clear the LPDTS interrupt flag */
|
||||
void lpdts_interrupt_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32H7XX_LPDTS_H */
|
||||
+236
File diff suppressed because it is too large
Load Diff
+480
File diff suppressed because it is too large
Load Diff
+200
File diff suppressed because it is too large
Load Diff
+802
File diff suppressed because it is too large
Load Diff
+125
@@ -0,0 +1,125 @@
|
||||
/*!
|
||||
\file gd32h7xx_ospim.h
|
||||
\brief definitions for the OSPIM
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_OSPIM_H
|
||||
#define GD32H7XX_OSPIM_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* OSPIM definitions */
|
||||
#define OSPIM OSPM_BASE
|
||||
|
||||
#define OSPIM_PCFG0 REG32(OSPIM + 0x00000004U) /*!< OSPI I/O manager port configuration register 0 */
|
||||
#define OSPIM_PCFG1 REG32(OSPIM + 0x00000008U) /*!< OSPI I/O manager port configuration register 1 */
|
||||
|
||||
/* OSPIM_PCFG */
|
||||
#define OSPIM_PCFG_SCKEN BIT(0) /*!< enable for sck of port n */
|
||||
#define OSPIM_PCFG_SRCPCK BIT(1) /*!< source selection for sck of port n */
|
||||
#define OSPIM_PCFG_NCSEN BIT(8) /*!< enable for csn of port n */
|
||||
#define OSPIM_PCFG_SRCPCS BIT(9) /*!< source selection for csn of port n */
|
||||
#define OSPIM_PCFG_POLEN BIT(16) /*!< enable for IO[3:0] of port n */
|
||||
#define OSPIM_PCFG_SRCPLIO BITS(17,18) /*!< source selection for IO[3:0] of port n */
|
||||
#define OSPIM_PCFG_POHEN BIT(24) /*!< enable for IO[7:4] of port n */
|
||||
#define OSPIM_PCFG_SRCPHIO BITS(25,26) /*!< source selection for IO[7:4] of port n */
|
||||
|
||||
/* constants definitions */
|
||||
/* ospi io manager configuration struct definitions */
|
||||
/* ospim register address */
|
||||
#define OSPIM_PCFG(regval) REG32(OSPIM + 0x4U * ((regval) + 1U)) /*!< the address of OSPI manager port configuration register */
|
||||
|
||||
/* ospim register address */
|
||||
#define OSPIM_PORT0 0x00U /*!< OSPI manager port 0 */
|
||||
#define OSPIM_PORT1 0x01U /*!< OSPI manager port 1 */
|
||||
|
||||
/* SCK of port */
|
||||
#define OSPIM_PORT_SCK_DISABLE 0x00000000U /*!< disable SCK of port */
|
||||
#define OSPIM_PORT_SCK_ENABLE OSPIM_PCFG_SCKEN /*!< disable SCK of port */
|
||||
|
||||
/* source selection for SCK of port */
|
||||
#define OSPIM_SCK_SOURCE_OSPI0_SCK 0x00000000U /*!< the source of SCK is OSPI0_SCK */
|
||||
#define OSPIM_SCK_SOURCE_OSPI1_SCK OSPIM_PCFG_SRCPCK /*!< the source of SCK is OSPI1_SCK */
|
||||
|
||||
/* CSN of port */
|
||||
#define OSPIM_PORT_CSN_DISABLE 0x00000000U /*!< disable CSN of port */
|
||||
#define OSPIM_PORT_CSN_ENABLE OSPIM_PCFG_NCSEN /*!< enable CSN of port */
|
||||
|
||||
/* source selection for CSN of port */
|
||||
#define OSPIM_CSN_SOURCE_OSPI0_CSN 0x00000000U /*!< the source of CSN is OSPI0_CSN */
|
||||
#define OSPIM_CSN_SOURCE_OSPI1_CSN OSPIM_PCFG_SRCPCS /*!< the source of CSN is OSPI1_CSN */
|
||||
|
||||
/* IO[3:0] of port */
|
||||
#define OSPIM_IO_LOW_DISABLE 0x00000000U /*!< disable IO[3:0] of port */
|
||||
#define OSPIM_IO_LOW_ENABLE OSPIM_PCFG_POLEN /*!< enable IO[3:0] of port */
|
||||
|
||||
/* source selection for IO[3:0] of port n */
|
||||
#define OSPIM_SRCPLIO(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
|
||||
#define OSPIM_SRCPLIO_OSPI0_IO_LOW OSPIM_SRCPLIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
|
||||
#define OSPIM_SRCPLIO_OSPI0_IO_HIGH OSPIM_SRCPLIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
|
||||
#define OSPIM_SRCPLIO_OSPI1_IO_LOW OSPIM_SRCPLIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
|
||||
#define OSPIM_SRCPLIO_OSPI1_IO_HIGH OSPIM_SRCPLIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
|
||||
|
||||
/* IO[7:4] of port */
|
||||
#define OSPIM_IO_HIGH_DISABLE 0x00000000U /*!< disable IO[7:4] of port */
|
||||
#define OSPIM_IO_HIGH_ENABLE OSPIM_PCFG_POHEN /*!< enable IO[7:4] of port */
|
||||
|
||||
/* source selection for IO[7:4] of port n */
|
||||
#define OSPIM_SRCPHIO(regval) (BITS(25,26) & ((uint32_t)(regval) << 25U))
|
||||
#define OSPIM_SRCPHIO_OSPI0_IO_LOW OSPIM_SRCPHIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
|
||||
#define OSPIM_SRCPHIO_OSPI0_IO_HIGH OSPIM_SRCPHIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
|
||||
#define OSPIM_SRCPHIO_OSPI1_IO_LOW OSPIM_SRCPHIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
|
||||
#define OSPIM_SRCPHIO_OSPI1_IO_HIGH OSPIM_SRCPHIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
|
||||
|
||||
/* function declarations */
|
||||
/* reset the OSPIM peripheral */
|
||||
void ospim_deinit(void);
|
||||
|
||||
/* ospim port configuration functions */
|
||||
/* configurate SCK for port */
|
||||
void ospim_port_sck_config(uint8_t port, uint32_t sckconfg);
|
||||
/* select source of SCK for port */
|
||||
void ospim_port_sck_source_select(uint8_t port, uint32_t sck_source);
|
||||
/* configurate CSN for port */
|
||||
void ospim_port_csn_config(uint8_t port, uint32_t csnconfig);
|
||||
/* select source of CSN for port */
|
||||
void ospim_port_csn_source_select(uint8_t port, uint32_t csn_source);
|
||||
/* configurate IO[3:0] for port */
|
||||
void ospim_port_io3_0_config(uint8_t port, uint32_t ioconfig);
|
||||
/* select source of IO[3:0] for port */
|
||||
void ospim_port_io3_0_source_select(uint8_t port, uint32_t io_source);
|
||||
/* configurate IO[7:4] for port */
|
||||
void ospim_port_io7_4_config(uint8_t port, uint32_t ioconfig);
|
||||
/* select source of IO[7:4] for port */
|
||||
void ospim_port_io7_4_source_select(uint8_t port, uint32_t io_source);
|
||||
|
||||
#endif /* GD32H7XX_OSPIM_H */
|
||||
+279
File diff suppressed because it is too large
Load Diff
+181
@@ -0,0 +1,181 @@
|
||||
/*!
|
||||
\file gd32h7xx_rameccmu.h
|
||||
\brief definitions for the RAMECCMU
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_RAMECCMU_H
|
||||
#define GD32H7XX_RAMECCMU_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* RAMECCMU definitions */
|
||||
#define RAMECCMU0 (RAMECCMU_BASE + 0x09FE6000U) /*!< RAMECCMU for Region 0 */
|
||||
#define RAMECCMU1 RAMECCMU_BASE /*!< RAMECCMU for Region 1 */
|
||||
|
||||
/* registers definitions */
|
||||
#define RAMECCMU_INT(rameccmux) REG32((rameccmux) + 0x00000000U) /*!< RAMECCMU global interruput register */
|
||||
|
||||
#define RAMECCMU_M0CTL(rameccmux) REG32((rameccmux) + 0x00000020U) /*!< RAMECCMU monitor 0 control register */
|
||||
#define RAMECCMU_M0STAT(rameccmux) REG32((rameccmux) + 0x00000024U) /*!< RAMECCMU monitor 0 status register */
|
||||
#define RAMECCMU_M0FADDR(rameccmux) REG32((rameccmux) + 0x00000028U) /*!< RAMECCMU monitor 0 ECC failing address register */
|
||||
#define RAMECCMU_M0FDL(rameccmux) REG32((rameccmux) + 0x0000002CU) /*!< RAMECCMU monitor 0 ECC failing data low register */
|
||||
#define RAMECCMU_M0FDH(rameccmux) REG32((rameccmux) + 0x00000030U) /*!< RAMECCMU monitor 0 ECC failing data high register */
|
||||
#define RAMECCMU_M0FECODE(rameccmux) REG32((rameccmux) + 0x00000034U) /*!< RAMECCMU monitor 0 failing ECC error code register */
|
||||
|
||||
#define RAMECCMU_M1CTL(rameccmux) REG32((rameccmux) + 0x00000040U) /*!< RAMECCMU monitor 1 control register */
|
||||
#define RAMECCMU_M1STAT(rameccmux) REG32((rameccmux) + 0x00000044U) /*!< RAMECCMU monitor 1 status register */
|
||||
#define RAMECCMU_M1FADDR(rameccmux) REG32((rameccmux) + 0x00000048U) /*!< RAMECCMU monitor 1 ECC failing address register */
|
||||
#define RAMECCMU_M1FDL(rameccmux) REG32((rameccmux) + 0x0000004CU) /*!< RAMECCMU monitor 1 ECC failing data low register */
|
||||
#define RAMECCMU_M1FDH(rameccmux) REG32((rameccmux) + 0x00000050U) /*!< RAMECCMU monitor 1 ECC failing data high register */
|
||||
#define RAMECCMU_M1FECODE(rameccmux) REG32((rameccmux) + 0x00000054U) /*!< RAMECCMU monitor 1 failing ECC error code register */
|
||||
|
||||
#define RAMECCMU_M2CTL(rameccmux) REG32((rameccmux) + 0x00000060U) /*!< RAMECCMU monitor 2 control register */
|
||||
#define RAMECCMU_M2STAT(rameccmux) REG32((rameccmux) + 0x00000064U) /*!< RAMECCMU monitor 2 status register */
|
||||
#define RAMECCMU_M2FADDR(rameccmux) REG32((rameccmux) + 0x00000068U) /*!< RAMECCMU monitor 2 ECC failing address register */
|
||||
#define RAMECCMU_M2FDL(rameccmux) REG32((rameccmux) + 0x0000006CU) /*!< RAMECCMU monitor 2 ECC failing data low register */
|
||||
#define RAMECCMU_M2FDH(rameccmux) REG32((rameccmux) + 0x00000070U) /*!< RAMECCMU monitor 2 ECC failing data high register */
|
||||
#define RAMECCMU_M2FECODE(rameccmux) REG32((rameccmux) + 0x00000074U) /*!< RAMECCMU monitor 2 failing ECC error code register */
|
||||
|
||||
#define RAMECCMU_M3CTL(rameccmux) REG32((rameccmux) + 0x00000080U) /*!< RAMECCMU monitor 3 control register */
|
||||
#define RAMECCMU_M3STAT(rameccmux) REG32((rameccmux) + 0x00000084U) /*!< RAMECCMU monitor 3 status register */
|
||||
#define RAMECCMU_M3FADDR(rameccmux) REG32((rameccmux) + 0x00000088U) /*!< RAMECCMU monitor 3 ECC failing address register */
|
||||
#define RAMECCMU_M3FDL(rameccmux) REG32((rameccmux) + 0x0000008CU) /*!< RAMECCMU monitor 3 ECC failing data low register */
|
||||
#define RAMECCMU_M3FDH(rameccmux) REG32((rameccmux) + 0x00000090U) /*!< RAMECCMU monitor 3 ECC failing data high register */
|
||||
#define RAMECCMU_M3FECODE(rameccmux) REG32((rameccmux) + 0x00000094U) /*!< RAMECCMU monitor 3 failing ECC error code register */
|
||||
|
||||
#define RAMECCMU_M4CTL(rameccmux) REG32((rameccmux) + 0x000000A0U) /*!< RAMECCMU monitor 4 control register */
|
||||
#define RAMECCMU_M4STAT(rameccmux) REG32((rameccmux) + 0x000000A4U) /*!< RAMECCMU monitor 4 status register */
|
||||
#define RAMECCMU_M4FADDR(rameccmux) REG32((rameccmux) + 0x000000A8U) /*!< RAMECCMU monitor 4 ECC failing address register */
|
||||
#define RAMECCMU_M4FDL(rameccmux) REG32((rameccmux) + 0x000000ACU) /*!< RAMECCMU monitor 4 ECC failing data low register */
|
||||
#define RAMECCMU_M4FDH(rameccmux) REG32((rameccmux) + 0x000000B0U) /*!< RAMECCMU monitor 4 ECC failing data high register */
|
||||
#define RAMECCMU_M4FECODE(rameccmux) REG32((rameccmux) + 0x000000B4U) /*!< RAMECCMU monitor 4 failing ECC error code register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RAMECCMU_INT */
|
||||
#define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */
|
||||
#define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */
|
||||
#define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */
|
||||
#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
|
||||
|
||||
/* RAMECCMU_MxCTL */
|
||||
#define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */
|
||||
#define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */
|
||||
#define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */
|
||||
#define RAMECCMU_MXCTL_ECCERRLATEN BIT(5) /*!< ECC error latching enable */
|
||||
|
||||
/* RAMECCMU_MxSTAT */
|
||||
#define RAMECCMU_MXSTAT_ECCSERRDCF BIT(0) /*!< ECC single error detected and corrected flag */
|
||||
#define RAMECCMU_MXSTAT_ECCDERRDF BIT(1) /*!< ECC double error detected flag */
|
||||
#define RAMECCMU_MXSTAT_ECCDERRBWDF BIT(2) /*!< ECC double error on byte write detected flag */
|
||||
|
||||
/* RAMECCMU_MxFADDR */
|
||||
#define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */
|
||||
|
||||
/* RAMECCMU_MxFDL */
|
||||
#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
|
||||
|
||||
/* RAMECCMU_MxFDH */
|
||||
#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
|
||||
|
||||
/* RAMECCMU_MxFECODE */
|
||||
#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
|
||||
|
||||
/* constants definitions */
|
||||
/* RAMECCMU monitor select */
|
||||
typedef enum
|
||||
{
|
||||
RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */
|
||||
RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */
|
||||
RAMECCMU0_MONITOR2 = 0x02U, /*!< RAMECCMU0 monitor 2 */
|
||||
RAMECCMU0_MONITOR3 = 0x03U, /*!< RAMECCMU0 monitor 3 */
|
||||
RAMECCMU0_MONITOR4 = 0x04U, /*!< RAMECCMU0 monitor 4 */
|
||||
RAMECCMU1_MONITOR0 = 0x10U, /*!< RAMECCMU1 monitor 0 */
|
||||
RAMECCMU1_MONITOR1 = 0x11U, /*!< RAMECCMU1 monitor 1 */
|
||||
RAMECCMU1_MONITOR2 = 0x12U /*!< RAMECCMU1 monitor 2 */
|
||||
} rameccmu_monitor_enum;
|
||||
|
||||
/* RAMECCMUx monitor register address */
|
||||
#define RAMECCMU_MXCTL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x20U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor control register */
|
||||
#define RAMECCMU_MXSTAT(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x24U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor status register */
|
||||
#define RAMECCMU_MXFADDR(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x28U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing address register */
|
||||
#define RAMECCMU_MXFDL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x2CU + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data low register */
|
||||
#define RAMECCMU_MXFDH(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x30U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data high register */
|
||||
#define RAMECCMU_MXFECODE(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x34U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor failing ECC error code register */
|
||||
|
||||
#define RAMECCMU_INT_ECC_GLOBAL_ERROR BIT(0) /*!< ECC global error interrupt */
|
||||
#define RAMECCMU_INT_ECC_SINGLE_ERROR BIT(1) /*!< ECC single error interrupt */
|
||||
#define RAMECCMU_INT_ECC_DOUBLE_ERROR BIT(2) /*!< ECC double error interrupt */
|
||||
#define RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE BIT(3) /*!< ECC double error on byte write interrupt */
|
||||
#define RAMECCMU_INT_ECC_ERROR_LATCHING BIT(4) /*!< ECC error latching */
|
||||
|
||||
#define RAMECCMU_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
|
||||
#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
|
||||
#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
|
||||
|
||||
#define RAMECCMU_INT_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
|
||||
#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
|
||||
#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
/* deinit RAMECCMU unit */
|
||||
void rameccmu_deinit(uint32_t rameccmu_periph);
|
||||
|
||||
/* RAMECCMU monitor ECC functions */
|
||||
/* get RAMECCMU monitor ECC failing address */
|
||||
uint32_t rameccmu_monitor_failing_address_get(rameccmu_monitor_enum rameccmu_monitor);
|
||||
/* get RAMECCMU monitor ECC failing data low 32 bits */
|
||||
uint32_t rameccmu_monitor_failing_data_low_bits_get(rameccmu_monitor_enum rameccmu_monitor);
|
||||
/* get RAMECCMU monitor ECC failing data high 32 bits */
|
||||
uint32_t rameccmu_monitor_failing_data_high_bits_get(rameccmu_monitor_enum rameccmu_monitor);
|
||||
/* get RAMECCMU monitor failing ECC error code */
|
||||
uint32_t rameccmu_monitor_failing_ecc_error_code_get(rameccmu_monitor_enum rameccmu_monitor);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable RAMECCMU global ECC interruput */
|
||||
void rameccmu_global_interrupt_enable(uint32_t rameccmu_periph, uint32_t interrupt);
|
||||
/* disable RAMECCMU global ECC interruput */
|
||||
void rameccmu_global_interrupt_disable(uint32_t rameccmu_periph, uint32_t interrupt);
|
||||
/* enable RAMECCMU monitor ECC error interruput */
|
||||
void rameccmu_monitor_interrupt_enable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
|
||||
/* disable RAMECCMU monitor ECC error interruput */
|
||||
void rameccmu_monitor_interrupt_disable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
|
||||
/* get RAMECCMU monitor ECC error flag */
|
||||
FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
|
||||
/* clear RAMECCMU monitor ECC error flag */
|
||||
void rameccmu_monitor_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
|
||||
/* get RAMECCMU monitor ECC interrupt error flag */
|
||||
FlagStatus rameccmu_monitor_interrupt_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
|
||||
/* clear RAMECCMU monitor interrupt ECC error flag */
|
||||
void rameccmu_monitor_interrupt_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
|
||||
|
||||
#endif /* GD32H7XX_RAMECCMU_H */
|
||||
+2097
File diff suppressed because it is too large
Load Diff
+326
File diff suppressed because it is too large
Load Diff
+729
File diff suppressed because it is too large
Load Diff
+166
@@ -0,0 +1,166 @@
|
||||
/*!
|
||||
\file gd32h7xx_rtdec.h
|
||||
\brief definitions for the RTDEC
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_RTDEC_H
|
||||
#define GD32H7XX_RTDEC_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* RTDEC definitions */
|
||||
#define RTDEC0 RTDEC_BASE /*!< RTDEC0 bsae address */
|
||||
#define RTDEC1 (RTDEC_BASE + 0x00000400U) /*!< RTDEC1 bsae address */
|
||||
#define RTDEC_AREA0 ((uint8_t)0x00U) /*!< RTDEC area0 */
|
||||
#define RTDEC_AREA1 ((uint8_t)0x01U) /*!< RTDEC area1 */
|
||||
#define RTDEC_AREA2 ((uint8_t)0x02U) /*!< RTDEC area2 */
|
||||
#define RTDEC_AREA3 ((uint8_t)0x03U) /*!< RTDEC area3 */
|
||||
#define RTDEC_ARE(rtdecx, rtdec_areax) ((rtdecx) + 0x00000030U * (rtdec_areax))
|
||||
|
||||
/* registers definitions */
|
||||
#define RTDEC_ARE_CFG(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000020U) /*!< area configuration register */
|
||||
#define RTDEC_ARE_SADDR(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000024U) /*!< area start address register */
|
||||
#define RTDEC_ARE_EADDR(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000028U) /*!< area end address register */
|
||||
#define RTDEC_ARE_NONCE0(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x0000002CU) /*!< area random number register 0 */
|
||||
#define RTDEC_ARE_NONCE1(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000030U) /*!< area random number register 1 */
|
||||
#define RTDEC_ARE_KEY0(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000034U) /*!< area key register 0 */
|
||||
#define RTDEC_ARE_KEY1(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000038U) /*!< area key register 1 */
|
||||
#define RTDEC_ARE_KEY2(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x0000003CU) /*!< area key register 2 */
|
||||
#define RTDEC_ARE_KEY3(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000040U) /*!< area key register 3 */
|
||||
#define RTDEC_INTF(rtdecx) REG32((rtdecx) + 0x00000300U) /*!< interrupt flag register */
|
||||
#define RTDEC_INTC(rtdecx) REG32((rtdecx) + 0x00000304U) /*!< interrupt flag clear register */
|
||||
#define RTDEC_INTEN(rtdecx) REG32((rtdecx) + 0x00000308U) /*!< interrupt enable register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTDEC_AREx_CFG */
|
||||
#define RTDEC_ARE_EN BIT(0) /*!< area real-time decryption enable bit */
|
||||
#define RTDEC_ARE_CFG_LK BIT(1) /*!< area configure lock bit */
|
||||
#define RTDEC_ARE_K_LK BIT(2) /*!< area key lock bit */
|
||||
#define RTDEC_MODE BITS(4, 5) /*!< RTDEC mode bits */
|
||||
#define RTDEC_ARE_K_CRC BITS(8, 15) /*!< 8-bit CRC of area key bits */
|
||||
#define RTDEC_ARE_FMVER BITS(16, 31) /*!< area firmware version bits */
|
||||
|
||||
/* RTDEC_AREx_SADDR */
|
||||
#define RTDEC_ARE_SADDR_SADDR BITS(0, 31) /*!< area start address bits */
|
||||
|
||||
/* RTDEC_AREx_EADDR */
|
||||
#define RTDEC_ARE_EADDR_EADDR BITS(0, 31) /*!< area end address bits */
|
||||
|
||||
/* RTDEC_AREx_NONCE */
|
||||
#define RTDEC_ARE_NONCE_NONCE BITS(0, 31) /*!< area random number address bits */
|
||||
|
||||
/* RTDEC_AREx_KEY */
|
||||
#define RTDEC_ARE_KEY_KEY BITS(0, 31) /*!< area key bits */
|
||||
|
||||
/* RTDEC_INTF */
|
||||
#define RTDEC_SECEF BIT(0) /*!< security error interrupt flag */
|
||||
#define RTDEC_ECONEF BIT(1) /*!< execute-only or execute-never error interrupt flag */
|
||||
#define RTDEC_KEF BIT(2) /*!< key error interrupt flag */
|
||||
|
||||
/* RTDEC_INTEN */
|
||||
#define RTDEC_SECEIE BIT(0) /*!< enable bit for security error interrupt */
|
||||
#define RTDEC_ECONEIE BIT(1) /*!< enable bit for execute-only or execute-never error interrupt */
|
||||
#define RTDEC_KEIE BIT(2) /*!< enable bit for key error interrupt */
|
||||
|
||||
/* constants definitions */
|
||||
/* RTDEC modes definitions */
|
||||
#define RTDEC_MODE_SEL(regval) (RTDEC_MODE & ((uint32_t)(regval) << 4U))
|
||||
#define RTDEC_MODE_CODE_ACCESS RTDEC_MODE_SEL(0) /*!< only code accesses are decrypted */
|
||||
#define RTDEC_MODE_DATA_ACCESS RTDEC_MODE_SEL(1) /*!< only data accesses are decrypted */
|
||||
#define RTDEC_MODE_BOTH_ACCESS RTDEC_MODE_SEL(2) /*!< all read accesses are decrypted (code or data) */
|
||||
|
||||
/* RTDEC interrupt flag definitions */
|
||||
#define RTDEC_INT_FLAG_SEC_ERROR RTDEC_SECEF /*!< bit constant of security error interrupt flag */
|
||||
#define RTDEC_INT_FLAG_MODE_ERROR RTDEC_ECONEF /*!< bit constant of execute-only or execute-never error interrupt flag */
|
||||
#define RTDEC_INT_FLAG_KEY_ERROR RTDEC_KEF /*!< bit constant of key error interrupt flag */
|
||||
|
||||
/* RTDEC interrupt enable definitions */
|
||||
#define RTDEC_INT_SEC RTDEC_SECEIE /*!< enable bit for security error interrupt */
|
||||
#define RTDEC_INT_MODE RTDEC_ECONEIE /*!< enable bit for execute-only or execute-never error interrupt */
|
||||
#define RTDEC_INT_KEY RTDEC_KEIE /*!< enable bit for key error interrupt */
|
||||
|
||||
/* RTDEC flag definitions */
|
||||
#define RTDEC_FLAG_SEC_ERROR RTDEC_SECEF /*!< bit constant of security error flag */
|
||||
#define RTDEC_FLAG_MODE_ERROR RTDEC_ECONEF /*!< bit constant of execute-only or execute-never error flag */
|
||||
#define RTDEC_FLAG_KEY_ERROR RTDEC_KEF /*!< bit constant of key error flag */
|
||||
|
||||
/* structure for rtdec initialization parameter */
|
||||
typedef struct {
|
||||
uint8_t access_mode; /*!< area access mode */
|
||||
uint8_t key_crc; /*!< key CRC value */
|
||||
uint16_t fw_version; /*!< area firmware version */
|
||||
uint32_t *key; /*!< area key bits */
|
||||
uint32_t *nonce; /*!< area nonce bits */
|
||||
uint32_t start_addr; /*!< area start address */
|
||||
uint32_t end_addr; /*!< area end address */
|
||||
} rtdec_parameter_struct;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset RTDEC */
|
||||
void rtdec_deinit(uint32_t rtdec_periph);
|
||||
/* initialize the parameters of RTDEC struct with default values */
|
||||
void rtdec_struct_para_init(rtdec_parameter_struct* rtdec_struct);
|
||||
/* initialize RTDEC */
|
||||
ErrStatus rtdec_init(uint32_t rtdec_periph, uint32_t rtdec_area, rtdec_parameter_struct *rtdec_struct);
|
||||
/* configure RTDEC area data attribute */
|
||||
void rtdec_config(uint32_t rtdec_periph, uint32_t rtdec_area, uint8_t access_mode, uint16_t firmware_version);
|
||||
/* configure RTDEC key or register lock */
|
||||
void rtdec_lock(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t lock_type);
|
||||
/* initialize RTDEC area address */
|
||||
void rtdec_addr_init(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t saddr, uint32_t eaddr);
|
||||
/* initialize RTDEC nonce, nonce follows little endian format */
|
||||
void rtdec_nonce_init(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t *nonce);
|
||||
/* initialize RTDEC key, key follows little endian format */
|
||||
void rtdec_key_init(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t *key);
|
||||
/* get CRC value of RTDEC key data */
|
||||
uint8_t rtdec_key_crc_get(uint32_t rtdec_periph, uint32_t rtdec_area);
|
||||
/* enable RTDEC area */
|
||||
void rtdec_enable(uint32_t rtdec_periph, uint32_t rtdec_area);
|
||||
/* disable RTDEC area */
|
||||
void rtdec_disable(uint32_t rtdec_periph, uint32_t rtdec_area);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* get RTDEC error flag */
|
||||
FlagStatus rtdec_flag_get(uint32_t rtdec_periph, uint32_t flag);
|
||||
/* clear RTDEC error flag */
|
||||
void rtdec_flag_clear(uint32_t rtdec_periph, uint32_t flag);
|
||||
/* enable RTDEC interrupt */
|
||||
void rtdec_interrupt_enable(uint32_t rtdec_periph, uint32_t interrupt);
|
||||
/* disable RTDEC interrupt */
|
||||
void rtdec_interrupt_disable(uint32_t rtdec_periph, uint32_t interrupt);
|
||||
/* get RTDEC interrupt flag */
|
||||
FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag);
|
||||
/* clear RTDEC interrupt flag */
|
||||
void rtdec_interrupt_flag_clear(uint32_t rtdec_periph, uint32_t int_flag);
|
||||
|
||||
#endif /* GD32H7XX_RTDEC_H */
|
||||
+541
File diff suppressed because it is too large
Load Diff
+534
File diff suppressed because it is too large
Load Diff
+693
File diff suppressed because it is too large
Load Diff
+633
File diff suppressed because it is too large
Load Diff
+1265
File diff suppressed because it is too large
Load Diff
+374
File diff suppressed because it is too large
Load Diff
+177
@@ -0,0 +1,177 @@
|
||||
/*!
|
||||
\file gd32h7xx_tmu.h
|
||||
\brief definitions for the TMU
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_TMU_H
|
||||
#define GD32H7XX_TMU_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* TMU definitions */
|
||||
#define TMU TMU_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define TMU_CS REG32(TMU + 0x00000000U) /*!< TMU control and status register */
|
||||
#define TMU_IDATA REG32(TMU + 0x00000004U) /*!< TMU input data register */
|
||||
#define TMU_ODATA REG32(TMU + 0x00000008U) /*!< TMU output data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* TMU_CS */
|
||||
#define TMU_CS_MODE BITS(0,3) /*!< TMU operation mode selection */
|
||||
#define TMU_CS_ITRTNUM BITS(4,7) /*!< number of iterations selection */
|
||||
#define TMU_CS_FACTOR BITS(8,10) /*!< scaling factor */
|
||||
#define TMU_CS_RIE BIT(16) /*!< read TMU_ODATA interrupt enable */
|
||||
#define TMU_CS_RDEN BIT(17) /*!< read TMU_ODATA DMA request enable */
|
||||
#define TMU_CS_WDEN BIT(18) /*!< write TMU_IDATA DMA request enable */
|
||||
#define TMU_CS_ONUM BIT(19) /*!< times the TMU_ODATA needs to be read */
|
||||
#define TMU_CS_INUM BIT(20) /*!< times the TMU_IDATA needs to be write */
|
||||
#define TMU_CS_OWIDTH BIT(21) /*!< width of output data */
|
||||
#define TMU_CS_IWIDTH BIT(22) /*!< width of input data */
|
||||
#define TMU_CS_ENDF BIT(31) /*!< end of TMU operation flag */
|
||||
|
||||
/* TMU_IDATA */
|
||||
#define TMU_IDATA_IDATA BITS(0,31) /*!< the input data of TMU operation */
|
||||
|
||||
/* TMU_ODATA */
|
||||
#define TMU_ODATA_ODATA BITS(0,31) /*!< the output data of TMU operation */
|
||||
|
||||
/* constants definitions */
|
||||
/* TMU init parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t mode; /*!< mode of TMU operation */
|
||||
uint32_t iterations_number; /*!< number of iterations selection */
|
||||
uint32_t scale; /*!< scaling factor */
|
||||
uint32_t dma_read; /*!< DMA request to read TMU_ODATA */
|
||||
uint32_t dma_write; /*!< DMA request to write TMU_IDATA */
|
||||
uint32_t read_times; /*!< times the TMU_ODATA needs to be read */
|
||||
uint32_t write_times; /*!< times the TMU_IDATA needs to be write */
|
||||
uint32_t output_width; /*!< width of output data */
|
||||
uint32_t input_width; /*!< width of input data */
|
||||
}tmu_parameter_struct;
|
||||
|
||||
/* TMU mode definitions */
|
||||
#define TMU_MODE(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define TMU_MODE_COS TMU_MODE(0) /*!< mode0: m*cos(��) */
|
||||
#define TMU_MODE_SIN TMU_MODE(1) /*!< mode1: m*sin(��) */
|
||||
#define TMU_MODE_ATAN2 TMU_MODE(2) /*!< mode2: atan2(y,x) */
|
||||
#define TMU_MODE_MODULUS TMU_MODE(3) /*!< mode3: sqrt(x^2+y^2) */
|
||||
#define TMU_MODE_ATAN TMU_MODE(4) /*!< mode4: atan(x) */
|
||||
#define TMU_MODE_COSH TMU_MODE(5) /*!< mode5: cosh(x) */
|
||||
#define TMU_MODE_SINH TMU_MODE(6) /*!< mode6: sinh(x) */
|
||||
#define TMU_MODE_ATANH TMU_MODE(7) /*!< mode7: atanh(x) */
|
||||
#define TMU_MODE_LN TMU_MODE(8) /*!< mode8: ln(x) */
|
||||
#define TMU_MODE_SQRT TMU_MODE(9) /*!< mode9: sqrt(x) */
|
||||
|
||||
/* TMU number of iterations definitions */
|
||||
#define ITERATIONS(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define TMU_ITERATION_STEPS_4 ITERATIONS(1) /*!< 4 iteration steps */
|
||||
#define TMU_ITERATION_STEPS_8 ITERATIONS(2) /*!< 8 iteration steps */
|
||||
#define TMU_ITERATION_STEPS_12 ITERATIONS(3) /*!< 12 iteration steps */
|
||||
#define TMU_ITERATION_STEPS_16 ITERATIONS(4) /*!< 16 iteration steps */
|
||||
#define TMU_ITERATION_STEPS_20 ITERATIONS(5) /*!< 20 iteration steps */
|
||||
#define TMU_ITERATION_STEPS_24 ITERATIONS(6) /*!< 24 iteration steps */
|
||||
|
||||
/* TMU scaling factor definitions */
|
||||
#define SCALE(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
|
||||
#define TMU_SCALING_FACTOR_1 SCALE(0) /*!< scaling factor = 1 */
|
||||
#define TMU_SCALING_FACTOR_2 SCALE(1) /*!< scaling factor = 2 */
|
||||
#define TMU_SCALING_FACTOR_4 SCALE(2) /*!< scaling factor = 4 */
|
||||
#define TMU_SCALING_FACTOR_8 SCALE(3) /*!< scaling factor = 8 */
|
||||
#define TMU_SCALING_FACTOR_16 SCALE(4) /*!< scaling factor = 16 */
|
||||
#define TMU_SCALING_FACTOR_32 SCALE(5) /*!< scaling factor = 32 */
|
||||
#define TMU_SCALING_FACTOR_64 SCALE(6) /*!< scaling factor = 64 */
|
||||
#define TMU_SCALING_FACTOR_128 SCALE(7) /*!< scaling factor = 128 */
|
||||
|
||||
/* TMU DMA read enable definitions */
|
||||
#define TMU_READ_DMA_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA request to read TMU_ODATA */
|
||||
#define TMU_READ_DMA_ENABLE TMU_CS_RDEN /*!< enable DMA request to read TMU_ODATA */
|
||||
|
||||
/* TMU DMA write enable definitions */
|
||||
#define TMU_WRITE_DMA_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA request to write TMU_IDATA */
|
||||
#define TMU_WRITE_DMA_ENABLE TMU_CS_WDEN /*!< enable DMA request to write TMU_IDATA */
|
||||
|
||||
/* TMU_ODATA read times definitions */
|
||||
#define TMU_READ_TIMES_1 ((uint32_t)0x00000000U) /*!< one 32-bit read operation */
|
||||
#define TMU_READ_TIMES_2 TMU_CS_ONUM /*!< two 32-bit read operation */
|
||||
|
||||
/* TMU_IDATA write times definitions */
|
||||
#define TMU_WRITE_TIMES_1 ((uint32_t)0x00000000U) /*!< one 32-bit write operation */
|
||||
#define TMU_WRITE_TIMES_2 TMU_CS_INUM /*!< two 32-bit write operation */
|
||||
|
||||
/* TMU output data width definitions */
|
||||
#define TMU_OUTPUT_WIDTH_32 ((uint32_t)0x00000000U) /*!< TMU_ODATA contains the output data in q1.31 format */
|
||||
#define TMU_OUTPUT_WIDTH_16 TMU_CS_OWIDTH /*!< TMU_ODATA contains the output data in q1.15 format */
|
||||
|
||||
/* TMU input data width definitions */
|
||||
#define TMU_INPUT_WIDTH_32 ((uint32_t)0x00000000U) /*!< TMU_IDATA contains the input data in q1.31 format */
|
||||
#define TMU_INPUT_WIDTH_16 TMU_CS_IWIDTH /*!< TMU_IDATA contains the input data in q1.15 format */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset the TMU registers */
|
||||
void tmu_deinit(void);
|
||||
/* initialize the parameters of TMU struct with the default values */
|
||||
void tmu_struct_para_init(tmu_parameter_struct* init_struct);
|
||||
/* initialize TMU */
|
||||
void tmu_init(tmu_parameter_struct* init_struct);
|
||||
|
||||
/* interrupt and dma configuration */
|
||||
/* enable TMU read interrupt */
|
||||
void tmu_read_interrupt_enable(void);
|
||||
/* disable TMU read interrupt */
|
||||
void tmu_read_interrupt_disable(void);
|
||||
/* enable TMU DMA read request */
|
||||
void tmu_dma_read_enable(void);
|
||||
/* disable TMU DMA read request */
|
||||
void tmu_dma_read_disable(void);
|
||||
/* enable TMU DMA write request */
|
||||
void tmu_dma_write_enable(void);
|
||||
/* disable TMU DMA write request */
|
||||
void tmu_dma_write_disable(void);
|
||||
|
||||
/* TMU data write and read */
|
||||
/* write one data in q1.31 format */
|
||||
void tmu_one_q31_write(uint32_t data);
|
||||
/* write two data in q1.31 format */
|
||||
void tmu_two_q31_write(uint32_t data1, uint32_t data2);
|
||||
/* write two data in q1.15 format */
|
||||
void tmu_two_q15_write(uint16_t data1, uint16_t data2);
|
||||
/* read one data in q1.31 format */
|
||||
void tmu_one_q31_read(uint32_t* p);
|
||||
/* read two data in q1.31 format */
|
||||
void tmu_two_q31_read(uint32_t* p1, uint32_t* p2);
|
||||
/* read two data in q1.15 format */
|
||||
void tmu_two_q15_read(uint16_t* p1, uint16_t* p2);
|
||||
|
||||
#endif /* GD32H7XX_TMU_H */
|
||||
+338
File diff suppressed because it is too large
Load Diff
+218
File diff suppressed because it is too large
Load Diff
+683
File diff suppressed because it is too large
Load Diff
+90
@@ -0,0 +1,90 @@
|
||||
/*!
|
||||
\file gd32h7xx_vref.h
|
||||
\brief definitions for the VREF
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_VREF_H
|
||||
#define GD32H7XX_VREF_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* VREF definitions */
|
||||
#define VREF VREF_BASE /*!< VREF base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define VREF_CS REG32(VREF + 0x00000000U) /*!< VREF Control and status register */
|
||||
#define VREF_CALIB REG32(VREF + 0x00000004U) /*!< VREF Calibration register */
|
||||
|
||||
/* bits definitions */
|
||||
/* VREF_CS */
|
||||
#define VREF_CS_VREFEN BIT(0) /*!< VREF enable */
|
||||
#define VREF_CS_HIPM BIT(1) /*!< High impedance mode */
|
||||
#define VREF_CS_VREFRDY BIT(3) /*!< VREF ready */
|
||||
#define VREF_CS_VREFS BITS(4,5) /*!< VREF voltage reference select */
|
||||
|
||||
/* VREF_CALIB */
|
||||
#define VREF_CALIB_VREFCAL BITS(0,5) /*!< VREF calibration */
|
||||
|
||||
/* constants definitions */
|
||||
/* VREF bit devinitions */
|
||||
#define VREF_EN VREF_CS_VREFEN /*!< VREF enable */
|
||||
#define VREF_HIGH_IMPEDANCE_MODE VREF_CS_HIPM /*!< High impedance mode */
|
||||
#define VREF_RDY VREF_CS_VREFRDY /*!< VREF ready */
|
||||
|
||||
/* VREF voltage reference select */
|
||||
#define CS_VREFS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U))
|
||||
#define VREF_VOLTAGE_SEL_2_5V CS_VREFS(0) /*!< VREF voltage reference select 2.5 V */
|
||||
#define VREF_VOLTAGE_SEL_2_048V CS_VREFS(1) /*!< VREF voltage reference select 2.048 V */
|
||||
#define VREF_VOLTAGE_SEL_1_8V CS_VREFS(2) /*!< VREF voltage reference select 1.8 V */
|
||||
#define VREF_VOLTAGE_SEL_1_5V CS_VREFS(3) /*!< VREF voltage reference select 1.5 V */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the VREF */
|
||||
void vref_deinit(void);
|
||||
/* enable VREF */
|
||||
void vref_enable(void);
|
||||
/* disable VREF */
|
||||
void vref_disable(void);
|
||||
/* enable VREF high impendance mode */
|
||||
void vref_high_impedance_mode_enable(void);
|
||||
/* disable VREF high impendance mode */
|
||||
void vref_high_impedance_mode_disable(void);
|
||||
/* get the status of VREF */
|
||||
FlagStatus vref_status_get(void);
|
||||
/* select the VREF voltage reference */
|
||||
void vref_voltage_select(uint32_t vref_voltage);
|
||||
/* set the calibration value of VREF */
|
||||
void vref_calib_value_set(uint8_t value);
|
||||
/* get the calibration value of VREF */
|
||||
uint8_t vref_calib_value_get(void);
|
||||
|
||||
#endif /* GD32H7XX_VREF_H */
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
/*!
|
||||
\file gd32h7xx_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32H7XX_WWDGT_H
|
||||
#define GD32H7XX_WWDGT_H
|
||||
|
||||
#include "gd32h7xx.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK3/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK3/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK3/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK3/4096)/8 */
|
||||
|
||||
/* function declarations */
|
||||
/* reset the WWDGT configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the WWDGT counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the WWDGT counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
|
||||
#endif /* GD32H7XX_WWDGT_H */
|
||||
+1300
File diff suppressed because it is too large
Load Diff
+1910
File diff suppressed because it is too large
Load Diff
+733
File diff suppressed because it is too large
Load Diff
+917
File diff suppressed because it is too large
Load Diff
+183
@@ -0,0 +1,183 @@
|
||||
/*!
|
||||
\file gd32h7xx_cau_des.c
|
||||
\brief CAU DES driver
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32h7xx_cau.h"
|
||||
|
||||
#define DESBUSY_TIMEOUT ((uint32_t)0x00010000U)
|
||||
|
||||
/* DES calculate process */
|
||||
static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *output);
|
||||
|
||||
/*!
|
||||
\brief encrypt and decrypt using DES in ECB mode
|
||||
\param[in] cau_parameter: pointer to the input structure
|
||||
alg_dir: algorithm directory
|
||||
CAU_ENCRYPT, CAU_DECRYPT
|
||||
key: key, 8 bytes
|
||||
input: input data
|
||||
in_length: input data length in bytes, must be a multiple of 8 bytes
|
||||
\param[out] output: pointer to the output buffer
|
||||
\retval ErrStatus: SUCCESS or ERROR
|
||||
*/
|
||||
ErrStatus cau_des_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
|
||||
{
|
||||
ErrStatus ret = ERROR;
|
||||
cau_key_parameter_struct key_initpara;
|
||||
uint32_t keyaddr = (uint32_t)(cau_parameter->key);
|
||||
uint32_t inputaddr = (uint32_t)(cau_parameter->input);
|
||||
uint32_t outputaddr = (uint32_t)output;
|
||||
|
||||
/* key structure initialization */
|
||||
cau_key_struct_para_init(&key_initpara);
|
||||
/* initialize the CAU peripheral */
|
||||
cau_init(cau_parameter->alg_dir, CAU_MODE_DES_ECB, CAU_SWAPPING_8BIT);
|
||||
|
||||
/* key initialisation */
|
||||
key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr));
|
||||
cau_key_init(&key_initpara);
|
||||
|
||||
/* flush the IN and OUT FIFOs */
|
||||
cau_fifo_flush();
|
||||
/* enable the CAU peripheral */
|
||||
cau_enable();
|
||||
/* DES calculate process */
|
||||
ret = cau_des_calculate((uint8_t *)inputaddr, cau_parameter->in_length, (uint8_t *)outputaddr);
|
||||
/* disable the CAU peripheral */
|
||||
cau_disable();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief encrypt and decrypt using DES in CBC mode
|
||||
\param[in] cau_parameter: pointer to the input structure
|
||||
alg_dir: algorithm directory
|
||||
CAU_ENCRYPT, CAU_DECRYPT
|
||||
key: key, 8 bytes
|
||||
iv: initialization vector, 8 bytes
|
||||
input: input data
|
||||
in_length: input data length in bytes, must be a multiple of 8 bytes
|
||||
\param[out] output: pointer to the output structure
|
||||
\retval ErrStatus: SUCCESS or ERROR
|
||||
*/
|
||||
ErrStatus cau_des_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
|
||||
{
|
||||
ErrStatus ret = ERROR;
|
||||
cau_key_parameter_struct key_initpara;
|
||||
cau_iv_parameter_struct iv_initpara;
|
||||
uint32_t keyaddr = (uint32_t)(cau_parameter->key);
|
||||
uint32_t inputaddr = (uint32_t)(cau_parameter->input);
|
||||
uint32_t outputaddr = (uint32_t)output;
|
||||
uint32_t ivaddr = (uint32_t)(cau_parameter->iv);
|
||||
|
||||
/* key structure initialization */
|
||||
cau_key_struct_para_init(&key_initpara);
|
||||
/* initialize the CAU peripheral */
|
||||
cau_init(cau_parameter->alg_dir, CAU_MODE_DES_CBC, CAU_SWAPPING_8BIT);
|
||||
|
||||
/* key initialisation */
|
||||
key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr));
|
||||
cau_key_init(&key_initpara);
|
||||
|
||||
/* vectors initialization */
|
||||
iv_initpara.iv_0_high = __REV(*(uint32_t *)(ivaddr));
|
||||
ivaddr += 4U;
|
||||
iv_initpara.iv_0_low = __REV(*(uint32_t *)(ivaddr));
|
||||
cau_iv_init(&iv_initpara);
|
||||
|
||||
/* flush the IN and OUT FIFOs */
|
||||
cau_fifo_flush();
|
||||
|
||||
/* enable the CAU peripheral */
|
||||
cau_enable();
|
||||
/* DES calculate process */
|
||||
ret = cau_des_calculate((uint8_t *)inputaddr, cau_parameter->in_length, (uint8_t *)outputaddr);
|
||||
/* disable the CAU peripheral */
|
||||
cau_disable();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief DES calculate process
|
||||
\param[in] input: pointer to the input buffer
|
||||
\param[in] in_length: length of the input buffer in bytes, must be a multiple of 8 bytes
|
||||
\param[in] output: pointer to the returned buffer
|
||||
\param[out] none
|
||||
\retval ErrStatus: SUCCESS or ERROR
|
||||
*/
|
||||
static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *output)
|
||||
{
|
||||
uint32_t inputaddr = (uint32_t)input;
|
||||
uint32_t outputaddr = (uint32_t)output;
|
||||
uint32_t i = 0U;
|
||||
__IO uint32_t counter = 0U;
|
||||
uint32_t busystatus = 0U;
|
||||
|
||||
/* the clock is not enabled or there is no embedded CAU peripheral */
|
||||
if(DISABLE == cau_enable_state_get()) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
for(i = 0U; i < in_length; i += 8U) {
|
||||
/* write data to the IN FIFO */
|
||||
cau_data_write(*(uint32_t *)(inputaddr));
|
||||
inputaddr += 4U;
|
||||
cau_data_write(*(uint32_t *)(inputaddr));
|
||||
inputaddr += 4U;
|
||||
|
||||
/* wait until the complete message has been processed */
|
||||
counter = 0U;
|
||||
do {
|
||||
busystatus = cau_flag_get(CAU_FLAG_BUSY);
|
||||
counter++;
|
||||
} while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus));
|
||||
|
||||
if(RESET != busystatus) {
|
||||
return ERROR;
|
||||
} else {
|
||||
/* read the output block from the output FIFO */
|
||||
*(uint32_t *)(outputaddr) = cau_data_read();
|
||||
outputaddr += 4U;
|
||||
*(uint32_t *)(outputaddr) = cau_data_read();
|
||||
outputaddr += 4U;
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+198
@@ -0,0 +1,198 @@
|
||||
/*!
|
||||
\file gd32h7xx_cau_tdes.c
|
||||
\brief CAU TDES driver
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32h7xx_cau.h"
|
||||
|
||||
#define TDESBSY_TIMEOUT ((uint32_t)0x00010000U)
|
||||
|
||||
/* TDES calculate process */
|
||||
static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t *output);
|
||||
|
||||
/*!
|
||||
\brief encrypt and decrypt using TDES in ECB mode
|
||||
\param[in] cau_parameter: pointer to the input structure
|
||||
alg_dir: algorithm directory
|
||||
CAU_ENCRYPT, CAU_DECRYPT
|
||||
key: key, 24 bytes
|
||||
input: input data
|
||||
in_length: input data length in bytes, must be a multiple of 8 bytes
|
||||
\param[out] output: pointer to the output structure
|
||||
\retval ErrStatus: SUCCESS or ERROR
|
||||
*/
|
||||
ErrStatus cau_tdes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
|
||||
{
|
||||
ErrStatus ret = ERROR;
|
||||
cau_key_parameter_struct key_initpara;
|
||||
uint32_t keyaddr = (uint32_t)(cau_parameter->key);
|
||||
uint32_t inputaddr = (uint32_t)(cau_parameter->input);
|
||||
uint32_t outputaddr = (uint32_t)output;
|
||||
|
||||
/* key structure initialization */
|
||||
cau_key_struct_para_init(&key_initpara);
|
||||
/* initialize the CAU peripheral */
|
||||
cau_init(cau_parameter->alg_dir, CAU_MODE_TDES_ECB, CAU_SWAPPING_8BIT);
|
||||
|
||||
/* key initialization */
|
||||
key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_2_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_2_low = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_3_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_3_low = __REV(*(uint32_t *)(keyaddr));
|
||||
cau_key_init(&key_initpara);
|
||||
|
||||
/* flush the IN and OUT FIFOs */
|
||||
cau_fifo_flush();
|
||||
|
||||
/* enable the CAU peripheral */
|
||||
cau_enable();
|
||||
/* TDES calculate process */
|
||||
ret = cau_tdes_calculate((uint8_t *)inputaddr, cau_parameter->in_length, (uint8_t *)outputaddr);
|
||||
/* disable the CAU peripheral */
|
||||
cau_disable();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief encrypt and decrypt using TDES in CBC mode
|
||||
\param[in] cau_parameter: pointer to the input structure
|
||||
alg_dir: algorithm directory
|
||||
CAU_ENCRYPT, CAU_DECRYPT
|
||||
key: key, 24 bytes
|
||||
iv: initialization vector, 8 bytes
|
||||
input: input data
|
||||
in_length: input data length in bytes, must be a multiple of 8 bytes
|
||||
\param[out] output: pointer to the output structure
|
||||
\retval ErrStatus: SUCCESS or ERROR
|
||||
*/
|
||||
ErrStatus cau_tdes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
|
||||
{
|
||||
ErrStatus ret = ERROR;
|
||||
cau_key_parameter_struct key_initpara;
|
||||
cau_iv_parameter_struct iv_initpara;
|
||||
uint32_t keyaddr = (uint32_t)(cau_parameter->key);
|
||||
uint32_t inputaddr = (uint32_t)(cau_parameter->input);
|
||||
uint32_t outputaddr = (uint32_t)output;
|
||||
uint32_t ivaddr = (uint32_t)(cau_parameter->iv);
|
||||
|
||||
/* key structure initialization */
|
||||
cau_key_struct_para_init(&key_initpara);
|
||||
/* initialize the CAU peripheral */
|
||||
cau_init(cau_parameter->alg_dir, CAU_MODE_TDES_CBC, CAU_SWAPPING_8BIT);
|
||||
|
||||
/* key initialization */
|
||||
key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_2_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_2_low = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_3_high = __REV(*(uint32_t *)(keyaddr));
|
||||
keyaddr += 4U;
|
||||
key_initpara.key_3_low = __REV(*(uint32_t *)(keyaddr));
|
||||
cau_key_init(&key_initpara);
|
||||
|
||||
/* vectors initialization */
|
||||
iv_initpara.iv_0_high = __REV(*(uint32_t *)(ivaddr));
|
||||
ivaddr += 4U;
|
||||
iv_initpara.iv_0_low = __REV(*(uint32_t *)(ivaddr));
|
||||
cau_iv_init(&iv_initpara);
|
||||
|
||||
/* flush the IN and OUT FIFOs */
|
||||
cau_fifo_flush();
|
||||
/* enable the CAU peripheral */
|
||||
cau_enable();
|
||||
/* TDES calculate process */
|
||||
ret = cau_tdes_calculate((uint8_t *)inputaddr, cau_parameter->in_length, (uint8_t *)outputaddr);
|
||||
/* disable the CAU peripheral */
|
||||
cau_disable();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief TDES calculate process
|
||||
\param[in] input: pointer to the input buffer
|
||||
\param[in] in_length: length of the input buffer in bytes, must be a multiple of 8 bytes
|
||||
\param[out] output: pointer to the returned buffer
|
||||
\retval ErrStatus: SUCCESS or ERROR
|
||||
*/
|
||||
static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t *output)
|
||||
{
|
||||
uint32_t inputaddr = (uint32_t)input;
|
||||
uint32_t outputaddr = (uint32_t)output;
|
||||
uint32_t i = 0U;
|
||||
__IO uint32_t counter = 0U;
|
||||
uint32_t busystatus = 0U;
|
||||
|
||||
/* the clock is not enabled or there is no embedded CAU peripheral */
|
||||
if(DISABLE == cau_enable_state_get()) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
for(i = 0U; i < in_length; i += 8U) {
|
||||
/* write data to the IN FIFO */
|
||||
cau_data_write(*(uint32_t *)(inputaddr));
|
||||
inputaddr += 4U;
|
||||
cau_data_write(*(uint32_t *)(inputaddr));
|
||||
inputaddr += 4U;
|
||||
|
||||
/* wait until the complete message has been processed */
|
||||
counter = 0U;
|
||||
do {
|
||||
busystatus = cau_flag_get(CAU_FLAG_BUSY);
|
||||
counter++;
|
||||
} while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus));
|
||||
|
||||
if(RESET != busystatus) {
|
||||
return ERROR;
|
||||
} else {
|
||||
/* read the output block from the output FIFO */
|
||||
*(uint32_t *)(outputaddr) = cau_data_read();
|
||||
outputaddr += 4U;
|
||||
*(uint32_t *)(outputaddr) = cau_data_read();
|
||||
outputaddr += 4U;
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+577
File diff suppressed because it is too large
Load Diff
+246
File diff suppressed because it is too large
Load Diff
+247
File diff suppressed because it is too large
Load Diff
+390
File diff suppressed because it is too large
Load Diff
+750
File diff suppressed because it is too large
Load Diff
+168
@@ -0,0 +1,168 @@
|
||||
/*!
|
||||
\file gd32h7xx_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32h7xx_dbg.h"
|
||||
|
||||
#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */
|
||||
|
||||
/*!
|
||||
\brief deinitialize the DBG
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_deinit(void)
|
||||
{
|
||||
DBG_CTL0 = DBG_RESET_VAL;
|
||||
DBG_CTL1 = DBG_RESET_VAL;
|
||||
DBG_CTL2 = DBG_RESET_VAL;
|
||||
DBG_CTL3 = DBG_RESET_VAL;
|
||||
DBG_CTL4 = DBG_RESET_VAL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable trace pin assignment
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_trace_pin_enable(void)
|
||||
{
|
||||
DBG_CTL0 |= DBG_CTL0_TRACECLKEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable trace pin assignment
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_trace_pin_disable(void)
|
||||
{
|
||||
DBG_CTL0 &= ~DBG_CTL0_TRACECLKEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief trace pin mode selection
|
||||
\param[in] trace_mode:
|
||||
\arg TRACE_MODE_ASYNC: trace pin used for async mode
|
||||
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
|
||||
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
|
||||
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_trace_pin_mode_set(uint32_t trace_mode)
|
||||
{
|
||||
DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
|
||||
DBG_CTL0 |= trace_mode;
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
only one parameter can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,14,15,16,22,23,30,31,40,41,42,43,44,50,51): hold TIMERx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1,2,3): hold I2Cx smbus when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1,2): hold CANx when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
only one parameter can be selected which are shown as below:
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,14,15,16,22,23,30,31,40,41,42,43,44,50,51): hold TIMERx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1,2,3): hold I2Cx smbus when core is halted
|
||||
\arg DBG_CANx_HOLD (x=0,1,2): hold CANx when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
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Reference in New Issue
Block a user