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添加TMS320C6678处理器，keystone架构底层代码

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Huang bo committed 2021-11-16 18:32:11 +08:00
1 parent 4907b44930
commit 3639963a97
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bsp/ti-c6678/.ccsproject
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bsp/ti-c6678/.cproject
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<name>device.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/device.c</locationURI>
</link>
<link>
<name>idle.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/idle.c</locationURI>
</link>
<link>
<name>inct.asm</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c6x/inct.asm</locationURI>
</link>
<link>
<name>interrupt.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c6x/interrupt.c</locationURI>
</link>
<link>
<name>ipc.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/ipc.c</locationURI>
</link>
<link>
<name>irq.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/irq.c</locationURI>
</link>
<link>
<name>kservice.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/kservice.c</locationURI>
</link>
<link>
<name>mem.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/mem.c</locationURI>
</link>
<link>
<name>memheap.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/memheap.c</locationURI>
</link>
<link>
<name>mempool.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/mempool.c</locationURI>
</link>
<link>
<name>object.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/object.c</locationURI>
</link>
<link>
<name>scheduler.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/scheduler.c</locationURI>
</link>
<link>
<name>signal.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/signal.c</locationURI>
</link>
<link>
<name>slab.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/slab.c</locationURI>
</link>
<link>
<name>stack.asm</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c6x/stack.asm</locationURI>
</link>
<link>
<name>thread.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/thread.c</locationURI>
</link>
<link>
<name>timer.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/src/timer.c</locationURI>
</link>
<link>
<name>trap.c</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c6x/trap.c</locationURI>
</link>
<link>
<name>vector.asm</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c6x/vector.asm</locationURI>
</link>
</linkedResources>
</projectDescription>
bsp/ti-c6678/.settings/org.eclipse.cdt.codan.core.prefs
+3
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@@ -0,0 +1,3 @@
eclipse.preferences.version=1
inEditor=false
onBuild=false
bsp/ti-c6678/.settings/org.eclipse.cdt.debug.core.prefs
+2
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@@ -0,0 +1,2 @@
eclipse.preferences.version=1
org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
bsp/ti-c6678/.settings/org.eclipse.core.resources.prefs
+10
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@@ -0,0 +1,10 @@
eclipse.preferences.version=1
encoding//Debug/applications/subdir_rules.mk=UTF-8
encoding//Debug/applications/subdir_vars.mk=UTF-8
encoding//Debug/driver/subdir_rules.mk=UTF-8
encoding//Debug/driver/subdir_vars.mk=UTF-8
encoding//Debug/makefile=UTF-8
encoding//Debug/objects.mk=UTF-8
encoding//Debug/sources.mk=UTF-8
encoding//Debug/subdir_rules.mk=UTF-8
encoding//Debug/subdir_vars.mk=UTF-8
bsp/ti-c6678/KeyStone.cmd
+47
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@@ -0,0 +1,47 @@
/****************************************************************************/
/* */
/* M6678.cmd */
/* Copyright (c): NUDT */
/* */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on an M6678 */
/* device. Use it as a guideline. You will want to */
/* change the memory layout to match your specific C6xxx */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/* */
/****************************************************************************/
-heap 0x800
-stack 0x1000
MEMORY
{
VECTORS: o = 0x00800000 l = 0x00000200
LL2_CODE: o = 0x00800200 l = 0x0001FE00
LL2_RW_DATA: o = 0x00820000 l = 0x00020000 /*set memory protection attribitue as read/write*/
}
SECTIONS
{
.vecs > VECTORS
.text > LL2_CODE
.cinit > LL2_CODE
.const > LL2_CODE
.switch > LL2_CODE
.stack > LL2_RW_DATA
GROUP
{
.neardata
.rodata
.bss
} > LL2_RW_DATA
.far > LL2_RW_DATA
.fardata > LL2_RW_DATA
.cio > LL2_RW_DATA
.sysmem > LL2_RW_DATA
}
bsp/ti-c6678/applications/board.c
+60
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@@ -0,0 +1,60 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#include "board.h"
#include "trap.h"
#include "interrupt.h"
#include "drv_timer.h"
#include "KeyStone_common.h"
#include <rtthread.h>
/**
* This is the timer interrupt service routine.
*
*/
void rt_hw_systick_isr(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial board.
*/
void rt_hw_board_init(void)
{
// initial CPU core
KeyStone_common_CPU_init();
// initial interrupt controller
rt_hw_interrupt_init();
// initial system trap
rt_trap_init();
// initial system timer
hw_system_timer_init();
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
// ......
hw_system_timer_start();
}
bsp/ti-c6678/applications/board.h
+20
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@@ -0,0 +1,20 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#define RT_HW_HEAP_BEGIN (void*)0x0C000000
#define RT_HW_HEAP_END (void*)0x0C100000
void rt_hw_board_init(void);
#endif /* __BOARD_H__ */
bsp/ti-c6678/applications/main.c
+99
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@@ -0,0 +1,99 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
void rt_init_thread_entry(void *parameter)
{
while(1)
{
rt_thread_sleep(10);
}
}
void rt_my_thread_entry(void *parameter)
{
while(1)
{
rt_thread_sleep(20);
}
}
int rt_application_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 4096, 3, 200);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
} else {
return -1;
}
/******************************************************************/
tid = rt_thread_create("mythread", rt_my_thread_entry, RT_NULL, 4096, 3, 200);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
} else {
return -1;
}
return 0;
}
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init timer system */
rt_system_timer_init();
/* init scheduler system */
rt_system_scheduler_init();
/* init application */
rt_application_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
void main(void)
{
/* startup RT-Thread RTOS */
rtthread_startup();
for ( ; ; );
}
bsp/ti-c6678/driver/KeyStone_common.c
+4355
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bsp/ti-c6678/driver/KeyStone_common.h
+1090
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bsp/ti-c6678/driver/drv_timer.c
+55
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/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#include "drv_timer.h"
#include "KeyStone_common.h"
#include <rthw.h>
#include <rtthread.h>
/**
* @b Description
* @n
* The function initial system timer.
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
*
* @param[]
*
* @retval
* NULL
*/
void hw_system_timer_init(void)
{
// initial system timer interrupt
// map local timer interrupt to INT14
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN<<CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
// enable INT14
CPU_interrupt_enable(1<<14);
return ;
}
void hw_system_timer_start(void)
{
Timer64_Config tmrCfg;
//select output on TIMO0 from local timer.
gpBootCfgRegs->TOUTSEL = (DNUM*2)<<CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
/* configure the timer to generate clocks and interrupts */
tmrCfg.timer_num= DNUM;
tmrCfg.timerMode= TIMER_PERIODIC_CLOCK;
tmrCfg.period= (unsigned long long) RT_TICK_PER_SECOND*gDSP_Core_Speed_Hz/6000;
tmrCfg.reload_period= 0; //not used for this case
// initial timer
Timer64_Init(&tmrCfg);
}
bsp/ti-c6678/driver/drv_timer.h
+19
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@@ -0,0 +1,19 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#ifndef __SYS_TIMER_H__
#define __SYS_TIMER_H__
void hw_system_timer_init(void);
void hw_system_timer_start(void);
#endif /* __SYS_TIMER_H__ */
bsp/ti-c6678/rtconfig.h
+122
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
#define SOC_C6678
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_USING_ARCH_DATA_TYPE
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_8
#define RT_THREAD_PRIORITY_MAX 8
#define RT_TICK_PER_SECOND 100
//#define RT_USING_HOOK
//#define RT_USING_IDLE_HOOK
//#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
//#define RT_DEBUG
//#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
/* RT-Thread Components */
/* C++ features */
/* Command shell */
/* Device virtual file system */
/* Device Drivers */
/* Using WiFi */
/* Using USB */
/* POSIX layer and C standard library */
/* Network */
/* Socket abstraction layer */
/* light weight TCP/IP stack */
/* Modbus master and slave stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
#include "rtconfig_project.h"
#endif
bsp/ti-c6678/rtconfig_project.h
+23
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@@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-27 xuzhuoyi the first version
*/
#ifndef __RTCONFIG_PROJECT_H__
#define __RTCONFIG_PROJECT_H__
typedef signed char rt_int8_t; /**< 8bit integer type */
typedef signed short rt_int16_t; /**< 16bit integer type */
typedef signed long rt_int32_t; /**< 32bit integer type */
typedef signed long long rt_int64_t; /**< 64bit integer type */
typedef unsigned char rt_uint8_t; /**< 8bit unsigned integer type */
typedef unsigned short rt_uint16_t; /**< 16bit unsigned integer type */
typedef unsigned long rt_uint32_t; /**< 32bit unsigned integer type */
typedef unsigned long long rt_uint64_t; /**< 64bit unsigned integer type */
#endif
libcpu/ti-dsp/c6x/SConscript
+14
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@@ -0,0 +1,14 @@
# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*.asm')
CPPPATH = [cwd]
ASFLAGS = ''
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
Return('group')
libcpu/ti-dsp/c6x/c66xx.h
+106
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@@ -0,0 +1,106 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#ifndef __C66XX_H__
#define __C66XX_H__
#include <c6x.h>
#ifdef _BIG_ENDIAN
#define REG_PAIR(odd, even) unsigned long odd; unsigned long even
#else
#define REG_PAIR(odd, even) unsigned long even; unsigned long odd
#endif
/*
* this struct defines the way the registers are stored on the
* stack during a system call. fields defined with REG_PAIR
* are saved and restored using double-word memory operations
* which means the word ordering of the pair depends on endianess.
*/
struct rt_hw_register
{
REG_PAIR(b17, b16);
REG_PAIR(b19, b18);
REG_PAIR(b21, b20);
REG_PAIR(b23, b22);
REG_PAIR(b25, b24);
REG_PAIR(b27, b26);
REG_PAIR(b29, b28);
REG_PAIR(b31, b30);
REG_PAIR(b1, b0);
REG_PAIR(b3, b2);
REG_PAIR(b5, b4);
REG_PAIR(b7, b6);
REG_PAIR(b9, b8);
REG_PAIR(b11, b10);
REG_PAIR(b13, b12);
REG_PAIR(a17, a16);
REG_PAIR(a19, a18);
REG_PAIR(a21, a20);
REG_PAIR(a23, a22);
REG_PAIR(a25, a24);
REG_PAIR(a27, a26);
REG_PAIR(a29, a28);
REG_PAIR(a31, a30);
REG_PAIR(a1, a0);
REG_PAIR(a3, a2);
REG_PAIR(a5, a4);
REG_PAIR(a7, a6);
REG_PAIR(a9, a8);
REG_PAIR(a11, a10);
REG_PAIR(a13, a12);
REG_PAIR(a15, a14);
REG_PAIR(sp, dp);
};
struct rt_hw_exp_stack_register
{
REG_PAIR(tsr, orig_a4);
REG_PAIR(rilc, ilc);
REG_PAIR(pc, csr);
struct rt_hw_register hw_register;
};
extern cregister volatile unsigned int IERR; /* Internal Exception Report Register */
extern cregister volatile unsigned int ECR; /* Exception Clear Register */
extern cregister volatile unsigned int EFR; /* Exception Flag Register */
extern cregister volatile unsigned int TSR; /* Task State Register */
extern cregister volatile unsigned int ITSR; /* Interrupt Task State Register */
extern cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */
extern cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */
extern cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */
extern cregister volatile unsigned int DNUM; /* Core number */
#define get_creg(reg) reg
#define set_creg(reg, v) reg = (v)
#define or_creg(reg, n) reg |= (n)
#define and_creg(reg, n) reg &= (n)
#define __dint() asm(" DINT")
#define __rint() asm(" RINT")
#define __system_call() asm(" SWE")
#define __enter_idle() asm(" IDLE")
#define __nop() asm(" NOP")
#define __mfence() asm(" MFENCE")
#define __SYSREG(ADDR, TYPE) (*(volatile TYPE*)(ADDR))
#define __SYSREGA(ADDR, TYPE) ((volatile TYPE*)(ADDR))
extern void rt_hw_enable_exception(void);
#endif /* __C66XX_H__ */
libcpu/ti-dsp/c6x/context.asm
+312
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libcpu/ti-dsp/c6x/cpuport.c
+225
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libcpu/ti-dsp/c6x/inct.asm
+374
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libcpu/ti-dsp/c6x/interrupt.c
+90
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@@ -0,0 +1,90 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#include "c66xx.h"
#include "interrupt.h"
#define MAX_HANDLERS 128
extern volatile rt_uint8_t rt_interrupt_nest;
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
/* init exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
if (vector < 0 || vector >= MAX_HANDLERS)
return;
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
if (vector < 0 || vector >= MAX_HANDLERS)
return;
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS || vector >= 0)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
void rt_hw_interrupt_clear(int vector)
{
if (vector < 0 || vector >= MAX_HANDLERS)
return;
}
libcpu/ti-dsp/c6x/interrupt.h
+24
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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <rtthread.h>
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
void rt_hw_interrupt_clear(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#endif /* __INTERRUPT_H__ */
libcpu/ti-dsp/c6x/stack.asm
+103
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;
; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
;
; SPDX-License-Identifier: Apache-2.0
;
; Change Logs:
; Date Author Notes
; 2021-11-16 Dystopia the first version
;
;-----------------------------------------------------------
; build system stack for C6678 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
; macro definition
;-----------------------------------------------------------
ADDRESS_MSK .set 0xFFFFFFF0
;
;-----------------------------------------------------------
;
.sect ".text"
;
; rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
; tentry --> A4
; parameter --> B4
; stack_addr --> A6
; texit --> B6
;{
.global rt_hw_stack_init
rt_hw_stack_init:
SUB A6,1,B1 ;
MVKL ADDRESS_MSK,A1 ;
MVKH ADDRESS_MSK,A1 ; Build address mask
MVC CSR,B0 ;
AND -2,B0,B0 ; Clear GIE bit
OR 2,B0,B0 ; Set PGIE bit for interrupt return
AND A1,B1,B1 ; Ensure alignment
;
; Actually build the stack frame.
;
MV B1,A3
MV B14,A2
STDW A3:A2,*--B1[1] ; Initial B15:B14
SUBAW .D2 B1,2,B1
ZERO A2
ZERO A3 ; Clear value
STDW A3:A2,*B1--[1] ; Initial A15:A14
STDW A3:A2,*B1--[1] ; Initial A13:A12
STDW A3:A2,*B1--[1] ; Initial A11:A10
STDW A3:A2,*B1--[1] ; Initial A9:A8
STDW A3:A2,*B1--[1] ; Initial A7:A6
MV B4,A2
STDW A3:A2,*B1--[1] ; Initial A5:A4
ZERO A2
STDW A3:A2,*B1--[1] ; Initial A3:A2
STDW A3:A2,*B1--[1] ; Initial A1:A0
STDW A3:A2,*B1--[1] ; Initial A31:A30
STDW A3:A2,*B1--[1] ; Initial A29:A28
STDW A3:A2,*B1--[1] ; Initial A27:A26
STDW A3:A2,*B1--[1] ; Initial A25:A24
STDW A3:A2,*B1--[1] ; Initial A23:A22
STDW A3:A2,*B1--[1] ; Initial A21:A20
STDW A3:A2,*B1--[1] ; Initial A19:A18
STDW A3:A2,*B1--[1] ; Initial A17:A16
STDW A3:A2,*B1--[1] ; Initial B13:B12
STDW A3:A2,*B1--[1] ; Initial B11:B10
STDW A3:A2,*B1--[1] ; Initial B9:B8
STDW A3:A2,*B1--[1] ; Initial B7:B6
STDW A3:A2,*B1--[1] ; Initial B5:B4
MV B6,A3
STDW A3:A2,*B1--[1] ; Initial B3:B2
ZERO A3
STDW A3:A2,*B1--[1] ; Initial B1:B0
STDW A3:A2,*B1--[1] ; Initial B31:B30
STDW A3:A2,*B1--[1] ; Initial B29:B28
STDW A3:A2,*B1--[1] ; Initial B27:B26
STDW A3:A2,*B1--[1] ; Initial B25:B24
STDW A3:A2,*B1--[1] ; Initial B23:B22
STDW A3:A2,*B1--[1] ; Initial B21:B20
STDW A3:A2,*B1--[1] ; Initial B19:B18
STDW A3:A2,*B1--[1] ; Initial B17:B16
MV A4,A3
MV B0,A2
STDW A3:A2,*B1--[1] ; Initial PC:CSR
ZERO A2
ZERO A3
STDW A3:A2,*B1--[1] ; Initial ILC:RILC
B B3
MVKL 0x3,B0
MV B0,A3
MVKL 1,A2
STDW A3:A2,*B1--[1] ; Initial TSR:stack type
MV B1,A4 ; Save to TCB
;}
.end
libcpu/ti-dsp/c6x/trap.c
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libcpu/ti-dsp/c6x/trap.h
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/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#ifndef __TRAP_H__
#define __TRAP_H__
#include "c66xx.h"
/*
* exception operation macro
*/
#define disable_exception()
#define get_except_type() EFR
#define ack_exception(type) ECR = 1ul << (type)
#define get_iexcept() IERR
#define set_iexcept(mask) IERR = (mask)
/*
* exception types
*/
#define EXCEPT_TYPE_NXF 31 /* NMI */
#define EXCEPT_TYPE_EXC 30 /* external exception */
#define EXCEPT_TYPE_IXF 1 /* internal exception */
#define EXCEPT_TYPE_SXF 0 /* software exception */
#define EXCEPT_CAUSE_LBX (1 << 7) /* loop buffer exception */
#define EXCEPT_CAUSE_PRX (1 << 6) /* privilege exception */
#define EXCEPT_CAUSE_RAX (1 << 5) /* resource access exception */
#define EXCEPT_CAUSE_RCX (1 << 4) /* resource conflict exception */
#define EXCEPT_CAUSE_OPX (1 << 3) /* opcode exception */
#define EXCEPT_CAUSE_EPX (1 << 2) /* execute packet exception */
#define EXCEPT_CAUSE_FPX (1 << 1) /* fetch packet exception */
#define EXCEPT_CAUSE_IFX (1 << 0) /* instruction fetch exception */
enum SYSTEM_TRAP_CODE
{
ABORT_BUS_ADDRERR = 0, // bus address error
ABORT_BUS_ACCERR, // bus access permission error
ABORT_OPCODE_ILL, // illegal opcode
ABORT_PRVREG_ILL, // privilege register
ABORT_PRVOPC_ILL, // privileged opcode
ABORT_ILLTRP_ILL, // illegal trap
ABORT_BRKPT_ILL, // handling breakpoints
};
/*
* abort types
*/
#define ABORT_TYPE_BUS 0 // bus access abnormal
#define ABORT_TYPE_MAP 1 // page table mapping error
#define ABORT_TYPE_UNDDEF 0xff // undefined exception
#define ABORT_TYPE_FATAL 0xffffffff // fatal error
struct rt_exception_info {
char *kernel_str;
int type;
int code;
};
#define BKPT_OPCODE 0x56454314 /* illegal opcode */
#define INTC_MEXPMASK __SYSREGA(0x018000e0, unsigned int)
#define __ffs(a) (_lmbd(1, _bitr(a)))
#define fls(a) (!(a) ? 0 : (32 - _lmbd(1, (a))))
void rt_trap_init(void);
#endif /* __TRAP_H__ */
libcpu/ti-dsp/c6x/vector.asm
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;
; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
;
; SPDX-License-Identifier: Apache-2.0
;
; Change Logs:
; Date Author Notes
; 2021-11-16 Dystopia the first version
;
;-----------------------------------------------------------
; interrupt vector table for C6678 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
; extern function
;-----------------------------------------------------------
.ref _c_int00 ; entry point
.ref _nmi_handler
.ref _bad_handler
.ref _int4_handler
.ref _int5_handler
.ref _int6_handler
.ref _int7_handler
.ref _int8_handler
.ref _int9_handler
.ref _int10_handler
.ref _int11_handler
.ref _int12_handler
.ref _int13_handler
.ref _int14_handler
.ref _int15_handler
;-----------------------------------------------------------
; macro definition
;-----------------------------------------------------------
;
; create interrupt vector for reset (interrupt 0)
;
VEC_RESET .macro addr
MVKL addr,B0
MVKH addr,B0
B B0
MVC PCE1,B0
NOP 4
.align 32
.endm
;
; create interrupt vector for other used interrupts
;
IRQVEC .macro __name, __isr
.align 32
.hidden __name
.global __name
__name:
B .S2 __isr
NOP
NOP
NOP
NOP
NOP
NOP
NOP
.endm
;
;-----------------------------------------------------------
;
;
; vector table
;
.sect ".vecs"
.align 32
.global vector
vector:
VEC_RESET _c_int00
IRQVEC NMI, _nmi_handler
IRQVEC AINT, _bad_handler
IRQVEC MSGINT,_bad_handler
IRQVEC INT4, _int4_handler
IRQVEC INT5, _int5_handler
IRQVEC INT6, _int6_handler
IRQVEC INT7, _int7_handler
IRQVEC INT8, _int8_handler
IRQVEC INT9, _int9_handler
IRQVEC INT10, _int10_handler
IRQVEC INT11, _int11_handler
IRQVEC INT12, _int12_handler
IRQVEC INT13, _int13_handler
IRQVEC INT14, _int14_handler
IRQVEC INT15, _int15_handler
.end