Merge pull request #2 from RT-Thread/master

update
2026-11-09 20:45:41 +08:00 · 2020-11-21 16:23:43 +08:00
commit 3634621815
@@ -138,6 +138,7 @@ env:
  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='at32/at32f403a-start' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='at32/at32f407-start' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='smartfusion2' RTT_TOOL_CHAIN='sourcery-arm'

 stage: compile
 script:
@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40001
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set

 #
@@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
@@ -115,12 +118,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 CONFIG_RT_USING_CPUTIME=y
 # CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PHY=y
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
@@ -128,10 +132,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
-
-#
-# Using WiFi
-#
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set

 #
@@ -145,6 +149,7 @@ CONFIG_RT_USING_PIN=y
 #
 CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set

 #
 # Network
@@ -155,15 +160,26 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_RT_USING_SAL is not set

+#
+# Network interface device
+#
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+
 #
 # light weight TCP/IP stack
 #
 # CONFIG_RT_USING_LWIP is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+# CONFIG_RT_USING_LWIP212 is not set

 #
 # AT commands
@@ -178,7 +194,6 @@ CONFIG_RT_USING_LIBC=y
 #
 # Utilities
 #
-# CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
@@ -230,13 +245,12 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
 # CONFIG_PKG_USING_LSSDP is not set
 # CONFIG_PKG_USING_AIRKISS_OPEN is not set
-# CONFIG_PKG_USING_LIBRWS is not set

 #
 # security packages
@@ -294,6 +308,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SENSORS_DRIVERS is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AP3216C is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -310,7 +325,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
 # CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_PCA9685 is not set
-# CONFIG_PKG_USING_I2C_TOOLS is not set

 #
 # miscellaneous packages
@@ -354,10 +368,13 @@ CONFIG_BSP_USING_LPUART=y
 CONFIG_BSP_USING_LPUART1=y
 # CONFIG_BSP_LPUART1_RX_USING_DMA is not set
 # CONFIG_BSP_LPUART1_TX_USING_DMA is not set
+# CONFIG_BSP_USING_LPUART3 is not set

 #
 # Onboard Peripheral Drivers
 #
+# CONFIG_BSP_USING_SDRAM is not set
+# CONFIG_BSP_USING_ETH is not set

 #
 # Board extended module Drivers
@@ -67,5 +67,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))

+# include peripherals
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)
@@ -96,19 +96,41 @@ menu "Onboard Peripheral Drivers"

    menuconfig BSP_USING_ETH
 	bool "Enable Ethernet"
-	select PHY_USING_KSZ8081
 	select RT_USING_NETDEV
 	default n
+    

 	if BSP_USING_ETH
-		config PHY_USING_KSZ8081
-			bool "i.MX RT1050EVKB uses ksz8081 phy"
+		config BSP_USING_PHY
+            select RT_USING_PHY
+			bool "Enable ethernet phy"
 			default y

-			config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
-				bool "Enable the PHY ksz8081 RMII50M mode"
-				depends on PHY_USING_KSZ8081
-				default y
+	    if BSP_USING_PHY
+            config PHY_DEVICE_ADDRESS
+                int "Specify address of phy device"
+                default 2
+
+            config PHY_USING_KSZ8081
+                bool "i.MX RT1064EVK uses ksz8081 phy"
+                default y
+
+            if PHY_USING_KSZ8081
+                config PHY_RESET_PORT
+                    int "indicate port of reset"
+                    default 1
+
+                config PHY_RESET_PIN
+                    int "indicate pin of reset"
+                    default 9
+                
+                config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
+                    bool "Enable the PHY ksz8081 RMII50M mode"
+                    depends on PHY_USING_KSZ8081
+                    default y
+            endif
+
+        endif
 	endif
 endmenu

@@ -12,10 +12,6 @@ MCUX_Config/pin_mux.c
 CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
 CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1']

-if GetDepend(['PHY_USING_KSZ8081']):
-    src += Glob('ports/phyksz8081/fsl_phy.c')
-    CPPPATH += [cwd + '/ports/phyksz8081']
-
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)

 Return('group')
@@ -1,200 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- * All rights reserved.
- * 
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef _FSL_PHY_H_
-#define _FSL_PHY_H_
-
-#include "fsl_enet.h"
-
-/*!
- * @addtogroup phy_driver
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief PHY driver version */
-#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-
-/*! @brief Defines the PHY registers. */
-#define PHY_BASICCONTROL_REG 0x00U      /*!< The PHY basic control register. */
-#define PHY_BASICSTATUS_REG 0x01U       /*!< The PHY basic status register. */
-#define PHY_ID1_REG 0x02U               /*!< The PHY ID one register. */
-#define PHY_ID2_REG 0x03U               /*!< The PHY ID two register. */
-#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
-#define PHY_CONTROL1_REG 0x1EU          /*!< The PHY control one register. */
-#define PHY_CONTROL2_REG 0x1FU          /*!< The PHY control two register. */
-
-#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
-
-/*! @brief Defines the mask flag in basic control register. */
-#define PHY_BCTL_DUPLEX_MASK 0x0100U          /*!< The PHY duplex bit mask. */
-#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
-#define PHY_BCTL_AUTONEG_MASK 0x1000U         /*!< The PHY auto negotiation bit mask. */
-#define PHY_BCTL_SPEED_MASK 0x2000U           /*!< The PHY speed bit mask. */
-#define PHY_BCTL_LOOP_MASK 0x4000U            /*!< The PHY loop bit mask. */
-#define PHY_BCTL_RESET_MASK 0x8000U           /*!< The PHY reset bit mask. */
-#define PHY_BCTL_SPEED_100M_MASK  0x2000U     /*!< The PHY 100M speed mask. */
-
-/*!@brief Defines the mask flag of operation mode in control two register*/
-#define PHY_CTL2_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
-#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 
-#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U  /*!< The PHY 10M half duplex mask. */
-#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
-#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U  /*!< The PHY 10M full duplex mask. */
-#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
-#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U     /*!< The PHY speed and duplex mask. */
-#define PHY_CTL1_ENERGYDETECT_MASK 0x10U    /*!< The PHY signal present on rx differential pair. */
-#define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */        
-#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
-   
-/*! @brief Defines the mask flag in basic status register. */
-#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U  /*!< The PHY link status mask. */
-#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
-#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
-
-/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
-#define PHY_100BaseT4_ABILITY_MASK 0x200U    /*!< The PHY have the T4 ability. */
-#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
-#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
-#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U  /*!< The PHY has the 10M full duplex ability.*/
-#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U  /*!< The PHY has the 10M full duplex ability.*/
-
-/*! @brief Defines the PHY status. */
-enum _phy_status
-{
-    kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1),  /*!< ENET PHY SMI visit timeout. */
-    kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
-};
-
-/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
-typedef enum _phy_speed
-{
-    kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
-    kPHY_Speed100M      /*!< ENET PHY 100M speed. */
-} phy_speed_t;
-
-/*! @brief Defines the PHY link duplex. */
-typedef enum _phy_duplex
-{
-    kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
-    kPHY_FullDuplex       /*!< ENET PHY full duplex. */
-} phy_duplex_t;
-
-/*! @brief Defines the PHY loopback mode. */
-typedef enum _phy_loop
-{
-    kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
-    kPHY_RemoteLoop      /*!< ENET PHY remote loopback. */
-} phy_loop_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
-  * @name PHY Driver
-  * @{
-  */
-
-/*!
- * @brief Initializes PHY.
- *
- *  This function initialize the SMI interface and initialize PHY.
- *  The SMI is the MII management interface between PHY and MAC, which should be
- *  firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. 
- *
- * @param base       ENET peripheral base address.
- * @param phyAddr    The PHY address.
- * @param srcClock_Hz  The module clock frequency - system clock for MII management interface - SMI.
- * @retval kStatus_Success  PHY initialize success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- * @retval kStatus_PHY_AutoNegotiateFail  PHY auto negotiate fail
- */
-status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
-
-/*!
- * @brief PHY Write function. This function write data over the SMI to
- * the specified PHY register. This function is called by all PHY interfaces.
- *
- * @param base    ENET peripheral base address.
- * @param phyAddr The PHY address.
- * @param phyReg  The PHY register.
- * @param data    The data written to the PHY register.
- * @retval kStatus_Success     PHY write success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
-
-/*!
- * @brief PHY Read function. This interface read data over the SMI from the
- * specified PHY register. This function is called by all PHY interfaces.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param phyReg   The PHY register.
- * @param dataPtr  The address to store the data read from the PHY register.
- * @retval kStatus_Success  PHY read success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
-
-/*!
- * @brief Enables/disables PHY loopback.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param mode     The loopback mode to be enabled, please see "phy_loop_t".
- * the two loopback mode should not be both set. when one loopback mode is set
- * the other one should be disabled.
- * @param speed    PHY speed for loopback mode.
- * @param enable   True to enable, false to disable.
- * @retval kStatus_Success  PHY loopback success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
-
-/*!
- * @brief Gets the PHY link status.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param status   The link up or down status of the PHY.
- *         - true the link is up.
- *         - false the link is down.
- * @retval kStatus_Success   PHY get link status success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
-
-/*!
- * @brief Gets the PHY link speed and duplex.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param speed    The address of PHY link speed.
- * @param duplex   The link duplex of PHY.
- * @retval kStatus_Success   PHY get link speed and duplex success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_PHY_H_ */
@@ -40,7 +40,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40001
+#define RT_VER_NUM 0x40003

 /* RT-Thread Components */

@@ -78,11 +78,9 @@
 #define RT_USING_SERIAL
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_CPUTIME
+#define RT_USING_PHY
 #define RT_USING_PIN

-/* Using WiFi */
-
-
 /* Using USB */


@@ -95,12 +93,19 @@
 /* Socket abstraction layer */


+/* Network interface device */
+
+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0
+
 /* light weight TCP/IP stack */


-/* Modbus master and slave stack */
-
-
 /* AT commands */


@@ -163,6 +168,7 @@

 /* Onboard Peripheral Drivers */

+
 /* Board extended module Drivers */


@@ -39,7 +39,7 @@
 | :----------------- | :----------: | :------------------------------------- |
 | USB 转串口        |     支持     |                                       |
 | SPI Flash         |     支持     |                                       |
-| 以太网            |   暂不支持    |                                       |
+| 以太网            |      支持    |                                       |
 | SD卡              |   暂不支持   |                                       |
 | CAN               |   暂不支持   |                                       |
 | **片上外设**      | **支持情况** | **备注**                              |
@@ -66,5 +66,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))

+# include peripherals
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)
@@ -18,6 +18,7 @@

 int main(void)
 {
+#ifndef PHY_USING_KSZ8081
    /* set LED0 pin mode to output */
    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);

@@ -28,6 +29,7 @@ int main(void)
        rt_pin_write(LED0_PIN, PIN_LOW);
        rt_thread_mdelay(500);
    }
+#endif
 }

 void reboot(void)
@@ -37,7 +37,49 @@ menu "On-chip Peripheral Drivers"
 endmenu

 menu "Onboard Peripheral Drivers"
+    
+    config BSP_USING_SDRAM
+        bool "Enable SDRAM"
+        default n

+    menuconfig BSP_USING_ETH
+	bool "Enable Ethernet"
+	select RT_USING_NETDEV
+	default n
+    
+
+	if BSP_USING_ETH
+		config BSP_USING_PHY
+            select RT_USING_PHY
+			bool "Enable ethernet phy"
+			default y
+
+	    if BSP_USING_PHY
+            config PHY_DEVICE_ADDRESS
+                int "Specify address of phy device"
+                default 2
+
+            config PHY_USING_KSZ8081
+                bool "i.MX RT1064EVK uses ksz8081 phy"
+                default y
+
+            if PHY_USING_KSZ8081
+                config PHY_RESET_PORT
+                    int "indicate port of reset"
+                    default 1
+
+                config PHY_RESET_PIN
+                    int "indicate pin of reset"
+                    default 9
+                
+                config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
+                    bool "Enable the PHY ksz8081 RMII50M mode"
+                    depends on PHY_USING_KSZ8081
+                    default y
+            endif
+
+        endif
+	endif
 endmenu

 menu "Board extended module Drivers"
@@ -13,7 +13,7 @@ MCUX_Config/pin_mux.c

 CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']

-CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'STD=C99', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1']
+CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1']

 if rtconfig.CROSS_TOOL == 'keil':
    CPPDEFINES.append('__FPU_PRESENT=1')
@@ -45,5 +45,11 @@ extern int heap_end;

 void rt_hw_board_init(void);

+#ifdef BSP_USING_ETH
+void imxrt_enet_pins_init(void);
+void imxrt_enet_phy_reset_by_gpio(void);
+
+#endif
+
 #endif

@@ -66,6 +66,8 @@
 #define m_data3_start                  0x00000000       ; ITCM 128KB
 #define m_data3_size                   0x00020000

+#define m_ncache_start                 0x81E00000
+#define m_ncache_size                  0x00200000

 /* Sizes */
 #if (defined(__stack_size__))
@@ -124,7 +126,7 @@ LR_IROM1 m_text_start m_text_size
    RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}

    ; ncache RW data
-    RW_m_ncache m_data2_start m_data2_size 
+    RW_m_ncache m_ncache_start m_ncache_size
    { 
        * (NonCacheable.init)
        * (NonCacheable)
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-05     zylx         The first version for STM32F4xx
+ * 2019-4-25      misonyo      port to IMXRT
+ */
+
+#ifndef SDRAM_PORT_H__
+#define SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+
+#define SDRAM_BANK_ADDR                 ((uint32_t)0x80000000U)
+/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
+#define SDRAM_REGION                    kSEMC_SDRAM_CS0
+/* CS pin: kSEMC_MUXCSX0/1/2/3 */
+#define SDRAM_CS_PIN                    kSEMC_MUXCSX0
+/* size(kbyte):32MB = 32*1024*1KBytes */
+#define SDRAM_SIZE                      ((uint32_t)0x8000)
+/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
+#define SDRAM_DATA_WIDTH                kSEMC_PortSize16Bit
+/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
+#define SDRAM_COLUMN_BITS               kSEMC_SdramColunm_9bit
+/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
+#define SDRAM_CAS_LATENCY               kSEMC_LatencyThree
+
+/* Timing configuration for W9825G6KH */
+/* TRP:precharge to active command time (ns) */
+#define SDRAM_TRP                       18
+/* TRCD:active to read/write command delay time (ns) */
+#define SDRAM_TRCD                      18
+/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
+#define SDRAM_REFRESH_RECOVERY          67
+/* TWR:write recovery time (ns). */
+#define SDRAM_TWR                       12
+/* TRAS:active to precharge command time (ns). */
+#define SDRAM_TRAS       42
+/* TRC time (ns). */
+#define SDRAM_TRC                       60
+/* active to active time (ns). */
+#define SDRAM_ACT2ACT                   60
+/* refresh time (ns). 64ms */
+#define SDRAM_REFRESH_ROW               64 * 1000000 / 8192
+
+#endif /* SDRAM_PORT_H__ */
@@ -48,7 +48,7 @@ if PLATFORM == 'gcc':
    DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
    CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry'
    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
-    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -Xlinker -print-memory-usage'

    CPATH = ''
    LPATH = ''
@@ -57,8 +57,8 @@ if PLATFORM == 'gcc':
    AFLAGS += ' -D__STARTUP_CLEAR_BSS'

    if BUILD == 'debug':
-        CFLAGS += ' -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -g'
+        AFLAGS += ' -g'
        CFLAGS += ' -O0'
    else:
        CFLAGS += ' -O2 -Os'
@@ -44,6 +44,9 @@ if GetDepend('BSP_USING_LCD'):

 if GetDepend('BSP_USING_ETH'):
    src += ['drv_eth.c']
+    
+if GetDepend('BSP_USING_PHY'):
+    src += ['drv_mdio.c']

 if GetDepend('BSP_USING_USB_DEVICE'):
    src += ['drv_usbd.c']
@@ -7,6 +7,7 @@
 * Date           Author       Notes
 * 2017-10-10     Tanek        the first version
 * 2019-5-10      misonyo      add DMA TX and RX function
+ * 2020-10-14     wangqiang    use phy device in phy monitor thread
 */

 #include <rtthread.h>
@@ -19,7 +20,6 @@

 #include "fsl_enet.h"
 #include "fsl_gpio.h"
-#include "fsl_phy.h"
 #include "fsl_cache.h"
 #include "fsl_iomuxc.h"
 #include "fsl_common.h"
@@ -537,31 +537,47 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
    return NULL;
 }

+#ifdef BSP_USING_PHY
+static struct rt_phy_device *phy_dev = RT_NULL;
 static void phy_monitor_thread_entry(void *parameter)
 {
-    phy_speed_t speed;
-    phy_duplex_t duplex;
-    bool link = false;
+    rt_uint32_t speed;
+    rt_uint32_t duplex;
+    rt_bool_t link = RT_FALSE;

-    imxrt_enet_phy_reset_by_gpio();
-
-    PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk));
+    phy_dev = (struct rt_phy_device *)rt_device_find("rtt-phy");
+    if ((RT_NULL == phy_dev) || (RT_NULL == phy_dev->ops))
+    {
+        // TODO print warning information
+        LOG_E("Can not find phy device called \"rtt-phy\"");
+        return ;
+    }
+    if (RT_NULL == phy_dev->ops->init)
+    {
+        LOG_E("phy driver error!");
+        return ;
+    }
+    rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_DEVICE_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk));
+    if (PHY_STATUS_OK != status)
+    {
+        LOG_E("Phy device initialize unsuccessful!\n");
+        return ;
+    }

    while (1)
    {
-        bool new_link = false;
-        status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link);
+        rt_bool_t new_link = RT_FALSE;
+        rt_phy_status status = phy_dev->ops->get_link_status(&new_link);

-        if ((status == kStatus_Success) && (link != new_link))
+        if ((PHY_STATUS_OK == status) && (link != new_link))
        {
            link = new_link;

-            if (link)   // link up
+            if (link) // link up
            {
-                PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base,
-                                       PHY_ADDRESS, &speed, &duplex);
+                phy_dev->ops->get_link_speed_duplex(&speed, &duplex);

-                if (kPHY_Speed10M == speed)
+                if (PHY_SPEED_10M == speed)
                {
                    dbg_log(DBG_LOG, "10M\n");
                }
@@ -570,7 +586,7 @@ static void phy_monitor_thread_entry(void *parameter)
                    dbg_log(DBG_LOG, "100M\n");
                }

-                if (kPHY_HalfDuplex == duplex)
+                if (PHY_HALF_DUPLEX == duplex)
                {
                    dbg_log(DBG_LOG, "half dumplex\n");
                }
@@ -579,8 +595,7 @@ static void phy_monitor_thread_entry(void *parameter)
                    dbg_log(DBG_LOG, "full dumplex\n");
                }

-                if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed)
-                        || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
+                if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
                {
                    imxrt_eth_device.speed = (enet_mii_speed_t)speed;
                    imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex;
@@ -605,6 +620,7 @@ static void phy_monitor_thread_entry(void *parameter)
        rt_thread_delay(RT_TICK_PER_SECOND * 2);
    }
 }
+#endif

 static int rt_hw_imxrt_eth_init(void)
 {
@@ -657,6 +673,7 @@ static int rt_hw_imxrt_eth_init(void)

    /* start phy monitor */
    {
+        #ifdef BSP_USING_PHY
        rt_thread_t tid;
        tid = rt_thread_create("phy",
                               phy_monitor_thread_entry,
@@ -666,6 +683,7 @@ static int rt_hw_imxrt_eth_init(void)
                               2);
        if (tid != RT_NULL)
            rt_thread_startup(tid);
+        #endif
    }

    return state;
@@ -673,50 +691,47 @@ static int rt_hw_imxrt_eth_init(void)
 INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
 #endif

-#ifdef RT_USING_FINSH
+#if defined(RT_USING_FINSH) && defined(RT_USING_PHY)
 #include <finsh.h>

-void phy_read(uint32_t phyReg)
+void phy_read(rt_uint32_t phy_reg)
 {
-    uint32_t data;
-    status_t status;
+    rt_uint32_t data;

-    status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data);
-    if (kStatus_Success == status)
+    rt_phy_status status = phy_dev->ops->read(phy_reg, &data);
+    if (PHY_STATUS_OK == status)
    {
-        rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data);
+        rt_kprintf("PHY_Read: %02X --> %08X", phy_reg, data);
    }
    else
    {
-        rt_kprintf("PHY_Read: %02X --> faild", phyReg);
+        rt_kprintf("PHY_Read: %02X --> faild", phy_reg);
    }
 }

-void phy_write(uint32_t phyReg, uint32_t data)
+void phy_write(rt_uint32_t phy_reg, rt_uint32_t data)
 {
-    status_t status;
-
-    status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data);
-    if (kStatus_Success == status)
+    rt_phy_status status = phy_dev->ops->write(phy_reg, data);
+    if (PHY_STATUS_OK == status)
    {
-        rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data);
+        rt_kprintf("PHY_Write: %02X --> %08X\n", phy_reg, data);
    }
    else
    {
-        rt_kprintf("PHY_Write: %02X --> faild\n", phyReg);
+        rt_kprintf("PHY_Write: %02X --> faild\n", phy_reg);
    }
 }

 void phy_dump(void)
 {
-    uint32_t data;
-    status_t status;
+    rt_uint32_t data;
+    rt_phy_status status;

    int i;
    for (i = 0; i < 32; i++)
    {
-        status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data);
-        if (kStatus_Success != status)
+        status = phy_dev->ops->read(i, &data);
+        if (PHY_STATUS_OK != status)
        {
            rt_kprintf("phy_dump: %02X --> faild", i);
            break;
@@ -730,10 +745,11 @@ void phy_dump(void)
        {
            rt_kprintf("%02X --> %08X\n", i, data);
        }
-
    }
 }
+#endif

+#if defined(RT_USING_FINSH) && defined(RT_USING_LWIP)
 void enet_reg_dump(void)
 {
    ENET_Type *enet_base = imxrt_eth_device.enet_base;
@@ -0,0 +1,160 @@
+
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-09-29     WangQiang    the first version
+ *
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_PHY
+
+#define LOG_TAG "drv.mdio"
+#include <drv_log.h>
+
+#include <rtdevice.h>
+#include "drv_mdio.h"
+
+
+
+/*! @brief Defines the timeout macro. */
+#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
+
+/*!
+ * @brief Get the ENET instance from peripheral base address.
+ *
+ * @param base ENET peripheral base address.
+ * @return ENET instance.
+ */
+extern uint32_t ENET_GetInstance(ENET_Type *base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to enet clocks for each instance. */
+extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+static rt_bool_t rt_hw_mdio_init(void *bus, rt_uint32_t src_clock_hz)
+{
+    struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus;
+    uint32_t instance = ENET_GetInstance((ENET_Type *)(bus_obj->hw_obj));
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Set SMI first. */
+    CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    ENET_SetSMI((ENET_Type *)(bus_obj->hw_obj), src_clock_hz, RT_FALSE);
+
+    return RT_TRUE;
+}
+
+static rt_size_t rt_hw_mdio_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    RT_ASSERT(data);
+    struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus;
+
+    rt_uint32_t counter;
+    rt_uint32_t *data_ptr = (rt_uint32_t *)data;
+
+    if (4 != size)
+    {
+        return 0;
+    }
+
+    /* Clear the MII interrupt event. */
+    ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK);
+
+    /* Starts a SMI read command operation. */
+    ENET_StartSMIRead((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiReadValidFrame);
+
+    /* Wait for MII complete. */
+    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+    {
+        if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK)
+        {
+            break;
+        }
+    }
+
+    /* Check for timeout. */
+    if (!counter)
+    {
+        // return kStatus_PHY_SMIVisitTimeout;
+        return 0;
+    }
+
+    /* Get data from MII register. */
+    *data_ptr = ENET_ReadSMIData((ENET_Type *)(bus_obj->hw_obj));
+
+    /* Clear MII interrupt event. */
+    ENET_ClearInterruptStatus((ENET_Type *)bus_obj->hw_obj, ENET_EIR_MII_MASK);
+
+    return 4;
+}
+
+
+static rt_size_t rt_hw_mdio_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus;
+    uint32_t counter;
+    rt_uint32_t *data_ptr = (rt_uint32_t *)data;
+
+    if (4 != size)
+    {
+        return 0;
+    }
+
+    /* Clear the SMI interrupt event. */
+    ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK);
+
+    /* Starts a SMI write command. */
+    ENET_StartSMIWrite((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiWriteValidFrame, *data_ptr);
+
+    /* Wait for SMI complete. */
+    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+    {
+        if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK)
+        {
+            break;
+        }
+    }
+
+    /* Check for timeout. */
+    if (!counter)
+    {
+        return 0;
+    }
+
+    /* Clear MII interrupt event. */
+    ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK);
+
+    return size;
+}
+
+static struct rt_mdio_bus_ops imxrt_mdio_ops =
+{
+    .init = rt_hw_mdio_init,
+    .read = rt_hw_mdio_read,
+    .write = rt_hw_mdio_write,
+    .uninit = RT_NULL,
+};
+
+static rt_mdio_t mdio_bus;
+
+rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name)
+{
+    mdio_bus.hw_obj = hw_obj;
+    mdio_bus.name = name;
+    mdio_bus.ops = &imxrt_mdio_ops;
+    return &mdio_bus;
+}
+
+rt_mdio_t *rt_hw_mdio_get(void)
+{
+    return &mdio_bus;
+}
+
+#endif
@@ -0,0 +1,25 @@
+
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-09-29     WangQiang    the first version
+ *
+ */
+
+#ifndef DRV_MDIO_H__
+#define DRV_MDIO_H__
+
+#include <rtdevice.h>
+
+#include "fsl_enet.h"
+
+
+rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name);
+
+rt_mdio_t *rt_hw_mdio_get(void);
+
+#endif /*DRV_MDIO_H__*/
@@ -0,0 +1,16 @@
+from building import *
+
+src = []
+cwd = []
+CPPDEFINES = []
+
+cwd = GetCurrentDir()
+
+if GetDepend('BSP_USING_PHY') and GetDepend('PHY_USING_KSZ8081'):
+    src += ['phyksz8081.c']
+
+path = [cwd]
+
+group = DefineGroup('Peripherals', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES)
+
+Return('group')
@@ -21,3 +21,6 @@ def dist_do_building(BSP_ROOT, dist_dir=None):
    print("=> copy bsp drivers")
    bsp_copy_files(os.path.join(library_path, 'drivers'), os.path.join(library_dir, 'drivers'))
    shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
+
+    print("=> copy bsp peripherals")
+    bsp_copy_files(os.path.join(library_path, 'peripherals'), os.path.join(library_dir, 'peripherals'))
@@ -258,7 +258,7 @@ const static struct rt_pin_ops drv_pin_ops =
 int rt_hw_pin_init(void)
 {
    rt_err_t ret = RT_EOK;
-    memset(pin_alloc_table, 0, sizeof pin_alloc_table);
+    memset(pin_alloc_table, -1, sizeof pin_alloc_table);
    free_pin = GPIO_ALLOC_START;
    ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);

@@ -9,8 +9,10 @@ src = Split("""
 """)

 if GetDepend(['BSP_USING_UART']):
-    src += ['drv_uart.c']
-    
+    if GetDepend(['NRFX_USING_UART']):
+        src += ['drv_uart.c']
+    else:   
+        src += ['drv_uarte.c']   
 if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
    src += ['drv_flash.c']

@@ -6,6 +6,7 @@
 * Change Logs:
 * Date             Author          Notes
 * 2020-05-22       Sherman         first version
+ * 2020-11-02       xckhmf          fixed bug
 */

 #include <stdint.h>
@@ -19,6 +20,7 @@

 #ifdef BSP_USING_SPI

+#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2)
 static struct nrfx_drv_spi_config spi_config[] =
 {
 #ifdef BSP_USING_SPI0
@@ -117,12 +119,12 @@ static rt_err_t spi_configure(struct rt_spi_device *device,

    nrfx_spi_t spi = spi_bus_obj[index].spi;
    nrfx_spi_config_t config = NRFX_SPI_DEFAULT_CONFIG(bsp_spi_pin[index].sck_pin, 
-        bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, bsp_spi_pin[index].ss_pin);
+        bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, NRFX_SPI_PIN_NOT_USED);

    /* spi config ss pin */
-    if(device->user_data != RT_NULL)
+    if(device->parent.user_data != RT_NULL)
    {
-        config.ss_pin = (rt_uint8_t)device->user_data;
+        nrf_gpio_cfg_output((uint32_t)device->parent.user_data);
    }
    /* spi config bit order */
    if(configuration->mode & RT_SPI_MSB)
@@ -198,32 +200,43 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
    RT_ASSERT(device->bus->parent.user_data != RT_NULL);

    rt_uint8_t index = spi_index_find(device->bus);
+    nrfx_err_t nrf_ret;
    RT_ASSERT(index != 0xFF);

    nrfx_spi_t * p_instance =  &spi_bus_obj[index].spi;
    nrfx_spi_xfer_desc_t p_xfer_desc;
+
+    if(message->cs_take == 1)
+    {
+        nrf_gpio_pin_clear((uint32_t)device->parent.user_data);
+    }
+    p_xfer_desc.p_rx_buffer = message->recv_buf;
+    p_xfer_desc.rx_length = message->length;  
+    p_xfer_desc.p_tx_buffer = message->send_buf;
+    p_xfer_desc.tx_length = message->length ;
    if(message->send_buf == RT_NULL)
    {
-        p_xfer_desc.p_rx_buffer = message->recv_buf;
-        p_xfer_desc.rx_length = message->length;
-
-        p_xfer_desc.p_tx_buffer = RT_NULL;
        p_xfer_desc.tx_length = 0;
    }
+    if(message->recv_buf == RT_NULL)
+    {
+        p_xfer_desc.rx_length = 0;          
+    }
+
+    nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0);
+    if(message->cs_release == 1)
+    {
+        nrf_gpio_pin_set((uint32_t)device->parent.user_data);
+    }
+    
+    if( NRFX_SUCCESS != nrf_ret)
+    {
+        return 0;
+    }
    else
    {
-        p_xfer_desc.p_tx_buffer = message->send_buf;
-        p_xfer_desc.tx_length = message->length ;
-
-        p_xfer_desc.p_rx_buffer = RT_NULL;
-        p_xfer_desc.rx_length = 0;
+        return message->length;        
    }
-
-    nrfx_err_t nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0);
-    if( NRFX_SUCCESS == nrf_ret)
-        return message->length; 
-    else
-        return 0;
 }

 /* spi bus callback function  */
@@ -260,6 +273,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
 {
    RT_ASSERT(bus_name != RT_NULL);
    RT_ASSERT(device_name != RT_NULL);
+    RT_ASSERT(ss_pin != RT_NULL);

    rt_err_t result;
    struct rt_spi_device *spi_device;
@@ -267,8 +281,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
    spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
    RT_ASSERT(spi_device != RT_NULL);
    /* initialize the cs pin */
-    spi_device->user_data = (void*)ss_pin;
-    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, RT_NULL);
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void*)ss_pin);
    if (result != RT_EOK)
    {
        LOG_E("%s attach to %s faild, %d", device_name, bus_name, result);
@@ -278,4 +291,5 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
    return result;
 }

+#endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 */
 #endif /*BSP_USING_SPI*/
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-28     xckhmf       Modify for <nrfx>
+ * 2020-10-31     xckhmf       Support for UART1
+ *
+ */
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RT_DEVICE_CTRL_CUSTOM   0x20
+#define RT_DEVICE_CTRL_PIN      0x21
+#define RT_DEVICE_POWERSAVE     0x22
+#define RT_DEVICE_WAKEUP        0x23
+
+#define UART_CONFIG_BAUD_RATE_9600      1
+#define UART_CONFIG_BAUD_RATE_115200    2
+
+void rt_hw_uart_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_UART_H__ */
@@ -120,6 +120,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
@@ -195,15 +196,12 @@ CONFIG_RT_USING_LIBC=y
 #
 # IoT - internet of things
 #
-# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
-# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -230,7 +228,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
-# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -243,7 +240,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
@@ -265,7 +262,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
-# CONFIG_PKG_USING_NMEALIB is not set

 #
 # security packages
@@ -274,7 +270,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
-# CONFIG_PKG_USING_YD_CRYPTO is not set

 #
 # language packages
@@ -309,8 +304,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
-# CONFIG_PKG_USING_GPS_RMC is not set
-# CONFIG_PKG_USING_URLENCODE is not set

 #
 # system packages
@@ -321,7 +314,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -334,9 +326,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
-# CONFIG_PKG_USING_RAMDISK is not set
-# CONFIG_PKG_USING_MININI is not set
-# CONFIG_PKG_USING_QBOOT is not set

 #
 # peripheral libraries and drivers
@@ -378,7 +367,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
-# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
@@ -386,11 +374,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_BEEP is not set
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
-# CONFIG_PKG_USING_CAN_YMODEM is not set
-# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
-# CONFIG_PKG_USING_QLED is not set
-# CONFIG_PKG_USING_PAJ7620 is not set
-# CONFIG_PKG_USING_AGILE_CONSOLE is not set

 #
 # miscellaneous packages
@@ -427,31 +410,36 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
-# CONFIG_PKG_USING_CRCLIB is not set

 #
 # Hardware Drivers Config
 #
 CONFIG_SOC_NRF52832=y
+CONFIG_NRFX_CLOCK_ENABLED=1
+CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
+CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
 CONFIG_SOC_NORDIC=y

 #
 # Onboard Peripheral Drivers
 #
 # CONFIG_BSP_USING_JLINK_TO_USART is not set
-# CONFIG_BSP_USING_QSPI_FLASH is not set

 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
+CONFIG_NRFX_GPIOTE_ENABLED=1
+# CONFIG_BSP_USING_SAADC is not set
 # CONFIG_BSP_USING_PWM is not set
-# CONFIG_BSP_USING_SOFTDEVICE is not set
 CONFIG_BSP_USING_UART=y
+CONFIG_NRFX_USING_UART=y
+# CONFIG_NRFX_USING_UARTE is not set
+CONFIG_NRFX_UART_ENABLED=1
 CONFIG_BSP_USING_UART0=y
+CONFIG_NRFX_UART0_ENABLED=1
 CONFIG_BSP_UART0_RX_PIN=8
 CONFIG_BSP_UART0_TX_PIN=6
-# CONFIG_BSP_USING_UART1 is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ON_CHIP_FLASH is not set

@@ -463,3 +451,8 @@ CONFIG_MCU_FLASH_SIZE_KB=1024
 CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
 CONFIG_MCU_SRAM_SIZE_KB=256
 CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+CONFIG_BLE_STACK_USING_NULL=y
+# CONFIG_BSP_USING_SOFTDEVICE is not set
+# CONFIG_BSP_USING_NIMBLE is not set
@@ -157,12 +157,24 @@ menu "On-chip Peripheral Drivers"
        endif

    
-    menuconfig BSP_USING_UART
-        bool "Enable UART"
+    config BSP_USING_UART
+		bool "Enable UART"
        default y
        select RT_USING_SERIAL
-
-        if BSP_USING_UART
+		if BSP_USING_UART
+		choice
+		prompt "UART or UARTE"
+		default NRFX_USING_UART
+		help
+			Select the UART or UARTE
+		config NRFX_USING_UART
+			bool "UART"
+		
+		config NRFX_USING_UARTE
+			bool "UARTE"
+		endchoice
+		endif
+        if BSP_USING_UART&&NRFX_USING_UART
            config NRFX_UART_ENABLED
            int 
            default 1
@@ -183,9 +195,28 @@ menu "On-chip Peripheral Drivers"
                        range 0 31
                        default 6
                endif
-            config BSP_USING_UART1
-                bool "Enable UART1"
-                default n
+        endif
+        if BSP_USING_UART&&NRFX_USING_UARTE
+            config NRFX_UARTE_ENABLED
+            int 
+            default 1
+
+            config BSP_USING_UART0
+                bool "Enable UARTE0"
+                default n 
+                if BSP_USING_UART0
+                    config NRFX_UARTE0_ENABLED
+                    int 
+                    default 1
+                    config BSP_UART0_RX_PIN
+                        int "uarte0 rx pin number"
+                        range 0 31
+                        default 8
+                    config BSP_UART0_TX_PIN
+                        int "uarte0 tx pin number"
+                        range 0 31
+                        default 6
+                endif
        endif

    config BSP_USING_SPI
@@ -152,6 +152,9 @@
 /* Hardware Drivers Config */

 #define SOC_NRF52832
+#define NRFX_CLOCK_ENABLED 1
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
 #define SOC_NORDIC

 /* Onboard Peripheral Drivers */
@@ -160,8 +163,12 @@
 /* On-chip Peripheral Drivers */

 #define BSP_USING_GPIO
+#define NRFX_GPIOTE_ENABLED 1
 #define BSP_USING_UART
+#define NRFX_USING_UART
+#define NRFX_UART_ENABLED 1
 #define BSP_USING_UART0
+#define NRFX_UART0_ENABLED 1
 #define BSP_UART0_RX_PIN 8
 #define BSP_UART0_TX_PIN 6

@@ -172,5 +179,6 @@
 #define MCU_SRAM_START_ADDRESS 0x20000000
 #define MCU_SRAM_SIZE_KB 256
 #define MCU_FLASH_PAGE_SIZE 0x1000
+#define BLE_STACK_USING_NULL

 #endif
@@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
 CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -120,6 +120,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
@@ -195,15 +196,12 @@ CONFIG_RT_USING_LIBC=y
 #
 # IoT - internet of things
 #
-# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
-# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -230,7 +228,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
-# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -243,7 +240,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
@@ -273,7 +270,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
-# CONFIG_PKG_USING_YD_CRYPTO is not set

 #
 # language packages
@@ -308,7 +304,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
-# CONFIG_PKG_USING_URLENCODE is not set

 #
 # system packages
@@ -319,7 +314,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -332,8 +326,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
-# CONFIG_PKG_USING_RAMDISK is not set
-# CONFIG_PKG_USING_MININI is not set

 #
 # peripheral libraries and drivers
@@ -353,8 +345,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
 # CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRF5X_SDK_V1300 is not set
-# CONFIG_PKG_USING_NRF5X_SDK_LATEST_VERSION is not set
 CONFIG_PKG_USING_NRFX=y
 CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
 CONFIG_PKG_USING_NRFX_V210=y
@@ -384,10 +374,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_BEEP is not set
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
-# CONFIG_PKG_USING_CAN_YMODEM is not set
-# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
-# CONFIG_PKG_USING_QLED is not set
-# CONFIG_PKG_USING_PAJ7620 is not set

 #
 # miscellaneous packages
@@ -429,6 +415,10 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # Hardware Drivers Config
 #
 CONFIG_SOC_NRF52840=y
+CONFIG_NRFX_CLOCK_ENABLED=1
+CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
+CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
+CONFIG_SOC_NORDIC=y

 #
 # Onboard Peripheral Drivers
@@ -440,12 +430,17 @@ CONFIG_SOC_NRF52840=y
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
-# CONFIG_BSP_USING_SOFTDEVICE is not set
+CONFIG_NRFX_GPIOTE_ENABLED=1
+# CONFIG_BSP_USING_SAADC is not set
+# CONFIG_BSP_USING_PWM is not set
 CONFIG_BSP_USING_UART=y
+CONFIG_NRFX_USING_UART=y
+# CONFIG_NRFX_USING_UARTE is not set
+CONFIG_NRFX_UART_ENABLED=1
 CONFIG_BSP_USING_UART0=y
+CONFIG_NRFX_UART0_ENABLED=1
 CONFIG_BSP_UART0_RX_PIN=8
 CONFIG_BSP_UART0_TX_PIN=6
-# CONFIG_BSP_USING_UART1 is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ON_CHIP_FLASH is not set

@@ -457,3 +452,8 @@ CONFIG_MCU_FLASH_SIZE_KB=1024
 CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
 CONFIG_MCU_SRAM_SIZE_KB=256
 CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+CONFIG_BLE_STACK_USING_NULL=y
+# CONFIG_BSP_USING_SOFTDEVICE is not set
+# CONFIG_BSP_USING_NIMBLE is not set
@@ -194,12 +194,24 @@ menu "On-chip Peripheral Drivers"
        endif

    
-    menuconfig BSP_USING_UART
-        bool "Enable UART"
+    config BSP_USING_UART
+		bool "Enable UART"
        default y
        select RT_USING_SERIAL
-
-        if BSP_USING_UART
+		if BSP_USING_UART
+		choice
+		prompt "UART or UARTE"
+		default NRFX_USING_UART
+		help
+			Select the UART or UARTE
+		config NRFX_USING_UART
+			bool "UART"
+		
+		config NRFX_USING_UARTE
+			bool "UARTE"
+		endchoice
+		endif
+        if BSP_USING_UART&&NRFX_USING_UART
            config NRFX_UART_ENABLED
            int 
            default 1
@@ -220,9 +232,44 @@ menu "On-chip Peripheral Drivers"
                        range 0 31
                        default 6
                endif
+        endif
+        if BSP_USING_UART&&NRFX_USING_UARTE
+            config NRFX_UARTE_ENABLED
+            int 
+            default 1
+
+            config BSP_USING_UART0
+                bool "Enable UARTE0"
+                default n 
+                if BSP_USING_UART0
+                    config NRFX_UARTE0_ENABLED
+                    int 
+                    default 1
+                    config BSP_UART0_RX_PIN
+                        int "uarte0 rx pin number"
+                        range 0 31
+                        default 8
+                    config BSP_UART0_TX_PIN
+                        int "uarte0 tx pin number"
+                        range 0 31
+                        default 6
+                endif
            config BSP_USING_UART1
-                bool "Enable UART1"
-                default n
+                bool "Enable UARTE1"
+                default n 
+                if BSP_USING_UART1
+                    config NRFX_UARTE1_ENABLED
+                    int 
+                    default 1
+                    config BSP_UART1_RX_PIN
+                        int "uarte1 rx pin number"
+                        range 0 31
+                        default 7
+                    config BSP_UART1_TX_PIN
+                        int "uarte1 tx pin number"
+                        range 0 31
+                        default 5
+                endif
        endif

    config BSP_USING_SPI
@@ -152,6 +152,10 @@
 /* Hardware Drivers Config */

 #define SOC_NRF52840
+#define NRFX_CLOCK_ENABLED 1
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#define SOC_NORDIC

 /* Onboard Peripheral Drivers */

@@ -159,8 +163,12 @@
 /* On-chip Peripheral Drivers */

 #define BSP_USING_GPIO
+#define NRFX_GPIOTE_ENABLED 1
 #define BSP_USING_UART
+#define NRFX_USING_UART
+#define NRFX_UART_ENABLED 1
 #define BSP_USING_UART0
+#define NRFX_UART0_ENABLED 1
 #define BSP_UART0_RX_PIN 8
 #define BSP_UART0_TX_PIN 6

@@ -171,5 +179,6 @@
 #define MCU_SRAM_START_ADDRESS 0x20000000
 #define MCU_SRAM_SIZE_KB 256
 #define MCU_FLASH_PAGE_SIZE 0x1000
+#define BLE_STACK_USING_NULL

 #endif
@@ -134,6 +134,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_DFS_UFFS is not set
 # CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set

 #
 # Device Drivers
@@ -208,17 +209,79 @@ CONFIG_RT_USING_POSIX=y
 #
 # Network interface device
 #
-# CONFIG_RT_USING_NETDEV is not set
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set

 #
 # light weight TCP/IP stack
 #
-# CONFIG_RT_USING_LWIP is not set
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP212 is not set
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+# CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_RT_LWIP_DEBUG is not set

 #
 # AT commands
 #
 # CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set

 #
 # VBUS(Virtual Software BUS)
@@ -497,6 +560,8 @@ CONFIG_RT_USING_POSIX=y
 #
 # Network Utilities
 #
+# CONFIG_PKG_USING_MDNS is not set
+# CONFIG_PKG_USING_UPNP is not set
 # CONFIG_PKG_USING_WICED is not set
 # CONFIG_PKG_USING_CLOUDSDK is not set
 # CONFIG_PKG_USING_POWER_MANAGER is not set
@@ -128,6 +128,7 @@ msh />
 | WATCHDOG | 支持 | - |
 | HDMI | 支持 | - |
 | SDIO | 支持 | - |
+| ETH | 支持 | - |

 ## 5. 注意事项

@@ -19,8 +19,9 @@

 struct mem_desc platform_mem_desc[] = {
    {0x0, 0x6400000, 0x0, NORMAL_MEM},
-    {0x8000000, 0x8100000, 0x8000000, DEVICE_MEM},    //mbox msg
+    {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM},    //mbox msg
    {0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer
+    {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
    {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral
    {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM}  //gic
 };
@@ -122,9 +122,57 @@

 /* Network interface device */

+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0

 /* light weight TCP/IP stack */

+#define RT_USING_LWIP
+#define RT_USING_LWIP202
+#define RT_LWIP_MEM_ALIGNMENT 4
+#define RT_LWIP_IGMP
+#define RT_LWIP_ICMP
+#define RT_LWIP_DNS
+#define RT_LWIP_DHCP
+#define IP_SOF_BROADCAST 1
+#define IP_SOF_BROADCAST_RECV 1
+
+/* Static IPv4 Address */
+
+#define RT_LWIP_IPADDR "192.168.1.30"
+#define RT_LWIP_GWADDR "192.168.1.1"
+#define RT_LWIP_MSKADDR "255.255.255.0"
+#define RT_LWIP_UDP
+#define RT_LWIP_TCP
+#define RT_LWIP_RAW
+#define RT_MEMP_NUM_NETCONN 8
+#define RT_LWIP_PBUF_NUM 16
+#define RT_LWIP_RAW_PCB_NUM 4
+#define RT_LWIP_UDP_PCB_NUM 4
+#define RT_LWIP_TCP_PCB_NUM 4
+#define RT_LWIP_TCP_SEG_NUM 40
+#define RT_LWIP_TCP_SND_BUF 8196
+#define RT_LWIP_TCP_WND 8196
+#define RT_LWIP_TCPTHREAD_PRIORITY 10
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_PRIORITY 12
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#define LWIP_NETIF_LINK_CALLBACK 1
+#define SO_REUSE 1
+#define LWIP_SO_RCVTIMEO 1
+#define LWIP_SO_SNDTIMEO 1
+#define LWIP_SO_RCVBUF 1
+#define LWIP_SO_LINGER 0
+#define LWIP_NETIF_LOOPBACK 0
+#define RT_LWIP_USING_PING

 /* AT commands */

@@ -0,0 +1,17 @@
+from building import *
+import rtconfig
+
+cwd = GetCurrentDir()
+src	= Glob('*.c')
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += ['startup_gcc/startup_m2sxxx.S']
+    
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += ['startup_arm/startup_m2sxxx.s']
+
+CPPPATH = [cwd]
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,113 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
+ *
+ *  SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
+ *  Access Layer.
+ *
+ *  This file provides interfaces to perform register and register bit level 
+ *  read / write operations. These interfaces support bit-banding in case of 
+ *  Cortex-M3 CPU.
+ *
+ * SVN $Revision: 5263 $
+ * SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $
+ */
+
+#ifndef HW_REG_IO_H_
+#define HW_REG_IO_H_
+
+#include <stdint.h>                       /* Include standard types */
+
+#if defined ( __CC_ARM   )
+  #define __INLINE         __inline       /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __INLINE        inline          /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __INLINE        inline          /*!< inline keyword for GNU Compiler       */
+#endif
+
+/*****************************************************************************************
+ * Definitions for register access
+ */
+
+#define HW_REG(addr)            (*((volatile uint32_t *) (addr)))
+
+static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)
+{
+    HW_REG(reg) = val;
+}
+static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)
+{
+    HW_REG(reg) = val;
+}
+static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)
+{
+    HW_REG(reg) = val;
+}
+
+static __INLINE uint32_t read_reg32(volatile uint32_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+static __INLINE uint16_t read_reg16(volatile uint16_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+static __INLINE uint8_t read_reg8(volatile uint8_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+/*****************************************************************************************
+ * Definitions for register bits access using bit-band aliases for Cortex-M3 
+ */
+#define BITBAND(addr,bitnum)    (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))
+#define HW_REG_BIT(reg,bitnum)  (*(volatile unsigned int *)((BITBAND(reg,bitnum))))
+
+/*****************************************************************************************
+ * Functions to set a bit field in Cortex-M3 
+ */
+static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+/*****************************************************************************************
+ * Functions to clear a bit field in Cortex-M3
+ */
+static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+/*****************************************************************************************
+ * Functions to read a bit field in Cortex-M3
+ */
+static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+
+#endif /* HW_REG_IO_H_ */
@@ -0,0 +1,62 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Assertion implementation.
+ *
+ * This file provides the implementation of the ASSERT macro. This file can be
+ * modified to cater for project specific requirements regarding the way
+ * assertions are handled.
+ *
+ * SVN $Revision: 6422 $
+ * SVN $Date: 2014-05-14 14:37:56 +0100 (Wed, 14 May 2014) $
+ */
+#ifndef __MSS_ASSERT_H_
+#define __MSS_ASSERT_H_
+
+#if defined(NDEBUG)
+
+#define ASSERT(CHECK)
+
+#else   /* NDEBUG */
+
+#include <assert.h>
+
+#if defined ( __GNUC__   )
+
+/*
+ * SoftConsole assertion handling
+ */
+#define ASSERT(CHECK)  \
+    do { \
+        if (!(CHECK)) \
+        { \
+            __asm volatile ("BKPT\n\t"); \
+        } \
+    } while (0);
+    
+#elif defined ( __ICCARM__ )
+/*
+ * IAR Embedded Workbench assertion handling.
+ * Call C library assert function which should result in error message
+ * displayed in debugger.
+ */
+#define ASSERT(X)   assert(X)
+
+#else
+/*
+ * Keil assertion handling.
+ * Call C library assert function which should result in error message
+ * displayed in debugger.
+ */
+
+#ifndef __MICROLIB
+  #define ASSERT(X)   assert(X)
+#else
+  #define ASSERT(X)
+#endif
+
+#endif  /* Tool Chain */
+
+#endif  /* NDEBUG */
+
+#endif  /* __MSS_ASSERT_H_ */
@@ -0,0 +1,44 @@
+/*******************************************************************************
+ * (c) Copyright 2014 Microsemi SoC Products Group. All rights reserved.
+ *
+ *  Keil-MDK specific system initialization.
+ *
+ * SVN $Revision: 7375 $
+ * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
+ */
+#ifdef MSCC_NO_RELATIVE_PATHS
+#include "m2sxxx.h"
+#else
+#include "..\m2sxxx.h"
+#endif
+
+#define ENVM_BASE_ADDRESS       0x60000000U
+#define MDDR_BASE_ADDRESS       0xA0000000U
+
+//extern unsigned int Image$$ER_RW$$Base;
+//extern unsigned int Image$$ER_RO$$Base;
+
+/*==============================================================================
+ * The __low_level_init() function is called after SystemInit. Therefore, the
+ * external RAM should be configured at this stage if it is used.
+ */
+/* void low_level_init(void)
+{
+    volatile unsigned int rw_region_base;
+    volatile unsigned int readonly_region_base;
+    
+    rw_region_base = (unsigned int)&Image$$ER_RW$$Base;
+    if (rw_region_base >= MDDR_BASE_ADDRESS)
+    {
+        / --------------------------------------------------------------------------
+         * Remap MDDR to address 0x00000000.
+         /
+        SYSREG->ESRAM_CR = 0u;
+        SYSREG->ENVM_REMAP_BASE_CR = 0u;
+        SYSREG->DDR_CR = 1u;
+    }
+    
+    readonly_region_base = (unsigned int)&Image$$ER_RO$$Base;
+    SCB->VTOR = readonly_region_base;
+}  */
+
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * (c) Copyright 2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * Redirection of the standard library I/O to one of the SmartFusion2
+ * MMUART.
+ *
+ * SVN $Revision: 7375 $
+ * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
+ */
+
+/*==============================================================================
+ * The content of this source file will only be compiled if either one of the
+ * following two defined symbols are defined in the project settings:
+ *  - MICROSEMI_STDIO_THRU_MMUART0
+ *  - MICROSEMI_STDIO_THRU_MMUART1
+ *
+ */
+#ifdef MICROSEMI_STDIO_THRU_MMUART0
+#ifndef MICROSEMI_STDIO_THRU_UART
+#define MICROSEMI_STDIO_THRU_UART
+#endif
+#endif  /* MICROSEMI_STDIO_THRU_MMUART0 */
+
+#ifdef MICROSEMI_STDIO_THRU_MMUART1
+#ifndef MICROSEMI_STDIO_THRU_UART
+#define MICROSEMI_STDIO_THRU_UART
+#endif
+#endif  /* MICROSEMI_STDIO_THRU_MMUART1 */
+
+/*==============================================================================
+ * Actual implementation.
+ */
+#ifdef MICROSEMI_STDIO_THRU_UART
+
+#include <stdio.h>
+#include <rt_misc.h>
+
+#include "m2sxxx.h"
+#include "mss_uart.h"
+#include "core_uart_apb.h"
+
+
+/*
+ * The baud rate will default to 57600 baud if no baud rate is specified though the
+ * MICROSEMI_STDIO_BAUD_RATE define.
+ */
+#ifndef MICROSEMI_STDIO_BAUD_RATE
+#define MICROSEMI_STDIO_BAUD_RATE  MSS_UART_115200_BAUD
+#endif
+
+#ifdef MICROSEMI_STDIO_THRU_MMUART0
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
+#else
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;
+#endif
+
+/*==============================================================================
+ * Flag used to indicate if the UART driver needs to be initialized.
+ */
+static int g_stdio_uart_init_done = 0;
+
+
+#define LSR_THRE_MASK   0x20u
+
+/*
+ * Disable semihosting apis
+ */
+#pragma import(__use_no_semihosting_swi)
+
+/*==============================================================================
+ * sendchar()
+ */
+int sendchar(int ch)  
+{
+    uint32_t tx_ready;
+	//第一次调用时，初始化串口
+    if(!g_stdio_uart_init_done)
+    {
+        MSS_UART_init(gp_my_uart,
+                      MICROSEMI_STDIO_BAUD_RATE,
+                      MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);
+        g_stdio_uart_init_done = 1;
+    }
+    do {
+        tx_ready = gp_my_uart->hw_reg->LSR & LSR_THRE_MASK;
+    } while(!tx_ready);
+    gp_my_uart->hw_reg->THR = ch;
+    return (ch);
+}
+
+/*==============================================================================
+ * 
+ */
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+/*==============================================================================
+ * fputc()
+ */
+int fputc(int ch, FILE *f)
+{
+  return (sendchar(ch));
+}
+
+/*==============================================================================
+ * fgetc()
+ */
+int fgetc(FILE *f)
+{
+    uint8_t rx_size;
+    uint8_t rx_byte;
+    
+    do {
+        rx_size = MSS_UART_get_rx(gp_my_uart, &rx_byte, 1);
+    } while(0u == rx_size);
+
+    return rx_byte;
+}
+
+/*==============================================================================
+ * ferror()
+ */
+int ferror(FILE *f)
+{
+  /* Your implementation of ferror */
+  return EOF;
+}
+
+/*==============================================================================
+ * _ttywrch()
+ */
+void _ttywrch(int ch)
+{
+  sendchar(ch);
+}
+
+/*==============================================================================
+ * _sys_exit()
+ */
+void _sys_exit(int return_code)
+{
+    for(;;)
+    {
+        ;  /* endless loop */
+    }
+}
+
+#endif  /* MICROSEMI_STDIO_THRU_UART */
@@ -0,0 +1,49 @@
+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for debugging code executing in internal eSRAM.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+RAM_LOAD 0x20000000 0x10000
+{
+    ;   First half of RAM allocated to RO Execute and data
+    ER_RO 0x20000000 0x8000
+    {
+       *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+    ;   Heap size is defined in startup_m2sxxx.s
+    ;   Heap will be added after RW data in ER_RW unless explicitly 
+    ;   allocated a meemory region in .sct file
+    ;   Stack size is defined in startup_m2sxxx.s
+    ;   Stack will be added after heap in ER_RW unless explicitly 
+    ;   allocated a memory region in .sct file
+    ;   Second half of RAM allocated to RW data, heap and stack
+    ER_RW 0x20008000 0x8000
+    {
+        .ANY (+RW +ZI)
+    }
+}
+
@@ -0,0 +1,48 @@
+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for executing code in internal eNVM.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+FLASH_LOAD 0x00000000 0x40000		
+{
+;   All R only code/data is located in ENVM
+    ER_RO 0x00000000 0x40000
+    {
+       	*.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+;   Heap size is defined in startup_m2sxxx.s
+;   Heap will be added after RW data in ER_RW unless explicitly 
+;   allocated a meemory region in .sct file
+;   Stack size is defined in startup_m2sxxx.s
+;   Stack will be added after heap in ER_RW unless explicitly 
+;   allocated a memory region in .sct file
+    ER_RW 0x20000000 0x10000
+    {
+        .ANY (+RW +ZI)
+    }
+}
+
@@ -0,0 +1,54 @@
+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for debugging code executing in external MDDR.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+; Extern RAM 64M in total
+; allocate 1/2 to progam, 1/2 to variable data
+RAM_LOAD 0x00000000 0x04000000
+{
+;   Total = 64MB (lowest common amount accross dev kits) 32MB - First half of external memory allocated to RO Code
+    ER_RO 0x00000000 0x02000000
+    {
+       *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+    ;   Heap size is defined in startup_m2sxxx.s
+    ;   Heap will be added after RW data in ER_RW unless explicitly 
+    ;   allocated a meemory region in .sct file
+    ;   Stack size is defined in startup_m2sxxx.s
+    ;   Stack will be added after heap in ER_RW unless explicitly 
+    ;   allocated a memory region in .sct file as is the case below
+    STACKS 0x20000000 UNINIT
+    {
+        startup_m2sxxx.o (STACK)
+    }
+;   32 MB- Second half of external memory allocated to RW data
+    ER_RW 0xA2000000 0x02000000
+    {
+        .ANY (+RW +ZI)
+    }
+}
@@ -0,0 +1,74 @@
+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for relocating code to external RAM.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+FLASH_LOAD 0x60000000 0x40000
+{
+;   All code required on start-up located here before relocation has occured
+    ER_RO 0x60000000 0x40000
+    {
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        startup_m2sxxx.o
+        system_m2sxxx.o
+        sys_config.o
+        low_level_init.o
+	sys_config_SERDESIF_?.o
+	mscc_post_hw_cfg_init.o			
+    	ecc_error_handler.o		
+    }
+    ;   MDDR_RAM 0xA0000000 0x4000000  	
+    ;   -MDDR is mapped to address space from 0 on startup
+    ;   This allows the use of cache which is restriced to this area.
+    ;   Code is copied to RAM_EXEC space on startup by boot code.
+    RAM_EXEC 0x00000000 0x00040000	
+    {
+        .ANY (+RO)
+    }
+    ;   Heap size is defined in startup_m2sxxx.s
+    ;   Heap will be added after RW data in ER_RW unless explicitly 
+    ;   allocated a meemory region in .sct file
+    ;   Stack size is defined in startup_m2sxxx.s
+    ;   Stack will be added after heap in ER_RW unless explicitly 
+    ;   allocated a memory region in .sct file as is the case below
+    STACKS 0x20000000 UNINIT
+    {
+        startup_m2sxxx.o (STACK)
+    }
+;    All internal RAM has been allocatd to the stack
+;    INTERNAL_RAM 0x20008000 0x10000
+;    {
+;        .ANY (+RW +ZI)
+;    }
+
+;    MDDR_RAM 0xA0000000 0x4000000  So use top half of this for RW data
+;    Bottom half has been assigned to R only code already
+    ER_RW 0xA2000000 0x2000000
+    {
+        .ANY (+RW +ZI)
+    }
+}
+
@@ -0,0 +1,49 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  SmartFusion2 CMSIS system initialization.
+ *
+ * SVN $Revision: 5280 $
+ * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
+ */
+
+#ifndef SYSTEM_M2SXXX_H
+#define SYSTEM_M2SXXX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* Standard CMSIS global variables. */
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */
+
+/* SmartFusion2 specific clocks. */
+extern uint32_t g_FrequencyPCLK0;   /*!< Clock frequency of APB bus 0. */  
+extern uint32_t g_FrequencyPCLK1;   /*!< Clock frequency of APB bus 1. */
+extern uint32_t g_FrequencyPCLK2;   /*!< Clock frequency of APB bus 2. */
+extern uint32_t g_FrequencyFIC0;    /*!< Clock frequecny of FPGA fabric interface controller 1. */
+extern uint32_t g_FrequencyFIC1;    /*!< Clock frequecny of FPGA fabric inteface controller 2. */
+extern uint32_t g_FrequencyFIC64;   /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
+
+
+/***************************************************************************//**
+ * The SystemInit() is a standard CMSIS function called during system startup.
+ * It is meant to perform low level hardware setup such as configuring DDR and
+ * SERDES controllers.
+ */
+void SystemInit(void);
+
+/***************************************************************************//**
+ * The SystemCoreClockUpdate() is a standard CMSIS function which can be called
+ * by the application in order to ensure that the SystemCoreClock global
+ * variable contains the up to date Cortex-M3 core frequency. Calling this
+ * function also updates the global variables containing the frequencies of the
+ * APB busses connecting the peripherals.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "drivers/Kconfig"
+
+config SOC_SF2_M2S010
+    bool 
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
@@ -0,0 +1,102 @@
+## 移植RT-Thread到Microsemi SmartFusion2系列FPGA芯片
+
+### 1. BSP简介
+
+移植 RT-Thread 操作系统到一款 **FPGA 芯片——M2S010** ，该芯片属于 [Microsemi](https://www.microsemi.com/)（现Microchip）SmartFusion2系列，是一款**智能混合型FPGA**，片上除了 FPGA Fabric 逻辑部分，还包括一个 **ARM® Cortex™-M3 内核的 MCU**，主频最高 166MHz ，256KB eNVM，64KB eSRAM，集成GPIO、UART、I2C、SPI、CAN、USB等基本外设。
+
+> 关于 Microsemi，第三大 FPGA 厂商，原 Actel 半导体，2010 年，Microsemi 收购 Actel，2018 年， Microchip 收购 Microsemi。
+
+SmartFusion2 内部框图
+
+![Microsemi_Smartfusion2_BD](figures/Microsemi_Smartfusion2_BD.jpg)
+
+### 2. 外设支持
+
+移植了 RT-Thread 内核，支持线程调度、线程间同步和通信等，目前已经完成了PIN、Serial设备驱动，FinSH组件默认使用uart0设备。
+
+| **片上外设**      | **支持情况** |
+| :----------------- | :----------: |
+| GPIO              |     支持     |
+| UART              |     支持     |
+| SPI               |   暂不支持    |
+| I2C               |   暂不支持    |
+| RTC               |   暂不支持   |
+| USB        |   暂不支持   |
+
+### 3. scons构建系统
+
+通过加入`rtconfig.py`，`SConstruct`，`SConscript`文件，可支持scons构建系统，可以输入`scons`调用env工具中包含的arm-gcc编译器构建工程，支持以下scons命令：
+
+- `scons`：使用arm-gcc编译BSP
+- `scons -c`：清除执行 scons 时生成的临时文件和目标文件。
+- `scons --target=mdk4`：重新生成Keil MDK4环境下的工程。
+- `scons --target=mdk5`：重新生成Keil MDK5环境下的工程。
+- `scons --dist`：打包BSP工程，包括RT-Thread源码及BSP相关工程文件。
+
+添加Kconfig文件，用于生成rtconfig.h。
+
+### 4. 使用说明
+
+#### 4.1 FPGA 工程设计 
+
+FPGA 部分使用 SmartDesign 图形化设计，不需要写 HDL 代码，时钟来自外部 50M 晶体输入，PLL 倍频 100M 提供给 MCU 使用，顶层配置如下图所示：
+
+![](figures/top_sd.jpg)
+
+MSS 部分仅使用到了GPIO 和UART，GPIO_0配置成输出输出模式用于驱动LED。
+
+配置完成的 FPGA 工程文件下载：[sf2_fpga_prj.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/sf2_fpga_prj.rar)
+
+#### 4.2 ARM 程序设计
+
+ARM 程序使用 Keil MDK 5.26 开发，需要安装 M2S 系列芯片支持包：[Microsemi.M2Sxxx.1.0.64.pack](http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack)
+
+如果官网下载失败，可以到以下地址下载：[Microsemi.M2Sxxx.1.0.64.pack](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi.M2Sxxx.1.0.64.pack)
+
+在官方生成的示例工程目录下，添加 RT-Thread 相关组件，并实现一些对接函数，最终的文件结构：
+
+![](figures/files.jpg)
+
+### 5. 下载和运行
+
+为了能使用 ARM 调试器连接到 ARM 内核，而不是 FPGA，需要把 JTAG_SEL 引脚置为低电平。使用 ARM 调试器，如 JLink，对应连接 JTAG 口的 TMS、TCK、GND 引脚，如果连接正常，可以检测到 ARM 芯片，如下图所示：
+
+![](figures/jlink-ob.jpg)
+
+配置对应的 Flash 编程算法：
+
+![](figures/flash.jpg)
+
+下载完成：
+
+![](figures/finished.jpg)
+
+如果编译 & 烧写无误，下载完成或者按下复位按键之后，会在串口上看到 RT-Thread 的启动 LOG 信息：
+
+```c
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Jun  2 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh >
+```
+
+![](figures/log.jpg)
+
+### 6. 注意事项
+
+- FPGA 开发环境基于 Libero V11.8.2.4，向上兼容，不支持低版本 IDE。
+- ARM 开发环境基于 Keil MDK 5.26，如果使用SoftConsole IDE ，需要修改 `libcpu` 内的文件。
+- 调试内部 ARM 核，需要把 JTAG_SEL 拉低，否则调试器连接不上。 
+- 使用 SoftConsole 开发环境可以直接使用官方的 Flash Pro 调试器进行 ARM 程序的调试。
+- 内核时钟需要和 FPGA 中 MSS 配置的对应，Libero 自动生成的时钟文件，可以直接替换`bsp\smartfusion2\libraries\sys_config`文件夹下的文件 。
+
+### 7. 参考资料
+
+- [学习路线 - RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+- [Microsemi Libero系列中文教程](https://blog.csdn.net/whik1194/article/details/102901710)
+
+### 8. 联系我
+
+- Github：[whik](https://github.com/whik)
+- E-Mail：wangchao149@foxmail.com
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,35 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,10 @@
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+src	= Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN 0
+
+int main(void)
+{
+    int count = 1;
+
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while(count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    
+    return RT_EOK;
+}
@@ -0,0 +1,10 @@
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+src	= Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+ 
+#include <stdint.h>
+#include <rthw.h>
+#include <rtthread.h>
+
+#define _SCB_BASE       (0xE000E010UL)
+#define _SYSTICK_CTRL   (*(rt_uint32_t *)(_SCB_BASE + 0x0))
+#define _SYSTICK_LOAD   (*(rt_uint32_t *)(_SCB_BASE + 0x4))
+#define _SYSTICK_VAL    (*(rt_uint32_t *)(_SCB_BASE + 0x8))
+#define _SYSTICK_CALIB  (*(rt_uint32_t *)(_SCB_BASE + 0xC))
+#define _SYSTICK_PRI    (*(rt_uint8_t  *)(0xE000ED23UL))
+
+extern void SystemCoreClockUpdate(void);
+extern uint32_t SystemCoreClock;
+
+static uint32_t _SysTick_Config(rt_uint32_t ticks)
+{
+    if ((ticks - 1) > 0xFFFFFF)
+    {
+        return 1;
+    }
+    
+    _SYSTICK_LOAD = ticks - 1; 
+    _SYSTICK_PRI = 0xFF;
+    _SYSTICK_VAL  = 0;
+    _SYSTICK_CTRL = 0x07;  
+    
+    return 0;
+}
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+#define RT_HEAP_SIZE 1024
+static uint32_t rt_heap[RT_HEAP_SIZE];     // heap default size: 4K(1024 * 4)
+RT_WEAK void *rt_heap_begin_get(void)
+{
+    return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+    return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+/* This function will initial your board. */
+void rt_hw_board_init()
+{
+    /* System Clock Update */
+    SystemCoreClockUpdate();
+    
+    /* System Tick Configuration */
+    _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+    
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+}
+
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+#include "config.h"
+
+/* hardware initialization */
+void boardInit(void)
+{
+    /* disable watchdog timer */
+    SYSREG->WDOG_CR = 0;
+}
+INIT_BOARD_EXPORT(boardInit);
+
+/* custom finish command */
+extern uint32_t SystemCoreClock;
+void sayHello(void)
+{
+     rt_kprintf("Hello RT-Thread! By Microsemi SmartFusion2 Family FPGA-M2S010.\r\n");
+     rt_kprintf("MSS System Core Clock: %d Hz.\r\n", SystemCoreClock);
+}
+MSH_CMD_EXPORT(sayHello, "say hello to console");
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include "mss_gpio.h"
+#include "mss_uart.h"
+
+#include <rthw.h>
+#include <rtthread.h>
+
+void sw0_isr(void *args);
+void sw1_isr(void *args);
+void boardInit(void);
+void sayHello(void);
+
+#endif
@@ -0,0 +1,35 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+
+        menu "UART Drivers"
+            config BSP_USING_UART0
+                bool "Enable MSS_UART0"
+                select RT_USING_SERIAL
+                default y
+                help
+                config MSS_UART0
+        
+            config BSP_USING_UART1
+                bool "Enable MSS_UART1"
+                select RT_USING_SERIAL
+                default y
+                help 
+                config MSS_UART1
+            
+            config RT_CONSOLE_DEVICE_NAME
+                string "the device name for console"
+                default "uart0"
+        endmenu 
+        
+        menu "GPIO Drivers"
+            config BSP_USING_GPIO
+            bool "Enable MSS_GPIO"
+            select RT_USING_PIN
+            default y
+            help
+            config MSS_GPIO
+        endmenu
+    endmenu
+        
+endmenu
@@ -0,0 +1,16 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1'):
+   src += ['drv_uart.c']
+if  GetDepend('BSP_USING_GPIO'):
+   src += ['drv_gpio.c']
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include "mss_gpio.h"
+
+int rt_hw_pin_init(void);
+
+#endif
+
+
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "drv_uart.h"
+
+struct sf2_uart
+{
+    mss_uart_instance_t *uart;
+    IRQn_Type irq;
+};
+
+struct sf2_uart uart0=
+{
+    &g_mss_uart0,
+    UART0_IRQn,
+};
+struct rt_serial_device serial0;
+
+void uart0_rx_handler(mss_uart_instance_t *this_uart)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+struct sf2_uart uart1=
+{
+    &g_mss_uart1,
+    UART1_IRQn,
+};
+
+struct rt_serial_device serial1;
+void uart1_rx_handler(mss_uart_instance_t *this_uart)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+static rt_err_t sf2_uart_configure(struct rt_serial_device *serial, 
+	                               struct serial_configure *cfg)
+{
+    uint32_t baudRate;
+    uint8_t datBits, parity, stopBits;
+    uint8_t config;    
+    struct sf2_uart *uart;
+    
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    
+    uart = (struct sf2_uart *)serial->parent.user_data;
+    
+    switch(cfg->data_bits)
+    {
+        case DATA_BITS_5: datBits = MSS_UART_DATA_5_BITS; break;
+        case DATA_BITS_6: datBits = MSS_UART_DATA_6_BITS; break;
+        case DATA_BITS_7: datBits = MSS_UART_DATA_7_BITS; break;
+        case DATA_BITS_8: datBits = MSS_UART_DATA_8_BITS; break;
+        default:          datBits = MSS_UART_DATA_8_BITS; break;
+    }    
+    switch(cfg->parity)
+    {
+        case PARITY_NONE: parity = MSS_UART_NO_PARITY;   break;
+        case PARITY_EVEN: parity = MSS_UART_EVEN_PARITY; break;
+        case PARITY_ODD : parity = MSS_UART_ODD_PARITY;  break;
+        default         : parity = MSS_UART_NO_PARITY;   break;
+    }
+    switch(cfg->stop_bits)
+    {
+        case STOP_BITS_1: stopBits = MSS_UART_ONE_STOP_BIT; break;
+        case STOP_BITS_2: stopBits = MSS_UART_TWO_STOP_BITS; break;
+        case STOP_BITS_3: stopBits = MSS_UART_ONEHALF_STOP_BIT; break;
+        default         : stopBits = MSS_UART_ONE_STOP_BIT;    
+    }
+    
+    baudRate = cfg->baud_rate;
+    config = datBits | parity | stopBits;
+    
+    MSS_UART_init(uart->uart, baudRate, config);
+    if(uart->uart == &g_mss_uart0)
+        MSS_UART_set_rx_handler(uart->uart, uart0_rx_handler, MSS_UART_FIFO_SINGLE_BYTE);
+    else 
+        MSS_UART_set_rx_handler(uart->uart, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE);
+
+	return RT_EOK;
+}
+
+static rt_err_t sf2_uart_control(struct rt_serial_device *serial, 
+	                              int cmd, void *arg)
+{
+    struct sf2_uart* uart;
+    
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct sf2_uart*)serial->parent.user_data;
+
+    switch (cmd)
+    {
+        case RT_DEVICE_CTRL_CLR_INT:
+            NVIC_DisableIRQ(uart->irq);
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            NVIC_EnableIRQ(uart->irq);
+            break;
+    }
+
+    return RT_EOK;
+}
+
+static int sf2_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct sf2_uart* uart;
+    uint32_t tx_ready;
+    
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct sf2_uart*)serial->parent.user_data;
+        
+    do {
+        tx_ready = uart->uart->hw_reg->LSR & 0x20u;
+    } while(!tx_ready);
+    uart->uart->hw_reg->THR = c;
+
+    return 1;
+}
+
+static int sf2_uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    uint8_t err_status;
+    struct sf2_uart* uart;
+    
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct sf2_uart*)serial->parent.user_data;
+
+    err_status = MSS_UART_get_rx_status(uart->uart);
+    if(MSS_UART_NO_ERROR == err_status)
+        MSS_UART_get_rx(uart->uart, (uint8_t *)&ch, 1);
+        
+    return ch;
+}
+
+static const struct rt_uart_ops sf2_uart_ops =
+{
+    sf2_uart_configure,
+    sf2_uart_control,
+    sf2_uart_putc,
+    sf2_uart_getc,
+};
+
+int rt_hw_uart_init(void)
+{
+    rt_err_t result = RT_EOK;
+    struct sf2_uart* uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART0
+    uart = &uart0;
+    serial0.ops = &sf2_uart_ops;
+    /* default config: 115200, 8, no, 1 */
+    serial0.config = config;
+    result = rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); 
+    RT_ASSERT(result == RT_EOK);
+#endif
+
+#ifdef BSP_USING_UART1
+    uart = &uart1;
+    serial1.ops = &sf2_uart_ops;
+    /* default config: 115200, 8, no, 1 */
+    serial1.config = config;
+    result = rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); 
+    RT_ASSERT(result == RT_EOK);
+#endif
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-06     whik         first version
+ */
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include "mss_uart.h"
+void uart_rx_handler(mss_uart_instance_t *this_uart);
+
+void uart0_rx_handler(mss_uart_instance_t * this_uart);
+void uart1_rx_handler(mss_uart_instance_t * this_uart);
+int rt_hw_uart_init(void);
+
+#endif
@@ -0,0 +1,16 @@
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src	= [cwd + '/sys_config/sys_config.c']
+src += [cwd + '/mss_gpio/mss_gpio.c']
+src += [cwd + '/mss_uart/mss_uart.c']
+
+CPPPATH = [cwd+'/sys_config']
+CPPPATH += [cwd+'/mss_gpio']
+CPPPATH += [cwd+'/mss_uart']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,83 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Register bit offsets and masks defintions for SmartFusion2 MSS MMUART.
+ * 
+ * SVN $Revision: 5610 $
+ * SVN $Date: 2013-04-05 18:49:30 +0530 (Fri, 05 Apr 2013) $
+ */
+#ifndef MSS_UART_REGS_H_
+#define MSS_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ Register Bit definitions
+ */
+
+/* Line Control register bit definitions */
+#define SB                  6u      /* Set break */
+#define DLAB                7u      /* Divisor latch access bit */
+
+/* FIFO Control register bit definitions */
+#define RXRDY_TXRDYN_EN     0u      /* Enable TXRDY and RXRDY signals */
+#define CLEAR_RX_FIFO       1u      /* Clear receiver FIFO */
+#define CLEAR_TX_FIFO       2u      /* Clear transimtter FIFO */
+#define RDYMODE             3u      /* Mode 0 or Mode 1 for TXRDY and RXRDY */
+
+/* Modem Control register bit definitions */
+#define LOOP                4u      /* Local loopback */
+#define RLOOP               5u      /* Remote loopback */
+#define ECHO                6u      /* Automatic echo */
+#define RLOOP_MASK          0x6u    /* Remote loopback & Automatic echo*/
+
+/* Line Status register bit definitions   */
+#define DR                  0u      /* Data ready */
+#define THRE                5u      /* Transmitter holding register empty */
+#define TEMT                6u      /* Transitter empty */
+
+/* Interrupt Enable register bit definitions */
+#define ERBFI               0u      /* Enable receiver buffer full interrupt */
+#define ETBEI               1u      /* Enable transmitter buffer empty interrupt */
+#define ELSI                2u      /* Enable line status interrupt */
+#define EDSSI               3u      /* Enable modem status interrupt */
+
+/* Multimode register 0 bit definitions */
+#define ELIN                3u      /* Enable LIN header detection */
+#define ETTG                5u      /* Enable transmitter time guard */
+#define ERTO                6u      /* Enable receiver time-out */
+#define EFBR                7u      /* Enable fractional baud rate mode */
+
+/* Multimode register 1 bit definitions */
+#define E_MSB_RX            0u      /* MSB / LSB first for receiver */
+#define E_MSB_TX            1u      /* MSB / LSB first for transmitter */
+#define EIRD                2u      /* Enable IrDA modem */
+#define EIRX                3u      /* Input polarity for IrDA modem */
+#define EITX                4u      /* Output polarity for IrDA modem */
+#define EITP                5u      /* Output pulse width for IrDA modem */      
+
+/* Multimode register 2 bit definitions */
+#define EERR                0u      /* Enable ERR / NACK during stop time */
+#define EAFM                1u      /* Enable 9-bit address flag mode */
+#define EAFC                2u      /* Enable address flag clear */
+#define ESWM                3u      /* Enable single wire half-duplex mode */
+
+/* Multimode Interrupt Enable register and
+   Multimode Interrupt Identification register definitions */
+#define ERTOI               0u      /* Enable receiver timeout interrupt */
+#define ENACKI              1u      /* Enable NACK / ERR interrupt */
+#define EPID_PEI            2u      /* Enable PID parity error interrupt */
+#define ELINBI              3u      /* Enable LIN break interrupt */
+#define ELINSI              4u      /* Enable LIN sync detection interrupt */
+
+
+#ifdef __cplusplus                       
+}
+#endif
+
+#endif /* MSS_UART_REGS_H_ */
+
+
+
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ *  Smartfusion2 system configuration. This file is automatically generated
+ *  by the Libero tools.
+ *
+ */
+#ifndef MSS_SYSTEM_CONFIGURATION
+#define MSS_SYSTEM_CONFIGURATION
+
+/*==============================================================================
+ * Clock configuration
+ */
+#include "sys_config_mss_clocks.h"
+ 
+/*==============================================================================
+ * Memory remapping configuration
+ */
+/* TBD */
+
+/*==============================================================================
+ * FACC_INIT (Cortex-M3 runs the FACC INIT procedure)
+ * Only set to 1 for design targeting the M2S050T_ES device
+ */
+#define MSS_SYS_FACC_INIT_BY_CORTEX 0
+
+/*==============================================================================
+ * MDDR configuration
+ */
+#define MSS_SYS_MDDR_CONFIG_BY_CORTEX       0
+
+/*==============================================================================
+ * FDDR configuration
+ */
+#define MSS_SYS_FDDR_CONFIG_BY_CORTEX       0
+
+/*==============================================================================
+ * SERDES Interface configuration
+ */
+#define MSS_SYS_SERDES_0_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_0.h"
+#endif
+
+#define MSS_SYS_SERDES_1_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_1.h"
+#endif
+
+#define MSS_SYS_SERDES_2_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_2.h"
+#endif
+
+#define MSS_SYS_SERDES_3_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_3.h"
+#endif
+
+/*==============================================================================
+ * Cache configuration
+ */
+#define MSS_SYS_CACHE_CONFIG_BY_CORTEX      0
+
+#endif  /* MSS_SYSTEM_CONFIGURATION */
+
@@ -0,0 +1,21 @@
+/*=============================================================*/
+/* Created by Microsemi SmartDesign Fri May 22 15:04:18 2020   */
+/*                                                             */
+/* Warning: Do not modify this file, it may lead to unexpected */
+/*          functional failures in your design.                */
+/*                                                             */
+/*=============================================================*/
+
+#ifndef SYS_CONFIG_MSS_CLOCKS
+#define SYS_CONFIG_MSS_CLOCKS
+
+#define MSS_SYS_M3_CLK_FREQ             100000000u
+#define MSS_SYS_MDDR_CLK_FREQ           100000000u
+#define MSS_SYS_APB_0_CLK_FREQ          100000000u
+#define MSS_SYS_APB_1_CLK_FREQ          100000000u
+#define MSS_SYS_APB_2_CLK_FREQ          25000000u
+#define MSS_SYS_FIC_0_CLK_FREQ          100000000u
+#define MSS_SYS_FIC_1_CLK_FREQ          100000000u
+#define MSS_SYS_FIC64_CLK_FREQ          100000000u
+
+#endif /* SYS_CONFIG_MSS_CLOCKS */