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[bsp][hpmicro] upgrade to bsp v1.10.0, add hpm6p00evk and hpm5e00evk support

Browse Source 
- upgraded bsp to v1.10.0
- moved hpm_sdk to rt-thread package
- added support for hpm6p00evk and hpm5e00evk

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
This commit is contained in:
Fan YANG
2025-09-23 13:38:22 +08:00
committed by R b b666
parent db1779e239
commit 35672cd5cb
1312 changed files with 37744 additions and 1030013 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/hpmicro/hpm6800evk/.config
+58 -13
View File
@@ -104,11 +104,9 @@
#
# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
# end of rt_strnlen options
# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
# end of klibc options
CONFIG_RT_NAME_MAX=8
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_AMP is not set
@@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
CONFIG_RT_USING_CPU_USAGE_TRACER=y
#
# kservice options
@@ -187,6 +185,9 @@ CONFIG_RT_VER_NUM=0x50201
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV32=y
#
# RT-Thread Components
#
@@ -203,6 +204,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
# CONFIG_FINSH_USING_WORD_OPERATION is not set
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -253,13 +255,7 @@ CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SOFT_SPI is not set
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@@ -386,6 +382,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
# CONFIG_PKG_USING_ESP_HOSTED is not set
#
# Wi-Fi
@@ -493,6 +490,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -582,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_MCOREDUMP is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -627,6 +626,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ZDEBUG is not set
# CONFIG_PKG_USING_RVBACKTRACE is not set
# CONFIG_PKG_USING_HPATCHLITE is not set
# CONFIG_PKG_USING_THREAD_METRIC is not set
# end of tools packages
#
@@ -720,6 +720,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -801,6 +802,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_NUCLEI_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_MM32 is not set
@@ -843,6 +846,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
# end of HC32 DDL Drivers
#
@@ -856,6 +863,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
# end of NXP HAL & SDK Drivers
#
# NUVOTON Drivers
#
# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
# end of NUVOTON Drivers
#
# GD32 Drivers
#
# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
# end of GD32 Drivers
#
# HPMicro SDK
#
CONFIG_PKG_USING_HPM_SDK=y
CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
# CONFIG_PKG_USING_HPM_SDK_V110 is not set
CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
CONFIG_PKG_HPM_SDK_VER="latest"
# end of HPMicro SDK
# end of HAL & SDK Drivers
#
@@ -1027,6 +1059,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_SEAN_WS2812B is not set
# CONFIG_PKG_USING_IC74HC165 is not set
# CONFIG_PKG_USING_IST8310 is not set
# CONFIG_PKG_USING_ST7789_SPI is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@@ -1365,26 +1398,37 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# end of Arduino libraries
# end of RT-Thread online packages
CONFIG_SOC_HPM6800_SERIES=y
#
# Hardware Drivers Config
#
CONFIG_SOC_HPM6000=y
CONFIG_SOC_HPM6800=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_GPIO_IRQ_PRIORITY=1
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_UART0_RX_USING_DMA is not set
# CONFIG_BSP_UART0_TX_USING_DMA is not set
CONFIG_BSP_UART0_RX_BUFSIZE=128
CONFIG_BSP_UART0_TX_BUFSIZE=0
CONFIG_BSP_UART0_IRQ_PRIORITY=1
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
CONFIG_BSP_USING_UART3=y
# CONFIG_BSP_UART3_RX_USING_DMA is not set
# CONFIG_BSP_UART3_TX_USING_DMA is not set
CONFIG_BSP_UART3_RX_BUFSIZE=1024
CONFIG_BSP_UART3_TX_BUFSIZE=0
CONFIG_BSP_UART3_IRQ_PRIORITY=1
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_ETH is not set
@@ -1395,7 +1439,6 @@ CONFIG_BSP_UART3_TX_BUFSIZE=0
# CONFIG_BSP_USING_PDMA is not set
# CONFIG_BSP_USING_GPTMR is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_FEMC is not set
# CONFIG_INIT_EXT_RAM_FOR_DATA is not set
# CONFIG_BSP_USING_XPI_FLASH is not set
# CONFIG_BSP_USING_DAO is not set
@@ -1412,6 +1455,8 @@ CONFIG_BSP_UART3_TX_BUFSIZE=0
# CONFIG_BSP_USING_PIXELMUX is not set
# CONFIG_BSP_USING_MIPI_CSI is not set
# CONFIG_BSP_USING_MIPI_DSI is not set
# CONFIG_BSP_USING_LVB is not set
# CONFIG_BSP_USING_LCB is not set
# CONFIG_BSP_USING_RTT_LCD_DRIVER is not set
# end of On-chip Peripheral Drivers
# end of Hardware Drivers Config
bsp/hpmicro/hpm6800evk/SConstruct
-11
View File
@@ -55,17 +55,6 @@ GDB = rtconfig.GDB
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
# include components
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
# includes rtt drivers
bsp/hpmicro/hpm6800evk/board/Kconfig
+569 -86
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/hpm6800evk/board/board.c
+202 -219
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/hpm6800evk/board/board.h
+155 -63
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg
+3 -3
View File
@@ -206,13 +206,13 @@ proc init_dram {} {
}
$_TARGET0 configure -event reset-end {
init_clock
# init_clock
# init_ddr3
}
$_TARGET0 configure -event reset-init {
init_clock
init_ddr3
init_clock
# init_ddr3
}
$_TARGET0 configure -event gdb-attach {
bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld
+350
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld → bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld
+55 -24
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,23 +46,26 @@ SECTIONS
.start __app_load_addr__ : {
. = ALIGN(8);
KEEP(*(.start))
. = ALIGN(16);
} > XPI0
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
.vectors : AT(__vector_load_addr__) {
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_start__ = .;
KEEP(*(.vector_table))
KEEP(*(.isr_vector))
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_end__ = .;
} > ILM
.fast : AT(etext + __data_end__ - __tdata_start__) {
. = ALIGN(8);
.fast : AT(__fast_load_addr__) {
. = ALIGN(16);
__ramfunc_start__ = .;
*(.fast)
*(.fast.*)
. = ALIGN(16);
/* RT-Thread Core Start */
KEEP(*context_gcc.o(.text* .rodata*))
@@ -86,12 +89,12 @@ SECTIONS
/* HPMicro Driver Wrapper */
KEEP(*drv_*.o (.text .text* .rodata .rodata*))
. = ALIGN(8);
. = ALIGN(16);
__ramfunc_end__ = .;
} > ILM
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
. = ALIGN(8);
.text (__vector_load_addr__ + SIZEOF(.vectors)) : {
. = ALIGN(16);
*(.text)
*(.text*)
*(.rodata)
@@ -116,12 +119,6 @@ SECTIONS
* RT-Thread related sections - Start
*
*********************************************/
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@@ -155,6 +152,20 @@ SECTIONS
} > XPI0
.eh_frame :
{
__eh_frame_start = .;
KEEP(*(.eh_frame))
__eh_frame_end = .;
} > XPI0
.eh_frame_hdr :
{
KEEP(*(.eh_frame_hdr))
} > XPI0
__eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
__eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
.rel : {
KEEP(*(.rel*))
} > XPI0
@@ -167,6 +178,16 @@ SECTIONS
KEEP(*(.fast_ram))
} > DLM
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
} > DLM
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
@@ -187,22 +208,26 @@ SECTIONS
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -230,10 +255,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -253,8 +278,10 @@ SECTIONS
PROVIDE (__edata = .);
PROVIDE (_edata = .);
PROVIDE (edata = .);
} > DLM
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
} > DLM
__fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
__fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
.heap(NOLOAD) : {
. = ALIGN(8);
@@ -277,9 +304,10 @@ SECTIONS
PROVIDE (_stack = .);
PROVIDE (_stack_in_dlm = .);
PROVIDE( __rt_rvstack = . );
} > AXI_SRAM
} > DLM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -290,8 +318,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld → bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld
+64 -28
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,23 +46,26 @@ SECTIONS
.start __app_load_addr__ : {
. = ALIGN(8);
KEEP(*(.start))
. = ALIGN(16);
} > XPI0
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
.vectors : AT(__vector_load_addr__) {
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_start__ = .;
KEEP(*(.vector_table))
KEEP(*(.isr_vector))
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_end__ = .;
} > AXI_SRAM
} > ILM
.fast : AT(etext + __data_end__ - __tdata_start__) {
. = ALIGN(8);
.fast : AT(__fast_load_addr__) {
. = ALIGN(16);
__ramfunc_start__ = .;
*(.fast)
*(.fast.*)
. = ALIGN(16);
/* RT-Thread Core Start */
KEEP(*context_gcc.o(.text* .rodata*))
@@ -106,16 +109,12 @@ SECTIONS
KEEP(*ethernet*.o (.text .text* .rodata .rodata*))
KEEP(*ethernetif*.o (.text .text* .rodata .rodata*))
. = ALIGN(8);
. = ALIGN(16);
__ramfunc_end__ = .;
} > AXI_SRAM
} > ILM
.fast_ram (NOLOAD) : {
KEEP(*(.fast_ram))
} > DLM
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
. = ALIGN(8);
.text (__vector_load_addr__ + SIZEOF(.vectors)) : {
. = ALIGN(16);
*(.text)
*(.text*)
*(.rodata)
@@ -173,6 +172,20 @@ SECTIONS
} > XPI0
.eh_frame :
{
__eh_frame_start = .;
KEEP(*(.eh_frame))
__eh_frame_end = .;
} > XPI0
.eh_frame_hdr :
{
KEEP(*(.eh_frame_hdr))
} > XPI0
__eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
__eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
.rel : {
KEEP(*(.rel*))
} > XPI0
@@ -181,6 +194,20 @@ SECTIONS
PROVIDE (_etext = .);
PROVIDE (etext = .);
.fast_ram (NOLOAD) : {
KEEP(*(.fast_ram))
} > DLM
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
} > DLM
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
@@ -194,29 +221,33 @@ SECTIONS
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > AXI_SRAM
} > DLM
/* Note: the .tbss and .tdata section should be adjacent */
.tbss(NOLOAD) : {
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > AXI_SRAM
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > AXI_SRAM
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -244,10 +275,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -267,8 +298,10 @@ SECTIONS
PROVIDE (__edata = .);
PROVIDE (_edata = .);
PROVIDE (edata = .);
} > AXI_SRAM
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
} > DLM
__fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
__fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
.heap(NOLOAD) : {
. = ALIGN(8);
@@ -291,9 +324,10 @@ SECTIONS
PROVIDE (_stack = .);
PROVIDE (_stack_in_dlm = .);
PROVIDE( __rt_rvstack = . );
} > AXI_SRAM
} > DLM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -304,8 +338,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
@@ -324,7 +361,6 @@ SECTIONS
.sdram (NOLOAD) : {
. = ALIGN(8);
__sdram_start__ = .;
. += SDRAM_SIZE;
__sdram_end__ = .;
} > SDRAM
}
bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld → bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld
+55 -17
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,23 +46,26 @@ SECTIONS
.start __app_load_addr__ : {
. = ALIGN(8);
KEEP(*(.start))
. = ALIGN(16);
} > XPI0
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
.vectors : AT(__vector_load_addr__) {
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_start__ = .;
KEEP(*(.vector_table))
KEEP(*(.isr_vector))
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_end__ = .;
} > ILM
.fast : AT(etext + __data_end__ - __tdata_start__) {
. = ALIGN(8);
.fast : AT(__fast_load_addr__) {
. = ALIGN(16);
__ramfunc_start__ = .;
*(.fast)
*(.fast.*)
. = ALIGN(16);
/* RT-Thread Core Start */
KEEP(*context_gcc.o(.text* .rodata*))
@@ -82,16 +85,16 @@ SECTIONS
KEEP(*mem.o (.text .text* .rodata .rodata*))
KEEP(*mempool.o (.text .text* .rodata .rodata*))
/* RT-Thread Core End */
/* HPMicro Driver Wrapper */
KEEP(*drv_*.o (.text .text* .rodata .rodata*))
. = ALIGN(8);
. = ALIGN(16);
__ramfunc_end__ = .;
} > ILM
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
. = ALIGN(8);
.text (__vector_load_addr__ + SIZEOF(.vectors)) : {
. = ALIGN(16);
*(.text)
*(.text*)
*(.rodata)
@@ -149,6 +152,20 @@ SECTIONS
} > XPI0
.eh_frame :
{
__eh_frame_start = .;
KEEP(*(.eh_frame))
__eh_frame_end = .;
} > XPI0
.eh_frame_hdr :
{
KEEP(*(.eh_frame_hdr))
} > XPI0
__eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
__eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
.rel : {
KEEP(*(.rel*))
} > XPI0
@@ -161,6 +178,16 @@ SECTIONS
KEEP(*(.fast_ram))
} > DLM
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
} > DLM
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
@@ -176,26 +203,31 @@ SECTIONS
__bss_end__ = .;
} > DLM
/* Note: the .tbss and .tdata section should be adjacent */
.tbss(NOLOAD) : {
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -223,10 +255,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -247,9 +279,12 @@ SECTIONS
PROVIDE (_edata = .);
PROVIDE (edata = .);
} > DLM
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
__fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -260,8 +295,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld → bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld
+28 -9
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -106,6 +106,16 @@ SECTIONS
KEEP(*(.fast_ram))
} > DLM
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
} > DLM
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
@@ -126,22 +136,26 @@ SECTIONS
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -169,10 +183,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -195,7 +209,8 @@ SECTIONS
PROVIDE (edata = .);
} > DLM
.fast : AT(etext + __data_end__ - __tdata_start__) {
__fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
.fast : AT(__fast_load_addr__) {
. = ALIGN(8);
PROVIDE(__ramfunc_start__ = .);
*(.fast)
@@ -203,7 +218,8 @@ SECTIONS
PROVIDE(__ramfunc_end__ = .);
} > AXI_SRAM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -214,8 +230,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld → bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld
+19 -12
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -119,7 +119,7 @@ SECTIONS
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > AXI_SRAM
} > DLM
/* Note: .tbss and .tdata should be adjacent */
.tbss(NOLOAD) : {
@@ -129,9 +129,10 @@ SECTIONS
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > AXI_SRAM
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
@@ -139,9 +140,10 @@ SECTIONS
*(.tdata*)
. = ALIGN(8);
__tdata_end__ = .;
} > AXI_SRAM
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -169,10 +171,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -195,7 +197,8 @@ SECTIONS
PROVIDE (edata = .);
} > AXI_SRAM
.fast : AT(etext + __data_end__ - __tdata_start__) {
__fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
.fast : AT(__fast_load_addr__) {
. = ALIGN(8);
PROVIDE(__ramfunc_start__ = .);
*(.fast)
@@ -203,7 +206,8 @@ SECTIONS
PROVIDE(__ramfunc_end__ = .);
} > AXI_SRAM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -214,8 +218,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
bsp/hpmicro/hpm6800evk/board/pinmux.c
+73 -42
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 hpmicro
* Copyright (c) 2023-2024 hpmicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -56,22 +56,6 @@ void init_cap_pins(void)
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07;
}
void init_i2c_pins_as_gpio(I2C_Type *ptr)
{
if (ptr == HPM_I2C3) {
HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_GPIO_D_28;
HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_GPIO_D_29;
} else if (ptr == HPM_I2C1) {
HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_GPIO_E_12;
HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_GPIO_E_13;
} else if (ptr == HPM_I2C0) {
HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPIO_F_09;
HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08;
} else {
;
}
}
void init_i2c_pins(I2C_Type *ptr)
{
if (ptr == HPM_I2C3) { /* Audio */
@@ -138,10 +122,10 @@ void init_gpio_pins(void)
/* configure pad setting: pull enable and pull up, schmitt trigger enable */
/* enable schmitt trigger to eliminate jitter of pin used as button */
HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPIO_F_06;
HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11);
HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(3);
HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07;
HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11);
HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(3);
}
void init_spi_pins(SPI_Type *ptr)
@@ -151,6 +135,12 @@ void init_spi_pins(SPI_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO;
HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI;
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI3_CS_0;
/* set max frequency slew rate(200M) */
HPM_IOC->PAD[IOC_PAD_PE05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
HPM_IOC->PAD[IOC_PAD_PE06].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PE07].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
}
}
@@ -161,6 +151,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO;
HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI;
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04;
/* set max frequency slew rate(200M) */
HPM_IOC->PAD[IOC_PAD_PE05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
HPM_IOC->PAD[IOC_PAD_PE06].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PE07].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
}
}
@@ -177,6 +173,7 @@ void init_gptmr_pins(GPTMR_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0;
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0;
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1;
HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPTMR2_COMP_2;
}
}
@@ -316,16 +313,16 @@ void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8)
}
}
void init_usb_pins(void)
void init_usb_pins(USB_Type *ptr)
{
/* USB0_ID */
HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID;
/* USB0_OC */
HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC;
/* USB0_PWR */
HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR;
if (ptr == HPM_USB0) {
/* USB0_ID */
HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID;
/* USB0_OC */
HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC;
/* USB0_PWR */
HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR;
}
}
void init_can_pins(MCAN_Type *ptr)
@@ -520,25 +517,19 @@ void init_enet_pins(ENET_Type *ptr)
void init_enet_pps_pins(void)
{
HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_EVTO_0;
HPM_IOC->PAD[IOC_PAD_PE10].FUNC_CTL = IOC_PE10_FUNC_CTL_ETH0_EVTO_1;
}
void init_enet_pps_capture_pins(void)
{
HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH0_EVTI_0;
HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH0_EVTI_1;
}
void init_adc_pins(void)
{
HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
/* ADC0.INA12 */
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
}
void init_tamper_pins(void)
@@ -547,3 +538,43 @@ void init_tamper_pins(void)
HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_TAMP_PZ_05;
HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_TAMP_PZ_06;
}
/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
void init_uart_break_signal_pin(void)
{
HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04;
}
void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
if (ptr == HPM_GPTMR2) {
if (as_comp) {
switch (channel) {
case 0:
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0;
break;
case 1:
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1;
break;
case 2:
HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPTMR2_COMP_2;
default:
break;
}
} else {
switch (channel) {
case 0:
HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0;
break;
default:
break;
}
}
}
}
void init_clk_ref_pin(void)
{
HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SOC_REF1;
}
bsp/hpmicro/hpm6800evk/board/pinmux.h
+6 -4
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 hpmicro
* Copyright (c) 2023-2024 hpmicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -14,7 +14,6 @@ extern "C" {
void init_uart_pins(UART_Type *ptr);
void init_uart_pin_as_gpio(UART_Type *ptr);
void init_cap_pins(void);
void init_i2c_pins_as_gpio(I2C_Type *ptr);
void init_i2c_pins(I2C_Type *ptr);
void init_gpio_pins(void);
void init_spi_pins(SPI_Type *ptr);
@@ -26,9 +25,8 @@ void init_qei_trgm_pins(void);
void init_butn_pins(void);
void init_acmp_pins(void);
void init_adc_pins(void);
void init_usb_pins(void);
void init_usb_pins(USB_Type *ptr);
void init_can_pins(MCAN_Type *ptr);
void init_i2c_pins_as_gpio(I2C_Type *ptr);
void init_led_pins_as_gpio(void);
void init_cam_pins(void);
void init_cam_mipi_csi_pins(void);
@@ -53,8 +51,12 @@ void init_dao_pins(void);
void init_pdm_pins(void);
void init_enet_pins(ENET_Type *ptr);
void init_enet_pps_pins(void);
void init_enet_pps_capture_pins(void);
void init_adc_pins(void);
void init_tamper_pins(void);
void init_uart_break_signal_pin(void);
void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
void init_clk_ref_pin(void);
#ifdef __cplusplus
}
bsp/hpmicro/hpm6800evk/board/rtt_board.c
+50 -2
View File
@@ -61,6 +61,7 @@ void rtt_board_init(void)
void app_init_led_pins(void)
{
board_init_led_pins();
gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN);
gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN);
gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN);
@@ -99,7 +100,7 @@ void rt_hw_console_output(const char *str)
void app_init_usb_pins(void)
{
board_init_usb_pins();
board_init_usb(HPM_USB0);
}
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
@@ -111,7 +112,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
void rt_hw_cpu_reset(void)
{
HPM_PPOR->RESET_ENABLE = (1UL << 31);
HPM_PPOR->RESET_ENABLE |= (1UL << 31);
HPM_PPOR->SOFTWARE_RESET = 1000U;
while(1) {
@@ -130,3 +131,50 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
}
}
#endif
uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
{
uint32_t freq = 0;
if (ptr == HPM_ADC0) {
if (clk_src_ahb) {
/* Configure the ADC clock from AXI (@200MHz by default)*/
clock_set_adc_source(clock_adc0, clk_adc_src_axi0);
} else {
/* Configure the ADC clock from pll0_clk1 divided by 4 (@200MHz by default) */
clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
}
clock_add_to_group(clock_adc0, 0);
freq = clock_get_frequency(clock_adc0);
}
return freq;
}
uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr)
{
if (ptr == HPM_I2S0) {
clock_add_to_group(clock_i2s0, 0);
return clock_get_frequency(clock_i2s0);
} else if (ptr == HPM_I2S1) {
clock_add_to_group(clock_i2s1, 0);
return clock_get_frequency(clock_i2s1);
} else if (ptr == HPM_I2S2) {
clock_add_to_group(clock_i2s2, 0);
return clock_get_frequency(clock_i2s2);
} else if (ptr == HPM_I2S3) {
clock_add_to_group(clock_i2s3, 0);
return clock_get_frequency(clock_i2s3);
} else {
return 0;
}
}
#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
extern void hpm_isr_usb0(void);
RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
#endif
bsp/hpmicro/hpm6800evk/board/rtt_board.h
+21 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 hpmicro
* Copyright (c) 2021 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -11,6 +11,9 @@
#include "hpm_soc.h"
/* gpio section */
#define APP_LED0 (0U)
#define APP_LED1 (1U)
#define APP_LED2 (2U)
#define APP_LED0_GPIO_CTRL HPM_GPIO0
#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOF
#define APP_LED0_GPIO_PIN 1
@@ -28,6 +31,12 @@
/* mchtimer section */
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
/* gptmr as os_tick */
#define BOARD_OS_TIMER HPM_GPTMR0
#define BOARD_OS_TIMER_CH 1
#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0
#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
/* CAN section */
#define BOARD_CAN_NAME "can3"
#define BOARD_CAN_HWFILTER_INDEX (3U)
@@ -46,6 +55,17 @@
#define IRQn_PendSV IRQn_DEBUG0
#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */
#define BOARD_ENET0_INT_REF_CLK (0U)
#define BOARD_ENET0_PHY_RST_TIME (30)
#if BOARD_ENET0_INF
#define BOARD_ENET0_TX_DLY (0U)
#define BOARD_ENET0_RX_DLY (0U)
#endif
#if defined(__USE_ENET_PTP) && __USE_ENET_PTP
#define BOARD_ENET0_PTP_CLOCK (clock_ptp0)
#endif
/***************************************************************
*
* RT-Thread related definitions
bsp/hpmicro/hpm6800evk/rtconfig.h
+23 -3
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 8
#define RT_NAME_MAX 16
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
@@ -76,6 +76,7 @@
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 1024
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
@@ -108,6 +109,8 @@
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define ARCH_RISCV
#define ARCH_RISCV32
/* RT-Thread Components */
@@ -142,7 +145,6 @@
#define RT_USING_SERIAL_V2
#define RT_SERIAL_BUF_STRATEGY_OVERWRITE
#define RT_SERIAL_USING_DMA
#define RT_USING_SPI
#define RT_USING_PIN
/* end of Device Drivers */
@@ -305,6 +307,20 @@
/* NXP HAL & SDK Drivers */
/* end of NXP HAL & SDK Drivers */
/* NUVOTON Drivers */
/* end of NUVOTON Drivers */
/* GD32 Drivers */
/* end of GD32 Drivers */
/* HPMicro SDK */
#define PKG_USING_HPM_SDK
#define PKG_USING_HPM_SDK_LATEST_VERSION
/* end of HPMicro SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
@@ -384,21 +400,25 @@
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_HPM6800_SERIES
/* Hardware Drivers Config */
#define SOC_HPM6000
#define SOC_HPM6800
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_GPIO_IRQ_PRIORITY 1
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_BUFSIZE 128
#define BSP_UART0_TX_BUFSIZE 0
#define BSP_UART0_IRQ_PRIORITY 1
#define BSP_USING_UART3
#define BSP_UART3_RX_BUFSIZE 1024
#define BSP_UART3_TX_BUFSIZE 0
#define BSP_UART3_IRQ_PRIORITY 1
/* end of On-chip Peripheral Drivers */
/* end of Hardware Drivers Config */
bsp/hpmicro/hpm6800evk/rtconfig.py
+39 -6
View File
@@ -1,8 +1,41 @@
# Copyright 2021-2023 HPMicro
# Copyright 2021-2025 HPMicro
# SPDX-License-Identifier: BSD-3-Clause
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
need_update = True
for p in os.listdir("packages"):
if p.startswith("hpm_sdk-"):
need_update = False
break
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
# toolchains options
ARCH='risc-v'
@@ -80,27 +113,27 @@ if PLATFORM == 'gcc':
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
LFLAGS += ' -O0'
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
elif BUILD == 'ram_release':
CFLAGS += ' -O2'
LFLAGS += ' -O2'
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
elif BUILD == 'flash_debug':
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
LFLAGS += ' -O0'
CFLAGS += ' -DFLASH_XIP=1'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
elif BUILD == 'flash_release':
CFLAGS += ' -O2'
LFLAGS += ' -O2'
CFLAGS += ' -DFLASH_XIP=1'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
else:
CFLAGS += ' -O2'
LFLAGS += ' -O2'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
LFLAGS += ' -T ' + LINKER_FILE
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c
+16 -7
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2025 HPMicro
*
*
*/
@@ -9,6 +9,7 @@
#include "hpm_l1c_drv.h"
#include <rtthread.h>
void system_init(void);
extern int entry(void);
@@ -20,6 +21,7 @@ void system_init(void)
{
disable_global_irq(CSR_MSTATUS_MIE_MASK);
disable_irq_from_intc();
enable_irq_from_intc();
enable_global_irq(CSR_MSTATUS_MIE_MASK);
#ifndef CONFIG_NOT_ENABLE_ICACHE
@@ -32,6 +34,7 @@ void system_init(void)
__attribute__((weak)) void c_startup(void)
{
#ifndef __SES_RISCV
uint32_t i, size;
#ifdef FLASH_XIP
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
@@ -45,6 +48,10 @@ __attribute__((weak)) void c_startup(void)
extern uint8_t __bss_start__[], __bss_end__[];
extern uint8_t __tbss_start__[], __tbss_end__[];
extern uint8_t __tdata_start__[], __tdata_end__[];
extern uint8_t __fast_load_addr__[];
extern uint8_t __noncacheable_init_load_addr__[];
extern uint8_t __data_load_addr__[];
extern uint8_t __tdata_load_addr__[];
extern uint8_t __data_start__[], __data_end__[];
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
@@ -71,26 +78,27 @@ __attribute__((weak)) void c_startup(void)
/* tdata section LMA: etext */
size = __tdata_end__ - __tdata_start__;
for (i = 0; i < size; i++) {
*(__tdata_start__ + i) = *(__etext + i);
*(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
}
/* data section LMA: etext */
size = __data_end__ - __data_start__;
for (i = 0; i < size; i++) {
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
*(__data_start__ + i) = *(__data_load_addr__ + i);
}
/* ramfunc section LMA: etext + data length */
size = __ramfunc_end__ - __ramfunc_start__;
for (i = 0; i < size; i++) {
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
*(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
}
/* noncacheable init section LMA: etext + data length + ramfunc length */
size = __noncacheable_init_end__ - __noncacheable_init_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
*(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
}
#endif
}
__attribute__((weak)) int main(void)
@@ -113,9 +121,10 @@ void reset_handler(void)
/* Call platform specific hardware initialization */
system_init();
#ifndef __SES_RISCV
/* Do global constructors */
__libc_init_array();
#endif
/* Entry function */
@@ -123,6 +132,6 @@ void reset_handler(void)
}
__attribute__((weak)) void _init()
__attribute__((weak)) void _init(void)
{
}
bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S
+2 -1
View File
@@ -5,7 +5,8 @@
*
*/
#include "cpuport.h"
.section .text.entry, "ax"
.align 2
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S
-1
View File
@@ -77,7 +77,6 @@ _start:
nmi_handler:
1: j 1b
.global default_irq_handler
.weak default_irq_handler
.align 2
default_irq_handler: