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[bsp][hpmicro] upgrade to bsp v1.10.0, add hpm6p00evk and hpm5e00evk support

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- upgraded bsp to v1.10.0
- moved hpm_sdk to rt-thread package
- added support for hpm6p00evk and hpm5e00evk

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
This commit is contained in:
Fan YANG
2025-09-23 13:38:22 +08:00
committed by R b b666
parent db1779e239
commit 35672cd5cb
1312 changed files with 37744 additions and 1030013 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/hpmicro/.ignore_format.yml
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@@ -4,11 +4,24 @@
dir_path:
- hpm6200evk/startup
- hpm6200evk/board
- hpm6300evk/startup
- hpm6300evk/board
- hpm6750evk/startup
- hpm6750evk/board
- hpm6750evk2/startup
- hpm6750evk2/board
- hpm6750evkmini/startup
- hpm6750evkmini/board
- hpm5300evk/startup
- hpm5300evk/board
- hpm5301evklite/startup
- hpm5301evklite/board
- hpm6800evk/startup
- libraries/hpm_sdk
- hpm6800evk/board
- hpm6e00evk/startup
- hpm6e00evk/board
- hpm6p00evk/startup
- hpm6p00evk/board
- hpm5e00evk/startup
- hpm5e00evk/board
bsp/hpmicro/README.md
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@@ -0,0 +1,193 @@
# HPMicro Board Support Package (BSP) Introduction
[中文页](README_zh.md) |
## Introduction
This document provides an overview of the HPMicro BSPs (Board Support Package) available in the RT-Thread repository. Each BSP is tailored for specific HPMicro development boards, offering necessary drivers and configurations to run RT-Thread seamlessly on RISC-V based HPMicro microcontrollers.
The document consists of the following parts:
- HPMicro BSP Overview
- Available BSPs
- Quick Start Guide
- Common Development Environment Setup
- References
By reading the Quick Start Guide section, developers can quickly get their hands on any HPMicro BSP and run RT-Thread on the board. Each individual BSP contains detailed documentation for specific board features and advanced usage.
## Available BSPs
Below is a comprehensive list of HPMicro BSPs currently supported:
| BSP Name | Supported Board | MCU | Description |
|----------|-----------------|-----|-------------|
| hpm5300evk | HPM5300EVK | HPM5361 | Development board for HPM5300 series |
| hpm5301evklite | HPM5301EVKLITE | HPM5301 | Lite version development board for HPM5301 |
| hpm5e00evk | HPM5E00EVK | HPM5E31 | Development board for HPM5E00 series |
| hpm6200evk | HPM6200EVK | HPM6200 | Development board for HPM6200 series |
| hpm6300evk | HPM6300EVK | HPM6360 | Development board for HPM6300 series with Ethernet support |
| hpm6750evk | HPM6750EVK | HPM6750 | Development board for HPM6750 series with dual-core RISC-V |
| hpm6750evk2 | HPM6750EVK2 | HPM6750 | Second generation development board for HPM6750 series |
| hpm6750evkmini | HPM6750EVKMINI | HPM6750 | Mini development board for HPM6750 series |
| hpm6800evk | HPM6800EVK | HPM6800 | Development board for HPM6800 series |
| hpm6e00evk | HPM6E00EVK | HPM6E00 | Development board for HPM6E00 series |
| hpm6p00evk | HPM6P00EVK | HPM6P00 | Development board for HPM6P00 series |
## Quick Start Guide
### Prerequisites
Before getting started with any HPMicro BSP, you need to prepare the following development environment:
#### 1. RT-Thread ENV
- Download and install [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
#### 2. RISC-V Toolchain
- Download the RISC-V toolchain: [riscv32-gnu-toolchain](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
- Extract it to a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
- Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
#### 3. OpenOCD for HPMicro
- Download OpenOCD: [rtt-debugger-support-package](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
- Extract it to a specified directory, for example: `C:\DevTools\openocd-hpmicro`
- Set environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
- For example: `C:\DevTools\openocd-hpmicro\bin`
### Getting Started with a Specific BSP
1. **Navigate to the desired BSP directory**:
```bash
cd rt-thread/bsp/hpmicro/<bsp_name>
```
2. **Configure the project**:
- Open RT-Thread ENV command-line
- Change directory to the BSP directory
- Run `menuconfig` to configure the project
3. **Build the project**:
```bash
scons -jN # N equals to the number of CPU cores
```
4. **Hardware Connection**:
- Switch BOOT pin to 2'b00
- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
5. **Download and Debug**:
- Use the provided OpenOCD scripts for downloading and debugging
- Refer to individual BSP README files for specific commands
### Running Results
Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
Connect the serial port of the board to the PC, communicate with it via a serial terminal tool (115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
```
\ | /
- RT - Thread Operating System
/ | \ 5.2.2 build Aug 16 2025 18:18:18
2006 - 2025 Copyright by RT-Thread team
msh >
```
## Common Peripheral Support
Most HPMicro BSPs support the following peripherals:
| **On-board Peripherals** | **Support** | **Note** |
| ------------------------ | ----------- | -------- |
| USB | √ | |
| QSPI Flash | √ | |
| GPIO | √ | |
| SPI | √ | |
| I2C | √ | |
| UART | √ | |
| PWM | √ | |
| RTC | √ | |
| On-Board Debugger | √ | ft2232 |
Additional peripherals may be supported depending on the specific board:
- **Ethernet**: Available on
- HPM6300EVK
- HPM6750EVK
- HPM6750EVK2
- HPM6750EVKMINI + ART-Pi Industry IO extension
- HPM6800EVK
- HPM6E00EVK
- HPM6P00EVK
- HPM5E00EVK
- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK and HPM5E00EVK
- **SDIO**: Available on HPM6300EVK, HPM6750EVKMINI, HPM6750EVK, HPM6750EVK2 and HPM6800EVK
- **Display/Audio**: Available on HPM6750EVK, HPM6800EVK, HPM6E00EVK，HPM6P00EVK
## Development Environment Setup
### Using Command Line Tools
1. Set up the environment variables as described in the Prerequisites section
2. Use `scons` for building
3. Use OpenOCD and GDB for debugging or use the Ozone + JLink for debugging
## Individual BSP Documentation
Each BSP contains its own detailed README file with:
- Board-specific hardware information
- Peripheral configuration details
- Specific download and debug commands
- Advanced features and examples
Please refer to the individual BSP directories for detailed documentation:
- `hpm5300evk/README.md`
- `hpm5301evklite/README.md`
- `hpm5e00evk/README.md`
- `hpm6200evk/README.md`
- `hpm6300evk/README.md`
- `hpm6750evk/README.md`
- `hpm6750evk2/README.md`
- `hpm6750evkmini/README.md`
- `hpm6800evk/README.md`
- `hpm6e00evk/README.md`
- `hpm6p00evk/README.md`
## Troubleshooting
### Common Issues
1. **Toolchain not found**: Ensure `RTT_RISCV_TOOLCHAIN` environment variable is set correctly
2. **OpenOCD connection failed**: Check USB connection and driver installation
3. **Build errors**: Verify all dependencies are installed and environment variables are set
4. **Serial communication issues**: Check baud rate (115200) and COM port settings
### Getting Help
- Check the individual BSP README files for board-specific issues
- Visit [RT-Thread Community](https://club.rt-thread.org/)
- Refer to [RT-Thread Documentation](https://www.rt-thread.org/document/site/)
## References
- [RT-Thread Document Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
- [RT-Thread ENV](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
- [HPMicro Official Website](https://www.hpmicro.com/)
- [HPMicro SDK Documentation](https://hpmicro.github.io/)
- [RISC-V Toolchain](https://github.com/riscv/riscv-gnu-toolchain)
## Contributing
Contributions to enhance existing BSPs or add new ones are welcome. Please follow the RT-Thread contribution guidelines and ensure that your BSP adheres to the project's standards.
For contributing to HPMicro BSPs:
1. Fork the `RT-Thread` repository
2. Create a feature branch
3. Make your changes following the existing code style
4. Test your changes thoroughly
5. Submit a pull request with a clear description
## License
This BSP is released under the [RT-Thread license](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE).
bsp/hpmicro/README_zh.md
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# HPMicro 板级支持包 (BSP) 介绍
[English](README.md) |
## 简介
本文档提供了 RT-Thread 仓库中可用的 HPMicro BSP（板级支持包）的概述。每个 BSP 都针对特定的 HPMicro 开发板进行了定制，提供必要的驱动程序和配置，以便在基于 RISC-V 的 HPMicro 微控制器上无缝运行 RT-Thread。
本文档包含以下部分：
- HPMicro BSP 概述
- 可用的 BSP
- 快速开始指南
- 通用开发环境设置
- 参考资料
通过阅读快速开始指南部分，开发者可以快速上手任何 HPMicro BSP 并在开发板上运行 RT-Thread。每个单独的 BSP 都包含特定开发板功能和高级用法的详细文档。
## 可用的 BSP
以下是当前支持的 HPMicro BSP 的完整列表：
| BSP 名称 | 支持的开发板 | MCU | 描述 |
|----------|-------------|-----|------|
| hpm5300evk | HPM5300EVK | HPM5361 | HPM5300 系列开发板 |
| hpm5301evklite | HPM5301EVKLITE | HPM5301 | HPM5301精简版开发板 |
| hpm5e00evk | HPM5E00EVK | HPM5E31 | HPM5E00 系列开发板 |
| hpm6200evk | HPM6200EVK | HPM6200 | HPM6200 系列开发板 |
| hpm6300evk | HPM6300EVK | HPM6360 | HPM6300 系列开发板，支持以太网 |
| hpm6750evk | HPM6750EVK | HPM6750 | HPM6750 系列开发板，双核 RISC-V |
| hpm6750evk2 | HPM6750EVK2 | HPM6750 | HPM6750 系列第二代开发板 |
| hpm6750evkmini | HPM6750EVKMINI | HPM6750 | HPM6750 系列迷你开发板 |
| hpm6800evk | HPM6800EVK | HPM6800 | HPM6800 系列开发板 |
| hpm6e00evk | HPM6E00EVK | HPM6E00 | HPM6E00 系列开发板 |
| hpm6p00evk | HPM6P00EVK | HPM6P00 | HPM6P00 系列开发板 |
## 快速开始指南
### 前提条件
在开始使用任何 HPMicro BSP 之前，您需要准备以下开发环境：
#### 1. RT-Thread ENV
- 下载并安装 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
#### 2. RISC-V 工具链
- 下载 RISC-V 工具链：[riscv32-gnu-toolchain](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
- 解压到指定目录，例如：`C:\DevTools\riscv32-gnu-toolchain`
- 设置环境变量 `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`
- 例如：`C:\DevTools\riscv32-gnu-toolchain\bin`
#### 3. HPMicro 专用 OpenOCD
- 下载 OpenOCD：[rtt-debugger-support-package](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
- 解压到指定目录，例如：`C:\DevTools\openocd-hpmicro`
- 设置环境变量 `OPENOCD_HPMICRO` 为 `<OPENOCD_HPMICRO_DIR>\bin`
- 例如：`C:\DevTools\openocd-hpmicro\bin`
### 使用特定 BSP 开始
1. **导航到所需的 BSP 目录**：
```bash
cd rt-thread/bsp/hpmicro/<bsp_name>
```
2. **配置项目**：
- 打开 RT-Thread ENV 命令行
- 切换到 BSP 目录
- 运行 `menuconfig` 来配置项目
3. **构建项目**：
```bash
scons -jN # N 等于 CPU 核心数
```
4. **硬件连接**：
- 将 BOOT 引脚切换到 2'b00
- 通过 TYPE-C 线缆将 `PWR_DEBUG` 端口连接到 PC
5. **下载和调试**：
- 使用提供的 OpenOCD 脚本进行下载和调试
- 参考各个 BSP 的 README 文件获取具体命令
### 运行结果
项目成功下载后，系统会自动运行。开发板上的 LED 会周期性闪烁。
将开发板的串口连接到 PC，通过串口终端工具（115200-8-1-N）与其通信。重置开发板后，将观察到 RT-Thread 的启动信息：
```
\ | /
- RT - Thread Operating System
/ | \ 5.2.2 build Aug 16 2025 18:18:18
2006 - 2025 Copyright by RT-Thread team
msh >
```
## 通用外设支持
大多数 HPMicro BSP 支持以下外设：
| **板载外设** | **支持** | **备注** |
| ------------ | -------- | -------- |
| USB | √ | |
| QSPI Flash | √ | |
| GPIO | √ | |
| SPI | √ | |
| I2C | √ | |
| UART | √ | |
| PWM | √ | |
| RTC | √ | |
| 板载调试器 | √ | ft2232 |
根据特定开发板，可能支持其他外设：
- **以太网**：在如下开发板上可用
- HPM6300EVK
- HPM6750EVK
- HPM6750EVK2
- HPM6750EVKMINI + ART-Pi Industry IO 扩展板
- HPM6800EVK
- HPM6E00EVK
- HPM6P00EVK
- HPM5E00EVK
- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK 和HPM5E00EVK
- **SDIO**：HPM6300EVK、HPM6750EVK 系列可用
- **显示/音频**：HPM6750EVK 系列可用
## 开发环境设置
### 使用命令行工具
1. 按照前提条件部分所述设置环境变量
2. 使用 `scons` 进行构建
3. 使用 OpenOCD 和 GDB 进行调试
## 各个 BSP 文档
每个 BSP 都包含自己的详细 README 文件，内容包括：
- 特定开发板的硬件信息
- 外设配置详情
- 具体的下载和调试命令
- 高级功能和示例
请参考各个 BSP 目录获取详细文档：
- `hpm5300evk/README.md`
- `hpm5301evklite/README.md`
- `hpm5e00evk/README.md`
- `hpm6200evk/README.md`
- `hpm6300evk/README.md`
- `hpm6750evk/README.md`
- `hpm6750evk2/README.md`
- `hpm6750evkmini/README.md`
- `hpm6800evk/README.md`
- `hpm6e00evk/README.md`
- `hpm6p00evk/README.md`
## 故障排除
### 常见问题
1. **找不到工具链**：确保 `RTT_RISCV_TOOLCHAIN` 环境变量设置正确
2. **OpenOCD 连接失败**：检查 USB 连接和驱动程序安装
3. **构建错误**：验证所有依赖项已安装且环境变量已设置
4. **串口通信问题**：检查波特率（115200）和 COM 端口设置
### 获取帮助
- 查看各个 BSP 的 README 文件了解特定开发板的问题
- 访问 [RT-Thread 社区](https://club.rt-thread.org/)
- 参考 [RT-Thread 文档](https://www.rt-thread.org/document/site/)
## 参考资料
- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
- [RT-Thread ENV](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
- [HPMicro 官方网站](https://www.hpmicro.com/)
- [HPMicro SDK 文档](https://hpmicro.github.io/)
- [RISC-V 工具链](https://github.com/riscv/riscv-gnu-toolchain)
## 贡献
欢迎对增强现有 BSP 或添加新 BSP 做出贡献。请遵循 RT-Thread 贡献指南，确保您的 BSP 符合项目标准。
为 HPMicro BSP 做出贡献：
1. Fork `RT-Thread` 仓库
2. 创建功能分支
3. 按照现有代码风格进行更改
4. 彻底测试您的更改
5. 提交带有清晰描述的拉取请求
## 许可证
此 BSP 在 [RT-Thread 许可证](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE) 下发布。
bsp/hpmicro/hpm5300evk/.config
+50 -3
View File
@@ -104,8 +104,6 @@
#
# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
# end of rt_strnlen options
# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
# end of klibc options
CONFIG_RT_NAME_MAX=8
@@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV32=y
#
# RT-Thread Components
#
@@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
# CONFIG_FINSH_USING_WORD_OPERATION is not set
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -376,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
# CONFIG_PKG_USING_ESP_HOSTED is not set
#
# Wi-Fi
@@ -483,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -572,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_MCOREDUMP is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -617,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ZDEBUG is not set
# CONFIG_PKG_USING_RVBACKTRACE is not set
# CONFIG_PKG_USING_HPATCHLITE is not set
# CONFIG_PKG_USING_THREAD_METRIC is not set
# end of tools packages
#
@@ -710,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -791,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_NUCLEI_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_MM32 is not set
@@ -833,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
# end of HC32 DDL Drivers
#
@@ -846,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
# end of NXP HAL & SDK Drivers
#
# NUVOTON Drivers
#
# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
# end of NUVOTON Drivers
#
# GD32 Drivers
#
# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
# end of GD32 Drivers
#
# HPMicro SDK
#
CONFIG_PKG_USING_HPM_SDK=y
CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
# CONFIG_PKG_USING_HPM_SDK_V110 is not set
CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
CONFIG_PKG_HPM_SDK_VER="latest"
# end of HPMicro SDK
# end of HAL & SDK Drivers
#
@@ -1017,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_SEAN_WS2812B is not set
# CONFIG_PKG_USING_IC74HC165 is not set
# CONFIG_PKG_USING_IST8310 is not set
# CONFIG_PKG_USING_ST7789_SPI is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@@ -1355,20 +1394,28 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# end of Arduino libraries
# end of RT-Thread online packages
CONFIG_SOC_HPM5300_SERIES=y
#
# Hardware Drivers Config
#
CONFIG_SOC_HPM5000=y
CONFIG_SOC_HPM5300=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_GPIO_IRQ_PRIORITY=1
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_UART0_RX_BUFSIZE=128
CONFIG_BSP_UART0_TX_BUFSIZE=0
CONFIG_BSP_UART0_IRQ_PRIORITY=1
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_GPTMR is not set
bsp/hpmicro/hpm5300evk/SConstruct
-11
View File
@@ -55,17 +55,6 @@ GDB = rtconfig.GDB
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
# include components
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
# includes rtt drivers
bsp/hpmicro/hpm5300evk/board/Kconfig
+326 -23
View File
@@ -1,8 +1,8 @@
menu "Hardware Drivers Config"
config SOC_HPM5000
config SOC_HPM5300
bool
select SOC_SERIES_HPM5300
select SOC_HPM5300_SERIES
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
@@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers"
bool "Enable GPIO"
select RT_USING_PIN if BSP_USING_GPIO
default n
if BSP_USING_GPIO
config BSP_GPIO_IRQ_PRIORITY
int "GPIO Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART
bool "Enable UART"
@@ -41,6 +47,10 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART0_IRQ_PRIORITY
int "UART0 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
@@ -64,6 +74,118 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART2_IRQ_PRIORITY
int "UART2 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 1024
config BSP_UART3_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART3_IRQ_PRIORITY
int "UART3 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART4
bool "Enable UART4"
default n
if BSP_USING_UART4
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_UART4_TX_USING_DMA
bool "Enable UART4 TX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_UART4_RX_BUFSIZE
int "Set UART4 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 1024
config BSP_UART4_TX_BUFSIZE
int "Set UART4 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART4_IRQ_PRIORITY
int "UART4 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART5
bool "Enable UART5"
default n
if BSP_USING_UART5
config BSP_UART5_RX_USING_DMA
bool "Enable UART5 RX DMA"
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
default n
config BSP_UART5_TX_USING_DMA
bool "Enable UART5 TX DMA"
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
default n
config BSP_UART5_RX_BUFSIZE
int "Set UART5 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 1024
config BSP_UART5_TX_BUFSIZE
int "Set UART5 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART5_IRQ_PRIORITY
int "UART5 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART6
bool "Enable UART6"
default n
if BSP_USING_UART6
config BSP_UART6_RX_USING_DMA
bool "Enable UART6 RX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
default n
config BSP_UART6_TX_USING_DMA
bool "Enable UART6 TX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
default n
config BSP_UART6_RX_BUFSIZE
int "Set UART6 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 1024
config BSP_UART6_TX_BUFSIZE
int "Set UART6 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART6_IRQ_PRIORITY
int "UART6 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART7
bool "Enable UART7"
@@ -95,29 +217,125 @@ menu "On-chip Peripheral Drivers"
default n
select RT_USING_SPI if BSP_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0"
default n
if BSP_USING_SPI0
config BSP_SPI0_USING_DMA
bool "Enable SPI0 DMA"
default n
config BSP_SPI0_IRQ_PRIORITY
int "SPI0 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI0 CS TYPE"
default BSP_SPI0_USING_SOFT_CS
config BSP_SPI0_USING_SOFT_CS
bool "Enable SPI0 software cs"
config BSP_SPI0_USING_HARD_CS
bool "Enable SPI0 hardware cs"
endchoice
choice
prompt "Select SPI0 IO mode"
default BSP_SPI0_USING_SINGLE_IO
config BSP_SPI0_USING_SINGLE_IO
bool "Enable SPI0 single IO mode"
config BSP_SPI0_USING_DUAL_IO
bool "Enable SPI0 dual IO mode"
config BSP_SPI0_USING_QUAD_IO
bool "Enable SPI0 quad IO mode"
endchoice
endif
config BSP_USING_SPI1
bool "Enable SPI1"
default y
if BSP_USING_SPI1
config BSP_SPI1_USING_DMA
bool "Enable SPI1 DMA"
default n
bool "Enable SPI1 DMA"
default n
config BSP_SPI1_IRQ_PRIORITY
int "SPI1 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI1 CS TYPE"
default BSP_SPI1_USING_SOFT_CS
config BSP_SPI1_USING_SOFT_CS
bool "Enable SPI1 software cs"
config BSP_SPI1_USING_HARD_CS
bool "Enable SPI1 hardware cs"
endchoice
choice
prompt "Select SPI1 IO mode"
default BSP_SPI1_USING_SINGLE_IO
config BSP_SPI1_USING_SINGLE_IO
bool "Enable SPI1 single IO mode"
config BSP_SPI1_USING_DUAL_IO
bool "Enable SPI1 dual IO mode"
config BSP_SPI1_USING_QUAD_IO
bool "Enable SPI1 quad IO mode"
endchoice
endif
config BSP_USING_SPI2
bool "Enable SPI2"
default n
if BSP_USING_SPI2
config BSP_SPI2_USING_DMA
bool "Enable SPI2 DMA"
default n
bool "Enable SPI2 DMA"
default n
config BSP_SPI2_IRQ_PRIORITY
int "SPI2 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI2 CS TYPE"
default BSP_SPI2_USING_SOFT_CS
config BSP_SPI2_USING_SOFT_CS
bool "Enable SPI2 software cs"
config BSP_SPI2_USING_HARD_CS
bool "Enable SPI2 hardware cs"
endchoice
choice
prompt "Select SPI2 IO mode"
default BSP_SPI2_USING_SINGLE_IO
config BSP_SPI2_USING_SINGLE_IO
bool "Enable SPI2 single IO mode"
config BSP_SPI2_USING_DUAL_IO
bool "Enable SPI2 dual IO mode"
config BSP_SPI2_USING_QUAD_IO
bool "Enable SPI2 quad IO mode"
endchoice
endif
config BSP_USING_SPI3
bool "Enable SPI3"
default n
if BSP_USING_SPI3
config BSP_SPI3_USING_DMA
bool "Enable SPI3 DMA"
default n
bool "Enable SPI3 DMA"
default n
config BSP_SPI3_IRQ_PRIORITY
int "SPI3 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI3 CS TYPE"
default BSP_SPI3_USING_SOFT_CS
config BSP_SPI3_USING_SOFT_CS
bool "Enable SPI3 software cs"
config BSP_SPI3_USING_HARD_CS
bool "Enable SPI3 hardware cs"
endchoice
choice
prompt "Select SPI3 IO mode"
default BSP_SPI3_USING_SINGLE_IO
config BSP_SPI3_USING_SINGLE_IO
bool "Enable SPI3 single IO mode"
config BSP_SPI3_USING_DUAL_IO
bool "Enable SPI3 dual IO mode"
config BSP_SPI3_USING_QUAD_IO
bool "Enable SPI3 quad IO mode"
endchoice
endif
endif
@@ -126,35 +344,98 @@ menu "On-chip Peripheral Drivers"
default n
select RT_USING_HWTIMER if BSP_USING_GPTMR
if BSP_USING_GPTMR
config BSP_USING_GPTMR0
bool "Enable GPTMR0"
depends on !HPM_USING_VECTOR_PREEMPTED_MODE
default n
if BSP_USING_GPTMR0
config BSP_GPTMR0_IRQ_PRIORITY
int "GPTMR0 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_GPTMR1
bool "Enable GPTMR1"
default n
if BSP_USING_GPTMR1
config BSP_GPTMR1_IRQ_PRIORITY
int "GPTMR1 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_GPTMR2
bool "Enable GPTMR2"
default n
if BSP_USING_GPTMR2
config BSP_GPTMR2_IRQ_PRIORITY
int "GPTMR2 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_GPTMR3
bool "Enable GPTMR3"
default n
if BSP_USING_GPTMR3
config BSP_GPTMR3_IRQ_PRIORITY
int "GPTMR3 Interrupt Priority"
range 1 7
default 1
endif
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
default n
select RT_USING_I2C if BSP_USING_I2C
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default y
if BSP_USING_I2C0
config BSP_I2C0_USING_DMA
bool "Enable I2C0 DMA"
default n
endif
if BSP_USING_I2C0
config BSP_I2C0_USING_DMA
bool "Enable I2C0 DMA"
default n
config BSP_I2C0_IRQ_PRIORITY
int "I2C0 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_I2C1
bool "Enable I2C1"
default n
if BSP_USING_I2C1
config BSP_I2C1_USING_DMA
bool "Enable I2C1 DMA"
default n
config BSP_I2C1_IRQ_PRIORITY
int "I2C1 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_I2C2
bool "Enable I2C2"
default n
if BSP_USING_I2C2
config BSP_I2C2_USING_DMA
bool "Enable I2C2 DMA"
default n
config BSP_I2C2_IRQ_PRIORITY
int "I2C2 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_I2C3
bool "Enable I2C3"
default n
if BSP_USING_I2C3
config BSP_I2C3_USING_DMA
bool "Enable I2C3 DMA"
default n
endif
if BSP_USING_I2C3
config BSP_I2C3_USING_DMA
bool "Enable I2C3 DMA"
default n
config BSP_I2C3_IRQ_PRIORITY
int "I2C3 Interrupt Priority"
range 1 7
default 1
endif
endif
menuconfig BSP_USING_XPI_FLASH
@@ -165,6 +446,7 @@ menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM if BSP_USING_PWM
menuconfig BSP_USING_USB
bool "Enable USB"
@@ -172,6 +454,7 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_USB
config BSP_USING_USB_DEVICE
bool "Enable USB Device"
select RT_USING_CACHE
default n
config BSP_USING_USB_HOST
bool "Enable USB HOST"
@@ -200,15 +483,39 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_MCAN0
bool "Enable MCAN0"
default n
if BSP_USING_MCAN0
config BSP_MCAN0_IRQ_PRIORITY
int "MCAN0 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_MCAN1
bool "Enable MCAN1"
default n
if BSP_USING_MCAN1
config BSP_MCAN1_IRQ_PRIORITY
int "MCAN1 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_MCAN2
bool "Enable MCAN2"
default n
if BSP_USING_MCAN2
config BSP_MCAN2_IRQ_PRIORITY
int "MCAN2 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_MCAN3
bool "Enable MCAN3"
default n
if BSP_USING_MCAN3
config BSP_MCAN3_IRQ_PRIORITY
int "MCAN3 Interrupt Priority"
range 1 7
default 1
endif
endif
menuconfig BSP_USING_ADC
@@ -226,11 +533,7 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
endif
endif
endmenu
endmenu
bsp/hpmicro/hpm5300evk/board/board.c
+105 -140
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@@ -13,8 +13,8 @@
#include "hpm_pllctlv2_drv.h"
#include "hpm_i2c_drv.h"
#include "hpm_pcfg_drv.h"
#include <rtconfig.h>
static board_timer_cb timer_cb;
/**
* @brief FLASH configuration option definitions:
@@ -49,7 +49,7 @@ static board_timer_cb timer_cb;
* 2 - Internal loopback
* 3 - External DQS
* [3:0] Frequency option
* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz
*
* option[2] (Effective only if the bit[3:0] in option[0] > 1)
* [31:20] Reserved
@@ -70,11 +70,11 @@ static board_timer_cb timer_cb;
* 0 - 4MB / 1 - 8MB / 2 - 16MB
*/
#if defined(FLASH_XIP) && FLASH_XIP
__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0};
#endif
#if defined(FLASH_UF2) && FLASH_UF2
ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
#endif
void board_init_console(void)
@@ -89,8 +89,6 @@ void board_init_console(void)
*/
init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
/* Configure the UART clock to 24MHz */
clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
cfg.type = BOARD_CONSOLE_TYPE;
@@ -143,7 +141,6 @@ void board_print_clock_freq(void)
void board_init(void)
{
init_xtal_pins();
init_py_pins_as_pgpio();
board_init_usb_dp_dm_pins();
@@ -176,7 +173,7 @@ void board_init_usb_dp_dm_pins(void)
} else {
uint8_t tmp;
tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); /* NOLINT */
clock_add_to_group(clock_usb0, 0);
usb_phy_disable_dp_dm_pulldown(HPM_USB0);
clock_remove_from_group(clock_usb0, 0);
@@ -205,67 +202,26 @@ void board_init_clock(void)
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_mchtmr0, 0);
clock_add_to_group(clock_rom, 0);
clock_add_to_group(clock_can0, 0);
clock_add_to_group(clock_can1, 0);
clock_add_to_group(clock_can2, 0);
clock_add_to_group(clock_can3, 0);
clock_add_to_group(clock_ptpc, 0);
clock_add_to_group(clock_gptmr0, 0);
clock_add_to_group(clock_gptmr1, 0);
clock_add_to_group(clock_gptmr2, 0);
clock_add_to_group(clock_gptmr3, 0);
clock_add_to_group(clock_i2c0, 0);
clock_add_to_group(clock_i2c1, 0);
clock_add_to_group(clock_i2c2, 0);
clock_add_to_group(clock_i2c3, 0);
clock_add_to_group(clock_spi0, 0);
clock_add_to_group(clock_spi1, 0);
clock_add_to_group(clock_spi2, 0);
clock_add_to_group(clock_spi3, 0);
clock_add_to_group(clock_uart0, 0);
clock_add_to_group(clock_uart1, 0);
clock_add_to_group(clock_uart2, 0);
clock_add_to_group(clock_uart3, 0);
clock_add_to_group(clock_uart4, 0);
clock_add_to_group(clock_uart5, 0);
clock_add_to_group(clock_uart6, 0);
/* group0[1] */
clock_add_to_group(clock_uart7, 0);
clock_add_to_group(clock_watchdog0, 0);
clock_add_to_group(clock_watchdog1, 0);
clock_add_to_group(clock_mbx0, 0);
clock_add_to_group(clock_tsns, 0);
clock_add_to_group(clock_crc0, 0);
clock_add_to_group(clock_adc0, 0);
clock_add_to_group(clock_adc1, 0);
clock_add_to_group(clock_dac0, 0);
clock_add_to_group(clock_dac1, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_opa0, 0);
clock_add_to_group(clock_opa1, 0);
clock_add_to_group(clock_mot0, 0);
clock_add_to_group(clock_rng, 0);
clock_add_to_group(clock_sdp, 0);
clock_add_to_group(clock_kman, 0);
clock_add_to_group(clock_gpio, 0);
clock_add_to_group(clock_hdma, 0);
clock_add_to_group(clock_xpi0, 0);
clock_add_to_group(clock_usb0, 0);
clock_add_to_group(clock_ptpc, 0);
/* Connect Group0 to CPU0 */
clock_connect_group_to_cpu(0, 0);
/* Bump up DCDC voltage to 1175mv */
pcfg_dcdc_set_voltage(HPM_PCFG, 1175);
/* Bump up DCDC voltage to 1275mv */
pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
/* Configure CPU to 480MHz, AXI/AHB to 160MHz */
sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
/* Configure PLL0 Post Divider */
pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 960MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 600MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 400MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0); /* PLL0CLK0: 960MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p6); /* PLL0CLK1: 600MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk2, pllctlv2_div_2p4); /* PLL0CLK2: 400MHz */
/* Configure PLL0 Frequency to 960MHz */
pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000);
pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, 960000000);
clock_update_core_clock();
@@ -283,6 +239,9 @@ void board_delay_ms(uint32_t ms)
clock_cpu_delay_ms(ms);
}
#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
static board_timer_cb timer_cb;
SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
void board_timer_isr(void)
{
if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
@@ -290,7 +249,6 @@ void board_timer_isr(void)
timer_cb();
}
}
SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
void board_timer_create(uint32_t ms, board_timer_cb cb)
{
@@ -310,6 +268,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb)
gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
}
#endif
void board_init_gpio_pins(void)
{
@@ -323,15 +282,19 @@ void board_init_led_pins(void)
gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
}
void board_init_usb_pins(void)
void board_init_usb(USB_Type *ptr)
{
init_usb_pins();
usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
/* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
board_delay_ms(100);
if (ptr == HPM_USB0) {
init_usb_pins(ptr);
clock_add_to_group(clock_usb0, 0);
/* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
/* usb_phy_using_internal_vbus(BOARD_USB); */
usb_hcd_set_power_ctrl_polarity(ptr, true);
/* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
board_delay_ms(100);
/* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
/* usb_phy_using_internal_vbus(ptr); */
}
}
void board_led_write(uint8_t state)
@@ -383,18 +346,12 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
}
void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
{
(void) usb_index;
(void) level;
}
uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)
{
uint32_t freq = 0;
if (ptr == HPM_ADC0) {
if (clk_src_ahb) {
if (ptr == (void *)HPM_ADC0) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
} else {
@@ -402,10 +359,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
}
clock_add_to_group(clock_adc0, 0);
freq = clock_get_frequency(clock_adc0);
} else if (ptr == HPM_ADC1) {
if (clk_src_ahb) {
} else if (ptr == (void *)HPM_ADC1) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
} else {
@@ -413,7 +370,7 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U);
}
clock_add_to_group(clock_adc1, 0);
freq = clock_get_frequency(clock_adc1);
}
@@ -425,6 +382,17 @@ void board_init_adc16_pins(void)
init_adc_pins();
}
void board_init_acmp_pins(void)
{
init_acmp_pins();
}
void board_init_acmp_clock(ACMP_Type *ptr)
{
(void)ptr;
clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
}
uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
{
uint32_t freq = 0;
@@ -438,7 +406,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
clock_set_dac_source(clock_dac0, clk_dac_src_ana2);
clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2);
}
clock_add_to_group(clock_dac0, 0);
freq = clock_get_frequency(clock_dac0);
} else if (ptr == HPM_DAC1) {
if (clk_src_ahb == true) {
@@ -449,7 +417,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
clock_set_dac_source(clock_dac1, clk_dac_src_ana3);
clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
}
clock_add_to_group(clock_dac1, 0);
freq = clock_get_frequency(clock_dac1);
}
@@ -487,17 +455,6 @@ uint32_t board_init_can_clock(MCAN_Type *ptr)
return freq;
}
uint32_t board_init_pwm_clock(PWM_Type *ptr)
{
uint32_t freq = 0;
(void) ptr;
clock_add_to_group(clock_mot0, 0);
freq = clock_get_frequency(clock_mot0);
return freq;
}
void board_init_rgb_pwm_pins(void)
{
init_led_pins_as_pwm();
@@ -536,26 +493,19 @@ uint32_t board_init_uart_clock(UART_Type *ptr)
{
uint32_t freq = 0U;
if (ptr == HPM_UART0) {
clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
clock_add_to_group(clock_uart0, 0);
freq = clock_get_frequency(clock_uart0);
} else if (ptr == HPM_UART1) {
clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
clock_add_to_group(clock_uart1, 0);
freq = clock_get_frequency(clock_uart1);
} else if (ptr == HPM_UART2) {
clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 8);
clock_add_to_group(clock_uart2, 0);
freq = clock_get_frequency(clock_uart2);
} else if (ptr == HPM_UART3) {
clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 8);
clock_add_to_group(clock_uart3, 0);
freq = clock_get_frequency(clock_uart3);
} else if (ptr == HPM_UART7) {
clock_set_source_divider(clock_uart7, clk_src_pll0_clk2, 6); /* 80MHz */
clock_add_to_group(clock_uart7, 0);
freq = clock_get_frequency(clock_uart7);
}
return freq;
}
@@ -577,39 +527,51 @@ void board_i2c_bus_clear(I2C_Type *ptr)
printf("I2C bus is ready\n");
return;
}
i2s_gen_reset_signal(ptr, 9);
i2c_gen_reset_signal(ptr, 9);
board_delay_ms(100);
printf("I2C bus is cleared\n");
}
uint32_t board_init_i2c_clock(I2C_Type *ptr)
{
uint32_t freq = 0;
if (ptr == HPM_I2C0) {
clock_add_to_group(clock_i2c0, 0);
freq = clock_get_frequency(clock_i2c0);
} else if (ptr == HPM_I2C1) {
clock_add_to_group(clock_i2c1, 0);
freq = clock_get_frequency(clock_i2c1);
} else if (ptr == HPM_I2C2) {
clock_add_to_group(clock_i2c2, 0);
freq = clock_get_frequency(clock_i2c2);
} else if (ptr == HPM_I2C3) {
clock_add_to_group(clock_i2c3, 0);
freq = clock_get_frequency(clock_i2c3);
} else {
;
}
return freq;
}
void board_init_i2c(I2C_Type *ptr)
{
i2c_config_t config;
hpm_stat_t stat;
uint32_t freq;
if (ptr == NULL) {
return;
}
freq = board_init_i2c_clock(ptr);
init_i2c_pins(ptr);
board_i2c_bus_clear(ptr);
clock_add_to_group(clock_i2c0, 0);
clock_add_to_group(clock_i2c1, 0);
clock_add_to_group(clock_i2c2, 0);
clock_add_to_group(clock_i2c3, 0);
/* Configure the I2C clock to 24MHz */
clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
config.i2c_mode = i2c_mode_normal;
config.is_10bit_addressing = false;
freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
stat = i2c_init_master(ptr, freq, &config);
if (stat != status_success) {
printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
while (1) {
}
}
}
void board_init_adc_qeiv2_pins(void)
@@ -629,34 +591,37 @@ void board_lin_transceiver_control(bool enable)
}
}
void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
init_gptmr_channel_pin(ptr, channel, as_comp);
}
void board_init_clk_ref_pin(void)
{
init_clk_ref_pin();
}
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
{
uint32_t freq = 0;
clock_name_t gptmr_clock =0;
uint32_t HPM_GPTMR = (uint32_t)ptr;
bool gptmr_valid = true;
switch(HPM_GPTMR){
case HPM_GPTMR0_BASE:
gptmr_clock = clock_gptmr0;
break;
case HPM_GPTMR1_BASE:
gptmr_clock = clock_gptmr1;
break;
case HPM_GPTMR2_BASE:
gptmr_clock = clock_gptmr2;
break;
case HPM_GPTMR3_BASE:
gptmr_clock = clock_gptmr3;
break;
default:
gptmr_valid = false;
}
if(gptmr_valid)
{
clock_add_to_group(gptmr_clock, 0);
clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4);
freq = clock_get_frequency(gptmr_clock);
uint32_t freq = 0U;
if (ptr == HPM_GPTMR0) {
clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr0);
} else if (ptr == HPM_GPTMR1) {
clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr1);
} else if (ptr == HPM_GPTMR2) {
clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr2);
} else if (ptr == HPM_GPTMR3) {
clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr3);
} else if (ptr == HPM_PTMR) {
clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_ptmr);
} else {
/* Not supported */
}
return freq;
}
bsp/hpmicro/hpm5300evk/board/board.h
+158 -44
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023-2024 HPMicro
* Copyright (c) 2023-2025 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -23,6 +23,7 @@
/* ACMP desction */
#define BOARD_ACMP HPM_ACMP
#define BOARD_ACMP_CLK clock_acmp0
#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1
#define BOARD_ACMP_IRQ IRQn_ACMP_1
#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */
@@ -41,14 +42,24 @@
/* uart section */
#ifndef BOARD_APP_UART_BASE
#define BOARD_APP_UART_BASE HPM_UART2
#define BOARD_APP_UART_IRQ IRQn_UART2
#define BOARD_APP_UART_BASE HPM_UART2
#define BOARD_APP_UART_IRQ IRQn_UART2
#define BOARD_APP_UART_BAUDRATE (115200UL)
#define BOARD_APP_UART_CLK_NAME clock_uart2
#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX
#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX
#endif
#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PA26
/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */
#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG0
#define BOARD_UART_TRGM HPM_TRGM0
#define BOARD_UART_TRGM_GPTMR HPM_GPTMR3
#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr3
#define BOARD_UART_TRGM_GPTMR_CH 2
#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2
/* uart lin sample section */
#define BOARD_UART_LIN HPM_UART3
#define BOARD_UART_LIN_IRQ IRQn_UART3
@@ -56,7 +67,6 @@
#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOA
#define BOARD_UART_LIN_TX_PIN (15U) /* PA15 should align with used pin in pinmux configuration */
#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
#ifndef BOARD_CONSOLE_TYPE
#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
@@ -64,9 +74,9 @@
#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
#ifndef BOARD_CONSOLE_UART_BASE
#define BOARD_CONSOLE_UART_BASE HPM_UART0
#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
#define BOARD_CONSOLE_UART_IRQ IRQn_UART0
#define BOARD_CONSOLE_UART_BASE HPM_UART0
#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
#define BOARD_CONSOLE_UART_IRQ IRQn_UART0
#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
#endif
@@ -82,6 +92,8 @@
/* rtthread-nano finsh section */
#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE
#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME
#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ
/* modbus sample section */
#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE
@@ -126,13 +138,12 @@
/* 12V Power Enable for lin transceiver */
#define BOARD_SUPPORT_LIN_TRANSCEIVER_CONTROL 1
#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0
#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_12V_EN_GPIO_PIN 24
#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL HPM_GPIO0
#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_LIN_TRANSCEIVER_GPIO_PIN 13
#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0
#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_12V_EN_GPIO_PIN 24
#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL HPM_GPIO0
#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_LIN_TRANSCEIVER_GPIO_PIN 13
/* gpiom section */
#define BOARD_APP_GPIOM_BASE HPM_GPIOM
@@ -144,6 +155,7 @@
#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_APP_GPIO_PIN 9
#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A
#define BOARD_BUTTON_PRESSED_VALUE 0
/* spi section */
#define BOARD_APP_SPI_BASE HPM_SPI1
@@ -164,12 +176,14 @@
#define BOARD_APP_ADC16_IRQn IRQn_ADC0
#define BOARD_APP_ADC16_CH_1 (13U)
#define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0)
#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0
#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0
#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI
#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0
#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0
#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0
#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI
#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
@@ -206,6 +220,7 @@
#define BOARD_APP_TRGM HPM_TRGM0
#define BOARD_APP_PWM_IRQ IRQn_PWM0
#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM0_SYNCI
#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0
/*BLDC pwm*/
/*PWM define*/
@@ -231,15 +246,16 @@
/*HALL define*/
/*RDC*/
#define BOARD_RDC_BASE HPM_RDC
#define BOARD_RDC_TRGM HPM_TRGM0
#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC_TRGO_0
#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0
#define BOARD_RDC_TRG_ADC_NUM TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_RDC_TRG_IN HPM_TRGM0_INPUT_SRC_RDC_TRGO_0
#define BOARD_RDC_TRG_OUT TRGM_TRGOCFG_MOT_GPIO0
#define BOARD_RDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_RDC_ADC_I_BASE HPM_ADC0
#define BOARD_RDC_ADC_Q_BASE HPM_ADC1
#define BOARD_RDC_ADC_I_CHN (5U)
#define BOARD_RDC_ADC_Q_CHN (6U)
#define BOARD_RDC_ADC_IRQn IRQn_ADC0
#define BOARD_RDC_IRQ IRQn_RDC
#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete
#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A
@@ -250,16 +266,44 @@
#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U)
#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0
#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U)
#define BOARD_BLDC_QEI_ADC_MATRIX_ADC0 trgm_adc_matrix_output_to_qei1_adc0
#define BOARD_BLDC_QEI_ADC_MATRIX_ADC1 trgm_adc_matrix_output_to_qei1_adc1
#define BOARD_APP_QEIV2_BASE HPM_QEI1
#define BOARD_APP_QEIV2_IRQ IRQn_QEI1
#define BOARD_APP_QEI_CLOCK_SOURCE clock_mot0
#define BOARD_APP_QEI_ADC_COS_BASE HPM_ADC0
#define BOARD_APP_QEI_ADC_COS_CHN (4U)
#define BOARD_APP_QEI_ADC_SIN_BASE HPM_ADC1
#define BOARD_APP_QEI_ADC_SIN_CHN (5U)
#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_qei1_adc0
#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei1_adc1
#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc0
#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc1
#define BOARD_APP_QEI_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A
/*Timer define*/
#define BOARD_BLDC_TMR_1MS HPM_GPTMR2
#define BOARD_BLDC_TMR_CH 0
#define BOARD_BLDC_TMR_CMP 0
#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2
#define BOARD_BLDC_TMR_CLOCK clock_gptmr2
#define BOARD_BLDC_TMR_RELOAD (100000U)
/* BLDC PARAM */
#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f)
#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f)
#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f)
#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f)
#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f)
#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f)
#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f)
#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f)
#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f)
#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f)
#define BOARD_BLDC_HFI_PLL_KP (10.0f)
#define BOARD_BLDC_HFI_PLL_KI (1.0f)
/*adc*/
#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16)
#define BOARD_BLDC_ADC_U_BASE HPM_ADC0
@@ -275,23 +319,38 @@
#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A
#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U)
#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U)
#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
#define BOARD_BLDC_DMA_MUX_SRC HPM_DMA_SRC_MOT_0
#define BOARD_BLDC_DMA_CHN (0U)
#define BOARD_BLDC_DMA_TRG_DST TRGM_TRGOCFG_TRGM_DMA0
#define BOARD_BLDC_DMA_TRG_SRC HPM_TRGM0_DMA_SRC_TRGM0
#define BOARD_BLDC_DMA_TRG_INDEX TRGM_DMACFG_0
#define BOARD_BLDC_DMA_TRG_CMP_INDEX (9U)
#define BOARD_BLDC_DMA_TRG_IN HPM_TRGM0_INPUT_SRC_PWM0_CH9REF
/* PLB */
#define BOARD_PLB_CLOCK_NAME clock_mot0
#define BOARD_PLB_COUNTER HPM_PLB
#define BOARD_PLB_PWM_BASE HPM_PWM0
#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0
#define BOARD_PLB_TRGM HPM_TRGM0
#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF)
#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00)
#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02)
#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO2)
#define BOARD_PLB_IN_PWM_TRG (TRGM_TRGOCFG_PLB_IN_00)
#define BOARD_PLB_IN_PWM_PULSE_TRG (TRGM_TRGOCFG_PLB_IN_02)
#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT16)
#define BOARD_PLB_TO_TRG_IN (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
#define BOARD_PLB_TRG_OUT (HPM_TRGM0_OUTPUT_SRC_TRGM0_P2)
#define BOARD_PLB_IO_TRG_SHIFT (2)
#define BOARD_PLB_PWM_CMP (8U)
#define BOARD_PLB_PWM_CHN (8U)
#define BOARD_PLB_CHN plb_chn0
#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P4
#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2
#define BOARD_PLB_FILTER_IO_TRG_SHIFT (2)
/* QEO */
#define BOARD_QEO HPM_QEO0
#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0
@@ -302,13 +361,12 @@
/* SEI */
#define BOARD_SEI HPM_SEI
#define BOARD_SEI_CTRL SEI_CTRL_1
#define BOARD_SEI_IRQn IRQn_SEI1
/* USB */
#define BOARD_USB HPM_USB0
#define BOARD_SEI_IRQn IRQn_SEI0_1
#define BOARD_SEI_CLOCK_NAME clock_mot0
/* OPAMP */
#define BOARD_APP_OPAMP HPM_OPAMP0
#define BOARD_APP_OPAMP HPM_OPAMP0
#define BOARD_APP_OPAMP_CLOCK clock_opa0
#ifndef BOARD_SHOW_CLOCK
#define BOARD_SHOW_CLOCK 1
@@ -323,11 +381,62 @@
#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2
#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2
#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0
#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0
#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0
#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR
#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1
#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR
#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr
/* Threadx Definitions */
#define BOARD_THREADX_TIMER HPM_GPTMR2
#define BOARD_THREADX_TIMER_CHANNEL 1
#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2
#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2
#define BOARD_THREADX_TIMER HPM_GPTMR2
#define BOARD_THREADX_TIMER_CHANNEL 1
#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2
#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2
#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR
#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1
#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR
#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
/* uC/OS-III Definitions */
#define BOARD_UCOS_TIMER HPM_GPTMR2
#define BOARD_UCOS_TIMER_CHANNEL 1
#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR2
#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr2
/* i2s over spi Section*/
#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0
#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_I2S_SPI_CS_GPIO_PIN 11
#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA11
#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR0
#define BOARD_GPTMR_I2S_MCLK_CHANNEL 3
#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR0
#define BOARD_GPTMR_I2S_LRCK_CHANNEL 1
#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0
#define BOARD_GPTMR_I2S_BLCK_CHANNEL 0
#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0
#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0
#define BOARD_GPTMR_I2S_FINSH_CHANNEL 2
#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0
#define BOARD_APP_CLK_REF_PIN_NAME "P1[15] (PA30)"
#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0
#define BOARD_APP_CLK_REF_SRC_NAME clk_src_pll1_clk1
#define BOARD_APP_PLLCTLV2_TEST_PLL pllctlv2_pll1
#define BOARD_APP_PLLCTLV2_TEST_PLL_CLK pllctlv2_clk1
#define BOARD_APP_PLLCTLV2_TEST_PLL_NAME clk_pll1clk1
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
@@ -338,16 +447,17 @@ void board_init(void);
void board_init_console(void);
void board_init_gpio_pins(void);
void board_init_led_pins(void);
void board_init_usb_pins(void);
void board_init_usb(USB_Type *ptr);
void board_led_write(uint8_t state);
void board_led_toggle(void);
void board_init_uart(UART_Type *ptr);
uint32_t board_init_spi_clock(SPI_Type *ptr);
void board_init_spi_pins(SPI_Type *ptr);
void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb);
uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus);
void board_init_adc16_pins(void);
uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb);
void board_init_acmp_pins(void);
void board_init_acmp_clock(ACMP_Type *ptr);
void board_init_can(MCAN_Type *ptr);
uint32_t board_init_can_clock(MCAN_Type *ptr);
void board_init_rgb_pwm_pins(void);
@@ -372,13 +482,17 @@ void board_init_pmp(void);
uint32_t board_init_uart_clock(UART_Type *ptr);
void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
uint32_t board_init_i2c_clock(I2C_Type *ptr);
void board_init_i2c(I2C_Type *ptr);
void board_init_adc_qeiv2_pins(void);
void board_lin_transceiver_control(bool enable);
void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
void board_init_clk_ref_pin(void);
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
uint32_t board_init_pwm_clock(PWM_Type *ptr);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld → bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld
+68 -34
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +14,7 @@ MEMORY
{
XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K
DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K
DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768
AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K
}
@@ -41,22 +41,25 @@ SECTIONS
.start __app_load_addr__ : {
. = ALIGN(8);
KEEP(*(.start))
. = ALIGN(16);
} > XPI0
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
.vectors : AT(__vector_load_addr__) {
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_start__ = .;
KEEP(*(.vector_table))
KEEP(*(.isr_vector))
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_end__ = .;
} > ILM
.fast : AT(etext + __data_end__ - __tdata_start__) {
. = ALIGN(8);
.fast : AT(__fast_load_addr__) {
. = ALIGN(16);
__ramfunc_start__ = .;
*(.fast)
*(.fast.*)
. = ALIGN(16);
/* RT-Thread Core Start */
KEEP(*context_gcc.o(.text* .rodata*))
@@ -77,12 +80,12 @@ SECTIONS
KEEP(*mempool.o (.text .text* .rodata .rodata*))
/* RT-Thread Core End */
. = ALIGN(8);
. = ALIGN(16);
__ramfunc_end__ = .;
} > ILM
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
. = ALIGN(8);
.text (__vector_load_addr__ + SIZEOF(.vectors)) : {
. = ALIGN(16);
*(.text)
*(.text*)
*(.rodata)
@@ -107,12 +110,6 @@ SECTIONS
* RT-Thread related sections - Start
*
*********************************************/
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@@ -146,6 +143,20 @@ SECTIONS
} > XPI0
.eh_frame :
{
__eh_frame_start = .;
KEEP(*(.eh_frame))
__eh_frame_end = .;
} > XPI0
.eh_frame_hdr :
{
KEEP(*(.eh_frame_hdr))
} > XPI0
__eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
__eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
.rel : {
KEEP(*(.rel*))
} > XPI0
@@ -158,19 +169,14 @@ SECTIONS
KEEP(*(.fast_ram))
} > DLM
.bss(NOLOAD) : {
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
/* Note: the .tbss and .tdata section should be adjacent */
@@ -178,22 +184,26 @@ SECTIONS
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -221,10 +231,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -245,6 +255,26 @@ SECTIONS
PROVIDE (_edata = .);
PROVIDE (edata = .);
} > DLM
__fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
__fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
.heap(NOLOAD) : {
@@ -265,7 +295,8 @@ SECTIONS
PROVIDE( __rt_rvstack = . );
} > DLM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -276,8 +307,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > DLM
bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld → bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld
+83 -65
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000;
MEMORY
{
ILM (wx) : ORIGIN = 0, LENGTH = 128K
DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
DLM (w) : ORIGIN = 0x80300, LENGTH = 96K - 768
NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE
AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k
}
SECTIONS
@@ -30,10 +30,6 @@ SECTIONS
KEEP(*(.vector_table))
. = ALIGN(8);
} > ILM
.fast_ram (NOLOAD) : {
KEEP(*(.fast_ram))
} > ILM
.text : {
. = ALIGN(8);
@@ -56,7 +52,7 @@ SECTIONS
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(8);
/*********************************************
*
* RT-Thread related sections - Start
@@ -92,28 +88,74 @@ SECTIONS
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
__usbh_class_info_end__ = .;
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
} > ILM
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.tdata : AT(etext) {
.rel : {
KEEP(*(.rel*))
} > DLM
.fast_ram (NOLOAD) : {
KEEP(*(.fast_ram))
} > ILM
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
} > ILM
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
/* Note: .tbss and .tdata should be adjacent */
.tbss(NOLOAD) : {
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
*(.data)
*(.data*)
*(.sdata)
@@ -138,10 +180,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -164,43 +206,39 @@ SECTIONS
PROVIDE (edata = .);
} > DLM
.fast : AT(etext + __data_end__ - __tdata_start__) {
__fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
.fast : AT(__fast_load_addr__) {
. = ALIGN(8);
PROVIDE(__ramfunc_start__ = .);
*(.fast)
. = ALIGN(8);
PROVIDE(__ramfunc_end__ = .);
} > DLM
.rel : {
KEEP(*(.rel*))
} > DLM
.bss(NOLOAD) : {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
__noncacheable_init_end__ = .;
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
} > NONCACHEABLE_RAM
/* Note: .tbss and .tdata should be adjacent */
.tbss(NOLOAD) : {
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
.stack(NOLOAD) : {
. = ALIGN(8);
__stack_base__ = .;
@@ -221,24 +259,4 @@ SECTIONS
.ahb_sram (NOLOAD) : {
KEEP(*(.ahb_sram))
} > AHB_SRAM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
__noncacheable_init_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
}
bsp/hpmicro/hpm5300evk/board/pinmux.c
+80 -37
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023-2025 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -15,15 +15,6 @@
#include "board.h"
#include "pinmux.h"
void init_xtal_pins(void)
{
/* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */
/*
* HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
* HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
*/
}
void init_py_pins_as_pgpio(void)
{
/* Set PY00-PY05 default function to PGPIO */
@@ -48,10 +39,6 @@ void init_uart_pins(UART_Type *ptr)
/* using for uart_lin function */
HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_UART3_RXD;
HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_UART3_TXD;
} else if (ptr == HPM_UART7) {
/* using for uart_lin function */
HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_UART7_TXD;
HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_UART7_RXD;
} else {
;
}
@@ -115,6 +102,13 @@ void init_spi_pins(SPI_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
/* set max frequency slew rate(200M) */
HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
}
}
@@ -126,6 +120,13 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
/* set max frequency slew rate(200M) */
HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
}
}
@@ -136,6 +137,7 @@ void init_gptmr_pins(GPTMR_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0;
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0;
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
}
}
@@ -197,31 +199,27 @@ void init_adc_qeiv2_pins(void)
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */
}
void init_usb_pins(void)
void init_usb_pins(USB_Type *ptr)
{
/* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */
/*
* HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
* HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
*/
if (ptr == HPM_USB0) {
/* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */
/*
* HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
* HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
*/
/* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */
/*
* HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
* HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
*/
/* USB0_ID */
HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
/* USB0_OC */
HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
/* USB0_PWR */
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
/* USB0_ID */
HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
/* USB0_OC */
HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
/* USB0_PWR */
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
/* PY port IO needs to configure PIOC as well */
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
/* PY port IO needs to configure PIOC as well */
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
}
}
void init_can_pins(MCAN_Type *ptr)
@@ -254,11 +252,18 @@ void init_dac_pins(DAC_Type *ptr)
}
}
void init_plb_pins(void)
void init_plb_pulse_pins(void)
{
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02;
}
void init_plb_filter_pins(void)
{
HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0);
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_TRGM0_P_04;
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02;
}
void init_qeo_pins(QEO_Type *ptr)
{
if (ptr == HPM_QEO0) {
@@ -323,3 +328,41 @@ void init_opamp_pins(void)
HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
}
/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
void init_uart_break_signal_pin(void)
{
HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26;
}
void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
if (ptr == HPM_GPTMR0) {
if (as_comp) {
switch (channel) {
case 0:
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0;
break;
case 1:
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
break;
case 3:
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
break;
default:
break;
}
} else {
if (channel == 0) {
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0;
}
}
}
}
void init_clk_ref_pin(void)
{
HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_SOC_REF0;
}
bsp/hpmicro/hpm5300evk/board/pinmux.h
+8 -4
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 HPMicro
* Copyright (c) 2022-2025 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -11,7 +11,6 @@
#ifdef __cplusplus
extern "C" {
#endif
void init_xtal_pins(void);
void init_py_pins_as_pgpio(void);
void init_uart_pins(UART_Type *ptr);
void init_uart_pin_as_gpio(UART_Type *ptr);
@@ -28,12 +27,13 @@ void init_pwm_pins(PWM_Type *ptr);
void init_adc_pins(void);
void init_adc_bldc_pins(void);
void init_adc_qeiv2_pins(void);
void init_usb_pins(void);
void init_usb_pins(USB_Type *ptr);
void init_can_pins(MCAN_Type *ptr);
void init_dac_pins(DAC_Type *ptr);
void init_led_pins_as_gpio(void);
void init_led_pins_as_pwm(void);
void init_plb_pins(void);
void init_plb_pulse_pins(void);
void init_plb_filter_pins(void);
void init_qeo_pins(QEO_Type *ptr);
void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
void init_rdc_pin(void);
@@ -42,6 +42,10 @@ void init_qeiv2_ab_pins(QEIV2_Type *ptr);
void init_qeiv2_abz_pins(QEIV2_Type *ptr);
void init_opamp_pins(void);
void init_lin_transceiver_ctrl_pin(void);
void init_uart_break_signal_pin(void);
void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
void init_clk_ref_pin(void);
#ifdef __cplusplus
}
#endif
bsp/hpmicro/hpm5300evk/board/rtt_board.c
+51 -3
View File
@@ -52,7 +52,7 @@ void rtt_board_init(void)
os_tick_config();
/* Configure the USB pins*/
board_init_usb_pins();
board_init_usb(HPM_USB0);
/* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
rt_hw_uart_init();
@@ -63,6 +63,7 @@ void rtt_board_init(void)
void app_init_led_pins(void)
{
board_init_led_pins();
gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
}
@@ -95,7 +96,7 @@ void rt_hw_console_output(const char *str)
void app_init_usb_pins(void)
{
board_init_usb_pins();
board_init_usb(HPM_USB0);
}
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
@@ -107,7 +108,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
void rt_hw_cpu_reset(void)
{
HPM_PPOR->RESET_ENABLE = (1UL << 31);
HPM_PPOR->RESET_ENABLE |= (1UL << 31);
HPM_PPOR->SOFTWARE_RESET = 1000U;
while(1) {
@@ -127,3 +128,50 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
}
}
#endif
uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
{
uint32_t freq = 0;
if (ptr == HPM_ADC0) {
if (clk_src_ahb) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
}
clock_add_to_group(clock_adc0, 0);
freq = clock_get_frequency(clock_adc0);
} else if (ptr == HPM_ADC1) {
if (clk_src_ahb) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U);
}
clock_add_to_group(clock_adc1, 0);
freq = clock_get_frequency(clock_adc1);
}
return freq;
}
uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr)
{
uint32_t freq = 0;
(void) ptr;
clock_add_to_group(clock_mot0, 0);
freq = clock_get_frequency(clock_mot0);
return freq;
}
#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
extern void hpm_isr_usb0(void);
RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
#endif
bsp/hpmicro/hpm5300evk/board/rtt_board.h
+12 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 hpmicro
* Copyright (c) 2021 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -10,8 +10,10 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <drv_gpio.h>
#include "board.h"
/* gpio section */
#define APP_LED0 (0U)
#define APP_LED0_PIN_NUM GET_PIN(A, 23)
#define APP_LED_ON (1)
#define APP_LED_OFF (0)
@@ -19,6 +21,11 @@
/* mchtimer section */
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
#define BOARD_OS_TIMER HPM_GPTMR0
#define BOARD_OS_TIMER_CH 1
#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0
#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
/* CAN section */
#define BOARD_CAN_NAME "can0"
#define BOARD_CAN_HWFILTER_INDEX (0U)
@@ -31,6 +38,10 @@
#define BOARD_PWM_NAME "pwm0"
#define BOARD_PWM_CHANNEL (6)
/* ADC section */
#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME
#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1
#define IRQn_PendSV IRQn_DEBUG0
/***************************************************************
bsp/hpmicro/hpm5300evk/rtconfig.h
+20 -1
View File
@@ -104,6 +104,8 @@
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define ARCH_RISCV
#define ARCH_RISCV32
/* RT-Thread Components */
@@ -300,6 +302,20 @@
/* NXP HAL & SDK Drivers */
/* end of NXP HAL & SDK Drivers */
/* NUVOTON Drivers */
/* end of NUVOTON Drivers */
/* GD32 Drivers */
/* end of GD32 Drivers */
/* HPMicro SDK */
#define PKG_USING_HPM_SDK
#define PKG_USING_HPM_SDK_LATEST_VERSION
/* end of HPMicro SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
@@ -379,18 +395,21 @@
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_HPM5300_SERIES
/* Hardware Drivers Config */
#define SOC_HPM5000
#define SOC_HPM5300
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_GPIO_IRQ_PRIORITY 1
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_BUFSIZE 128
#define BSP_UART0_TX_BUFSIZE 0
#define BSP_UART0_IRQ_PRIORITY 1
/* end of On-chip Peripheral Drivers */
/* end of Hardware Drivers Config */
bsp/hpmicro/hpm5300evk/rtconfig.py
+39 -6
View File
@@ -1,8 +1,41 @@
# Copyright 2021-2023 HPMicro
# Copyright 2021-2025 HPMicro
# SPDX-License-Identifier: BSD-3-Clause
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
need_update = True
for p in os.listdir("packages"):
if p.startswith("hpm_sdk-"):
need_update = False
break
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
# toolchains options
ARCH='risc-v'
@@ -80,27 +113,27 @@ if PLATFORM == 'gcc':
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
LFLAGS += ' -O0'
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
elif BUILD == 'ram_release':
CFLAGS += ' -O2'
LFLAGS += ' -O2'
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
elif BUILD == 'flash_debug':
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
LFLAGS += ' -O0'
CFLAGS += ' -DFLASH_XIP=1'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
elif BUILD == 'flash_release':
CFLAGS += ' -O2'
LFLAGS += ' -O2'
CFLAGS += ' -DFLASH_XIP=1'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
else:
CFLAGS += ' -O2'
LFLAGS += ' -O2'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
LFLAGS += ' -T ' + LINKER_FILE
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c
+129 -122
View File
@@ -4,125 +4,132 @@
*
*/
#include "hpm_common.h"
#include "hpm_soc.h"
#include "hpm_l1c_drv.h"
#include <rtthread.h>
void system_init(void);
extern int entry(void);
extern void __libc_init_array(void);
extern void __libc_fini_array(void);
void system_init(void)
{
disable_global_irq(CSR_MSTATUS_MIE_MASK);
disable_irq_from_intc();
enable_irq_from_intc();
enable_global_irq(CSR_MSTATUS_MIE_MASK);
#ifndef CONFIG_NOT_ENABLE_ICACHE
l1c_ic_enable();
#endif
#ifndef CONFIG_NOT_ENABLE_DCACHE
l1c_dc_enable();
#endif
}
__attribute__((weak)) void c_startup(void)
{
uint32_t i, size;
#ifdef FLASH_XIP
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
size = __vector_ram_end__ - __vector_ram_start__;
for (i = 0; i < size; i++) {
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
}
#endif
extern uint8_t __etext[];
extern uint8_t __bss_start__[], __bss_end__[];
extern uint8_t __tbss_start__[], __tbss_end__[];
extern uint8_t __tdata_start__[], __tdata_end__[];
extern uint8_t __data_start__[], __data_end__[];
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
/* tbss section */
size = __tbss_end__ - __tbss_start__;
for (i = 0; i < size; i++) {
*(__tbss_start__ + i) = 0;
}
/* bss section */
size = __bss_end__ - __bss_start__;
for (i = 0; i < size; i++) {
*(__bss_start__ + i) = 0;
}
/* noncacheable bss section */
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_bss_start__ + i) = 0;
}
/* tdata section LMA: etext */
size = __tdata_end__ - __tdata_start__;
for (i = 0; i < size; i++) {
*(__tdata_start__ + i) = *(__etext + i);
}
/* data section LMA: etext */
size = __data_end__ - __data_start__;
for (i = 0; i < size; i++) {
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
}
/* ramfunc section LMA: etext + data length */
size = __ramfunc_end__ - __ramfunc_start__;
for (i = 0; i < size; i++) {
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
}
/* noncacheable init section LMA: etext + data length + ramfunc length */
size = __noncacheable_init_end__ - __noncacheable_init_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
}
}
__attribute__((weak)) int main(void)
{
while(1);
}
void reset_handler(void)
{
/**
* Disable preemptive interrupt
*/
HPM_PLIC->FEATURE = 0;
/*
* Initialize LMA/VMA sections.
* Relocation for any sections that need to be copied from LMA to VMA.
*/
c_startup();
/* Call platform specific hardware initialization */
system_init();
/* Do global constructors */
__libc_init_array();
/* Entry function */
entry();
}
__attribute__((weak)) void _init()
{
}
#include "hpm_common.h"
#include "hpm_soc.h"
#include "hpm_l1c_drv.h"
#include <rtthread.h>
void system_init(void);
extern int entry(void);
extern void __libc_init_array(void);
extern void __libc_fini_array(void);
void system_init(void)
{
disable_global_irq(CSR_MSTATUS_MIE_MASK);
disable_irq_from_intc();
enable_irq_from_intc();
enable_global_irq(CSR_MSTATUS_MIE_MASK);
#ifndef CONFIG_NOT_ENABLE_ICACHE
l1c_ic_enable();
#endif
#ifndef CONFIG_NOT_ENABLE_DCACHE
l1c_dc_enable();
#endif
}
__attribute__((weak)) void c_startup(void)
{
#ifndef __SES_RISCV
uint32_t i, size;
#ifdef FLASH_XIP
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
size = __vector_ram_end__ - __vector_ram_start__;
for (i = 0; i < size; i++) {
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
}
#endif
extern uint8_t __etext[];
extern uint8_t __bss_start__[], __bss_end__[];
extern uint8_t __tbss_start__[], __tbss_end__[];
extern uint8_t __tdata_start__[], __tdata_end__[];
extern uint8_t __fast_load_addr__[];
extern uint8_t __noncacheable_init_load_addr__[];
extern uint8_t __data_load_addr__[];
extern uint8_t __tdata_load_addr__[];
extern uint8_t __data_start__[], __data_end__[];
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
/* tbss section */
size = __tbss_end__ - __tbss_start__;
for (i = 0; i < size; i++) {
*(__tbss_start__ + i) = 0;
}
/* bss section */
size = __bss_end__ - __bss_start__;
for (i = 0; i < size; i++) {
*(__bss_start__ + i) = 0;
}
/* noncacheable bss section */
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_bss_start__ + i) = 0;
}
/* tdata section LMA: etext */
size = __tdata_end__ - __tdata_start__;
for (i = 0; i < size; i++) {
*(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
}
/* data section LMA: etext */
size = __data_end__ - __data_start__;
for (i = 0; i < size; i++) {
*(__data_start__ + i) = *(__data_load_addr__ + i);
}
/* ramfunc section LMA: etext + data length */
size = __ramfunc_end__ - __ramfunc_start__;
for (i = 0; i < size; i++) {
*(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
}
/* noncacheable init section LMA: etext + data length + ramfunc length */
size = __noncacheable_init_end__ - __noncacheable_init_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
}
#endif
}
__attribute__((weak)) int main(void)
{
while(1);
}
void reset_handler(void)
{
/**
* Disable preemptive interrupt
*/
HPM_PLIC->FEATURE = 0;
/*
* Initialize LMA/VMA sections.
* Relocation for any sections that need to be copied from LMA to VMA.
*/
c_startup();
/* Call platform specific hardware initialization */
system_init();
#ifndef __SES_RISCV
/* Do global constructors */
__libc_init_array();
#endif
/* Entry function */
entry();
}
__attribute__((weak)) void _init(void)
{
}
bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S
+1 -1
View File
@@ -5,7 +5,7 @@
*
*/
#include "cpuport.h"
.section .text.entry, "ax"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S
-1
View File
@@ -62,7 +62,6 @@ _start:
nmi_handler:
1: j 1b
.global default_irq_handler
.weak default_irq_handler
.align 2
default_irq_handler:
bsp/hpmicro/hpm5301evklite/.config
+50 -6
View File
@@ -104,11 +104,9 @@
#
# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
# end of rt_strnlen options
# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
# end of klibc options
CONFIG_RT_NAME_MAX=8
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_AMP is not set
@@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
CONFIG_RT_USING_CPU_USAGE_TRACER=y
#
# kservice options
@@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV32=y
#
# RT-Thread Components
#
@@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
# CONFIG_FINSH_USING_WORD_OPERATION is not set
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -376,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
# CONFIG_PKG_USING_ESP_HOSTED is not set
#
# Wi-Fi
@@ -483,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -572,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_MCOREDUMP is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -617,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ZDEBUG is not set
# CONFIG_PKG_USING_RVBACKTRACE is not set
# CONFIG_PKG_USING_HPATCHLITE is not set
# CONFIG_PKG_USING_THREAD_METRIC is not set
# end of tools packages
#
@@ -710,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -791,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_NUCLEI_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_MM32 is not set
@@ -833,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
# end of HC32 DDL Drivers
#
@@ -846,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
# end of NXP HAL & SDK Drivers
#
# NUVOTON Drivers
#
# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
# end of NUVOTON Drivers
#
# GD32 Drivers
#
# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
# end of GD32 Drivers
#
# HPMicro SDK
#
CONFIG_PKG_USING_HPM_SDK=y
CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
# CONFIG_PKG_USING_HPM_SDK_V110 is not set
CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
CONFIG_PKG_HPM_SDK_VER="latest"
# end of HPMicro SDK
# end of HAL & SDK Drivers
#
@@ -1017,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_SEAN_WS2812B is not set
# CONFIG_PKG_USING_IC74HC165 is not set
# CONFIG_PKG_USING_IST8310 is not set
# CONFIG_PKG_USING_ST7789_SPI is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@@ -1355,21 +1394,26 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# end of Arduino libraries
# end of RT-Thread online packages
CONFIG_SOC_HPM5300_SERIES=y
#
# Hardware Drivers Config
#
CONFIG_SOC_HPM5000=y
CONFIG_SOC_HPM5300=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_GPIO_IRQ_PRIORITY=1
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_UART0_RX_BUFSIZE=128
CONFIG_BSP_UART0_TX_BUFSIZE=0
CONFIG_BSP_UART0_IRQ_PRIORITY=1
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_GPTMR is not set
# CONFIG_BSP_USING_I2C is not set
bsp/hpmicro/hpm5301evklite/SConstruct
-10
View File
@@ -55,17 +55,7 @@ GDB = rtconfig.GDB
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
# include components
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
# includes rtt drivers
bsp/hpmicro/hpm5301evklite/board/Kconfig
+249 -26
View File
@@ -1,8 +1,8 @@
menu "Hardware Drivers Config"
config SOC_HPM5000
config SOC_HPM5300
bool
select SOC_SERIES_HPM5300
select SOC_HPM5300_SERIES
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
@@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers"
bool "Enable GPIO"
select RT_USING_PIN if BSP_USING_GPIO
default n
if BSP_USING_GPIO
config BSP_GPIO_IRQ_PRIORITY
int "GPIO Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART
bool "Enable UART"
@@ -41,6 +47,37 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART0_IRQ_PRIORITY
int "UART0 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 1024
config BSP_UART1_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART1_IRQ_PRIORITY
int "UART1 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
@@ -64,29 +101,37 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART2_IRQ_PRIORITY
int "UART2 Interrupt Priority"
range 1 7
default 1
endif
menuconfig BSP_USING_UART6
bool "Enable UART6"
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART6
config BSP_UART6_RX_USING_DMA
bool "Enable UART6 RX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
if BSP_USING_UART3
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART6_TX_USING_DMA
bool "Enable UART6 TX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART6_RX_BUFSIZE
int "Set UART6 RX buffer size"
config BSP_UART3_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 1024
config BSP_UART6_TX_BUFSIZE
int "Set UART6 TX buffer size"
config BSP_UART3_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
config BSP_UART3_IRQ_PRIORITY
int "UART3 Interrupt Priority"
range 1 7
default 1
endif
endif
@@ -95,48 +140,225 @@ menu "On-chip Peripheral Drivers"
default n
select RT_USING_SPI if BSP_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0"
default n
if BSP_USING_SPI0
config BSP_SPI0_USING_DMA
bool "Enable SPI0 DMA"
default n
config BSP_SPI0_IRQ_PRIORITY
int "SPI0 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI0 CS TYPE"
default BSP_SPI0_USING_SOFT_CS
config BSP_SPI0_USING_SOFT_CS
bool "Enable SPI0 software cs"
config BSP_SPI0_USING_HARD_CS
bool "Enable SPI0 hardware cs"
endchoice
choice
prompt "Select SPI0 IO mode"
default BSP_SPI0_USING_SINGLE_IO
config BSP_SPI0_USING_SINGLE_IO
bool "Enable SPI0 single IO mode"
config BSP_SPI0_USING_DUAL_IO
bool "Enable SPI0 dual IO mode"
config BSP_SPI0_USING_QUAD_IO
bool "Enable SPI0 quad IO mode"
endchoice
endif
config BSP_USING_SPI1
bool "Enable SPI1"
default y
if BSP_USING_SPI1
config BSP_SPI1_USING_DMA
bool "Enable SPI1 DMA"
default n
config BSP_SPI1_IRQ_PRIORITY
int "SPI1 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI1 CS TYPE"
default BSP_SPI1_USING_SOFT_CS
config BSP_SPI1_USING_SOFT_CS
bool "Enable SPI1 software cs"
config BSP_SPI1_USING_HARD_CS
bool "Enable SPI1 hardware cs"
endchoice
choice
prompt "Select SPI1 IO mode"
default BSP_SPI1_USING_SINGLE_IO
config BSP_SPI1_USING_SINGLE_IO
bool "Enable SPI1 single IO mode"
config BSP_SPI1_USING_DUAL_IO
bool "Enable SPI1 dual IO mode"
config BSP_SPI1_USING_QUAD_IO
bool "Enable SPI1 quad IO mode"
endchoice
endif
config BSP_USING_SPI2
bool "Enable SPI2"
default n
if BSP_USING_SPI2
config BSP_SPI2_USING_DMA
bool "Enable SPI2 DMA"
default n
config BSP_SPI2_IRQ_PRIORITY
int "SPI2 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI2 CS TYPE"
default BSP_SPI2_USING_SOFT_CS
config BSP_SPI2_USING_SOFT_CS
bool "Enable SPI2 software cs"
config BSP_SPI2_USING_HARD_CS
bool "Enable SPI2 hardware cs"
endchoice
choice
prompt "Select SPI2 IO mode"
default BSP_SPI2_USING_SINGLE_IO
config BSP_SPI2_USING_SINGLE_IO
bool "Enable SPI2 single IO mode"
config BSP_SPI2_USING_DUAL_IO
bool "Enable SPI2 dual IO mode"
config BSP_SPI2_USING_QUAD_IO
bool "Enable SPI2 quad IO mode"
endchoice
endif
config BSP_USING_SPI3
bool "Enable SPI3"
default n
if BSP_USING_SPI3
config BSP_SPI3_USING_DMA
bool "Enable SPI3 DMA"
default n
config BSP_SPI3_IRQ_PRIORITY
int "SPI3 Interrupt Priority"
range 1 7
default 1
choice
prompt "Select SPI3 CS TYPE"
default BSP_SPI3_USING_SOFT_CS
config BSP_SPI3_USING_SOFT_CS
bool "Enable SPI3 software cs"
config BSP_SPI3_USING_HARD_CS
bool "Enable SPI3 hardware cs"
endchoice
choice
prompt "Select SPI3 IO mode"
default BSP_SPI3_USING_SINGLE_IO
config BSP_SPI3_USING_SINGLE_IO
bool "Enable SPI3 single IO mode"
config BSP_SPI3_USING_DUAL_IO
bool "Enable SPI3 dual IO mode"
config BSP_SPI3_USING_QUAD_IO
bool "Enable SPI3 quad IO mode"
endchoice
endif
endif
menuconfig BSP_USING_GPTMR
bool "Enable GPTMR"
default n
select RT_USING_HWTIMER if BSP_USING_GPTMR
if BSP_USING_GPTMR
config BSP_USING_GPTMR0
bool "Enable GPTMR0"
default n
if BSP_USING_GPTMR0
config BSP_GPTMR0_IRQ_PRIORITY
int "GPTMR0 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_GPTMR1
bool "Enable GPTMR1"
default n
if BSP_USING_GPTMR1
config BSP_GPTMR1_IRQ_PRIORITY
int "GPTMR1 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_GPTMR2
bool "Enable GPTMR2"
default n
if BSP_USING_GPTMR2
config BSP_GPTMR2_IRQ_PRIORITY
int "GPTMR2 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_GPTMR3
bool "Enable GPTMR3"
default n
if BSP_USING_GPTMR3
config BSP_GPTMR3_IRQ_PRIORITY
int "GPTMR3 Interrupt Priority"
range 1 7
default 1
endif
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
default n
select RT_USING_I2C if BSP_USING_I2C
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default y
if BSP_USING_I2C0
config BSP_I2C0_USING_DMA
bool "Enable I2C0 DMA"
default n
endif
if BSP_USING_I2C0
config BSP_I2C0_USING_DMA
bool "Enable I2C0 DMA"
default n
config BSP_I2C0_IRQ_PRIORITY
int "I2C0 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_I2C1
bool "Enable I2C1"
default n
if BSP_USING_I2C1
config BSP_I2C1_USING_DMA
bool "Enable I2C1 DMA"
default n
config BSP_I2C1_IRQ_PRIORITY
int "I2C1 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_I2C2
bool "Enable I2C2"
default n
if BSP_USING_I2C2
config BSP_I2C2_USING_DMA
bool "Enable I2C2 DMA"
default n
config BSP_I2C2_IRQ_PRIORITY
int "I2C2 Interrupt Priority"
range 1 7
default 1
endif
config BSP_USING_I2C3
bool "Enable I2C3"
default n
if BSP_USING_I2C3
config BSP_I2C3_USING_DMA
bool "Enable I2C3 DMA"
default n
endif
if BSP_USING_I2C3
config BSP_I2C3_USING_DMA
bool "Enable I2C3 DMA"
default n
config BSP_I2C3_IRQ_PRIORITY
int "I2C3 Interrupt Priority"
range 1 7
default 1
endif
endif
menuconfig BSP_USING_XPI_FLASH
@@ -150,6 +372,7 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_USB
config BSP_USING_USB_DEVICE
bool "Enable USB Device"
select RT_USING_CACHE
default n
config BSP_USING_USB_HOST
bool "Enable USB HOST"
bsp/hpmicro/hpm5301evklite/board/board.c
+107 -90
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@@ -13,8 +13,7 @@
#include "hpm_pllctlv2_drv.h"
#include "hpm_i2c_drv.h"
#include "hpm_pcfg_drv.h"
static board_timer_cb timer_cb;
#include <rtconfig.h>
/**
* @brief FLASH configuration option definitions:
@@ -49,7 +48,7 @@ static board_timer_cb timer_cb;
* 2 - Internal loopback
* 3 - External DQS
* [3:0] Frequency option
* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz
*
* option[2] (Effective only if the bit[3:0] in option[0] > 1)
* [31:20] Reserved
@@ -70,11 +69,11 @@ static board_timer_cb timer_cb;
* 0 - 4MB / 1 - 8MB / 2 - 16MB
*/
#if defined(FLASH_XIP) && FLASH_XIP
__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0};
#endif
#if defined(FLASH_UF2) && FLASH_UF2
ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
#endif
void board_init_console(void)
@@ -89,8 +88,6 @@ void board_init_console(void)
*/
init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
/* Configure the UART clock to 24MHz */
clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
cfg.type = BOARD_CONSOLE_TYPE;
@@ -143,7 +140,6 @@ void board_print_clock_freq(void)
void board_init(void)
{
init_xtal_pins();
init_py_pins_as_pgpio();
board_init_usb_dp_dm_pins();
@@ -176,7 +172,7 @@ void board_init_usb_dp_dm_pins(void)
} else {
uint8_t tmp;
tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); /* NOLINT */
clock_add_to_group(clock_usb0, 0);
usb_phy_disable_dp_dm_pulldown(HPM_USB0);
clock_remove_from_group(clock_usb0, 0);
@@ -199,31 +195,20 @@ void board_init_clock(void)
sysctl_clock_set_preset(HPM_SYSCTL, 2);
}
/* select XTAL as pll ref clock */
pllctlv2_select_reference_clock(HPM_PLLCTLV2, pllctlv2_pll0, 0);
pllctlv2_select_reference_clock(HPM_PLLCTLV2, pllctlv2_pll1, 0);
/* group0[0] */
clock_add_to_group(clock_cpu0, 0);
clock_add_to_group(clock_ahb, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_mchtmr0, 0);
clock_add_to_group(clock_rom, 0);
clock_add_to_group(clock_gptmr0, 0);
clock_add_to_group(clock_gptmr1, 0);
clock_add_to_group(clock_i2c2, 0);
clock_add_to_group(clock_spi1, 0);
clock_add_to_group(clock_uart0, 0);
clock_add_to_group(clock_uart3, 0);
clock_add_to_group(clock_watchdog0, 0);
clock_add_to_group(clock_watchdog1, 0);
clock_add_to_group(clock_mbx0, 0);
clock_add_to_group(clock_tsns, 0);
clock_add_to_group(clock_crc0, 0);
clock_add_to_group(clock_adc0, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_kman, 0);
clock_add_to_group(clock_mot0, 0); /* for trgm and synt peripheral */
clock_add_to_group(clock_gpio, 0);
clock_add_to_group(clock_hdma, 0);
clock_add_to_group(clock_xpi0, 0);
clock_add_to_group(clock_usb0, 0);
/* Connect Group0 to CPU0 */
clock_connect_group_to_cpu(0, 0);
@@ -234,11 +219,11 @@ void board_init_clock(void)
/* Configure CPU to 360MHz, AXI/AHB to 120MHz */
sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
/* Configure PLL0 Post Divider */
pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 720MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 450MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 300MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0); /* PLL0CLK0: 720MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p2); /* PLL0CLK1: 600MHz */
pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk2, pllctlv2_div_1p8); /* PLL0CLK2: 400MHz */
/* Configure PLL0 Frequency to 720MHz */
pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000);
pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, 720000000);
clock_update_core_clock();
@@ -246,32 +231,6 @@ void board_init_clock(void)
clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
}
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
{
uint32_t freq = 0;
clock_name_t gptmr_clock =0;
uint32_t HPM_GPTMR = (uint32_t)ptr;
bool gptmr_valid = true;
switch(HPM_GPTMR){
case HPM_GPTMR0_BASE:
gptmr_clock = clock_gptmr0;
break;
case HPM_GPTMR1_BASE:
gptmr_clock = clock_gptmr1;
break;
default:
gptmr_valid = false;
}
if(gptmr_valid)
{
clock_add_to_group(gptmr_clock, 0);
clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4);
freq = clock_get_frequency(gptmr_clock);
}
return freq;
}
void board_delay_us(uint32_t us)
{
clock_cpu_delay_us(us);
@@ -282,6 +241,17 @@ void board_delay_ms(uint32_t ms)
clock_cpu_delay_ms(ms);
}
#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
static board_timer_cb timer_cb;
SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
void board_timer_isr(void)
{
if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
timer_cb();
}
}
void board_timer_create(uint32_t ms, board_timer_cb cb)
{
uint32_t gptmr_freq;
@@ -300,6 +270,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb)
gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
}
#endif
void board_init_gpio_pins(void)
{
@@ -313,15 +284,19 @@ void board_init_led_pins(void)
gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
}
void board_init_usb_pins(void)
void board_init_usb(USB_Type *ptr)
{
init_usb_pins();
usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
/* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
board_delay_ms(100);
if (ptr == HPM_USB0) {
init_usb_pins(ptr);
clock_add_to_group(clock_usb0, 0);
/* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
usb_phy_using_internal_vbus(BOARD_USB);
usb_hcd_set_power_ctrl_polarity(ptr, true);
/* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
board_delay_ms(100);
/* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
usb_phy_using_internal_vbus(ptr);
}
}
void board_led_write(uint8_t state)
@@ -373,18 +348,12 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
}
void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
{
(void) usb_index;
(void) level;
}
uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)
{
uint32_t freq = 0;
if (ptr == HPM_ADC0) {
if (clk_src_ahb) {
if (ptr == (void *)HPM_ADC0) {
if (clk_src_bus) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
} else {
@@ -404,6 +373,17 @@ void board_init_adc16_pins(void)
init_adc_pins();
}
void board_init_acmp_clock(ACMP_Type *ptr)
{
(void)ptr;
clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
}
void board_init_acmp_pins(void)
{
init_acmp_pins();
}
void board_disable_output_rgb_led(uint8_t color)
{
(void) color;
@@ -427,15 +407,9 @@ uint32_t board_init_uart_clock(UART_Type *ptr)
{
uint32_t freq = 0U;
if (ptr == HPM_UART0) {
clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
clock_add_to_group(clock_uart0, 0);
freq = clock_get_frequency(clock_uart0);
} else if (ptr == HPM_UART2) {
clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 6);
clock_add_to_group(clock_uart2, 0);
freq = clock_get_frequency(clock_uart2);
} else if (ptr == HPM_UART3) {
clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 6); /* 50MHz */
clock_add_to_group(clock_uart3, 0);
freq = clock_get_frequency(clock_uart3);
}
@@ -456,35 +430,78 @@ void board_i2c_bus_clear(I2C_Type *ptr)
printf("I2C bus is ready\n");
return;
}
i2s_gen_reset_signal(ptr, 9);
i2c_gen_reset_signal(ptr, 9);
board_delay_ms(100);
printf("I2C bus is cleared\n");
}
uint32_t board_init_i2c_clock(I2C_Type *ptr)
{
uint32_t freq = 0;
if (ptr == HPM_I2C0) {
clock_add_to_group(clock_i2c0, 0);
freq = clock_get_frequency(clock_i2c0);
} else if (ptr == HPM_I2C1) {
clock_add_to_group(clock_i2c1, 0);
freq = clock_get_frequency(clock_i2c1);
} else if (ptr == HPM_I2C2) {
clock_add_to_group(clock_i2c2, 0);
freq = clock_get_frequency(clock_i2c2);
} else if (ptr == HPM_I2C3) {
clock_add_to_group(clock_i2c3, 0);
freq = clock_get_frequency(clock_i2c3);
} else {
;
}
return freq;
}
void board_init_i2c(I2C_Type *ptr)
{
i2c_config_t config;
hpm_stat_t stat;
uint32_t freq;
if (ptr == NULL) {
return;
}
freq = board_init_i2c_clock(ptr);
init_i2c_pins(ptr);
board_i2c_bus_clear(ptr);
clock_add_to_group(clock_i2c2, 0);
/* Configure the I2C clock to 24MHz */
clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
config.i2c_mode = i2c_mode_normal;
config.is_10bit_addressing = false;
freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
stat = i2c_init_master(ptr, freq, &config);
if (stat != status_success) {
printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
while (1) {
}
}
}
void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
init_gptmr_channel_pin(ptr, channel, as_comp);
}
void board_init_clk_ref_pin(void)
{
init_clk_ref_pin();
}
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
{
uint32_t freq = 0U;
if (ptr == HPM_GPTMR0) {
clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr0);
} else if (ptr == HPM_GPTMR1) {
clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_gptmr1);
} else if (ptr == HPM_PTMR) {
clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
freq = clock_get_frequency(clock_ptmr);
} else {
/* Not supported */
}
return freq;
}
bsp/hpmicro/hpm5301evklite/board/board.h
+145 -76
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023-2025 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -23,6 +23,7 @@
/* ACMP desction */
#define BOARD_ACMP HPM_ACMP
#define BOARD_ACMP_CLK clock_acmp0
#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1
#define BOARD_ACMP_IRQ IRQn_ACMP_1
#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */
@@ -39,15 +40,26 @@
#define BOARD_RUNNING_CORE HPM_CORE0
#endif
/* uart section */
#ifndef BOARD_APP_UART_BASE
#define BOARD_APP_UART_BASE HPM_UART3
#define BOARD_APP_UART_IRQ IRQn_UART3
#define BOARD_APP_UART_BASE HPM_UART3
#define BOARD_APP_UART_IRQ IRQn_UART3
#define BOARD_APP_UART_BAUDRATE (115200UL)
#define BOARD_APP_UART_CLK_NAME clock_uart3
#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART3_RX
#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART3_TX
#endif
#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PA26
/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */
#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG0
#define BOARD_UART_TRGM HPM_TRGM0
#define BOARD_UART_TRGM_GPTMR HPM_GPTMR1
#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr1
#define BOARD_UART_TRGM_GPTMR_CH 2
#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2
/* uart lin sample section */
#define BOARD_UART_LIN BOARD_APP_UART_BASE
#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ
@@ -55,7 +67,6 @@
#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOB
#define BOARD_UART_LIN_TX_PIN (15U) /* PB15 should align with used pin in pinmux configuration */
#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
#ifndef BOARD_CONSOLE_TYPE
#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
@@ -63,9 +74,9 @@
#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
#ifndef BOARD_CONSOLE_UART_BASE
#define BOARD_CONSOLE_UART_BASE HPM_UART0
#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
#define BOARD_CONSOLE_UART_IRQ IRQn_UART0
#define BOARD_CONSOLE_UART_BASE HPM_UART0
#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
#define BOARD_CONSOLE_UART_IRQ IRQn_UART0
#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
#endif
@@ -81,6 +92,8 @@
/* rtthread-nano finsh section */
#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE
#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME
#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ
/* modbus sample section */
#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE
@@ -93,26 +106,26 @@
#define BOARD_FLASH_SIZE (SIZE_1MB)
/* i2c section */
#define BOARD_APP_I2C_BASE HPM_I2C2
#define BOARD_APP_I2C_IRQ IRQn_I2C2
#define BOARD_APP_I2C_CLK_NAME clock_i2c2
#define BOARD_APP_I2C_BASE HPM_I2C3
#define BOARD_APP_I2C_IRQ IRQn_I2C3
#define BOARD_APP_I2C_CLK_NAME clock_i2c3
#define BOARD_APP_I2C_DMA HPM_HDMA
#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX
#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C2
#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C3
/* gptmr section */
#define BOARD_GPTMR HPM_GPTMR0
#define BOARD_GPTMR_IRQ IRQn_GPTMR0
#define BOARD_GPTMR_CHANNEL 0
#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0
#define BOARD_GPTMR_CHANNEL 1
#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_1
#define BOARD_GPTMR_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_PWM HPM_GPTMR0
#define BOARD_GPTMR_PWM_CHANNEL 0
#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0
#define BOARD_GPTMR_PWM_CHANNEL 1
#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_1
#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0
#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0
#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1
#define BOARD_GPTMR_PWM_SYNC_CHANNEL 2
#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0
/* User LED */
@@ -121,91 +134,94 @@
#define BOARD_LED_GPIO_PIN 10
#define BOARD_LED_OFF_LEVEL 1
#define BOARD_LED_ON_LEVEL 0
#define BOARD_LED_ON_LEVEL 0
/* 12V Power Enable*/
#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0
#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0
#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_12V_EN_GPIO_PIN 24
#define BOARD_12V_EN_GPIO_PIN 24
/* gpiom section */
#define BOARD_APP_GPIOM_BASE HPM_GPIOM
#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO
#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
/* GPIO read value macro,spec for sample cherryusb on board hpm5301evklite*/
#define BOARD_BUTTON_PRESSED_VALUE 1
/* tinyuf2 button on hpm5301evklite*/
#define BOARD_BUTTON_TINYUF2_PIN 9
/* User button */
#define BOARD_APP_GPIO_CTRL HPM_GPIO0
#define BOARD_APP_GPIO_CTRL HPM_GPIO0
#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_APP_GPIO_PIN 3
#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A
#define BOARD_APP_GPIO_PIN 3
#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A
#define BOARD_BUTTON_PRESSED_VALUE 1
/* spi section */
#define BOARD_APP_SPI_BASE HPM_SPI1
#define BOARD_APP_SPI_BASE HPM_SPI1
#define BOARD_APP_SPI_CLK_NAME clock_spi1
#define BOARD_APP_SPI_IRQ IRQn_SPI1
#define BOARD_APP_SPI_SCLK_FREQ (20000000UL)
#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U)
#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX
#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX
#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0
#define BOARD_SPI_CS_PIN IOC_PAD_PA26
#define BOARD_SPI_CS_ACTIVE_LEVEL (0U)
#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX
#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX
#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0
#define BOARD_SPI_CS_PIN IOC_PAD_PA26
#define BOARD_SPI_CS_ACTIVE_LEVEL (0U)
/* ADC section */
#define BOARD_APP_ADC16_NAME "ADC0"
#define BOARD_APP_ADC16_BASE HPM_ADC0
#define BOARD_APP_ADC16_IRQn IRQn_ADC0
#define BOARD_APP_ADC16_CH_1 (11U)
#define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
#define BOARD_APP_ADC16_NAME "ADC0"
#define BOARD_APP_ADC16_BASE HPM_ADC0
#define BOARD_APP_ADC16_IRQn IRQn_ADC0
#define BOARD_APP_ADC16_CH_1 (2U)
#define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0)
#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
/* Flash section */
#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0)
#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U)
#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U)
#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U)
#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0)
#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U)
#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U)
#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U)
/* CALLBACK TIMER section */
#define BOARD_CALLBACK_TIMER (HPM_GPTMR1)
#define BOARD_CALLBACK_TIMER_CH 0
#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR1
#define BOARD_CALLBACK_TIMER (HPM_GPTMR1)
#define BOARD_CALLBACK_TIMER_CH 0
#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR1
#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr1)
/*Timer define*/
#define BOARD_BLDC_TMR_1MS HPM_GPTMR2
#define BOARD_BLDC_TMR_CH 0
#define BOARD_BLDC_TMR_CMP 0
#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2
#define BOARD_BLDC_TMR_RELOAD (100000U)
#define BOARD_BLDC_TMR_1MS HPM_GPTMR2
#define BOARD_BLDC_TMR_CH 0
#define BOARD_BLDC_TMR_CMP 0
#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2
#define BOARD_BLDC_TMR_CLOCK clock_gptmr2
#define BOARD_BLDC_TMR_RELOAD (100000U)
/*adc*/
#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16)
#define BOARD_BLDC_ADC_U_BASE HPM_ADC0
#define BOARD_BLDC_ADC_V_BASE HPM_ADC1
#define BOARD_BLDC_ADC_W_BASE HPM_ADC1
#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete
#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16)
#define BOARD_BLDC_ADC_U_BASE HPM_ADC0
#define BOARD_BLDC_ADC_V_BASE HPM_ADC1
#define BOARD_BLDC_ADC_W_BASE HPM_ADC1
#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete
#define BOARD_BLDC_ADC_CH_U (5U)
#define BOARD_BLDC_ADC_CH_V (6U)
#define BOARD_BLDC_ADC_CH_W (4U)
#define BOARD_BLDC_ADC_IRQn IRQn_ADC0
#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)
#define BOARD_BLDC_ADC_CH_U (5U)
#define BOARD_BLDC_ADC_CH_V (6U)
#define BOARD_BLDC_ADC_CH_W (4U)
#define BOARD_BLDC_ADC_IRQn IRQn_ADC0
#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)
#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A
#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U)
#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U)
#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A
/* USB */
#define BOARD_USB HPM_USB0
#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U)
#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U)
#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A
#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
#define BOARD_BLDC_DMA_MUX_SRC HPM_DMA_SRC_MOT_0
#define BOARD_BLDC_DMA_CHN (0U)
#define BOARD_BLDC_DMA_TRG_DST TRGM_TRGOCFG_TRGM_DMA0
#define BOARD_BLDC_DMA_TRG_SRC HPM_TRGM0_DMA_SRC_TRGM0
#define BOARD_BLDC_DMA_TRG_INDEX TRGM_DMACFG_0
#define BOARD_BLDC_DMA_TRG_CMP_INDEX (9U)
#define BOARD_BLDC_DMA_TRG_IN HPM_TRGM0_INPUT_SRC_PWM0_CH9REF
#ifndef BOARD_SHOW_CLOCK
#define BOARD_SHOW_CLOCK 1
@@ -220,29 +236,77 @@
#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR0
#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr0
#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0
#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0
#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0
#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR
#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1
#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR
#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr
/* Threadx Definitions */
#define BOARD_THREADX_TIMER HPM_GPTMR0
#define BOARD_THREADX_TIMER_CHANNEL 1
#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR0
#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr0
#define BOARD_THREADX_TIMER HPM_GPTMR0
#define BOARD_THREADX_TIMER_CHANNEL 1
#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR0
#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr0
#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR
#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1
#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR
#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
/* uC/OS-III Definitions */
#define BOARD_UCOS_TIMER HPM_GPTMR0
#define BOARD_UCOS_TIMER_CHANNEL 1
#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR0
#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr0
/* i2s over spi Section*/
#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0
#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA
#define BOARD_I2S_SPI_CS_GPIO_PIN 31
#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA31
#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR1
#define BOARD_GPTMR_I2S_MCLK_CHANNEL 1
#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1
#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR0
#define BOARD_GPTMR_I2S_LRCK_CHANNEL 2
#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0
#define BOARD_GPTMR_I2S_BLCK_CHANNEL 3
#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0
#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0
#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0
#define BOARD_GPTMR_I2S_FINSH_CHANNEL 0
#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0
#define BOARD_APP_CLK_REF_PIN_NAME "J3[32] (PA09)"
#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
typedef void (*board_timer_cb)(void);
void board_init_console(void);
void board_init_gpio_pins(void);
void board_init_led_pins(void);
void board_init_usb_pins(void);
void board_init_usb(USB_Type *ptr);
void board_led_write(uint8_t state);
void board_led_toggle(void);
void board_init_console(void);
void board_init_uart(UART_Type *ptr);
uint32_t board_init_spi_clock(SPI_Type *ptr);
void board_init_spi_pins(SPI_Type *ptr);
void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb);
uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus);
void board_init_adc16_pins(void);
void board_init_acmp_pins(void);
void board_init_acmp_clock(ACMP_Type *ptr);
void board_disable_output_rgb_led(uint8_t color);
void board_enable_output_rgb_led(uint8_t color);
void board_write_spi_cs(uint32_t pin, uint8_t state);
@@ -251,7 +315,6 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
void board_init(void);
void board_init_usb_dp_dm_pins(void);
void board_init_clock(void);
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
void board_delay_us(uint32_t us);
void board_delay_ms(uint32_t ms);
void board_timer_create(uint32_t ms, board_timer_cb cb);
@@ -263,7 +326,13 @@ void board_init_pmp(void);
uint32_t board_init_uart_clock(UART_Type *ptr);
uint32_t board_init_i2c_clock(I2C_Type *ptr);
void board_init_i2c(I2C_Type *ptr);
void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
void board_init_clk_ref_pin(void);
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld → bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld
+68 -34
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +14,7 @@ MEMORY
{
XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K
DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K
DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768
AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K
}
@@ -41,22 +41,25 @@ SECTIONS
.start __app_load_addr__ : {
. = ALIGN(8);
KEEP(*(.start))
. = ALIGN(16);
} > XPI0
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
.vectors : AT(__vector_load_addr__) {
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_start__ = .;
KEEP(*(.vector_table))
KEEP(*(.isr_vector))
. = ALIGN(8);
. = ALIGN(16);
__vector_ram_end__ = .;
} > ILM
.fast : AT(etext + __data_end__ - __tdata_start__) {
. = ALIGN(8);
.fast : AT(__fast_load_addr__) {
. = ALIGN(16);
__ramfunc_start__ = .;
*(.fast)
*(.fast.*)
. = ALIGN(16);
/* RT-Thread Core Start */
KEEP(*context_gcc.o(.text* .rodata*))
@@ -77,12 +80,12 @@ SECTIONS
KEEP(*mempool.o (.text .text* .rodata .rodata*))
/* RT-Thread Core End */
. = ALIGN(8);
. = ALIGN(16);
__ramfunc_end__ = .;
} > ILM
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
. = ALIGN(8);
.text (__vector_load_addr__ + SIZEOF(.vectors)) : {
. = ALIGN(16);
*(.text)
*(.text*)
*(.rodata)
@@ -107,12 +110,6 @@ SECTIONS
* RT-Thread related sections - Start
*
*********************************************/
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@@ -146,6 +143,20 @@ SECTIONS
} > XPI0
.eh_frame :
{
__eh_frame_start = .;
KEEP(*(.eh_frame))
__eh_frame_end = .;
} > XPI0
.eh_frame_hdr :
{
KEEP(*(.eh_frame_hdr))
} > XPI0
__eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
__eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
.rel : {
KEEP(*(.rel*))
} > XPI0
@@ -158,19 +169,14 @@ SECTIONS
KEEP(*(.fast_ram))
} > DLM
.bss(NOLOAD) : {
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
/* Note: the .tbss and .tdata section should be adjacent */
@@ -178,22 +184,26 @@ SECTIONS
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
.tdata : AT(etext) {
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
@@ -221,10 +231,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -245,6 +255,26 @@ SECTIONS
PROVIDE (_edata = .);
PROVIDE (edata = .);
} > DLM
__fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
__fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
.heap(NOLOAD) : {
@@ -265,7 +295,8 @@ SECTIONS
PROVIDE( __rt_rvstack = . );
} > DLM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
@@ -276,8 +307,11 @@ SECTIONS
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > DLM
bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld → bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld
+83 -65
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2023 HPMicro
* Copyright 2021-2025 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000;
MEMORY
{
ILM (wx) : ORIGIN = 0, LENGTH = 128K
DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
DLM (w) : ORIGIN = 0x80300, LENGTH = 96K - 768
NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE
AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k
}
SECTIONS
@@ -30,10 +30,6 @@ SECTIONS
KEEP(*(.vector_table))
. = ALIGN(8);
} > ILM
.fast_ram (NOLOAD) : {
KEEP(*(.fast_ram))
} > ILM
.text : {
. = ALIGN(8);
@@ -56,7 +52,7 @@ SECTIONS
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(8);
/*********************************************
*
* RT-Thread related sections - Start
@@ -92,28 +88,74 @@ SECTIONS
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
__usbh_class_info_end__ = .;
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
} > ILM
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.tdata : AT(etext) {
.rel : {
KEEP(*(.rel*))
} > DLM
.fast_ram (NOLOAD) : {
KEEP(*(.fast_ram))
} > ILM
__fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
.fast_ram.init : AT(__fast_ram_init_load_addr__) {
. = ALIGN(8);
__fast_ram_init_start__ = .;
KEEP(*(.fast_ram.init))
KEEP(*(.fast_ram.init.*))
__fast_ram_init_end__ = .;
. = ALIGN(8);
} > ILM
.bss(NOLOAD) : {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
/* Note: .tbss and .tdata should be adjacent */
.tbss(NOLOAD) : {
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.gnu.linkonce.tb.*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
__tdata_load_addr__ = etext;
.tdata : AT(__tdata_load_addr__) {
. = ALIGN(8);
__tdata_start__ = .;
__thread_pointer = .;
*(.tdata)
*(.tdata*)
*(.gnu.linkonce.td.*)
. = ALIGN(8);
__tdata_end__ = .;
} > DLM
.data : AT(etext + __tdata_end__ - __tdata_start__) {
__data_load_addr__ = etext + SIZEOF(.tdata);
.data : AT(__data_load_addr__) {
. = ALIGN(8);
__data_start__ = .;
__global_pointer$ = . + 0x800;
*(.data)
*(.data*)
*(.sdata)
@@ -138,10 +180,10 @@ SECTIONS
PROVIDE(__init_array_end = .);
. = ALIGN(8);
PROVIDE(__finit_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
KEEP(*(.finit_array))
PROVIDE(__finit_array_end = .);
PROVIDE(__fini_array_start = .);
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE(__fini_array_end = .);
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
@@ -164,43 +206,39 @@ SECTIONS
PROVIDE (edata = .);
} > DLM
.fast : AT(etext + __data_end__ - __tdata_start__) {
__fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
.fast : AT(__fast_load_addr__) {
. = ALIGN(8);
PROVIDE(__ramfunc_start__ = .);
*(.fast)
. = ALIGN(8);
PROVIDE(__ramfunc_end__ = .);
} > DLM
.rel : {
KEEP(*(.rel*))
} > DLM
.bss(NOLOAD) : {
__noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
.noncacheable.init : AT(__noncacheable_init_load_addr__) {
. = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss*)
*(.scommon)
*(.scommon*)
*(.dynsbss*)
*(COMMON)
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
__noncacheable_init_end__ = .;
. = ALIGN(8);
_end = .;
__bss_end__ = .;
} > DLM
} > NONCACHEABLE_RAM
/* Note: .tbss and .tdata should be adjacent */
.tbss(NOLOAD) : {
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
__tbss_start__ = .;
*(.tbss*)
*(.tcommon*)
_end = .;
__tbss_end__ = .;
} > DLM
KEEP(*(.noncacheable))
KEEP(*(.noncacheable.non_init))
KEEP(*(.noncacheable.non_init.*))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
KEEP(*(.noncacheable.bss.*))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
.stack(NOLOAD) : {
. = ALIGN(8);
__stack_base__ = .;
@@ -221,24 +259,4 @@ SECTIONS
.ahb_sram (NOLOAD) : {
KEEP(*(.ahb_sram))
} > AHB_SRAM
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
. = ALIGN(8);
__noncacheable_init_start__ = .;
KEEP(*(.noncacheable.init))
__noncacheable_init_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
.noncacheable.bss (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.noncacheable))
__noncacheable_bss_start__ = .;
KEEP(*(.noncacheable.bss))
__noncacheable_bss_end__ = .;
. = ALIGN(8);
} > NONCACHEABLE_RAM
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
}
bsp/hpmicro/hpm5301evklite/board/pinmux.c
+81 -30
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023,2025 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -15,15 +15,6 @@
#include "board.h"
#include "pinmux.h"
void init_xtal_pins(void)
{
/* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */
/*
* HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
* HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
*/
}
void init_py_pins_as_pgpio(void)
{
/* Set PY00-PY05 default function to PGPIO */
@@ -40,10 +31,6 @@ void init_uart_pins(UART_Type *ptr)
if (ptr == HPM_UART0) {
HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
} else if (ptr == HPM_UART2) {
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD;
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD;
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE;
} else if (ptr == HPM_UART3) {
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_UART3_TXD;
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_UART3_RXD;
@@ -73,8 +60,11 @@ void init_i2c_pins(I2C_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
} else {
;
} else if (ptr == HPM_I2C3) {
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_I2C3_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
}
}
@@ -96,6 +86,12 @@ void init_spi_pins(SPI_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
/* set max frequency slew rate(200M) */
HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
}
}
@@ -106,13 +102,26 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
/* set max frequency slew rate(200M) */
HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
}
}
void init_gptmr_pins(GPTMR_Type *ptr)
{
(void) ptr;
if (ptr == HPM_GPTMR0) {
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPTMR0_COMP_2;
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1;
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
} else if (ptr == HPM_GPTMR1) {
HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_GPTMR1_COMP_1;
}
}
void init_butn_pins(void)
@@ -152,22 +161,24 @@ void init_adc_bldc_pins(void)
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */
}
void init_usb_pins(void)
void init_usb_pins(USB_Type *ptr)
{
HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
if (ptr == HPM_USB0) {
HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
/* USB0_ID */
HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
/* USB0_OC */
HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
/* USB0_PWR */
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
/* USB0_ID */
HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
/* USB0_OC */
HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
/* USB0_PWR */
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
/* PY port IO needs to configure PIOC as well */
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
/* PY port IO needs to configure PIOC as well */
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
}
}
void init_led_pins_as_gpio(void)
@@ -175,3 +186,43 @@ void init_led_pins_as_gpio(void)
HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10;
}
/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
void init_uart_break_signal_pin(void)
{
HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26;
}
void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
if (ptr == HPM_GPTMR0) {
if (as_comp) {
switch (channel) {
case 1:
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
break;
case 2:
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPTMR0_COMP_2;
break;
case 3:
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
break;
default:
break;
}
} else {
if (channel == 1) {
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1;
}
}
} else if (ptr == HPM_GPTMR1) {
if ((as_comp == true) && (channel == 3)) {
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPTMR1_COMP_3;
}
}
}
void init_clk_ref_pin(void)
{
HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SOC_REF0;
}
bsp/hpmicro/hpm5301evklite/board/pinmux.h
+7 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023,2025 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -11,9 +11,9 @@
#ifdef __cplusplus
extern "C" {
#endif
void init_xtal_pins(void);
void init_py_pins_as_pgpio(void);
void init_uart_pins(UART_Type *ptr);
void init_uart_pin_as_gpio(UART_Type *ptr);
void init_i2c_pins(I2C_Type *ptr);
void init_gpio_pins(void);
void init_spi_pins(SPI_Type *ptr);
@@ -23,8 +23,12 @@ void init_butn_pins(void);
void init_acmp_pins(void);
void init_adc_pins(void);
void init_adc_bldc_pins(void);
void init_usb_pins(void);
void init_usb_pins(USB_Type *ptr);
void init_led_pins_as_gpio(void);
void init_uart_break_signal_pin(void);
void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
void init_clk_ref_pin(void);
#ifdef __cplusplus
}
#endif
bsp/hpmicro/hpm5301evklite/board/rtt_board.c
+40 -3
View File
@@ -52,7 +52,7 @@ void rtt_board_init(void)
os_tick_config();
/* Configure the USB pins*/
board_init_usb_pins();
board_init_usb(HPM_USB0);
/* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
rt_hw_uart_init();
@@ -63,6 +63,7 @@ void rtt_board_init(void)
void app_init_led_pins(void)
{
board_init_led_pins();
gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
}
@@ -96,7 +97,7 @@ void rt_hw_console_output(const char *str)
void app_init_usb_pins(void)
{
board_init_usb_pins();
board_init_usb(HPM_USB0);
}
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
@@ -108,7 +109,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
void rt_hw_cpu_reset(void)
{
HPM_PPOR->RESET_ENABLE = (1UL << 31);
HPM_PPOR->RESET_ENABLE |= (1UL << 31);
HPM_PPOR->SOFTWARE_RESET = 1000U;
while(1) {
@@ -117,3 +118,39 @@ void rt_hw_cpu_reset(void)
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
#ifdef RT_USING_CACHE
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_FLUSH) {
l1c_dc_flush((uint32_t)addr, size);
} else {
l1c_dc_invalidate((uint32_t)addr, size);
}
}
#endif
uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
{
uint32_t freq = 0;
if (ptr == HPM_ADC0) {
if (clk_src_ahb) {
/* Configure the ADC clock from AHB (@200MHz by default)*/
clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
} else {
/* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
}
clock_add_to_group(clock_adc0, 0);
freq = clock_get_frequency(clock_adc0);
}
return freq;
}
#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
extern void hpm_isr_usb0(void);
RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
#endif
bsp/hpmicro/hpm5301evklite/board/rtt_board.h
+15 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 hpmicro
* Copyright (c) 2021 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -10,8 +10,10 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <drv_gpio.h>
#include "board.h"
/* gpio section */
#define APP_LED0 (0U)
#define APP_LED0_PIN_NUM GET_PIN(A, 10)
#define APP_LED_ON (1)
#define APP_LED_OFF (0)
@@ -21,13 +23,23 @@
/* mchtimer section */
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
/* gptmr as os_tick */
#define BOARD_OS_TIMER HPM_GPTMR0
#define BOARD_OS_TIMER_CH 1
#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0
#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
/* CAN section */
#define BOARD_CAN_NAME "can0"
#define BOARD_CAN_HWFILTER_INDEX (0U)
/* UART section */
#define BOARD_UART_NAME "uart2"
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE
#define BOARD_UART_NAME "uart3"
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART3_RX_BUFSIZE
/* ADC section */
#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME
#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1
#define IRQn_PendSV IRQn_DEBUG0
bsp/hpmicro/hpm5301evklite/rtconfig.h
+22 -2
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 8
#define RT_NAME_MAX 16
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
@@ -76,6 +76,7 @@
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 1024
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
@@ -104,6 +105,8 @@
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define ARCH_RISCV
#define ARCH_RISCV32
/* RT-Thread Components */
@@ -300,6 +303,20 @@
/* NXP HAL & SDK Drivers */
/* end of NXP HAL & SDK Drivers */
/* NUVOTON Drivers */
/* end of NUVOTON Drivers */
/* GD32 Drivers */
/* end of GD32 Drivers */
/* HPMicro SDK */
#define PKG_USING_HPM_SDK
#define PKG_USING_HPM_SDK_LATEST_VERSION
/* end of HPMicro SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
@@ -379,18 +396,21 @@
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_HPM5300_SERIES
/* Hardware Drivers Config */
#define SOC_HPM5000
#define SOC_HPM5300
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_GPIO_IRQ_PRIORITY 1
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_BUFSIZE 128
#define BSP_UART0_TX_BUFSIZE 0
#define BSP_UART0_IRQ_PRIORITY 1
/* end of On-chip Peripheral Drivers */
/* end of Hardware Drivers Config */
bsp/hpmicro/hpm5301evklite/rtconfig.py
+39 -6
View File
@@ -1,8 +1,41 @@
# Copyright 2021-2023 HPMicro
# Copyright 2021-2025 HPMicro
# SPDX-License-Identifier: BSD-3-Clause
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
need_update = True
for p in os.listdir("packages"):
if p.startswith("hpm_sdk-"):
need_update = False
break
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
# toolchains options
ARCH='risc-v'
@@ -80,27 +113,27 @@ if PLATFORM == 'gcc':
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
LFLAGS += ' -O0'
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
elif BUILD == 'ram_release':
CFLAGS += ' -O2'
LFLAGS += ' -O2'
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
elif BUILD == 'flash_debug':
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
LFLAGS += ' -O0'
CFLAGS += ' -DFLASH_XIP=1'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
elif BUILD == 'flash_release':
CFLAGS += ' -O2'
LFLAGS += ' -O2'
CFLAGS += ' -DFLASH_XIP=1'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
else:
CFLAGS += ' -O2'
LFLAGS += ' -O2'
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
LFLAGS += ' -T ' + LINKER_FILE
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c
+129 -122
View File
@@ -4,125 +4,132 @@
*
*/
#include "hpm_common.h"
#include "hpm_soc.h"
#include "hpm_l1c_drv.h"
#include <rtthread.h>
void system_init(void);
extern int entry(void);
extern void __libc_init_array(void);
extern void __libc_fini_array(void);
void system_init(void)
{
disable_global_irq(CSR_MSTATUS_MIE_MASK);
disable_irq_from_intc();
enable_irq_from_intc();
enable_global_irq(CSR_MSTATUS_MIE_MASK);
#ifndef CONFIG_NOT_ENABLE_ICACHE
l1c_ic_enable();
#endif
#ifndef CONFIG_NOT_ENABLE_DCACHE
l1c_dc_enable();
#endif
}
__attribute__((weak)) void c_startup(void)
{
uint32_t i, size;
#ifdef FLASH_XIP
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
size = __vector_ram_end__ - __vector_ram_start__;
for (i = 0; i < size; i++) {
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
}
#endif
extern uint8_t __etext[];
extern uint8_t __bss_start__[], __bss_end__[];
extern uint8_t __tbss_start__[], __tbss_end__[];
extern uint8_t __tdata_start__[], __tdata_end__[];
extern uint8_t __data_start__[], __data_end__[];
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
/* tbss section */
size = __tbss_end__ - __tbss_start__;
for (i = 0; i < size; i++) {
*(__tbss_start__ + i) = 0;
}
/* bss section */
size = __bss_end__ - __bss_start__;
for (i = 0; i < size; i++) {
*(__bss_start__ + i) = 0;
}
/* noncacheable bss section */
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_bss_start__ + i) = 0;
}
/* tdata section LMA: etext */
size = __tdata_end__ - __tdata_start__;
for (i = 0; i < size; i++) {
*(__tdata_start__ + i) = *(__etext + i);
}
/* data section LMA: etext */
size = __data_end__ - __data_start__;
for (i = 0; i < size; i++) {
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
}
/* ramfunc section LMA: etext + data length */
size = __ramfunc_end__ - __ramfunc_start__;
for (i = 0; i < size; i++) {
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
}
/* noncacheable init section LMA: etext + data length + ramfunc length */
size = __noncacheable_init_end__ - __noncacheable_init_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
}
}
__attribute__((weak)) int main(void)
{
while(1);
}
void reset_handler(void)
{
/**
* Disable preemptive interrupt
*/
HPM_PLIC->FEATURE = 0;
/*
* Initialize LMA/VMA sections.
* Relocation for any sections that need to be copied from LMA to VMA.
*/
c_startup();
/* Call platform specific hardware initialization */
system_init();
/* Do global constructors */
__libc_init_array();
/* Entry function */
entry();
}
__attribute__((weak)) void _init()
{
}
#include "hpm_common.h"
#include "hpm_soc.h"
#include "hpm_l1c_drv.h"
#include <rtthread.h>
void system_init(void);
extern int entry(void);
extern void __libc_init_array(void);
extern void __libc_fini_array(void);
void system_init(void)
{
disable_global_irq(CSR_MSTATUS_MIE_MASK);
disable_irq_from_intc();
enable_irq_from_intc();
enable_global_irq(CSR_MSTATUS_MIE_MASK);
#ifndef CONFIG_NOT_ENABLE_ICACHE
l1c_ic_enable();
#endif
#ifndef CONFIG_NOT_ENABLE_DCACHE
l1c_dc_enable();
#endif
}
__attribute__((weak)) void c_startup(void)
{
#ifndef __SES_RISCV
uint32_t i, size;
#ifdef FLASH_XIP
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
size = __vector_ram_end__ - __vector_ram_start__;
for (i = 0; i < size; i++) {
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
}
#endif
extern uint8_t __etext[];
extern uint8_t __bss_start__[], __bss_end__[];
extern uint8_t __tbss_start__[], __tbss_end__[];
extern uint8_t __tdata_start__[], __tdata_end__[];
extern uint8_t __fast_load_addr__[];
extern uint8_t __noncacheable_init_load_addr__[];
extern uint8_t __data_load_addr__[];
extern uint8_t __tdata_load_addr__[];
extern uint8_t __data_start__[], __data_end__[];
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
/* tbss section */
size = __tbss_end__ - __tbss_start__;
for (i = 0; i < size; i++) {
*(__tbss_start__ + i) = 0;
}
/* bss section */
size = __bss_end__ - __bss_start__;
for (i = 0; i < size; i++) {
*(__bss_start__ + i) = 0;
}
/* noncacheable bss section */
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_bss_start__ + i) = 0;
}
/* tdata section LMA: etext */
size = __tdata_end__ - __tdata_start__;
for (i = 0; i < size; i++) {
*(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
}
/* data section LMA: etext */
size = __data_end__ - __data_start__;
for (i = 0; i < size; i++) {
*(__data_start__ + i) = *(__data_load_addr__ + i);
}
/* ramfunc section LMA: etext + data length */
size = __ramfunc_end__ - __ramfunc_start__;
for (i = 0; i < size; i++) {
*(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
}
/* noncacheable init section LMA: etext + data length + ramfunc length */
size = __noncacheable_init_end__ - __noncacheable_init_start__;
for (i = 0; i < size; i++) {
*(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
}
#endif
}
__attribute__((weak)) int main(void)
{
while(1);
}
void reset_handler(void)
{
/**
* Disable preemptive interrupt
*/
HPM_PLIC->FEATURE = 0;
/*
* Initialize LMA/VMA sections.
* Relocation for any sections that need to be copied from LMA to VMA.
*/
c_startup();
/* Call platform specific hardware initialization */
system_init();
#ifndef __SES_RISCV
/* Do global constructors */
__libc_init_array();
#endif
/* Entry function */
entry();
}
__attribute__((weak)) void _init(void)
{
}
bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S
+2 -1
View File
@@ -5,7 +5,8 @@
*
*/
#include "cpuport.h"
.section .text.entry, "ax"
.align 2
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
bsp/hpmicro/hpm5e00evk/.config
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bsp/hpmicro/hpm5e00evk/.cproject
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bsp/hpmicro/hpm5e00evk/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>blink_led</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.rt-thread.studio.rttnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>
bsp/hpmicro/hpm5e00evk/.settings/org.eclipse.core.runtime.prefs
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content-types/enabled=true
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
eclipse.preferences.version=1
bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini
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#RT-Thread Studio Project Configuration
# Fri Apr 25 13:53:29 2025
cfg_version=v3.0
board_name=
bsp_version=
bsp_path=
chip_name=
project_base_rtt_bsp=true
is_use_scons_build=true
hardware_adapter=
selected_rtt_version=latest
board_base_nano_proj=false
is_base_example_project=false
example_name=
project_type=rt-thread
os_branch=master
os_version=latest
project_name=blink_led
output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk
bsp/hpmicro/hpm5e00evk/Kconfig
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mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../..
PKGS_DIR := packages
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
rsource "board/Kconfig"
bsp/hpmicro/hpm5e00evk/README.md
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# HPMicro HPM5E00EVK BSP(Board Support Package) Introduction
[中文页](README_zh.md) |
## Introduction
This document provides brief introduction of the BSP (board support package) for the HPM5E00EVK development board.
The document consists of the following parts:
- HPM5E00EVK Board Resources Introduction
- Quickly Getting Started
- Refreences
By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
## Board Resources Introduction
HPM5E00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, motor control，etc.
![board](figures/board.png)
## Peripheral Condition
Each peripheral supporting condition for this BSP is as follows:
| **On-board Peripherals** | **Support** | **Note** |
| ------------------------ | ----------- | ------------------------------------- |
| USB | √ | |
| QSPI Flash | √ | |
| Ethernet | √ | |
| GPIO | √ | |
| SPI | √ | |
| I2C | √ | |
| PWM | √ | |
| On-Board Debugger | √ | ft2232 |
## Execution Instruction
### Quickly Getting Started
The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
#### Parpare Environment
- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
- For example: `C:\DevTools\openocd-hpmicro\bin`
#### Configure and Build project
Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
- Configure the project via `menuconfig` in `RT-Thread ENV`
- Build the project using `scons -jN`, `N` equals to the number of CPU cores
- Clean the project using `scons -c`
#### Hardware Connection
- Switch BOOT pin to 2'b00
- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
#### Dowload / Debug
- Users can download the project via the below command:
```console
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
```
- Users can debug the project via the below command:
- Connect debugger via `OpenOCD`:
```console
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg
```
- Start Debugger via `GDB`:
```console
%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
```
- In the `gdb shell`, type the following commands:
```console
load
c
```
### **Running Results**
Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
```
\ | /
- RT - Thread Operating System
/ | \ 5.2.2 build Aug 16 2025 18:18:18
2006 - 2025 Copyright by RT-Thread team
```
## **References**
- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
- [HPM5E00EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5e00evk)
bsp/hpmicro/hpm5e00evk/README_zh.md
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# 先楫 HPM5E00EVK BSP(板级支持包)说明
[English](README.md) |
## 简介
本文档为 HPM5E00EVK 的 BSP (板级支持包) 说明。
本文包含如下部分:
- HPM5E00EVK 板级资源介绍
- 快速上手指南
- 参考链接
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 板级资源介绍
HPM5E00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联和电机控制等应用。
开发板外观如下图所示：
![board](figures/board.png)
## 板载外设
本 BSP 目前对外设的支持情况如下:
| **板载外设** | **支持情况** | **备注** |
| ------------------------ | ----------- | ------------------------------------- |
| USB | √ | |
| QSPI Flash | √ | |
| 以太网 | √ | |
| GPIO | √ | |
| SPI | √ | |
| I2C | √ | |
| PWM | √ | |
| 板载调试器 | √ | ft2232 |
## 使用说明
### 快速开始
本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
#### 准备环境
- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
#### 配置和构建工程
通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
- 通过 `scons -c` 命令清除构建
#### 硬件连接
- 将BOOT 引脚拨到2'b00
- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
#### 下载 和 调试
- 通过如下命令完成下载:
```console
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
```
- 通过如下命令实现调试:
- 通过 `OpenOCD` 来连接开发板:
```console
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg
```
- 通过 `GDB` 实现调试:
```console
%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
```
- 在`GDB Shell`中使用如下命令来加载和运行:
```console
load
c
```
### **运行结果**
一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
```
\ | /
- RT - Thread Operating System
/ | \ 5.2.2 build Aug 16 2025 18:18:18
2006 - 2025 Copyright by RT-Thread team
```
## **参考链接**
- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
- [HPM5E00EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5e00evk)
bsp/hpmicro/hpm5e00evk/SConscript
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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
ASFLAGS = ' -I' + cwd
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/hpmicro/hpm5e00evk/SConstruct
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
AddOption('--run',
dest = 'run',
type='string',
nargs=1,
action = 'store',
default = "",
help = 'Upload or debug application using openocd')
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
else:
libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
GDB = rtconfig.GDB
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# includes rtt drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/hpmicro/hpm5e00evk/applications/SConscript
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import rtconfig
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPDEFINES=[]
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
Return('group')
bsp/hpmicro/hpm5e00evk/applications/main.c
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/*
* Copyright (c) 2021-2024 HPMicro
*
* Change Logs:
* Date Author Notes
* 2021-08-13 Fan YANG first version
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "rtt_board.h"
void thread_entry(void *arg);
int main(void)
{
app_init_led_pins();
static uint32_t led_thread_arg = 0;
rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
rt_thread_startup(led_thread);
return 0;
}
void thread_entry(void *arg)
{
while(1){
app_led_write(0, APP_LED_ON);
rt_thread_mdelay(500);
app_led_write(0, APP_LED_OFF);
rt_thread_mdelay(500);
app_led_write(1, APP_LED_ON);
rt_thread_mdelay(500);
app_led_write(1, APP_LED_OFF);
rt_thread_mdelay(500);
app_led_write(2, APP_LED_ON);
rt_thread_mdelay(500);
app_led_write(2, APP_LED_OFF);
rt_thread_mdelay(500);
}
}
bsp/hpmicro/hpm5e00evk/board/Kconfig
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bsp/hpmicro/hpm5e00evk/board/SConscript
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from building import *
cwd = GetCurrentDir()
# add the general drivers
src = Split("""
board.c
rtt_board.c
pinmux.c
fal_flash_port.c
""")
CPPPATH = [cwd]
CPPDEFINES=['D45', 'HPM5E31']
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/hpmicro/hpm5e00evk/board/board.c
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