mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-03-23 14:33:05 +08:00
fix[libcpu][risc-v]:
- Implement _noncache() and _cache() function features; - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration; - Update C908/C906 PTE macro definition configuration;
This commit is contained in:
shuta.lst
Rbb666
@@ -740,12 +740,18 @@ void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
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static int _noncache(rt_ubase_t *pte)
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{
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return 0;
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*pte &= ~PTE_PBMT_MASK;
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*pte |= PTE_PBMT_NC;
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rt_hw_cpu_dcache_clean(pte, sizeof(*pte));
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return RT_EOK;
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}
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static int _cache(rt_ubase_t *pte)
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{
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return 0;
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*pte &= ~PTE_PBMT_MASK;
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*pte |= PTE_PBMT_PMA;
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rt_hw_cpu_dcache_clean(pte, sizeof(*pte));
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return RT_EOK;
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}
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static int (*control_handler[MMU_CNTL_DUMMY_END])(rt_ubase_t *pte)=
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@@ -829,7 +835,7 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
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attr = MMU_MAP_K_RWCB;
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break;
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case NORMAL_NOCACHE_MEM:
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attr = MMU_MAP_K_RWCB;
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attr = MMU_MAP_K_RW;
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break;
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case DEVICE_MEM:
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attr = MMU_MAP_K_DEVICE;
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@@ -19,12 +19,31 @@
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#undef PAGE_SIZE
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/* C-SKY extend */
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#if !CONFIG_XUANTIE_SVPBMT
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/*
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* RISC-V Standard Svpbmt Extension (Bit 61-62)
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* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
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* 01: NC (Non-cacheable, Weakly-ordered)
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* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
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* 11: Reserved
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*/
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#define PTE_PBMT_PMA (0UL << 61)
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#define PTE_PBMT_NC (1UL << 61)
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#define PTE_PBMT_IO (2UL << 61)
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#define PTE_PBMT_MASK (3UL << 61)
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#else
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/* XuanTie Extension (Bit 59-63) */
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#define PTE_SEC (1UL << 59) /* Security */
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#define PTE_SHARE (1UL << 60) /* Shareable */
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#define PTE_BUF (1UL << 61) /* Bufferable */
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#define PTE_CACHE (1UL << 62) /* Cacheable */
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#define PTE_SO (1UL << 63) /* Strong Order */
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/* Compatible with Standard Svpbmt */
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#define PTE_PBMT_PMA (PTE_CACHE | PTE_BUF | PTE_SHARE)
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#define PTE_PBMT_NC (PTE_BUF | PTE_SHARE)
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#define PTE_PBMT_IO (PTE_SO | PTE_SHARE)
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#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
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#endif
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#define PAGE_OFFSET_SHIFT 0
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#define PAGE_OFFSET_BIT 12
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@@ -65,11 +84,20 @@
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#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
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#define PAGE_ATTR_DEV (PTE_SO)
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#if !CONFIG_XUANTIE_SVPBMT
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/*
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* Default Leaf Attribute:
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* RWX + User + Valid + Global + Accessed + Dirty + PMA(Cacheable)
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*/
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#define PAGE_DEFAULT_ATTR_LEAF \
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(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)
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#else
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#define PAGE_DEFAULT_ATTR_LEAF \
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(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | \
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PAGE_ATTR_RWX | PTE_V)
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#define PAGE_DEFAULT_ATTR_NEXT \
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(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
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#endif
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#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
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#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
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@@ -89,6 +117,38 @@
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#define ARCH_VADDR_WIDTH 39
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#define SATP_MODE SATP_MODE_SV39
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#if !CONFIG_XUANTIE_SVPBMT
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/*
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* Kernel Mappings
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*/
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/* Device: IO Mode (Strongly Ordered) */
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#define MMU_MAP_K_DEVICE (PTE_PBMT_IO | PTE_A | PTE_D | PTE_G | PTE_W | PTE_R | PTE_V)
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/* RW: Non-Cacheable (NC Mode) */
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#define MMU_MAP_K_RW (PTE_PBMT_NC | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)
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/* RWCB: Cacheable (PMA Mode) - Normal RAM */
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#define MMU_MAP_K_RWCB (PTE_PBMT_PMA | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)
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/*
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* User Mappings
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*/
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/* User RW: Non-Cacheable */
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#define MMU_MAP_U_RW (PTE_PBMT_NC | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)
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/* User RWCB: Cacheable */
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#define MMU_MAP_U_RWCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)
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/* User ROCB: Cacheable */
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#define MMU_MAP_U_ROCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_READONLY | PTE_V)
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/* User RWCB: Cacheable */
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#define MMU_MAP_U_RWCB_XN (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_XN | PTE_V)
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/* Early Mapping: Cacheable */
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#define MMU_MAP_EARLY \
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PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_PBMT_PMA)
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#else
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#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
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@@ -99,6 +159,8 @@
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#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_EARLY \
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PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF)
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#endif
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#define MMU_MAP_TRACE(attr) (attr)
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#define PTE_XWR_MASK 0xe
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@@ -23,15 +23,15 @@
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#if !CONFIG_XUANTIE_SVPBMT
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/*
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* RISC-V Standard Svpbmt Extension (Bit 61-62)
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* 00: PMA (Normal Memory, Cacheable)
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* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
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* 01: NC (Non-cacheable, Weakly-ordered)
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* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
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* 11: Reserved
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*/
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#define PTE_PBMT_MASK (3UL << 61)
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#define PTE_PBMT_PMA (0UL << 61)
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#define PTE_PBMT_NC (1UL << 61)
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#define PTE_PBMT_IO (2UL << 61)
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#define PTE_PBMT_MASK (3UL << 61)
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#else
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/* XuanTie Extension (Bit 59-63) */
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#define PTE_SEC (1UL << 59) /* Security */
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@@ -39,6 +39,11 @@
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#define PTE_BUF (1UL << 61) /* Bufferable */
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#define PTE_CACHE (1UL << 62) /* Cacheable */
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#define PTE_SO (1UL << 63) /* Strong Order */
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/* Compatible with Standard Svpbmt */
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#define PTE_PBMT_PMA (PTE_CACHE | PTE_BUF | PTE_SHARE)
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#define PTE_PBMT_NC (PTE_BUF | PTE_SHARE)
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#define PTE_PBMT_IO (PTE_SO | PTE_SHARE)
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#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
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#endif
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#define PAGE_OFFSET_SHIFT 0
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@@ -82,22 +87,13 @@
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*/
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#define PAGE_DEFAULT_ATTR_LEAF \
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(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)
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/*
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* Next Level Attribute:
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* Svpbmt spec requires PBMT bits to be 0 for non-leaf PTEs.
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*/
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#define PAGE_DEFAULT_ATTR_NEXT \
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(PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_A | PTE_D)
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#else
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#define PAGE_DEFAULT_ATTR_LEAF \
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(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | \
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PTE_CACHE | PTE_A | PTE_D)
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#define PAGE_DEFAULT_ATTR_NEXT \
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(PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D)
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#endif
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#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
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#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
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#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
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@@ -18,6 +18,18 @@
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#undef PAGE_SIZE
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/*
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* RISC-V Standard Svpbmt Extension (Bit 61-62)
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* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
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* 01: NC (Non-cacheable, Weakly-ordered)
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* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
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* 11: Reserved
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*/
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#define PTE_PBMT_PMA (0UL << 61)
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#define PTE_PBMT_NC (1UL << 61)
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#define PTE_PBMT_IO (2UL << 61)
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#define PTE_PBMT_MASK (3UL << 61)
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#define PAGE_OFFSET_SHIFT 0
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#define PAGE_OFFSET_BIT 12
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#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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