bsp: k230: add sysctl driver

SystemCtrl includes:
- boot
- clock
- power
- reset

These drivers are built-in by default.

Signed-off-by: Wang Chen <unicorn_wang@outlook.com>

bsp/k230/drivers/interdrv/sysctl/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Sysctl', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+file_list = os.listdir(cwd)
+
+for item in file_list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/k230/drivers/interdrv/sysctl/sysctl_boot/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Sysctl_boot', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+file_list = os.listdir(cwd)
+
+for item in file_list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/k230/drivers/interdrv/sysctl/sysctl_boot/sysctl_boot.c

@@ -0,0 +1,97 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtthread.h>
+#include "sysctl_boot.h"
+#include "ioremap.h"
+#include "board.h"
+
+volatile sysctl_boot_t* sysctl_boot = (volatile sysctl_boot_t*)BOOT_BASE_ADDR;
+
+sysctl_boot_mode_e sysctl_boot_get_boot_mode(void)
+{
+    switch(sysctl_boot->soc_boot_ctl & 0x3) /* bit 0~1 */
+    {
+        case 1:
+            return SYSCTL_BOOT_NANDFLASH;
+        case 2:
+            return SYSCTL_BOOT_EMMC;
+        case 3:
+            return SYSCTL_BOOT_SDCARD;
+        case 0:
+        default:
+            return SYSCTL_BOOT_NORFLASH;
+    }
+}
+
+bool sysctl_boot_get_otp_bypass(void)
+{
+    if(sysctl_boot->soc_boot_ctl & 0x10)
+        return true;
+    else
+        return false;
+}
+
+void sysctl_boot_set_pll_lock(void)
+{
+    sysctl_boot->soc_boot_ctl |= 1 << 3;
+}
+
+void sysctl_boot_set_spi2axi(void)
+{
+    sysctl_boot->soc_boot_ctl |= 1 << 2;
+}
+
+void sysctl_boot_reset_soc(void)
+{
+    sysctl_boot->soc_glb_rst |= (1 << 0) | (1 << 16);
+    while(1)
+    {
+    }
+}
+
+
+void sysctl_boot_soc_sleep_ctl(void)
+{
+    sysctl_boot->soc_slp_ctl |= (1 << 4) | (1 << 20);
+}
+
+int sysctl_boot_read_is_boot_wakeup(void)
+{
+    return sysctl_boot->soc_wakeup_src;
+}
+
+int rt_hw_sysctl_boot_init(void)
+{
+    sysctl_boot = rt_ioremap((void*)BOOT_BASE_ADDR, BOOT_IO_SIZE);
+    if(!sysctl_boot)
+    {
+        rt_kprintf("sysctl_boot ioremap error\n");
+        return -1;
+    }
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_sysctl_boot_init);

bsp/k230/drivers/interdrv/sysctl/sysctl_boot/sysctl_boot.h

@@ -0,0 +1,96 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SYSCTL_BOOT_H__
+#define __SYSCTL_BOOT_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef struct pll {
+    volatile uint32_t cfg0;
+    volatile uint32_t cfg1;
+    volatile uint32_t ctl;
+    volatile uint32_t state;
+} pll_t;
+
+/*
+ * pll related registers see TRM 2.2.4 Table 2-2-8
+ * soc_glb_rst: see TRM 2.1.4 Table 2-2-1
+ * Others: see TRM 2.3.4 Table 2-3-2
+ */
+typedef struct sysctl_boot {
+    pll_t pll[4];
+    volatile uint32_t soc_boot_ctl;         /* 0x40 */
+    volatile uint32_t reserved0[7];         /* 0x44 0x48 0x4c 0x50 0x54 0x58 0x5c*/
+    volatile uint32_t soc_glb_rst;          /* 0x60 */
+    volatile uint32_t soc_rst_tim;          /* 0x64 */
+    volatile uint32_t soc_slp_tim;          /* 0x68 */
+    volatile uint32_t soc_slp_ctl;          /* 0x6c */
+    volatile uint32_t clk_stable_tim;       /* 0x70 */
+    volatile uint32_t cpu_wakeup_tim;       /* 0x74 */
+    volatile uint32_t soc_wakeup_src;       /* 0x78 */
+    volatile uint32_t cpu_wakeup_cfg;       /* 0x7c */
+    volatile uint32_t timer_pause_ctl;      /* 0x80 */
+    volatile uint32_t reserved1[3];         /* 0x84 0x88 0x8c */
+    volatile uint32_t sysctl_int0_raw;      /* 0x90 */
+    volatile uint32_t sysctl_int0_en;       /* 0x94 */
+    volatile uint32_t sysctl_int0_state;    /* 0x98 */
+    volatile uint32_t reserved2;            /* 0x9c */
+    volatile uint32_t sysctl_int1_raw;      /* 0xa0 */
+    volatile uint32_t sysctl_int1_en;       /* 0xa4 */
+    volatile uint32_t sysctl_int1_state;    /* 0xa8 */
+    volatile uint32_t reserved3;            /* 0xac */
+    volatile uint32_t sysctl_int2_raw;      /* 0xb0 */
+    volatile uint32_t sysctl_int2_en;       /* 0xb4 */
+    volatile uint32_t sysctl_int2_state;    /* 0xb8 */
+    volatile uint32_t reserved4[17];        /* 0xbc 0xc0-0xcc 0xd0-0xdc 0xe0-0xec 0xf0-0xfc*/
+    volatile uint32_t cpu0_hart_rstvec;     /* 0x100 */
+    volatile uint32_t cpu1_hart_rstvec;     /* 0x104 */
+    volatile uint32_t reserved5[4];         /* 0x108 0x10c 0x110 0x114 */
+    volatile uint32_t soc_sleep_mask;       /* 0x118 */
+} sysctl_boot_t;
+
+
+/* See TRM 1.4.1 Boot media Selection */
+typedef enum
+{
+    SYSCTL_BOOT_NORFLASH    = 0,
+    SYSCTL_BOOT_NANDFLASH   = 1,
+    SYSCTL_BOOT_EMMC        = 2,
+    SYSCTL_BOOT_SDCARD      = 3,
+    SYSCTL_BOOT_MAX,
+} sysctl_boot_mode_e;
+
+sysctl_boot_mode_e sysctl_boot_get_boot_mode(void);
+bool sysctl_boot_get_otp_bypass(void);
+void sysctl_boot_set_pll_lock(void);
+void sysctl_boot_set_spi2axi(void);
+void sysctl_boot_reset_soc(void);
+
+int sysctl_boot_read_is_boot_wakeup(void);
+void sysctl_boot_soc_sleep_ctl(void);
+
+#endif

bsp/k230/drivers/interdrv/sysctl/sysctl_clock/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Sysctl_clock', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+file_list = os.listdir(cwd)
+
+for item in file_list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/k230/drivers/interdrv/sysctl/sysctl_power/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Sysctl_power', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+file_list = os.listdir(cwd)
+
+for item in file_list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/k230/drivers/interdrv/sysctl/sysctl_power/sysctl_pwr.h

@@ -0,0 +1,174 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SYSCTL_PWR_H__
+#define __SYSCTL_PWR_H__
+
+/* created by yangfan */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* See TRM 2.3.4 Table 2-3-3 */
+typedef struct
+{
+    volatile uint32_t cpu0_pwr_tim;         /* 0x00 */
+    volatile uint32_t cpu0_lpi_tim;         /* 0x04 */
+    volatile uint32_t cpu0_pwr_lpi_ctl;     /* 0x08 */
+    volatile uint32_t cpu0_pwr_lpi_state;   /* 0x0c */
+
+    volatile uint32_t cpu1_pwr_tim;         /* 0x10 */
+    volatile uint32_t cpu1_lpi_tim;         /* 0x14 */
+    volatile uint32_t cpu1_pwr_lpi_ctl;     /* 0x18 */
+    volatile uint32_t cpu1_pwr_lpi_state;   /* 0x1c */
+
+    volatile uint32_t ai_pwr_tim;           /* 0x20 */
+    volatile uint32_t ai_lpi_tim;           /* 0x24 */
+    volatile uint32_t ai_pwr_lpi_ctl;       /* 0x28 */
+    volatile uint32_t ai_pwr_lpi_state;     /* 0x2c */
+
+    volatile uint32_t disp_pwr_tim;         /* 0x30 */
+    volatile uint32_t disp_lpi_tim;         /* 0x34 */
+    volatile uint32_t disp_gpu_tim;         /* 0x38 */
+    volatile uint32_t disp_lpi_ctl;         /* 0x3c */
+    volatile uint32_t disp_lpi_state;       /* 0x40 */
+    volatile uint32_t disp_reserved[7];     /* 0x44-0x4c, 0x50-0x5c */
+
+    volatile uint32_t shrm_pwr_tim;         /* 0x60 */
+    volatile uint32_t shrm_lpi_tim;         /* 0x64 */
+    volatile uint32_t shrm_pwr_lpi_ctl;     /* 0x68 */
+    volatile uint32_t shrm_pwr_lpi_state;   /* 0x6c */
+
+    volatile uint32_t vpu_pwr_tim;          /* 0x70 */
+    volatile uint32_t vpu_lpi_tim;          /* 0x74 */
+    volatile uint32_t vpu_qch_tim;          /* 0x78 */
+    volatile uint32_t vpu_pwr_lpi_ctl;      /* 0x7c */
+    volatile uint32_t vpu_lpi_state;        /* 0x80 */
+    volatile uint32_t vpu_reserved[3];      /* 0x84-0x8c */
+
+    volatile uint32_t mctl_pwr_tim0;        /* 0x90 */
+    volatile uint32_t mctl_noc_lpi_tim;     /* 0x94 */
+    volatile uint32_t mctl_axi_lpi_tim;     /* 0x98 */
+    volatile uint32_t mctl_pwr_lpi_ctl;     /* 0x9c */
+    volatile uint32_t mctl_clock_switch;    /* 0xa0 */
+    volatile uint32_t mctl_lpi_state;       /* 0xa4 */
+    volatile uint32_t mctl_reserved[22];    /* 0xa8-0xac, 0xb0-0xbc, 0xc0-0xcc, 0xd0-0xdc, 0xe0-0xec, 0xf0-0xfc */
+
+    volatile uint32_t dpu_pwr_tim;          /* 0x100 */
+    volatile uint32_t dpu_lpi_tim;          /* 0x104 */
+    volatile uint32_t dpu_pwr_lpi_ctl;      /* 0x108 */
+    volatile uint32_t dpu_pwr_lpi_state;    /* 0x10c */
+
+    volatile uint32_t hi_pwr_tim;           /* 0x110 */
+    volatile uint32_t hi_lpi_tim;           /* 0x114 */
+    volatile uint32_t hi_pwr_lpi_ctl;       /* 0x118 */
+    volatile uint32_t hi_lpi_state;         /* 0x11c */
+
+    volatile uint32_t ls_pwr_tim;           /* 0x120 */
+    volatile uint32_t ls_lpi_tim;           /* 0x124 */
+    volatile uint32_t ls_pwr_lpi_ctl;       /* 0x128 */
+    volatile uint32_t ls_lpi_state;         /* 0x12c */
+
+    volatile uint32_t sec_pwr_tim;          /* 0x130 */
+    volatile uint32_t sec_lpi_tim;          /* 0x134 */
+    volatile uint32_t sec_pwr_lpi_ctl;      /* 0x138 */
+    volatile uint32_t sec_pwr_lpi_state;    /* 0x13c */
+
+    volatile uint32_t isp_pwr_tim;          /* 0x140 */
+    volatile uint32_t isp_lpi_tim;          /* 0x144 */
+    volatile uint32_t isp_pwr_lpi_ctl;      /* 0x148 */
+    volatile uint32_t isp_pwr_lpi_state;    /* 0x14c */
+
+    volatile uint32_t pmu_pwr_tim;          /* 0x150 */
+    volatile uint32_t pmu_lpi_tim;          /* 0x154 */
+    volatile uint32_t pmu_pwr_lpi_ctl;      /* 0x158 */
+    volatile uint32_t pmu_pwr_lpi_state;    /* 0x15c */
+
+    volatile uint32_t repair_status;        /* 0x160 */
+    volatile uint32_t sram0_repair_tim;     /* 0x164 */
+    volatile uint32_t ssys_ctl_gpio_ctl;    /* 0x168 */
+    volatile uint32_t ssys_reserved;        /* 0x16c */
+    volatile uint32_t ssys_ctl_gpio_en0;    /* 0x170 */
+    volatile uint32_t ssys_ctl_gpio_en1;    /* 0x174 */
+
+    volatile uint32_t cpu_repair_tim;       /* 0x178 */
+} sysctl_pwr_s;
+
+/* See TRM 2.3.1 Table 2-3-1 */
+typedef enum
+{
+    SYSCTL_PD_CPU1,
+    SYSCTL_PD_AI,
+    SYSCTL_PD_DISP,
+    SYSCTL_PD_VPU,
+    SYSCTL_PD_DPU,
+    SYSCTL_PD_MAX,
+} sysctl_pwr_domain_e;
+
+
+typedef enum
+{
+    SYSCTL_PWR_ACK_TO_TIM,  /* idleReq to idleAck max time */
+    SYSCTL_PWR_IDLE_TO_TIM, /* idleAck to idle max time */
+    SYSCTL_PWR_IDLE_HD_TIM, /* idle hold tim, from idle to cancel idleReq min time */
+    SYSCTL_PWR_ISO_SU_TIM,  /* isolation setup tim */
+    SYSCTL_PWR_PD_HD_TIM,   /* power done hardware tim */
+    SYSCTL_PWR_SU_TIM,      /* Power bringup tim */
+    SYSCTL_PWR_WFI_TIM,     /* wait for interrupt tim*/
+    SYSCTL_PWR_MAX_TIM,
+} sysctl_pwr_tim_e;
+
+
+bool sysctl_pwr_set_iso_su_tim(volatile uint32_t *reg, uint32_t iso_su_tim);
+bool sysctl_pwr_set_pd_hd_tim(volatile uint32_t *reg, uint32_t pd_hd_tim);
+bool sysctl_pwr_set_pwr_su_tim(volatile uint32_t *reg, uint32_t pwr_su_tim);
+bool sysctl_pwr_set_ack_to_tim(volatile uint32_t *reg, uint32_t ack_to_tim);
+bool sysctl_pwr_set_idle_to_tim(volatile uint32_t *reg, uint32_t idle_to_tim);
+bool sysctl_pwr_set_idle_hd_tim(volatile uint32_t *reg, uint32_t idle_hd_tim);
+bool sysctl_pwr_set_wfi_tim(volatile uint32_t *reg, uint32_t wfi_tim);
+bool sysctl_pwr_set_tim(sysctl_pwr_domain_e powerdomain, sysctl_pwr_tim_e timtype, uint32_t tim_value);
+bool sysctl_pwr_get_iso_su_tim(volatile uint32_t *reg, uint32_t *iso_su_tim);
+bool sysctl_pwr_get_pd_hd_tim(volatile uint32_t *reg, uint32_t *pd_hd_tim);
+bool sysctl_pwr_get_pwr_su_tim(volatile uint32_t *reg, uint32_t *pwr_su_tim);
+bool sysctl_pwr_get_ack_to_tim(volatile uint32_t *reg, uint32_t *ack_to_tim);
+bool sysctl_pwr_get_idle_to_tim(volatile uint32_t *reg, uint32_t *idle_to_tim);
+bool sysctl_pwr_get_idle_hd_tim(volatile uint32_t *reg, uint32_t *idle_hd_tim);
+bool sysctl_pwr_get_wfi_tim(volatile uint32_t *reg, uint32_t *wfi_tim);
+bool sysctl_pwr_get_tim(sysctl_pwr_domain_e powerdomain, sysctl_pwr_tim_e timtype, uint32_t *tim_value);
+bool sysctl_pwr_set_poweroff_keep_reset(sysctl_pwr_domain_e powerdomain, bool enable);
+bool sysctl_pwr_get_poweroff_keep_reset(sysctl_pwr_domain_e powerdomain, bool *enable);
+bool sysctl_pwr_set_auto_pwr(sysctl_pwr_domain_e powerdomain, bool enable);
+bool sysctl_pwr_get_auto_pwr(sysctl_pwr_domain_e powerdomain, bool *enable);
+bool sysctl_pwr_set_repair_enable(sysctl_pwr_domain_e powerdomain);
+bool sysctl_pwr_check_repair_done(sysctl_pwr_domain_e powerdomain);
+bool sysctl_pwr_set_lpi(sysctl_pwr_domain_e powerdomain, bool enable);
+bool sysctl_pwr_set_pwr_reg(volatile uint32_t *regctl, volatile uint32_t *regsta, bool enable);
+bool sysctl_pwr_set_power(sysctl_pwr_domain_e powerdomain, bool enable);
+
+/* Following two APIs are used to control the power on and off of the SOC power domain */
+bool sysctl_pwr_up(sysctl_pwr_domain_e powerdomain);
+bool sysctl_pwr_off(sysctl_pwr_domain_e powerdomain);
+
+#endif

bsp/k230/drivers/interdrv/sysctl/sysctl_reset/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Sysctl_reset', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+file_list = os.listdir(cwd)
+
+for item in file_list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/k230/drivers/interdrv/sysctl/sysctl_reset/sysctl_rst.h

@@ -0,0 +1,199 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SYSCTL_RST_H__
+#define __SYSCTL_RST_H__
+
+/* created by yangfan */
+
+#include <stdint.h>
+#include "stdbool.h"
+
+typedef enum
+{
+    SYSCTL_RESET_CPU0_CORE,
+    /* SYSCTL_RESET_CPU0_APB, */
+    /* SYSCTL_RESET_CPU0_TDI, */
+    SYSCTL_RESET_CPU0_FLUSH,
+    SYSCTL_RESET_CPU1_CORE,
+    /* SYSCTL_RESET_CPU1_APB, */
+    SYSCTL_RESET_CPU1_FLUSH,
+    SYSCTL_RESET_AI,
+    SYSCTL_RESET_VPU,
+    SYSCTL_RESET_HS,
+    SYSCTL_RESET_HS_AHB,
+    SYSCTL_RESET_SDIO0,
+    SYSCTL_RESET_SDIO1,
+    SYSCTL_RESET_SDIO_AXI,
+    SYSCTL_RESET_USB0,
+    SYSCTL_RESET_USB1,
+    SYSCTL_RESET_USB0_AHB,
+    SYSCTL_RESET_USB1_AHB,
+    SYSCTL_RESET_SPI0,
+    SYSCTL_RESET_SPI1,
+    SYSCTL_RESET_SPI2,
+    SYSCTL_RESET_SEC,
+    SYSCTL_RESET_PDMA,
+    SYSCTL_RESET_SDMA,
+    SYSCTL_RESET_DECOMPRESS,
+    SYSCTL_RESET_SRAM,
+    SYSCTL_RESET_SHRM_AXIM,
+    SYSCTL_RESET_SHRM_AXIS,
+    SYSCTL_RESET_SHRM_APB,
+    SYSCTL_RESET_NONAI2D,
+    SYSCTL_RESET_MCTL,
+    SYSCTL_RESET_ISP,
+    SYSCTL_RESET_ISP_DW,
+    SYSCTL_RESET_CSI0_APB,
+    SYSCTL_RESET_CSI1_APB,
+    SYSCTL_RESET_CSI2_APB,
+    SYSCTL_RESET_CSI_DPHY_APB,
+    SYSCTL_RESET_ISP_AHB,
+    SYSCTL_RESET_M0,
+    SYSCTL_RESET_M1,
+    SYSCTL_RESET_M2,
+    SYSCTL_RESET_DPU,
+    SYSCTL_RESET_DISP,
+    SYSCTL_RESET_GPU,
+    SYSCTL_RESET_AUDIO,
+    SYSCTL_RESET_TIMER0,
+    SYSCTL_RESET_TIMER1,
+    SYSCTL_RESET_TIMER2,
+    SYSCTL_RESET_TIMER3,
+    SYSCTL_RESET_TIMER4,
+    SYSCTL_RESET_TIMER5,
+    SYSCTL_RESET_TIMER_APB,
+    SYSCTL_RESET_HDI,
+    SYSCTL_RESET_WDT0,
+    SYSCTL_RESET_WDT1,
+    SYSCTL_RESET_WDT0_APB,
+    SYSCTL_RESET_WDT1_APB,
+    SYSCTL_RESET_TS_APB,
+    SYSCTL_RESET_MAILBOX,
+    SYSCTL_RESET_STC,
+    SYSCTL_RESET_PMU,
+    SYSCTL_RESET_LS_APB,
+    SYSCTL_RESET_UART0,
+    SYSCTL_RESET_UART1,
+    SYSCTL_RESET_UART2,
+    SYSCTL_RESET_UART3,
+    SYSCTL_RESET_UART4,
+    SYSCTL_RESET_I2C0,
+    SYSCTL_RESET_I2C1,
+    SYSCTL_RESET_I2C2,
+    SYSCTL_RESET_I2C3,
+    SYSCTL_RESET_I2C4,
+    SYSCTL_RESET_JAMLINK0_APB,
+    SYSCTL_RESET_JAMLINK1_APB,
+    SYSCTL_RESET_JAMLINK2_APB,
+    SYSCTL_RESET_JAMLINK3_APB,
+    SYSCTL_RESET_CODEC_APB,
+    SYSCTL_RESET_GPIO_DB,
+    SYSCTL_RESET_GPIO_APB,
+    SYSCTL_RESET_ADC,
+    SYSCTL_RESET_ADC_APB,
+    SYSCTL_RESET_PWM_APB,
+    SYSCTL_RESET_SPI2AXI,
+} sysctl_reset_e;
+
+typedef enum
+{
+    SYSCTL_RESET_TIME_CPU0,
+    SYSCTL_RESET_TIME_CPU0_APB,
+    SYSCTL_RESET_TIME_CPU1,
+    SYSCTL_RESET_TIME_CPU1_APB,
+    SYSCTL_RESET_TIME_AI,
+    SYSCTL_RESET_TIME_VPU,
+    SYSCTL_RESET_TIME_HS_HCLK,
+    SYSCTL_RESET_TIME_SDCTL,
+    SYSCTL_RESET_TIME_USB,
+    SYSCTL_RESET_TIME_USB_AHB,
+    SYSCTL_RESET_TIME_SPI,
+    SYSCTL_RESET_TIME_SEC_SYS,
+    SYSCTL_RESET_TIME_DMAC,
+    SYSCTL_RESET_TIME_DECOMPRESS,
+    SYSCTL_RESET_TIME_SRAM,
+    SYSCTL_RESET_TIME_NONAI2D,
+    SYSCTL_RESET_TIME_MCTL,
+    SYSCTL_RESET_TIME_ISP,
+    SYSCTL_RESET_TIME_ISP_DW,
+    SYSCTL_RESET_TIME_DPU,
+    SYSCTL_RESET_TIME_DISP_SYS,
+    SYSCTL_RESET_TIME_V2P5D_SYS,
+    SYSCTL_RESET_TIME_AUDIO,
+} sysctl_reset_time_e;
+
+/* See TRM 2.1.4, Table 2-1-2 */
+typedef struct {
+    volatile uint32_t cpu0_rst_tim;         /* 0x00 */
+    volatile uint32_t cpu0_rst_ctl;         /* 0x04 */
+    volatile uint32_t cpu1_rst_tim;         /* 0x08 */
+    volatile uint32_t cpu1_rst_ctl;         /* 0x0c */
+    volatile uint32_t ai_rst_tim;           /* 0x10 */
+    volatile uint32_t ai_rst_ctl;           /* 0x14 */
+    volatile uint32_t vpu_rst_tim;          /* 0x18 */
+    volatile uint32_t vpu_rst_ctl;          /* 0x1c */
+    volatile uint32_t soc_ctl_rst_ctl;      /* 0x20 */
+    volatile uint32_t losys_rst_ctl;        /* 0x24 */
+    volatile uint32_t hisys_hclk_tim;       /* 0x28 */
+    volatile uint32_t hisys_rst_ctl;        /* 0x2c */
+    volatile uint32_t sdctl_rst_tim;        /* 0x30 */
+    volatile uint32_t sdc_rst_ctl;          /* 0x34 */
+    volatile uint32_t usb_rst_tim;          /* 0x38 */
+    volatile uint32_t usb_rst_ctl;          /* 0x3c */
+    volatile uint32_t spi_rst_tim;          /* 0x40 */
+    volatile uint32_t spi_rst_ctl;          /* 0x44 */
+    volatile uint32_t sec_sys_rst_tim;      /* 0x48 */
+    volatile uint32_t sec_rst_ctl;          /* 0x4c */
+    volatile uint32_t dmac_rst_tim;         /* 0x50 */
+    volatile uint32_t dma_rst_ctl;          /* 0x54 */
+    volatile uint32_t decompress_rst_tim;   /* 0x58 */
+    volatile uint32_t decompress_rst_ctl;   /* 0x5c */
+    volatile uint32_t sram_rst_tim;         /* 0x60 */
+    volatile uint32_t sram_rst_ctl;         /* 0x64 */
+    volatile uint32_t nonai2d_rst_tim;      /* 0x68 */
+    volatile uint32_t nonai2d_rst_ctl;      /* 0x6c */
+    volatile uint32_t mctl_rst_tim;         /* 0x70 */
+    volatile uint32_t mctl_rst_ctl;         /* 0x74 */
+    volatile uint32_t isp_rst_tim;          /* 0x78 */
+    volatile uint32_t isp_dw_rst_tim;       /* 0x7c */
+    volatile uint32_t isp_rst_ctl;          /* 0x80 */
+    volatile uint32_t dpu_rst_tim;          /* 0x84 */
+    volatile uint32_t dpu_rst_ctl;          /* 0x88 */
+    volatile uint32_t disp_sys_rst_tim;     /* 0x8c */
+    volatile uint32_t disp_rst_ctl;         /* 0x90 */
+    volatile uint32_t v2p5d_sys_rst_tim;    /* 0x94 */
+    volatile uint32_t v2p5d_rst_ctl;        /* 0x98 */
+    volatile uint32_t reserved;             /* 0x9c */
+    volatile uint32_t audio_rst_tim;        /* 0xa0 */
+    volatile uint32_t audio_rst_ctl;        /* 0xa4 */
+    volatile uint32_t spi2axi_rst_ctl;      /* 0xa8 */
+} sysctl_rst_t;
+
+/* Just call this API to reset */
+bool sysctl_reset(sysctl_reset_e reset);
+bool sysctl_set_reset_time(sysctl_reset_time_e reset, uint32_t tim0, uint32_t tim1, uint32_t tim2);
+
+#endif