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[BSP][stm32f103-100ask-pro]add ext_sram driver to stm32f103-100ask-pro

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This commit is contained in:
WKJay
2024-05-29 20:19:46 +08:00
committed by Rbb666
parent 07d7b71345
commit 2fd9ff56dc
9 changed files with 616 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/stm32/stm32f103-100ask-pro/README.md
+1
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@@ -45,6 +45,7 @@ STM32F103 Pro开发板是百问网推出的一块基于ARM Cortex-M3内核的开
| 电位器 | 支持 | ADC1/2/3 CH10 |
| SPI FLASH | 支持 | W25Q64 |
| EEPROM | 支持 | 软件i2c1 |
| SRAM | 支持 | IS62WV51216BLL |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
| UART | 支持 | UART1/2/3 |
bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/.mxproject
+2 -2
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File diff suppressed because one or more lines are too long
bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/CubeMX_Config.ioc
+227 -61
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File diff suppressed because it is too large Load Diff
bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
+1 -1
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@@ -63,7 +63,7 @@
/*#define HAL_SDRAM_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/*#define HAL_SRAM_MODULE_ENABLED */
#define HAL_SRAM_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
+184
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@@ -870,6 +870,190 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
}
static uint32_t FSMC_Initialized = 0;
static void HAL_FSMC_MspInit(void){
/* USER CODE BEGIN FSMC_MspInit 0 */
/* USER CODE END FSMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
if (FSMC_Initialized) {
return;
}
FSMC_Initialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FSMC_CLK_ENABLE();
/** FSMC GPIO Configuration
PF0 ------> FSMC_A0
PF1 ------> FSMC_A1
PF2 ------> FSMC_A2
PF3 ------> FSMC_A3
PF4 ------> FSMC_A4
PF5 ------> FSMC_A5
PF12 ------> FSMC_A6
PF13 ------> FSMC_A7
PF14 ------> FSMC_A8
PF15 ------> FSMC_A9
PG0 ------> FSMC_A10
PG1 ------> FSMC_A11
PE7 ------> FSMC_D4
PE8 ------> FSMC_D5
PE9 ------> FSMC_D6
PE10 ------> FSMC_D7
PE11 ------> FSMC_D8
PE12 ------> FSMC_D9
PE13 ------> FSMC_D10
PE14 ------> FSMC_D11
PE15 ------> FSMC_D12
PD8 ------> FSMC_D13
PD9 ------> FSMC_D14
PD10 ------> FSMC_D15
PD11 ------> FSMC_A16
PD12 ------> FSMC_A17
PD13 ------> FSMC_A18
PD14 ------> FSMC_D0
PD15 ------> FSMC_D1
PG2 ------> FSMC_A12
PG3 ------> FSMC_A13
PG4 ------> FSMC_A14
PG5 ------> FSMC_A15
PD0 ------> FSMC_D2
PD1 ------> FSMC_D3
PD4 ------> FSMC_NOE
PD5 ------> FSMC_NWE
PG10 ------> FSMC_NE3
PE0 ------> FSMC_NBL0
PE1 ------> FSMC_NBL1
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN FSMC_MspInit 1 */
/* USER CODE END FSMC_MspInit 1 */
}
void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
/* USER CODE BEGIN SRAM_MspInit 0 */
/* USER CODE END SRAM_MspInit 0 */
HAL_FSMC_MspInit();
/* USER CODE BEGIN SRAM_MspInit 1 */
/* USER CODE END SRAM_MspInit 1 */
}
static uint32_t FSMC_DeInitialized = 0;
static void HAL_FSMC_MspDeInit(void){
/* USER CODE BEGIN FSMC_MspDeInit 0 */
/* USER CODE END FSMC_MspDeInit 0 */
if (FSMC_DeInitialized) {
return;
}
FSMC_DeInitialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FSMC_CLK_DISABLE();
/** FSMC GPIO Configuration
PF0 ------> FSMC_A0
PF1 ------> FSMC_A1
PF2 ------> FSMC_A2
PF3 ------> FSMC_A3
PF4 ------> FSMC_A4
PF5 ------> FSMC_A5
PF12 ------> FSMC_A6
PF13 ------> FSMC_A7
PF14 ------> FSMC_A8
PF15 ------> FSMC_A9
PG0 ------> FSMC_A10
PG1 ------> FSMC_A11
PE7 ------> FSMC_D4
PE8 ------> FSMC_D5
PE9 ------> FSMC_D6
PE10 ------> FSMC_D7
PE11 ------> FSMC_D8
PE12 ------> FSMC_D9
PE13 ------> FSMC_D10
PE14 ------> FSMC_D11
PE15 ------> FSMC_D12
PD8 ------> FSMC_D13
PD9 ------> FSMC_D14
PD10 ------> FSMC_D15
PD11 ------> FSMC_A16
PD12 ------> FSMC_A17
PD13 ------> FSMC_A18
PD14 ------> FSMC_D0
PD15 ------> FSMC_D1
PG2 ------> FSMC_A12
PG3 ------> FSMC_A13
PG4 ------> FSMC_A14
PG5 ------> FSMC_A15
PD0 ------> FSMC_D2
PD1 ------> FSMC_D3
PD4 ------> FSMC_NOE
PD5 ------> FSMC_NWE
PG10 ------> FSMC_NE3
PE0 ------> FSMC_NBL0
PE1 ------> FSMC_NBL1
*/
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
|GPIO_PIN_14|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
/* USER CODE BEGIN FSMC_MspDeInit 1 */
/* USER CODE END FSMC_MspDeInit 1 */
}
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){
/* USER CODE BEGIN SRAM_MspDeInit 0 */
/* USER CODE END SRAM_MspDeInit 0 */
HAL_FSMC_MspDeInit();
/* USER CODE BEGIN SRAM_MspDeInit 1 */
/* USER CODE END SRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
bsp/stm32/stm32f103-100ask-pro/board/Kconfig
+6
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@@ -37,6 +37,12 @@ menu "Onboard Peripheral Drivers"
select BSP_USING_I2C1
default n
config BSP_USING_EXT_SRAM
bool "Enable external sram"
default n
help
Chip name is IS62WV51216BLL, 1Mbytes static RAMs organized as 512K words by 16bits.
endmenu
menu "On-chip Peripheral Drivers"
bsp/stm32/stm32f103-100ask-pro/board/SConscript
+3
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@@ -12,6 +12,9 @@ board.c
CubeMX_Config/Src/stm32f1xx_hal_msp.c
''')
if GetDepend(['BSP_USING_EXT_SRAM']):
src += Glob('ports/drv_sram.c')
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/spi_flash_init.c')
bsp/stm32/stm32f103-100ask-pro/board/ports/drv_sram.c
+169
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@@ -0,0 +1,169 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-01-05 linyiyang first version
* 2024-05-28 WKjay add this file to stm32f103-100ask-pro
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef BSP_USING_EXT_SRAM
#include <sram_port.h>
#define DRV_DEBUG
#define LOG_TAG "drv.ext_sram"
#include <drv_log.h>
static SRAM_HandleTypeDef hsram1;
#ifdef RT_USING_MEMHEAP_AS_HEAP
static struct rt_memheap system_heap;
#endif
static int external_sram_init(void)
{
int result = RT_EOK;
FSMC_NORSRAM_TimingTypeDef Timing = {0};
/** Perform the SRAM1 memory initialization sequence
*/
hsram1.Instance = FSMC_NORSRAM_DEVICE;
hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
/* hsram1.Init */
hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
#if EXTERNAL_SRAM_DATA_WIDTH == 8
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
#else
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_32;
#endif
hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
/* Timing */
Timing.AddressSetupTime = 0;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 3;
Timing.BusTurnAroundDuration = 0;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
/* ExtTiming */
/* Initialize the SRAM controller */
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
{
LOG_E("External SRAM init failed!");
result = -RT_ERROR;
}
else
{
LOG_D("External sram init success, mapped at 0x%X, size is %d bytes, data width is %d", EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE, EXTERNAL_SRAM_DATA_WIDTH);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
rt_memheap_init(&system_heap, "ext_sram", (void *)EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE);
#endif
}
/** Disconnect NADV
*/
__HAL_AFIO_FSMCNADV_DISCONNECTED();
return result;
}
INIT_BOARD_EXPORT(external_sram_init);
#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
int external_sram_test(void)
{
int i = 0;
uint32_t start_time = 0, time_cast = 0;
#if EXTERNAL_SRAM_DATA_WIDTH == 8
char data_width = 1;
uint8_t data = 0;
uint8_t *ptr = (uint8_t *)EXTERNAL_SRAM_BANK_ADDR;
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
char data_width = 2;
uint16_t data = 0;
uint16_t *ptr = (uint16_t *)EXTERNAL_SRAM_BANK_ADDR;
#else
char data_width = 4;
uint32_t data = 0;
uint32_t *ptr = (uint32_t *)EXTERNAL_SRAM_BANK_ADDR;
#endif
/* write data */
LOG_D("Writing the %ld bytes data, waiting....", EXTERNAL_SRAM_SIZE);
start_time = rt_tick_get();
for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
{
#if EXTERNAL_SRAM_DATA_WIDTH == 8
((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
#else
((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
#endif
}
time_cast = rt_tick_get() - start_time;
LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
/* read data */
LOG_D("start Reading and verifying data, waiting....");
for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
{
#if EXTERNAL_SRAM_DATA_WIDTH == 8
data = ((__IO uint8_t *)ptr)[i];
if (data != 0x55)
{
LOG_E("External SRAM test failed!");
break;
}
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
data = ((__IO uint16_t *)ptr)[i];
if (data != 0x5555)
{
LOG_E("External SRAM test failed!");
break;
}
#else
data = ((__IO uint32_t *)ptr)[i];
if (data != 0x55555555)
{
LOG_E("External SRAM test failed!");
break;
}
#endif
}
if (i >= EXTERNAL_SRAM_SIZE / data_width)
{
LOG_D("External SRAM test success!");
}
return RT_EOK;
}
MSH_CMD_EXPORT(external_sram_test, sram test);
#endif /* FINSH_USING_MSH */
#endif /* DRV_DEBUG */
#endif /* BSP_USING_EXT_SRAM */
bsp/stm32/stm32f103-100ask-pro/board/ports/sram_port.h
+23
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@@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-01-05 linyiyang first version
* 2024-05-28 WKjay add this file to stm32f103-100ask-pro
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* stm32f1 Bank1:0x68000000 */
#define EXTERNAL_SRAM_BANK_ADDR ((uint32_t)0x68000000)
/* data width: 8, 16, 32 */
#define EXTERNAL_SRAM_DATA_WIDTH 16
/* sram size */
#define EXTERNAL_SRAM_SIZE ((uint32_t)0x100000)
#endif