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https://github.com/RT-Thread/rt-thread.git
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rm48x50: cleanup HALCoGen code
This commit is contained in:
Grissiom
@@ -1,98 +0,0 @@
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;-------------------------------------------------------------------------------
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; dabort.asm
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;
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; (c) Texas Instruments 2009-2013, All rights reserved.
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;
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.text
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.arm
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;-------------------------------------------------------------------------------
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; Run Memory Test
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.ref custom_dabort
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.def _dabort
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.asmfunc
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_dabort
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stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
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ldr r12, esmsr3 ; ESM Group3 status register
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ldr r0, [r12]
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tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
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bne ramErrorFound
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tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
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bne ramErrorFound
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noRAMerror
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tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
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bne flashErrorFound
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bl custom_dabort ; custom data abort handler required
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; If this custom handler is written in assembly, all registers used in the routine
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; and the link register must be saved on to the stack upon entry, and restored before
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; return from the routine.
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ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
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subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
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ramErrorFound
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ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
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ldr r2, [r1]
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tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
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beq ramErrorReal
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mov r2, #0x20
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str r2, [r1, #0x10] ; clear RAM error status register
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ldr r1, ram2ctrl
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str r2, [r1, #0x10] ; clear RAM error status register
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mov r2, #0x28
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str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors
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mov r2, #5
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str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
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ldmfd r13!, {r0 - r12, lr}
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subs pc, lr, #4 ; branch to instruction after the one that caused the abort
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; this is the case because the data abort was caused intentionally
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; and we do not want to cause the same data abort again.
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ramErrorReal
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b ramErrorReal ; branch here forever as continuing operation is not recommended
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flashErrorFound
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ldr r1, flashbase
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ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
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mov r2, r2, lsr #16
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tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
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beq flashErrorReal
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mov r2, #1
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mov r2, r2, lsl #8
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str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
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mov r2, #0x80
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str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
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mov r2, #5
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str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
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ldmfd r13!, {r0 - r12, lr}
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subs pc, lr, #4 ; branch to instruction after the one that caused the abort
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; this is the case because the data abort was caused intentionally
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; and we do not want to cause the same data abort again.
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flashErrorReal
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b flashErrorReal ; branch here forever as continuing operation is not recommended
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esmsr3 .word 0xFFFFF520
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ramctrl .word 0xFFFFF800
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ram2ctrl .word 0xFFFFF900
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ram1errstat .word 0xFFFFF810
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ram2errstat .word 0xFFFFF910
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flashbase .word 0xFFF87000
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.endasmfunc
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File diff suppressed because it is too large
Load Diff
@@ -1,125 +0,0 @@
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/** @file notification.c
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* @brief User Notification Definition File
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* @date 29.May.2013
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* @version 03.05.02
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*
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* This file defines empty notification routines to avoid
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* linker errors, Driver expects user to define the notification.
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* The user needs to either remove this file and use their custom
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* notification function or place their code sequence in this file
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* between the provided USER CODE BEGIN and USER CODE END.
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*
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*/
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/* Include Files */
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#include "esm.h"
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#include "sys_selftest.h"
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#include "gio.h"
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#include "sci.h"
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#include "rti.h"
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#include "sys_dma.h"
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/* USER CODE BEGIN (0) */
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#include <stdint.h>
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/* USER CODE END */
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void esmGroup1Notification(uint32 channel)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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void esmGroup2Notification(uint32 channel)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (3) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (4) */
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/* USER CODE END */
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void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (5) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (6) */
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/* USER CODE END */
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void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (7) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (8) */
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/* USER CODE END */
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void rtiNotification(uint32 notification)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (9) */
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sciSendByte(scilinREG, 'I');
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/* USER CODE END */
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}
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/* USER CODE BEGIN (10) */
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/* USER CODE END */
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void gioNotification(gioPORT_t *port, sint32 bit)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (19) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (20) */
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/* USER CODE END */
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void sciNotification(sciBASE_t *sci, uint32 flags)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (29) */
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if (sci == scilinREG && flags == SCI_RX_INT)
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{
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}
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/* USER CODE END */
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}
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/* USER CODE BEGIN (30) */
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/* USER CODE END */
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/* USER CODE BEGIN (43) */
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/* USER CODE END */
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/* USER CODE BEGIN (47) */
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/* USER CODE END */
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/* USER CODE BEGIN (50) */
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/* USER CODE END */
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/* USER CODE BEGIN (53) */
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/* USER CODE END */
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void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
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{
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/* enter user code between the USER CODE BEGIN and USER CODE END. */
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/* USER CODE BEGIN (54) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (55) */
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/* USER CODE END */
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/* USER CODE BEGIN (56) */
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/* USER CODE END */
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@@ -1,121 +0,0 @@
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/** @file pinmux.c
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* @brief PINMUX Driver Inmplmentation File
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* @date 29.May.2013
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* @version 03.05.02
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*
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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/* Include Files */
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#include "pinmux.h"
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#define PINMUX_SET(REG, BALLID, MUX) \
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pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
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#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \
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pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
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#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
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pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
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#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
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pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
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#define PINMUX_ETHERNET_SELECT(interface) \
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pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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void muxInit(void){
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/* Enable Pin Muxing */
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kickerReg->KICKER0 = 0x83E70B13U;
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kickerReg->KICKER1 = 0x95A4F1E0U;
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
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pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
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pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
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pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
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pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
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pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
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pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
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pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
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pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
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pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
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pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
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pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
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pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
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pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
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pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
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pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
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pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
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pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
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pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
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pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
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pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
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pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
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pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
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pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
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pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
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||||
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||||
pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
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||||
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||||
pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
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||||
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||||
pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
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||||
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||||
pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
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||||
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||||
pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
|
||||
|
||||
PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
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||||
PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
|
||||
PINMUX_ALT_ADC_TRIGGER_SELECT(1);
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||||
PINMUX_ETHERNET_SELECT(RMII);
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||||
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||||
/* USER CODE BEGIN (3) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Disable Pin Muxing */
|
||||
kickerReg->KICKER0 = 0x00000000U;
|
||||
kickerReg->KICKER1 = 0x00000000U;
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||||
|
||||
/* USER CODE BEGIN (4) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (5) */
|
||||
/* USER CODE END */
|
||||
@@ -764,31 +764,3 @@ void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* USER CODE BEGIN (82) */
|
||||
/* USER CODE END */
|
||||
|
||||
/** @fn void rtiCompare3Interrupt(void)
|
||||
* @brief RTI1 Compare 3 Interrupt Handler
|
||||
*
|
||||
* RTI1 Compare 3 interrupt handler
|
||||
*
|
||||
*/
|
||||
|
||||
void rtiCompare3Interrupt(void)
|
||||
{
|
||||
/* USER CODE BEGIN (83) */
|
||||
/* USER CODE END */
|
||||
|
||||
rtiREG1->INTFLAG = 8U;
|
||||
rtiNotification(rtiNOTIFICATION_COMPARE3);
|
||||
|
||||
/* USER CODE BEGIN (84) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -7,17 +7,14 @@
|
||||
.text
|
||||
.arm
|
||||
|
||||
.ref _c_int00
|
||||
|
||||
.def _reset
|
||||
.asmfunc
|
||||
_reset
|
||||
;-------------------------------------------------------------------------------
|
||||
; Initialize CPU Registers
|
||||
|
||||
.def _coreInitRegisters_
|
||||
.asmfunc
|
||||
|
||||
|
||||
_coreInitRegisters_
|
||||
|
||||
|
||||
; After reset, the CPU is in the Supervisor mode (M = 10011)
|
||||
; After reset, the CPU is in the Supervisor mode (M = 10011)
|
||||
mov r0, lr
|
||||
mov r1, #0x0000
|
||||
mov r2, #0x0000
|
||||
@@ -33,7 +30,7 @@ _coreInitRegisters_
|
||||
mov r12, #0x0000
|
||||
mov r13, #0x0000
|
||||
mrs r1, cpsr
|
||||
msr spsr_cxsf, r1
|
||||
msr spsr_cxsf, r1
|
||||
; Switch to FIQ mode (M = 10001)
|
||||
cps #17
|
||||
mov lr, r0
|
||||
@@ -43,27 +40,27 @@ _coreInitRegisters_
|
||||
mov r11, #0x0000
|
||||
mov r12, #0x0000
|
||||
mrs r1, cpsr
|
||||
msr spsr_cxsf, r1
|
||||
msr spsr_cxsf, r1
|
||||
; Switch to IRQ mode (M = 10010)
|
||||
cps #18
|
||||
mov lr, r0
|
||||
mrs r1,cpsr
|
||||
msr spsr_cxsf, r1
|
||||
msr spsr_cxsf, r1
|
||||
; Switch to Abort mode (M = 10111)
|
||||
cps #23
|
||||
mov lr, r0
|
||||
mrs r1,cpsr
|
||||
msr spsr_cxsf, r1
|
||||
msr spsr_cxsf, r1
|
||||
; Switch to Undefined Instruction Mode (M = 11011)
|
||||
cps #27
|
||||
mov lr, r0
|
||||
mrs r1,cpsr
|
||||
msr spsr_cxsf, r1
|
||||
msr spsr_cxsf, r1
|
||||
; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
|
||||
cps #31
|
||||
mov lr, r0
|
||||
mrs r1,cpsr
|
||||
msr spsr_cxsf, r1
|
||||
msr spsr_cxsf, r1
|
||||
; Switch back to Supervisor Mode (M = 10011)
|
||||
cps #19
|
||||
|
||||
@@ -94,27 +91,9 @@ _coreInitRegisters_
|
||||
fmdrr d14, r1, r1
|
||||
fmdrr d15, r1, r1
|
||||
.endif
|
||||
bl next1
|
||||
next1
|
||||
bl next2
|
||||
next2
|
||||
bl next3
|
||||
next3
|
||||
bl next4
|
||||
next4
|
||||
bx r0
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Initialize Stack Pointers
|
||||
|
||||
.def _coreInitStackPointer_
|
||||
.asmfunc
|
||||
|
||||
_coreInitStackPointer_
|
||||
|
||||
cps #17
|
||||
ldr sp, fiqSp
|
||||
cps #18
|
||||
@@ -127,8 +106,19 @@ _coreInitStackPointer_
|
||||
ldr sp, userSp
|
||||
cps #19
|
||||
ldr sp, svcSp
|
||||
bx lr
|
||||
|
||||
bl next1
|
||||
next1
|
||||
bl next2
|
||||
next2
|
||||
bl next3
|
||||
next3
|
||||
bl next4
|
||||
next4
|
||||
ldr lr, int00ad
|
||||
bx lr
|
||||
|
||||
int00ad .word _c_int00
|
||||
userSp .word 0x08000000+0x00001000
|
||||
svcSp .word 0x08000000+0x00001000+0x00000100
|
||||
fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
|
||||
@@ -138,90 +128,6 @@ undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get CPSR Value
|
||||
|
||||
.def _getCPSRValue_
|
||||
.asmfunc
|
||||
|
||||
_getCPSRValue_
|
||||
|
||||
mrs r0, CPSR
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Take CPU to IDLE state
|
||||
|
||||
.def _gotoCPUIdle_
|
||||
.asmfunc
|
||||
|
||||
_gotoCPUIdle_
|
||||
|
||||
WFI
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable VFP Unit
|
||||
|
||||
.def _coreEnableVfp_
|
||||
.asmfunc
|
||||
|
||||
_coreEnableVfp_
|
||||
|
||||
mrc p15, #0x00, r0, c1, c0, #0x02
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, #0x00, r0, c1, c0, #0x02
|
||||
mov r0, #0x40000000
|
||||
fmxr fpexc, r0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable Event Bus Export
|
||||
|
||||
.def _coreEnableEventBusExport_
|
||||
.asmfunc
|
||||
|
||||
_coreEnableEventBusExport_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0x00, r0, c9, c12, #0x00
|
||||
orr r0, r0, #0x10
|
||||
mcr p15, #0x00, r0, c9, c12, #0x00
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable Event Bus Export
|
||||
|
||||
.def _coreDisableEventBusExport_
|
||||
.asmfunc
|
||||
|
||||
_coreDisableEventBusExport_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0x00, r0, c9, c12, #0x00
|
||||
bic r0, r0, #0x10
|
||||
mcr p15, #0x00, r0, c9, c12, #0x00
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable RAM ECC Support
|
||||
|
||||
@@ -234,7 +140,7 @@ _coreEnableRamEcc_
|
||||
mrc p15, #0x00, r0, c1, c0, #0x01
|
||||
orr r0, r0, #0x0C000000
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -252,7 +158,7 @@ _coreDisableRamEcc_
|
||||
mrc p15, #0x00, r0, c1, c0, #0x01
|
||||
bic r0, r0, #0x0C000000
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -271,7 +177,7 @@ _coreEnableFlashEcc_
|
||||
orr r0, r0, #0x02000000
|
||||
dmb
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -289,30 +195,11 @@ _coreDisableFlashEcc_
|
||||
mrc p15, #0x00, r0, c1, c0, #0x01
|
||||
bic r0, r0, #0x02000000
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable Offset via Vic controller
|
||||
|
||||
.def _coreEnableIrqVicOffset_
|
||||
.asmfunc
|
||||
|
||||
_coreEnableIrqVicOffset_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #0x01000000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get data fault status register
|
||||
|
||||
@@ -338,7 +225,7 @@ _coreClearDataFault_
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -369,7 +256,7 @@ _coreClearInstructionFault_
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c0, #1
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -400,7 +287,7 @@ _coreClearDataFaultAddress_
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -431,7 +318,7 @@ _coreClearInstructionFaultAddress_
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c0, #2
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -462,7 +349,7 @@ _coreClearAuxiliaryDataFault_
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c1, #0
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
@@ -492,64 +379,11 @@ _coreClearAuxiliaryInstructionFault_
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mrc p15, #0, r0, c5, c1, #1
|
||||
ldmfd sp!, {r0}
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable interrupts - R4 IRQ & FIQ
|
||||
|
||||
.def _disable_interrupt_
|
||||
.asmfunc
|
||||
|
||||
_disable_interrupt_
|
||||
|
||||
cpsid if
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable FIQ interrupt
|
||||
|
||||
.def _disable_FIQ_interrupt_
|
||||
.asmfunc
|
||||
|
||||
_disable_FIQ_interrupt_
|
||||
|
||||
cpsid f
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable FIQ interrupt
|
||||
|
||||
.def _disable_IRQ_interrupt_
|
||||
.asmfunc
|
||||
|
||||
_disable_IRQ_interrupt_
|
||||
|
||||
cpsid i
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable interrupts - R4 IRQ & FIQ
|
||||
|
||||
.def _enable_interrupt_
|
||||
.asmfunc
|
||||
|
||||
_enable_interrupt_
|
||||
|
||||
cpsie if
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear ESM CCM errorss
|
||||
|
||||
@@ -558,7 +392,7 @@ _enable_interrupt_
|
||||
|
||||
_esmCcmErrorsClear_
|
||||
|
||||
stmfd sp!, {r0-r2}
|
||||
stmfd sp!, {r0-r2}
|
||||
ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
|
||||
ldr r2, ESMSR1_ERR_CLR
|
||||
str r2, [r0] ; clear the ESMSR1 register
|
||||
@@ -581,7 +415,7 @@ _esmCcmErrorsClear_
|
||||
ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
|
||||
ldr r2, CCMR4_ERR_CLR
|
||||
str r2, [r0] ; clear the CCMR4 status register
|
||||
ldmfd sp!, {r0-r2}
|
||||
ldmfd sp!, {r0-r2}
|
||||
bx lr
|
||||
|
||||
ESMSR1_REG .word 0xFFFFF518
|
||||
@@ -598,16 +432,16 @@ ESMSSR2_ERR_CLR .word 0x00000004
|
||||
VIM_INT_CLR .word 0x00000001
|
||||
VIM_INTREQ .word 0xFFFFFE20
|
||||
|
||||
.endasmfunc
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Work Around for Errata CORTEX-R4#57:
|
||||
;
|
||||
; Errata Description:
|
||||
;
|
||||
; Errata Description:
|
||||
; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
|
||||
; Workaround:
|
||||
; Disable out-of-order single-precision floating point
|
||||
; multiply-accumulate instruction completion
|
||||
; Disable out-of-order single-precision floating point
|
||||
; multiply-accumulate instruction completion
|
||||
|
||||
.def _errata_CORTEXR4_57_
|
||||
.asmfunc
|
||||
@@ -615,22 +449,22 @@ VIM_INTREQ .word 0xFFFFFE20
|
||||
_errata_CORTEXR4_57_
|
||||
|
||||
push {r0}
|
||||
mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
|
||||
orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
|
||||
mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
|
||||
mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
|
||||
orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
|
||||
mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
|
||||
pop {r0}
|
||||
bx lr
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Work Around for Errata CORTEX-R4#66:
|
||||
;
|
||||
; Errata Description:
|
||||
; Register Corruption During A Load-Multiple Instruction At
|
||||
;
|
||||
; Errata Description:
|
||||
; Register Corruption During A Load-Multiple Instruction At
|
||||
; an Exception Vector
|
||||
; Workaround:
|
||||
; Disable out-of-order completion for divide instructions in
|
||||
; Auxiliary Control register
|
||||
; Disable out-of-order completion for divide instructions in
|
||||
; Auxiliary Control register
|
||||
|
||||
.def _errata_CORTEXR4_66_
|
||||
.asmfunc
|
||||
@@ -639,12 +473,33 @@ _errata_CORTEXR4_66_
|
||||
|
||||
push {r0}
|
||||
mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
|
||||
orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
|
||||
orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
|
||||
; for divide instructions.)
|
||||
mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
|
||||
pop {r0}
|
||||
pop {r0}
|
||||
bx lr
|
||||
.endasmfunc
|
||||
|
||||
.def turnon_VFP
|
||||
.asmfunc
|
||||
turnon_VFP
|
||||
; Enable FPV
|
||||
STMDB sp!, {r0}
|
||||
fmrx r0, fpexc
|
||||
orr r0, r0, #0x40000000
|
||||
fmxr fpexc, r0
|
||||
LDMIA sp!, {r0}
|
||||
subs pc, lr, #4
|
||||
.endasmfunc
|
||||
|
||||
.def _dabort
|
||||
.asmfunc
|
||||
|
||||
_dabort
|
||||
stmfd r13!, {r0 - r12, lr}
|
||||
ldmfd r13!, {r0 - r12, lr}
|
||||
subs pc, lr, #8
|
||||
.endasmfunc
|
||||
;-------------------------------------------------------------------------------
|
||||
; C++ construct table pointers
|
||||
|
||||
@@ -655,6 +510,6 @@ __TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
|
||||
__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
|
||||
|
||||
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -1,322 +0,0 @@
|
||||
/** @file dma.c
|
||||
* @brief DMA Driver Inmplmentation File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
|
||||
#include "sys_dma.h"
|
||||
|
||||
|
||||
/** @fn void dmaEnable(void)
|
||||
* @brief enables DMA module
|
||||
*
|
||||
* This function brings DMA out of reset
|
||||
*/
|
||||
void dmaEnable(void)
|
||||
{
|
||||
dmaREG->GCTRL = 0x00000001U; /* reset dma */
|
||||
dmaREG->GCTRL |= 0x00010000U; /* enable dma */
|
||||
dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */
|
||||
}
|
||||
|
||||
/** @fn void dmaDisable(void)
|
||||
* @brief disables DMA module
|
||||
*
|
||||
* This function disables DMA module
|
||||
*/
|
||||
void dmaDisable(void)
|
||||
{
|
||||
/* Wait until DMA's external bus has completed data transfer */
|
||||
while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U)
|
||||
{
|
||||
} /* Wait */
|
||||
/* Disable DMA module */
|
||||
dmaREG->GCTRL = 0U;
|
||||
}
|
||||
|
||||
|
||||
/** @fn void dmaReqAssign(uint32 channel,uint32 reqline)
|
||||
* @brief Initializes the DMA Driver
|
||||
* @param[in] channel DMA channel
|
||||
* @param[in] reqline DMA request line
|
||||
*
|
||||
* This function assigns dma request lines to channels
|
||||
*/
|
||||
void dmaReqAssign(uint32 channel,uint32 reqline)
|
||||
{
|
||||
register uint32 i=0U,j=0U;
|
||||
|
||||
i = channel >> 2U; /* Find the register to configure */
|
||||
j = channel -(i<<2U); /* Find the offset of the type */
|
||||
j = 3U-j; /* reverse the byte order */
|
||||
j = j<<3U; /* find the bit location */
|
||||
|
||||
/* mapping channel 'i' to request line 'j' */
|
||||
dmaREG->DREQASI[i] &= ~(0xffU<<j);
|
||||
dmaREG->DREQASI[i] |= (reqline<<j);
|
||||
}
|
||||
|
||||
|
||||
/** @fn uint32 dmaGetReq(uint32 channel)
|
||||
* @brief Gets the request line number mapped to the selected channel
|
||||
* @param[in] channel DMA channel
|
||||
*
|
||||
* This function returns the request line number mapped to the selected channel
|
||||
*/
|
||||
uint32 dmaGetReq(uint32 channel)
|
||||
{
|
||||
register uint32 i=0U,j=0U;
|
||||
|
||||
i = channel >> 2U; /* Find the register to configure */
|
||||
j = channel -(i<<2U); /* Find the offset of the type */
|
||||
j = 3U-j; /* reverse the byte order */
|
||||
j = j<<3U; /* find the bit location */
|
||||
return ((dmaREG->DREQASI[i] >> j) &0xffU);
|
||||
}
|
||||
|
||||
|
||||
/** @fn void dmaSetCtrlPacket(uint32 channel)
|
||||
* @brief Initializes the DMA Driver
|
||||
*
|
||||
* This function sets control packet
|
||||
*/
|
||||
void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT)
|
||||
{
|
||||
register uint32 i=0U,j=0U;
|
||||
|
||||
dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD;
|
||||
|
||||
dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD;
|
||||
|
||||
dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT;
|
||||
|
||||
dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14U) | (g_dmaCTRLPKT.WRSIZE << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \
|
||||
(g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT);
|
||||
|
||||
dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);
|
||||
|
||||
dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET);
|
||||
|
||||
dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET);
|
||||
|
||||
i = channel >> 3U; /* Find the register to write */
|
||||
j = channel -(i << 3U); /* Find the offset of the 4th bit */
|
||||
j = 7U -j; /* Reverse the order of the 4th bit offset */
|
||||
j = j<<2U; /* Find the bit location of the 4th bit to write */
|
||||
|
||||
dmaREG->PAR[i] &= ~(0xfU<<j);
|
||||
dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaSetChEnable(uint32 channel,uint32 type)
|
||||
* @brief Enable channel
|
||||
* @param[in] channel DMA channel
|
||||
* @param[in] type Type of triggering
|
||||
* - DMA_HW: Enables the selected DMA channel for hardware triggering
|
||||
* - DMA_SW: Enables the selected DMA channel for software triggering
|
||||
*
|
||||
* This function enables the DMA channel for hardware or software triggering
|
||||
*/
|
||||
void dmaSetChEnable(uint32 channel,uint32 type)
|
||||
{
|
||||
if(type == DMA_HW)
|
||||
{
|
||||
dmaREG->HWCHENAS = (1U << channel);
|
||||
}
|
||||
else if(type == DMA_SW)
|
||||
{
|
||||
dmaREG->SWCHENAS = (1U << channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/** Empty */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
|
||||
* @brief Assign Priority to the channel
|
||||
* @param[in] channel DMA channel
|
||||
* @param[in] priority Priority queue to which channel needs to be assigned
|
||||
* - LOWPRIORITY : The selected channel will be assigned to low priority queue
|
||||
* - HIGHPRIORITY: The selected channel will be assigned to high priority queue
|
||||
*
|
||||
* This function assigns the selected priority to the selected channel
|
||||
*/
|
||||
void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
|
||||
{
|
||||
if (priority == LOWPRIORITY)
|
||||
{
|
||||
dmaREG->CHPRIOR |= 1U << channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
dmaREG->CHPRIOS |= 1U << channel;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
|
||||
* @brief Enable selected interrupt
|
||||
* @param[in] channel DMA channel
|
||||
* @param[in] inttype Interrupt to be enabled
|
||||
* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
|
||||
* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
|
||||
* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
|
||||
* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
|
||||
* - BER: Bus Error Interrupt will be disabled for the selected channel
|
||||
*
|
||||
* This function enables the selected interrupt for the selected channel
|
||||
*/
|
||||
void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
|
||||
{
|
||||
dmaREG->GCHIENAS = 1 << channel;
|
||||
|
||||
switch (inttype)
|
||||
{
|
||||
case FTC: dmaREG->FTCINTENAS |= 1U << channel;
|
||||
break;
|
||||
case LFS: dmaREG->LFSINTENAS |= 1U << channel;
|
||||
break;
|
||||
case HBC: dmaREG->HBCINTENAS |= 1U << channel;
|
||||
break;
|
||||
case BTC: dmaREG->BTCINTENAS |= 1U << channel;
|
||||
break;
|
||||
default :
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
|
||||
* @brief Disable selected interrupt
|
||||
* @param[in] channel DMA channel
|
||||
* @param[in] inttype Interrupt to be disabled
|
||||
* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
|
||||
* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
|
||||
* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
|
||||
* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
|
||||
* - BER: Bus Error Interrupt will be disabled for the selected channel
|
||||
*
|
||||
* This function disables the selected interrupt for the selected channel
|
||||
*/
|
||||
void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
|
||||
{
|
||||
switch (inttype)
|
||||
{
|
||||
case FTC: dmaREG->FTCINTENAR |= 1U << channel;
|
||||
break;
|
||||
case LFS: dmaREG->LFSINTENAR |= 1U << channel;
|
||||
break;
|
||||
case HBC: dmaREG->HBCINTENAR |= 1U << channel;
|
||||
break;
|
||||
case BTC: dmaREG->BTCINTENAR |= 1U << channel;
|
||||
break;
|
||||
default :
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
|
||||
* @brief Configure start and end address of the region
|
||||
* @param[in] region Memory Region
|
||||
* - DMA_REGION0
|
||||
* - DMA_REGION1
|
||||
* - DMA_REGION2
|
||||
* - DMA_REGION3
|
||||
* @param[in] start_add Start address of the the region
|
||||
* @param[in] end_add End address of the region
|
||||
*
|
||||
* This function configure start and end address of the selected region
|
||||
*/
|
||||
void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
|
||||
{
|
||||
dmaREG->DMAMPR[region].STARTADD = start_add;
|
||||
dmaREG->DMAMPR[region].ENDADD = end_add;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
|
||||
* @brief Enable the selected region
|
||||
* @param[in] region Memory Region
|
||||
* - DMA_REGION0
|
||||
* - DMA_REGION1
|
||||
* - DMA_REGION2
|
||||
* - DMA_REGION3
|
||||
* @param[in] access Access permission of the selected region
|
||||
* - FULLACCESS
|
||||
* - READONLY
|
||||
* - WRITEONLY
|
||||
* - NOACCESS
|
||||
* @param[in] intenable Interrupt to be enabled or not
|
||||
* - INTERRUPT_ENABLE : Enable interrupt for the selected region
|
||||
* - INTERRUPT_DISABLE: Disable interrupt for the selected region
|
||||
*
|
||||
* This function enables the selected region with selected access permission with or without interrupt enable
|
||||
*/
|
||||
void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
|
||||
{
|
||||
/* Enable the region */
|
||||
dmaREG->DMAMPCTRL |= 1U << (region*8U);
|
||||
/* Set access permission for the region */
|
||||
dmaREG->DMAMPCTRL |= access << ((region*8U) + 1U);
|
||||
/* Enable or Disable interrupt */
|
||||
dmaREG->DMAMPCTRL |= intenable << ((region*8U) + 3U);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaDisableRegion(dmaREGION_t region)
|
||||
* @brief Disable the selected region
|
||||
* @param[in] region Memory Region
|
||||
* - DMA_REGION0
|
||||
* - DMA_REGION1
|
||||
* - DMA_REGION2
|
||||
* - DMA_REGION3
|
||||
*
|
||||
* This function disables the selected region(no address checking done).
|
||||
*/
|
||||
void dmaDisableRegion(dmaREGION_t region)
|
||||
{
|
||||
dmaREG->DMAMPCTRL &= ~(1U << (region*8U));
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaEnableParityCheck(void)
|
||||
* @brief Enable Parity Check
|
||||
*
|
||||
* This function enables parit check
|
||||
*/
|
||||
void dmaEnableParityCheck(void)
|
||||
{
|
||||
dmaREG->DMAPCR = 0x5U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @fn void dmaDisableParityCheck(void)
|
||||
* @brief Disable Parity Check
|
||||
*
|
||||
* This function disables parity check
|
||||
*/
|
||||
void dmaDisableParityCheck(void)
|
||||
{
|
||||
dmaREG->DMAPCR = 0xAU;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -10,17 +10,18 @@
|
||||
;-------------------------------------------------------------------------------
|
||||
; import reference for interrupt routines
|
||||
|
||||
.ref _c_int00
|
||||
.ref _reset
|
||||
.ref _dabort
|
||||
.ref turnon_VFP
|
||||
.ref IRQ_Handler
|
||||
|
||||
|
||||
.def resetEntry
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; interrupt vectors
|
||||
|
||||
resetEntry
|
||||
b _c_int00
|
||||
b _reset
|
||||
b turnon_VFP
|
||||
svcEntry
|
||||
b svcEntry
|
||||
@@ -32,13 +33,4 @@ reservedEntry
|
||||
b IRQ_Handler
|
||||
ldr pc,[pc,#-0x1b0]
|
||||
|
||||
.sect ".text"
|
||||
turnon_VFP
|
||||
; Enable FPV
|
||||
STMDB sp!, {r0}
|
||||
fmrx r0, fpexc
|
||||
orr r0, r0, #0x40000000
|
||||
fmxr fpexc, r0
|
||||
LDMIA sp!, {r0}
|
||||
subs pc, lr, #4
|
||||
;-------------------------------------------------------------------------------
|
||||
|
||||
@@ -1,82 +0,0 @@
|
||||
/** @file sys_main.c
|
||||
* @brief Application main file
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains an empty main function,
|
||||
* which can be used for the application.
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* we will use our own main and get rid off everything from HALCoGen here */
|
||||
#if 0
|
||||
#include <stdint.h>
|
||||
/* USER CODE END */
|
||||
|
||||
/* Include Files */
|
||||
|
||||
#include "sys_common.h"
|
||||
#include "system.h"
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
|
||||
/* Include HET header file - types, definitions and function declarations for system driver */
|
||||
#include "het.h"
|
||||
#include "esm.h"
|
||||
#include "sci.h"
|
||||
#include "rti.h"
|
||||
|
||||
/* Task1 */
|
||||
void vTaskDelay(int t)
|
||||
{
|
||||
for (; t; t--)
|
||||
{
|
||||
int i;
|
||||
for(i = 100000;i ; i--)
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
/* USER CODE END */
|
||||
|
||||
/** @fn void main(void)
|
||||
* @brief Application main function
|
||||
* @note This function is empty by default.
|
||||
*
|
||||
* This function is called after startup.
|
||||
* The user can use this function to implement the application.
|
||||
*/
|
||||
|
||||
/* USER CODE BEGIN (2) */
|
||||
uint8_t sci_buf;
|
||||
/* USER CODE END */
|
||||
|
||||
void main(void)
|
||||
{
|
||||
/* USER CODE BEGIN (3) */
|
||||
|
||||
/* Set high end timer GIO port hetPort pin direction to all output */
|
||||
gioSetDirection(hetPORT1, 0xFFFFFFFF);
|
||||
sciInit();
|
||||
rtiInit();
|
||||
rtiStartCounter(rtiCOUNTER_BLOCK1);
|
||||
rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
|
||||
_enable_IRQ();
|
||||
sciReceive(scilinREG, 1, &sci_buf);
|
||||
|
||||
for(;;)
|
||||
{
|
||||
gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
|
||||
/* Taggle HET[1] with timer tick */
|
||||
/*sciSendByte(scilinREG, 'b');*/
|
||||
vTaskDelay(100);
|
||||
/*sciSendByte(scilinREG, 'a');*/
|
||||
}
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (4) */
|
||||
#endif
|
||||
/* USER CODE END */
|
||||
@@ -1,403 +0,0 @@
|
||||
;-------------------------------------------------------------------------------
|
||||
; sys_mpu.asm
|
||||
;
|
||||
; (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
;
|
||||
|
||||
.text
|
||||
.arm
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Initalize Mpu
|
||||
|
||||
.def _mpuInit_
|
||||
.asmfunc
|
||||
|
||||
_mpuInit_
|
||||
stmfd sp!, {r0}
|
||||
; Disable mpu
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #1
|
||||
dsb
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
isb
|
||||
; Disable background region
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #0x20000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
; Setup region 1
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r1Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x1000
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 2
|
||||
mov r0, #1
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r2Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x0600
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region
|
||||
mov r0, #2
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r3Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x0300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 4
|
||||
mov r0, #3
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r4Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x0300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 5
|
||||
mov r0, #4
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r5Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0000
|
||||
orr r0, r0, #0x0300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 6
|
||||
mov r0, #5
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r6Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0000
|
||||
orr r0, r0, #0x0300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 7
|
||||
mov r0, #6
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r7Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x1200
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 8
|
||||
mov r0, #7
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r8Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0010
|
||||
orr r0, r0, #0x1300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 9
|
||||
mov r0, #8
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r9Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0010
|
||||
orr r0, r0, #0x1300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x08 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 10
|
||||
mov r0, #9
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r10Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0010
|
||||
orr r0, r0, #0x1300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 11
|
||||
mov r0, #10
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r11Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x1100
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (0))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
; Setup region 12
|
||||
mov r0, #11
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
ldr r0, r12Base
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
mov r0, #0x0008
|
||||
orr r0, r0, #0x1300
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (0))
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
|
||||
|
||||
; Enable mpu background region
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #0x20000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
; Enable mpu
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #1
|
||||
dsb
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
isb
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
r1Base .word 0x00000000
|
||||
r2Base .word 0x00000000
|
||||
r3Base .word 0x08000000
|
||||
r4Base .word 0x08400000
|
||||
r5Base .word 0x60000000
|
||||
r6Base .word 0x80000000
|
||||
r7Base .word 0xF0000000
|
||||
r8Base .word 0xFC000000
|
||||
r9Base .word 0xFE000000
|
||||
r10Base .word 0xFF000000
|
||||
r11Base .word 0x08001000
|
||||
r12Base .word 0x20000000
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable Mpu
|
||||
|
||||
.def _mpuEnable_
|
||||
.asmfunc
|
||||
|
||||
_mpuEnable_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #1
|
||||
dsb
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
isb
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable Mpu
|
||||
|
||||
.def _mpuDisable_
|
||||
.asmfunc
|
||||
|
||||
_mpuDisable_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #1
|
||||
dsb
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
isb
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable Mpu background region
|
||||
|
||||
.def _mpuEnableBackgroundRegion_
|
||||
.asmfunc
|
||||
|
||||
_mpuEnableBackgroundRegion_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #0x20000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable Mpu background region
|
||||
|
||||
.def _mpuDisableBackgroundRegion_
|
||||
.asmfunc
|
||||
|
||||
_mpuDisableBackgroundRegion_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #0x20000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Returns number of implemented Mpu regions
|
||||
|
||||
.def _mpuGetNumberOfRegions_
|
||||
.asmfunc
|
||||
|
||||
_mpuGetNumberOfRegions_
|
||||
|
||||
mrc p15, #0, r0, c0, c0, #4
|
||||
uxtb r0, r0, ROR #8
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Returns the type of the implemented mpu regions
|
||||
|
||||
.def _mpuAreRegionsSeparate_
|
||||
.asmfunc
|
||||
|
||||
_mpuAreRegionsSeparate_
|
||||
|
||||
mrc p15, #0, r0, c0, c0, #4
|
||||
uxtb r0, r0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Set mpu region number
|
||||
|
||||
.def _mpuSetRegion_
|
||||
.asmfunc
|
||||
|
||||
_mpuSetRegion_
|
||||
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get mpu region number
|
||||
|
||||
.def _mpuGetRegion_
|
||||
.asmfunc
|
||||
|
||||
_mpuGetRegion_
|
||||
|
||||
mrc p15, #0, r0, c6, c2, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Set base address
|
||||
|
||||
.def _mpuSetRegionBaseAddress_
|
||||
.asmfunc
|
||||
|
||||
_mpuSetRegionBaseAddress_
|
||||
|
||||
mcr p15, #0, r0, c6, c1, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get base address
|
||||
|
||||
.def _mpuGetRegionBaseAddress_
|
||||
.asmfunc
|
||||
|
||||
_mpuGetRegionBaseAddress_
|
||||
|
||||
mrc p15, #0, r0, c6, c1, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Set type and permission
|
||||
|
||||
.def _mpuSetRegionTypeAndPermission_
|
||||
.asmfunc
|
||||
|
||||
_mpuSetRegionTypeAndPermission_
|
||||
|
||||
orr r0, r0, r1
|
||||
mcr p15, #0, r0, c6, c1, #4
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get type
|
||||
|
||||
.def _mpuGetRegionType_
|
||||
.asmfunc
|
||||
|
||||
_mpuGetRegionType_
|
||||
|
||||
mrc p15, #0, r0, c6, c1, #4
|
||||
bic r0, r0, #0xFF00
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get permission
|
||||
|
||||
.def _mpuGetRegionPermission_
|
||||
.asmfunc
|
||||
|
||||
_mpuGetRegionPermission_
|
||||
|
||||
mrc p15, #0, r0, c6, c1, #4
|
||||
bic r0, r0, #0xFF
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Set region size register value
|
||||
|
||||
.def _mpuSetRegionSizeRegister_
|
||||
.asmfunc
|
||||
|
||||
_mpuSetRegionSizeRegister_
|
||||
|
||||
mcr p15, #0, r0, c6, c1, #2
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,32 +0,0 @@
|
||||
/** @file sys_phantom.c
|
||||
* @brief Phantom Interrupt Source File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
* This file contains:
|
||||
* - Phantom Interrupt Handler
|
||||
*/
|
||||
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#include "sys_common.h"
|
||||
|
||||
/* USER CODE BEGIN (0) */
|
||||
/* USER CODE END */
|
||||
|
||||
/* Phantom Interrupt Handler */
|
||||
|
||||
/* USER CODE BEGIN (1) */
|
||||
/* USER CODE END */
|
||||
|
||||
#pragma CODE_STATE(phantomInterrupt, 32)
|
||||
#pragma INTERRUPT(phantomInterrupt, IRQ)
|
||||
|
||||
void phantomInterrupt(void)
|
||||
{
|
||||
/* USER CODE BEGIN (2) */
|
||||
/* USER CODE END */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN (3) */
|
||||
/* USER CODE END */
|
||||
@@ -1,348 +0,0 @@
|
||||
/** @file sys_pmm.c
|
||||
* @brief PCR Driver Implementation File
|
||||
* @date 29.May.2013
|
||||
* @version 03.05.02
|
||||
*
|
||||
*/
|
||||
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
||||
|
||||
#include "sys_pmm.h"
|
||||
|
||||
/** @fn void pmmInit(void)
|
||||
* @brief Initializes the PMM Driver
|
||||
*
|
||||
* This function initializes the PMM module.
|
||||
*/
|
||||
void pmmInit(void)
|
||||
{
|
||||
/*Disable clocks to all logic domains*/
|
||||
pmmREG->PDCLKDISREG = 0xFU;
|
||||
/*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/
|
||||
pmmREG->GLOBALCTRL1 = (0U << 8U) | (0U << 0U); /*from GUI*/
|
||||
/*Power on the logic power domains*/
|
||||
pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
|
||||
/*Power on the memory-only power domains*/
|
||||
pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
|
||||
|
||||
/*wait till Logic Power Domain PD2 turns ON*/
|
||||
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
/*wait till Logic Power Domain PD3 turns ON*/
|
||||
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
/*wait till Logic Power Domain PD4 turns OFF*/
|
||||
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
/*wait till Logic Power Domain PD5 turns ON*/
|
||||
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
|
||||
/*wait till Memory Only Power Domain RAM_PD1 turns ON*/
|
||||
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
/*wait till Memory Only Power Domain RAM_PD2 turns ON*/
|
||||
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
/*wait till Memory Only Power Domain RAM_PD3 turns ON*/
|
||||
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD3] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
|
||||
{
|
||||
/* Enable clocks for the selected logic domain */
|
||||
pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
|
||||
* @brief Turns on Logic Power Domain
|
||||
* @param[in] logicPD - Power Domain to be turned on
|
||||
* - PMM_LOGICPD2: Power domain PD2 will be turned on
|
||||
* - PMM_LOGICPD3: Power domain PD3 will be turned on
|
||||
* - PMM_LOGICPD4: Power domain PD4 will be turned on
|
||||
* - PMM_LOGICPD5: Power domain PD5 will be turned on
|
||||
*
|
||||
* This function turns on the selected Logic Power Domain
|
||||
*
|
||||
*/
|
||||
void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
|
||||
{
|
||||
if (logicPD != PMM_LOGICPD1)
|
||||
{
|
||||
/* Power on the domain */
|
||||
if (logicPD == PMM_LOGICPD2)
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
|
||||
}
|
||||
else if (logicPD == PMM_LOGICPD3)
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
|
||||
}
|
||||
else if (logicPD == PMM_LOGICPD4)
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0x5U << 0U);
|
||||
}
|
||||
/* Wait until the power domain turns on */
|
||||
while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
|
||||
{
|
||||
/* Enable clocks to the power domain */
|
||||
pmmREG->PDCLKDISCLRREG = 1U << (uint32)logicPD;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
|
||||
* @brief Turns on Memory Power Domain
|
||||
* @param[in] memPD - Power Domain to be tured on
|
||||
* - PMM_MEMPD1: Power domain RAM_PD1 will be turned on
|
||||
* - PMM_MEMPD2: Power domain RAM_PD2 will be turned on
|
||||
* - PMM_MEMPD3: Power domain RAM_PD3 will be turned on
|
||||
*
|
||||
* This function turns on the selected Memory Power Domain
|
||||
*
|
||||
*/
|
||||
void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
|
||||
{
|
||||
/* Power on the domain */
|
||||
if (memPD == PMM_MEMPD1)
|
||||
{
|
||||
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
|
||||
}
|
||||
else if (memPD == PMM_MEMPD2)
|
||||
{
|
||||
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
|
||||
}
|
||||
/*Wait until the power domain turns on*/
|
||||
while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
}
|
||||
|
||||
/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
|
||||
* @brief Turns off Logic Power Domain
|
||||
* @param[in] logicPD - Power Domain to be tured off
|
||||
* - PMM_LOGICPD2: Power domain PD2 will be turned off
|
||||
* - PMM_LOGICPD3: Power domain PD3 will be turned off
|
||||
* - PMM_LOGICPD4: Power domain PD4 will be turned off
|
||||
* - PMM_LOGICPD5: Power doamin PD5 will be turned off
|
||||
*
|
||||
* This function turns off the selected Logic Power Domain
|
||||
*
|
||||
*/
|
||||
void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
|
||||
{
|
||||
if (logicPD != PMM_LOGICPD1)
|
||||
{
|
||||
/* Disable all clocks to the power domain */
|
||||
pmmREG->PDCLKDISSETREG = 1U << (uint32)logicPD;
|
||||
|
||||
/* Power down the domain */
|
||||
if (logicPD == PMM_LOGICPD2)
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
|
||||
}
|
||||
else if (logicPD == PMM_LOGICPD3)
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
|
||||
}
|
||||
else if (logicPD == PMM_LOGICPD4)
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0xAU << 0U);
|
||||
}
|
||||
/* Wait until the power domain turns off */
|
||||
while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
}
|
||||
}
|
||||
|
||||
/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
|
||||
* @brief Turns off Memory Power Domain
|
||||
* @param[in] memPD - Power Domain to be tured off
|
||||
* - PMM_MEMPD1: Power domain RAM_PD1 will be turned off
|
||||
* - PMM_MEMPD2: Power domain RAM_PD2 will be turned off
|
||||
* - PMM_MEMPD3: Power domain RAM_PD3 will be turned off
|
||||
*
|
||||
* This function turns off the selected Memory Power Domain
|
||||
*
|
||||
*/
|
||||
void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
|
||||
{
|
||||
/* Power down the domain */
|
||||
if (memPD == PMM_MEMPD1)
|
||||
{
|
||||
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
|
||||
}
|
||||
else if (memPD == PMM_MEMPD2)
|
||||
{
|
||||
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
|
||||
}
|
||||
/*Wait until the power domain turns off*/
|
||||
while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U)
|
||||
{
|
||||
}/* Wait */
|
||||
}
|
||||
|
||||
/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
|
||||
* @brief Check if the power domain is active or not
|
||||
* @param[in] logicPD - Power Domain to be be checked
|
||||
* - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not
|
||||
* - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not
|
||||
* - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not
|
||||
* - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not
|
||||
* @return The function will return:
|
||||
* - TRUE : When the selected power domain is in Active state.
|
||||
* - FALSE: When the selected power domain is in OFF state.
|
||||
*
|
||||
* This function checks whether the selected power domain is active or not.
|
||||
*
|
||||
*/
|
||||
boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
|
||||
{
|
||||
boolean status;
|
||||
if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
status = FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = TRUE;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
|
||||
* @brief Check if the power domain is active or not
|
||||
* @param[in] memPD - Power Domain to be tured off
|
||||
* - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not
|
||||
* - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not
|
||||
* - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not
|
||||
* @return The function will return:
|
||||
* - TRUE : When the selected power domain is in Active state.
|
||||
* - FALSE: When the selected power domain is in OFF state.
|
||||
*
|
||||
* This function checks whether the selected power domain is active or not.
|
||||
*
|
||||
*/
|
||||
boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
|
||||
{
|
||||
boolean status;
|
||||
if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
|
||||
{
|
||||
status = FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = TRUE;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
|
||||
* @brief Get the initial or current values of the configuration register
|
||||
* @param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored
|
||||
* @param[in] type - whether initial or current value of the configuration registers need to be stored
|
||||
* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
|
||||
* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
|
||||
* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
|
||||
*/
|
||||
void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
|
||||
{
|
||||
if (type == InitialValue)
|
||||
{
|
||||
config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
|
||||
config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
|
||||
config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
|
||||
config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0;
|
||||
config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0;
|
||||
config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG;
|
||||
config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1;
|
||||
}
|
||||
}
|
||||
|
||||
/** @fn void pmmSetMode(pmm_Mode_t mode)
|
||||
* @brief Set PSCON Compare Block Mode
|
||||
* @param[in] mode - PSCON Compare Block mode
|
||||
* - LockStep : PSCON compare block is set to Lock-Step mode
|
||||
* - SelfTest : PSCON compare block is set to Self-Test mode
|
||||
* - ErrorForcing : PSCON compare block is set to Error-Forcing mode
|
||||
* - SelfTestErrorForcing : PSCON compare block is set to Self-Test-Error-Forcing mode
|
||||
*
|
||||
* This function sets the PSCON Compare block to the selected mode
|
||||
*
|
||||
*/
|
||||
void pmmSetMode(pmm_Mode_t mode)
|
||||
{
|
||||
/* Set PSCON Compare Block Mode */
|
||||
pmmREG->PRCKEYREG = mode;
|
||||
}
|
||||
|
||||
/** @fn boolean pmmPerformSelfTest(void)
|
||||
* @brief Perform self test and return the result
|
||||
*
|
||||
* @return The function will return
|
||||
* - TRUE if PSCON compare block passed self-test
|
||||
* - FALSE if PSCON compare block failed in self-test
|
||||
*
|
||||
* This function checks whether PSCON compare block passed the self-test or not.
|
||||
*
|
||||
*/
|
||||
boolean pmmPerformSelfTest(void)
|
||||
{
|
||||
boolean status = TRUE;
|
||||
/*Enter self-test mode*/
|
||||
pmmREG->PRCKEYREG = SelfTest;
|
||||
/*Wait till self test is completed*/
|
||||
while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU)
|
||||
{
|
||||
}/* Wait */
|
||||
|
||||
while ((pmmREG->MPDDCSTAT1 & 0x7U) != 0x7U)
|
||||
{
|
||||
}/* Wait */
|
||||
|
||||
/*Check whether self-test passed or not*/
|
||||
if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U)
|
||||
{
|
||||
status = FALSE;
|
||||
}
|
||||
if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U)
|
||||
{
|
||||
status = FALSE;
|
||||
}
|
||||
/*Enter lock-step mode*/
|
||||
pmmREG->PRCKEYREG = LockStep;
|
||||
|
||||
return status;
|
||||
}
|
||||
@@ -1,223 +0,0 @@
|
||||
;-------------------------------------------------------------------------------
|
||||
; sys_pmu.asm
|
||||
;
|
||||
; (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
;
|
||||
|
||||
.text
|
||||
.arm
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Initialize Pmu
|
||||
; Note: It will reset all counters
|
||||
|
||||
.def _pmuInit_
|
||||
.asmfunc
|
||||
|
||||
_pmuInit_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
; set control register
|
||||
mrc p15, #0, r0, c9, c12, #0
|
||||
orr r0, r0, #(1 << 4) + 6 + 1
|
||||
mcr p15, #0, r0, c9, c12, #0
|
||||
; clear flags
|
||||
mov r0, #0
|
||||
sub r1, r1, #1
|
||||
mcr p15, #0, r0, c9, c12, #3
|
||||
; select counter 0 event
|
||||
mcr p15, #0, r0, c9, c12, #5 ; select counter
|
||||
mov r0, #0x11
|
||||
mcr p15, #0, r0, c9, c13, #1 ; select event
|
||||
; select counter 1 event
|
||||
mov r0, #1
|
||||
mcr p15, #0, r0, c9, c12, #5 ; select counter
|
||||
mov r0, #0x11
|
||||
mcr p15, #0, r0, c9, c13, #1 ; select event
|
||||
; select counter 2 event
|
||||
mov r0, #2
|
||||
mcr p15, #0, r0, c9, c12, #5 ; select counter
|
||||
mov r0, #0x11
|
||||
mcr p15, #0, r0, c9, c13, #1 ; select event
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Enable Counters Global [Cycle, Event [0..2]]
|
||||
; Note: It will reset all counters
|
||||
|
||||
.def _pmuEnableCountersGlobal_
|
||||
.asmfunc
|
||||
|
||||
_pmuEnableCountersGlobal_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c9, c12, #0
|
||||
orr r0, r0, #7
|
||||
mcr p15, #0, r0, c9, c12, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Disable Counters Global [Cycle, Event [0..2]]
|
||||
|
||||
.def _pmuDisableCountersGlobal_
|
||||
.asmfunc
|
||||
|
||||
_pmuDisableCountersGlobal_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c9, c12, #0
|
||||
bic r0, r0, #1
|
||||
mcr p15, #0, r0, c9, c12, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Reset Cycle Counter
|
||||
|
||||
.def _pmuResetCycleCounter_
|
||||
.asmfunc
|
||||
|
||||
_pmuResetCycleCounter_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c9, c12, #0
|
||||
orr r0, r0, #4
|
||||
mcr p15, #0, r0, c9, c12, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Reset Event Counters [0..2]
|
||||
|
||||
.def _pmuResetEventCounters_
|
||||
.asmfunc
|
||||
|
||||
_pmuResetEventCounters_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c9, c12, #0
|
||||
orr r0, r0, #2
|
||||
mcr p15, #0, r0, c9, c12, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Reset Cycle Counter abd Event Counters [0..2]
|
||||
|
||||
.def _pmuResetCounters_
|
||||
.asmfunc
|
||||
|
||||
_pmuResetCounters_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0, r0, c9, c12, #0
|
||||
orr r0, r0, #6
|
||||
mcr p15, #0, r0, c9, c12, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Start Counters [Cycle, 0..2]
|
||||
|
||||
.def _pmuStartCounters_
|
||||
.asmfunc
|
||||
|
||||
_pmuStartCounters_
|
||||
|
||||
mcr p15, #0, r0, c9, c12, #1
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Stop Counters [Cycle, 0..2]
|
||||
|
||||
.def _pmuStopCounters_
|
||||
.asmfunc
|
||||
|
||||
_pmuStopCounters_
|
||||
|
||||
mcr p15, #0, r0, c9, c12, #2
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Set Count event
|
||||
|
||||
.def _pmuSetCountEvent_
|
||||
.asmfunc
|
||||
|
||||
_pmuSetCountEvent_
|
||||
|
||||
lsr r0, r0, #1
|
||||
mcr p15, #0, r0, c9, c12, #5 ; select counter
|
||||
mcr p15, #0, r1, c9, c13, #1 ; select event
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get Cycle Count
|
||||
|
||||
.def _pmuGetCycleCount_
|
||||
.asmfunc
|
||||
|
||||
_pmuGetCycleCount_
|
||||
|
||||
mrc p15, #0, r0, c9, c13, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get Event Counter Count Value
|
||||
|
||||
.def _pmuGetEventCount_
|
||||
.asmfunc
|
||||
|
||||
_pmuGetEventCount_
|
||||
|
||||
lsr r0, r0, #1
|
||||
mcr p15, #0, r0, c9, c12, #5 ; select counter
|
||||
mrc p15, #0, r0, c9, c13, #2 ; read event counter
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get Overflow Flags
|
||||
|
||||
.def _pmuGetOverflow_
|
||||
.asmfunc
|
||||
|
||||
_pmuGetOverflow_
|
||||
|
||||
mrc p15, #0, r0, c9, c12, #3 ; read overflow
|
||||
mov r1, #0
|
||||
sub r1, r1, #1
|
||||
mcr p15, #0, r1, c9, c12, #3 ; clear flags
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -30,140 +30,6 @@ typedef volatile struct vimRam
|
||||
|
||||
#define vimRAM ((vimRAM_t *)0xFFF82000U)
|
||||
|
||||
static const t_isrFuncPTR s_vim_init[129] =
|
||||
{
|
||||
&phantomInterrupt,
|
||||
&esmHighInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&rtiCompare3Interrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&linHighLevelInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
&phantomInterrupt,
|
||||
};
|
||||
void vimParityErrorHandler(void);
|
||||
|
||||
/** @fn void vimInit(void)
|
||||
* @brief Initializes VIM module
|
||||
*
|
||||
@@ -172,18 +38,8 @@ void vimParityErrorHandler(void);
|
||||
|
||||
void vimInit(void)
|
||||
{
|
||||
/* Initialize VIM table */
|
||||
{
|
||||
uint32 i;
|
||||
|
||||
for (i = 0U; i < (VIM_CHANNELS + 1U); i++)
|
||||
{
|
||||
vimRAM->ISR[i] = s_vim_init[i];
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Fall-Back Address Parity Error Register */
|
||||
VIM_FBPARERR = (uint32)&vimParityErrorHandler;
|
||||
/*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/
|
||||
|
||||
/* set IRQ/FIQ priorities */
|
||||
vimREG->FIRQPR0 = SYS_FIQ
|
||||
@@ -627,6 +483,7 @@ void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
#pragma CODE_STATE(vimParityErrorHandler, 32)
|
||||
#pragma INTERRUPT(vimParityErrorHandler, IRQ)
|
||||
|
||||
@@ -674,3 +531,4 @@ void vimParityErrorHandler(void)
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -282,7 +282,7 @@ void systemInit(void)
|
||||
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
|
||||
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
|
||||
*/
|
||||
efcCheck();
|
||||
//efcCheck();
|
||||
|
||||
/* USER CODE BEGIN (17) */
|
||||
/* USER CODE END */
|
||||
@@ -294,17 +294,18 @@ void systemInit(void)
|
||||
/* USER CODE END */
|
||||
|
||||
/* Configure device-level multiplexing and I/O multiplexing */
|
||||
muxInit();
|
||||
//muxInit();
|
||||
|
||||
/* USER CODE BEGIN (19) */
|
||||
/* USER CODE END */
|
||||
|
||||
#if 0
|
||||
/* Wait for eFuse controller self-test to complete and check results */
|
||||
if ((!checkefcSelfTest()) !=0U) /* eFuse controller ECC logic self-test failed */
|
||||
{
|
||||
efcClass2Error(); /* device operation is not reliable */
|
||||
}
|
||||
|
||||
#endif
|
||||
/* USER CODE BEGIN (20) */
|
||||
/* USER CODE END */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user