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rm48x50: cleanup HALCoGen code

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This commit is contained in:
Grissiom committed 2013-10-20 04:04:59 +08:00
1 parent 6bcf1bc48b
commit 2f4329430d
19 files changed
+146 -6515
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bsp/rm48x50/HALCoGen/source/dabort.asm
-98
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@@ -1,98 +0,0 @@
;-------------------------------------------------------------------------------
; dabort.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Run Memory Test
.ref custom_dabort
.def _dabort
.asmfunc
_dabort
stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
ldr r12, esmsr3 ; ESM Group3 status register
ldr r0, [r12]
tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
bne ramErrorFound
tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
bne ramErrorFound
noRAMerror
tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
bne flashErrorFound
bl custom_dabort ; custom data abort handler required
; If this custom handler is written in assembly, all registers used in the routine
; and the link register must be saved on to the stack upon entry, and restored before
; return from the routine.
ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
ramErrorFound
ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
ldr r2, [r1]
tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
beq ramErrorReal
mov r2, #0x20
str r2, [r1, #0x10] ; clear RAM error status register
ldr r1, ram2ctrl
str r2, [r1, #0x10] ; clear RAM error status register
mov r2, #0x28
str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors
mov r2, #5
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
ldmfd r13!, {r0 - r12, lr}
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
; this is the case because the data abort was caused intentionally
; and we do not want to cause the same data abort again.
ramErrorReal
b ramErrorReal ; branch here forever as continuing operation is not recommended
flashErrorFound
ldr r1, flashbase
ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
mov r2, r2, lsr #16
tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
beq flashErrorReal
mov r2, #1
mov r2, r2, lsl #8
str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
mov r2, #0x80
str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
mov r2, #5
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
ldmfd r13!, {r0 - r12, lr}
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
; this is the case because the data abort was caused intentionally
; and we do not want to cause the same data abort again.
flashErrorReal
b flashErrorReal ; branch here forever as continuing operation is not recommended
esmsr3 .word 0xFFFFF520
ramctrl .word 0xFFFFF800
ram2ctrl .word 0xFFFFF900
ram1errstat .word 0xFFFFF810
ram2errstat .word 0xFFFFF910
flashbase .word 0xFFF87000
.endasmfunc
bsp/rm48x50/HALCoGen/source/esm.c
-713
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bsp/rm48x50/HALCoGen/source/notification.c
-125
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@@ -1,125 +0,0 @@
/** @file notification.c
* @brief User Notification Definition File
* @date 29.May.2013
* @version 03.05.02
*
* This file defines empty notification routines to avoid
* linker errors, Driver expects user to define the notification.
* The user needs to either remove this file and use their custom
* notification function or place their code sequence in this file
* between the provided USER CODE BEGIN and USER CODE END.
*
*/
/* Include Files */
#include "esm.h"
#include "sys_selftest.h"
#include "gio.h"
#include "sci.h"
#include "rti.h"
#include "sys_dma.h"
/* USER CODE BEGIN (0) */
#include <stdint.h>
/* USER CODE END */
void esmGroup1Notification(uint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (1) */
/* USER CODE END */
}
/* USER CODE BEGIN (2) */
/* USER CODE END */
void esmGroup2Notification(uint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (3) */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (5) */
/* USER CODE END */
}
/* USER CODE BEGIN (6) */
/* USER CODE END */
void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (7) */
/* USER CODE END */
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
void rtiNotification(uint32 notification)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (9) */
sciSendByte(scilinREG, 'I');
/* USER CODE END */
}
/* USER CODE BEGIN (10) */
/* USER CODE END */
void gioNotification(gioPORT_t *port, sint32 bit)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
/* USER CODE BEGIN (20) */
/* USER CODE END */
void sciNotification(sciBASE_t *sci, uint32 flags)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (29) */
if (sci == scilinREG && flags == SCI_RX_INT)
{
}
/* USER CODE END */
}
/* USER CODE BEGIN (30) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* USER CODE BEGIN (47) */
/* USER CODE END */
/* USER CODE BEGIN (50) */
/* USER CODE END */
/* USER CODE BEGIN (53) */
/* USER CODE END */
void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (54) */
/* USER CODE END */
}
/* USER CODE BEGIN (55) */
/* USER CODE END */
/* USER CODE BEGIN (56) */
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/pinmux.c
-121
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@@ -1,121 +0,0 @@
/** @file pinmux.c
* @brief PINMUX Driver Inmplmentation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* Include Files */
#include "pinmux.h"
#define PINMUX_SET(REG, BALLID, MUX) \
pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
#define PINMUX_ETHERNET_SELECT(interface) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
/* USER CODE BEGIN (0) */
/* USER CODE END */
void muxInit(void){
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Enable Pin Muxing */
kickerReg->KICKER0 = 0x83E70B13U;
kickerReg->KICKER1 = 0x95A4F1E0U;
/* USER CODE BEGIN (2) */
/* USER CODE END */
pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
PINMUX_ALT_ADC_TRIGGER_SELECT(1);
PINMUX_ETHERNET_SELECT(RMII);
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Disable Pin Muxing */
kickerReg->KICKER0 = 0x00000000U;
kickerReg->KICKER1 = 0x00000000U;
/* USER CODE BEGIN (4) */
/* USER CODE END */
}
/* USER CODE BEGIN (5) */
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/rti.c
-28
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@@ -764,31 +764,3 @@ void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
}
}
/* USER CODE BEGIN (82) */
/* USER CODE END */
/** @fn void rtiCompare3Interrupt(void)
* @brief RTI1 Compare 3 Interrupt Handler
*
* RTI1 Compare 3 interrupt handler
*
*/
void rtiCompare3Interrupt(void)
{
/* USER CODE BEGIN (83) */
/* USER CODE END */
rtiREG1->INTFLAG = 8U;
rtiNotification(rtiNOTIFICATION_COMPARE3);
/* USER CODE BEGIN (84) */
/* USER CODE END */
}
bsp/rm48x50/HALCoGen/source/sci.c
-549
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bsp/rm48x50/HALCoGen/source/sys_core.asm
+73 -218
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bsp/rm48x50/HALCoGen/source/sys_dma.c
-322
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bsp/rm48x50/HALCoGen/source/sys_intvecs.asm
+4 -12
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@@ -10,17 +10,18 @@
;-------------------------------------------------------------------------------
; import reference for interrupt routines
.ref _c_int00
.ref _reset
.ref _dabort
.ref turnon_VFP
.ref IRQ_Handler
.def resetEntry
;-------------------------------------------------------------------------------
; interrupt vectors
resetEntry
b _c_int00
b _reset
b turnon_VFP
svcEntry
b svcEntry
@@ -32,13 +33,4 @@ reservedEntry
b IRQ_Handler
ldr pc,[pc,#-0x1b0]
.sect ".text"
turnon_VFP
; Enable FPV
STMDB sp!, {r0}
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
LDMIA sp!, {r0}
subs pc, lr, #4
;-------------------------------------------------------------------------------
bsp/rm48x50/HALCoGen/source/sys_main.c
-82
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@@ -1,82 +0,0 @@
/** @file sys_main.c
* @brief Application main file
* @date 29.May.2013
* @version 03.05.02
*
* This file contains an empty main function,
* which can be used for the application.
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* USER CODE BEGIN (0) */
/* we will use our own main and get rid off everything from HALCoGen here */
#if 0
#include <stdint.h>
/* USER CODE END */
/* Include Files */
#include "sys_common.h"
#include "system.h"
/* USER CODE BEGIN (1) */
/* Include HET header file - types, definitions and function declarations for system driver */
#include "het.h"
#include "esm.h"
#include "sci.h"
#include "rti.h"
/* Task1 */
void vTaskDelay(int t)
{
for (; t; t--)
{
int i;
for(i = 100000;i ; i--)
{
}
}
}
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
uint8_t sci_buf;
/* USER CODE END */
void main(void)
{
/* USER CODE BEGIN (3) */
/* Set high end timer GIO port hetPort pin direction to all output */
gioSetDirection(hetPORT1, 0xFFFFFFFF);
sciInit();
rtiInit();
rtiStartCounter(rtiCOUNTER_BLOCK1);
rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
_enable_IRQ();
sciReceive(scilinREG, 1, &sci_buf);
for(;;)
{
gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
/* Taggle HET[1] with timer tick */
/*sciSendByte(scilinREG, 'b');*/
vTaskDelay(100);
/*sciSendByte(scilinREG, 'a');*/
}
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
#endif
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/sys_mpu.asm
-403
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bsp/rm48x50/HALCoGen/source/sys_pcr.c
-602
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bsp/rm48x50/HALCoGen/source/sys_phantom.c
-32
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@@ -1,32 +0,0 @@
/** @file sys_phantom.c
* @brief Phantom Interrupt Source File
* @date 29.May.2013
* @version 03.05.02
*
* This file contains:
* - Phantom Interrupt Handler
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Phantom Interrupt Handler */
/* USER CODE BEGIN (1) */
/* USER CODE END */
#pragma CODE_STATE(phantomInterrupt, 32)
#pragma INTERRUPT(phantomInterrupt, IRQ)
void phantomInterrupt(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
}
/* USER CODE BEGIN (3) */
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/sys_pmm.c
-348
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bsp/rm48x50/HALCoGen/source/sys_pmu.asm
-223
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bsp/rm48x50/HALCoGen/source/sys_selftest.c
-2178
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bsp/rm48x50/HALCoGen/source/sys_startup.c
+62 -313
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bsp/rm48x50/HALCoGen/source/sys_vim.c
+3 -145
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@@ -30,140 +30,6 @@ typedef volatile struct vimRam
#define vimRAM ((vimRAM_t *)0xFFF82000U)
static const t_isrFuncPTR s_vim_init[129] =
{
&phantomInterrupt,
&esmHighInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&rtiCompare3Interrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&linHighLevelInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
};
void vimParityErrorHandler(void);
/** @fn void vimInit(void)
* @brief Initializes VIM module
*
@@ -172,18 +38,8 @@ void vimParityErrorHandler(void);
void vimInit(void)
{
/* Initialize VIM table */
{
uint32 i;
for (i = 0U; i < (VIM_CHANNELS + 1U); i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
/* Set Fall-Back Address Parity Error Register */
VIM_FBPARERR = (uint32)&vimParityErrorHandler;
/*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/
/* set IRQ/FIQ priorities */
vimREG->FIRQPR0 = SYS_FIQ
@@ -627,6 +483,7 @@ void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
}
#if 0
#pragma CODE_STATE(vimParityErrorHandler, 32)
#pragma INTERRUPT(vimParityErrorHandler, IRQ)
@@ -674,3 +531,4 @@ void vimParityErrorHandler(void)
}
}
}
#endif
bsp/rm48x50/HALCoGen/source/system.c
+4 -3
View File
@@ -282,7 +282,7 @@ void systemInit(void)
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efcCheck();
//efcCheck();
/* USER CODE BEGIN (17) */
/* USER CODE END */
@@ -294,17 +294,18 @@ void systemInit(void)
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
//muxInit();
/* USER CODE BEGIN (19) */
/* USER CODE END */
#if 0
/* Wait for eFuse controller self-test to complete and check results */
if ((!checkefcSelfTest()) !=0U) /* eFuse controller ECC logic self-test failed */
{
efcClass2Error(); /* device operation is not reliable */
}
#endif
/* USER CODE BEGIN (20) */
/* USER CODE END */