[bsp][lpc55sxx] add support of LPC5528/LPC55S28 (#6667)

* [bsp][lpc55sxx] add support of LPC5528/LPC55S28

1. add .ignore_format
2. add support of LPC55S28
3. fix LPC55S69 keil comiple error
3. refine README

* [bsp][lpc55sxx]

1. remove cmake file
2. formating code using rt-thread formating tools
3. CMSIS folder -> ../

* [bsp][lpc55s69]

 - add IAR support(IAR version: 9.30.1)

bsp/lpc55sxx/Libraries/.ignore_format.yml

@@ -0,0 +1,8 @@
+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- LPC55S6X
+- LPC55S06
+- LPC5502
+- LPC55S28
+- LPC55S36

bsp/lpc55sxx/Libraries/Kconfig

@@ -1,9 +1,4 @@
-config SOC_LPC55S6X_SERIES
-    bool
-    select ARCH_ARM_CORTEX_M33
-    select ARCH_ARM_CORTEX_FPU
-    
-config SOC_LPC55S66_SERIES
+config SOC_LPC55S28_SERIES
     bool
     select ARCH_ARM_CORTEX_M33
     select ARCH_ARM_CORTEX_FPU

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_flash.scf

@@ -0,0 +1,83 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S28JBD100_cm33_core0
+**                          LPC55S28JBD64_cm33_core0
+**                          LPC55S28JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x00000000
+#define  m_interrupts_size             0x00000200
+
+#define m_text_start                   0x00000200
+#define m_text_size                    0x0007FDFF
+
+#define  m_data_start                  0x20000000
+#define  m_data_size                   0x00030000
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_ram.scf

@@ -0,0 +1,83 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S28JBD100_cm33_core0
+**                          LPC55S28JBD64_cm33_core0
+**                          LPC55S28JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x04000000
+#define  m_interrupts_size             0x00000200
+
+#define m_text_start                   0x04000200
+#define m_text_size                    0x00007DFF
+
+#define  m_data_start                  0x20000000
+#define  m_data_size                   0x00030000
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55xx.dbgconf

@@ -0,0 +1,18 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <o0> SWO pin
+// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
+// <i> for an external debug tool to evaluate.
+//      <0=> PIO0_10
+//      <1=> PIO0_8
+SWO_Pin = 0;
+// 
+
+// <h>Debug Configuration
+//   <o.0>    StopAfterBootloader       <i> Stop after Bootloader
+// </h>
+Dbg_CR = 0x00000001;
+//
+
+
+// <<< end of configuration section >>>

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_cmp.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cmp.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cmp_1"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmpReg = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(kCLOCK_Comp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
+    /* Reset the CMP module. */
+    RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn);
+#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */
+
+    tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK |
+                            PMC_COMP_FILTERCGF_SAMPLEMODE_MASK));
+
+    if (true == config->enableLowPower)
+    {
+        tmpReg |= PMC_COMP_LOWPOWER_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_LOWPOWER_MASK;
+    }
+
+    if (true == config->enableHysteresis)
+    {
+        tmpReg |= PMC_COMP_HYST_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_HYST_MASK;
+    }
+
+    tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) |
+               PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode));
+
+    PMC->COMP = tmpReg;
+}
+
+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
+void CMP_Deinit(void)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(kCLOCK_Comp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableHysteresis   = true;
+    config->enableLowPower     = true;
+    config->filterClockDivider = kCMP_FilterClockDivide1;
+    config->filterSampleMode   = kCMP_FilterSampleMode0;
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config)
+{
+    assert(NULL != config);
+    assert(config->vrefValue < 32U);
+
+    uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK);
+
+    tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue);
+
+    PMC->COMP = tmpReg;
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc((size_t)alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
+#endif

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.c

@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2019-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_crc"
+#endif
+
+#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
+/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
+#define CRC_DRIVER_DEFAULT_REVERSE_IN false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
+/*< Default is without complement of written data */
+#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Enables and configures the CRC peripheral module.
+ *
+ * This functions enables the CRC peripheral clock in the LPC SYSCON block.
+ * It also configures the CRC engine and starts checksum computation by writing the seed.
+ *
+ * param base   CRC peripheral address.
+ * param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to CRC */
+    CLOCK_EnableClock(kCLOCK_Crc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET)
+    RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn);
+#endif
+
+    /* configure CRC module and write the seed */
+    base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
+                 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
+                 CRC_MODE_CMPL_SUM(config->complementOut);
+    base->SEED = config->seed;
+}
+
+/*!
+ * brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * code
+ *   config->polynomial = kCRC_Polynomial_CRC_CCITT;
+ *   config->reverseIn = false;
+ *   config->complementIn = false;
+ *   config->reverseOut = false;
+ *   config->complementOut = false;
+ *   config->seed = 0xFFFFU;
+ * endcode
+ *
+ * param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
+
+    *config = default_config;
+}
+
+/*!
+ * brief resets CRC peripheral module.
+ *
+ * param base   CRC peripheral address.
+ */
+void CRC_Reset(CRC_Type *base)
+{
+    crc_config_t config;
+    CRC_GetDefaultConfig(&config);
+    CRC_Init(base, &config);
+}
+
+/*!
+ * brief Write seed (initial checksum) to CRC peripheral module.
+ *
+ * param base   CRC peripheral address.
+ * param seed   CRC Seed value.
+ */
+void CRC_WriteSeed(CRC_Type *base, uint32_t seed)
+{
+    /*  write the seed (initial checksum) */
+    base->SEED = seed;
+}
+
+/*!
+ * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
+ *
+ * The values, including seed, can be used to resume CRC calculation later.
+
+ * param base   CRC peripheral address.
+ * param config CRC protocol configuration structure
+ */
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
+{
+    /* extract CRC mode settings */
+    uint32_t mode = base->MODE;
+    config->polynomial =
+        (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT);
+    config->reverseIn     = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
+    config->complementIn  = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
+    config->reverseOut    = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
+    config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
+
+    /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
+    base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
+
+    /* now we can obtain intermediate raw CRC sum value */
+    config->seed = base->SUM;
+
+    /* restore original CRC sum bit reverse and 1's complement setting */
+    base->MODE = mode;
+}
+
+/*!
+ * brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ *
+ * param base     CRC peripheral address.
+ * param data     Input data stream, MSByte in data[0].
+ * param dataSize Size of the input data buffer in bytes.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)(uint32_t)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        *((__O uint32_t *)&(base->WR_DATA)) = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (0U != dataSize)
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2019-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.1.1.
+ *
+ * Current version: 2.1.1
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ * - Version 2.0.1
+ *   - add explicit type cast when writing to WR_DATA
+ * - Version 2.0.2
+ *   - Fix MISRA issue
+ * - Version 2.1.0
+ *   - Add CRC_WriteSeed function
+ * - Version 2.1.1
+ *   - Fix MISRA issue
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
+#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC polynomials to use. */
+typedef enum _crc_polynomial
+{
+    kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
+    kCRC_Polynomial_CRC_16    = 1U, /*!< x^16+x^15+x^2+1 */
+    kCRC_Polynomial_CRC_32    = 2U  /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
+} crc_polynomial_t;
+
+/*!
+ * @brief CRC protocol configuration.
+ *
+ * This structure holds the configuration for the CRC protocol.
+ *
+ */
+typedef struct _crc_config
+{
+    crc_polynomial_t polynomial; /*!< CRC polynomial. */
+    bool reverseIn;              /*!< Reverse bits on input. */
+    bool complementIn;           /*!< Perform 1's complement on input. */
+    bool reverseOut;             /*!< Reverse bits on output. */
+    bool complementOut;          /*!< Perform 1's complement on output. */
+    uint32_t seed;               /*!< Starting checksum value. */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This functions enables the CRC peripheral clock in the LPC SYSCON block.
+ * It also configures the CRC engine and starts checksum computation by writing the seed.
+ *
+ * @param base   CRC peripheral address.
+ * @param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This functions disables the CRC peripheral clock in the LPC SYSCON block.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* disable clock to CRC */
+    CLOCK_DisableClock(kCLOCK_Crc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief resets CRC peripheral module.
+ *
+ * @param base   CRC peripheral address.
+ */
+void CRC_Reset(CRC_Type *base);
+
+/*!
+ * @brief Write seed to CRC peripheral module.
+ *
+ * @param base   CRC peripheral address.
+ * @param seed   CRC Seed value.
+ */
+void CRC_WriteSeed(CRC_Type *base, uint32_t seed);
+
+/*!
+ * @brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * @code
+ *   config->polynomial = kCRC_Polynomial_CRC_CCITT;
+ *   config->reverseIn = false;
+ *   config->complementIn = false;
+ *   config->reverseOut = false;
+ *   config->complementOut = false;
+ *   config->seed = 0xFFFFU;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
+ *
+ * The values, including seed, can be used to resume CRC calculation later.
+
+ * @param base   CRC peripheral address.
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ *
+ * @param base     CRC peripheral address.
+ * @param data     Input data stream, MSByte in data[0].
+ * @param dataSize Size of the input data buffer in bytes.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads 32-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 32-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->SUM;
+}
+
+/*!
+ * @brief Reads 16-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 16-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    return (uint16_t)base->SUM;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_fro_calib.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FRO_CALIB_H_
+#define _FSL_FRO_CALIB_H_
+
+#include "fsl_common.h"
+#include "fsl_device_registers.h"
+#include <stdint.h>
+
+/*!
+ * @addtogroup power
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FRO_CALIB driver version 1.0.0. */
+#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.fro_calib"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Returns the version of the FRO Calibration library */
+unsigned int fro_calib_Get_Lib_Ver(void);
+
+/* ctimer instance */
+/* ctimer clock frquency in KHz */
+void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq);
+
+/* USB_SOF_Event */
+/* Application software should be written to make sure the USB_SOF_EVENT() is */
+/* being called with lower interrupt latency for calibration to work properly */
+void USB_SOF_Event(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _FSL_FRO_CALIB_H_ */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_I2C_DMA_H_
+#define _FSL_I2C_DMA_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup i2c_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C DMA driver version. */
+#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+/*@}*/
+
+/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
+#define I2C_MAX_DMA_TRANSFER_COUNT 1024
+
+/*! @brief I2C master dma handle typedef. */
+typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
+
+/*! @brief I2C master dma transfer callback typedef. */
+typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
+                                                   i2c_master_dma_handle_t *handle,
+                                                   status_t status,
+                                                   void *userData);
+
+/*! @brief Typedef for master dma handler. */
+typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/*! @brief I2C master dma transfer structure. */
+struct _i2c_master_dma_handle
+{
+    uint8_t state;              /*!< Transfer state machine current state. */
+    uint32_t transferCount;     /*!< Indicates progress of the transfer */
+    uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
+    uint8_t *buf;               /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    bool checkAddrNack;             /*!< Whether to check the nack signal is detected during addressing. */
+    dma_handle_t *dmaHandle;        /*!< The DMA handler used. */
+    i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
+    i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
+    void *userData;                                        /*!< Callback parameter passed to callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Block DMA Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Init the I2C handle which is used in transactional functions
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param callback pointer to user callback function
+ * @param userData user param passed to the callback function
+ * @param dmaHandle DMA handle pointer
+ */
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Performs a master dma non-blocking transfer on the I2C bus
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param xfer pointer to transfer structure of i2c_master_transfer_t
+ * @retval kStatus_Success Sucessully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ */
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get master transfer status during a dma non-blocking transfer
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a master dma non-blocking transfer in a early time
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ */
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+#endif /*_FSL_I2C_DMA_H_*/

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_skboot_authenticate.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_
+#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup skboot_authenticate
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief SKBOOT return status*/
+typedef enum _skboot_status
+{
+    kStatus_SKBOOT_Success               = 0x5ac3c35au, /*!< SKBOOT return success status.*/
+    kStatus_SKBOOT_Fail                  = 0xc35ac35au, /*!< SKBOOT return fail status.*/
+    kStatus_SKBOOT_InvalidArgument       = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/
+    kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/
+    kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess =
+        0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/
+    kStatus_SKBOOT_HashcryptFinishedWithStatusFail =
+        0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/
+} skboot_status_t;
+
+/*! @brief Secure bool flag*/
+typedef enum _secure_bool
+{
+    kSECURE_TRUE                       = 0xc33cc33cU, /*!< Secure true flag.*/
+    kSECURE_FALSE                      = 0x5aa55aa5U, /*!< Secure false flag.*/
+    kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/
+    kSECURE_CALLPROTECT_IS_APP_READY   = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/
+    kSECURE_TRACKER_VERIFIED           = 0x55aacc33U, /*!< Secure tracker verified flag.*/
+} secure_bool_t;
+
+/*******************************************************************************
+ * Externs
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Authenticate entry function with ARENA allocator init
+ *
+ * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface
+ */
+skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified);
+
+/*!
+ * @brief Interface for image authentication API
+ */
+void HASH_IRQHandler(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.c

@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_inputmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.inputmux"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ *
+ * retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
+    CLOCK_EnableClock(kCLOCK_Sct);
+    CLOCK_EnableClock(kCLOCK_Dma);
+#else
+    CLOCK_EnableClock(kCLOCK_InputMux);
+#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ * param index Destination peripheral to attach the signal to.
+ * param connection Selects connection.
+ *
+ * retval None.
+ */
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
+{
+    uint32_t pmux_id;
+    uint32_t output_id;
+
+    /* extract pmux to be used */
+    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
+    /*  extract function number */
+    output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U);
+    /* programm signal */
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id;
+}
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
+/*!
+ * brief Enable/disable a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ * param signal Enable signal register id and bit offset.
+ * param enable Selects enable or disable.
+ *
+ * retval None.
+ */
+void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
+{
+    uint32_t ena_id;
+    uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U;
+    uint32_t bit_offset;
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX
+    uint32_t chmux_offset;
+    uint32_t chmux_value;
+
+    /* Only enable need to update channel mux */
+    if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U))
+    {
+        chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL);
+        chmux_value  = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL);
+        *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value;
+    }
+    ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U;
+#endif
+    /* extract enable register to be used */
+    ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask;
+    /* extract enable bit offset */
+    bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U);
+    /* set signal */
+    if (enable)
+    {
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset);
+    }
+    else
+    {
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset);
+    }
+}
+#endif
+
+/*!
+ * brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ *
+ * retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
+    CLOCK_DisableClock(kCLOCK_Sct);
+    CLOCK_DisableClock(kCLOCK_Dma);
+#else
+    CLOCK_DisableClock(kCLOCK_InputMux);
+#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_INPUTMUX_H_
+#define _FSL_INPUTMUX_H_
+
+#include "fsl_inputmux_connections.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_inputmux_connections.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group interrupt driver version for SDK */
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base);
+
+/*!
+ * @brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param index Destination peripheral to attach the signal to.
+ * @param connection Selects connection.
+ *
+ * @retval None.
+ */
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
+/*!
+ * @brief Enable/disable a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param signal Enable signal register id and bit offset.
+ * @param enable Selects enable or disable.
+ *
+ * @retval None.
+ */
+void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable);
+#endif
+
+/*!
+ * @brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_H_ */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.c

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_mrt.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mrt"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Multi-Rate timer peripheral base address
+ *
+ * @return The MRT instance
+ */
+static uint32_t MRT_GetInstance(MRT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to MRT bases for each instance. */
+static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to MRT clocks for each instance. */
+static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+#if defined(MRT_RSTS_N)
+/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */
+static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N;
+#elif defined(MRT_RSTS)
+/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */
+static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t MRT_GetInstance(MRT_Type *base)
+{
+    uint32_t instance;
+    uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < mrtArrayCount; instance++)
+    {
+        if (s_mrtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < mrtArrayCount);
+
+    return instance;
+}
+
+/*!
+ * brief Ungates the MRT clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the MRT driver.
+ *
+ * param base   Multi-Rate timer peripheral base address
+ * param config Pointer to user's MRT config structure. If MRT has  MULTITASK bit field in
+ *               MODCFG reigster, param config is useless.
+ */
+void MRT_Init(MRT_Type *base, const mrt_config_t *config)
+{
+    assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate the MRT clock */
+    CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+#if defined(MRT_RSTS_N) || defined(MRT_RSTS)
+    /* Reset the module. */
+    RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
+
+#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
+    /* Set timer operating mode */
+    base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
+#endif
+}
+
+/*!
+ * brief Gate the MRT clock
+ *
+ * param base Multi-Rate timer peripheral base address
+ */
+void MRT_Deinit(MRT_Type *base)
+{
+    /* Stop all the timers */
+    MRT_StopTimer(base, kMRT_Channel_0);
+    MRT_StopTimer(base, kMRT_Channel_1);
+#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U)
+    MRT_StopTimer(base, kMRT_Channel_2);
+#endif
+#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U)
+    MRT_StopTimer(base, kMRT_Channel_3);
+#endif
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the MRT clock*/
+    CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Used to update the timer period in units of count.
+ *
+ * The new value will be immediately loaded or will be loaded at the end of the current time
+ * interval. For one-shot interrupt mode the new value will be immediately loaded.
+ *
+ * note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * param base          Multi-Rate timer peripheral base address
+ * param channel       Timer channel number
+ * param count         Timer period in units of ticks
+ * param immediateLoad true: Load the new value immediately into the TIMER register;
+ *                      false: Load the new value at the end of current timer interval
+ */
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
+{
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+
+    uint32_t newValue = count;
+    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad))
+    {
+        /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
+        newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
+    }
+
+    /* Update the timer interval value */
+    base->CHANNEL[channel].INTVAL = newValue;
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright  2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_plu.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.plu"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base PLU peripheral base address
+ *
+ * @return The PLU instance
+ */
+static uint32_t PLU_GetInstance(PLU_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to PLU bases for each instance. */
+static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to PLU clocks for each instance. */
+static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+/*! @brief Pointers to PLU resets for each instance. */
+static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N;
+#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t PLU_GetInstance(PLU_Type *base)
+{
+    uint32_t instance;
+    uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < pluArrayCount; instance++)
+    {
+        if (s_pluBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < pluArrayCount);
+
+    return instance;
+}
+
+/*!
+ * brief Ungates the PLU clock and reset the module.
+ *
+ * note This API should be called at the beginning of the application using the PLU driver.
+ *
+ * param base PLU peripheral base address
+ */
+void PLU_Init(PLU_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the PLU peripheral clock */
+    CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+    /* Reset the module. */
+    RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
+}
+
+/*!
+ * brief Gate the PLU clock
+ *
+ * param base PLU peripheral base address
+ */
+void PLU_Deinit(PLU_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the module clock */
+    CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)]));
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG
+/*!
+ * @brief Gets an available pre-defined settings for wakeup/interrupt control.
+ *
+ * This function initializes the initial configuration structure with an available settings. The default values are:
+ * @code
+ *   config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS;
+ *   config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC;
+ * @endcode
+ * @param config Pointer to configuration structure.
+ */
+void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->filterMode  = kPLU_WAKEINT_FILTER_MODE_BYPASS;
+    config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC;
+}
+
+/*!
+ * @brief Enable PLU outputs wakeup/interrupt request.
+ *
+ * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt
+ * request.
+ *
+ * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN
+ * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint
+ * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the
+ * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may
+ * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is
+ * generated.
+ *
+ * @param base PLU peripheral base address.
+ * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration).
+ * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration)
+ */
+void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config)
+{
+    uint32_t tmp32 = 0U;
+
+    tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) |
+            PLU_WAKEINT_CTRL_MASK(interruptMask);
+
+    base->WAKEINT_CTRL = tmp32;
+}
+
+/*!
+ * @brief Clear the latched interrupt
+ *
+ * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt()
+ *
+ * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit.
+ *
+ * @param base PLU peripheral base address.
+ */
+void PLU_ClearLatchedInterrupt(PLU_Type *base)
+{
+    base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK;
+    /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */
+    while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK))
+    {
+    }
+}
+#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos   = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask  = 1UL << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* reset register is in SYSCON */
+    /* set bit */
+    SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+    /* wait until it reads 0b1 */
+    while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask))
+    {
+    }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos   = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask  = 1UL << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* reset register is in SYSCON */
+
+    /* clear bit */
+    SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+    /* wait until it reads 0b0 */
+    while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask))
+    {
+    }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.h

@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017, 2019, 2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RNG_DRIVER_H_
+#define _FSL_RNG_DRIVER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rng
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief RNG driver version. Version 2.0.3.
+ *
+ * Current version: 2.0.3
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version
+ *
+ * - Version 2.0.1
+ *   - Fix MISRA C-2012 issue.
+ *
+ * - Version 2.0.2
+ *   - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions.
+ *
+ * - Version 2.0.3
+ *   - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions.
+ *   - These changes are reflecting recommended usage of RNG according to device UM.
+ */
+#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the RNG.
+ *
+ * This function initializes the RNG.
+ * When called, the RNG module and ring oscillator is enabled.
+ *
+ * @param base  RNG base address
+ * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error.
+ */
+void RNG_Init(RNG_Type *base);
+
+/*!
+ * @brief Shuts down the RNG.
+ *
+ * This function shuts down the RNG.
+ *
+ * @param base  RNG base address.
+ */
+void RNG_Deinit(RNG_Type *base);
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function gets random data from the RNG.
+ *
+ * @param base  RNG base address.
+ * @param data  Pointer address used to store random data.
+ * @param dataSize  Size of the buffer pointed by the data parameter.
+ * @return random data
+ */
+status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize);
+
+/*!
+ * @brief Returns random 32-bit number.
+ *
+ * This function gets random number from the RNG.
+ *
+ * @param base  RNG base address.
+ * @return random number
+ */
+static inline uint32_t RNG_GetRandomWord(RNG_Type *base)
+{
+    return base->RANDOM_NUMBER;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /*_FSL_RNG_H_*/

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.h

@@ -0,0 +1,186 @@
+/*
+ * Copyright  2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_SYSCTL_H_
+#define _FSL_SYSCTL_H_
+
+#include "fsl_common.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup sysctl
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_sysctl.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group sysctl driver version for SDK */
+#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */
+/*@}*/
+
+/*! @brief SYSCTL share set*/
+enum _sysctl_share_set_index
+{
+    kSYSCTL_ShareSet0 = 0, /*!< share set 0 */
+    kSYSCTL_ShareSet1 = 1, /*!< share set 1 */
+};
+
+/*! @brief SYSCTL flexcomm signal */
+typedef enum _sysctl_fcctrlsel_signal
+{
+    kSYSCTL_FlexcommSignalSCK     = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT,   /*!< SCK signal */
+    kSYSCTL_FlexcommSignalWS      = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT,    /*!< WS signal */
+    kSYSCTL_FlexcommSignalDataIn  = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT,  /*!< Data in signal */
+    kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */
+} sysctl_fcctrlsel_signal_t;
+
+/*! @brief SYSCTL flexcomm index*/
+enum _sysctl_share_src
+{
+    kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */
+    kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */
+    kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */
+    kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */
+    kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */
+    kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */
+    kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */
+};
+
+/*! @brief SYSCTL shared data out mask */
+enum _sysctl_dataout_mask
+{
+    kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */
+    kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */
+    kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */
+    kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */
+    kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */
+    kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */
+    kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */
+};
+
+/*! @brief SYSCTL flexcomm signal */
+typedef enum _sysctl_sharedctrlset_signal
+{
+    kSYSCTL_SharedCtrlSignalSCK     = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT,  /*!< SCK signal */
+    kSYSCTL_SharedCtrlSignalWS      = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT,   /*!< WS signal */
+    kSYSCTL_SharedCtrlSignalDataIn  = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */
+    kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT,  /*!< Data out signal */
+} sysctl_sharedctrlset_signal_t;
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief SYSCTL initial
+ *
+ * @param base Base address of the SYSCTL peripheral.
+ */
+void SYSCTL_Init(SYSCTL_Type *base);
+
+/*!
+ * @brief SYSCTL deinit
+ *
+ * @param base Base address of the SYSCTL peripheral.
+ */
+void SYSCTL_Deinit(SYSCTL_Type *base);
+
+/* @} */
+
+/*!
+ * @name SYSCTL share signal configure
+ * @{
+ */
+
+/*!
+ * @brief SYSCTL share set configure for flexcomm
+ *
+ * @param base Base address of the SYSCTL peripheral.
+ * @param flexCommIndex index of flexcomm, reference _sysctl_share_src
+ * @param sckSet share set for sck,reference _sysctl_share_set_index
+ * @param wsSet share set for ws, reference _sysctl_share_set_index
+ * @param dataInSet share set for data in, reference _sysctl_share_set_index
+ * @param dataOutSet share set for data out, reference _sysctl_dataout_mask
+ *
+ */
+void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base,
+                                uint32_t flexCommIndex,
+                                uint32_t sckSet,
+                                uint32_t wsSet,
+                                uint32_t dataInSet,
+                                uint32_t dataOutSet);
+
+/*!
+ * @brief SYSCTL share set configure for separate signal
+ *
+ * @param base Base address of the SYSCTL peripheral
+ * @param flexCommIndex index of flexcomm,reference _sysctl_share_src
+ * @param signal FCCTRLSEL signal shift
+ * @param set share set for sck, reference _sysctl_share_set_index
+ *
+ */
+void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set);
+
+/*!
+ * @brief SYSCTL share set source configure
+ *
+ * @param base Base address of the SYSCTL peripheral
+ * @param setIndex index of share set, reference _sysctl_share_set_index
+ * @param sckShareSrc sck source for this share set,reference _sysctl_share_src
+ * @param wsShareSrc ws source for this share set,reference _sysctl_share_src
+ * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src
+ * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask
+ *
+ */
+void SYSCTL_SetShareSetSrc(SYSCTL_Type *base,
+                           uint32_t setIndex,
+                           uint32_t sckShareSrc,
+                           uint32_t wsShareSrc,
+                           uint32_t dataInShareSrc,
+                           uint32_t dataOutShareSrc);
+
+/*!
+ * @brief SYSCTL sck source configure
+ *
+ * @param base Base address of the SYSCTL peripheral
+ * @param setIndex index of share set, reference _sysctl_share_set_index
+ * @param signal FCCTRLSEL signal shift
+ * @param shareSrc sck source fro this share set,reference _sysctl_share_src
+ *
+ */
+void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base,
+                              uint32_t setIndex,
+                              sysctl_sharedctrlset_signal_t signal,
+                              uint32_t shareSrc);
+
+/* @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_SYSCTL_H_ */