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[bsp][lpc55sxx] add support of LPC5528/LPC55S28 (#6667)

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* [bsp][lpc55sxx] add support of LPC5528/LPC55S28

1. add .ignore_format
2. add support of LPC55S28
3. fix LPC55S69 keil comiple error
3. refine README

* [bsp][lpc55sxx]

1. remove cmake file
2. formating code using rt-thread formating tools
3. CMSIS folder -> ../

* [bsp][lpc55s69]

 - add IAR support(IAR version: 9.30.1)
This commit is contained in:
杨熙
2022-11-30 08:56:50 +08:00
committed by GitHub
parent 2f0f426375
commit 2bbbd4b3fd
212 changed files with 180741 additions and 23741 deletions
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8
bsp/lpc55sxx/Libraries/.ignore_format.yml Normal file
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# files format check exclude path, please follow the instructions below to modify;
dir_path:
- LPC55S6X
- LPC55S06
- LPC5502
- LPC55S28
- LPC55S36

0
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armcc.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armcc.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang.h
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0
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang_ltm.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_compiler.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_gcc.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_gcc.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_iccarm.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_version.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_version.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/core_cm33.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/core_cm33.h
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0
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/mpu_armv8.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/mpu_armv8.h
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0
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/tz_context.h → bsp/lpc55sxx/Libraries/CMSIS/Core/Include/tz_context.h
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bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/LICENSE.txt → bsp/lpc55sxx/Libraries/CMSIS/LICENSE.txt
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bsp/lpc55sxx/Libraries/Kconfig
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config SOC_LPC55S6X_SERIES
bool
select ARCH_ARM_CORTEX_M33
select ARCH_ARM_CORTEX_FPU
config SOC_LPC55S66_SERIES
config SOC_LPC55S28_SERIES
bool
select ARCH_ARM_CORTEX_M33
select ARCH_ARM_CORTEX_FPU

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bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.h Normal file
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bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.xml Normal file
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bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28_features.h Normal file
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/*
** ###################################################################
** Version: rev. 1.1, 2019-05-16
** Build: b220303
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
** - rev. 1.1 (2019-05-16)
** Initial A1 version based on v1.3UM
**
** ###################################################################
*/
#ifndef _LPC55S28_FEATURES_H_
#define _LPC55S28_FEATURES_H_
/* SOC module features */
/* @brief CASPER availability on the SoC. */
#define FSL_FEATURE_SOC_CASPER_COUNT (1)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (2)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (2)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
/* @brief SECGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
/* @brief HASHCRYPT availability on the SoC. */
#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (8)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (8)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
/* @brief LPADC availability on the SoC. */
#define FSL_FEATURE_SOC_LPADC_COUNT (1)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (1)
/* @brief OSTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (1)
/* @brief SECPINT availability on the SoC. */
#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (1)
/* @brief PUF availability on the SoC. */
#define FSL_FEATURE_SOC_PUF_COUNT (1)
/* @brief LPC_RNG1 availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (1)
/* @brief SDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SDIF_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (9)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief SYSCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (8)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (1)
/* @brief USBFSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
/* @brief USBHSD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
/* @brief USBHSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
/* @brief UTICK availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* LPADC module features */
/* @brief FIFO availability on the SoC. */
#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
/* @brief Has calibration (bitfield CFG[CALOFS]). */
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
/* @brief Has offset trim (register OFSTRIM). */
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
/* @brief Has Trigger status register. */
#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
/* @brief Has power select (bitfield CFG[PWRSEL]). */
#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
/* @brief Conversion averaged bitfiled width. */
#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
/* @brief Has internal temperature sensor. */
#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
/* @brief Temperature sensor parameter A (slope). */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
/* @brief Temperature sensor parameter B (offset). */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
/* @brief Temperature sensor parameter Alpha. */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
/* @brief the buffer size of temperature sensor. */
#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
/* ANALOGCTRL module features */
/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
/* @brief Has auxiliary bias(register AUX_BIAS). */
#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
/* CASPER module features */
/* @brief Base address of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
/* @brief SW interleaving of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
/* @brief CASPER dedicated RAM offset */
#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
/* CTIMER module features */
/* @brief CTIMER has no capture channel. */
#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
/* @brief CTIMER has no capture 2 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
/* @brief CTIMER capture 3 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
/* @brief Align size of DMA descriptor */
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
/* @brief DMA head link descriptor table align size */
#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
/* FLEXCOMM module features */
/* @brief FLEXCOMM0 USART INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
/* @brief FLEXCOMM0 SPI INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
/* @brief FLEXCOMM0 I2C INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
/* @brief FLEXCOMM0 I2S INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
/* @brief FLEXCOMM1 USART INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
/* @brief FLEXCOMM1 SPI INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
/* @brief FLEXCOMM1 I2C INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
/* @brief FLEXCOMM1 I2S INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
/* @brief FLEXCOMM2 USART INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
/* @brief FLEXCOMM2 SPI INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
/* @brief FLEXCOMM2 I2C INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
/* @brief FLEXCOMM2 I2S INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
/* @brief FLEXCOMM3 USART INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
/* @brief FLEXCOMM3 SPI INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
/* @brief FLEXCOMM3 I2C INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
/* @brief FLEXCOMM3 I2S INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
/* @brief FLEXCOMM4 USART INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
/* @brief FLEXCOMM4 SPI INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
/* @brief FLEXCOMM4 I2C INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
/* @brief FLEXCOMM4 I2S INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
/* @brief FLEXCOMM5 USART INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
/* @brief FLEXCOMM5 SPI INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
/* @brief FLEXCOMM5 I2C INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
/* @brief FLEXCOMM5 I2S INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
/* @brief FLEXCOMM6 USART INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
/* @brief FLEXCOMM6 SPI INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
/* @brief FLEXCOMM6 I2C INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
/* @brief FLEXCOMM6 I2S INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
/* @brief FLEXCOMM7 USART INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
/* @brief FLEXCOMM7 SPI INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
/* @brief FLEXCOMM7 I2C INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
/* @brief FLEXCOMM7 I2S INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
/* HASHCRYPT module features */
/* @brief the address of alias offset */
#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
/* I2S module features */
/* @brief I2S support dual channel transfer. */
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
/* IOCON module features */
/* @brief Func bit field width */
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
/* MRT module features */
/* @brief number of channels. */
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
/* PLU module features */
/* @brief Has WAKEINT_CTRL register. */
#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
/* PMC module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* @brief WDT OSC does not support PD configure. */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
/* POWERLIB module features */
/* @brief Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_EXTEND (1)
/* PUF module features */
/* @brief Number of PUF key slots available on device. */
#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
/* @brief the shift status value */
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
/* RTC module features */
/* No feature definitions */
/* SCT module features */
/* @brief Number of events */
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
/* @brief Number of states */
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
/* @brief Number of match capture */
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
/* @brief Number of outputs */
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
/* SDIF module features */
/* @brief FIFO depth, every location is a WORD */
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
/* @brief Max DMA buffer size */
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
/* @brief Max source clock in HZ */
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
/* @brief support 2 cards */
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
/* SECPINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
/* SYSCON module features */
/* @brief Flash page size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
/* @brief Flash sector size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
/* @brief Has Power Down mode */
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* @brief Starter register discontinuous. */
#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
/* SYSCTL1 module features */
/* No feature definitions */
/* USB module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USB_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USB version */
#define FSL_FEATURE_USB_VERSION (200)
/* @brief Number of the endpoint in USB FS */
#define FSL_FEATURE_USB_EP_NUM (5)
/* USBFSH module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBFSH version */
#define FSL_FEATURE_USBFSH_VERSION (200)
/* USBHSD module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSD version */
#define FSL_FEATURE_USBHSD_VERSION (300)
/* @brief Number of the endpoint in USB HS */
#define FSL_FEATURE_USBHSD_EP_NUM (6)
/* USBHSH module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSH version */
#define FSL_FEATURE_USBHSH_VERSION (300)
/* USBPHY module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSD version */
#define FSL_FEATURE_USBPHY_VERSION (300)
/* @brief Number of the endpoint in USB HS */
#define FSL_FEATURE_USBPHY_EP_NUM (6)
/* WWDT module features */
/* @brief Has no RESET register. */
#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
/* @brief WWDT does not support oscillator lock. */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
#endif /* _LPC55S28_FEATURES_H_ */

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#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
/*
** ###################################################################
** Processors: LPC55S28JBD100_cm33_core0
** LPC55S28JBD64_cm33_core0
** LPC55S28JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b200722
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* USB BDT size */
#define usb_bdt_size 0x0
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x00000200
#define m_text_size 0x0007FDFF
#define m_data_start 0x20000000
#define m_data_size 0x00030000
#define m_usb_sram_start 0x40100000
#define m_usb_sram_size 0x00004000
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}

83
bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_ram.scf Normal file
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#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
/*
** ###################################################################
** Processors: LPC55S28JBD100_cm33_core0
** LPC55S28JBD64_cm33_core0
** LPC55S28JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b200722
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* USB BDT size */
#define usb_bdt_size 0x0
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#define m_interrupts_start 0x04000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x04000200
#define m_text_size 0x00007DFF
#define m_data_start 0x20000000
#define m_data_size 0x00030000
#define m_usb_sram_start 0x40100000
#define m_usb_sram_size 0x00004000
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}

BIN
bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55XX_512.FLM Normal file
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18
bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55xx.dbgconf Normal file
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// <<< Use Configuration Wizard in Context Menu >>>
// <o0> SWO pin
// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
// <i> for an external debug tool to evaluate.
// <0=> PIO0_10
// <1=> PIO0_8
SWO_Pin = 0;
//
// <h>Debug Configuration
// <o.0> StopAfterBootloader <i> Stop after Bootloader
// </h>
Dbg_CR = 0x00000001;
//
// <<< end of configuration section >>>

801
bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/startup_LPC55S28.S Normal file
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251
bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.c Normal file
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/*
* Copyright 2018-2021, NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_anactrl.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.anactrl"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for ANACTRL module.
*
* @param base ANACTRL peripheral base address
*/
static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to ANACTRL bases for each instance. */
static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to ANACTRL clocks for each instance. */
static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Get the ANACTRL instance from peripheral base address.
*
* param base ANACTRL peripheral base address.
* return ANACTRL instance.
*/
static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++)
{
if (s_anactrlBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_anactrlBases));
return instance;
}
/*!
* brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
*
* param base ANACTRL peripheral base address.
*/
void ANACTRL_Init(ANACTRL_Type *base)
{
assert(NULL != base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock for ANACTRL instance. */
CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
*
* param base ANACTRL peripheral base address.
*/
void ANACTRL_Deinit(ANACTRL_Type *base)
{
assert(NULL != base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock for ANACTRL instance. */
CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output
* and enable/disable 96MHZ clock output.
*
* param base ANACTRL peripheral base address.
* param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
*/
void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = base->FRO192M_CTRL;
tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK);
if (config->enable12MHzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
}
if (config->enable96MHzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
}
base->FRO192M_CTRL |= tmp32;
}
/*!
* brief Gets the default configuration of FRO192M.
* The default values are:
* code
config->enable12MHzClk = true;
config->enable96MHzClk = false;
endcode
* param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
*/
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->enable12MHzClk = true;
config->enable96MHzClk = false;
}
/*!
* brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
* system, and so on.
*
* param base ANACTRL peripheral base address.
* param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
*/
void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = base->XO32M_CTRL;
tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK);
/* Set XO32M CTRL. */
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
if (config->enablePllUsbOutput)
{
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
}
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
if (config->enableACBufferBypass)
{
tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
}
if (config->enableSysCLkOutput)
{
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
}
base->XO32M_CTRL = tmp32;
#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
if (config->enableADCOutput)
{
base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
}
else
{
base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
}
#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
}
/*!
* brief Gets the default configuration of XO32M.
* The default values are:
* code
config->enableSysCLkOutput = false;
config->enableACBufferBypass = false;
endcode
* param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
*/
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
config->enablePllUsbOutput = false;
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
config->enableSysCLkOutput = false;
config->enableACBufferBypass = false;
#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
config->enableADCOutput = true;
#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
}
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
/*!
* brief Measures the frequency of the target clock source.
*
* This function measures target frequency according to a accurate reference frequency.The formula is:
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
*
* note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET register
* in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
*
* param base ANACTRL peripheral base address.
* param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
* param refClkFreq frequency of the reference clock.
*
* return frequency of the target clock.
*/
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
{
assert(scale >= 2U);
uint32_t targetClkFreq = 0U;
uint32_t capval = 0U;
/* Init a measurement cycle. */
base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale);
while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK))
{
}
/* Calculate the target clock frequency. */
capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL);
return targetClkFreq;
}
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */

377
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/*
* Copyright 2018-2021, NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_ANACTRL_H__
#define __FSL_ANACTRL_H__
#include "fsl_common.h"
/*!
* @addtogroup anactrl
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief ANACTRL driver version. */
#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */`
/*!
* @brief ANACTRL interrupt flags
*/
enum _anactrl_interrupt_flags
{
#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status
before Interrupt Enable. */
kANACTRL_BodVDDMainInterruptFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status
after Interrupt Enable. */
kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN
power status output. */
#else
kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before
Interrupt Enable. */
kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status
after Interrupt Enable. */
kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power
status output. */
#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before
Interrupt Enable. */
kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status
after Interrupt Enable. */
kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power
status output. */
kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before
Interrupt Enable. */
kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after
Interrupt Enable. */
kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power
status output. */
};
/*!
* @brief ANACTRL interrupt control
*/
enum _anactrl_interrupt
{
#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN
interrupt control. */
#else
kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt
control. */
#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt
control. */
kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */
};
/*!
* @brief ANACTRL status flags
*/
enum _anactrl_flags
{
kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */
kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization
error status. */
};
/*!
* @brief ANACTRL FRO192M and XO32M status flags
*/
enum _anactrl_osc_flags
{
kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */
kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector
output (signal vcco_ok). */
kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out
frequency statibilty. */
};
/*!
* @brief Configuration for FRO192M
*
* This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize
* this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a
* pointer to your config structure instance.
*/
typedef struct _anactrl_fro192M_config
{
bool enable12MHzClk; /*!< Enable 12MHz clock. */
bool enable96MHzClk; /*!< Enable 96MHz clock. */
} anactrl_fro192M_config_t;
/*!
* @brief Configuration for XO32M
*
* This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this
* structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a
* pointer to your config structure instance.
*/
typedef struct _anactrl_xo32M_config
{
bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */
#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
} anactrl_xo32M_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
*
* @param base ANACTRL peripheral base address.
*/
void ANACTRL_Init(ANACTRL_Type *base);
/*!
* @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
*
* @param base ANACTRL peripheral base address.
*/
void ANACTRL_Deinit(ANACTRL_Type *base);
/* @} */
/*!
* @name Set oscillators
* @{
*/
/*!
* @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock
* output and enable/disable 96MHZ clock output.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
*/
void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config);
/*!
* @brief Gets the default configuration of FRO192M.
* The default values are:
* @code
config->enable12MHzClk = true;
config->enable96MHzClk = false;
@endcode
* @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
*/
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config);
/*!
* @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
* system, and so on.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
*/
void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config);
/*!
* @brief Gets the default configuration of XO32M.
* The default values are:
* @code
config->enableSysCLkOutput = false;
config->enableACBufferBypass = false;
@endcode
* @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
*/
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config);
/* @} */
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
/*!
* @name Measure Frequency
* @{
*/
/*!
* @brief Measures the frequency of the target clock source.
*
* This function measures target frequency according to a accurate reference frequency.The formula is:
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
*
* @note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET
* register in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
*
* @param base ANACTRL peripheral base address.
* @param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
* @param refClkFreq frequency of the reference clock.
*
* @return frequency of the target clock.
*/
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq);
/* @} */
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */
/*!
* @name Interrupt Interface
* @{
*/
/*!
* @brief Enables the ANACTRL interrupts.
*
* @param base ANACTRL peripheral base address.
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
*/
static inline void ANACTRL_EnableInterrupts(ANACTRL_Type *base, uint32_t mask)
{
base->BOD_DCDC_INT_CTRL |= (0x15U & mask);
}
/*!
* @brief Disables the ANACTRL interrupts.
*
* @param base ANACTRL peripheral base address.
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
*/
static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask)
{
base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask);
}
/*!
* @brief Clears the ANACTRL interrupts.
*
* @param base ANACTRL peripheral base address.
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
*/
static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask)
{
base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL);
}
/* @} */
/*!
* @name Status Interface
* @{
*/
/*!
* @brief Gets ANACTRL status flags.
*
* This function gets Analog control status flags. The flags are returned as the logical
* OR value of the enumerators @ref _anactrl_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _anactrl_flags.
* For example, to check whether the flash is in power down mode:
* @code
* if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL))
* {
* ...
* }
* @endcode
*
* @param base ANACTRL peripheral base address.
* @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags.
*/
static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base)
{
return base->ANALOG_CTRL_STATUS;
}
/*!
* @brief Gets ANACTRL oscillators status flags.
*
* This function gets Anactrl oscillators status flags. The flags are returned as the logical
* OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _anactrl_osc_flags.
* For example, to check whether the FRO192M clock output is valid:
* @code
* if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL))
* {
* ...
* }
* @endcode
*
* @param base ANACTRL peripheral base address.
* @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
*/
static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base)
{
return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U);
}
/*!
* @brief Gets ANACTRL interrupt status flags.
*
* This function gets Anactrl interrupt status flags. The flags are returned as the logical
* OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _anactrl_interrupt_flags.
* For example, to check whether the VBAT voltage level is above the threshold:
* @code
* if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL))
* {
* ...
* }
* @endcode
*
* @param base ANACTRL peripheral base address.
* @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
*/
static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base)
{
return base->BOD_DCDC_INT_STATUS & 0x1FFU;
}
/* @} */
#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U))
/*!
* @brief Aux_Bias Control Interfaces
* @{
*/
/*!
* @brief Enables/disabless 1V reference voltage buffer.
*
* @param base ANACTRL peripheral base address.
* @param enable Used to enable or disable 1V reference voltage buffer.
*/
static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable)
{
if (enable)
{
base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
}
else
{
base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
}
}
/* @} */
#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */
#if defined(__cplusplus)
}
#endif
/* @}*/
#endif /* __FSL_ANACTRL_H__ */

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/*
* Copyright 2018-2021 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CASPER_H_
#define _FSL_CASPER_H_
#include "fsl_common.h"
/*! @file */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @addtogroup casper_driver
* @{
*/
/*! @name Driver version */
/*@{*/
/*! @brief CASPER driver version. Version 2.2.3.
*
* Current version: 2.2.3
*
* Change log:
* - Version 2.0.0
* - Initial version
* - Version 2.0.1
* - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input
* - Version 2.0.2
* - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of
* CASPER_RAM
* - Version 2.0.3
* - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation.
* - Version 2.0.4
* - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option.
* This driver is very specific and requires -fno-strict-aliasing.
* - Version 2.0.5
* - Fix sign-compare warning.
* - Version 2.0.6
* - Fix IAR Pa082 warning.
* - Version 2.0.7
* - Fix MISRA-C 2012 issue.
* - Version 2.0.8
* - Add feature macro for CASPER_RAM_OFFSET.
* - Version 2.0.9
* - Remove unused function Jac_oncurve().
* - Fix ECC384 build.
* - Version 2.0.10
* - Fix MISRA-C 2012 issue.
* - Version 2.1.0
* - Add ECC NIST P-521 elliptic curve.
* - Version 2.2.0
* - Rework driver to support multiple curves at once.
* - Version 2.2.1
* - Fix MISRA-C 2012 issue.
* - Version 2.2.2
* - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE
* - Version 2.2.3
* - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control.
*/
#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
/*@}*/
/*! @brief CASPER operation
*
*/
typedef enum _casper_operation
{
kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/
kCASPER_OpMul6464Sum =
0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/
kCASPER_OpMul6464FullSum =
0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */
kCASPER_OpMul6464Reduce =
0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/
kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/
kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last
borrow implicit if any*/
kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/
kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */
kCASPER_OpShiftLeft32 =
0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/
kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by
app (off_CD not used) and off_RES starts at MSW*/
kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/
kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/
kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */
kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */
kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/
kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/
} casper_operation_t;
/*! @brief Algorithm used for CASPER operation */
typedef enum _casper_algo_t
{
kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/
kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */
kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */
} casper_algo_t;
#define CASPER_CP 1
#define CASPER_CP_CTRL0 (0x0 >> 2)
#define CASPER_CP_CTRL1 (0x4 >> 2)
#define CASPER_CP_LOADER (0x8 >> 2)
#define CASPER_CP_STATUS (0xC >> 2)
#define CASPER_CP_INTENSET (0x10 >> 2)
#define CASPER_CP_INTENCLR (0x14 >> 2)
#define CASPER_CP_INTSTAT (0x18 >> 2)
#define CASPER_CP_AREG (0x20 >> 2)
#define CASPER_CP_BREG (0x24 >> 2)
#define CASPER_CP_CREG (0x28 >> 2)
#define CASPER_CP_DREG (0x2C >> 2)
#define CASPER_CP_RES0 (0x30 >> 2)
#define CASPER_CP_RES1 (0x34 >> 2)
#define CASPER_CP_RES2 (0x38 >> 2)
#define CASPER_CP_RES3 (0x3C >> 2)
#define CASPER_CP_MASK (0x60 >> 2)
#define CASPER_CP_REMASK (0x64 >> 2)
#define CASPER_CP_LOCK (0x80 >> 2)
#define CASPER_CP_ID (0xFFC >> 2)
/* mcr (cp, opc1, value, CRn, CRm, opc2) */
#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0)
/* mcrr(coproc, opc1, value, CRm) */
#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off)
/* mrc(coproc, opc1, CRn, CRm, opc2) */
#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0)
/* The model for this algo is that it can be implemented for a fixed size RSA key */
/* for max speed. If this is made into a variable (to allow varying size), then */
/* it will be slower by a bit. */
/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */
/* #define N_bitlen 2048 */
#define N_wordlen_max (4096U / 32U)
enum
{
kCASPER_RamOffset_Result = 0x0u,
kCASPER_RamOffset_Base = (N_wordlen_max + 8u),
kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u),
kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
kCASPER_RamOffset_M64 = 1022U,
};
/*! @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @addtogroup casper_driver
* @{
*/
/*!
* @brief Enables clock and disables reset for CASPER peripheral.
*
* Enable clock and disable reset for CASPER.
*
* @param base CASPER base address
*/
void CASPER_Init(CASPER_Type *base);
/*!
* @brief Disables clock for CASPER peripheral.
*
* Disable clock and enable reset.
*
* @param base CASPER base address
*/
void CASPER_Deinit(CASPER_Type *base);
/*!
*@}
*/ /* end of casper_driver */
/*******************************************************************************
* PKHA API
******************************************************************************/
/*!
* @addtogroup casper_driver_pkha
* @{
*/
/*!
* @brief Performs modular exponentiation - (A^E) mod N.
*
* This function performs modular exponentiation.
*
* @param base CASPER base address
* @param signature first addend (in little endian format)
* @param pubN modulus (in little endian format)
* @param wordLen Size of pubN in bytes
* @param pubE exponent
* @param[out] plaintext Output array to store result of operation (in little endian format)
*/
void CASPER_ModExp(CASPER_Type *base,
const uint8_t *signature,
const uint8_t *pubN,
size_t wordLen,
uint32_t pubE,
uint8_t *plaintext);
/*!
* @brief Initialize prime modulus mod in Casper memory .
*
* Set the prime modulus mod in Casper memory and set N_wordlen
* according to selected algorithm.
*
* @param curve elliptic curve algoritm
*/
void CASPER_ecc_init(casper_algo_t curve);
/*!
* @brief Performs ECC secp256r1 point single scalar multiplication
*
* This function performs ECC secp256r1 point single scalar multiplication
* [resX; resY] = scalar * [X; Y]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate in normal form, little endian.
* @param[out] resY Output Y affine coordinate in normal form, little endian.
* @param X Input X affine coordinate in normal form, little endian.
* @param Y Input Y affine coordinate in normal form, little endian.
* @param scalar Input scalar integer, in normal form, little endian.
*/
void CASPER_ECC_SECP256R1_Mul(
CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]);
/*!
* @brief Performs ECC secp256r1 point double scalar multiplication
*
* This function performs ECC secp256r1 point double scalar multiplication
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate.
* @param[out] resY Output Y affine coordinate.
* @param X1 Input X1 affine coordinate.
* @param Y1 Input Y1 affine coordinate.
* @param scalar1 Input scalar1 integer.
* @param X2 Input X2 affine coordinate.
* @param Y2 Input Y2 affine coordinate.
* @param scalar2 Input scalar2 integer.
*/
void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base,
uint32_t resX[8],
uint32_t resY[8],
uint32_t X1[8],
uint32_t Y1[8],
uint32_t scalar1[8],
uint32_t X2[8],
uint32_t Y2[8],
uint32_t scalar2[8]);
/*!
* @brief Performs ECC secp384r1 point single scalar multiplication
*
* This function performs ECC secp384r1 point single scalar multiplication
* [resX; resY] = scalar * [X; Y]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate in normal form, little endian.
* @param[out] resY Output Y affine coordinate in normal form, little endian.
* @param X Input X affine coordinate in normal form, little endian.
* @param Y Input Y affine coordinate in normal form, little endian.
* @param scalar Input scalar integer, in normal form, little endian.
*/
void CASPER_ECC_SECP384R1_Mul(
CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]);
/*!
* @brief Performs ECC secp384r1 point double scalar multiplication
*
* This function performs ECC secp384r1 point double scalar multiplication
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate.
* @param[out] resY Output Y affine coordinate.
* @param X1 Input X1 affine coordinate.
* @param Y1 Input Y1 affine coordinate.
* @param scalar1 Input scalar1 integer.
* @param X2 Input X2 affine coordinate.
* @param Y2 Input Y2 affine coordinate.
* @param scalar2 Input scalar2 integer.
*/
void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base,
uint32_t resX[12],
uint32_t resY[12],
uint32_t X1[12],
uint32_t Y1[12],
uint32_t scalar1[12],
uint32_t X2[12],
uint32_t Y2[12],
uint32_t scalar2[12]);
/*!
* @brief Performs ECC secp521r1 point single scalar multiplication
*
* This function performs ECC secp521r1 point single scalar multiplication
* [resX; resY] = scalar * [X; Y]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate in normal form, little endian.
* @param[out] resY Output Y affine coordinate in normal form, little endian.
* @param X Input X affine coordinate in normal form, little endian.
* @param Y Input Y affine coordinate in normal form, little endian.
* @param scalar Input scalar integer, in normal form, little endian.
*/
void CASPER_ECC_SECP521R1_Mul(
CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]);
/*!
* @brief Performs ECC secp521r1 point double scalar multiplication
*
* This function performs ECC secp521r1 point double scalar multiplication
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate.
* @param[out] resY Output Y affine coordinate.
* @param X1 Input X1 affine coordinate.
* @param Y1 Input Y1 affine coordinate.
* @param scalar1 Input scalar1 integer.
* @param X2 Input X2 affine coordinate.
* @param Y2 Input Y2 affine coordinate.
* @param scalar2 Input scalar2 integer.
*/
void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base,
uint32_t resX[18],
uint32_t resY[18],
uint32_t X1[18],
uint32_t Y1[18],
uint32_t scalar1[18],
uint32_t X2[18],
uint32_t Y2[18],
uint32_t scalar2[18]);
void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1);
/*!
*@}
*/ /* end of casper_driver_pkha */
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_CASPER_H_ */

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/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cmp.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cmp_1"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief CMP initialization.
*
* This function enables the CMP module and do necessary settings.
*
* @param config Pointer to the configuration structure.
*/
void CMP_Init(const cmp_config_t *config)
{
assert(NULL != config);
uint32_t tmpReg = 0U;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(kCLOCK_Comp);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
/* Reset the CMP module. */
RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn);
#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */
tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK |
PMC_COMP_FILTERCGF_SAMPLEMODE_MASK));
if (true == config->enableLowPower)
{
tmpReg |= PMC_COMP_LOWPOWER_MASK;
}
else
{
tmpReg &= ~PMC_COMP_LOWPOWER_MASK;
}
if (true == config->enableHysteresis)
{
tmpReg |= PMC_COMP_HYST_MASK;
}
else
{
tmpReg &= ~PMC_COMP_HYST_MASK;
}
tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) |
PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode));
PMC->COMP = tmpReg;
}
/*!
* @brief CMP deinitialization.
*
* This function gates the clock for CMP module.
*/
void CMP_Deinit(void)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(kCLOCK_Comp);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* @code
* config->enableHysteresis = true;
* config->enableLowPower = true;
* config->filterClockDivider = kCMP_FilterClockDivide1;
* config->filterSampleMode = kCMP_FilterSampleMode0;
* @endcode
* @param config Pointer to the configuration structure.
*/
void CMP_GetDefaultConfig(cmp_config_t *config)
{
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->enableHysteresis = true;
config->enableLowPower = true;
config->filterClockDivider = kCMP_FilterClockDivide1;
config->filterSampleMode = kCMP_FilterSampleMode0;
}
/*!
* @brief Configures the VREFINPUT.
*
* @param config Pointer to the configuration structure.
*/
void CMP_SetVREF(const cmp_vref_config_t *config)
{
assert(NULL != config);
assert(config->vrefValue < 32U);
uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK);
tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue);
PMC->COMP = tmpReg;
}

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/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_CMP_H_
#define __FSL_CMP_H_
#include "fsl_common.h"
/*!
* @addtogroup cmp_1
* @{
*/
/******************************************************************************
* Definitions.
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 2.2.1. */
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U))
/*@}*/
/*! @brief CMP input mux for positive and negative sides. */
enum _cmp_input_mux
{
kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */
kCMP_Input1 = 1U, /*!< Cmp input source 1. */
kCMP_Input2 = 2U, /*!< Cmp input source 2. */
kCMP_Input3 = 3U, /*!< Cmp input source 3. */
kCMP_Input4 = 4U, /*!< Cmp input source 4. */
kCMP_Input5 = 5U, /*!< Cmp input source 5. */
};
/*! @brief CMP interrupt type. */
enum _cmp_interrupt_type
{
kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */
kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */
kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */
kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */
kCMP_LevelDisable = 1U, /*!< Disable level interupt. */
kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */
kCMP_LevelLow = 5U, /*!< Interrupt on low level. */
};
/*! @brief CMP Voltage Reference source. */
typedef enum _cmp_vref_source
{
KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */
KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */
} cmp_vref_source_t;
typedef struct _cmp_vref_config
{
cmp_vref_source_t vrefSource; /*!< Reference voltage source. */
uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */
} cmp_vref_config_t;
/*! @brief CMP Filter sample mode. */
typedef enum _cmp_filtercgf_samplemode
{
kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */
kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */
kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */
kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */
} cmp_filtercgf_samplemode_t;
/*! @brief CMP Filter clock divider. */
typedef enum _cmp_filtercgf_clkdiv
{
kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */
kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */
kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */
kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */
kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */
kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */
kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */
} cmp_filtercgf_clkdiv_t;
/*! @brief CMP configuration structure. */
typedef struct _cmp_config
{
bool enableHysteresis; /*!< Enable hysteresis. */
bool enableLowPower; /*!< Enable low power mode. */
cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock
divided by 2^FILTERCGF_CLKDIV. */
cmp_filtercgf_samplemode_t
filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */
} cmp_config_t;
/*************************************************************************************************
* API
************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief CMP initialization.
*
* This function enables the CMP module and do necessary settings.
*
* @param config Pointer to the configuration structure.
*/
void CMP_Init(const cmp_config_t *config);
/*!
* @brief CMP deinitialization.
*
* This function gates the clock for CMP module.
*/
void CMP_Deinit(void);
/*!
* @brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* @code
* config->enableHysteresis = true;
* config->enableLowPower = true;
* config->filterClockDivider = kCMP_FilterClockDivide1;
* config->filterSampleMode = kCMP_FilterSampleMode0;
* @endcode
* @param config Pointer to the configuration structure.
*/
void CMP_GetDefaultConfig(cmp_config_t *config);
/* @} */
/*!
* @name Compare Interface
* @{
*/
/*
* @brief Set the input channels for the comparator.
*
* @param positiveChannel Positive side input channel number. See "_cmp_input_mux".
* @param negativeChannel Negative side input channel number. See "_cmp_input_mux".
*/
static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel)
{
PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel));
}
/*!
* @brief Configures the VREFINPUT.
*
* @param config Pointer to the configuration structure.
*/
void CMP_SetVREF(const cmp_vref_config_t *config);
/*!
* @brief Get CMP compare output.
*
* @return The output result. true: voltage on positive side is greater than negative side.
* false: voltage on positive side is lower than negative side.
*/
static inline bool CMP_GetOutput(void)
{
return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK);
}
/* @} */
/*!
* @name Interrupt Interface
* @{
*/
/*!
* @brief CMP enable interrupt.
*
* @param type CMP interrupt type. See "_cmp_interrupt_type".
*/
static inline void CMP_EnableInterrupt(uint32_t type)
{
SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK);
}
/*!
* @brief CMP disable interrupt.
*
*/
static inline void CMP_DisableInterrupt(void)
{
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
}
/*!
* @brief CMP clear interrupt.
*
*/
static inline void CMP_ClearInterrupt(void)
{
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
}
/*!
* @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection.
*
* @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
* true: Select Analog Comparator filtered output as input for interrupt detection.
*
* @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the
* interupt source, that is, call this function and set parameter enable to false.
*/
static inline void CMP_EnableFilteredInterruptSource(bool enable)
{
if (enable)
{
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
}
else
{
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
}
}
/* @} */
/*!
* @name Status Interface
* @{
*/
/*!
* @brief Get CMP interrupt status before interupt enable.
*
* @return Interrupt status. true: interrupt pending,
* false: no interrupt pending.
*/
static inline bool CMP_GetPreviousInterruptStatus(void)
{
return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK);
}
/*!
* @brief Get CMP interrupt status after interupt enable.
*
* @return Interrupt status. true: interrupt pending,
* false: no interrupt pending.
*/
static inline bool CMP_GetInterruptStatus(void)
{
return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK);
}
/* @} */
/*!
* @name Filter Interface
* @{
*/
/*!
* @brief CMP Filter Sample Config.
*
* This function allows the users to configure the sampling mode and clock divider of the CMP Filter.
*
* @param filterSampleMode CMP Select filter sample mode
* @param filterClockDivider CMP Set fileter clock divider
*/
static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode,
cmp_filtercgf_clkdiv_t filterClockDivider)
{
uint32_t comp = PMC->COMP;
comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK);
comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) |
((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT));
PMC->COMP = comp;
}
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* __FSL_CMP_H_ */

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#define SDK_MEM_MAGIC_NUMBER 12345U
typedef struct _mem_align_control_block
{
uint16_t identifier; /*!< Identifier for the memory control block. */
uint16_t offset; /*!< offset from aligned address to real address */
} mem_align_cb_t;
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.common"
#endif
#if !((defined(__DSC__) && defined(__CW__)))
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;
uint32_t alignedsize;
/* Check overflow. */
alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
if (alignedsize < size)
{
return NULL;
}
if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
{
return NULL;
}
alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
union
{
void *pointer_value;
uintptr_t unsigned_value;
} p_align_addr, p_addr;
p_addr.pointer_value = malloc((size_t)alignedsize);
if (p_addr.pointer_value == NULL)
{
return NULL;
}
p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
return p_align_addr.pointer_value;
}
void SDK_Free(void *ptr)
{
union
{
void *pointer_value;
uintptr_t unsigned_value;
} p_free;
p_free.pointer_value = ptr;
mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
{
return;
}
p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
free(p_free.pointer_value);
}
#endif

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
#include <stddef.h>
#endif
#include "fsl_device_registers.h"
/*!
* @addtogroup ksdk_common
* @{
*/
/*******************************************************************************
* Configurations
******************************************************************************/
/*! @brief Macro to use the default weak IRQ handler in drivers. */
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Construct a status code value from a group and code number. */
#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
/*! @brief Construct the version number for drivers.
*
* The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
* and 16-bit platforms(such as DSC).
*
* @verbatim
| Unused || Major Version || Minor Version || Bug Fix |
31 25 24 17 16 9 8 0
@endverbatim
*/
#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix))
/*! @name Driver version */
/*@{*/
/*! @brief common driver version. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
/*@}*/
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
/*! @brief Status group numbers. */
enum _status_groups
{
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */
kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */
};
/*! \public
* @brief Generic status return codes.
*/
enum
{
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
kStatus_NoTransferInProgress =
MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
kStatus_NoData =
MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*!
* @name Min/max macros
* @{
*/
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* @} */
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
#if !defined(UINT16_MAX)
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @name Suppress fallthrough warning macro */
/* For switch case code block, if case section ends without "break;" statement, there wil be
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
case section which misses "break;"statement.
*/
/* @{ */
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
#else
#define SUPPRESS_FALL_THROUGH_WARNING()
#endif
/* @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
#if !((defined(__DSC__) && defined(__CW__)))
/*!
* @brief Allocate memory with given alignment and aligned size.
*
* This is provided to support the dynamically allocated memory
* used in cache-able region.
* @param size The length required to malloc.
* @param alignbytes The alignment size.
* @retval The allocated memory.
*/
void *SDK_Malloc(size_t size, size_t alignbytes);
/*!
* @brief Free memory.
*
* @param ptr The memory to be release.
*/
void SDK_Free(void *ptr);
#endif
/*!
* @brief Delay at least for some time.
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
* if precise delay count was needed, please implement a new delay function with hardware timer.
*
* @param delayTime_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}
#endif
/*! @} */
#if (defined(__DSC__) && defined(__CW__))
#include "fsl_common_dsc.h"
#elif defined(__XCC__)
#include "fsl_common_dsp.h"
#else
#include "fsl_common_arm.h"
#endif
#endif /* _FSL_COMMON_H_ */

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.common_arm"
#endif
#ifndef __GIC_PRIO_BITS
#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
#ifdef __VECTOR_TABLE
#undef __VECTOR_TABLE
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
irqMaskValue = DisableGlobalIRQ();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[(int32_t)irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
return ret;
}
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#endif /* __GIC_PRIO_BITS. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
* powerlib should be used instead of these functions.
*/
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
/*
* When the SYSCON STARTER registers are discontinuous, these functions are
* implemented in fsl_power.c.
*/
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1UL << intNumber;
(void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
(void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERCLR[index] = 1UL << intNumber;
}
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
/* Use WDT. */
static void enableCpuCycleCounter(void)
{
/* Make sure the DWT trace fucntion is enabled. */
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
{
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
}
/* CYCCNT not supported on this device. */
assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
/* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
{
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
}
}
static uint32_t getCpuCycleCount(void)
{
return DWT->CYCCNT;
}
#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
/* Use software loop. */
#if defined(__CC_ARM) /* This macro is arm v5 specific */
/* clang-format off */
__ASM static void DelayLoop(uint32_t count)
{
loop
SUBS R0, R0, #1
CMP R0, #0
BNE loop
BX LR
}
/* clang-format on */
#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
* use SUB and CMP here for compatibility */
static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV R0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
" SUB R0, R0, #1 \n"
#else
" SUBS R0, R0, #1 \n"
#endif
" CMP R0, #0 \n"
" BNE loop \n"
:
:
: "r0");
}
#endif /* defined(__CC_ARM) */
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
/*!
* @brief Delay at least for some time.
* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
*
* @param delayTime_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
{
uint64_t count;
if (delayTime_us > 0U)
{
count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
assert(count <= UINT32_MAX);
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
enableCpuCycleCounter();
/* Calculate the count ticks. */
count += getCpuCycleCount();
if (count > UINT32_MAX)
{
count -= UINT32_MAX;
/* Wait for cyccnt overflow. */
while (count < getCpuCycleCount())
{
}
}
/* Wait for cyccnt reach count value. */
while (count > getCpuCycleCount())
{
}
#else
/* Divide value may be different in various environment to ensure delay is precise.
* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
* two instructions in one period, through test here set divide 1.5. Other M cores use
* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
* not matter because other instructions outside while loop is enough to fill the time.
*/
#if (__CORTEX_M == 7)
count = count / 3U * 2U;
#else
count = count / 4U;
#endif
DelayLoop((uint32_t)count);
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
}
}

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_crc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.lpc_crc"
#endif
#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
/* @brief Default user configuration structure for CRC-CCITT */
#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
#define CRC_DRIVER_DEFAULT_REVERSE_IN false
/*< Default is no bit reverse */
#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
/*< Default is without complement of written data */
#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
/*< Default is no bit reverse */
#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
/*< Default is without complement of CRC data register read data */
#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
/*< Default initial checksum */
#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Enables and configures the CRC peripheral module.
*
* This functions enables the CRC peripheral clock in the LPC SYSCON block.
* It also configures the CRC engine and starts checksum computation by writing the seed.
*
* param base CRC peripheral address.
* param config CRC module configuration structure.
*/
void CRC_Init(CRC_Type *base, const crc_config_t *config)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* enable clock to CRC */
CLOCK_EnableClock(kCLOCK_Crc);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET)
RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn);
#endif
/* configure CRC module and write the seed */
base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
CRC_MODE_CMPL_SUM(config->complementOut);
base->SEED = config->seed;
}
/*!
* brief Loads default values to CRC protocol configuration structure.
*
* Loads default values to CRC protocol configuration structure. The default values are:
* code
* config->polynomial = kCRC_Polynomial_CRC_CCITT;
* config->reverseIn = false;
* config->complementIn = false;
* config->reverseOut = false;
* config->complementOut = false;
* config->seed = 0xFFFFU;
* endcode
*
* param config CRC protocol configuration structure
*/
void CRC_GetDefaultConfig(crc_config_t *config)
{
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN,
CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT,
CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
*config = default_config;
}
/*!
* brief resets CRC peripheral module.
*
* param base CRC peripheral address.
*/
void CRC_Reset(CRC_Type *base)
{
crc_config_t config;
CRC_GetDefaultConfig(&config);
CRC_Init(base, &config);
}
/*!
* brief Write seed (initial checksum) to CRC peripheral module.
*
* param base CRC peripheral address.
* param seed CRC Seed value.
*/
void CRC_WriteSeed(CRC_Type *base, uint32_t seed)
{
/* write the seed (initial checksum) */
base->SEED = seed;
}
/*!
* brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
*
* The values, including seed, can be used to resume CRC calculation later.
* param base CRC peripheral address.
* param config CRC protocol configuration structure
*/
void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
{
/* extract CRC mode settings */
uint32_t mode = base->MODE;
config->polynomial =
(crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT);
config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
/* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
/* now we can obtain intermediate raw CRC sum value */
config->seed = base->SUM;
/* restore original CRC sum bit reverse and 1's complement setting */
base->MODE = mode;
}
/*!
* brief Writes data to the CRC module.
*
* Writes input data buffer bytes to CRC data register.
*
* param base CRC peripheral address.
* param data Input data stream, MSByte in data[0].
* param dataSize Size of the input data buffer in bytes.
*/
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
{
const uint32_t *data32;
/* 8-bit reads and writes till source address is aligned 4 bytes */
while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
{
*((__O uint8_t *)&(base->WR_DATA)) = *data;
data++;
dataSize--;
}
/* use 32-bit reads and writes as long as possible */
data32 = (const uint32_t *)(uint32_t)data;
while (dataSize >= sizeof(uint32_t))
{
*((__O uint32_t *)&(base->WR_DATA)) = *data32;
data32++;
dataSize -= sizeof(uint32_t);
}
data = (const uint8_t *)data32;
/* 8-bit reads and writes till end of data buffer */
while (0U != dataSize)
{
*((__O uint8_t *)&(base->WR_DATA)) = *data;
data++;
dataSize--;
}
}

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CRC_H_
#define _FSL_CRC_H_
#include "fsl_common.h"
/*!
* @addtogroup crc
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CRC driver version. Version 2.1.1.
*
* Current version: 2.1.1
*
* Change log:
* - Version 2.0.0
* - initial version
* - Version 2.0.1
* - add explicit type cast when writing to WR_DATA
* - Version 2.0.2
* - Fix MISRA issue
* - Version 2.1.0
* - Add CRC_WriteSeed function
* - Version 2.1.1
* - Fix MISRA issue
*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
#endif
/*! @brief CRC polynomials to use. */
typedef enum _crc_polynomial
{
kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */
kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
} crc_polynomial_t;
/*!
* @brief CRC protocol configuration.
*
* This structure holds the configuration for the CRC protocol.
*
*/
typedef struct _crc_config
{
crc_polynomial_t polynomial; /*!< CRC polynomial. */
bool reverseIn; /*!< Reverse bits on input. */
bool complementIn; /*!< Perform 1's complement on input. */
bool reverseOut; /*!< Reverse bits on output. */
bool complementOut; /*!< Perform 1's complement on output. */
uint32_t seed; /*!< Starting checksum value. */
} crc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enables and configures the CRC peripheral module.
*
* This functions enables the CRC peripheral clock in the LPC SYSCON block.
* It also configures the CRC engine and starts checksum computation by writing the seed.
*
* @param base CRC peripheral address.
* @param config CRC module configuration structure.
*/
void CRC_Init(CRC_Type *base, const crc_config_t *config);
/*!
* @brief Disables the CRC peripheral module.
*
* This functions disables the CRC peripheral clock in the LPC SYSCON block.
*
* @param base CRC peripheral address.
*/
static inline void CRC_Deinit(CRC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* disable clock to CRC */
CLOCK_DisableClock(kCLOCK_Crc);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief resets CRC peripheral module.
*
* @param base CRC peripheral address.
*/
void CRC_Reset(CRC_Type *base);
/*!
* @brief Write seed to CRC peripheral module.
*
* @param base CRC peripheral address.
* @param seed CRC Seed value.
*/
void CRC_WriteSeed(CRC_Type *base, uint32_t seed);
/*!
* @brief Loads default values to CRC protocol configuration structure.
*
* Loads default values to CRC protocol configuration structure. The default values are:
* @code
* config->polynomial = kCRC_Polynomial_CRC_CCITT;
* config->reverseIn = false;
* config->complementIn = false;
* config->reverseOut = false;
* config->complementOut = false;
* config->seed = 0xFFFFU;
* @endcode
*
* @param config CRC protocol configuration structure
*/
void CRC_GetDefaultConfig(crc_config_t *config);
/*!
* @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
*
* The values, including seed, can be used to resume CRC calculation later.
* @param base CRC peripheral address.
* @param config CRC protocol configuration structure
*/
void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
/*!
* @brief Writes data to the CRC module.
*
* Writes input data buffer bytes to CRC data register.
*
* @param base CRC peripheral address.
* @param data Input data stream, MSByte in data[0].
* @param dataSize Size of the input data buffer in bytes.
*/
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
/*!
* @brief Reads 32-bit checksum from the CRC module.
*
* Reads CRC data register.
*
* @param base CRC peripheral address.
* @return final 32-bit checksum, after configured bit reverse and complement operations.
*/
static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
{
return base->SUM;
}
/*!
* @brief Reads 16-bit checksum from the CRC module.
*
* Reads CRC data register.
*
* @param base CRC peripheral address.
* @return final 16-bit checksum, after configured bit reverse and complement operations.
*/
static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
{
return (uint16_t)base->SUM;
}
#if defined(__cplusplus)
}
#endif
/*!
*@}
*/
#endif /* _FSL_CRC_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_flexcomm.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
#endif
/*!
* @brief Used for conversion between `void*` and `uint32_t`.
*/
typedef union pvoid_to_u32
{
void *pvoid;
uint32_t u32;
} pvoid_to_u32_t;
/*******************************************************************************
* Prototypes
******************************************************************************/
/*! @brief Set the FLEXCOMM mode . */
static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
/*! @brief check whether flexcomm supports peripheral type */
static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Array to map FLEXCOMM instance number to base address. */
static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS;
/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)];
/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)];
/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief IDs of clock for each FLEXCOMM module */
static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
/*! @brief Pointers to FLEXCOMM resets for each instance. */
static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
#endif
/*******************************************************************************
* Code
******************************************************************************/
/* check whether flexcomm supports peripheral type */
static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
{
if (periph == FLEXCOMM_PERIPH_NONE)
{
return true;
}
else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
{
return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
}
else if (periph == FLEXCOMM_PERIPH_I2S_RX)
{
return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;
}
else
{
return false;
}
}
/* Get the index corresponding to the FLEXCOMM */
/*! brief Returns instance number for FLEXCOMM module with given base address. */
uint32_t FLEXCOMM_GetInstance(void *base)
{
uint32_t i;
pvoid_to_u32_t BaseAddr;
BaseAddr.pvoid = base;
for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
{
if (BaseAddr.u32 == s_flexcommBaseAddrs[i])
{
break;
}
}
assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT);
return i;
}
/* Changes FLEXCOMM mode */
static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
{
/* Check whether peripheral type is present */
if (!FLEXCOMM_PeripheralIsPresent(base, periph))
{
return kStatus_OutOfRange;
}
/* Flexcomm is locked to different peripheral type than expected */
if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
{
return kStatus_Fail;
}
/* Check if we are asked to lock */
if (lock != 0)
{
base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
}
else
{
base->PSELID = (uint32_t)periph;
}
return kStatus_Success;
}
/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
{
uint32_t idx = FLEXCOMM_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the peripheral clock */
CLOCK_EnableClock(s_flexcommClocks[idx]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
/* Reset the FLEXCOMM module */
RESET_PeripheralReset(s_flexcommResets[idx]);
#endif
/* Set the FLEXCOMM to given peripheral */
return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
}
/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
* mode */
void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(base);
/* Clear handler first to avoid execution of the handler with wrong handle */
s_flexcommIrqHandler[instance] = NULL;
s_flexcommHandle[instance] = flexcommHandle;
s_flexcommIrqHandler[instance] = handler;
SDK_ISR_EXIT_BARRIER;
}
/* IRQ handler functions overloading weak symbols in the startup */
#if defined(FLEXCOMM0)
void FLEXCOMM0_DriverIRQHandler(void);
void FLEXCOMM0_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM0);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM1)
void FLEXCOMM1_DriverIRQHandler(void);
void FLEXCOMM1_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM1);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM2)
void FLEXCOMM2_DriverIRQHandler(void);
void FLEXCOMM2_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM2);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM3)
void FLEXCOMM3_DriverIRQHandler(void);
void FLEXCOMM3_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM3);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM4)
void FLEXCOMM4_DriverIRQHandler(void);
void FLEXCOMM4_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM4);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM5)
void FLEXCOMM5_DriverIRQHandler(void);
void FLEXCOMM5_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM5);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM6)
void FLEXCOMM6_DriverIRQHandler(void);
void FLEXCOMM6_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM6);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM7)
void FLEXCOMM7_DriverIRQHandler(void);
void FLEXCOMM7_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM7);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM8)
void FLEXCOMM8_DriverIRQHandler(void);
void FLEXCOMM8_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM8);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM9)
void FLEXCOMM9_DriverIRQHandler(void);
void FLEXCOMM9_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM9);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM10)
void FLEXCOMM10_DriverIRQHandler(void);
void FLEXCOMM10_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM10);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM11)
void FLEXCOMM11_DriverIRQHandler(void);
void FLEXCOMM11_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM11);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM12)
void FLEXCOMM12_DriverIRQHandler(void);
void FLEXCOMM12_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM12);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM13)
void FLEXCOMM13_DriverIRQHandler(void);
void FLEXCOMM13_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM13);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM14)
void FLEXCOMM14_DriverIRQHandler(void);
void FLEXCOMM14_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM14);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM15)
void FLEXCOMM15_DriverIRQHandler(void);
void FLEXCOMM15_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM15);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM16)
void FLEXCOMM16_DriverIRQHandler(void);
void FLEXCOMM16_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM16);
assert(s_flexcommIrqHandler[instance] != NULL);
s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
SDK_ISR_EXIT_BARRIER;
}
#endif

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXCOMM_H_
#define _FSL_FLEXCOMM_H_
#include "fsl_common.h"
/*!
* @addtogroup flexcomm_driver
* @{
*/
/*! @name Driver version */
/*@{*/
/*! @brief FlexCOMM driver version 2.0.2. */
#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief FLEXCOMM peripheral modes. */
typedef enum
{
FLEXCOMM_PERIPH_NONE, /*!< No peripheral */
FLEXCOMM_PERIPH_USART, /*!< USART peripheral */
FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */
FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */
FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
} FLEXCOMM_PERIPH_T;
/*! @brief Typedef for interrupt handler. */
typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
/*! @brief Array with IRQ number for each FLEXCOMM module. */
extern IRQn_Type const kFlexcommIrqs[];
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*! @brief Returns instance number for FLEXCOMM module with given base address. */
uint32_t FLEXCOMM_GetInstance(void *base);
/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
* mode */
void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
#if defined(__cplusplus)
}
#endif
/*@}*/
#endif /* _FSL_FLEXCOMM_H_*/

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bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_fro_calib.h Normal file
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/*
* Copyright (c) 2017, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FRO_CALIB_H_
#define _FSL_FRO_CALIB_H_
#include "fsl_common.h"
#include "fsl_device_registers.h"
#include <stdint.h>
/*!
* @addtogroup power
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief FRO_CALIB driver version 1.0.0. */
#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
/*@}*/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.fro_calib"
#endif
/*******************************************************************************
* API
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/* Returns the version of the FRO Calibration library */
unsigned int fro_calib_Get_Lib_Ver(void);
/* ctimer instance */
/* ctimer clock frquency in KHz */
void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq);
/* USB_SOF_Event */
/* Application software should be written to make sure the USB_SOF_EVENT() is */
/* being called with lower interrupt latency for calibration to work properly */
void USB_SOF_Event(void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* _FSL_FRO_CALIB_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_gint.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.gint"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to GINT bases for each instance. */
static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Clocks for each instance. */
static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/*! @brief Resets for each instance. */
static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
/* @brief Irq number for each instance */
static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
/*! @brief Callback function array for GINT(s). */
static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t GINT_GetInstance(GINT_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++)
{
if (s_gintBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_gintBases));
return instance;
}
/*!
* brief Initialize GINT peripheral.
* This function initializes the GINT peripheral and enables the clock.
*
* param base Base address of the GINT peripheral.
*
* retval None.
*/
void GINT_Init(GINT_Type *base)
{
uint32_t instance;
instance = GINT_GetInstance(base);
s_gintCallback[instance] = NULL;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the peripheral clock */
CLOCK_EnableClock(s_gintClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(s_gintResets[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
}
/*!
* brief Setup GINT peripheral control parameters.
* This function sets the control parameters of GINT peripheral.
*
* param base Base address of the GINT peripheral.
* param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
* param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
* param callback This function is called when configured group interrupt is generated.
*
* retval None.
*/
void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
{
uint32_t instance;
instance = GINT_GetInstance(base);
base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
/* Save callback pointer */
s_gintCallback[instance] = callback;
}
/*!
* brief Get GINT peripheral control parameters.
* This function returns the control parameters of GINT peripheral.
*
* param base Base address of the GINT peripheral.
* param comb Pointer to store combine input value.
* param trig Pointer to store trigger value.
* param callback Pointer to store callback function.
*
* retval None.
*/
void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
{
uint32_t instance;
uint32_t combValue;
uint32_t trigValue;
instance = GINT_GetInstance(base);
combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT;
*comb = (gint_comb_t)combValue;
trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT;
*trig = (gint_trig_t)trigValue;
*callback = s_gintCallback[instance];
}
/*!
* brief Configure GINT peripheral pins.
* This function enables and controls the polarity of enabled pin(s) of a given port.
*
* param base Base address of the GINT peripheral.
* param port Port number.
* param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
* param enableMask Each bit position selects if the corresponding pin is enabled or not.
* 0 = The pin is disabled. 1 = The pin is enabled.
*
* retval None.
*/
void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
{
base->PORT_POL[port] = polarityMask;
base->PORT_ENA[port] = enableMask;
}
/*!
* brief Get GINT peripheral pin configuration.
* This function returns the pin configuration of a given port.
*
* param base Base address of the GINT peripheral.
* param port Port number.
* param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
enabled pin.
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
* param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
or not.
* 0 = The pin is disabled. 1 = The pin is enabled.
*
* retval None.
*/
void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
{
*polarityMask = base->PORT_POL[port];
*enableMask = base->PORT_ENA[port];
}
/*!
* brief Enable callback.
* This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
* as soon as they are enabled, the callback function is not enabled until this function is called.
*
* param base Base address of the GINT peripheral.
*
* retval None.
*/
void GINT_EnableCallback(GINT_Type *base)
{
uint32_t instance;
instance = GINT_GetInstance(base);
/* If GINT is configured in "AND" mode a spurious interrupt is generated.
Clear status and pending interrupt before enabling the irq in NVIC. */
GINT_ClrStatus(base);
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
(void)EnableIRQ(s_gintIRQ[instance]);
}
/*!
* brief Disable callback.
* This function disables the interrupt for the selected GINT peripheral. Although the pins are still
* being monitored but the callback function is not called.
*
* param base Base address of the peripheral.
*
* retval None.
*/
void GINT_DisableCallback(GINT_Type *base)
{
uint32_t instance;
instance = GINT_GetInstance(base);
(void)DisableIRQ(s_gintIRQ[instance]);
GINT_ClrStatus(base);
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
}
/*!
* brief Deinitialize GINT peripheral.
* This function disables the GINT clock.
*
* param base Base address of the GINT peripheral.
*
* retval None.
*/
void GINT_Deinit(GINT_Type *base)
{
uint32_t instance;
instance = GINT_GetInstance(base);
/* Cleanup */
GINT_DisableCallback(base);
s_gintCallback[instance] = NULL;
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(s_gintResets[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the peripheral clock */
CLOCK_DisableClock(s_gintClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/* IRQ handler functions overloading weak symbols in the startup */
#if defined(GINT0)
void GINT0_DriverIRQHandler(void);
void GINT0_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[0] != NULL)
{
s_gintCallback[0]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT1)
void GINT1_DriverIRQHandler(void);
void GINT1_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[1] != NULL)
{
s_gintCallback[1]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT2)
void GINT2_DriverIRQHandler(void);
void GINT2_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[2] != NULL)
{
s_gintCallback[2]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT3)
void GINT3_DriverIRQHandler(void);
void GINT3_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[3] != NULL)
{
s_gintCallback[3]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT4)
void GINT4_DriverIRQHandler(void);
void GINT4_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[4] != NULL)
{
s_gintCallback[4]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT5)
void GINT5_DriverIRQHandler(void);
void GINT5_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[5] != NULL)
{
s_gintCallback[5]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT6)
void GINT6_DriverIRQHandler(void);
void GINT6_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[6] != NULL)
{
s_gintCallback[6]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(GINT7)
void GINT7_DriverIRQHandler(void);
void GINT7_DriverIRQHandler(void)
{
/* Clear interrupt before callback */
s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
/* Call user function */
if (s_gintCallback[7] != NULL)
{
s_gintCallback[7]();
}
SDK_ISR_EXIT_BARRIER;
}
#endif

222
bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.h Normal file
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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_GINT_H_
#define _FSL_GINT_H_
#include "fsl_common.h"
/*!
* @addtogroup gint_driver
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
/*@}*/
/*! @brief GINT combine inputs type */
typedef enum _gint_comb
{
kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
} gint_comb_t;
/*! @brief GINT trigger type */
typedef enum _gint_trig
{
kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
} gint_trig_t;
/* @brief GINT port type */
typedef enum _gint_port
{
kGINT_Port0 = 0U,
kGINT_Port1 = 1U,
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
kGINT_Port2 = 2U,
#endif
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
kGINT_Port3 = 3U,
#endif
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
kGINT_Port4 = 4U,
#endif
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
kGINT_Port5 = 5U,
#endif
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
kGINT_Port6 = 6U,
#endif
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
kGINT_Port7 = 7U,
#endif
} gint_port_t;
/*! @brief GINT Callback function. */
typedef void (*gint_cb_t)(void);
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Initialize GINT peripheral.
* This function initializes the GINT peripheral and enables the clock.
*
* @param base Base address of the GINT peripheral.
*
* @retval None.
*/
void GINT_Init(GINT_Type *base);
/*!
* @brief Setup GINT peripheral control parameters.
* This function sets the control parameters of GINT peripheral.
*
* @param base Base address of the GINT peripheral.
* @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
* @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
* @param callback This function is called when configured group interrupt is generated.
*
* @retval None.
*/
void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
/*!
* @brief Get GINT peripheral control parameters.
* This function returns the control parameters of GINT peripheral.
*
* @param base Base address of the GINT peripheral.
* @param comb Pointer to store combine input value.
* @param trig Pointer to store trigger value.
* @param callback Pointer to store callback function.
*
* @retval None.
*/
void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
/*!
* @brief Configure GINT peripheral pins.
* This function enables and controls the polarity of enabled pin(s) of a given port.
*
* @param base Base address of the GINT peripheral.
* @param port Port number.
* @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
* @param enableMask Each bit position selects if the corresponding pin is enabled or not.
* 0 = The pin is disabled. 1 = The pin is enabled.
*
* @retval None.
*/
void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
/*!
* @brief Get GINT peripheral pin configuration.
* This function returns the pin configuration of a given port.
*
* @param base Base address of the GINT peripheral.
* @param port Port number.
* @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
enabled pin.
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
* @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
or not.
* 0 = The pin is disabled. 1 = The pin is enabled.
*
* @retval None.
*/
void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
/*!
* @brief Enable callback.
* This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
* as soon as they are enabled, the callback function is not enabled until this function is called.
*
* @param base Base address of the GINT peripheral.
*
* @retval None.
*/
void GINT_EnableCallback(GINT_Type *base);
/*!
* @brief Disable callback.
* This function disables the interrupt for the selected GINT peripheral. Although the pins are still
* being monitored but the callback function is not called.
*
* @param base Base address of the peripheral.
*
* @retval None.
*/
void GINT_DisableCallback(GINT_Type *base);
/*!
* @brief Clear GINT status.
* This function clears the GINT status bit.
*
* @param base Base address of the GINT peripheral.
*
* @retval None.
*/
static inline void GINT_ClrStatus(GINT_Type *base)
{
base->CTRL |= GINT_CTRL_INT_MASK;
}
/*!
* @brief Get GINT status.
* This function returns the GINT status.
*
* @param base Base address of the GINT peripheral.
*
* @retval status = 0 No group interrupt request. = 1 Group interrupt request active.
*/
static inline uint32_t GINT_GetStatus(GINT_Type *base)
{
return (base->CTRL & GINT_CTRL_INT_MASK);
}
/*!
* @brief Deinitialize GINT peripheral.
* This function disables the GINT clock.
*
* @param base Base address of the GINT peripheral.
*
* @retval None.
*/
void GINT_Deinit(GINT_Type *base);
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* _FSL_GINT_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_gpio.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Array to map FGPIO instance number to clock name. */
static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
/*! @brief Pointers to GPIO resets for each instance. */
static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
#endif
/*******************************************************************************
* Prototypes
************ ******************************************************************/
/*!
* @brief Enable GPIO port clock.
*
* @param base GPIO peripheral base pointer.
* @param port GPIO port number.
*/
static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port);
/*******************************************************************************
* Code
******************************************************************************/
static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
assert(port < ARRAY_SIZE(s_gpioClockName));
/* Upgate the GPIO clock */
CLOCK_EnableClock(s_gpioClockName[port]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Initializes the GPIO peripheral.
*
* This function ungates the GPIO clock.
*
* param base GPIO peripheral base pointer.
* param port GPIO port number.
*/
void GPIO_PortInit(GPIO_Type *base, uint32_t port)
{
GPIO_EnablePortClock(base, port);
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
/* Reset the GPIO module */
RESET_PeripheralReset(s_gpioResets[port]);
#endif
}
/*!
* brief Initializes a GPIO pin used by the board.
*
* To initialize the GPIO, define a pin configuration, either input or output, in the user file.
* Then, call the GPIO_PinInit() function.
*
* This is an example to define an input pin or output pin configuration:
* code
* Define a digital input pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalInput,
* 0,
* }
* Define a digital output pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalOutput,
* 0,
* }
* endcode
*
* param base GPIO peripheral base pointer(Typically GPIO)
* param port GPIO port number
* param pin GPIO pin number
* param config GPIO pin configuration pointer
*/
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
{
GPIO_EnablePortClock(base, port);
if (config->pinDirection == kGPIO_DigitalInput)
{
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
base->DIRCLR[port] = 1UL << pin;
#else
base->DIR[port] &= ~(1UL << pin);
#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
}
else
{
/* Set default output value */
if (config->outputLogic == 0U)
{
base->CLR[port] = (1UL << pin);
}
else
{
base->SET[port] = (1UL << pin);
}
/* Set pin direction */
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
base->DIRSET[port] = 1UL << pin;
#else
base->DIR[port] |= 1UL << pin;
#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
}
}
#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
/*!
* @brief Set the configuration of pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number
* @param pin GPIO pin number.
* @param config GPIO pin interrupt configuration..
*/
void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
{
base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin);
base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin);
}
/*!
* @brief Enables multiple pins interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
{
if ((uint32_t)kGPIO_InterruptA == index)
{
base->INTENA[port] = base->INTENA[port] | mask;
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
base->INTENB[port] = base->INTENB[port] | mask;
}
else
{
/*Should not enter here*/
}
}
/*!
* @brief Disables multiple pins interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
{
if ((uint32_t)kGPIO_InterruptA == index)
{
base->INTENA[port] = base->INTENA[port] & ~mask;
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
base->INTENB[port] = base->INTENB[port] & ~mask;
}
else
{
/*Should not enter here*/
}
}
/*!
* @brief Clears multiple pins interrupt flag. Status flags are cleared by
* writing a 1 to the corresponding bit position.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
{
if ((uint32_t)kGPIO_InterruptA == index)
{
base->INTSTATA[port] = mask;
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
base->INTSTATB[port] = mask;
}
else
{
/*Should not enter here*/
}
}
/*!
* @ Read port interrupt status.
*
* @param base GPIO base pointer.
* @param port GPIO port number
* @param index GPIO interrupt number.
* @retval masked GPIO status value
*/
uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)
{
uint32_t status = 0U;
if ((uint32_t)kGPIO_InterruptA == index)
{
status = base->INTSTATA[port];
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
status = base->INTSTATB[port];
}
else
{
/*Should not enter here*/
}
return status;
}
/*!
* @brief Enables the specific pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param pin GPIO pin number.
* @param index GPIO interrupt number.
*/
void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
{
if ((uint32_t)kGPIO_InterruptA == index)
{
base->INTENA[port] = base->INTENA[port] | (1UL << pin);
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
base->INTENB[port] = base->INTENB[port] | (1UL << pin);
}
else
{
/*Should not enter here*/
}
}
/*!
* @brief Disables the specific pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param pin GPIO pin number.
* @param index GPIO interrupt number.
*/
void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
{
if ((uint32_t)kGPIO_InterruptA == index)
{
base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);
}
else
{
/*Should not enter here*/
}
}
/*!
* @brief Clears the specific pin interrupt flag. Status flags are cleared by
* writing a 1 to the corresponding bit position.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
{
if ((uint32_t)kGPIO_InterruptA == index)
{
base->INTSTATA[port] = 1UL << pin;
}
else if ((uint32_t)kGPIO_InterruptB == index)
{
base->INTSTATB[port] = 1UL << pin;
}
else
{
/*Should not enter here*/
}
}
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _LPC_GPIO_H_
#define _LPC_GPIO_H_
#include "fsl_common.h"
/*!
* @addtogroup lpc_gpio
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief LPC GPIO driver version. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
/*@}*/
/*! @brief LPC GPIO direction definition */
typedef enum _gpio_pin_direction
{
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
} gpio_pin_direction_t;
/*!
* @brief The GPIO pin configuration structure.
*
* Every pin can only be configured as either output pin or input pin at a time.
* If configured as a input pin, then leave the outputConfig unused.
*/
typedef struct _gpio_pin_config
{
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
/* Output configurations, please ignore if configured as a input one */
uint8_t outputLogic; /*!< Set default output logic, no use in input */
} gpio_pin_config_t;
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
#define GPIO_PIN_INT_LEVEL 0x00U
#define GPIO_PIN_INT_EDGE 0x01U
#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
/*! @brief GPIO Pin Interrupt enable mode */
typedef enum _gpio_pin_enable_mode
{
kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */
} gpio_pin_enable_mode_t;
/*! @brief GPIO Pin Interrupt enable polarity */
typedef enum _gpio_pin_enable_polarity
{
kGPIO_PinIntEnableHighOrRise =
PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */
kGPIO_PinIntEnableLowOrFall =
PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */
} gpio_pin_enable_polarity_t;
/*! @brief LPC GPIO interrupt index definition */
typedef enum _gpio_interrupt_index
{
kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/
kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/
} gpio_interrupt_index_t;
/*! @brief Configures the interrupt generation condition. */
typedef struct _gpio_interrupt_config
{
uint8_t mode; /* The trigger mode of GPIO interrupts */
uint8_t polarity; /* The polarity of GPIO interrupts */
} gpio_interrupt_config_t;
#endif
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*! @name GPIO Configuration */
/*@{*/
/*!
* @brief Initializes the GPIO peripheral.
*
* This function ungates the GPIO clock.
*
* @param base GPIO peripheral base pointer.
* @param port GPIO port number.
*/
void GPIO_PortInit(GPIO_Type *base, uint32_t port);
/*!
* @brief Initializes a GPIO pin used by the board.
*
* To initialize the GPIO, define a pin configuration, either input or output, in the user file.
* Then, call the GPIO_PinInit() function.
*
* This is an example to define an input pin or output pin configuration:
* @code
* Define a digital input pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalInput,
* 0,
* }
* Define a digital output pin configuration,
* gpio_pin_config_t config =
* {
* kGPIO_DigitalOutput,
* 0,
* }
* @endcode
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param pin GPIO pin number
* @param config GPIO pin configuration pointer
*/
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
/*@}*/
/*! @name GPIO Output Operations */
/*@{*/
/*!
* @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param pin GPIO pin number
* @param output GPIO pin output logic level.
* - 0: corresponding pin output low-logic level.
* - 1: corresponding pin output high-logic level.
*/
static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
{
base->B[port][pin] = output;
}
/*@}*/
/*! @name GPIO Input Operations */
/*@{*/
/*!
* @brief Reads the current input value of the GPIO PIN.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param pin GPIO pin number
* @retval GPIO port input value
* - 0: corresponding pin input low-logic level.
* - 1: corresponding pin input high-logic level.
*/
static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
{
return (uint32_t)base->B[port][pin];
}
/*@}*/
/*!
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
{
base->SET[port] = mask;
}
/*!
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
{
base->CLR[port] = mask;
}
/*!
* @brief Reverses current output logic of the multiple GPIO pins.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
{
base->NOT[port] = mask;
}
/*@}*/
/*!
* @brief Reads the current input value of the whole GPIO port.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
*/
static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
{
return (uint32_t)base->PIN[port];
}
/*@}*/
/*! @name GPIO Mask Operations */
/*@{*/
/*!
* @brief Sets port mask, 0 - enable pin, 1 - disable pin.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
{
base->MASK[port] = mask;
}
/*!
* @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @param output GPIO port output value.
*/
static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
{
base->MPIN[port] = output;
}
/*!
* @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
* affected.
*
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
* @retval masked GPIO port value
*/
static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
{
return (uint32_t)base->MPIN[port];
}
#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
/*!
* @brief Set the configuration of pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number
* @param pin GPIO pin number.
* @param config GPIO pin interrupt configuration..
*/
void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);
/*!
* @brief Enables multiple pins interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
/*!
* @brief Disables multiple pins interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
/*!
* @brief Clears pin interrupt flag. Status flags are cleared by
* writing a 1 to the corresponding bit position.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param index GPIO interrupt number.
* @param mask GPIO pin number macro.
*/
void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
/*!
* @ Read port interrupt status.
*
* @param base GPIO base pointer.
* @param port GPIO port number
* @param index GPIO interrupt number.
* @retval masked GPIO status value
*/
uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);
/*!
* @brief Enables the specific pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param pin GPIO pin number.
* @param index GPIO interrupt number.
*/
void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
/*!
* @brief Disables the specific pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param pin GPIO pin number.
* @param index GPIO interrupt number.
*/
void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
/*!
* @brief Clears the specific pin interrupt flag. Status flags are cleared by
* writing a 1 to the corresponding bit position.
*
* @param base GPIO base pointer.
* @param port GPIO port number.
* @param pin GPIO pin number.
* @param index GPIO interrupt number.
*/
void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
/*@}*/
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _LPC_GPIO_H_*/

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