[bsp][gd32103c-eval] Add hwtimer driver

This commit is contained in:
iysheng committed 2021-02-05 11:45:05 +08:00
1 parent d514fea54a
commit 2b50fbafe2
9 files changed
+787 -148

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+30
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@@ -66,5 +66,35 @@ menu "On-chip Peripheral Drivers"
bool "using adc1"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
endmenu
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@@ -455,14 +455,14 @@ typedef struct {
#define RCC_APB2PERIPH_GPIOG RCC_APB2CCR_PGEN
#define RCC_APB2PERIPH_ADC0 RCC_APB2CCR_ADC0EN
#define RCC_APB2PERIPH_ADC1 RCC_APB2CCR_ADC1EN
#define RCC_APB2PERIPH_TIMER1 RCC_APB2CCR_TIMER1EN
#define RCC_APB2PERIPH_TIMER0 RCC_APB2CCR_TIMER0EN
#define RCC_APB2PERIPH_SPI1 RCC_APB2CCR_SPI1EN
#define RCC_APB2PERIPH_TIMER8 RCC_APB2CCR_TIMER8EN
#define RCC_APB2PERIPH_TIMER7 RCC_APB2CCR_TIMER7EN
#define RCC_APB2PERIPH_USART1 RCC_APB2CCR_USART1EN
#define RCC_APB2PERIPH_ADC2 RCC_APB2CCR_ADC2EN
#define RCC_APB2PERIPH_TIMER9 RCC_APB2CCR_TIMER9EN
#define RCC_APB2PERIPH_TIMER8 RCC_APB2CCR_TIMER8EN
#define RCC_APB2PERIPH_TIMER9 RCC_APB2CCR_TIMER9EN
#define RCC_APB2PERIPH_TIMER10 RCC_APB2CCR_TIMER10EN
#define RCC_APB2PERIPH_TIMER11 RCC_APB2CCR_TIMER11EN
/**
* @}
@@ -481,14 +481,14 @@ typedef struct {
#define RCC_APB2PERIPH_GPIOGRST RCC_APB2RCR_PGRST
#define RCC_APB2PERIPH_ADC0RST RCC_APB2RCR_ADC0RST
#define RCC_APB2PERIPH_ADC1RST RCC_APB2RCR_ADC1RST
#define RCC_APB2PERIPH_TIMER1RST RCC_APB2RCR_TIMER1RST
#define RCC_APB2PERIPH_TIMER0RST RCC_APB2RCR_TIMER0RST
#define RCC_APB2PERIPH_SPI1RST RCC_APB2RCR_SPI1RST
#define RCC_APB2PERIPH_TIMER8RST RCC_APB2RCR_TIMER8RST
#define RCC_APB2PERIPH_TIMER7RST RCC_APB2RCR_TIMER7RST
#define RCC_APB2PERIPH_USART0RST RCC_APB2RCR_USART0RST
#define RCC_APB2PERIPH_ADC2RST RCC_APB2RCR_ADC2RST
#define RCC_APB2PERIPH_TIMER8RST RCC_APB2RCR_TIMER8RST
#define RCC_APB2PERIPH_TIMER9RST RCC_APB2RCR_TIMER9RST
#define RCC_APB2PERIPH_TIMER10RST RCC_APB2RCR_TIMER10RST
#define RCC_APB2PERIPH_TIMER11RST RCC_APB2RCR_TIMER11RST
/**
* @}
@@ -497,15 +497,15 @@ typedef struct {
/** @defgroup RCC_APB1_peripheral
* @{
*/
#define RCC_APB1PERIPH_TIMER1 RCC_APB1CCR_TIMER1EN
#define RCC_APB1PERIPH_TIMER2 RCC_APB1CCR_TIMER2EN
#define RCC_APB1PERIPH_TIMER3 RCC_APB1CCR_TIMER3EN
#define RCC_APB1PERIPH_TIMER4 RCC_APB1CCR_TIMER4EN
#define RCC_APB1PERIPH_TIMER5 RCC_APB1CCR_TIMER5EN
#define RCC_APB1PERIPH_TIMER6 RCC_APB1CCR_TIMER6EN
#define RCC_APB1PERIPH_TIMER7 RCC_APB1CCR_TIMER7EN
#define RCC_APB1PERIPH_TIMER11 RCC_APB1CCR_TIMER11EN
#define RCC_APB1PERIPH_TIMER12 RCC_APB1CCR_TIMER12EN
#define RCC_APB1PERIPH_TIMER13 RCC_APB1CCR_TIMER13EN
#define RCC_APB1PERIPH_TIMER14 RCC_APB1CCR_TIMER14EN
#define RCC_APB1PERIPH_WWDG RCC_APB1CCR_WWDGEN
#define RCC_APB1PERIPH_SPI2 RCC_APB1CCR_SPI2EN
#define RCC_APB1PERIPH_SPI3 RCC_APB1CCR_SPI3EN
@@ -529,15 +529,15 @@ typedef struct {
/** @defgroup RCC_APB1_Peripherals_RST
* @{
*/
#define RCC_APB1PERIPH_TIMER1RST RCC_APB1RCR_TIMER1RST
#define RCC_APB1PERIPH_TIMER2RST RCC_APB1RCR_TIMER2RST
#define RCC_APB1PERIPH_TIMER3RST RCC_APB1RCR_TIMER3RST
#define RCC_APB1PERIPH_TIMER4RST RCC_APB1RCR_TIMER4RST
#define RCC_APB1PERIPH_TIMER5RST RCC_APB1RCR_TIMER5RST
#define RCC_APB1PERIPH_TIMER6RST RCC_APB1RCR_TIMER6RST
#define RCC_APB1PERIPH_TIMER7RST RCC_APB1RCR_TIMER7RST
#define RCC_APB1PERIPH_TIMER11RST RCC_APB1RCR_TIMER11RST
#define RCC_APB1PERIPH_TIMER12RST RCC_APB1RCR_TIMER12RST
#define RCC_APB1PERIPH_TIMER13RST RCC_APB1RCR_TIMER13RST
#define RCC_APB1PERIPH_TIMER14RST RCC_APB1RCR_TIMER14RST
#define RCC_APB1PERIPH_WWDGRST RCC_APB1RCR_WWDGRST
#define RCC_APB1PERIPH_SPI2RST RCC_APB1RCR_SPI2RST
#define RCC_APB1PERIPH_SPI3RST RCC_APB1RCR_SPI3RST
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+1
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@@ -47,6 +47,7 @@ msh />
| UART | 支持 | UART0~4 |
| GPIO | 支持 | GPIOA~G |
| ADC | 支持 | ADC0~1 |
| HWTIMER | 支持 | TIMER0~7 |
| IIC | 未支持 | I2C0~1 |
| SPI | 未支持 | SPI0~2 |
| ETH | 未支持 | |
+3
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@@ -21,6 +21,9 @@ if GetDepend('RT_USING_PIN'):
if GetDepend('RT_USING_ADC'):
src += ['drv_adc.c']
if GetDepend('RT_USING_HWTIMER'):
src += ['drv_hwtimer.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
+27
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@@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 iysheng first version
*/
#ifndef __DRV_COMM_H__
#define __DRV_COMM_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */
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+38
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@@ -0,0 +1,38 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-15 iysheng first release
*/
#ifndef __DRV_HWTIMER_H__
#define __DRV_HWTIMER_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <drivers/hwtimer.h>
typedef struct {
TIMER_TypeDef *reg_base;
IRQn_Type irqn;
rcu_periph_enum rcu;
} gd32_hwtimer_data;
typedef struct {
char dev_name[RT_NAME_MAX];
const gd32_hwtimer_data hw_data;
rt_hwtimer_t hwtimer_dev;
const struct rt_hwtimer_info hwtimer_info;
} gd32_hwtimer_device;
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */