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bsp:Separate HC32F4 series library (#10427)

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* bsp:Separate HC32F4 series library
This commit is contained in:
沐攸
2025-06-25 10:02:43 +08:00
committed by GitHub
parent 1fe2a0bbb6
commit 29ab5334af
685 changed files with 15248 additions and 1108314 deletions
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10
bsp/hc32/ev_hc32f448_lqfp80/.config
View File

@@ -496,6 +496,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -725,6 +726,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -848,6 +850,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_cmsis"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_series"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
# end of HC32 DDL Drivers
#

25
bsp/hc32/ev_hc32f448_lqfp80/SConstruct
View File

@@ -15,6 +15,25 @@ except:
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -47,11 +66,7 @@ Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f448_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

11
bsp/hc32/ev_hc32f448_lqfp80/board/SConscript
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@@ -1,9 +1,6 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
@@ -16,14 +13,6 @@ path = [cwd]
path += [cwd + '/ports']
path += [cwd + '/config']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']
CPPDEFINES = ['HC32F448', '__DEBUG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

1130
bsp/hc32/ev_hc32f448_lqfp80/project.uvoptx
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1832
bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx
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4
bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h
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@@ -306,6 +306,10 @@
/* HC32 DDL Drivers */
#define PKG_USING_HC32F4_CMSIS_DRIVER
#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION
#define PKG_USING_HC32F4_SERIES_DRIVER
#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */

10
bsp/hc32/ev_hc32f460_lqfp100_v2/.config
View File

@@ -496,6 +496,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -725,6 +726,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -848,6 +850,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_cmsis"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_series"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
# end of HC32 DDL Drivers
#

25
bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct
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@@ -15,6 +15,25 @@ except:
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -47,11 +66,7 @@ Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f460_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

12
bsp/hc32/ev_hc32f460_lqfp100_v2/board/SConscript
View File

@@ -1,9 +1,6 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
@@ -17,15 +14,6 @@ path += [cwd + '/ports']
path += [cwd + '/config']
path += [cwd + '/config/usb_config']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s']
CPPDEFINES = ['HC32F460', '__DEBUG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

1218
bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvoptx
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1993
bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx
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4
bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h
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@@ -306,6 +306,10 @@
/* HC32 DDL Drivers */
#define PKG_USING_HC32F4_CMSIS_DRIVER
#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION
#define PKG_USING_HC32F4_SERIES_DRIVER
#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */

10
bsp/hc32/ev_hc32f472_lqfp100/.config
View File

@@ -496,6 +496,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -725,6 +726,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -848,6 +850,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_cmsis"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_series"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
# end of HC32 DDL Drivers
#

25
bsp/hc32/ev_hc32f472_lqfp100/SConstruct
View File

@@ -15,6 +15,25 @@ except:
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -47,11 +66,7 @@ Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f472_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

12
bsp/hc32/ev_hc32f472_lqfp100/board/SConscript
View File

@@ -1,9 +1,6 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
@@ -17,15 +14,6 @@ path += [cwd + '/ports']
path += [cwd + '/config']
path += [cwd + '/config/usb_config']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f472.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f472.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f472.s']
CPPDEFINES = ['HC32F472', '__DEBUG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

1116
bsp/hc32/ev_hc32f472_lqfp100/project.uvoptx
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1825
bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx
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4
bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h
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@@ -306,6 +306,10 @@
/* HC32 DDL Drivers */
#define PKG_USING_HC32F4_CMSIS_DRIVER
#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION
#define PKG_USING_HC32F4_SERIES_DRIVER
#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */

10
bsp/hc32/ev_hc32f4a0_lqfp176/.config
View File

@@ -499,6 +499,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -728,6 +729,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -851,6 +853,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_cmsis"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_series"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
# end of HC32 DDL Drivers
#

25
bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct
View File

@@ -15,6 +15,25 @@ except:
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -47,11 +66,7 @@ Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f4a0_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

12
bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript
View File

@@ -1,9 +1,6 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
@@ -17,15 +14,6 @@ path += [cwd + '/ports']
path += [cwd + '/config']
path += [cwd + '/config/usb_config']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
CPPDEFINES = ['HC32F4A0', '__DEBUG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

1130
bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx
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1807
bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx
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4
bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h
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@@ -309,6 +309,10 @@
/* HC32 DDL Drivers */
#define PKG_USING_HC32F4_CMSIS_DRIVER
#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION
#define PKG_USING_HC32F4_SERIES_DRIVER
#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */

14
bsp/hc32/ev_hc32f4a8_lqfp176/.config
View File

@@ -499,6 +499,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -728,6 +729,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -851,10 +853,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
CONFIG_PKG_USING_HC32F4A8_DDL=y
CONFIG_PKG_HC32F4A8_DDL_PATH="/packages/peripherals/hal-sdk/hc32/hc32f4a8_ddl"
CONFIG_PKG_USING_HC32F4A8_DDL_LATEST_VERSION=y
CONFIG_PKG_HC32F4A8_DDL_VER="latest"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_cmsis"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_series"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
# end of HC32 DDL Drivers
#

34
bsp/hc32/ev_hc32f4a8_lqfp176/SConscript
View File

@@ -12,38 +12,4 @@ for d in list:
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
def find_keyword_replace(file_path, keyword, replace, split_num, split_char):
with open(file_path, 'r', encoding='utf-8') as file:
lines = file.readlines()
for i, line in enumerate(lines):
if keyword in line:
parts = line.split(split_char)
parts[split_num] = replace
new_line = split_char.join(parts)
lines[i] = new_line
with open(file_path, 'w', encoding='utf-8') as file:
file.writelines(lines)
Import('PACKAGES_PATH')
replace = PACKAGES_PATH.split("\\")[-1]
if rtconfig.PLATFORM in ['gcc']:
file_path = os.path.join(cwd, 'jlink', 'ev_hc32f4a8_lqfp176 Debug.launch')
svd_keyword = 'HC32F4A8.svd'
split_num = 3
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
file_path = os.path.join(cwd, 'template.uvprojx')
svd_keyword = 'HC32F4A8.SFR'
split_num = 2
elif rtconfig.PLATFORM in ['iccarm']:
file_path = os.path.join(cwd, 'project.ewd')
svd_keyword = 'HC32F4A8.svd'
split_num = 3
board_keyword = 'FlashHC32F4A8xI.board'
find_keyword_replace(file_path, board_keyword, replace, split_num, '/')
find_keyword_replace(file_path, svd_keyword, replace, split_num, '/')
Return('objs')

22
bsp/hc32/ev_hc32f4a8_lqfp176/SConstruct
View File

@@ -15,6 +15,25 @@ except:
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -47,8 +66,7 @@ Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f4a8_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

1
bsp/hc32/ev_hc32f4a8_lqfp176/board/SConscript
View File

@@ -1,5 +1,4 @@
import os
import rtconfig
from building import *
cwd = GetCurrentDir()

2
bsp/hc32/ev_hc32f4a8_lqfp176/jlink/ev_hc32f4a8_lqfp176 Debug.launch
View File

@@ -41,7 +41,7 @@
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/./packages/hc32f4a8_ddl-latest/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F4A8.svd"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/./packages/hc32f4a8/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F4A8.svd"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>

1130
bsp/hc32/ev_hc32f4a8_lqfp176/project.uvoptx
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1686
bsp/hc32/ev_hc32f4a8_lqfp176/project.uvprojx
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File diff suppressed because it is too large Load Diff

6
bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h
View File

@@ -309,8 +309,10 @@
/* HC32 DDL Drivers */
#define PKG_USING_HC32F4A8_DDL
#define PKG_USING_HC32F4A8_DDL_LATEST_VERSION
#define PKG_USING_HC32F4_CMSIS_DRIVER
#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION
#define PKG_USING_HC32F4_SERIES_DRIVER
#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */

10
bsp/hc32/lckfb-hc32f4a0-lqfp100/.config
View File

@@ -499,6 +499,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -728,6 +729,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -851,6 +853,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_cmsis"
CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32_f4_series"
CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y
CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
# end of HC32 DDL Drivers
#

25
bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct
View File

@@ -15,6 +15,25 @@ except:
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -47,11 +66,7 @@ Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f4a0_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

12
bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript
View File

@@ -1,9 +1,6 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
@@ -17,15 +14,6 @@ path += [cwd + '/ports']
path += [cwd + '/config']
path += [cwd + '/config/usb_config']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/hc32f4a0_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
CPPDEFINES = ['HC32F4A0', '__DEBUG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

1128
bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvoptx
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1805
bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvprojx
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File diff suppressed because it is too large Load Diff

4
bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h
View File

@@ -309,6 +309,10 @@
/* HC32 DDL Drivers */
#define PKG_USING_HC32F4_CMSIS_DRIVER
#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION
#define PKG_USING_HC32F4_SERIES_DRIVER
#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */

1
bsp/hc32/libraries/Kconfig
View File

@@ -10,6 +10,7 @@ config SOC_SERIES_HC32F4
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_HC32
select PKG_USING_HC32F4_SERIES_DRIVER
config SOC_SERIES_HC32M1
bool

362
bsp/hc32/libraries/hc32f448_ddl/ChangeLog.md
View File

@@ -1,362 +0,0 @@
# Update History
------
## V1.1.0 Dec 15, 2023
#### documents
#### drivers
- ##### bsp/components
- **24cxx**
- Add null pointer check
- **gt9xx**
- Add null pointer check
- **nt35510**
- Add null pointer check
- **tca9539**
- Add null pointer check
- **w25qxx**
- Add null pointer check
- ##### bsp/ev_hc32f448_lqfp80
- Add API BSP_XTAL32_Init()
- Optimize function BSP_I2C_Init()
- Update EXCLK clock frequency: 100MHz -> 50MHZ in function BSP_CLK_Init()
- Add include file named hc32_ll_fcm.h and add declaration of BSP_XTAL32_Init()
- Modify I2C baudrate: 400000 -> 100000
- Modify the timing: EXCLK 100MHz -> 40MHz
- ##### cmsis/Device
- Optimize TMR4_OCMRxx
- Rename EMB_CTL1 register bit: SRAMERREN -> SRAMECCERREN
- ##### hc32_ll_driver
- **adc**
- Modify typo
- API fixed: ADC_DeInit()
- Add declaration of API ADC_MxChCmd(), ADC_ConvDataAverageMxChCmd(), and add defgroup ADC_Mx_Channel
- Add declaration of API ADC_GetResolution()
- Add API ADC_MxChCmd(),ADC_ConvDataAverageMxChCmd
- Add API ADC_GetResolution()
- **clk**
- Modify comment
- Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType
- Modify API CLK_Xtal32Cmd(), CLK_MrcCmd() and CLK_LrcCmd(), use DDL_DelayUS() to replace CLK_Delay()
- **cmp**
- Modify typo
- **ctc**
- Modify typo
- **dac**
- Refine data validation
- Add assert for set DAC source and modify IS_AMP_CTRL_ALLOWED()
- **dbgc**
- Remove API DBGC_GetChipID()
- Add macro definition DBGC_Trace_Mode
- Add declaration of API DBGC_TraceIoCmd,DBGC_TraceModeConfig
- Remove API DBGC_GetChipID()A
- Add assert to DBGC_PeriphCmd & DBGC_Periph2Cmd
- Add assert IS_DGBC_TRACE_MD and add API DBGC_TraceIoCmd,DBGC_TraceModeConfig
- **dcu**
- Modify typo
- Modify function DCU_IntCmd() for misra
- **dma**
- Add API DMA_SetDataWidth()
- Delete group DMA_AHB_HPROT_Config
- Delete API DMA_AHB_HProtPrivilegeCmd()
- Modify API input param type:u16->u32
- Add structure stc_dma_rc_nonseq_init_t
- Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit()
- Optimize set blocksize & repeat count process
- Add DMA Repeat size assert
- Use macros replace immediate data, modify IS_DMA_NON_SEQ_TRANS_CNT
- **efm**
- Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment
- Optimized macro group EFM_Remap_Size definitions
- Add structure of stc_efm_location_t and declaration of API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID()
- Modify typo
- Remove address assert from EFM_ReadByte()
- Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM
- Add API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID()
- Modify flash sector number defined and API EFM_SequenceSectorOperateCmd()
- **emb**
- Update EMB_CTL1_CMPEN0~3 to EMB_CTL1_CMPEN1~4
- Add stc_emb_monitor_sys_t to combine osc, sram, lockup, lvd
- Replace macro: EMB_CTL1_SRAMERREN -> EMB_CTL1_SRAMECCERREN
- Add marco EMB_FLAG_CLR_ALL
- Function EMB_TMR4_Init don't call EMB_DeInit
- Function EMB_TMR6_Init don't call EMB_DeInit
- Modify stc_emb_monitor_sys_t structure relevant code
- Modify API EMB_ClearStatus assert
- **gpio**
- Modify GPIO_SetFunc()
- Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd
- Optimize API: GPIO_Init(), GPIO_SetFunc(), GPIO_SubFuncCmd(), GPIO_InputMOSCmd(), GPIO_AnalogCmd(), GPIO_ExtIntCmd()
- Add assert for GPIO register lock status in API GPIO_AnalogCmd(), GPIO_ExtIntCmd()
- **i2c**
- Move macro define I2C_SRC_CLK to head file and add marco I2C_WIDTH_MAX_IMME
- Rename I2C_FIFO_FLAG_xx as I2C_FLAG_xx_FIFO_xx, I2C_INT_RFREQ as I2C_INT_RX_FIFO_REQ
- Adjust I2C_FLAG_ALL & I2C_FLAG_CLR_ALL & I2C_INT_ALL
- Add I2C_Flag_Clear def group
- Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus
- Fix I2C_Deinit
- Move macro define I2C_SRC_CLK to head file
- Modify I2C_Restart()
- Refine I2C Flag & API I2C_SlaveAddrConfig/I2C_SlaveMaskAddrConfig
- **icg**
- Modify macro defineICG_SWDT_LPM_CNT_CONTINUE -> ICG_SWDT_LPM_CNT_CONT
- **interrupts**
- Add declaration of API INTC_GetIntSrcState()
- Remove space line
- Add API INTC_GetIntSrcState()
- **mcan**
- Removed definitions related to BEC and BEU.
- Optimized driver:
- 1. Integrated stc_mcan_classic_config_t and stc_mcan_fd_config_t into stc_mcan_bit_time_config_t
- 2. Integrated u32FdIso into u32FrameFormat.
- 3. Removed API MCAN_SetFdIsoOperation(), added API MCAN_SetFrameFormat().
- 4. Optimized the handling of the parameter stc_mcan_filter_t.u32FilterIndex
- 5. Add 5 APIs for better get protocol status(register PSR):
- MCAN_GetTdcValue(), MCAN_GetDataLastErrorCode(), MCAN_GetLastErrorCode(),
- MCAN_GetComState(), MCAN_GetProtocolFlagStatus()
- 6. Changed u8Activity of stc_mcan_protocol_status_t to u8ComState.
- 7. Changed MCAN_Comm_State to MCAN_Com_State and optimized the macros definitions.
- 8. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex. Optimized MCAN_HPM_Storage macros definitions.
- 7. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex.
- 8. Optimized local function MCAN_FilterInitConfig()
- 9. When the frame to be transmitted is a remote frame, do not write the data field to the message RAM.
- When the received frame is a remote frame, do not read the data field from the message RAM.
- Optimized comments.
- **mpu**
- Add structure stc_mpu_unit_init_t, and declaration of MPU_UnitInit(), MPU_UnitStructInit()
- Refine def group MPU_Flag
- Optimize MPU_ClearStatus function
- Add API MPU_UnitInit(), MPU_UnitStructInit()
- **pwc**
- Modify group PWC_Stop_Type
- Add function PWC_LVD_DeInit
- Modify the PWC_LVD_Detection_Voltage_Sel comment
- Modify PWC_RAM_PD_CAN1 as PWC_RAM_PD_MCAN
- Refine API PWC_SLEEP_Enter()
- Remove redundant assert
- Modify API PWC_PD_Enter() #use assert to replace the unlock, and add return value
- Modify API PWC_WKT_SetCompareValue()
- Refine PWC_SLEEP_Enter()
- Add API PWC_PD_SetIoState() & PWC_PD_SetMode()
- **qspi**
- Optimize QSPI_ClearStatus function
- **spi**
- Rename SPI_FLAG_OVERLOAD as SPI_FLAG_OVERRUN, SPI_FLAG_UNDERLOAD as SPI_FLAG_UNDERRUN
- Modify some assert
- Rename some API SPI_xxxConfig as SPI_Setxxx
- Add Send restriction in SPI_TxRx function
- **sram**
- Modify typo
- Refine def group SRAM_ECC_Mode, and refine def group SRAM_Err_Mode as SRAM_Exception_Type
- Remove wait cycle relevant code
- API fixed: SRAM_ClearStatus()
- Refine SRAM_SetEccMode, and refine SRAM_SetErrorMode() as SRAM_SetExceptionType
- **swdt**
- Modify macro define: SWDT_LPM_CNT_CONTINUE -> SWDT_LPM_CNT_CONT
- Optimize SWDT_ClearStatus function timeout
- **tmr6**
- Modify macro define for group TMR6_Emb_Ch_Define
- Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON
- Modify typo
- **usart**
- Remove u32StopBit param from stc_usart_smartcard_init_t structure
- Add the declaration of API USART_GetFuncState()
- Modify return type of function USART_DeInit()
- Modify USART_SmartCard_Init() for stc_usart_smartcard_init_t has modified(u32StopBit has removed)
- Fix bug: did not enable MP while USART_MultiProcessor_Init()
- API refined: USART_SetBaudrate()
- Add API USART_GetFuncState()
- **utility**
- Modify register USART DR to USART TDR
- Prohibit DDL_DelayMS and DDL_DelayUS functions from being optimized
- **wdt**
- Modify macro define: WDT_LPM_CNT_CONTINUE -> WDT_LPM_CNT_CONT
- Optimize WDT_ClearStatus function timeout
#### midwares
#### projects
- ##### ev_hc32f448_lqfp80/applications
- **functional_safety/iec60730_class_b**
- Initialize XTAL32 using BSP_XTAL32_Init
- **iap/iap_boot**
- Removed SRAM wait cycle relevant code
- **iap/iap_ymodem_boot**
- Removed SRAM wait cycle relevant code
- ##### ev_hc32f448_lqfp80/examples
- **adc/adc_awd**
- Set XTAL as system clock source
- **adc/adc_base**
- Set XTAL as system clock source
- **adc/adc_buffer_mode**
- Set XTAL as system clock source
- **adc/adc_channel_remap**
- Set XTAL as system clock source
- **adc/adc_dma**
- Set XTAL as system clock source
- **adc/adc_hard_trigger**
- Set XTAL as system clock source
- **adc/adc_internal_analog_channel**
- Set XTAL as system clock source
- **adc/adc_over_sample**
- Set XTAL as system clock source
- **adc/adc_sync_mode**
- Removed SRAM wait cycle relevant code
- **aes/aes_base**
- Set XTAL as system clock source
- **clk/clk_switch_sysclk**
- Modify XTAL32 initialize process
- Removed SRAM wait cycle relevant code
- **clk/clk_xtalstop_detect**
- Use CLK_XtalStdInit() to replace XtalStopDetctInit()
- Modify XTAL_STOP_IrqCallback
- **ctc/ctc_ctcref_single_trimming**
- Initialize XTAL32 using BSP_XTAL32_Init
- **ctc/ctc_xtal32_trimming**
- Initialize XTAL32 using BSP_XTAL32_Init
- **dmac/dmac_base**
- Optimize DMA2_Error_Handler()
- **dmac/dmac_non_sequence**
- Fixed bug #revert test code.
- **efm/efm_chip_erase**
- Fixed bug # release write protect before sector erase
- **efm/efm_dbus**
- Set API DBUS_Protect_test optimization level
- **efm/efm_sequence_program**
- Re-structure
- **efm/efm_swap**
- Use EFM_GetSwapStatus to judge
- **emb/emb_cmp_brake_timer4**
- Fix magic number
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- **emb/emb_cmp_brake_timer6**
- Fix magic number
- **emb/emb_lockup_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- Optimize comments: HardFault_Generate and HardFault_Handler
- **emb/emb_lockup_brake_timer6**
- Optimize comments: HardFault_Generate and HardFault_Handler
- **emb/emb_lvd_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- **emb/emb_osc_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- **emb/emb_port_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- **emb/emb_pwm_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- **emb/emb_sram_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- Optimize the 2nd data in SRAM_GenerateError()
- **emb/emb_sram_brake_timer6**
- Optimize the 2nd data in SRAM_GenerateError()
- **emb/emb_sw_brake_timer4**
- Modify TMR4_PwmConfig: enable main output following PWM initialization
- **event_port/ep_inout**
- Comment revise
- **exmc/exmc_smc_lcd_nt35510**
- Re-implement BSP_CLK_Init()
- **exmc/exmc_smc_sram_is61lv6416**
- Fix typos and modify file brief
- Fix memory address printf value
- Re-implement BSP_CLK_Init()
- **exmc/exmc_smc_sram_is61lv6416_dma**
- Add exmc_smc_sram_is61lv6416_dma example
- **hash/hash_base**
- Set XTAL as system clock source
- **i2c/i2c_master_dma**
- Add definition I2C_ADDR_MD as address condition select
- Configure DMA interrupt disable in I2C_DMA_Initialize() function
- **i2c/i2c_master_polling**
- Add definition I2C_ADDR_MD as address condition select
- **i2c/i2c_master_polling_fifo**
- Add definition I2C_ADDR_MD as address condition select
- **i2c/i2c_slave_dma**
- Remove redundant process for slave address commands
- Add definition I2C_ADDR_MD as address condition select
- Configure DMA interrupt disable in I2C_DMA_Initialize() function
- **i2c/i2c_slave_int**
- Remove redundant process for slave address commands
- Add definition I2C_ADDR_MD as address condition select
- **i2c/i2c_slave_polling**
- Add definition I2C_ADDR_MD as address condition select
- **i2c/i2c_slave_polling_fifo**
- Remove redundant process for slave address commands
- Add definition I2C_ADDR_MD as address condition select
- **icg/icg_wdt_interrupt_hw_startup**
- Add delay before WDT_GetStatus function
- **intc/intc_nmi_xtalstop**
- optimize function NMI_Xtal_Init
- **mcan/mcan_classical**
- Updates related to MCAN driver optimization.
- Peripheral SRAMC not used, removed related code.
- Code and comments optimized.
- **mcan/mcan_fd**
- Updates related to MCAN driver optimization.
- Peripheral SRAMC not used, removed related code.
- Code and comments optimized.
- **mcan/mcan_loopback**
- Optimized the example.
- **mpu/mpu_core_write_protect**
- Fixed parameters error of Core_MPU_Region_Size
- Modify trigger condition for RTC protection
- Optimize RTC init sequence
- **mpu/mpu_dma_write_protect**
- Remove key jitter
- **mpu/mpu_ip_read_protect**
- Optimize RTC init sequence
- **pwc/pwc_lpc**
- Disable HRC when enter sleep mode
- **pwc/pwc_stop_wake**
- Delete redundant code
- **qspi/qspi_base**
- Add read function of direct communication mode
- **rtc/rtc_alarm**
- Optimize RTC init sequence
- Replace XTAL32_ClkInit to BSP_XTAL32_Init
- **rtc/rtc_calendar**
- Optimize RTC init sequence
- **rtc/rtc_calibration_output**
- Optimize RTC init sequence
- Replace XTAL32_ClkInit to BSP_XTAL32_Init
- **rtc/rtc_low_power**
- Optimize RTC init sequence
- **sram/sram_error_check**
- sample code changed according to driver change
- **timer0/timer0_basetimer**
- Replace XTAL32_Config to BSP_XTAL32_Init
- **timer4/timer4_pwm_through**
- Modify the initial configuration to achieve 0% or 100% duty cycle
- **timer6/timer6_cmp_deadtime**
- Remove redundant code
- **timer6/timer6_cmp_sawtooth**
- Remove redundant code
- **timer6/timer6_cmp_sawtooth_dual_buf**
- Remove redundant code
- Modify compare register buffer initialization value
- **timer6/timer6_cmp_triangular_buf**
- Remove redundant code
- Modify compare register buffer initialization value
- **timer6/timer6_pwm_dynamic_dutycycle**
- Add timer6_pwm_dynamic_dutycycle example
- **timer6/timer6_valid_period**
- Modify compare register buffer initialization value
- **timera/timera_capture**
- Set XTAL as system clock source
- **timera/timera_compare_value_buffer**
- Set XTAL as system clock source
- **timera/timera_position_overflow_count**
- Set XTAL as system clock source
- **trng/trng_base**
- TRNG_Handler add __DSB for Arm Errata 838869
- Add TRNG_Cmd function
- Set XTAL as system clock source
- **usart/usart_clocksync_dma**
- Fix bug: possible null pointer for ClockSync_DMAConfig parameter pstcHandle
- **usart/usart_smartcard_atr**
- Remove u32StopBit from stcSmartCardInit structure
- **usart/usart_uart_dma**
- Optimize function: USART_TxComplete_IrqCallback
- **usart/usart_uart_multiprocessor**
- Optimize the RX process
- **wdt/wdt_interrupt_sw_startup**
- Add delay before WDT_GetStatus function
#### utils
------
## V1.0.0 May 31, 2023
- Initial release.

29
bsp/hc32/libraries/hc32f448_ddl/LICENSE
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@@ -1,29 +0,0 @@
BSD 3-Clause License
Copyright (c) 2022-2023, Xiaohua Semiconductor Co., Ltd. ("XHSC")
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

97
bsp/hc32/libraries/hc32f448_ddl/SConscript
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split('''
cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f448.c
hc32_ll_driver/src/hc32_ll.c
hc32_ll_driver/src/hc32_ll_aos.c
hc32_ll_driver/src/hc32_ll_clk.c
hc32_ll_driver/src/hc32_ll_dma.c
hc32_ll_driver/src/hc32_ll_efm.c
hc32_ll_driver/src/hc32_ll_fcg.c
hc32_ll_driver/src/hc32_ll_fcm.c
hc32_ll_driver/src/hc32_ll_gpio.c
hc32_ll_driver/src/hc32_ll_icg.c
hc32_ll_driver/src/hc32_ll_interrupts.c
hc32_ll_driver/src/hc32_ll_pwc.c
hc32_ll_driver/src/hc32_ll_rmu.c
hc32_ll_driver/src/hc32_ll_sram.c
hc32_ll_driver/src/hc32_ll_utility.c
''')
if GetDepend(['RT_USING_SERIAL']):
src += ['hc32_ll_driver/src/hc32_ll_usart.c']
src += ['hc32_ll_driver/src/hc32_ll_tmr0.c']
if GetDepend(['RT_USING_I2C']):
src += ['hc32_ll_driver/src/hc32_ll_i2c.c']
if GetDepend(['RT_USING_SPI']):
src += ['hc32_ll_driver/src/hc32_ll_spi.c']
if GetDepend(['RT_USING_QSPI']):
src += ['hc32_ll_driver/src/hc32_ll_qspi.c']
if GetDepend(['RT_USING_CAN']):
src += ['hc32_ll_driver/src/hc32_ll_mcan.c']
if GetDepend(['RT_USING_ADC']):
src += ['hc32_ll_driver/src/hc32_ll_adc.c']
if GetDepend(['RT_USING_DAC']):
src += ['hc32_ll_driver/src/hc32_ll_dac.c']
if GetDepend(['RT_USING_RTC']):
src += ['hc32_ll_driver/src/hc32_ll_rtc.c']
if GetDepend(['RT_USING_WDT']):
src += ['hc32_ll_driver/src/hc32_ll_swdt.c']
src += ['hc32_ll_driver/src/hc32_ll_wdt.c']
if GetDepend(['RT_USING_ON_CHIP_FLASH']):
src += ['hc32_ll_driver/src/hc32_ll_efm.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['hc32_ll_driver/src/hc32_ll_tmr4.c']
src += ['hc32_ll_driver/src/hc32_ll_tmr6.c']
src += ['hc32_ll_driver/src/hc32_ll_tmra.c']
if GetDepend(['RT_USING_PULSE_ENCODER']):
src += ['hc32_ll_driver/src/hc32_ll_tmr6.c']
src += ['hc32_ll_driver/src/hc32_ll_tmra.c']
if GetDepend(['RT_USING_PWM']):
src += ['hc32_ll_driver/src/hc32_ll_tmr4.c']
src += ['hc32_ll_driver/src/hc32_ll_tmr6.c']
src += ['hc32_ll_driver/src/hc32_ll_tmra.c']
if GetDepend(['RT_HWCRYPTO_USING_RNG']):
src += ['hc32_ll_driver/src/hc32_ll_trng.c']
if GetDepend(['RT_HWCRYPTO_USING_CRC']):
src += ['hc32_ll_driver/src/hc32_ll_crc.c']
if GetDepend(['RT_HWCRYPTO_USING_AES']):
src += ['hc32_ll_driver/src/hc32_ll_aes.c']
if GetDepend(['RT_HWCRYPTO_USING_SHA2']):
src += ['hc32_ll_driver/src/hc32_ll_hash.c']
if GetDepend(['BSP_RTC_USING_XTAL32']) or GetDepend(['RT_USING_PM']):
src += ['hc32_ll_driver/src/hc32_ll_fcm.c']
path = [
cwd + '/cmsis/Device/HDSC/hc32f4xx/Include',
cwd + '/cmsis/Include',
cwd + '/hc32_ll_driver/inc',]
CPPDEFINES = ['USE_DDL_DRIVER']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

13622
bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Include/hc32f448.h
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bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h
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/**
*******************************************************************************
* @file hc32f4xx.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2023-05-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4XX_H__
#define __HC32F4XX_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
/**
* @brief HC32F4xx Device Include
*/
#if defined(HC32F448)
#include "hc32f448.h"
#include "system_hc32f448.h"
#else
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4XX_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

140
bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f448.h
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/**
*******************************************************************************
* @file system_hc32f448.h
* @brief This file contains all the functions prototypes of the HC32 System.
@verbatim
Change Logs:
Date Author Notes
2023-05-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __SYSTEM_HC32F448_H__
#define __SYSTEM_HC32F448_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F448_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/**
* @addtogroup HC32F448_System_Global_Macros
* @{
*/
/**
* @addtogroup HC32F448_System_Clock_Source
* @{
*/
#if !defined (MRC_VALUE)
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
#endif
#if !defined (HCLK_VALUE)
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/**
* @addtogroup HC32F448_System_Exported_Variable
* @{
*/
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @}
*/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HC32F448_System_Global_Functions
* @{
*/
extern void SystemInit(void); /*!< Initialize the system */
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
#if defined (ROM_EXT_QSPI)
void SystemInit_QspiMem(void);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_HC32F448_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F448_128K.FLM
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bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F448_256K.FLM
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bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F448_RAM.FLM
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bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F448_otp.FLM
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16
bsp/hc32/libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini
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FUNC void Setup (void) {
SP = _RDWORD(0x1FFE0000);
PC = _RDWORD(0x1FFE0004);
_WDWORD(0xE000ED08, 0x1FFE0000);
}
LOAD .\output\release\efm_chip_erase.axf INCREMENTAL
Setup();
g, main

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