add LPC4330 BSP based on NGX xplorer development board

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2487 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/xplorer4330/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/applications/application.c

@@ -0,0 +1,62 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+
+#ifdef RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+
+#include "board_ngx_xplorer_18304330.h"
+
+static void rt_init_thread_entry(void *parameter)
+{
+    Board_LED_Init();
+
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+    while (1)
+    {
+        Board_LED_Set(0, 1);
+        rt_thread_delay(50);
+        Board_LED_Set(0, 0);
+        rt_thread_delay(50);
+    }
+}
+
+void rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry,
+                           RT_NULL,
+                           2048,
+                           RT_THREAD_PRIORITY_MAX / 3,
+                           20);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+}
+
+/*@}*/

bsp/xplorer4330/applications/startup.c

@@ -0,0 +1,91 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2012-12-11     lgnq         modified for LPC4330
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "platform.h"
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define LPC4300_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define LPC4300_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define LPC4300_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init((void *)LPC4300_SRAM_BEGIN, (void *)(0x10000000 + 1024*128));
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+#ifdef RT_USING_DEVICE
+    /* init all device */
+    rt_device_init_all();
+#endif
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/xplorer4330/drivers/SConscript

@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_SERIAL') == False:
+    SrcRemove(src, 'usart.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/drivers/platform.c

@@ -0,0 +1,64 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-13     lgnq         first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "cmsis.h"
+
+#ifdef RT_USING_SERIAL
+#include "usart.h"
+#endif
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initialize the LPC4330 Xplorer board.
+ */
+void rt_hw_board_init(void)
+{
+    Board_Init();
+
+    /* Configure the SysTick - Generate interrupt @ 100 Hz*/
+    SysTick_Config(Chip_Clock_GetRate(CLK_MX_MXCORE) / 100);
+
+#ifdef RT_USING_SERIAL
+    rt_hw_serial_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+#endif
+}
+
+/*@}*/

bsp/xplorer4330/drivers/platform.h

@@ -0,0 +1,19 @@
+/*
+ * File      : platform.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+void rt_hw_board_init(void);
+
+#endif

bsp/xplorer4330/drivers/usart.c

@@ -0,0 +1,394 @@
+/*
+ * File      : usart.c
+ * mb9bf506r uart driver
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-30     lgnq         first  version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "usart.h"
+#include "uart_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct serial_ringbuffer uart0_int_rx;
+struct uart_device uart0 =
+{
+    LPC_USART0,
+    USART0_IRQn,
+};
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_USART0);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial0);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(RT_USING_UART1)
+/* UART1 device driver structure */
+struct serial_ringbuffer uart1_int_rx;
+struct uart_device uart1 =
+{
+    LPC_UART1,
+    USART1_IRQn,
+};
+struct rt_serial_device serial1;
+
+void UART1_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_UART1);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial1);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(RT_USING_UART2)
+/* UART2 device driver structure */
+struct serial_ringbuffer uart2_int_rx;
+struct uart_device uart2 =
+{
+    LPC_USART2,
+    USART2_IRQn,
+};
+struct rt_serial_device serial2;
+
+void UART2_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_USART2);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial2);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(RT_USING_UART3)
+/* UART3 device driver structure */
+struct serial_ringbuffer uart3_int_rx;
+struct uart_device uart3 =
+{
+    LPC_USART3,
+    USART3_IRQn,
+};
+struct rt_serial_device serial3;
+
+void UART3_IRQHandler(void)
+{
+    UART_Int_Status status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = Chip_UART_GetIntStatus(LPC_USART3);
+
+    /* error */
+    if (status == UART_ERROR)
+    {
+        return;
+    }
+
+    /* ready for Read Data */
+    if (status & READY_TO_RECEIVE)
+    {
+        rt_hw_serial_isr(&serial3);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+void uart_pin_setup(void)
+{
+#if defined(RT_USING_UART0)
+    Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2);                   /* P6.5 : UART0_TXD */
+    Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);  /* P6.4 : UART0_RXD */
+#endif
+
+#if defined(RT_USING_UART1)
+    Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2);                  /* P1.13 : UART1_TXD */
+    Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P1.14 : UART1_RX */
+#endif
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct uart_device *uart;
+    UART_DATABIT_Type   databit;
+    UART_STOPBIT_Type   stopbit;
+    UART_PARITY_Type    parity;
+
+    /* UART FIFO configuration Struct variable */
+    UART_FIFO_CFG_Type UARTFIFOConfigStruct;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    Chip_UART_Init(uart->uart_regs);
+
+    Chip_UART_SetBaud(uart->uart_regs, cfg->baud_rate);
+
+    /* set stop bits */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        stopbit = UART_STOPBIT_1;
+        break;
+    case STOP_BITS_2:
+        stopbit = UART_STOPBIT_2;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    /* set data bits */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        databit = UART_DATABIT_5;
+        break;
+    case DATA_BITS_6:
+        databit = UART_DATABIT_6;
+        break;
+    case DATA_BITS_7:
+        databit = UART_DATABIT_7;
+        break;
+    case DATA_BITS_8:
+        databit = UART_DATABIT_8;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    /* set parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        parity = UART_PARITY_NONE;
+        break;
+    case PARITY_EVEN:
+        parity = UART_PARITY_EVEN;
+        break;
+    case PARITY_ODD:
+        parity = UART_PARITY_ODD;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    Chip_UART_ConfigData(uart->uart_regs, databit, parity, stopbit);
+
+    /* Enable UART Transmit */
+    Chip_UART_TxCmd(uart->uart_regs, ENABLE);
+
+    Chip_UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
+
+    /* Enable DMA mode in UART */
+    UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE;
+    /* Initialize FIFO for UART0 peripheral */
+    Chip_UART_FIFOConfig(uart->uart_regs, &UARTFIFOConfigStruct);
+
+    /* Enable UART Rx interrupt */
+    Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RBR, ENABLE);
+    /* Enable UART line status interrupt */
+    Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RLS, ENABLE);
+
+    /* Enable Interrupt for UART channel */
+    /* Priority = 1 */
+    NVIC_SetPriority(uart->irq_num, 1);
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_DISABLE_IRQ(uart->irq_num);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_ENABLE_IRQ(uart->irq_num);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    /* wait send buffer is empty */
+    while (!(uart->uart_regs->LSR & UART_LSR_THRE))
+        ;
+    /* write to send buffer */
+    uart->uart_regs->THR = c & UART_THR_MASKBIT;
+
+    return (1);
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    struct uart_device *uart;
+    uint8_t ch;
+
+    RT_ASSERT(serial != RT_NULL);
+    
+    uart = (struct uart_device *)serial->parent.user_data;
+
+    /* receive buffer is full */
+    if (uart->uart_regs->LSR & UART_LSR_RDR)
+    {
+        ch = uart->uart_regs->RBR & UART_RBR_MASKBIT;
+
+        return (ch);
+    }
+    else
+        return (-1);
+}
+
+static struct rt_uart_ops uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+void rt_hw_serial_init(void)
+{
+    struct serial_configure config;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+
+    uart_pin_setup();
+
+#if defined(RT_USING_UART0)
+    serial0.ops    = &uart_ops;
+    serial0.int_rx = &uart0_int_rx;
+    serial0.config = config;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0,
+                          "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+#endif
+
+#if defined(RT_USING_UART1)
+    serial1.ops    = &uart_ops;
+    serial1.int_rx = &uart1_int_rx;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart1);
+#endif
+
+#if defined(RT_USING_UART2)
+    serial2.ops    = &uart_ops;
+    serial2.int_rx = &uart2_int_rx;
+    serial2.config = config;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2,
+                          "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart2);
+#endif
+
+#if defined(RT_USING_UART3)
+    serial3.ops    = &uart_ops;
+    serial3.int_rx = &uart3_int_rx;
+    serial3.config = config;
+
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3,
+                          "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart3);
+#endif
+}

bsp/xplorer4330/drivers/usart.h

@@ -0,0 +1,39 @@
+/*
+ * File      : usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include <rtthread.h>
+
+#include "chip_lpc43xx.h"
+#include "cmsis.h"
+
+/**
+ *  Enable/DISABLE Interrupt Controller
+ */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct uart_device
+{
+    LPC_USART_Type *uart_regs;
+
+    /* irq number */
+    IRQn_Type irq_num;
+};
+
+void rt_hw_serial_init(void);
+
+#endif

bsp/xplorer4330/libraries/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/xplorer4330/libraries/lpc_board/SConscript

@@ -0,0 +1,44 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+#src = Glob('board_common/*.c')
+src  = []
+path = [cwd + '/board_common']
+
+if rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_4330':
+    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
+             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
+    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
+             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330']
+elif rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_1830':
+    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
+             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
+    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
+             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830']
+elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_4357':
+    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
+             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
+    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
+             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357']
+elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_1857':
+    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
+             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
+    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
+             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857']
+elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_4350':
+    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
+             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
+    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
+             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350']
+elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_1850':
+    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
+             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
+    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
+             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850']
+
+group = DefineGroup('lpc_board', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_board/board_common/Retarget.c

@@ -0,0 +1,253 @@
+/*
+ * @brief	IO redirection support
+ *
+ * This file adds re-direction support to the library for various
+ * projects. It can be configured in one of 3 ways - no redirection,
+ * redirection via a UART, or redirection via semihosting. If DEBUG
+ * is not defined, all printf statements will do nothing with the
+ * output being throw away. If DEBUG is defined, then the choice of
+ * output is selected by the DEBUG_SEMIHOSTING define. If the
+ * DEBUG_SEMIHOSTING is not defined, then output is redirected via
+ * the UART. If DEBUG_SEMIHOSTING is defined, then output will be
+ * attempted to be redirected via semihosting. If the UART method
+ * is used, then the Board_UARTPutChar and Board_UARTGetChar
+ * functions must be defined to be used by this driver and the UART
+ * must already be initialized to the correct settings.
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "sys_config.h"
+#include "board.h"
+
+/* Keil (Realview) support */
+#if defined(__CC_ARM)
+
+#include <stdio.h>
+#include <rt_misc.h>
+
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#define ITM_Port8(n)    (*((volatile unsigned char *) (0xE0000000 + 4 * n)))
+#define ITM_Port16(n)   (*((volatile unsigned short *) (0xE0000000 + 4 * n)))
+#define ITM_Port32(n)   (*((volatile unsigned long *) (0xE0000000 + 4 * n)))
+
+#define DEMCR           (*((volatile unsigned long *) (0xE000EDFC)))
+#define TRCENA          0x01000000
+
+/* Write to SWO */
+void _ttywrch(int ch)
+{
+	if (DEMCR & TRCENA) {
+		while (ITM_Port32(0) == 0) {}
+		ITM_Port8(0) = ch;
+	}
+}
+
+#else
+static INLINE void BoardOutChar(char ch)
+{
+	Board_UARTPutChar(ch);
+}
+
+#endif /* defined(DEBUG_SEMIHOSTING) */
+#endif /* defined(DEBUG) */
+
+struct __FILE {
+	int handle;
+};
+
+FILE __stdout;
+FILE __stdin;
+FILE __stderr;
+
+void *_sys_open(const char *name, int openmode)
+{
+	return 0;
+}
+
+int fputc(int c, FILE *f)
+{
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+	_ttywrch(c);
+#else
+	BoardOutChar((char) c);
+#endif
+#endif
+	return 0;
+}
+
+int fgetc(FILE *f)
+{
+#if defined(DEBUG) && !defined(DEBUG_SEMIHOSTING)
+	return Board_UARTGetChar();
+#else
+	return 0;
+#endif
+}
+
+int ferror(FILE *f)
+{
+	return EOF;
+}
+
+void _sys_exit(int return_code)
+{
+label:  goto label;	/* endless loop */
+}
+
+#endif /* defined (__CC_ARM) */
+
+/* IAR support */
+#if defined(__ICCARM__)
+/*******************
+ *
+ * Copyright 1998-2003 IAR Systems.  All rights reserved.
+ *
+ * $Revision: 30870 $
+ *
+ * This is a template implementation of the "__write" function used by
+ * the standard library.  Replace it with a system-specific
+ * implementation.
+ *
+ * The "__write" function should output "size" number of bytes from
+ * "buffer" in some application-specific way.  It should return the
+ * number of characters written, or _LLIO_ERROR on failure.
+ *
+ * If "buffer" is zero then __write should perform flushing of
+ * internal buffers, if any.  In this case "handle" can be -1 to
+ * indicate that all handles should be flushed.
+ *
+ * The template implementation below assumes that the application
+ * provides the function "MyLowLevelPutchar".  It should return the
+ * character written, or -1 on failure.
+ *
+ ********************/
+
+#include <yfuns.h>
+
+_STD_BEGIN
+
+#pragma module_name = "?__write"
+
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#error Semihosting support not yet working on IAR
+#endif /* defined(DEBUG_SEMIHOSTING) */
+#endif /* defined(DEBUG) */
+
+/*
+   If the __write implementation uses internal buffering, uncomment
+   the following line to ensure that we are called with "buffer" as 0
+   (i.e. flush) when the application terminates. */
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+#if defined(DEBUG)
+	size_t nChars = 0;
+
+	if (buffer == 0) {
+		/*
+		   This means that we should flush internal buffers.  Since we
+		   don't we just return.  (Remember, "handle" == -1 means that all
+		   handles should be flushed.)
+		 */
+		return 0;
+	}
+
+	/* This template only writes to "standard out" and "standard err",
+	   for all other file handles it returns failure. */
+	if (( handle != _LLIO_STDOUT) && ( handle != _LLIO_STDERR) ) {
+		return _LLIO_ERROR;
+	}
+
+	for ( /* Empty */; size != 0; --size) {
+		Board_UARTPutChar(*buffer++);
+		++nChars;
+	}
+
+	return nChars;
+#else
+	return size;
+#endif /* defined(DEBUG) */
+}
+
+_STD_END
+
+#endif /* defined (__ICCARM__) */
+
+#if defined( __GNUC__ )
+/* Include stdio.h to pull in __REDLIB_INTERFACE_VERSION__ */
+#include <stdio.h>
+
+#if (__REDLIB_INTERFACE_VERSION__ >= 20000)
+/* We are using new Redlib_v2 semihosting interface */
+	#define WRITEFUNC __sys_write
+	#define READFUNC __sys_readc
+#else
+/* We are using original Redlib semihosting interface */
+	#define WRITEFUNC __write
+	#define READFUNC __readc
+#endif
+
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+/* Do nothing, semihosting is enabled by default in LPCXpresso */
+#endif /* defined(DEBUG_SEMIHOSTING) */
+#endif /* defined(DEBUG) */
+
+#if !defined(DEBUG_SEMIHOSTING)
+int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength)
+{
+#if defined(DEBUG)
+	unsigned int i;
+	for (i = 0; i < iLength; i++) {
+		Board_UARTPutChar(pcBuffer[i]);
+	}
+#endif
+
+	return iLength;
+}
+
+/* Called by bottom level of scanf routine within RedLib C library to read
+   a character. With the default semihosting stub, this would read the character
+   from the debugger console window (which acts as stdin). But this version reads
+   the character from the LPC1768/RDB1768 UART. */
+int READFUNC(void)
+{
+#if defined(DEBUG)
+	char c = Board_UARTGetChar();
+	return (int) c;
+
+#else
+	return (int) -1;
+#endif
+}
+
+#endif /* !defined(DEBUG_SEMIHOSTING) */
+#endif /* defined ( __GNUC__ ) */

bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h

@@ -0,0 +1,176 @@
+/*
+ * @brief Common board API functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_API_H_
+#define __BOARD_API_H_
+
+#include "lpc_types.h"
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_COMMON_API BOARD: Common board functions
+ * @ingroup BOARD_Common
+ * This file contains common board definitions that are shared across
+ * boards and devices. All of these functions do not need to be
+ * impemented for a specific board, but if they are implemented, they
+ * should use this API standard.
+ * @{
+ */
+
+/**
+ * @brief	Set up and initialize all required blocks and functions related to the board hardware.
+ * @return	None
+ */
+void Board_Init(void);
+
+/**
+ * @brief	Initializes board UART for output, required for printf redirection
+ * @return	None
+ */
+void Board_Debug_Init(void);
+
+/**
+ * @brief	Sends a single character on the UART, required for printf redirection
+ * @param	ch	: character to send
+ * @return	None
+ */
+void Board_UARTPutChar(char ch);
+
+/**
+ * @brief	Get a single character from the UART, required for scanf input
+ * @return	EOF if not character was received, or character value
+ */
+int Board_UARTGetChar(void);
+
+/**
+ * @brief	Prints a string to the UART
+ * @param	str	: Terminated string to output
+ * @return	None
+ */
+void Board_UARTPutSTR(char *str);
+
+/**
+ * @brief	Initializes board LED(s)
+ * @return	None
+ */
+void Board_LED_Init(void);
+
+/**
+ * @brief	Sets the state of a board LED to on or off
+ * @param	LEDNumber	: LED number to set state for
+ * @param	State		: true for on, false for off
+ * @return	None
+ */
+void Board_LED_Set(uint8_t LEDNumber, bool State);
+
+/**
+ * @brief	Returns the current state of a board LED
+ * @param	LEDNumber	: LED number to set state for
+ * @return	true if the LED is on, otherwise false
+ */
+bool Board_LED_Test(uint8_t LEDNumber);
+
+/**
+ * @brief	Toggles the current state of a board LED
+ * @param	LEDNumber	: LED number to change state for
+ * @return	None
+ */
+STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)
+{
+	Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));
+}
+
+
+/**
+ * @brief	Current system clock rate, mainly used for sysTick
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	Turn on Board LCD Backlight
+ * @param	Intensity	: Backlight intensity (0 = off, >=1 = on)
+ * @return	None
+ * On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
+ * value will turn off or on the backlight. On some boards, a non-0 value will
+ * control backlight intensity via a PWN. For PWM systems, the intensity value
+ * is a percentage value between 0 and 100%.
+ */
+void Board_LCD_Set_Backlight(uint8_t Intensity);
+
+/**
+ * @brief Function prototype for a MS delay function. Board layers or example code may
+ *        define this function as needed.
+ */
+typedef void (*p_msDelay_func_t)(uint32_t);
+
+/* The DEBUG* functions are selected based on system configuration.
+   Code that uses the DEBUG* functions will have their I/O routed to
+   the UART, semihosting, or nowhere. */
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#define DEBUGINIT()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) printf(str)
+#define DEBUGIN() (int) EOF
+
+#else
+#define DEBUGINIT() Board_Debug_Init()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) Board_UARTPutSTR(str)
+#define DEBUGIN() Board_UARTGetChar()
+#endif /* defined(DEBUG_SEMIHOSTING) */
+
+#else
+#define DEBUGINIT()
+#define DEBUGOUT(...)
+#define DEBUGSTR(str)
+#define DEBUGIN() (int) EOF
+#endif /* defined(DEBUG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_API_H_ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h

@@ -0,0 +1,90 @@
+/*
+ * @brief Common PHY functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_PHY_H_
+#define __LPC_PHY_H_
+
+#include "board.h"
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers
+ * @ingroup BOARD_Common
+ * The simple PHY function API provides simple non-blocking PHY status
+ * monitoring and initialization support for various Ethernet PHYs.
+ * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires
+ * several standard functions from the MAC driver for interfacing to the
+ * PHY via a MII link (Chip_ENET_Start_MII_Write(), Chip_ENET_Is_MII_Busy(),
+ * Chip_ENET_Start_MII_Read(), and Chip_ENET_Read_MII_Data()).
+ *
+ * Once initialized, just preiodically call the lpcPHYStsPoll() function
+ * from the background loop or a thread and monitor the returned status
+ * to determine if the PHY state has changed and the current PHY state.
+ * @{
+ */
+#define PHY_LINK_ERROR     (1 << 0)	/*!< PHY status bit for link error */
+#define PHY_LINK_BUSY      (1 << 1)	/*!< PHY status bit for MII link busy */
+#define PHY_LINK_CHANGED   (1 << 2)	/*!< PHY status bit for changed state (not persistent) */
+#define PHY_LINK_CONNECTED (1 << 3)	/*!< PHY status bit for connected state */
+#define PHY_LINK_SPEED100  (1 << 4)	/*!< PHY status bit for 100Mbps mode */
+#define PHY_LINK_FULLDUPLX (1 << 5)	/*!< PHY status bit for full duplex mode */
+
+/**
+ * @brief	Phy status update state machine
+ * @return	An Or'ed value of PHY_LINK_* statuses
+ * This function can be called at any rate and will poll the the PHY status. Multiple
+ * calls may be needed to determine PHY status.
+ */
+uint32_t lpcPHYStsPoll(void);
+
+/**
+ * @brief	Initialize the PHY
+ * @param	rmii			: Initializes PHY for RMII mode if true, MII if false
+ * @param	pDelayMsFunc	: Delay function (in mS) used for this driver
+ * @return	PHY_LINK_ERROR or 0 on success
+ * This function initializes the PHY. It will block until complete. It will not
+ * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to
+ * detect cable insertion.
+ */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC_PHY_H_ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c

@@ -0,0 +1,281 @@
+/*
+ * @brief Mational DP83848 simple PHY driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+#include "lpc_phy.h"
+
+/** @defgroup DP83848_PHY	BOARD: PHY status and control driver for the DP83848
+ * @ingroup BOARD_PHY
+ * Various functions for controlling and monitoring the status of the
+ * DP83848 PHY.
+ * @{
+ */
+
+/** @brief  DP83848 PHY register offsets */
+#define DP8_BMCR_REG        0x0	/*!< Basic Mode Control Register */
+#define DP8_BMSR_REG        0x1	/*!< Basic Mode Status Reg */
+#define DP8_ANADV_REG       0x4	/*!< Auto_Neg Advt Reg  */
+#define DP8_ANLPA_REG       0x5	/*!< Auto_neg Link Partner Ability Reg */
+#define DP8_ANEEXP_REG      0x6	/*!< Auto-neg Expansion Reg  */
+#define DP8_PHY_STAT_REG    0x10/*!< PHY Status Register  */
+#define DP8_PHY_INT_CTL_REG 0x11/*!< PHY Interrupt Control Register */
+#define DP8_PHY_RBR_REG     0x17/*!< PHY RMII and Bypass Register  */
+#define DP8_PHY_STS_REG     0x19/*!< PHY Status Register  */
+
+/* DP83848 Control register definitions */
+#define DP8_RESET          (1 << 15)	/*!< 1= S/W Reset */
+#define DP8_LOOPBACK       (1 << 14)	/*!< 1=loopback Enabled */
+#define DP8_SPEED_SELECT   (1 << 13)	/*!< 1=Select 100MBps */
+#define DP8_AUTONEG        (1 << 12)	/*!< 1=Enable auto-negotiation */
+#define DP8_POWER_DOWN     (1 << 11)	/*!< 1=Power down PHY */
+#define DP8_ISOLATE        (1 << 10)	/*!< 1=Isolate PHY */
+#define DP8_RESTART_AUTONEG (1 << 9)	/*!< 1=Restart auto-negoatiation */
+#define DP8_DUPLEX_MODE    (1 << 8)		/*!< 1=Full duplex mode */
+#define DP8_COLLISION_TEST (1 << 7)		/*!< 1=Perform collsion test */
+
+/* DP83848 Status register definitions */
+#define DP8_100BASE_T4     (1 << 15)	/*!< T4 mode */
+#define DP8_100BASE_TX_FD  (1 << 14)	/*!< 100MBps full duplex */
+#define DP8_100BASE_TX_HD  (1 << 13)	/*!< 100MBps half duplex */
+#define DP8_10BASE_T_FD    (1 << 12)	/*!< 100Bps full duplex */
+#define DP8_10BASE_T_HD    (1 << 11)	/*!< 10MBps half duplex */
+#define DP8_MF_PREAMB_SUPPR (1 << 6)	/*!< Preamble suppress */
+#define DP8_AUTONEG_COMP   (1 << 5)		/*!< Auto-negotation complete */
+#define DP8_RMT_FAULT      (1 << 4)		/*!< Fault */
+#define DP8_AUTONEG_ABILITY (1 << 3)	/*!< Auto-negotation supported */
+#define DP8_LINK_STATUS    (1 << 2)		/*!< 1=Link active */
+#define DP8_JABBER_DETECT  (1 << 1)		/*!< Jabber detect */
+#define DP8_EXTEND_CAPAB   (1 << 0)		/*!< Supports extended capabilities */
+
+/* DP83848 PHY RBR MII dode definitions */
+#define DP8_RBR_RMII_MODE  (1 << 5)		/*!< Use RMII mode */
+
+/* DP83848 PHY status definitions */
+#define DP8_REMOTEFAULT    (1 << 6)		/*!< Remote fault */
+#define DP8_FULLDUPLEX     (1 << 2)		/*!< 1=full duplex */
+#define DP8_SPEED10MBPS    (1 << 1)		/*!< 1=10MBps speed */
+#define DP8_VALID_LINK     (1 << 0)		/*!< 1=Link active */
+
+/* DP83848 PHY ID register definitions */
+#define DP8_PHYID1_OUI     0x2000		/*!< Expected PHY ID1 */
+#define DP8_PHYID2_OUI     0x5c90		/*!< Expected PHY ID2 */
+
+/* DP83848 PHY update flags */
+static uint32_t physts, olddphysts;
+
+/* PHY update counter for state machine */
+static int32_t phyustate;
+
+/* Pointer to delay function used for this driver */
+static p_msDelay_func_t pDelayMs;
+
+/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_write(uint8_t reg, uint16_t data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Write value for register */
+	Chip_ENET_Start_MII_Write(reg, data);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (Chip_ENET_Is_MII_Busy()) {
+			mst--;
+			pDelayMs(1);
+		}
+		else {
+			mst = 0;
+			sts = SUCCESS;
+		}
+	}
+
+	return sts;
+}
+
+/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_read(uint8_t reg, uint16_t *data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Start register read */
+	Chip_ENET_Start_MII_Read(reg);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (!Chip_ENET_Is_MII_Busy()) {
+			mst = 0;
+			*data = Chip_ENET_Read_MII_Data();
+			sts = SUCCESS;
+		}
+		else {
+			mst--;
+			pDelayMs(1);
+		}
+	}
+
+	return sts;
+}
+
+/* Update PHY status from passed value */
+static void lpc_update_phy_sts(uint16_t linksts)
+{
+	/* Update link active status */
+	if (linksts & DP8_VALID_LINK) {
+		physts |= PHY_LINK_CONNECTED;
+	}
+	else {
+		physts &= ~PHY_LINK_CONNECTED;
+	}
+
+	/* Full or half duplex */
+	if (linksts & DP8_FULLDUPLEX) {
+		physts |= PHY_LINK_FULLDUPLX;
+	}
+	else {
+		physts &= ~PHY_LINK_FULLDUPLX;
+	}
+
+	/* Configure 100MBit/10MBit mode. */
+	if (linksts & DP8_SPEED10MBPS) {
+		physts &= ~PHY_LINK_SPEED100;
+	}
+	else {
+		physts |= PHY_LINK_SPEED100;
+	}
+
+	/* If the status has changed, indicate via change flag */
+	if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
+		(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
+		olddphysts = physts;
+		physts |= PHY_LINK_CHANGED;
+	}
+}
+
+/* Initialize the DP83848 PHY */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
+{
+	uint16_t tmp;
+	int32_t i;
+
+	pDelayMs = pDelayMsFunc;
+
+	/* Initial states for PHY status and state machine */
+	olddphysts = physts = phyustate = 0;
+
+	/* Only first read and write are checked for failure */
+	/* Put the DP83848C in reset mode and wait for completion */
+	if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != SUCCESS) {
+		return ERROR;
+	}
+	i = 400;
+	while (i > 0) {
+		pDelayMs(1);
+		if (lpc_mii_read(DP8_BMCR_REG, &tmp) != SUCCESS) {
+			return ERROR;
+		}
+
+		if (!(tmp & (DP8_RESET | DP8_POWER_DOWN))) {
+			i = -1;
+		}
+		else {
+			i--;
+		}
+	}
+	/* Timeout? */
+	if (i == 0) {
+		return ERROR;
+	}
+
+#if 0
+	/* Setup link based on configuration options */
+#if PHY_USE_AUTONEG == 1
+	tmp = DP8_AUTONEG;
+#else
+	tmp = 0;
+#endif
+#if PHY_USE_100MBS == 1
+	tmp |= DP8_SPEED_SELECT;
+#endif
+#if PHY_USE_FULL_DUPLEX == 1
+	tmp |= DP8_DUPLEX_MODE;
+#endif
+
+#else
+	tmp = DP8_AUTONEG;
+#endif
+
+	lpc_mii_write(DP8_BMCR_REG, tmp);
+
+	/* Enable RMII mode for PHY */
+	if (rmii) {
+		lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
+	}
+
+	/* The link is not set active at this point, but will be detected
+	   later */
+
+	return SUCCESS;
+}
+
+/* Phy status update state machine */
+uint32_t lpcPHYStsPoll(void)
+{
+	switch (phyustate) {
+	default:
+	case 0:
+		/* Read BMSR to clear faults */
+		Chip_ENET_Start_MII_Read(DP8_PHY_STAT_REG);
+		physts &= ~PHY_LINK_CHANGED;
+		physts = physts | PHY_LINK_BUSY;
+		phyustate = 1;
+		break;
+
+	case 1:
+		/* Wait for read status state */
+		if (!Chip_ENET_Is_MII_Busy()) {
+			/* Update PHY status */
+			physts &= ~PHY_LINK_BUSY;
+			lpc_update_phy_sts(Chip_ENET_Read_MII_Data());
+			phyustate = 0;
+		}
+		break;
+	}
+
+	return physts;
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c

@@ -0,0 +1,270 @@
+/*
+ * @brief SMSC 87x0 simple PHY driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+#include "lpc_phy.h"
+
+/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0
+ * @ingroup BOARD_PHY
+ * Various functions for controlling and monitoring the status of the
+ * SMSC 87x0 PHY.
+ * @{
+ */
+
+/* LAN8720 PHY register offsets */
+#define LAN8_BCR_REG        0x0	/*!< Basic Control Register */
+#define LAN8_BSR_REG        0x1	/*!< Basic Status Reg */
+#define LAN8_PHYID1_REG     0x2	/*!< PHY ID 1 Reg  */
+#define LAN8_PHYID2_REG     0x3	/*!< PHY ID 2 Reg */
+#define LAN8_PHYSPLCTL_REG  0x1F/*!< PHY special control/status Reg */
+
+/* LAN8720 BCR register definitions */
+#define LAN8_RESET          (1 << 15)	/*!< 1= S/W Reset */
+#define LAN8_LOOPBACK       (1 << 14)	/*!< 1=loopback Enabled */
+#define LAN8_SPEED_SELECT   (1 << 13)	/*!< 1=Select 100MBps */
+#define LAN8_AUTONEG        (1 << 12)	/*!< 1=Enable auto-negotiation */
+#define LAN8_POWER_DOWN     (1 << 11)	/*!< 1=Power down PHY */
+#define LAN8_ISOLATE        (1 << 10)	/*!< 1=Isolate PHY */
+#define LAN8_RESTART_AUTONEG (1 << 9)	/*!< 1=Restart auto-negoatiation */
+#define LAN8_DUPLEX_MODE    (1 << 8)	/*!< 1=Full duplex mode */
+
+/* LAN8720 BSR register definitions */
+#define LAN8_100BASE_T4     (1 << 15)	/*!< T4 mode */
+#define LAN8_100BASE_TX_FD  (1 << 14)	/*!< 100MBps full duplex */
+#define LAN8_100BASE_TX_HD  (1 << 13)	/*!< 100MBps half duplex */
+#define LAN8_10BASE_T_FD    (1 << 12)	/*!< 100Bps full duplex */
+#define LAN8_10BASE_T_HD    (1 << 11)	/*!< 10MBps half duplex */
+#define LAN8_AUTONEG_COMP   (1 << 5)	/*!< Auto-negotation complete */
+#define LAN8_RMT_FAULT      (1 << 4)	/*!< Fault */
+#define LAN8_AUTONEG_ABILITY (1 << 3)	/*!< Auto-negotation supported */
+#define LAN8_LINK_STATUS    (1 << 2)	/*!< 1=Link active */
+#define LAN8_JABBER_DETECT  (1 << 1)	/*!< Jabber detect */
+#define LAN8_EXTEND_CAPAB   (1 << 0)	/*!< Supports extended capabilities */
+
+/* LAN8720 PHYSPLCTL status definitions */
+#define LAN8_SPEEDMASK      (7 << 2)	/*!< Speed and duplex mask */
+#define LAN8_SPEED100F      (6 << 2)	/*!< 100BT full duplex */
+#define LAN8_SPEED10F       (5 << 2)	/*!< 10BT full duplex */
+#define LAN8_SPEED100H      (2 << 2)	/*!< 100BT half duplex */
+#define LAN8_SPEED10H       (1 << 2)	/*!< 10BT half duplex */
+
+/* LAN8720 PHY ID 1/2 register definitions */
+#define LAN8_PHYID1_OUI     0x0007		/*!< Expected PHY ID1 */
+#define LAN8_PHYID2_OUI     0xC0F0		/*!< Expected PHY ID2, except last 4 bits */
+
+/* DP83848 PHY update flags */
+static uint32_t physts, olddphysts;
+
+/* PHY update counter for state machine */
+static int32_t phyustate;
+
+/* Pointer to delay function used for this driver */
+static p_msDelay_func_t pDelayMs;
+
+/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_write(uint8_t reg, uint16_t data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Write value for register */
+	Chip_ENET_Start_MII_Write(reg, data);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (Chip_ENET_Is_MII_Busy()) {
+			mst--;
+			pDelayMs(1);
+		}
+		else {
+			mst = 0;
+			sts = SUCCESS;
+		}
+	}
+
+	return sts;
+}
+
+/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
+   true on success, or false on failure */
+static Status lpc_mii_read(uint8_t reg, uint16_t *data)
+{
+	Status sts = ERROR;
+	int32_t mst = 250;
+
+	/* Start register read */
+	Chip_ENET_Start_MII_Read(reg);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if (!Chip_ENET_Is_MII_Busy()) {
+			mst = 0;
+			*data = Chip_ENET_Read_MII_Data();
+			sts = SUCCESS;
+		}
+		else {
+			mst--;
+			pDelayMs(1);
+		}
+	}
+
+	return sts;
+}
+
+/* Update PHY status from passed value */
+static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts)
+{
+	/* Update link active status */
+	if (linksts & LAN8_LINK_STATUS) {
+		physts |= PHY_LINK_CONNECTED;
+	}
+	else {
+		physts &= ~PHY_LINK_CONNECTED;
+	}
+
+	switch (sdsts & LAN8_SPEEDMASK) {
+	case LAN8_SPEED100F:
+	default:
+		physts |= PHY_LINK_SPEED100;
+		physts |= PHY_LINK_FULLDUPLX;
+		break;
+
+	case LAN8_SPEED10F:
+		physts &= ~PHY_LINK_SPEED100;
+		physts |= PHY_LINK_FULLDUPLX;
+		break;
+
+	case LAN8_SPEED100H:
+		physts |= PHY_LINK_SPEED100;
+		physts &= ~PHY_LINK_FULLDUPLX;
+		break;
+
+	case LAN8_SPEED10H:
+		physts &= ~PHY_LINK_SPEED100;
+		physts &= ~PHY_LINK_FULLDUPLX;
+		break;
+	}
+
+	/* If the status has changed, indicate via change flag */
+	if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
+		(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
+		olddphysts = physts;
+		physts |= PHY_LINK_CHANGED;
+	}
+}
+
+/* Initialize the SMSC 87x0 PHY */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
+{
+	uint16_t tmp;
+	int32_t i;
+
+	pDelayMs = pDelayMsFunc;
+
+	/* Initial states for PHY status and state machine */
+	olddphysts = physts = phyustate = 0;
+
+	/* Only first read and write are checked for failure */
+	/* Put the DP83848C in reset mode and wait for completion */
+	if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) {
+		return ERROR;
+	}
+	i = 400;
+	while (i > 0) {
+		pDelayMs(1);
+		if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) {
+			return ERROR;
+		}
+
+		if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) {
+			i = -1;
+		}
+		else {
+			i--;
+		}
+	}
+	/* Timeout? */
+	if (i == 0) {
+		return ERROR;
+	}
+
+	/* Setup link */
+	lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG);
+
+	/* The link is not set active at this point, but will be detected
+	   later */
+
+	return SUCCESS;
+}
+
+/* Phy status update state machine */
+uint32_t lpcPHYStsPoll(void)
+{
+	static uint16_t sts;
+
+	switch (phyustate) {
+	default:
+	case 0:
+		/* Read BMSR to clear faults */
+		Chip_ENET_Start_MII_Read(LAN8_BSR_REG);
+		physts &= ~PHY_LINK_CHANGED;
+		physts = physts | PHY_LINK_BUSY;
+		phyustate = 1;
+		break;
+
+	case 1:
+		/* Wait for read status state */
+		if (!Chip_ENET_Is_MII_Busy()) {
+			/* Get PHY status with link state */
+			sts = Chip_ENET_Read_MII_Data();
+			Chip_ENET_Start_MII_Read(LAN8_PHYSPLCTL_REG);
+			phyustate = 2;
+		}
+		break;
+
+	case 2:
+		/* Wait for read status state */
+		if (!Chip_ENET_Is_MII_Busy()) {
+			/* Update PHY status */
+			physts &= ~PHY_LINK_BUSY;
+			smsc_update_phy_sts(sts, Chip_ENET_Read_MII_Data());
+			phyustate = 0;
+		}
+		break;
+	}
+
+	return physts;
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox

@@ -0,0 +1,62 @@
+/*
+ * @brief LPCOpen 18xx/43xx board support page
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+/** @defgroup BOARDS_18XX_43XX BOARD: LPC18XX and LPC43XX boards
+ * @ingroup Board_Layer
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/*!
+ * @page LPCOPEN_BSP_18XX43XX Supported 18xx/43xx platforms
+ *
+ * <b>Device Support</b><br/>
+ * All LPC18xx and LPC43xx device variants are supported.<br/><br/>
+ * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=103">LPC18xx documentation links</a><br/>
+ * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=104">LPC43xx documentation links</a><br/><br/>
+ * <b>Board Support</b><br/>
+ * Hitex, Keil, and NGX boards for both 18xx and 43xx variants are supported.
+ * Click <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco">here</a> for LPCOpen build procedures and default jumper configuration for supported boards.<br/><br/>
+ * <a href="http://www.hitex.com/index.php?id=3455/">Hitex LPC1857 and LPC4357 evaluation boards </a><br/>
+ * <a href="http://www.keil.com/mcb1800/">Keil MCB1800</a> and <a href="http://www.keil.com/mcb4300/">Keil MCB4300 boards</a><br/>
+ * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC1830-Xplorer_Quick_Start_Guide">NGX LPC1830 Xplorer</a> and 
+ * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC4330-Xplorer_Quick_Start_Guide">NGX LPC4330 Xplorer boards</a><br/>
+ *
+ * <b>Toolchain Support</b><br/>
+ * Code Red Xpresso, IAR EWARM, and Keil MDK are all supported. See the <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco#Supported_toolchains">build support pages</a>
+ * for information on specific versions of the toolchains tested with the LPCOpen platform.<br/><br/>
+ * <a href="http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/">IAR EWARM</a><br/>
+ * <a href="http://www.keil.com/arm/mdk.asp">ARM MDK-ARM</a><br/>
+ * <a href="http://code-red-tech.com/lpcxpresso">LPCXpresso</a>
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief Hitex EVA 1850/4350 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_hitex_eva_18504350.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h

@@ -0,0 +1,244 @@
+/*
+ * @brief Hitex EVA 1850/4350 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_HITEX_EVA_18504350_H_
+#define __BOARD_HITEX_EVA_18504350_H_
+
+#include "chip.h"
+#include "board_api.h"
+#include "lpc_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_HITEX_EVA_18504350 LPC1850 and LPC4350 Hitex EVA board support functions
+ * @ingroup BOARDS_18XX_43XX
+ * @{
+ */
+
+/** @defgroup BOARD_HITEX_EVA_18504350_OPTIONS BOARD: LPC1850 and LPC4350 Hitex EVA board builds options
+ * The NGX board has options that configure it's operation at build-time.<br/>
+ * CHIP_LPC*
+ *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
+ * DEBUG:<br/>
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
+ * DEBUG_UART:<br/>
+ *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
+ * CRYSTAL_MAIN_FREQ_IN:<br/>
+ *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
+ * CRYSTAL_32K_FREQ_IN:<br/>
+ *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
+ * EXTERNAL_CLKIN_FREQ_IN:<br/>
+ *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
+ * MAX_CLOCK_FREQ:<br/>
+ *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
+ *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
+ * USE_RMII:<br/>
+ *  - When defined, the system will be configured for RMII mode for Ethernet<br/>
+ *  - When not defined, the system will be configured for MII mode for Ethernet<br/><p>
+ * BOARD_HITEX_EVA_18504350:<br/>
+ *  - When building for Hitex boards, BOARD_HITEX_EVA_18504350 is defined<br/>
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * HITEX board defintion, can be used in examples for board specific code
+ */
+#define BOARD_HITEX_EVA_18504350
+
+/* For USBLIB examples */
+#define LEDS_LED1           0x01
+#define LEDS_LED2           0x02
+#define LEDS_LED3           0x04
+#define LEDS_LED4           0x08
+#define LEDS_NO_LEDS        0x00
+#define BUTTONS_BUTTON1     0x01
+#define JOY_UP              0x01
+#define JOY_DOWN            0x02
+#define JOY_LEFT            0x04
+#define JOY_RIGHT           0x08
+#define JOY_PRESS           0x10
+#define NO_BUTTON_PRESSED   0x00
+
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM   6
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM    21
+
+#define I2CDEV_PCA9502_ADDR     (0x9A >> 1)
+#define PCA9502_REG_IODIR       0x0A
+#define PCA9502_REG_IOSTATE     0x0B
+#define PCA9502_REG_IOINTENA    0x0C
+#define PCA9502_REG_IOCONTROL   0x0E
+#define PCA9502_REG_ADDR(x)     (((x) & 0x0F) << 3)
+
+/**
+ * Address of I2C device (UDA1380 CODEC) on board
+ */
+#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
+
+/**
+ * Default location of LCD buffer is in DRAM
+ */
+#define FRAMEBUFFER_ADDR        0x28000000
+
+/**
+ * LCD configuration data
+ */
+extern const LCD_Config_Type EA320x240;
+
+/**
+ * Default LCD configuration data for examples
+ */
+#define BOARD_LCD EA320x240
+
+/**
+ * CODEC audio input sources
+ */
+typedef enum {
+	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
+	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
+} Board_Audio_Input_Sel_Type;
+
+/**
+ * @brief	Initialize pin muxing for a UART
+ * @param	UARTx	: Pointer to UART register block for UART pins to init
+ * @return	Nothing
+ */
+void Board_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Initialize button(s) interface on board
+ * @return	Nothing
+ */
+void Board_Buttons_Init(void);
+
+/**
+ * @brief	Returns button(s) state on board
+ * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
+ */
+uint32_t Buttons_GetStatus(void);
+
+/**
+ * @brief	Initialize joystick interface on board
+ * @return	Nothing
+ */
+void Board_Joystick_Init(void);
+
+/**
+ * @brief	Returns joystick states on board
+ * @return	Returns a JOY_* value, ir JOY_PRESS or JOY_UP
+ */
+uint8_t Joystick_GetStatus(void);
+
+/**
+ * @brief	Returns the MAC address assigned to this board
+ * @param	mcaddr : Pointer to 6-byte character array to populate with MAC address
+ * @return	Nothing
+ */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);
+
+/**
+ * @brief	Sets up board specific ADC interface
+ * @return	Nothing
+ */
+void Board_ADC_Init(void);
+
+/**
+ * @brief	Sets up board specific I2C interface
+ * @param	I2Cx	: Pointer to I2C interface to initialize
+ * @return	Nothing
+ */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Initialize the LCD interface
+ * @return	Nothing
+ */
+void Board_LCD_Init(void);
+
+/**
+ * @brief	Initialize TSC2046 touchscreen controller
+ * @return	Nothing
+ */
+void Init_Touch_Controller(void);
+
+/**
+ * @brief	Get Touch coordinates
+ * @param	pX	: Pointer to x-Coord to populate
+ * @param	pY	: Pointer to y-Coord to populate
+ * @return	Nothing
+ */
+bool GetTouchPos(int16_t *pX, int16_t *pY);
+
+/**
+ * @brief	Initialize pin muxing for SDMMC interface
+ * @return	Nothing
+ */
+void Board_SDMMC_Init(void);
+
+/**
+ * @brief	Initialize pin muxing for SSP interface
+ * @param	SSPx	: Pointer to SSP interface to initialize
+ * @return	Nothing
+ */
+void Board_SSP_Init(LPC_SSP_Type *SSPx);
+
+/**
+ * @brief	Initialize I2S interface for the board and UDA1380
+ * @param	I2Sx			: Pointer to I2S register interface used on this board
+ * @param	audio_in_sel	: Audio input selection
+ * @return	Nothing
+ */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
+
+/**
+ * @brief	FIXME
+ * @param	Stream	: FIXME
+ * @return	Nothing
+ */
+void Serial_CreateStream(void *Stream);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_HITEX_EVA_18504350_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+// #define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+// #define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c

@@ -0,0 +1,455 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+
+/** @defgroup BOARD_HITEX_EVA_18504350_SYSINIT LPC1850 and LPC4350 Hitex EVA board System Init code
+ * @ingroup BOARD_HITEX_EVA_18504350
+ * The System initialization code is called prior to the application and
+ * initializes the board for run-time operation. Board initialization
+ * for the Hitex EVA boards includes clock setup, default pin muxing, and
+ * memory configuration.
+ *
+ * With the exception of stack space, no RW memory is used for this call.
+ *
+ * LPC1850 and LPC4350 Hitex EVA setup<BR>
+ *  Clocking:<BR>
+ *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
+ *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
+ *   SPIFI FLASH clock setup for fastest speed<BR>
+ *  Pin muxing:<BR>
+ *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
+ *   Sets up the external memory controller signals<BR>
+ *  Memory:<BR>
+ *   Sets up DRAM, static RAM, and NOR FLASH.
+ * @{
+ */
+
+#ifndef CORE_M0
+/* SCR pin definitions for pin muxing */
+typedef struct {
+	uint8_t pingrp;	/* Pin group */
+	uint8_t pinnum;	/* Pin number */
+	uint8_t pincfg;	/* Pin configuration for SCU */
+	uint8_t funcnum;/* Function number */
+} PINMUX_GRP_T;
+
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+	CGU_BASE_CLK_T clk;	/* Base clock */
+	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
+	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
+	bool powerdn;		/* Set to true if the base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {
+	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
+	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
+#if defined(USE_RMII)
+	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
+#else
+	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
+#endif
+	{CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
+#endif
+	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
+	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
+};
+
+/* SPIFI high speed pin mode setup */
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {
+	{0x3, 3,  (MD_PLN_FAST),  FUNC3},	/* SPIFI CLK */
+	{0x3, 4,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D3 */
+	{0x3, 5,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D2 */
+	{0x3, 6,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D1 */
+	{0x3, 7,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D0 */
+	{0x3, 8,  (MD_PLN_FAST),  FUNC3}	/* SPIFI CS/SSEL */
+};
+
+/* Setup system clocking */
+STATIC void SystemSetupClocking(void)
+{
+	int i;
+
+	/* Switch main system clocking to crystal */
+	Chip_Clock_EnableCrystal();
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
+
+	/* Setup PLL for 100MHz and switch main system clocking */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
+
+	/* Setup PLL for maximum clock */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
+
+	/* Setup system base clocks and initial states. This won't enable and
+	   disable individual clocks, but sets up the base clock sources for
+	   each individual peripheral clock. */
+	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
+		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
+								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
+	}
+
+	/* Reset and enable 32Khz oscillator */
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+	/* SPIFI pin setup is done prior to setting up system clocking */
+	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
+		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
+						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
+	}
+
+	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
+	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
+#if (MAX_CLOCK_FREQ > 180000000)
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
+#else
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
+#endif
+	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
+}
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+#if defined(USE_RMII)
+	/* RMII pin group */
+	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
+	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
+	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0xC, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
+	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
+#else
+	/* MII pin group */
+	{0x1, 19, (MD_PLN | MD_EZI),                   FUNC0},
+	{0x0, 1,  (MD_PLN),                            FUNC6},
+	{0x1, 18, (MD_PLN),                            FUNC3},
+	{0x1, 20, (MD_PLN),                            FUNC3},
+	{0x1, 17, (MD_PLN | MD_EZI),                   FUNC3},
+	{0xC, 1,  (MD_PLN),                            FUNC3},
+	{0x1, 16, (MD_PLN | MD_EZI),                   FUNC7},
+	{0x1, 15, (MD_PLN | MD_EZI),                   FUNC3},
+	{0x0, 0,  (MD_PLN | MD_EZI),                   FUNC2},
+	{0x9, 4,  (MD_PLN),                            FUNC5},
+	{0x9, 5,  (MD_PLN),                            FUNC5},
+	{0xC, 0,  (MD_PLN | MD_EZI),                   FUNC3},
+	{0x9, 0,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 1,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 6,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 3,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0x9, 2,  (MD_PLN | MD_EZI),                   FUNC5},
+	{0xC, 8,  (MD_PLN | MD_EZI),                   FUNC4},
+#endif
+	/* External data lines D0 .. D15 */
+	{0x1, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x5, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	/* Address lines A0 .. A23 */
+	{0x2, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0x6, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xA, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	/* EMC control signals */
+	{0x1, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{PINMUX_CLK, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xD, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 3,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 4,  MD_PLN_FAST,                         FUNC3},
+	{0x6, 6,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 5,  MD_PLN_FAST,                         FUNC3},
+	/* LCD interface, 24bpp */
+	{0x7, 7,  MD_PUP,                              FUNC3},
+	{0x4, 7,  MD_PUP,                              FUNC0},
+	{0x4, 5,  MD_PUP,                              FUNC2},
+	{0x4, 6,  MD_PUP,                              FUNC2},
+	{0x7, 6,  MD_PUP,                              FUNC3},
+	{0x4, 1,  MD_PUP,                              FUNC2},
+	{0x4, 4,  MD_PUP,                              FUNC2},
+	{0x4, 2,  MD_PUP,                              FUNC2},
+	{0x8, 7,  MD_PUP,                              FUNC3},
+	{0x8, 6,  MD_PUP,                              FUNC3},
+	{0x8, 5,  MD_PUP,                              FUNC3},
+	{0x8, 4,  MD_PUP,                              FUNC3},
+	{0x7, 5,  MD_PUP,                              FUNC3},
+	{0x4, 8,  MD_PUP,                              FUNC2},
+	{0x4, 10, MD_PUP,                              FUNC2},
+	{0x4, 9,  MD_PUP,                              FUNC2},
+	{0x8, 3,  MD_PUP,                              FUNC3},
+	{0xB, 6,  MD_PUP,                              FUNC2},
+	{0xB, 5,  MD_PUP,                              FUNC2},
+	{0xB, 4,  MD_PUP,                              FUNC2},
+	{0x7, 4,  MD_PUP,                              FUNC3},
+	{0x7, 2,  MD_PUP,                              FUNC3},
+	{0x7, 1,  MD_PUP,                              FUNC3},
+	{0xB, 3,  MD_PUP,                              FUNC2},
+	{0xB, 2,  MD_PUP,                              FUNC2},
+	{0xB, 1,  MD_PUP,                              FUNC2},
+	{0xB, 0,  MD_PUP,                              FUNC2},
+	{0x7, 0,  MD_PUP,                              FUNC3},
+	{0x4, 4,  MD_PUP,                              FUNC0},
+	{0x7, 3,  MD_PUP,                              FUNC0},
+	{0x4, 1,  MD_PUP,                              FUNC0},
+	/* Board LEDs */
+	{0x8, 1,  MD_PDN,                              FUNC0},
+	{0xE, 6,  MD_PDN,                              FUNC4},	/* GPIO7.6, green */
+	{0xE, 8,  MD_PDN,                              FUNC4},	/* GPIO7.8, blue */
+	{0xE, 5,  MD_PDN,                              FUNC4},	/* GPIO7.5, red */
+	/* Board ADC */
+	{0xF, 9,  MD_PLN,                              FUNC7},
+	/*  I2S  */
+	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
+	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
+	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
+};
+
+/* Sets up system pin muxing */
+STATIC void SystemSetupMuxing(void)
+{
+	int i;
+
+	/* Setup system level pin muxing */
+	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
+		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
+						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
+	}
+}
+
+/* EMC clock delay */
+#define CLK0_DELAY 7
+
+/* Hitex SDRAM timing and chip Config */
+STATIC const IP_EMC_DYN_CONFIG_Type IS42S16400_config = {
+	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
+	0x01,	/* Command Delayed */
+	EMC_NANOSECOND(20),
+	EMC_NANOSECOND(60),
+	EMC_NANOSECOND(63),
+	EMC_CLOCK(0x05),
+	EMC_CLOCK(0x05),
+	EMC_CLOCK(0x04),
+	EMC_NANOSECOND(63),
+	EMC_NANOSECOND(63),
+	EMC_NANOSECOND(63),
+	EMC_NANOSECOND(14),
+	EMC_CLOCK(0x02),
+	{
+		{
+			EMC_ADDRESS_DYCS0,	/* Hitex Board uses DYCS0 for SDRAM */
+			3,	/* RAS */
+
+			EMC_DYN_MODE_WBMODE_PROGRAMMED |
+			EMC_DYN_MODE_OPMODE_STANDARD |
+			EMC_DYN_MODE_CAS_3 |
+			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
+			EMC_DYN_MODE_BURST_LEN_8,
+
+			EMC_DYN_CONFIG_DATA_BUS_16 |
+			EMC_DYN_CONFIG_LPSDRAM |
+			EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
+			EMC_DYN_CONFIG_MD_SDRAM
+		},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0}
+	}
+};
+
+/* Hitex Static RAM timing and chip Config */
+STATIC const IP_EMC_STATIC_CONFIG_Type IS62WV25616_config = {
+	2,
+	EMC_STATIC_CONFIG_MEM_WIDTH_16 |
+	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
+	EMC_STATIC_CONFIG_BLS_HIGH /* |
+							      EMC_CONFIG_BUFFER_ENABLE*/,
+
+	EMC_NANOSECOND(0),
+	EMC_NANOSECOND(30),
+	EMC_NANOSECOND(90),
+	EMC_NANOSECOND(55),
+	EMC_NANOSECOND(55),
+	EMC_NANOSECOND(55)
+};
+
+/* Hitex NorFlash timing and chip Config */
+STATIC const IP_EMC_STATIC_CONFIG_Type SST39VF320_config = {
+	0,
+	EMC_STATIC_CONFIG_MEM_WIDTH_16 |
+	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
+	EMC_STATIC_CONFIG_BLS_HIGH /* |
+							      EMC_CONFIG_BUFFER_ENABLE*/,
+
+	EMC_NANOSECOND(0),
+	EMC_NANOSECOND(35),
+	EMC_NANOSECOND(70),
+	EMC_NANOSECOND(70),
+	EMC_NANOSECOND(40),
+	EMC_CLOCK(4)
+};
+
+/* Setup external memories */
+STATIC void SystemSetupMemory(void)
+{
+	/* Setup EMC Delays */
+	/* Move all clock delays together */
+	LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
+
+	/* Setup EMC Clock Divider for divide by 2 */
+	Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
+	LPC_CREG->CREG6 |= (1 << 16);
+	Chip_Clock_Enable(CLK_MX_EMC);
+
+	/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
+	Chip_EMC_Init(1, 0, 0);
+	/* Init EMC Dynamic Controller */
+	Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config);
+	/* Init EMC Static Controller CS2 */
+	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config);
+	/* Init EMC Static Controller CS0 */
+	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config);
+
+	/* Enable Buffer for External Flash */
+	LPC_EMC->STATICCONFIG0 |= 1 << 19;
+}
+
+#endif
+
+/**
+ * @brief	Setup the system
+ *			SystemInit() is called prior to the application and sets up system
+ *			clocking, memory, and any resources needed prior to the application
+ *			starting.
+ * @return	none
+ */
+void SystemInit(void)
+{
+#if defined(CORE_M3) || defined(CORE_M4)
+	unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+
+#if defined(__IAR_SYSTEMS_ICC__)
+	extern void *__vector_table;
+
+	*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(__CODE_RED)
+	extern void *g_pfnVectors;
+
+	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
+#elif defined(__ARMCC_VERSION)
+	extern void *__Vectors;
+
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+
+	/* Setup system clocking and memory. This is done early to allow the
+	   application and tools to clear memory and use scatter loading to
+	   external memory. */
+	SystemSetupClocking();
+	SystemSetupMuxing();
+	SystemSetupMemory();
+#endif
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief Keil MCB 1857/4357 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_keil_mcb_18574357.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h

@@ -0,0 +1,304 @@
+/*
+ * @brief Keil MCB 1857/4357 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_KEIL_MCB_18574357_H_
+#define __BOARD_KEIL_MCB_18574357_H_
+
+#include "chip.h"
+#include "board_api.h"
+#include "lpc_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_KEIL_MCB_18574357 LPC1857 and LPC4357 Keil MCB board support functions
+ * @ingroup BOARDS_18XX_43XX
+ * @{
+ */
+
+/** @defgroup BOARD_KEIL_MCB_18574357_OPTIONS BOARD: LPC1857 and LPC4357 Keil MCB board builds options
+ * The NGX board has options that configure it's operation at build-time.<br/>
+ * CHIP_LPC*
+ *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
+ * DEBUG:<br/>
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
+ * DEBUG_UART:<br/>
+ *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
+ * CRYSTAL_MAIN_FREQ_IN:<br/>
+ *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
+ * CRYSTAL_32K_FREQ_IN:<br/>
+ *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
+ * EXTERNAL_CLKIN_FREQ_IN:<br/>
+ *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
+ * MAX_CLOCK_FREQ:<br/>
+ *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
+ *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
+ * BOARD_HITEX_EVA_18504350:<br/>
+ *  - When building for Keil boards, BOARD_KEIL_MCB_18574357 is defined<br/>
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#define BOARD_KEIL_MCB_18574357
+
+#define LED_NUMBER_OF 1
+
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM			2
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM			0
+#define JOYSTICK_UP_GPIO_PORT_NUM               6
+#define JOYSTICK_UP_GPIO_BIT_NUM                10
+#define JOYSTICK_DOWN_GPIO_PORT_NUM             6
+#define JOYSTICK_DOWN_GPIO_BIT_NUM              11
+#define JOYSTICK_LEFT_GPIO_PORT_NUM             6
+#define JOYSTICK_LEFT_GPIO_BIT_NUM              12
+#define JOYSTICK_RIGHT_GPIO_PORT_NUM            6
+#define JOYSTICK_RIGHT_GPIO_BIT_NUM             13
+#define JOYSTICK_PRESS_GPIO_PORT_NUM            6
+#define JOYSTICK_PRESS_GPIO_BIT_NUM             8
+
+#define JOY_UP              0x01
+#define JOY_DOWN            0x02
+#define JOY_LEFT            0x04
+#define JOY_RIGHT           0x08
+#define JOY_PRESS           0x10
+#define NO_BUTTON_PRESSED   0x00
+
+#define BUTTONS_BUTTON1     0x01
+
+#define LEDS_LED1           0x01
+#define LEDS_LED2           0x02
+#define LEDS_LED3           0x04
+#define LEDS_LED4           0x08
+#define LEDS_NO_LEDS        0x00
+
+/** UDA1380 register values */
+#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
+#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
+
+#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE	(1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
+#define UDA1380_REG_ANAMIX_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_HEADAMP_DEFAULT_VALUE	( 1 << 9 | 2)
+
+#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_MIXVOL_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_MODEBBT_DEFAULT_VALUE	0x0000
+#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE	(2 << 8 | 2)
+#define UDA1380_REG_MIXSDO_DEFAULT_VALUE	0x0000
+
+#define UDA1380_REG_DECVOL_DEFAULT_VALUE	0xE4E4			/* Decrease Volume -28dB */
+#define UDA1380_REG_PGA_DEFAULT_VALUE		0x0000
+#define UDA1380_REG_ADC_DEFAULT_VALUE		0x0001			/* Apply 0bB VGA Gain, enable DC Filter */
+#define UDA1380_REG_AGC_DEFAULT_VALUE		0x0000
+
+#define UDA1380_REG_L3_DEFAULT_VALUE		0x0000
+
+/* UDA1380 address */
+#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
+
+/* UDA1380 Register Address */
+typedef enum {
+	UDA_EVALM_CLK = 0x00,
+	UDA_BUS_CTRL,
+	UDA_POWER_CTRL,
+	UDA_ANALOG_CTRL,
+	UDA_HPAMP_CTRL,
+	UDA_MASTER_VOL_CTRL = 0x10,
+	UDA_MIXER_VOL_CTRL,
+	UDA_MODE_CTRL,
+	UDA_MUTE_CTRL,
+	UDA_MIXER_FILTER_CTRL,
+	UDA_DEC_VOL_CTRL = 0x20,
+	UDA_PGA_CTRL,
+	UDA_ADC_CTRL,
+	UDA_AGC_CTRL,
+	UDA_TOTAL_REG
+} UDA1380_REG;
+
+/* Frame buffer address for lcd */
+#define FRAMEBUFFER_ADDR        0x28000000
+
+extern const LCD_Config_Type MCB4300_LCD;
+#define BOARD_LCD MCB4300_LCD
+
+/** Audio input select structure */
+typedef enum {
+	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
+	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
+} Board_Audio_Input_Sel_Type;
+
+/** LCD controller definitions */
+#define SSP_ID LPC_SSP0
+#define C_GLCD_H_SIZE   240
+#define C_GLCD_V_SIZE   320
+
+/** Private types/definitions for touch screen controller (STMPE811) */
+
+#define TSC_I2C_ADDR    (0x82 >> 1)	/* Touchscreen 7-bit I2C address */
+
+/** STMPE811 Register addresses */
+#define SYS_CTRL1       0x03
+#define SYS_CTRL2       0x04
+#define INT_CTRL        0x09
+#define INT_EN          0x0A
+#define INT_STA         0x0B
+#define GPIO_ALT_FUNCT  0x17
+#define ADC_CTRL1       0x20
+#define ADC_CTRL2       0x21
+#define TSC_CTRL        0x40
+#define TSC_CFG         0x41
+#define FIFO_TH         0x4A
+#define FIFO_STA        0x4B
+#define FIFO_SIZE       0x4C
+#define DATA_X          0x4D
+#define DATA_Y          0x4F
+#define DATA_Z          0x51
+#define TSC_FRACTION_Z  0x56
+#define TSC_I_DRIVE     0x58
+#define TSC_SHIELD      0x59
+#define DATA_XYZ        0xD7
+
+/**
+ * @brief	Sets up board specific ADC interface
+ * @return	Nothing
+ */
+void Board_ADC_Init(void);
+
+/**
+ * @brief	Sets up board specific I2C interface
+ * @param	I2Cx	: Pointer to I2C interface to initialize
+ * @return	Nothing
+ */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Initializes board specific GPIO Interrupt
+ * @return	Nothing
+ */
+void Board_GPIO_Int_Init(void);
+
+/**
+ * @brief	Sets up board specific SDMMC interface
+ * @return	Nothing
+ */
+void Board_SDMMC_Init(void);
+
+/**
+ * @brief	Sets up board specific SSP interface
+ * @param	SSPx	: Pointer to SSP interface to initialize
+ * @return	Nothing
+ */
+void Board_SSP_Init(LPC_SSP_Type *SSPx);
+
+/**
+ * @brief	Returns the MAC address assigned to this board
+ * @param	mcaddr	: Pointer to 6-byte character array to populate with MAC address
+ * @return	Nothing
+ */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);
+
+/**
+ * @brief	Initialize pin muxing for a UART
+ * @param	UARTx	: Pointer to UART register block for UART pins to init
+ * @return	Nothing
+ */
+void Board_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Initialize the LCD interface
+ * @return	Nothing
+ */
+void Board_LCD_Init(void);
+
+/**
+ * @brief	Initializes the STMPE811 touch screen controller
+ * @return	Nothing
+ */
+void Init_Touch_Controller(void);
+
+/**
+ * @brief	Get touch screen position
+ * @param	pX	: pointer to X position
+ * @param	pY	: pointer to Y position
+ * @return	true if touch is detected or false if otherwise
+ */
+bool GetTouchPos(int16_t *pX, int16_t *pY);
+
+/**
+ * @brief	Initializes board specific buttons
+ * @return	Nothing
+ */
+void Board_Buttons_Init (void);
+
+/**
+ * @brief	Initializes board specific joystick
+ * @return	Nothing
+ */
+void Board_Joystick_Init (void);
+
+/**
+ * @brief	Initialize joystick interface on board
+ * @return	joystick status: up, down, left or right
+ */
+uint8_t Joystick_GetStatus (void);
+
+/**
+ * @brief	Returns button(s) state on board
+ * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
+ */
+uint32_t Buttons_GetStatus(void);
+
+/**
+ * @brief	Sets up board specific I2S interface and UDA1380
+ * @param	I2Sx			: Pointer to I2S interface to initialize
+ * @param	audio_in_sel	: audio input selection
+ * @return	Nothing
+ */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
+
+//FIXME Should we remove this function?
+void Serial_CreateStream(void *Stream);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_KEIL_MCB_18574357_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART3
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING'
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART3
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c

@@ -0,0 +1,433 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+
+/** @defgroup BOARD_KEIL_MCB_18574357_SYSINIT LPC1857 and LPC4357 Keil MCB board System Init code
+ * @ingroup BOARD_KEIL_MCB_18574357
+ * The System initialization code is called prior to the application and
+ * initializes the board for run-time operation. Board initialization
+ * for the Keil MCB boards includes clock setup, default pin muxing, and
+ * memory configuration.
+ *
+ * With the exception of stack space, no RW memory is used for this call.
+ *
+ * LPC1857 and LPC4357 Keil MCB setup<BR>
+ *  Clocking:<BR>
+ *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
+ *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
+ *   SPIFI FLASH clock setup for fastest speed<BR>
+ *  Pin muxing:<BR>
+ *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
+ *   Sets up the external memory controller signals<BR>
+ *  Memory:<BR>
+ *   Sets up DRAM and NOR FLASH.
+ * @{
+ */
+
+#ifndef CORE_M0
+/* SCR pin definitions for pin muxing */
+typedef struct {
+	uint8_t pingrp;	/* Pin group */
+	uint8_t pinnum;	/* Pin number */
+	uint8_t pincfg;	/* Pin configuration for SCU */
+	uint8_t funcnum;/* Function number */
+} PINMUX_GRP_T;
+
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+	CGU_BASE_CLK_T clk;	/* Base clock */
+	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
+	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
+	bool powerdn;		/* Set to true if the base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {
+	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
+	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
+#if defined(USE_RMII)
+	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
+#else
+	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
+#endif
+	{CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
+#endif
+	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
+	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
+};
+
+/* SPIFI high speed pin mode setup */
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {
+	{0x3, 3,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 4,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 5,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 6,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 7,  (MD_PLN_FAST),  FUNC3},
+	{0x3, 8,  (MD_PLN_FAST),  FUNC3}
+};
+
+/* Setup system clocking */
+STATIC void SystemSetupClocking(void)
+{
+	int i;
+
+	/* Setup FLASH acceleration to target clock rate prior to clock switch */
+	Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
+
+	/* Switch main system clocking to crystal */
+	Chip_Clock_EnableCrystal();
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
+
+	/* Setup PLL for 100MHz and switch main system clocking */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
+
+	/* Setup PLL for maximum clock */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
+
+	/* Setup system base clocks and initial states. This won't enable and
+	   disable individual clocks, but sets up the base clock sources for
+	   each individual peripheral clock. */
+	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
+		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
+								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
+	}
+
+	/* Reset and enable 32Khz oscillator */
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+	/* SPIFI pin setup is done prior to setting up system clocking */
+	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
+		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
+						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
+	}
+
+	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
+	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
+#if (MAX_CLOCK_FREQ > 180000000)
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
+#else
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
+#endif
+	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
+}
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+	/* RMII pin group */
+	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
+	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
+	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0xC, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
+	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
+	/* External data lines D0 .. D15 */
+	{0x1, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x5, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x5, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	/* Address lines A0 .. A23 */
+	{0x2, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x1, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x2, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x2, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0x6, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xE, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xA, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	/* EMC control signals */
+	{0x1, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
+	{0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0x6, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{PINMUX_CLK, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{PINMUX_CLK, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
+	{0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0xD, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
+	{0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
+	{0x1, 3,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 4,  MD_PLN_FAST,                         FUNC3},
+	{0x6, 6,  MD_PLN_FAST,                         FUNC1},
+	{0x1, 5,  MD_PLN_FAST,                         FUNC3},
+	{0x1, 6,  MD_PLN_FAST,                         FUNC3},
+	/* Board LEDs */
+	{0xD, 10, (MD_PLN),                            FUNC4},
+	{0xD, 11, (MD_PLN),                            FUNC4},
+	{0xD, 12, (MD_PLN),                            FUNC4},
+	{0xD, 13, (MD_PLN),                            FUNC4},
+	{0xD, 14, (MD_PLN),                            FUNC4},
+	{0x9, 0,  (MD_PLN),                            FUNC0},
+	{0x9, 1,  (MD_PLN),                            FUNC0},
+	{0x9, 2,  (MD_PLN),                            FUNC0},
+	/* SSP0 */
+	{0xF, 0,  (MD_PLN_FAST),                       FUNC0},
+	{0xF, 1,  (MD_PLN_FAST),                       FUNC4},
+	{0xF, 2,  (MD_PLN_FAST),                       FUNC2},
+	{0xF, 3,  (MD_PLN_FAST),                       FUNC2},
+	/* LCD interface, 16bpp */
+	{0x4, 1,  MD_PUP,                              FUNC5},
+	{0x4, 2,  MD_PUP,                              FUNC2},
+	{0x4, 5,  MD_PUP,                              FUNC2},
+	{0x4, 6,  MD_PUP,                              FUNC2},
+	{0x4, 7,  MD_PUP,                              FUNC0},
+	{0x4, 9,  MD_PUP,                              FUNC2},
+	{0x4, 10, MD_PUP,                              FUNC2},
+	{0x7, 0,  MD_PUP,                              FUNC0},
+	{0x7, 6,  MD_PUP,                              FUNC3},
+	{0x8, 3,  MD_PUP,                              FUNC3},
+	{0x8, 4,  MD_PUP,                              FUNC3},
+	{0x8, 5,  MD_PUP,                              FUNC3},
+	{0x8, 6,  MD_PUP,                              FUNC3},
+	{0x8, 7,  MD_PUP,                              FUNC3},
+	{0xB, 0,  MD_PUP,                              FUNC2},
+	{0xB, 1,  MD_PUP,                              FUNC2},
+	{0xB, 2,  MD_PUP,                              FUNC2},
+	{0xB, 3,  MD_PUP,                              FUNC2},
+	{0xB, 4,  MD_PUP,                              FUNC2},
+	{0xB, 5,  MD_PUP,                              FUNC2},
+	{0xB, 6,  MD_PUP,                              FUNC2},
+	/*  I2S  */
+	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
+	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
+	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
+};
+
+/* Sets up system pin muxing */
+STATIC void SystemSetupMuxing(void)
+{
+	int i;
+
+	/* Setup system level pin muxing */
+	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
+		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
+						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
+	}
+}
+
+/* EMC clock delay */
+#define CLK0_DELAY 7
+
+/* Keil SDRAM timing and chip Config */
+STATIC const IP_EMC_DYN_CONFIG_Type MT48LC4M32_config = {
+	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
+	0x01,	/* Command Delayed */
+	EMC_NANOSECOND(18),
+	EMC_NANOSECOND(42),
+	EMC_NANOSECOND(70),
+	EMC_CLOCK(0x01),
+	EMC_CLOCK(0x05),
+	EMC_NANOSECOND(12),
+	EMC_NANOSECOND(60),
+	EMC_NANOSECOND(60),
+	EMC_NANOSECOND(70),
+	EMC_NANOSECOND(12),
+	EMC_CLOCK(0x02),
+	{
+		{
+			EMC_ADDRESS_DYCS0,	/* Keil Board uses DYCS0 for SDRAM */
+			3,	/* RAS */
+
+			EMC_DYN_MODE_WBMODE_PROGRAMMED |
+			EMC_DYN_MODE_OPMODE_STANDARD |
+			EMC_DYN_MODE_CAS_3 |
+			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
+			EMC_DYN_MODE_BURST_LEN_4,
+
+			EMC_DYN_CONFIG_DATA_BUS_32 |
+			EMC_DYN_CONFIG_LPSDRAM |
+			EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS |
+			EMC_DYN_CONFIG_MD_SDRAM
+		},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0}
+	}
+};
+
+/* Keil NorFlash timing and chip Config */
+/* FIXME : Keil NOR FLASH not yet tested */
+STATIC const IP_EMC_STATIC_CONFIG_Type S29GL64N90_config = {
+	0,
+	EMC_STATIC_CONFIG_MEM_WIDTH_32 |
+	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
+	EMC_STATIC_CONFIG_BLS_HIGH /* |
+							      EMC_CONFIG_BUFFER_ENABLE*/,
+
+	EMC_NANOSECOND(0),
+	EMC_NANOSECOND(65),
+	EMC_NANOSECOND(90),
+	EMC_NANOSECOND(90),
+	EMC_NANOSECOND(35),
+	EMC_CLOCK(4)
+};
+
+/* Setup external memories */
+STATIC void SystemSetupMemory(void)
+{
+	/* Setup EMC Delays */
+	/* Move all clock delays together */
+	LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
+
+	/* Setup EMC Clock Divider for divide by 2 */
+	Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
+	LPC_CREG->CREG6 |= (1 << 16);
+	Chip_Clock_Enable(CLK_MX_EMC);
+
+	/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
+	Chip_EMC_Init(1, 0, 0);
+	/* Init EMC Dynamic Controller */
+	Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &MT48LC4M32_config);
+	/* Init EMC Static Controller CS0 */
+	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &S29GL64N90_config);
+
+	/* Enable Buffer for External Flash */
+	LPC_EMC->STATICCONFIG0 |= 1 << 19;
+}
+
+#endif
+
+/**
+ * @brief	Setup the system
+ *			SystemInit() is called prior to the application and sets up system
+ *			clocking, memory, and any resources needed prior to the application
+ *			starting.
+ * @return	none
+ */
+void SystemInit(void)
+{
+#if defined(CORE_M3) || defined(CORE_M4)
+	unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+
+#if defined(__IAR_SYSTEMS_ICC__)
+	extern void *__vector_table;
+
+	*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(__CODE_RED)
+	extern void *g_pfnVectors;
+
+	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
+#elif defined(__ARMCC_VERSION)
+	extern void *__Vectors;
+
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+
+	/* Setup system clocking and memory. This is done early to allow the
+	   application and tools to clear memory and use scatter loading to
+	   external memory. */
+	SystemSetupClocking();
+	SystemSetupMuxing();
+	SystemSetupMemory();
+#endif
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief NGX Xplorer 1830/4330 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_ngx_xplorer_18304330.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c

@@ -0,0 +1,385 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+#include "string.h"
+
+#include "lpc_phy_smsc87x0.c"
+#include "retarget.c"
+
+/** @ingroup BOARD_NGX_XPLORER_18304330
+ * @{
+ */
+
+void Board_UART_Init(LPC_USART_Type *UARTx)
+{
+	if (UARTx == LPC_USART0) {
+		Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2);					/* P6.5 : UART0_TXD */
+		Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P6.4 : UART0_RXD */
+	}
+	else if (UARTx == LPC_UART1) {
+		Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2);				/* P1.13 : UART1_TXD */
+		Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P1.14 : UART1_RX */
+	}
+}
+
+/* Initialize debug output via UART for board */
+void Board_Debug_Init(void)
+{
+#if defined(DEBUG_UART)
+	Board_UART_Init(DEBUG_UART);
+
+	Chip_UART_Init(DEBUG_UART);
+	Chip_UART_SetBaud(DEBUG_UART, 115200);
+	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
+
+	/* Enable UART Transmit */
+	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
+#endif
+}
+
+/* Sends a character on the UART */
+void Board_UARTPutChar(char ch)
+{
+#if defined(DEBUG_UART)
+	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
+#endif
+}
+
+/* Gets a character from the UART, returns EOF if no character is ready */
+int Board_UARTGetChar(void)
+{
+#if defined(DEBUG_UART)
+	uint8_t data;
+
+	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
+		return (int) data;
+	}
+#endif
+	return EOF;
+}
+
+/* Outputs a string on the debug UART */
+void Board_UARTPutSTR(char *str)
+{
+#if defined(DEBUG_UART)
+	while (*str != '\0') {
+		Board_UARTPutChar(*str++);
+	}
+#endif
+}
+
+void Board_LED_Init()
+{
+	/* P2.12 : LED D2 as output */
+	Chip_GPIO_WriteDirBit(1, 12, true);
+
+	/* P2.11 : LED D3 as output */
+	Chip_GPIO_WriteDirBit(1, 11, true);
+
+	/* Set initial states to off (true to disable) */
+	Chip_GPIO_WritePortBit(1, 12, (bool) true);
+	Chip_GPIO_WritePortBit(1, 11, (bool) true);
+}
+
+void Board_LED_Set(uint8_t LEDNumber, bool On)
+{
+	if (LEDNumber == 0) {
+		Chip_GPIO_WritePortBit(1, 12, (bool) !On);
+	}
+	else if (LEDNumber == 1) {
+		Chip_GPIO_WritePortBit(1, 11, (bool) !On);
+	}
+}
+
+bool Board_LED_Test(uint8_t LEDNumber)
+{
+	if (LEDNumber == 0) {
+		return (bool) !Chip_GPIO_ReadPortBit(1, 12);
+	}
+	else if (LEDNumber == 1) {
+		return (bool) !Chip_GPIO_ReadPortBit(1, 11);
+	}
+
+	return false;
+}
+
+void Board_Buttons_Init(void)	// FIXME not functional ATM
+{
+	Chip_SCU_PinMux(0x2, 7, MD_PUP | MD_EZI | MD_ZI, FUNC0);		// P2_7 as GPIO0[7]
+	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false);	// input
+}
+
+uint32_t Buttons_GetStatus(void)
+{
+	uint8_t ret = NO_BUTTON_PRESSED;
+	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
+		ret |= BUTTONS_BUTTON1;
+	}
+	return ret;
+}
+
+void Board_Joystick_Init(void)
+{}
+
+uint8_t Joystick_GetStatus(void)
+{
+	return NO_BUTTON_PRESSED;
+}
+
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
+}
+
+/* Returns the MAC address assigned to this board */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr)
+{
+	uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
+
+	memcpy(mcaddr, boardmac, 6);
+}
+
+/* Set up and initialize all required blocks and functions related to the
+   board hardware */
+void Board_Init(void)
+{
+	/* Sets up DEBUG UART */
+	DEBUGINIT();
+
+	/* Updates SystemCoreClock global var with current clock speed */
+	SystemCoreClockUpdate();
+
+	/* Initializes GPIO */
+	Chip_GPIO_Init();
+
+	/* Setup GPIOs for USB demos */
+	Chip_SCU_PinMux(0x2, 6, (MD_PUP | MD_EZI), FUNC4);			/* P2_6 USB1_PWR_EN, USB1 VBus function */
+	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	/* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
+	Chip_SCU_PinMux(0x1, 7, (MD_PUP | MD_EZI), FUNC4);			/* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */
+	Chip_GPIO_WriteDirBit(5, 6, true);							/* GPIO5[6] = USB1_PWR_EN */
+	Chip_GPIO_WritePortBit(5, 6, true);							/* GPIO5[6] output high */
+}
+
+void Board_I2C_Init(LPC_I2C_Type *I2Cx)
+{
+	if (I2Cx == LPC_I2C1) {
+		/* Configure pin function for I2C1*/
+		Chip_SCU_PinMux(0x2, 3, MD_ZI | MD_EZI, FUNC1);		/* P2.3 : I2C1_SDA */
+		Chip_SCU_PinMux(0x2, 4, MD_ZI | MD_EZI, FUNC1);		/* P2.4 : I2C1_SCL */
+	}
+}
+
+void GPIO0_IRQHandler(void)
+{
+	static bool On;
+
+	if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
+		Chip_GPIO_IntClear(0, 0);
+		On = (bool) !On;
+		Board_LED_Set(1, On);
+	}
+}
+
+void Board_GPIO_Int_Init()
+{
+	Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0);	/* PF.9 : POTI button */
+	Chip_GPIO_WriteDirBit(7, 23, false);						/* PF.9 -> GPIO7[23] : input */
+	Chip_SCU_GPIOIntPinSel(0, 7, 23);
+	Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE);			/* Configure GPIO0[7] to interrupt pin (SW2 switch) */
+
+	NVIC_EnableIRQ(PIN_INT0_IRQn);	/* enable GPIO interrupt 0 */
+}
+
+void Board_SDMMC_Init(void)
+{
+	Chip_SCU_PinMux(0x1, 9, MD_PLN_FAST, FUNC7);	/* P1.9 connected to SDIO_D0 */
+	Chip_SCU_PinMux(0x1, 10, MD_PLN_FAST, FUNC7);	/* P1.10 connected to SDIO_D1 */
+	Chip_SCU_PinMux(0x1, 11, MD_PLN_FAST, FUNC7);	/* P1.11 connected to SDIO_D2 */
+	Chip_SCU_PinMux(0x1, 12, MD_PLN_FAST, FUNC7);	/* P1.12 connected to SDIO_D3 */
+
+	Chip_SCU_PinMux(PINMUX_CLK, 2, MD_PLN | MD_EZI, FUNC4);	/* CLK2 connected to SDIO_CLK */
+	Chip_SCU_PinMux(0x1, 6, MD_PLN_FAST, FUNC7);	/* P1.6 connected to SDIO_CMD */
+}
+
+void Board_SSP_Init(LPC_SSP_Type *SSPx)
+{
+	if (SSPx == LPC_SSP1) {
+		/* Set up clock and power for SSP1 module */
+		/* Configure SSP1 pins*/
+		/* SCLK comes out pin CLK0 */
+		Chip_SCU_PinMux(PINMUX_CLK, 0, MD_PLN_FAST, FUNC6);		/* CLK0 connected to CLK	func6=SSP1 CLK1  */
+		Chip_SCU_PinMux(0x1, 5, MD_PLN_FAST, FUNC5);			/* P1.5 connected to nCS	func5=SSP1 SSEL1 */
+		Chip_SCU_PinMux(0x1, 3, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.3 connected to SO		func5=SSP1 MISO1 */
+		Chip_SCU_PinMux(0x1, 4, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.4 connected to nSI	func5=SSP1 MOSI1 */
+		Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
+	}
+	else {
+		return;
+	}
+}
+
+/* System Register Data Set */
+uint16_t UDA_sys_regs_dat[] = {
+	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
+	UDA1380_REG_I2S_DEFAULT_VALUE,
+	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
+	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
+	UDA1380_REG_HEADAMP_DEFAULT_VALUE
+};
+
+/* System Register Data Set */
+uint16_t UDA_interfil_regs_dat[] = {
+	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
+	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
+	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
+	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
+	UDA1380_REG_MIXSDO_DEFAULT_VALUE
+};
+/* decimator Register Data Set */
+uint16_t UDA_decimator_regs_dat[] = {
+	UDA1380_REG_DECVOL_DEFAULT_VALUE,
+	UDA1380_REG_PGA_DEFAULT_VALUE,
+	UDA1380_REG_ADC_DEFAULT_VALUE,
+	UDA1380_REG_AGC_DEFAULT_VALUE
+};
+static void delay(uint32_t i) {
+	while (i--) {}
+}
+
+static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
+
+	I2C_Config->tx_data[0] = reg;
+	I2C_Config->tx_data[1] = value >> 8;
+	I2C_Config->tx_data[2] = value & 0xFF;
+	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
+	delay(10000);
+}
+
+static uint16_t UDA_Reg_read(UDA1380_REG reg) {
+	uint8_t rx_data[2];
+	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
+	return rx_data[0] << 8 | rx_data[1];
+}
+
+static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint16_t temp;
+	uint8_t  i;
+	/* Reset UDA1380 on board NGX Xplorer */
+	Chip_SCU_PinMux(0x2, 10, MD_PUP, FUNC0);
+	Chip_GPIO_WriteDirBit(0, 14, true);
+	Chip_GPIO_WritePortBit(0, 14, true);
+	// delay 1us
+	delay(100000);
+	Chip_GPIO_WritePortBit(0, 14, false);
+	delay(100000);
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
+		if (temp != UDA_sys_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	/* interfilter regs init */
+	for (i = 0; i < 5; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
+		if (temp != UDA_interfil_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+	/* decimator regs init */
+	for (i = 0; i < 4; i++) {
+		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
+		if (temp != UDA_decimator_regs_dat[i]) {
+			return ERROR;
+		}
+	}
+
+	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
+		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
+		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
+					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
+					  I2C_Config);
+		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
+		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
+			return ERROR;
+		}
+	}
+	return SUCCESS;
+
+}
+
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
+{
+	uint8_t uda1380_tx_data_buf[3];
+	Chip_I2S_Audio_Format_Type I2S_Config;
+	I2C_M_SETUP_Type I2C_Config;
+	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
+	I2C_Config.retransmissions_max = 5;
+	I2C_Config.tx_length = 3;
+	I2C_Config.tx_data = uda1380_tx_data_buf;
+	I2C_Config.rx_length = 0;
+	I2C_Config.rx_data = NULL;
+
+	/* Initialize I2C peripheral ------------------------------------*/
+	/* Init I2C */
+	Chip_I2C_Init(LPC_I2C0);
+	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
+
+	I2S_Config.SampleRate = 48000;
+	I2S_Config.ChannelNumber = 2;		/* 1 is mono, 2 is stereo */
+	I2S_Config.WordWidth =  16;			/* 8, 16 or 32 bits */
+	Chip_I2S_Init(LPC_I2S0);
+	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
+	/* Enable Slave I2C operation */
+	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
+	/* Init UDA1380 CODEC */
+	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
+
+}
+
+/* FIXME Should we remove this function? */
+void Serial_CreateStream(void *Stream)
+{}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h

@@ -0,0 +1,232 @@
+/*
+ * @brief NGX Xplorer 1830/4330 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_NGX_XPLORER_18304330_H_
+#define __BOARD_NGX_XPLORER_18304330_H_
+
+#include "chip.h"
+#include "board_api.h"
+#include "lpc_phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions
+ * @ingroup BOARDS_18XX_43XX
+ * @{
+ */
+
+/** @defgroup BOARD_NGX_XPLORER_18304330_OPTIONS BOARD: LPC1830 and LPC4330 NGX Xplorer board builds options
+ * The NGX board has options that configure it's operation at build-time.<br/>
+ * CHIP_LPC*
+ *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
+ * DEBUG:<br/>
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
+ * DEBUG_UART:<br/>
+ *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
+ * CRYSTAL_MAIN_FREQ_IN:<br/>
+ *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
+ * CRYSTAL_32K_FREQ_IN:<br/>
+ *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
+ * EXTERNAL_CLKIN_FREQ_IN:<br/>
+ *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
+ * MAX_CLOCK_FREQ:<br/>
+ *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
+ *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
+ * BOARD_HITEX_EVA_18504350:<br/>
+ *  - When building for NGX boards, BOARD_NGX_XPLORER_18304330 is defined<br/>
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#define BOARD_NGX_XPLORER_18304330
+
+#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
+
+#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
+#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
+
+#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE   (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
+#define UDA1380_REG_ANAMIX_DEFAULT_VALUE    0x0000
+#define UDA1380_REG_HEADAMP_DEFAULT_VALUE   ( 1 << 9 | 2)
+
+#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE   0x0000
+#define UDA1380_REG_MIXVOL_DEFAULT_VALUE    0x0000
+#define UDA1380_REG_MODEBBT_DEFAULT_VALUE   0x0000
+#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE  (2 << 8 | 2)
+#define UDA1380_REG_MIXSDO_DEFAULT_VALUE      0x0000
+
+#define UDA1380_REG_DECVOL_DEFAULT_VALUE     0xE4E4			/* Decrease Volume -28dB */
+#define UDA1380_REG_PGA_DEFAULT_VALUE         0x0000
+#define UDA1380_REG_ADC_DEFAULT_VALUE         0x0001			/* Apply 0bB VGA Gain, enable DC Filter */
+#define UDA1380_REG_AGC_DEFAULT_VALUE         0x0000
+#define UDA1380_REG_L3_DEFAULT_VALUE          0x0000
+
+/* For USBLIB examples */
+#define LEDS_LED1           0x01
+#define LEDS_LED2           0x02
+#define LEDS_LED3           0x04
+#define LEDS_LED4           0x08
+#define LEDS_NO_LEDS        0x00
+#define BUTTONS_BUTTON1     0x01
+#define JOY_UP              0x01
+#define JOY_DOWN            0x02
+#define JOY_LEFT            0x04
+#define JOY_RIGHT           0x08
+#define JOY_PRESS           0x10
+#define NO_BUTTON_PRESSED   0x00
+
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM   0
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM    7
+#define LED1_GPIO_PORT_NUM              1
+#define LED1_GPIO_BIT_NUM               11
+#define LED2_GPIO_PORT_NUM              1
+#define LED2_GPIO_BIT_NUM               12
+
+typedef enum {
+	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
+	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
+} Board_Audio_Input_Sel_Type;
+
+/* UDA1380 Register Address */
+typedef enum {
+	UDA_EVALM_CLK = 0x00,
+	UDA_BUS_CTRL,
+	UDA_POWER_CTRL,
+	UDA_ANALOG_CTRL,
+	UDA_HPAMP_CTRL,
+	UDA_MASTER_VOL_CTRL = 0x10,
+	UDA_MIXER_VOL_CTRL,
+	UDA_MODE_CTRL,
+	UDA_MUTE_CTRL,
+	UDA_MIXER_FILTER_CTRL,
+	UDA_DEC_VOL_CTRL = 0x20,
+	UDA_PGA_CTRL,
+	UDA_ADC_CTRL,
+	UDA_AGC_CTRL,
+	UDA_TOTAL_REG
+} UDA1380_REG;
+
+/**
+ * @brief	Sets up board specific I2C interface
+ * @param	I2Cx	: Pointer to I2C interface to initialize
+ * @return	Nothing
+ */
+void Board_I2C_Init(LPC_I2C_Type *I2Cx);
+
+/**
+ * @brief	Initializes board specific GPIO Interrupt
+ * @return	Nothing
+ */
+void Board_GPIO_Int_Init(void);
+
+/**
+ * @brief	Initialize pin muxing for SSP interface
+ * @param	SSPx	: Pointer to SSP interface to initialize
+ * @return	Nothing
+ */
+void Board_SSP_Init(LPC_SSP_Type *SSPx);
+
+/**
+ * @brief	Returns the MAC address assigned to this board
+ * @param	mcaddr : Pointer to 6-byte character array to populate with MAC address
+ * @return	Nothing
+ */
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);
+
+/**
+ * @brief	Initialize pin muxing for a UART
+ * @param	UARTx	: Pointer to UART register block for UART pins to init
+ * @return	Nothing
+ */
+void Board_UART_Init(LPC_USART_Type *UARTx);
+
+/**
+ * @brief	Initialize pin muxing for SDMMC interface
+ * @return	Nothing
+ */
+void Board_SDMMC_Init(void);
+
+/**
+ * @brief	Initialize button(s) interface on board
+ * @return	Nothing
+ */
+void Board_Buttons_Init(void);
+
+/**
+ * @brief	Initialize joystick interface on board
+ * @return	Nothing
+ */
+void Board_Joystick_Init(void);
+
+/**
+ * @brief	Returns joystick states on board
+ * @return	Returns a JOY_* value, ir JOY_PRESS or JOY_UP
+ */
+uint8_t Joystick_GetStatus(void);
+
+/**
+ * @brief	Returns button(s) state on board
+ * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
+ */
+uint32_t Buttons_GetStatus (void);
+
+/**
+ * @brief	Initialize I2S interface for the board and UDA1380
+ * @param	I2Sx			: Pointer to I2S register interface used on this board
+ * @param	audio_in_sel	: Audio input selection
+ * @return	Nothing
+ */
+void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
+
+/**
+ * @brief	FIXME
+ * @param	Stream	: FIXME
+ * @return	Nothing
+ */
+void Serial_CreateStream(void *Stream);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_NGX_XPLORER_18304330_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+// #define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+// #define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c

@@ -0,0 +1,239 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "board.h"
+
+/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code
+ * @ingroup BOARD_NGX_XPLORER_18304330
+ * The System initialization code is called prior to the application and
+ * initializes the board for run-time operation. Board initialization
+ * for the NGX Xplorer boards includes clock setup and default pin muxing
+ * configuration.
+ *
+ * With the exception of stack space, no RW memory is used for this call.
+ *
+ * LPC1830 and LPC4330 NGX Xplorer setup<BR>
+ *  Clocking:<BR>
+ *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
+ *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
+ *   SPIFI FLASH clock setup for fastest speed<BR>
+ *  Pin muxing:<BR>
+ *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
+ *  Memory:<BR>
+ *   There is no memory setup for this board.
+ * @{
+ */
+
+#ifndef CORE_M0
+/* SCR pin definitions for pin muxing */
+typedef struct {
+	uint8_t pingrp;	/* Pin group */
+	uint8_t pinnum;	/* Pin number */
+	uint8_t pincfg;	/* Pin configuration for SCU */
+	uint8_t funcnum;/* Function number */
+} PINMUX_GRP_T;
+
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+	CGU_BASE_CLK_T clk;	/* Base clock */
+	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
+	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
+	bool powerdn;		/* Set to true if the base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {
+	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
+	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
+#endif
+	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
+#if defined(USE_RMII)
+	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
+#else
+	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
+#endif
+	{CLK_BASE_LCD, CLKIN_MAINPLL, false, true},
+#if defined(CHIP_LPC43XX)
+	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
+#endif
+	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
+	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
+	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
+	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
+};
+
+/* SPIFI high speed pin mode setup */
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {
+	{0x3, 3,  (MD_PLN_FAST),  FUNC3},	/* SPIFI CLK */
+	{0x3, 4,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D3 */
+	{0x3, 5,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D2 */
+	{0x3, 6,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D1 */
+	{0x3, 7,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D0 */
+	{0x3, 8,  (MD_PLN_FAST),  FUNC3}	/* SPIFI CS/SSEL */
+};
+
+/* Setup system clocking */
+STATIC void SystemSetupClocking(void)
+{
+	int i;
+
+	/* Switch main system clocking to crystal */
+	Chip_Clock_EnableCrystal();
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
+
+	/* Setup PLL for 100MHz and switch main system clocking */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
+	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
+
+	/* Setup PLL for maximum clock */
+	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
+
+	/* Setup system base clocks and initial states. This won't enable and
+	   disable individual clocks, but sets up the base clock sources for
+	   each individual peripheral clock. */
+	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
+		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
+								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
+	}
+
+	/* Reset and enable 32Khz oscillator */
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+	/* SPIFI pin setup is done prior to setting up system clocking */
+	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
+		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
+						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
+	}
+
+	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
+	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
+#if (MAX_CLOCK_FREQ > 180000000)
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
+#else
+	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
+#endif
+	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
+}
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+	/* RMII pin group */
+	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
+	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
+	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
+	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
+	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
+	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
+	{0x2, 0,  (MD_EHS | MD_PLN | MD_ZI),           FUNC7},
+	/* Board LEDs */
+	{0x2, 11, MD_PDN,                              FUNC0},
+	{0x2, 12, MD_PDN,                              FUNC0},
+	/*  I2S  */
+	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
+	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
+	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
+	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
+};
+
+/* Sets up system pin muxing */
+STATIC void SystemSetupMuxing(void)
+{
+	int i;
+
+	/* Setup system level pin muxing */
+	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
+		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
+						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
+	}
+}
+
+/* Nothing to do for the Xplorer board */
+STATIC void SystemSetupMemory(void)
+{}
+
+#endif
+
+/**
+ * @brief	Setup the system
+ * @return	none
+ * SystemInit() is called prior to the application and sets up system
+ * clocking, memory, and any resources needed prior to the application
+ * starting.
+ */
+void SystemInit(void)
+{
+#if defined(CORE_M3) || defined(CORE_M4)
+	volatile unsigned int *pSCB_VTOR = (volatile unsigned int *) 0xE000ED08;
+
+#if defined(__IAR_SYSTEMS_ICC__)
+	extern void *__vector_table;
+
+	*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(__CODE_RED)
+	extern void *g_pfnVectors;
+
+	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
+#elif defined(__ARMCC_VERSION)
+	extern void *__Vectors;
+
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+
+	/* Setup system clocking and memory. This is done early to allow the
+	   application and tools to clear memory and use scatter loading to
+	   external memory. */
+	SystemSetupClocking();
+	SystemSetupMuxing();
+	SystemSetupMemory();
+#endif
+}
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_chip/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Glob('chip_18xx_43xx/*.c')
+src += Glob('chip_common/*.c')
+
+path = [cwd + '/chip_18xx_43xx',
+        cwd + '/chip_common']
+
+group = DefineGroup('lpc_chip', src, depend = [], CPPPATH = path)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c

@@ -0,0 +1,136 @@
+/*
+ * @brief LPC18xx/43xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "adc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*The channel to be operated on */
+static uint8_t active_channel;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Returns the clock for the selected ADC */
+static CCU_CLK_T Chip_ADC_GetClk(LPC_ADC_Type *pADC)
+{
+	CCU_CLK_T adcclk;
+
+	if (pADC == LPC_ADC0) {
+		adcclk = CLK_APB3_ADC0;
+	}
+	else {
+		adcclk = CLK_APB3_ADC1;
+	}
+
+	return adcclk;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC peripheral and the ADC setup structure to default value */
+void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup)
+{
+	CCU_CLK_T adcclk = Chip_ADC_GetClk(pADC);
+
+	/* Enable ADC clocking */
+	Chip_Clock_EnableOpts(adcclk, true, true, 1);
+	ADCSetup->adcPerClock = Chip_Clock_GetRate(adcclk);
+
+	ADCSetup->adcRate = 400000;
+	ADCSetup->bitsAccuracy = ADC_10BITS;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+}
+
+/* Select the mode starting the AD conversion */
+void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption)
+{
+	if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
+		IP_ADC_EdgeStartConfig(pADC, (uint8_t) EdgeOption);
+	}
+	IP_ADC_SetStartMode(pADC, (uint8_t) mode);
+}
+
+/* Set the ADC Sample rate */
+void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate)
+{
+	ADCSetup->adcRate = rate;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+
+}
+
+/* Set the ADC accuracy bits */
+void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution)
+{
+	ADCSetup->bitsAccuracy = resolution;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+}
+
+/* Enable or disable the ADC channel on ADC peripheral */
+void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState)
+{
+	IP_ADC_SetChannelNumber(pADC, channel, NewState);
+	active_channel = channel;
+}
+
+/* Enable burst mode */
+void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
+{
+	IP_ADC_SetStartMode(pADC, ADC_NO_START);
+	IP_ADC_SetBurstMode(pADC, NewState);
+}
+
+/* Read the ADC value and convert it to 8bits value */
+Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data)
+{
+	uint16_t temp;
+	Status rt;
+
+	rt = IP_ADC_Get_Val(pADC, active_channel, &temp);
+	*data = (uint8_t) temp;
+
+	return rt;
+}
+
+/* Set a channel to be read A/D data */
+void Chip_ADC_Active_Channel(uint8_t channel)
+{
+	active_channel = channel;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h

@@ -0,0 +1,240 @@
+/*
+ * @brief LPC18xx/43xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_18XX_43XX_H_
+#define __ADC_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** The channels on one ADC peripheral*/
+typedef enum ADC_Channel {
+	ADC_CH0 = 0,	/**< ADC channel 0 */
+	ADC_CH1,		/**< ADC channel 1 */
+	ADC_CH2,		/**< ADC channel 2 */
+	ADC_CH3,		/**< ADC channel 3 */
+	ADC_CH4,		/**< ADC channel 4 */
+	ADC_CH5,		/**< ADC channel 5 */
+	ADC_CH6,		/**< ADC channel 6 */
+	ADC_CH7,		/**< ADC channel 7 */
+} ADC_Channel;
+
+/** The number of bits of accuracy of the result in the LS bits of ADDR*/
+typedef enum ADC_Resolution {
+	ADC_10BITS = 0,		/**< ADC 10 bits */
+	ADC_9BITS,			/**< ADC 9 bits  */
+	ADC_8BITS,			/**< ADC 8 bits  */
+	ADC_7BITS,			/**< ADC 7 bits  */
+	ADC_6BITS,			/**< ADC 6 bits  */
+	ADC_5BITS,			/**< ADC 5 bits  */
+	ADC_4BITS,			/**< ADC 4 bits  */
+	ADC_3BITS,			/**< ADC 3 bits  */
+} ADC_Resolution;
+
+/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
+typedef enum ADC_EdgeCfg {
+	ADC_TRIGGERMODE_RISING = 0,		/**< Trigger event: rising edge */
+	ADC_TRIGGERMODE_FALLING,		/**< Trigger event: falling edge */
+} ADC_EdgeCfg;
+
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum ADC_StartMode {
+	ADC_NO_START = 0,
+	ADC_START_NOW,			/*!< Start conversion now */
+	ADC_START_ON_CTOUT15,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+	ADC_START_ON_CTOUT8,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+	ADC_START_ON_ADCTRIG0,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+	ADC_START_ON_ADCTRIG1,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+	ADC_START_ON_MCOA2		/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_StartMode;
+
+/** Clock setup structure for ADC controller passed to the initialize function */
+typedef struct {
+	uint32_t adcPerClock;	/*!< ADC peripheral Clock */
+	uint32_t adcRate;		/*!< ADC rate */
+	uint8_t  bitsAccuracy;	/*!< ADC bit accuracy */
+} ADC_Clock_Setup_Type;
+
+/**
+ * @brief	Read the ADC value from a channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	data		: Pointer to where to put data
+ * @return	SUCCESS or ERROR if no conversion is ready
+ */
+STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_Type *pADC, uint8_t channel, uint16_t *data)
+{
+	return IP_ADC_Get_Val(pADC, channel, data);
+}
+
+/**
+ * @brief	Read the ADC channel status
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	StatusType	: Status type of ADC_DR_*
+ * @return	SET or RESET
+ */
+STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_Type *pADC, uint8_t channel, uint32_t StatusType)
+{
+	return IP_ADC_GetStatus(pADC, channel, StatusType);
+}
+
+/**
+ * @brief	Enable/Disable interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	SET or RESET
+ */
+STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_Type *pADC, uint8_t channel, FunctionalState NewState)
+{
+	IP_ADC_Int_Enable(pADC, channel, NewState);
+}
+
+/**
+ * @brief	Enable/Disable global interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
+{
+	IP_ADC_Int_Enable(pADC, 8, NewState);
+}
+
+/**
+ * @brief	Shutdown ADC
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ADC_DeInit(LPC_ADC_Type *pADC)
+{
+	IP_ADC_DeInit(pADC);
+}
+
+/**
+ * @brief	Initialize the ADC peripheral and the ADC setup structure to default value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be set
+ * @return	Nothing
+ * Default setting for ADC is 400kHz - 10bits
+ */
+void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup);
+
+/**
+ * @brief	Select the mode starting the AD conversion
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	mode		: Stating mode, should be :
+ *							- ADC_NO_START				: Must be set for Burst mode
+ *							- ADC_START_NOW				: Start conversion now
+ *							- ADC_START_ON_CTOUT15		: Start conversion when the edge selected by bit 27 occurs on CTOUT_15
+ *							- ADC_START_ON_CTOUT8		: Start conversion when the edge selected by bit 27 occurs on CTOUT_8
+ *							- ADC_START_ON_ADCTRIG0		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
+ *							- ADC_START_ON_ADCTRIG1		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
+ *							- ADC_START_ON_MCOA2		: Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
+ * @param	EdgeOption	: Stating Edge Condition, should be :
+ *							- ADC_TRIGGERMODE_RISING	: Trigger event on rising edge
+ *							- ADC_TRIGGERMODE_FALLING	: Trigger event on falling edge
+ * @return	Nothing
+ */
+void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption);
+
+/**
+ * @brief	Set the ADC Sample rate
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	rate		: Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
+ * @return	Nothing
+ */
+void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate);
+
+/**
+ * @brief	Set the ADC accuracy bits
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	resolution	: The resolution, should be ADC_10BITS -> ADC_3BITS
+ * @return	Nothing
+ */
+void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution);
+
+/**
+ * @brief	Enable or disable the ADC channel on ADC peripheral
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel to be enable or disable
+ * @param	NewState	: New state, should be:
+ *								- ENABLE
+ *								- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState);
+
+/**
+ * @brief	Enable burst mode
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, should be:
+ *							- ENABLE
+ *							- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState);
+
+/**
+ * @brief	Read the ADC value and convert it to 8bits value
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @param	data	: Storage for data
+ * @return	Status	: ERROR or SUCCESS
+ */
+Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data);
+
+/**
+ * @brief	Set a channel to be read A/D data
+ * @param	channel	: Channel to be active
+ * @return	Nothing
+ */
+void Chip_ADC_Active_Channel(uint8_t channel);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c

@@ -0,0 +1,55 @@
+/*
+ * @brief LPC18xx/43xx ATimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "atimer_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize Alarm Timer */
+void Chip_ATIMER_Init(uint32_t PresetValue)
+{
+	Chip_ATIMER_UpdatePresetValue(PresetValue);
+	Chip_ATIMER_ClearIntStatus();
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h

@@ -0,0 +1,117 @@
+/*
+ * @brief LPC18xx/43xx ATimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ATIMER_18XX_43XX_H_
+#define __ATIMER_18XX_43XX_H_
+
+#include "chip.h"
+
+/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize Alarm Timer
+ * @param PresetValue Count of 1 to 1024s for Alarm
+ * @return	None
+ */
+void Chip_ATIMER_Init(uint32_t PresetValue);
+
+/**
+ * @brief	Close ATIMER device
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_DeInit(void)
+{
+	IP_ATIMER_DeInit(LPC_ATIMER);
+}
+
+/**
+ * @brief	Enable ATIMER Interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_IntEnable(void)
+{
+	IP_ATIMER_IntEnable(LPC_ATIMER);
+}
+
+/**
+ * @brief	Disable ATIMER Interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_IntDisable(void)
+{
+	IP_ATIMER_IntDisable(LPC_ATIMER);
+}
+
+/**
+ * @brief	Clear ATIMER Interrupt Status
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_ClearIntStatus(void)
+{
+	IP_ATIMER_ClearIntStatus(LPC_ATIMER);
+}
+
+/**
+ * @brief	Set ATIMER Interrupt Status
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_SetIntStatus(void)
+{
+	IP_ATIMER_SetIntStatus(LPC_ATIMER);
+}
+
+/**
+ * @brief	Update Preset value
+ * @param	PresetValue	: updated preset value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ATIMER_UpdatePresetValue(uint32_t PresetValue)
+{
+	IP_ATIMER_UpdatePresetValue(LPC_ATIMER, PresetValue);
+}
+
+/**
+ * @brief	Read value of preset register
+ * @return	Value of capture register
+ */
+STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(void)
+{
+	return IP_ATIMER_GetPresetValue(LPC_ATIMER);
+}
+
+/**
+ * @}
+ */
+
+ #endif /* __ATIMER_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h

@@ -0,0 +1,104 @@
+/*
+ * @brief CGU/CCU registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CGUCCU_18XX_43XX_H_
+#define __CGUCCU_18XX_43XX_H_
+
+#include "cmsis.h"
+#include "chip_clocks.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup CLOCK_18XX_43XX
+ * @{
+ */
+
+/**
+ * @brief LPC18XX/43XX CGU register block structure
+ */
+typedef struct {							/*!< (@ 0x40050000) CGU Structure          */
+	__I  uint32_t  RESERVED0[5];
+	__IO uint32_t  FREQ_MON;				/*!< (@ 0x40050014) Frequency monitor register */
+	__IO uint32_t  XTAL_OSC_CTRL;			/*!< (@ 0x40050018) Crystal oscillator control register */
+	__I  uint32_t  PLL0USB_STAT;			/*!< (@ 0x4005001C) PLL0 (USB) status register */
+	__IO uint32_t  PLL0USB_CTRL;			/*!< (@ 0x40050020) PLL0 (USB) control register */
+	__IO uint32_t  PLL0USB_MDIV;			/*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+	__IO uint32_t  PLL0USB_NP_DIV;			/*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+	__I  uint32_t  PLL0AUDIO_STAT;			/*!< (@ 0x4005002C) PLL0 (audio) status register */
+	__IO uint32_t  PLL0AUDIO_CTRL;			/*!< (@ 0x40050030) PLL0 (audio) control register */
+	__IO uint32_t  PLL0AUDIO_MDIV;			/*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+	__IO uint32_t  PLL0AUDIO_NP_DIV;		/*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+	__IO uint32_t  PLL0AUDIO_FRAC;			/*!< (@ 0x4005003C) PLL0 (audio)           */
+	__I  uint32_t  PLL1_STAT;				/*!< (@ 0x40050040) PLL1 status register   */
+	__IO uint32_t  PLL1_CTRL;				/*!< (@ 0x40050044) PLL1 control register  */
+	__IO uint32_t  IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
+	__IO uint32_t  BASE_CLK[CLK_BASE_LAST];	/*!< (@ 0x4005005C) Start of base clock registers */
+} LPC_CGU_T;
+
+/**
+ * @brief CCU clock config/status register pair
+ */
+typedef struct {
+	__IO uint32_t  CFG;						/*!< CCU clock configuration register */
+	__I  uint32_t  STAT;					/*!< CCU clock status register */
+} CCU_CFGSTAT_T;
+
+/**
+ * @brief CCU1 register block structure
+ */
+typedef struct {							/*!< (@ 0x40051000) CCU1 Structure         */
+	__IO uint32_t  PM;						/*!< (@ 0x40051000) CCU1 power mode register */
+	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40051004) CCU1 base clocks status register */
+	__I  uint32_t  RESERVED0[62];
+	CCU_CFGSTAT_T  CLKCCU[CLK_CCU1_LAST];	/*!< (@ 0x40051100) Start of CCU1 clock registers */
+} LPC_CCU1_Type;
+
+/**
+ * @brief CCU2 register block structure
+ */
+typedef struct {							/*!< (@ 0x40052000) CCU2 Structure         */
+	__IO uint32_t  PM;						/*!< (@ 0x40052000) Power mode register    */
+	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40052004) CCU base clocks status register */
+	__I  uint32_t  RESERVED0[62];
+	CCU_CFGSTAT_T  CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST];	/*!< (@ 0x40052100) Start of CCU2 clock registers */
+} LPC_CCU2_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CGUCCU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h

@@ -0,0 +1,44 @@
+/*
+ * @brief Chip inclusion selector file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "sys_config.h"
+
+#if defined(CHIP_LPC18XX)
+#include "chip_lpc18xx.h"
+
+#elif defined(CHIP_LPC43XX)
+#include "chip_lpc43xx.h"
+
+#else
+#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
+#endif
+
+#endif /* __CHIP_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox

@@ -0,0 +1,51 @@
+/*
+ * @brief LPCOpen 18xx/43xx chip group page
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+/** @defgroup CHIP_18XX_43XX_Drivers LPC18XX/43XX chip specific drivers
+ * @ingroup Chip_Drivers
+ * @{
+ */
+
+/** @defgroup CHIP_18XX_43XX_DRIVER_OPTIONS CHIP: LPC18XX/43XX Chip driver build time options
+ * Some chip drivers require build-time configuration. Using a build-time
+ * configuration option allows the driver to be smaller and faster. A
+ * build-time option is configured by the use of a definition passed to
+ * the compiler during the build.
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h

@@ -0,0 +1,252 @@
+/*
+ * @brief	LPC18xx/43xx chip clock list used by CGU and CCU drivers
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_CLOCKS_H_
+#define __CHIP_CLOCKS_H_
+
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup CLOCK_18XX_43XX
+ * @{
+ */
+
+/**
+ * @brief CGU clock input list
+ * These are possible input clocks for the CGU and can come
+ * from both external (crystal) and internal (PLL) sources. These
+ * clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T).
+ */
+typedef enum {
+	CLKIN_32K,		/*!< External 32KHz input */
+	CLKIN_IRC,		/*!< Internal IRC (12MHz) input */
+	CLKIN_ENET_RX,	/*!< External ENET_RX pin input */
+	CLKIN_ENET_TX,	/*!< External ENET_TX pin input */
+	CLKIN_CLKIN,	/*!< External GPCLKIN pin input */
+	CLKIN_RESERVED1,
+	CLKIN_CRYSTAL,	/*!< External (main) crystal pin input */
+	CLKIN_USBPLL,	/*!< Internal USB PLL input */
+	CLKIN_AUDIOPLL,	/*!< Internal Audio PLL input */
+	CLKIN_MAINPLL,	/*!< Internal Main PLL input */
+	CLKIN_RESERVED2,
+	CLKIN_RESERVED3,
+	CLKIN_IDIVA,	/*!< Internal divider A input */
+	CLKIN_IDIVB,	/*!< Internal divider B input */
+	CLKIN_IDIVC,	/*!< Internal divider C input */
+	CLKIN_IDIVD,	/*!< Internal divider D input */
+	CLKIN_IDIVE,	/*!< Internal divider E input */
+	CLKINPUT_PD		/*!< External 32KHz input */
+} CGU_CLKIN_T;
+
+/**
+ * @brief CGU base clocks
+ * CGU base clocks are clocks that are associated with a single input clock
+ * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
+ * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
+ * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
+ * CLK_PERIPH_SGPIO periphral clocks.
+ */
+typedef enum {
+	CLK_BASE_SAFE,		/*!< Base clock for WDT oscillator, IRC input only */
+	CLK_BASE_USB0,		/*!< Base USB clock for USB0, USB PLL input only */
+#if defined(CHIP_LPC43XX)
+	CLK_BASE_PERIPH,	/*!< Base clock for SGPIO */
+#else
+	CLK_BASE_RESERVED1,
+#endif
+	CLK_BASE_USB1,		/*!< Base USB clock for USB1 */
+	CLK_BASE_MX,		/*!< Base clock for CPU core */
+	CLK_BASE_SPIFI,		/*!< Base clock for SPIFI */
+#if defined(CHIP_LPC43XX)
+	CLK_BASE_SPI,		/*!< Base clock for SPI */
+#else
+	CLK_BASE_RESERVED2,
+#endif
+	CLK_BASE_PHY_RX,	/*!< Base clock for PHY RX */
+	CLK_BASE_PHY_TX,	/*!< Base clock for PHY TX */
+	CLK_BASE_APB1,		/*!< Base clock for APB1 group */
+	CLK_BASE_APB3,		/*!< Base clock for APB3 group */
+	CLK_BASE_LCD,		/*!< Base clock for LCD pixel clock */
+#if defined(CHIP_LPC43XX)
+	CLK_BASE_VADC,		/*!< Base clock for VADC */
+#else
+	CLK_BASE_RESERVED3,
+#endif
+	CLK_BASE_SDIO,		/*!< Base clock for SDIO */
+	CLK_BASE_SSP0,		/*!< Base clock for SSP0 */
+	CLK_BASE_SSP1,		/*!< Base clock for SSP1 */
+	CLK_BASE_UART0,		/*!< Base clock for UART0 */
+	CLK_BASE_UART1,		/*!< Base clock for UART1 */
+	CLK_BASE_UART2,		/*!< Base clock for UART2 */
+	CLK_BASE_UART3,		/*!< Base clock for UART3 */
+	CLK_BASE_OUT,		/*!< Base clock for CLKOUT pin */
+	CLK_BASE_RESERVED4,
+	CLK_BASE_RESERVED5,
+	CLK_BASE_RESERVED6,
+	CLK_BASE_RESERVED7,
+	CLK_BASE_APLL,		/*!< Base clock for audio PLL */
+	CLK_BASE_CGU_OUT0,	/*!< Base clock for CGUOUT0 pin */
+	CLK_BASE_CGU_OUT1,	/*!< Base clock for CGUOUT1 pin */
+	CLK_BASE_LAST,
+	CLK_BASE_NONE = CLK_BASE_LAST
+} CGU_BASE_CLK_T;
+
+/**
+ * @brief CGU dividers
+ * CGU dividers provide an extra clock state where a specific clock can be
+ * divided before being routed to a peripheral group. A divider accepts an
+ * input clock and then divides it. To use the divided clock for a base clock
+ * group, use the divider as the input clock for the base clock (for example,
+ * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
+ */
+typedef enum {
+	CLK_IDIV_A,		/*!< CGU clock divider A */
+	CLK_IDIV_B,		/*!< CGU clock divider B */
+	CLK_IDIV_C,		/*!< CGU clock divider A */
+	CLK_IDIV_D,		/*!< CGU clock divider D */
+	CLK_IDIV_E,		/*!< CGU clock divider E */
+	CLK_IDIV_LAST
+} CGU_IDIV_T;
+
+/**
+ * @brief Peripheral clocks
+ * Peripheral clocks are individual clocks routed to peripherals. Although
+ * multiple peripherals may share a same base clock, each peripheral's clock
+ * can be enabled or disabled individually. Some peripheral clocks also have
+ * additional dividers associated with them.
+ */
+typedef enum {
+	/* CCU1 clocks */
+	CLK_APB3_BUS,		/*!< APB3 bus clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_I2C1,		/*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_DAC,		/*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_ADC0,		/*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_ADC1,		/*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB3_CAN0,		/*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
+	CLK_APB1_BUS = 32,	/*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_MOTOCON,	/*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_I2C0,		/*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_I2S,		/*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_APB1_CAN1,		/*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
+	CLK_SPIFI = 64,		/*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
+	CLK_MX_BUS = 96,	/*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
+	CLK_MX_SPIFI,		/*!< SPIFI register clock from base clock CLK_BASE_MX */
+	CLK_MX_GPIO,		/*!< GPIO register clock from base clock CLK_BASE_MX */
+	CLK_MX_LCD,			/*!< LCD register clock from base clock CLK_BASE_MX */
+	CLK_MX_ETHERNET,	/*!< ETHERNET register clock from base clock CLK_BASE_MX */
+	CLK_MX_USB0,		/*!< USB0 register clock from base clock CLK_BASE_MX */
+	CLK_MX_EMC,			/*!< EMC clock from base clock CLK_BASE_MX */
+	CLK_MX_SDIO,		/*!< SDIO register clock from base clock CLK_BASE_MX */
+	CLK_MX_DMA,			/*!< DMA register clock from base clock CLK_BASE_MX */
+	CLK_MX_MXCORE,		/*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
+	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
+	CLK_MX_SCT,			/*!< SCT register clock from base clock CLK_BASE_MX */
+	CLK_MX_USB1,		/*!< USB1 register clock from base clock CLK_BASE_MX */
+	CLK_MX_EMC_DIV,		/*!< ENC divider clock from base clock CLK_BASE_MX */
+	CLK_MX_FLASHA,		/*!< FLASHA bank clock from base clock CLK_BASE_MX */
+	CLK_MX_FLASHB,		/*!< FLASHB bank clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+	CLK_M4_M0APP,		/*!< M0 app CPU core clock from base clock CLK_BASE_MX */
+	CLK_MX_VADC,		/*!< VADC clock from base clock CLK_BASE_MX */
+#else
+	CLK_RESERVED1,
+	CLK_RESERVED2,
+#endif
+	CLK_MX_EEPROM,		/*!< EEPROM clock from base clock CLK_BASE_MX */
+	CLK_MX_WWDT = 128,	/*!< WWDT register clock from base clock CLK_BASE_MX */
+	CLK_MX_UART0,		/*!< UART0 register clock from base clock CLK_BASE_MX */
+	CLK_MX_UART1,		/*!< UART1 register clock from base clock CLK_BASE_MX */
+	CLK_MX_SSP0,		/*!< SSP0 register clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER0,		/*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER1,		/*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_SCU,			/*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_CREG,		/*!< CREG clock from base clock CLK_BASE_MX */
+	CLK_MX_RITIMER = 160,	/*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_UART2,		/*!< UART3 register clock from base clock CLK_BASE_MX */
+	CLK_MX_UART3,		/*!< UART4 register clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER2,		/*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_TIMER3,		/*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
+	CLK_MX_SSP1,		/*!< SSP1 register clock from base clock CLK_BASE_MX */
+	CLK_MX_QEI,			/*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+	CLK_PERIPH_BUS = 192,	/*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
+	CLK_RESERVED3,
+	CLK_PERIPH_CORE,	/*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
+	CLK_PERIPH_SGPIO,	/*!< SGPIO clock from base clock CLK_BASE_PERIPH */
+#else
+	CLK_RESERVED3 = 192,
+	CLK_RESERVED3A,
+	CLK_RESERVED4,
+	CLK_RESERVED5,
+#endif
+	CLK_USB0 = 224,			/*!< USB0 clock from base clock CLK_BASE_USB0 */
+	CLK_USB1 = 256,			/*!< USB1 clock from base clock CLK_BASE_USB1 */
+#if defined(CHIP_LPC43XX)
+	CLK_SPI = 288,			/*!< SPI clock from base clock CLK_BASE_SPI */
+	CLK_VADC,				/*!< VADC clock from base clock CLK_BASE_VADC */
+#else
+	CLK_RESERVED7 = 320,
+	CLK_RESERVED8,
+#endif
+	CLK_CCU1_LAST,
+
+	/* CCU2 clocks */
+	CLK_CCU2_START,
+	CLK_APLL = CLK_CCU2_START,	/*!< Audio PLL clock from base clock CLK_BASE_APLL */
+	RESERVED_ALIGNB = CLK_CCU2_START + 31,
+	CLK_APB2_UART3,			/*!< UART3 clock from base clock CLK_BASE_UART3 */
+	RESERVED_ALIGNC = CLK_CCU2_START + 63,
+	CLK_APB2_UART2,			/*!< UART2 clock from base clock CLK_BASE_UART2 */
+	RESERVED_ALIGND = CLK_CCU2_START + 95,
+	CLK_APB0_UART1,			/*!< UART1 clock from base clock CLK_BASE_UART1 */
+	RESERVED_ALIGNE = CLK_CCU2_START + 127,
+	CLK_APB0_UART0,			/*!< UART0 clock from base clock CLK_BASE_UART0 */
+	RESERVED_ALIGNF = CLK_CCU2_START + 159,
+	CLK_APB2_SSP1,			/*!< SSP1 clock from base clock CLK_BASE_SSP1 */
+	RESERVED_ALIGNG = CLK_CCU2_START + 191,
+	CLK_APB0_SSP0,			/*!< SSP0 clock from base clock CLK_BASE_SSP0 */
+	RESERVED_ALIGNH = CLK_CCU2_START + 223,
+	CLK_APB2_SDIO,			/*!< SDIO clock from base clock CLK_BASE_SDIO */
+	CLK_CCU2_LAST
+} CCU_CLK_T;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_CLOCKS_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h

@@ -0,0 +1,240 @@
+/*
+ * @brief LPC18xx basic chip inclusion file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC18XX_H_
+#define __CHIP_LPC18XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifndef CORE_M3
+#error CORE_M3 is not defined for the LPC18xx architecture
+#error CORE_M3 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC18XX
+#error The LPC18XX Chip include path is used for this build, but
+#error CHIP_LPC18XX is not defined!
+#endif
+
+#include "adc_001.h"
+#include "atimer_001.h"
+#include "ccan_001.h"
+#include "dac_001.h"
+#include "emc_001.h"
+#include "enet_001.h"
+#include "gima_001.h"
+#include "gpdma_001.h"
+#include "gpiogrpint_001.h"
+#include "gpiopinint_001.h"
+#include "gpio_001.h"
+#include "i2c_001.h"
+#include "i2s_001.h"
+#include "lcd_001.h"
+#include "mcpwm_001.h"
+#include "pmc_001.h"
+#include "qei_001.h"
+#include "regfile_001.h"
+#include "ritimer_001.h"
+#include "rtc_001.h"
+#include "sct_001.h"
+#include "sdmmc_001.h"
+#include "ssp_001.h"
+#include "timer_001.h"
+#include "usart_001.h"
+#include "usbhs_001.h"
+#include "wwdt_001.h"
+#include "spifi_001.h"
+#include "rgu_18xx_43xx.h"
+#include "cguccu_18xx_43xx.h"
+
+/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#define LPC_SCT_BASE              0x40000000
+#define LPC_GPDMA_BASE            0x40002000
+#define LPC_SDMMC_BASE            0x40004000
+#define LPC_EMC_BASE              0x40005000
+#define LPC_USB0_BASE             0x40006000
+#define LPC_USB1_BASE             0x40007000
+#define LPC_LCD_BASE              0x40008000
+#define LPC_ETHERNET_BASE         0x40010000
+#define LPC_ATIMER_BASE           0x40040000
+#define LPC_REGFILE_BASE          0x40041000
+#define LPC_PMC_BASE              0x40042000
+#define LPC_CREG_BASE             0x40043000
+#define LPC_EVRT_BASE             0x40044000
+#define LPC_RTC_BASE              0x40046000
+#define LPC_CGU_BASE              0x40050000
+#define LPC_CCU1_BASE             0x40051000
+#define LPC_CCU2_BASE             0x40052000
+#define LPC_RGU_BASE              0x40053000
+#define LPC_WWDT_BASE             0x40080000
+#define LPC_USART0_BASE           0x40081000
+#define LPC_USART2_BASE           0x400C1000
+#define LPC_USART3_BASE           0x400C2000
+#define LPC_UART1_BASE            0x40082000
+#define LPC_SSP0_BASE             0x40083000
+#define LPC_SSP1_BASE             0x400C5000
+#define LPC_TIMER0_BASE           0x40084000
+#define LPC_TIMER1_BASE           0x40085000
+#define LPC_TIMER2_BASE           0x400C3000
+#define LPC_TIMER3_BASE           0x400C4000
+#define LPC_SCU_BASE              0x40086000
+#define LPC_GPIO_PIN_INT_BASE     0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
+#define LPC_MCPWM_BASE            0x400A0000
+#define LPC_I2C0_BASE             0x400A1000
+#define LPC_I2C1_BASE             0x400E0000
+#define LPC_I2S0_BASE             0x400A2000
+#define LPC_I2S1_BASE             0x400A3000
+#define LPC_C_CAN1_BASE           0x400A4000
+#define LPC_RITIMER_BASE          0x400C0000
+#define LPC_QEI_BASE              0x400C6000
+#define LPC_GIMA_BASE             0x400C7000
+#define LPC_DAC_BASE              0x400E1000
+#define LPC_C_CAN0_BASE           0x400E2000
+#define LPC_ADC0_BASE             0x400E3000
+#define LPC_ADC1_BASE             0x400E4000
+#define LPC_GPIO_PORT_BASE        0x400F4000
+#define LPC_SPI_BASE              0x40100000
+#define LPC_SGPIO_BASE            0x40101000
+
+/* Normalize types */
+typedef IP_SCT_001_Type LPC_SCT_Type;
+typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
+typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
+typedef IP_EMC_001_Type LPC_EMC_Type;
+typedef IP_USBHS_001_Type LPC_USBHS_Type;
+typedef IP_ENET_001_Type LPC_ENET_Type;
+typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
+typedef IP_REGFILE_001_T LPC_REGFILE_T;
+typedef IP_PMC_001_Type LPC_PMC_Type;
+typedef IP_RTC_001_T LPC_RTC_Type;
+typedef IP_WWDT_001_Type LPC_WWDT_Type;
+typedef IP_USART_001_Type LPC_USART_Type;
+typedef IP_SSP_001_Type LPC_SSP_Type;
+typedef IP_TIMER_001_Type LPC_TIMER_Type;
+typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
+typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
+typedef IP_I2C_001_Type LPC_I2C_Type;
+typedef IP_I2S_001_Type LPC_I2S_Type;
+typedef IP_CCAN_001_Type LPC_CCAN_Type;
+typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
+typedef IP_QEI_001_Type LPC_QEI_Type;
+typedef IP_GIMA_001_Type LPC_GIMA_Type;
+typedef IP_DAC_001_Type LPC_DAC_Type;
+typedef IP_ADC_001_Type LPC_ADC_Type;
+typedef IP_GPIO_001_Type LPC_GPIO_Type;
+typedef IP_LCD_001_Type LPC_LCD_Type;
+
+#define LPC_SCT                   ((IP_SCT_001_Type              *) LPC_SCT_BASE)
+#define LPC_GPDMA                 ((IP_GPDMA_001_Type            *) LPC_GPDMA_BASE)
+#define LPC_SDMMC                 ((IP_SDMMC_001_Type            *) LPC_SDMMC_BASE)
+#define LPC_EMC                   ((IP_EMC_001_Type              *) LPC_EMC_BASE)
+#define LPC_USB0                  ((IP_USBHS_001_Type            *) LPC_USB0_BASE)
+#define LPC_USB1                  ((IP_USBHS_001_Type            *) LPC_USB1_BASE)
+#define LPC_LCD                   ((IP_LCD_001_Type              *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((IP_ENET_001_Type             *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER                ((IP_ATIMER_001_Type           *) LPC_ATIMER_BASE)
+#define LPC_REGFILE               ((IP_REGFILE_001_T             *) LPC_REGFILE_BASE)
+#define LPC_PMC                   ((IP_PMC_001_Type              *) LPC_PMC_BASE)
+#define LPC_EVRT                  ((LPC_EVRT_Type                *) LPC_EVRT_BASE)
+#define LPC_RTC                   ((IP_RTC_001_T                 *) LPC_RTC_BASE)
+#define LPC_CGU                   ((LPC_CGU_T                    *) LPC_CGU_BASE)
+#define LPC_CCU1                  ((LPC_CCU1_Type                *) LPC_CCU1_BASE)
+#define LPC_CCU2                  ((LPC_CCU2_Type                *) LPC_CCU2_BASE)
+#define LPC_CREG                  ((LPC_CREG_T                   *) LPC_CREG_BASE)
+#define LPC_RGU                   ((LPC_RGU_T                    *) LPC_RGU_BASE)
+#define LPC_WWDT                  ((IP_WWDT_001_Type             *) LPC_WWDT_BASE)
+#define LPC_USART0                ((IP_USART_001_Type            *) LPC_USART0_BASE)
+#define LPC_USART2                ((IP_USART_001_Type            *) LPC_USART2_BASE)
+#define LPC_USART3                ((IP_USART_001_Type            *) LPC_USART3_BASE)
+#define LPC_UART1                 ((IP_USART_001_Type            *) LPC_UART1_BASE)
+#define LPC_SSP0                  ((IP_SSP_001_Type              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((IP_SSP_001_Type              *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((IP_TIMER_001_Type            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((IP_TIMER_001_Type            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((IP_TIMER_001_Type            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((IP_TIMER_001_Type            *) LPC_TIMER3_BASE)
+#define LPC_SCU                   ((LPC_SCU_Type                 *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT          ((IP_GPIOPININT_001_Type       *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM                 ((IP_MCPWM_001_Type            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((IP_I2C_001_Type              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((IP_I2C_001_Type              *) LPC_I2C1_BASE)
+#define LPC_I2S0                  ((IP_I2S_001_Type              *) LPC_I2S0_BASE)
+#define LPC_I2S1                  ((IP_I2S_001_Type              *) LPC_I2S1_BASE)
+#define LPC_C_CAN1                ((IP_CCAN_001_Type             *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER               ((IP_RITIMER_001_Type          *) LPC_RITIMER_BASE)
+#define LPC_QEI                   ((IP_QEI_001_Type              *) LPC_QEI_BASE)
+#define LPC_GIMA                  ((IP_GIMA_001_Type             *) LPC_GIMA_BASE)
+#define LPC_DAC                   ((IP_DAC_001_Type              *) LPC_DAC_BASE)
+#define LPC_C_CAN0                ((IP_CCAN_001_Type             *) LPC_C_CAN0_BASE)
+#define LPC_ADC0                  ((IP_ADC_001_Type              *) LPC_ADC0_BASE)
+#define LPC_ADC1                  ((IP_ADC_001_Type              *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT             ((IP_GPIO_001_Type             *) LPC_GPIO_PORT_BASE)
+
+/**
+ * @}
+ */
+
+#include "clock_18xx_43xx.h"
+#include "gpio_18xx_43xx.h"
+#include "uart_18xx_43xx.h"
+#include "gpdma_18xx_43xx.h"
+#include "enet_18xx_43xx.h"
+#include "i2c_18xx_43xx.h"
+#include "i2s_18xx_43xx.h"
+#include "ssp_18xx_43xx.h"
+#include "rtc_18xx_43xx.h"
+#include "evrt_18xx_43xx.h"
+#include "atimer_18xx_43xx.h"
+#include "wwdt_18xx_43xx.h"
+#include "ritimer_18xx_43xx.h"
+#include "emc_18xx_43xx.h"
+#include "lcd_18xx_43xx.h"
+#include "adc_18xx_43xx.h"
+#include "sdmmc_18xx_43xx.h"
+#include "timer_18xx_43xx.h"
+#include "creg_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC18XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h

@@ -0,0 +1,248 @@
+/*
+ * @brief LPC43xx basic chip inclusion file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC43XX_H_
+#define __CHIP_LPC43XX_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(CORE_M4) && !defined(CORE_M0)
+#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture
+#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC43XX
+#error The LPC43XX Chip include path is used for this build, but
+#error CHIP_LPC43XX is not defined!
+#endif
+
+#include "adc_001.h"
+#include "atimer_001.h"
+#include "ccan_001.h"
+#include "dac_001.h"
+#include "emc_001.h"
+#include "enet_001.h"
+#include "gima_001.h"
+#include "gpdma_001.h"
+#include "gpiogrpint_001.h"
+#include "gpiopinint_001.h"
+#include "gpio_001.h"
+#include "i2c_001.h"
+#include "i2s_001.h"
+#include "lcd_001.h"
+#include "mcpwm_001.h"
+#include "pmc_001.h"
+#include "qei_001.h"
+#include "regfile_001.h"
+#include "ritimer_001.h"
+#include "rtc_001.h"
+#include "sct_001.h"
+#include "sdmmc_001.h"
+#include "sgpio_001.h"
+#include "spi_001.h"
+#include "ssp_001.h"
+#include "timer_001.h"
+#include "usart_001.h"
+#include "usbhs_001.h"
+#include "wwdt_001.h"
+#include "spifi_001.h"
+#include "rgu_18xx_43xx.h"
+#include "cguccu_18xx_43xx.h"
+
+/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#define LPC_SCT_BASE              0x40000000
+#define LPC_GPDMA_BASE            0x40002000
+#define LPC_SDMMC_BASE            0x40004000
+#define LPC_EMC_BASE              0x40005000
+#define LPC_USB0_BASE             0x40006000
+#define LPC_USB1_BASE             0x40007000
+#define LPC_LCD_BASE              0x40008000
+#define LPC_ETHERNET_BASE         0x40010000
+#define LPC_ATIMER_BASE           0x40040000
+#define LPC_REGFILE_BASE          0x40041000
+#define LPC_PMC_BASE              0x40042000
+#define LPC_CREG_BASE             0x40043000
+#define LPC_EVRT_BASE             0x40044000
+#define LPC_RTC_BASE              0x40046000
+#define LPC_CGU_BASE              0x40050000
+#define LPC_CCU1_BASE             0x40051000
+#define LPC_CCU2_BASE             0x40052000
+#define LPC_RGU_BASE              0x40053000
+#define LPC_WWDT_BASE             0x40080000
+#define LPC_USART0_BASE           0x40081000
+#define LPC_USART2_BASE           0x400C1000
+#define LPC_USART3_BASE           0x400C2000
+#define LPC_UART1_BASE            0x40082000
+#define LPC_SSP0_BASE             0x40083000
+#define LPC_SSP1_BASE             0x400C5000
+#define LPC_TIMER0_BASE           0x40084000
+#define LPC_TIMER1_BASE           0x40085000
+#define LPC_TIMER2_BASE           0x400C3000
+#define LPC_TIMER3_BASE           0x400C4000
+#define LPC_SCU_BASE              0x40086000
+#define LPC_GPIO_PIN_INT_BASE     0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
+#define LPC_MCPWM_BASE            0x400A0000
+#define LPC_I2C0_BASE             0x400A1000
+#define LPC_I2C1_BASE             0x400E0000
+#define LPC_I2S0_BASE             0x400A2000
+#define LPC_I2S1_BASE             0x400A3000
+#define LPC_C_CAN1_BASE           0x400A4000
+#define LPC_RITIMER_BASE          0x400C0000
+#define LPC_QEI_BASE              0x400C6000
+#define LPC_GIMA_BASE             0x400C7000
+#define LPC_DAC_BASE              0x400E1000
+#define LPC_C_CAN0_BASE           0x400E2000
+#define LPC_ADC0_BASE             0x400E3000
+#define LPC_ADC1_BASE             0x400E4000
+#define LPC_GPIO_PORT_BASE        0x400F4000
+#define LPC_SPI_BASE              0x40100000
+#define LPC_SGPIO_BASE            0x40101000
+
+/* Normalize types */
+typedef IP_SCT_001_Type LPC_SCT_Type;
+typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
+typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
+typedef IP_EMC_001_Type LPC_EMC_Type;
+typedef IP_USBHS_001_Type LPC_USBHS_Type;
+typedef IP_ENET_001_Type LPC_ENET_Type;
+typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
+typedef IP_REGFILE_001_T LPC_REGFILE_Type;
+typedef IP_PMC_001_Type LPC_PMC_Type;
+typedef IP_RTC_001_T LPC_RTC_Type;
+typedef IP_WWDT_001_Type LPC_WWDT_Type;
+typedef IP_USART_001_Type LPC_USART_Type;
+typedef IP_SSP_001_Type LPC_SSP_Type;
+typedef IP_TIMER_001_Type LPC_TIMER_Type;
+typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
+typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
+typedef IP_I2C_001_Type LPC_I2C_Type;
+typedef IP_I2S_001_Type LPC_I2S_Type;
+typedef IP_CCAN_001_Type LPC_CCAN_Type;
+typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
+typedef IP_QEI_001_Type LPC_QEI_Type;
+typedef IP_GIMA_001_Type LPC_GIMA_Type;
+typedef IP_DAC_001_Type LPC_DAC_Type;
+typedef IP_ADC_001_Type LPC_ADC_Type;
+typedef IP_GPIO_001_Type LPC_GPIO_Type;
+typedef IP_SPI_001_Type LPC_SPI_Type;
+typedef IP_SGPIO_001_Type LPC_SGPIO_Type;
+typedef IP_LCD_001_Type LPC_LCD_Type;
+
+#define LPC_SCT                   ((IP_SCT_001_Type              *) LPC_SCT_BASE)
+#define LPC_GPDMA                 ((IP_GPDMA_001_Type            *) LPC_GPDMA_BASE)
+#define LPC_SDMMC                 ((IP_SDMMC_001_Type            *) LPC_SDMMC_BASE)
+#define LPC_EMC                   ((IP_EMC_001_Type              *) LPC_EMC_BASE)
+#define LPC_USB0                  ((IP_USBHS_001_Type            *) LPC_USB0_BASE)
+#define LPC_USB1                  ((IP_USBHS_001_Type            *) LPC_USB1_BASE)
+#define LPC_LCD                   ((IP_LCD_001_Type              *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((IP_ENET_001_Type             *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER                ((IP_ATIMER_001_Type           *) LPC_ATIMER_BASE)
+#define LPC_REGFILE               ((IP_REGFILE_001_T             *) LPC_REGFILE_BASE)
+#define LPC_PMC                   ((IP_PMC_001_Type              *) LPC_PMC_BASE)
+#define LPC_EVRT                  ((LPC_EVRT_Type                *) LPC_EVRT_BASE)
+#define LPC_RTC                   ((IP_RTC_001_T                 *) LPC_RTC_BASE)
+#define LPC_CGU                   ((LPC_CGU_T                    *) LPC_CGU_BASE)
+#define LPC_CCU1                  ((LPC_CCU1_Type                *) LPC_CCU1_BASE)
+#define LPC_CCU2                  ((LPC_CCU2_Type                *) LPC_CCU2_BASE)
+#define LPC_CREG                  ((LPC_CREG_T                   *) LPC_CREG_BASE)
+#define LPC_RGU                   ((LPC_RGU_T                    *) LPC_RGU_BASE)
+#define LPC_WWDT                  ((IP_WWDT_001_Type             *) LPC_WWDT_BASE)
+#define LPC_USART0                ((IP_USART_001_Type            *) LPC_USART0_BASE)
+#define LPC_USART2                ((IP_USART_001_Type            *) LPC_USART2_BASE)
+#define LPC_USART3                ((IP_USART_001_Type            *) LPC_USART3_BASE)
+#define LPC_UART1                 ((IP_USART_001_Type            *) LPC_UART1_BASE)
+#define LPC_SSP0                  ((IP_SSP_001_Type              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((IP_SSP_001_Type              *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((IP_TIMER_001_Type            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((IP_TIMER_001_Type            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((IP_TIMER_001_Type            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((IP_TIMER_001_Type            *) LPC_TIMER3_BASE)
+#define LPC_SCU                   ((LPC_SCU_Type                 *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT          ((IP_GPIOPININT_001_Type       *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM                 ((IP_MCPWM_001_Type            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((IP_I2C_001_Type              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((IP_I2C_001_Type              *) LPC_I2C1_BASE)
+#define LPC_I2S0                  ((IP_I2S_001_Type              *) LPC_I2S0_BASE)
+#define LPC_I2S1                  ((IP_I2S_001_Type              *) LPC_I2S1_BASE)
+#define LPC_C_CAN1                ((IP_CCAN_001_Type             *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER               ((IP_RITIMER_001_Type          *) LPC_RITIMER_BASE)
+#define LPC_QEI                   ((IP_QEI_001_Type              *) LPC_QEI_BASE)
+#define LPC_GIMA                  ((IP_GIMA_001_Type             *) LPC_GIMA_BASE)
+#define LPC_DAC                   ((IP_DAC_001_Type              *) LPC_DAC_BASE)
+#define LPC_C_CAN0                ((IP_CCAN_001_Type             *) LPC_C_CAN0_BASE)
+#define LPC_ADC0                  ((IP_ADC_001_Type              *) LPC_ADC0_BASE)
+#define LPC_ADC1                  ((IP_ADC_001_Type              *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT             ((IP_GPIO_001_Type             *) LPC_GPIO_PORT_BASE)
+#define LPC_SPI                   ((IP_SPI_001_Type              *) LPC_SPI_BASE)
+#define LPC_SGPIO                 ((IP_SGPIO_001_Type            *) LPC_SGPIO_BASE)
+
+/**
+ * @}
+ */
+
+#include "clock_18xx_43xx.h"
+#include "gpio_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+#include "uart_18xx_43xx.h"
+#include "gpdma_18xx_43xx.h"
+#include "enet_18xx_43xx.h"
+#include "rgu_18xx_43xx.h"
+#include "i2c_18xx_43xx.h"
+#include "i2s_18xx_43xx.h"
+#include "ssp_18xx_43xx.h"
+#include "rtc_18xx_43xx.h"
+#include "evrt_18xx_43xx.h"
+#include "atimer_18xx_43xx.h"
+#include "wwdt_18xx_43xx.h"
+#include "ritimer_18xx_43xx.h"
+#include "emc_18xx_43xx.h"
+#include "lcd_18xx_43xx.h"
+#include "adc_18xx_43xx.h"
+#include "timer_18xx_43xx.h"
+#include "sdmmc_18xx_43xx.h"
+#include "fpu_init.h"
+#include "creg_18xx_43xx.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h

@@ -0,0 +1,238 @@
+/*
+ * @brief LPC18xx/43xx clock driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CLOCK_18XX_43XX_H_
+#define __CLOCK_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options
+ * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS 
+ * The clock driver has options that configure it's operation at build-time.<br/>
+ * MAX_CLOCK_FREQ:
+ * - This define, when set, identifies the maximumCPU clock rate of the system (change this to alter running CPU speed)
+ * - When this is not defined, The maximum clock rate for the CPU is used
+ * <br/><p>
+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Internal oscillator frequency */
+#define CGU_IRC_FREQ (12000000)
+
+#ifndef MAX_CLOCK_FREQ
+#if defined(CHIP_LPC43XX)
+#define MAX_CLOCK_FREQ (204000000)
+#else
+#define MAX_CLOCK_FREQ (180000000)
+#endif
+#endif /* MAX_CLOCK_FREQ */
+
+/**
+ * @brief	Enables the crystal oscillator
+ * @return	Nothing
+ */
+void Chip_Clock_EnableCrystal(void);
+
+/**
+ * @brief	Disables the crystal oscillator
+ * @return	Nothing
+ */
+void Chip_Clock_DisableCrystal(void);
+
+/**
+ * @brief   Configures the main PLL
+ * @param   Input		: Which clock input to use as the PLL input
+ * @param   MinHz		: Minimum allowable PLL output frequency
+ * @param   DesiredHz	: Desired PLL output frequency
+ * @param   MaxHz		: Maximum allowable PLL output frequency
+ * @return	Frequency of the PLL in Hz
+ * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz
+ * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if
+ * the PLL is locked.
+ */
+uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
+
+/**
+ * @brief	Directly set the PLL multipler
+ * @param   Input	: Which clock input to use as the PLL input
+ * @param	mult	: How many times to multiply the input clock
+ * @return	Frequency of the PLL in Hz
+ */
+uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult);
+
+/**
+ * @brief   Returns the frequency of the main PLL
+ * @return	Frequency of the PLL in Hz
+ * Returns zero if the main PLL is not running.
+ */
+uint32_t Chip_Clock_GetMainPLLHz(void);
+
+/**
+ * @brief	Disables the main PLL
+ * @return	none
+ * Make sure the main PLL is not needed to clock the part before disabling it.
+ * Saves power if the main PLL is not needed.
+ */
+void Chip_Clock_DisableMainPLL(void);
+
+/**
+ * @brief   Returns the lock status of the main PLL
+ * @return	true if the PLL is locked, otherwise false
+ * The main PLL should be locked prior to using it as a clock input for a base clock.
+ */
+bool Chip_Clock_MainPLLLocked(void);
+
+/**
+ * @brief	Sets up a CGU clock divider and it's input clock
+ * @param	Divider	: CGU_IDIV_T value indicating which divider to configure
+ * @param	Input	: CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
+ * @param	Divisor	: value to divide Input clock by
+ * @return	Nothing
+ */
+void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor);
+
+/**
+ * @brief	Gets a CGU clock divider source
+ * @param	Divider	: CGU_IDIV_T value indicating which divider to get the source of
+ * @return	CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
+ */
+CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider);
+
+/**
+ * @brief	Gets a CGU clock divider divisor
+ * @param	Divider	: CGU_IDIV_T value indicating which divider to get the source of
+ * @return	the divider value for the divider
+ */
+uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider);
+
+/**
+ * @brief	Returns the frequency of the specified input clock source
+ * @param	input	: Which clock input to return the frequency of
+ * @return	Frequency of input source in Hz
+ * This function returns an ideal frequency and not the actual frequency. Returns
+ * zero if the clock source is disabled.
+ */
+uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input);
+
+/**
+ * @brief	Returns the frequency of the specified base clock source
+ * @param	clock	: which base clock to return the frequency of.
+ * @return	Frequency of base source in Hz
+ * This function returns an ideal frequency and not the actual frequency. Returns
+ * zero if the clock source is disabled.
+ */
+uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock);
+
+/**
+ * @brief	Sets a CGU Base Clock clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to set
+ * @param	Input		: CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
+ * @param	autoblocken	: Enables autoblocking during frequency change if true
+ * @param	powerdn		: The clock base is setup, but powered down if true
+ * @return	Nothing
+ */
+void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
+
+/**
+ * @brief	Gets a CGU Base Clock clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for
+ * @return	CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
+ */
+CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock);
+
+/**
+ * @brief	Enables a base clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to enable
+ * @return	Nothing
+ */
+void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock);
+
+/**
+ * @brief	Disables a base clock source
+ * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to disable
+ * @return	Nothing
+ */
+void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock);
+
+/**
+ * @brief	Enables a peripheral clock and sets clock states
+ * @param	clk			: CCU_CLK_T value indicating which clock to enable
+ * @param	autoen		: true to enable autoblocking on a clock rate change, false to disable
+ * @param	wakeupen	: true to enable wakeup mechanism, false to disable
+ * @param	div			: Divider for the clock, must be 1 for most clocks, 2 supported on others
+ * @return	Nothing
+ */
+void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
+
+/**
+ * @brief	Enables a peripheral clock
+ * @param	clk	: CCU_CLK_T value indicating which clock to enable
+ * @return	Nothing
+ */
+void Chip_Clock_Enable(CCU_CLK_T clk);
+
+/**
+ * @brief	Disables a peripheral clock
+ * @param	clk	: CCU_CLK_T value indicating which clock to disable
+ * @return	Nothing
+ */
+void Chip_Clock_Disable(CCU_CLK_T clk);
+
+/**
+ * @brief	Returns a peripheral clock rate
+ * @param	clk	: CCU_CLK_T value indicating which clock to get rate for
+ * @return	0 if the clock is disabled, or the rate of the clock
+ */
+uint32_t Chip_Clock_GetRate(CCU_CLK_T clk);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLOCK_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h

@@ -0,0 +1,355 @@
+/*
+ * @brief Basic CMSIS include file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_H_
+#define __CMSIS_H_
+
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+  #pragma diag_suppress 2525
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+//  #pragma push // FIXME not usable for IAR
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+#if defined(CORE_M4)
+/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions
+ * @{
+ */
+
+#define __CM4_REV              0x0000		/*!< Cortex-M4 Core Revision               */
+#define __MPU_PRESENT             1			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#ifdef CHIP_LPC43XX
+#define __FPU_PRESENT             1			/*!< FPU present or not                    */
+#else
+#define __FPU_PRESENT             0			/*!< FPU present or not                    */
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M4 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+	SVCall_IRQn                       =  -5,/*!<  11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn                 =  -4,/*!<  12  Debug Monitor                    */
+	PendSV_IRQn                       =  -2,/*!<  14  Pendable request for system service */
+	SysTick_IRQn                      =  -1,/*!<  15  System Tick Timer                */
+
+	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
+	DAC_IRQn                          =   0,/*!<   0  DAC                              */
+	M0CORE_IRQn                       =   1,/*!<   1  M0a                              */
+	DMA_IRQn                          =   2,/*!<   2  DMA                              */
+	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
+	RESERVED2_IRQn                    =   4,
+	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
+	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
+	LCD_IRQn                          =   7,/*!<   7  LCD                              */
+	USB0_IRQn                         =   8,/*!<   8  USB0                             */
+	USB1_IRQn                         =   9,/*!<   9  USB1                             */
+	SCT_IRQn                          =  10,/*!<  10  SCT                              */
+	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
+	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
+	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
+	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
+	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
+	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
+	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
+	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
+	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
+	SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */
+	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
+	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
+	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
+	USART0_IRQn                       =  24,/*!<  24  USART0                           */
+	UART1_IRQn                        =  25,/*!<  25  UART1                            */
+	USART2_IRQn                       =  26,/*!<  26  USART2                           */
+	USART3_IRQn                       =  27,/*!<  27  USART3                           */
+	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
+	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
+	RESERVED4_IRQn                    =  30,
+	SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */
+	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
+	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
+	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
+	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
+	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
+	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
+	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
+	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
+	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
+	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
+	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
+	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
+	RESERVED6_IRQn                    =  44,
+	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
+	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
+	RTC_IRQn                          =  47,/*!<  47  RTC                              */
+	RESERVED8_IRQn                    =  48,
+	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
+	RESERVED9_IRQn                    =  50,
+	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
+	QEI_IRQn                          =  52,/*!<  52  QEI                              */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h"						/*!< Cortex-M4 processor and core peripherals */
+
+#elif defined(CORE_M3)
+/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions
+ * @{
+ */
+
+#define __MPU_PRESENT             1			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0			/*!< FPU present or not                    */
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M3 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+	SVCall_IRQn                       = -5,	/*!<  11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn                 = -4,	/*!<  12  Debug Monitor                    */
+	PendSV_IRQn                       = -2,	/*!<  14  Pendable request for system service */
+	SysTick_IRQn                      = -1,	/*!<  15  System Tick Timer                */
+
+	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
+	DAC_IRQn                          =   0,/*!<   0  DAC                              */
+	RESERVED0_IRQn                    =   1,
+	DMA_IRQn                          =   2,/*!<   2  DMA                              */
+	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
+	RESERVED2_IRQn                    =   4,
+	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
+	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
+	LCD_IRQn                          =   7,/*!<   7  LCD                              */
+	USB0_IRQn                         =   8,/*!<   8  USB0                             */
+	USB1_IRQn                         =   9,/*!<   9  USB1                             */
+	SCT_IRQn                          =  10,/*!<  10  SCT                              */
+	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
+	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
+	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
+	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
+	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
+	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
+	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
+	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
+	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
+	RESERVED3_IRQn                    =  20,
+	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
+	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
+	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
+	USART0_IRQn                       =  24,/*!<  24  USART0                           */
+	UART1_IRQn                        =  25,/*!<  25  UART1                            */
+	USART2_IRQn                       =  26,/*!<  26  USART2                           */
+	USART3_IRQn                       =  27,/*!<  27  USART3                           */
+	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
+	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
+	RESERVED4_IRQn                    =  30,
+	RESERVED5_IRQn                    =  31,
+	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
+	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
+	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
+	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
+	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
+	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
+	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
+	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
+	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
+	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
+	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
+	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
+	RESERVED6_IRQn                    =  44,
+	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
+	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
+	RTC_IRQn                          =  47,/*!<  47  RTC                              */
+	RESERVED8_IRQn                    =  48,
+	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
+	RESERVED9_IRQn                    =  50,
+	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
+	QEI_IRQn                          =  52,/*!<  52  QEI                              */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"						/*!< Cortex-M3 processor and core peripherals */
+
+#elif defined(CORE_M0)
+/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions
+ * @{
+ */
+
+#define __MPU_PRESENT             0			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          2			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0			/*!< FPU present or not                    */
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M0 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
+	SVCall_IRQn                       = -5,	/*!<  11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn                 = -4,	/*!<  12  Debug Monitor                    */
+	PendSV_IRQn                       = -2,	/*!<  14  Pendable request for system service */
+	SysTick_IRQn                      = -1,	/*!<  15  System Tick Timer           */
+
+	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
+	DAC_IRQn                          =   0,/*!<   0  DAC                              */
+	M0_M4CORE_IRQn                        =   1,/*!<   1  M0a                              */
+	DMA_IRQn                          =   2,/*!<   2  DMA                              */
+	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
+	RESERVED2_IRQn                    =   4,
+	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
+	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
+	LCD_IRQn                          =   7,/*!<   7  LCD                              */
+	USB0_IRQn                         =   8,/*!<   8  USB0                             */
+	USB1_IRQn                         =   9,/*!<   9  USB1                             */
+	SCT_IRQn                          =  10,/*!<  10  SCT                              */
+	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
+	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
+	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
+	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
+	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
+	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
+	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
+	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
+	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
+	SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */
+	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
+	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
+	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
+	USART0_IRQn                       =  24,/*!<  24  USART0                           */
+	UART1_IRQn                        =  25,/*!<  25  UART1                            */
+	USART2_IRQn                       =  26,/*!<  26  USART2                           */
+	USART3_IRQn                       =  27,/*!<  27  USART3                           */
+	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
+	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
+	RESERVED4_IRQn                    =  30,
+	SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */
+	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
+	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
+	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
+	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
+	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
+	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
+	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
+	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
+	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
+	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
+	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
+	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
+	RESERVED6_IRQn                    =  44,
+	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
+	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
+	RTC_IRQn                          =  47,/*!<  47  RTC                              */
+	RESERVED8_IRQn                    =  48,
+	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
+	RESERVED9_IRQn                    =  50,
+	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
+	QEI_IRQn                          =  52,/*!<  52  QEI                              */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h"						/*!< Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0, CORE_M3, or CORE_M4
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h

@@ -0,0 +1,181 @@
+/*
+ * @brief LPC18XX/43XX CREG control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CREG_18XX_43XX_H_
+#define __CREG_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief CREG Register Block
+ */
+typedef struct {						/*!< CREG Structure         */
+	__I  uint32_t  RESERVED0;
+	__IO uint32_t  CREG0;				/*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
+	__I  uint32_t  RESERVED1[62];
+	__IO uint32_t  MXMEMMAP;			/*!< ARM Cortex-M3/M4 memory mapping */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED2[5];
+#else
+	__I  uint32_t  RESERVED2;
+	__I  uint32_t  CREG1;				/*!< Configuration Register 1 */
+	__I  uint32_t  CREG2;				/*!< Configuration Register 2 */
+	__I  uint32_t  CREG3;				/*!< Configuration Register 3 */
+	__I  uint32_t  CREG4;				/*!< Configuration Register 4 */
+#endif
+	__IO uint32_t  CREG5;				/*!< Chip configuration register 5. Controls JTAG access. */
+	__IO uint32_t  DMAMUX;				/*!< DMA muxing control     */
+	__IO uint32_t  FLASHCFGA;			/*!< Flash accelerator configuration register for flash bank A */
+	__IO uint32_t  FLASHCFGB;			/*!< Flash accelerator configuration register for flash bank B */
+	__IO uint32_t  ETBCFG;				/*!< ETB RAM configuration  */
+	__IO uint32_t  CREG6;				/*!< Chip configuration register 6. */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED4[52];
+#else
+	__IO uint32_t  M4TXEVENT;			/*!< M4 IPC event register */
+	__I  uint32_t  RESERVED4[51];
+#endif
+	__I  uint32_t  CHIPID;				/*!< Part ID                */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED5[191];
+#else
+	__I  uint32_t  RESERVED5[127];
+	__IO uint32_t  M0TXEVENT;			/*!< M0 IPC Event register */
+	__IO uint32_t  M0APPMEMMAP;			/*!< ARM Cortex M0 memory mapping */
+	__I  uint32_t  RESERVED6[62];
+#endif
+	__IO uint32_t  USB0FLADJ;			/*!< USB0 frame length adjust register */
+	__I  uint32_t  RESERVED7[63];
+	__IO uint32_t  USB1FLADJ;			/*!< USB1 frame length adjust register */
+} LPC_CREG_T;
+
+/**
+ * @brief	Identifies whether on-chip flash is present
+ * @return	true if on chip flash is available, otherwise false
+ */
+STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
+{
+	return LPC_CREG->CHIPID != 0x3284E02B;
+}
+
+/**
+ * @brief	Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
+ * @param	Hz	: Current frequency in Hz of the CPU
+ * @return	Nothing
+ * This function should be called with the higher frequency before the clock frequency is
+ * increased and it should be called with the new lower value after the clock frequency is
+ * decreased.
+ */
+STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
+{
+	uint32_t FAValue = Hz / 21510000;
+
+	LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
+	LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
+}
+
+/**
+ * @brief	Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
+ * @param	Enable	: true to enable PHY, false to disable
+ * @return	Nothing
+ * The USB0 PLL & clock should be configured before calling this function. This function
+ * should be called before the USB0 registers are accessed.
+ */
+STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
+{
+	if (Enable) {
+		LPC_CREG->CREG0 &= ~(1 << 5);
+	}
+	else {
+		LPC_CREG->CREG0 |= (1 << 5);
+	}
+}
+
+/**
+ * @brief	Configures the BOD and Reset on LPC18xx/LPC43xx parts.
+ * @param	BODVL	: Brown-Out Detect voltage level (0-3)
+ * @param	BORVL	: Brown-Out Reset voltage level (0-3)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
+{
+	LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
+}
+
+#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
+/**
+ * @brief	Configures base address of image to be run in the Cortex M0 Core.
+ * @param	memaddr	: Address of the image (must be aligned to 4K)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
+{
+	LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
+}
+
+/**
+ * @brief	Clear M4 IPC Event
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ClearM4Event(void)
+{
+	LPC_CREG->M4TXEVENT = 0;
+}
+
+/**
+ * @brief	Clear M0 IPC Event
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ClearM0Event(void)
+{
+	LPC_CREG->M0TXEVENT = 0;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CREG_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c

@@ -0,0 +1,89 @@
+/*
+ * @brief LPC18xx/43xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "emc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Dyanmic memory setup */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config)
+{
+	uint32_t ClkFreq;
+	uint32_t EMCDiv;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
+
+	/* EMC Divider readback at pos 27
+	    TODO: just checked but dont mention in UM */
+	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
+
+	/* Check EMC Divider to get real EMC clock out */
+	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
+		ClkFreq >>= 1;
+	}
+
+	IP_EMC_Dynamic_Init(LPC_EMC, Dynamic_Config, ClkFreq);
+}
+
+/* Static memory setup */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config)
+{
+	uint32_t ClkFreq;
+	uint32_t EMCDiv;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
+
+	/* EMC Divider readback at pos 27 */
+	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
+
+	/* Check EMC Divider to get real EMC clock out */
+	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
+		ClkFreq >>= 1;
+	}
+
+	IP_EMC_Static_Init(LPC_EMC, Static_Config, ClkFreq);
+}