add LPC4330 BSP based on NGX xplorer development board

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2487 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/xplorer4330/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/applications/application.c

@@ -0,0 +1,62 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+
+#ifdef RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+
+#include "board_ngx_xplorer_18304330.h"
+
+static void rt_init_thread_entry(void *parameter)
+{
+    Board_LED_Init();
+
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+    while (1)
+    {
+        Board_LED_Set(0, 1);
+        rt_thread_delay(50);
+        Board_LED_Set(0, 0);
+        rt_thread_delay(50);
+    }
+}
+
+void rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry,
+                           RT_NULL,
+                           2048,
+                           RT_THREAD_PRIORITY_MAX / 3,
+                           20);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+}
+
+/*@}*/

bsp/xplorer4330/applications/startup.c

@@ -0,0 +1,91 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2012-12-11     lgnq         modified for LPC4330
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "platform.h"
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define LPC4300_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define LPC4300_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define LPC4300_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init((void *)LPC4300_SRAM_BEGIN, (void *)(0x10000000 + 1024*128));
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+#ifdef RT_USING_DEVICE
+    /* init all device */
+    rt_device_init_all();
+#endif
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/xplorer4330/drivers/SConscript

@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_SERIAL') == False:
+    SrcRemove(src, 'usart.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/drivers/platform.c

@@ -0,0 +1,64 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-13     lgnq         first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "cmsis.h"
+
+#ifdef RT_USING_SERIAL
+#include "usart.h"
+#endif
+
+/**
+ * @addtogroup LPC4330
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initialize the LPC4330 Xplorer board.
+ */
+void rt_hw_board_init(void)
+{
+    Board_Init();
+
+    /* Configure the SysTick - Generate interrupt @ 100 Hz*/
+    SysTick_Config(Chip_Clock_GetRate(CLK_MX_MXCORE) / 100);
+
+#ifdef RT_USING_SERIAL
+    rt_hw_serial_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+#endif
+}
+
+/*@}*/

bsp/xplorer4330/drivers/platform.h

@@ -0,0 +1,19 @@
+/*
+ * File      : platform.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+void rt_hw_board_init(void);
+
+#endif

bsp/xplorer4330/drivers/usart.h

@@ -0,0 +1,39 @@
+/*
+ * File      : usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include <rtthread.h>
+
+#include "chip_lpc43xx.h"
+#include "cmsis.h"
+
+/**
+ *  Enable/DISABLE Interrupt Controller
+ */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct uart_device
+{
+    LPC_USART_Type *uart_regs;
+
+    /* irq number */
+    IRQn_Type irq_num;
+};
+
+void rt_hw_serial_init(void);
+
+#endif

bsp/xplorer4330/libraries/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/xplorer4330/libraries/lpc_board/SConscript

@@ -0,0 +1,44 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+#src = Glob('board_common/*.c')
+src  = []
+path = [cwd + '/board_common']
+
+if rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_4330':
+    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
+             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
+    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
+             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330']
+elif rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_1830':
+    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
+             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
+    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
+             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830']
+elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_4357':
+    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
+             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
+    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
+             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357']
+elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_1857':
+    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
+             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
+    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
+             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857']
+elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_4350':
+    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
+             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
+    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
+             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350']
+elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_1850':
+    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
+             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
+    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
+             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850']
+
+group = DefineGroup('lpc_board', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h

@@ -0,0 +1,176 @@
+/*
+ * @brief Common board API functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_API_H_
+#define __BOARD_API_H_
+
+#include "lpc_types.h"
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_COMMON_API BOARD: Common board functions
+ * @ingroup BOARD_Common
+ * This file contains common board definitions that are shared across
+ * boards and devices. All of these functions do not need to be
+ * impemented for a specific board, but if they are implemented, they
+ * should use this API standard.
+ * @{
+ */
+
+/**
+ * @brief	Set up and initialize all required blocks and functions related to the board hardware.
+ * @return	None
+ */
+void Board_Init(void);
+
+/**
+ * @brief	Initializes board UART for output, required for printf redirection
+ * @return	None
+ */
+void Board_Debug_Init(void);
+
+/**
+ * @brief	Sends a single character on the UART, required for printf redirection
+ * @param	ch	: character to send
+ * @return	None
+ */
+void Board_UARTPutChar(char ch);
+
+/**
+ * @brief	Get a single character from the UART, required for scanf input
+ * @return	EOF if not character was received, or character value
+ */
+int Board_UARTGetChar(void);
+
+/**
+ * @brief	Prints a string to the UART
+ * @param	str	: Terminated string to output
+ * @return	None
+ */
+void Board_UARTPutSTR(char *str);
+
+/**
+ * @brief	Initializes board LED(s)
+ * @return	None
+ */
+void Board_LED_Init(void);
+
+/**
+ * @brief	Sets the state of a board LED to on or off
+ * @param	LEDNumber	: LED number to set state for
+ * @param	State		: true for on, false for off
+ * @return	None
+ */
+void Board_LED_Set(uint8_t LEDNumber, bool State);
+
+/**
+ * @brief	Returns the current state of a board LED
+ * @param	LEDNumber	: LED number to set state for
+ * @return	true if the LED is on, otherwise false
+ */
+bool Board_LED_Test(uint8_t LEDNumber);
+
+/**
+ * @brief	Toggles the current state of a board LED
+ * @param	LEDNumber	: LED number to change state for
+ * @return	None
+ */
+STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)
+{
+	Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));
+}
+
+
+/**
+ * @brief	Current system clock rate, mainly used for sysTick
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	Turn on Board LCD Backlight
+ * @param	Intensity	: Backlight intensity (0 = off, >=1 = on)
+ * @return	None
+ * On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
+ * value will turn off or on the backlight. On some boards, a non-0 value will
+ * control backlight intensity via a PWN. For PWM systems, the intensity value
+ * is a percentage value between 0 and 100%.
+ */
+void Board_LCD_Set_Backlight(uint8_t Intensity);
+
+/**
+ * @brief Function prototype for a MS delay function. Board layers or example code may
+ *        define this function as needed.
+ */
+typedef void (*p_msDelay_func_t)(uint32_t);
+
+/* The DEBUG* functions are selected based on system configuration.
+   Code that uses the DEBUG* functions will have their I/O routed to
+   the UART, semihosting, or nowhere. */
+#if defined(DEBUG)
+#if defined(DEBUG_SEMIHOSTING)
+#define DEBUGINIT()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) printf(str)
+#define DEBUGIN() (int) EOF
+
+#else
+#define DEBUGINIT() Board_Debug_Init()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) Board_UARTPutSTR(str)
+#define DEBUGIN() Board_UARTGetChar()
+#endif /* defined(DEBUG_SEMIHOSTING) */
+
+#else
+#define DEBUGINIT()
+#define DEBUGOUT(...)
+#define DEBUGSTR(str)
+#define DEBUGIN() (int) EOF
+#endif /* defined(DEBUG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_API_H_ */

bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h

@@ -0,0 +1,90 @@
+/*
+ * @brief Common PHY functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_PHY_H_
+#define __LPC_PHY_H_
+
+#include "board.h"
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers
+ * @ingroup BOARD_Common
+ * The simple PHY function API provides simple non-blocking PHY status
+ * monitoring and initialization support for various Ethernet PHYs.
+ * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires
+ * several standard functions from the MAC driver for interfacing to the
+ * PHY via a MII link (Chip_ENET_Start_MII_Write(), Chip_ENET_Is_MII_Busy(),
+ * Chip_ENET_Start_MII_Read(), and Chip_ENET_Read_MII_Data()).
+ *
+ * Once initialized, just preiodically call the lpcPHYStsPoll() function
+ * from the background loop or a thread and monitor the returned status
+ * to determine if the PHY state has changed and the current PHY state.
+ * @{
+ */
+#define PHY_LINK_ERROR     (1 << 0)	/*!< PHY status bit for link error */
+#define PHY_LINK_BUSY      (1 << 1)	/*!< PHY status bit for MII link busy */
+#define PHY_LINK_CHANGED   (1 << 2)	/*!< PHY status bit for changed state (not persistent) */
+#define PHY_LINK_CONNECTED (1 << 3)	/*!< PHY status bit for connected state */
+#define PHY_LINK_SPEED100  (1 << 4)	/*!< PHY status bit for 100Mbps mode */
+#define PHY_LINK_FULLDUPLX (1 << 5)	/*!< PHY status bit for full duplex mode */
+
+/**
+ * @brief	Phy status update state machine
+ * @return	An Or'ed value of PHY_LINK_* statuses
+ * This function can be called at any rate and will poll the the PHY status. Multiple
+ * calls may be needed to determine PHY status.
+ */
+uint32_t lpcPHYStsPoll(void);
+
+/**
+ * @brief	Initialize the PHY
+ * @param	rmii			: Initializes PHY for RMII mode if true, MII if false
+ * @param	pDelayMsFunc	: Delay function (in mS) used for this driver
+ * @return	PHY_LINK_ERROR or 0 on success
+ * This function initializes the PHY. It will block until complete. It will not
+ * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to
+ * detect cable insertion.
+ */
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC_PHY_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox

@@ -0,0 +1,62 @@
+/*
+ * @brief LPCOpen 18xx/43xx board support page
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+/** @defgroup BOARDS_18XX_43XX BOARD: LPC18XX and LPC43XX boards
+ * @ingroup Board_Layer
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/*!
+ * @page LPCOPEN_BSP_18XX43XX Supported 18xx/43xx platforms
+ *
+ * <b>Device Support</b><br/>
+ * All LPC18xx and LPC43xx device variants are supported.<br/><br/>
+ * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=103">LPC18xx documentation links</a><br/>
+ * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=104">LPC43xx documentation links</a><br/><br/>
+ * <b>Board Support</b><br/>
+ * Hitex, Keil, and NGX boards for both 18xx and 43xx variants are supported.
+ * Click <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco">here</a> for LPCOpen build procedures and default jumper configuration for supported boards.<br/><br/>
+ * <a href="http://www.hitex.com/index.php?id=3455/">Hitex LPC1857 and LPC4357 evaluation boards </a><br/>
+ * <a href="http://www.keil.com/mcb1800/">Keil MCB1800</a> and <a href="http://www.keil.com/mcb4300/">Keil MCB4300 boards</a><br/>
+ * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC1830-Xplorer_Quick_Start_Guide">NGX LPC1830 Xplorer</a> and 
+ * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC4330-Xplorer_Quick_Start_Guide">NGX LPC4330 Xplorer boards</a><br/>
+ *
+ * <b>Toolchain Support</b><br/>
+ * Code Red Xpresso, IAR EWARM, and Keil MDK are all supported. See the <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco#Supported_toolchains">build support pages</a>
+ * for information on specific versions of the toolchains tested with the LPCOpen platform.<br/><br/>
+ * <a href="http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/">IAR EWARM</a><br/>
+ * <a href="http://www.keil.com/arm/mdk.asp">ARM MDK-ARM</a><br/>
+ * <a href="http://code-red-tech.com/lpcxpresso">LPCXpresso</a>
+ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief Hitex EVA 1850/4350 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_hitex_eva_18504350.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+// #define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+// #define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief Keil MCB 1857/4357 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_keil_mcb_18574357.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART3
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+#define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING'
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART3
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h

@@ -0,0 +1,37 @@
+/*
+ * @brief NGX Xplorer 1830/4330 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "board_ngx_xplorer_18304330.h"
+
+#endif /* __BOARD_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC18XX
+
+/* Enable DEBUG for IO support via the UART */
+// #define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (180000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h

@@ -0,0 +1,58 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+#define USE_RMII
+#define CHIP_LPC43XX
+
+/* Enable DEBUG for IO support via the UART */
+// #define DEBUG
+
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
+   via semihosting */
+// #define DEBUG_SEMIHOSTING
+
+/* Board UART used for debug output */
+#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Frequency on external clock in pin */
+#define EXTERNAL_CLKIN_FREQ_IN 0
+
+/* Default CPU clock frequency */
+#define MAX_CLOCK_FREQ (204000000)
+
+#endif /* __SYS_CONFIG_H_ */

bsp/xplorer4330/libraries/lpc_chip/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Glob('chip_18xx_43xx/*.c')
+src += Glob('chip_common/*.c')
+
+path = [cwd + '/chip_18xx_43xx',
+        cwd + '/chip_common']
+
+group = DefineGroup('lpc_chip', src, depend = [], CPPPATH = path)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c

@@ -0,0 +1,136 @@
+/*
+ * @brief LPC18xx/43xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "adc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*The channel to be operated on */
+static uint8_t active_channel;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Returns the clock for the selected ADC */
+static CCU_CLK_T Chip_ADC_GetClk(LPC_ADC_Type *pADC)
+{
+	CCU_CLK_T adcclk;
+
+	if (pADC == LPC_ADC0) {
+		adcclk = CLK_APB3_ADC0;
+	}
+	else {
+		adcclk = CLK_APB3_ADC1;
+	}
+
+	return adcclk;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC peripheral and the ADC setup structure to default value */
+void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup)
+{
+	CCU_CLK_T adcclk = Chip_ADC_GetClk(pADC);
+
+	/* Enable ADC clocking */
+	Chip_Clock_EnableOpts(adcclk, true, true, 1);
+	ADCSetup->adcPerClock = Chip_Clock_GetRate(adcclk);
+
+	ADCSetup->adcRate = 400000;
+	ADCSetup->bitsAccuracy = ADC_10BITS;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+}
+
+/* Select the mode starting the AD conversion */
+void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption)
+{
+	if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
+		IP_ADC_EdgeStartConfig(pADC, (uint8_t) EdgeOption);
+	}
+	IP_ADC_SetStartMode(pADC, (uint8_t) mode);
+}
+
+/* Set the ADC Sample rate */
+void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate)
+{
+	ADCSetup->adcRate = rate;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+
+}
+
+/* Set the ADC accuracy bits */
+void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution)
+{
+	ADCSetup->bitsAccuracy = resolution;
+	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
+}
+
+/* Enable or disable the ADC channel on ADC peripheral */
+void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState)
+{
+	IP_ADC_SetChannelNumber(pADC, channel, NewState);
+	active_channel = channel;
+}
+
+/* Enable burst mode */
+void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
+{
+	IP_ADC_SetStartMode(pADC, ADC_NO_START);
+	IP_ADC_SetBurstMode(pADC, NewState);
+}
+
+/* Read the ADC value and convert it to 8bits value */
+Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data)
+{
+	uint16_t temp;
+	Status rt;
+
+	rt = IP_ADC_Get_Val(pADC, active_channel, &temp);
+	*data = (uint8_t) temp;
+
+	return rt;
+}
+
+/* Set a channel to be read A/D data */
+void Chip_ADC_Active_Channel(uint8_t channel)
+{
+	active_channel = channel;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c

@@ -0,0 +1,55 @@
+/*
+ * @brief LPC18xx/43xx ATimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "atimer_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize Alarm Timer */
+void Chip_ATIMER_Init(uint32_t PresetValue)
+{
+	Chip_ATIMER_UpdatePresetValue(PresetValue);
+	Chip_ATIMER_ClearIntStatus();
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h

@@ -0,0 +1,117 @@
+/*
+ * @brief LPC18xx/43xx ATimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ATIMER_18XX_43XX_H_
+#define __ATIMER_18XX_43XX_H_
+
+#include "chip.h"
+
+/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize Alarm Timer
+ * @param PresetValue Count of 1 to 1024s for Alarm
+ * @return	None
+ */
+void Chip_ATIMER_Init(uint32_t PresetValue);
+
+/**
+ * @brief	Close ATIMER device
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_DeInit(void)
+{
+	IP_ATIMER_DeInit(LPC_ATIMER);
+}
+
+/**
+ * @brief	Enable ATIMER Interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_IntEnable(void)
+{
+	IP_ATIMER_IntEnable(LPC_ATIMER);
+}
+
+/**
+ * @brief	Disable ATIMER Interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_IntDisable(void)
+{
+	IP_ATIMER_IntDisable(LPC_ATIMER);
+}
+
+/**
+ * @brief	Clear ATIMER Interrupt Status
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_ClearIntStatus(void)
+{
+	IP_ATIMER_ClearIntStatus(LPC_ATIMER);
+}
+
+/**
+ * @brief	Set ATIMER Interrupt Status
+ * @return	None
+ */
+STATIC INLINE void Chip_ATIMER_SetIntStatus(void)
+{
+	IP_ATIMER_SetIntStatus(LPC_ATIMER);
+}
+
+/**
+ * @brief	Update Preset value
+ * @param	PresetValue	: updated preset value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ATIMER_UpdatePresetValue(uint32_t PresetValue)
+{
+	IP_ATIMER_UpdatePresetValue(LPC_ATIMER, PresetValue);
+}
+
+/**
+ * @brief	Read value of preset register
+ * @return	Value of capture register
+ */
+STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(void)
+{
+	return IP_ATIMER_GetPresetValue(LPC_ATIMER);
+}
+
+/**
+ * @}
+ */
+
+ #endif /* __ATIMER_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h

@@ -0,0 +1,104 @@
+/*
+ * @brief CGU/CCU registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CGUCCU_18XX_43XX_H_
+#define __CGUCCU_18XX_43XX_H_
+
+#include "cmsis.h"
+#include "chip_clocks.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup CLOCK_18XX_43XX
+ * @{
+ */
+
+/**
+ * @brief LPC18XX/43XX CGU register block structure
+ */
+typedef struct {							/*!< (@ 0x40050000) CGU Structure          */
+	__I  uint32_t  RESERVED0[5];
+	__IO uint32_t  FREQ_MON;				/*!< (@ 0x40050014) Frequency monitor register */
+	__IO uint32_t  XTAL_OSC_CTRL;			/*!< (@ 0x40050018) Crystal oscillator control register */
+	__I  uint32_t  PLL0USB_STAT;			/*!< (@ 0x4005001C) PLL0 (USB) status register */
+	__IO uint32_t  PLL0USB_CTRL;			/*!< (@ 0x40050020) PLL0 (USB) control register */
+	__IO uint32_t  PLL0USB_MDIV;			/*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+	__IO uint32_t  PLL0USB_NP_DIV;			/*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+	__I  uint32_t  PLL0AUDIO_STAT;			/*!< (@ 0x4005002C) PLL0 (audio) status register */
+	__IO uint32_t  PLL0AUDIO_CTRL;			/*!< (@ 0x40050030) PLL0 (audio) control register */
+	__IO uint32_t  PLL0AUDIO_MDIV;			/*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+	__IO uint32_t  PLL0AUDIO_NP_DIV;		/*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+	__IO uint32_t  PLL0AUDIO_FRAC;			/*!< (@ 0x4005003C) PLL0 (audio)           */
+	__I  uint32_t  PLL1_STAT;				/*!< (@ 0x40050040) PLL1 status register   */
+	__IO uint32_t  PLL1_CTRL;				/*!< (@ 0x40050044) PLL1 control register  */
+	__IO uint32_t  IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
+	__IO uint32_t  BASE_CLK[CLK_BASE_LAST];	/*!< (@ 0x4005005C) Start of base clock registers */
+} LPC_CGU_T;
+
+/**
+ * @brief CCU clock config/status register pair
+ */
+typedef struct {
+	__IO uint32_t  CFG;						/*!< CCU clock configuration register */
+	__I  uint32_t  STAT;					/*!< CCU clock status register */
+} CCU_CFGSTAT_T;
+
+/**
+ * @brief CCU1 register block structure
+ */
+typedef struct {							/*!< (@ 0x40051000) CCU1 Structure         */
+	__IO uint32_t  PM;						/*!< (@ 0x40051000) CCU1 power mode register */
+	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40051004) CCU1 base clocks status register */
+	__I  uint32_t  RESERVED0[62];
+	CCU_CFGSTAT_T  CLKCCU[CLK_CCU1_LAST];	/*!< (@ 0x40051100) Start of CCU1 clock registers */
+} LPC_CCU1_Type;
+
+/**
+ * @brief CCU2 register block structure
+ */
+typedef struct {							/*!< (@ 0x40052000) CCU2 Structure         */
+	__IO uint32_t  PM;						/*!< (@ 0x40052000) Power mode register    */
+	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40052004) CCU base clocks status register */
+	__I  uint32_t  RESERVED0[62];
+	CCU_CFGSTAT_T  CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST];	/*!< (@ 0x40052100) Start of CCU2 clock registers */
+} LPC_CCU2_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CGUCCU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h

@@ -0,0 +1,44 @@
+/*
+ * @brief Chip inclusion selector file
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "sys_config.h"
+
+#if defined(CHIP_LPC18XX)
+#include "chip_lpc18xx.h"
+
+#elif defined(CHIP_LPC43XX)
+#include "chip_lpc43xx.h"
+
+#else
+#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
+#endif
+
+#endif /* __CHIP_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox

@@ -0,0 +1,51 @@
+/*
+ * @brief LPCOpen 18xx/43xx chip group page
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+/** @defgroup CHIP_18XX_43XX_Drivers LPC18XX/43XX chip specific drivers
+ * @ingroup Chip_Drivers
+ * @{
+ */
+
+/** @defgroup CHIP_18XX_43XX_DRIVER_OPTIONS CHIP: LPC18XX/43XX Chip driver build time options
+ * Some chip drivers require build-time configuration. Using a build-time
+ * configuration option allows the driver to be smaller and faster. A
+ * build-time option is configured by the use of a definition passed to
+ * the compiler during the build.
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h

@@ -0,0 +1,181 @@
+/*
+ * @brief LPC18XX/43XX CREG control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CREG_18XX_43XX_H_
+#define __CREG_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief CREG Register Block
+ */
+typedef struct {						/*!< CREG Structure         */
+	__I  uint32_t  RESERVED0;
+	__IO uint32_t  CREG0;				/*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
+	__I  uint32_t  RESERVED1[62];
+	__IO uint32_t  MXMEMMAP;			/*!< ARM Cortex-M3/M4 memory mapping */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED2[5];
+#else
+	__I  uint32_t  RESERVED2;
+	__I  uint32_t  CREG1;				/*!< Configuration Register 1 */
+	__I  uint32_t  CREG2;				/*!< Configuration Register 2 */
+	__I  uint32_t  CREG3;				/*!< Configuration Register 3 */
+	__I  uint32_t  CREG4;				/*!< Configuration Register 4 */
+#endif
+	__IO uint32_t  CREG5;				/*!< Chip configuration register 5. Controls JTAG access. */
+	__IO uint32_t  DMAMUX;				/*!< DMA muxing control     */
+	__IO uint32_t  FLASHCFGA;			/*!< Flash accelerator configuration register for flash bank A */
+	__IO uint32_t  FLASHCFGB;			/*!< Flash accelerator configuration register for flash bank B */
+	__IO uint32_t  ETBCFG;				/*!< ETB RAM configuration  */
+	__IO uint32_t  CREG6;				/*!< Chip configuration register 6. */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED4[52];
+#else
+	__IO uint32_t  M4TXEVENT;			/*!< M4 IPC event register */
+	__I  uint32_t  RESERVED4[51];
+#endif
+	__I  uint32_t  CHIPID;				/*!< Part ID                */
+#if defined(CHIP_LPC18XX)
+	__I  uint32_t  RESERVED5[191];
+#else
+	__I  uint32_t  RESERVED5[127];
+	__IO uint32_t  M0TXEVENT;			/*!< M0 IPC Event register */
+	__IO uint32_t  M0APPMEMMAP;			/*!< ARM Cortex M0 memory mapping */
+	__I  uint32_t  RESERVED6[62];
+#endif
+	__IO uint32_t  USB0FLADJ;			/*!< USB0 frame length adjust register */
+	__I  uint32_t  RESERVED7[63];
+	__IO uint32_t  USB1FLADJ;			/*!< USB1 frame length adjust register */
+} LPC_CREG_T;
+
+/**
+ * @brief	Identifies whether on-chip flash is present
+ * @return	true if on chip flash is available, otherwise false
+ */
+STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
+{
+	return LPC_CREG->CHIPID != 0x3284E02B;
+}
+
+/**
+ * @brief	Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
+ * @param	Hz	: Current frequency in Hz of the CPU
+ * @return	Nothing
+ * This function should be called with the higher frequency before the clock frequency is
+ * increased and it should be called with the new lower value after the clock frequency is
+ * decreased.
+ */
+STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
+{
+	uint32_t FAValue = Hz / 21510000;
+
+	LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
+	LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
+}
+
+/**
+ * @brief	Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
+ * @param	Enable	: true to enable PHY, false to disable
+ * @return	Nothing
+ * The USB0 PLL & clock should be configured before calling this function. This function
+ * should be called before the USB0 registers are accessed.
+ */
+STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
+{
+	if (Enable) {
+		LPC_CREG->CREG0 &= ~(1 << 5);
+	}
+	else {
+		LPC_CREG->CREG0 |= (1 << 5);
+	}
+}
+
+/**
+ * @brief	Configures the BOD and Reset on LPC18xx/LPC43xx parts.
+ * @param	BODVL	: Brown-Out Detect voltage level (0-3)
+ * @param	BORVL	: Brown-Out Reset voltage level (0-3)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
+{
+	LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
+}
+
+#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
+/**
+ * @brief	Configures base address of image to be run in the Cortex M0 Core.
+ * @param	memaddr	: Address of the image (must be aligned to 4K)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
+{
+	LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
+}
+
+/**
+ * @brief	Clear M4 IPC Event
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ClearM4Event(void)
+{
+	LPC_CREG->M4TXEVENT = 0;
+}
+
+/**
+ * @brief	Clear M0 IPC Event
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CREG_ClearM0Event(void)
+{
+	LPC_CREG->M0TXEVENT = 0;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CREG_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c

@@ -0,0 +1,89 @@
+/*
+ * @brief LPC18xx/43xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "emc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Dyanmic memory setup */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config)
+{
+	uint32_t ClkFreq;
+	uint32_t EMCDiv;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
+
+	/* EMC Divider readback at pos 27
+	    TODO: just checked but dont mention in UM */
+	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
+
+	/* Check EMC Divider to get real EMC clock out */
+	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
+		ClkFreq >>= 1;
+	}
+
+	IP_EMC_Dynamic_Init(LPC_EMC, Dynamic_Config, ClkFreq);
+}
+
+/* Static memory setup */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config)
+{
+	uint32_t ClkFreq;
+	uint32_t EMCDiv;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
+
+	/* EMC Divider readback at pos 27 */
+	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
+
+	/* Check EMC Divider to get real EMC clock out */
+	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
+		ClkFreq >>= 1;
+	}
+
+	IP_EMC_Static_Init(LPC_EMC, Static_Config, ClkFreq);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h

@@ -0,0 +1,156 @@
+/*
+ * @brief LPC18xx/43xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EMC_18XX_43XX_H_
+#define __EMC_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * Dynamic Chip Select Address
+ */
+#define EMC_ADDRESS_DYCS0   (0x28000000)
+#define EMC_ADDRESS_DYCS1   (0x30000000)
+#define EMC_ADDRESS_DYCS2   (0x60000000)
+#define EMC_ADDRESS_DYCS3   (0x70000000)
+
+/**
+ * Static Chip Select Address
+ */
+#define EMC_ADDRESS_CS0     (0x1C000000)
+#define EMC_ADDRESS_CS1     (0x1D000000)
+#define EMC_ADDRESS_CS2     (0x1E000000)
+#define EMC_ADDRESS_CS3     (0x1F000000)
+
+/**
+ * @brief	Dyanmic memory setup
+ * @param	Dynamic_Config	: Pointer to dynamic memory setup data
+ * @return	None
+ */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config);
+
+/**
+ * @brief	Static memory setup
+ * @param	Static_Config	: Pointer to static memory setup data
+ * @return	None
+ */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config);
+
+/**
+ * @brief	Set Deep Sleep Mode for Dynamic Memory Controller
+ * @param	Enable	: 1 = enter DeepSleep Mode, 0 = Normal Mode
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Dynamic_DeepSleepMode(uint32_t Enable)
+{
+	IP_EMC_Dynamic_DeepSleepMode(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Enable Dynamic Memory Controller
+ * @param	Enable	: 1 = Enable Dynamic Memory Controller, 0 = Disable
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable)
+{
+	IP_EMC_Dynamic_Enable(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Mirror CS1 to CS0 and DYCS0
+ * @param	Enable	: 1 = Mirror, 0 = Normal Memory Map
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable)
+{
+	IP_EMC_Mirror(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Enable EMC
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Enable(uint8_t Enable)
+{
+	IP_EMC_Enable(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Set EMC LowPower Mode
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable)
+{
+	IP_EMC_LowPowerMode(LPC_EMC, Enable);
+}
+
+/**
+ * @brief	Initialize EMC
+ * @param	Enable		: 1 = Enable, 0 = Disable
+ * @param	ClockRatio	: clock out ratio, 0 = 1:1, 1 = 1:2
+ * @param	EndianMode	: Endian Mode, 0 = Little, 1 = Big
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
+{
+	IP_EMC_Init(LPC_EMC, Enable, ClockRatio, EndianMode);
+}
+
+/**
+ * @brief	Set Static Memory Extended Wait in Clock
+ * @param	Wait16Clks	: Number of '16 clock' delay cycles
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
+{
+	IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EMC_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c

@@ -0,0 +1,82 @@
+/*
+ * @brief LPC18xx/43xx ethernet driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "enet_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Basic Ethernet interface initialization */
+void Chip_ENET_Init(void)
+{
+	LPC_CREG->CREG6 &= ~0x7;
+
+	/* Enable ethernet clock */
+	Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
+
+	/* PHY TX/RX base clock routing is setup as part of SystemInit() */
+
+#if defined(USE_RMII)
+	LPC_CREG->CREG6 |= 0x4;
+#endif
+
+	/* Reset ethernet and wait for reset to complete */
+	Chip_RGU_TriggerReset(RGU_ETHERNET_RST);
+	while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}
+
+	/* Reset ethernet peripheral */
+	Chip_ENET_Reset();
+
+	/* Setup MII link divider to /102 and PHY address 1 */
+	Chip_ENET_Setup_MII(4, 1);
+
+	IP_ENET_Init(LPC_ETHERNET);
+}
+
+/* Ethernet interface shutdown */
+void Chip_ENET_DeInit(void)
+{
+	IP_ENET_DeInit(LPC_ETHERNET);
+	Chip_Clock_Disable(CLK_MX_ETHERNET);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c

@@ -0,0 +1,111 @@
+/*
+ * @brief LPC18xx/43xx event router driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "evrt_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the EVRT */
+void Chip_EVRT_Init(void)
+{
+	uint8_t i = 0;
+	// Clear all register to be default
+	LPC_EVRT->HILO      = 0x0000;
+	LPC_EVRT->EDGE      = 0x0000;
+	LPC_EVRT->CLR_EN    = 0xFFFF;
+	do {
+		i++;
+		LPC_EVRT->CLR_STAT  = 0xFFFFF;
+	} while ((LPC_EVRT->STATUS != 0) && (i < 10));
+}
+
+/* Set up the type of interrupt type for a source to EVRT */
+void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type)
+{
+	switch (type) {
+	case EVRT_SRC_ACTIVE_LOW_LEVEL:
+		LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
+		break;
+
+	case EVRT_SRC_ACTIVE_HIGH_LEVEL:
+		LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
+		break;
+
+	case EVRT_SRC_ACTIVE_FALLING_EDGE:
+		LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
+		break;
+
+	case EVRT_SRC_ACTIVE_RISING_EDGE:
+		LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
+		LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/* Enable or disable interrupt sources to EVRT */
+void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state)
+{
+	if (state == ENABLE) {
+		LPC_EVRT->SET_EN = (1 << (uint8_t) EVRT_Src);
+	}
+	else {
+		LPC_EVRT->CLR_EN = (1 << (uint8_t) EVRT_Src);
+	}
+}
+
+/* Check if a source is sending interrupt to EVRT */
+IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src)
+{
+	if (LPC_EVRT->STATUS & (1 << (uint8_t) EVRT_Src)) {
+		return SET;
+	}
+	else {return RESET; }
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h

@@ -0,0 +1,173 @@
+/*
+ * @brief LPC18xx/43xx event router driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EVRT_18XX_43XX_H_
+#define __EVRT_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief Event Router register structure
+ */
+typedef struct {						/*!< EVENTROUTER Structure  */
+	__IO uint32_t HILO;					/*!< Level configuration register */
+	__IO uint32_t EDGE;					/*!< Edge configuration     */
+	__I  uint32_t RESERVED0[1012];
+	__O  uint32_t CLR_EN;				/*!< Event clear enable register */
+	__O  uint32_t SET_EN;				/*!< Event set enable register */
+	__I  uint32_t STATUS;				/*!< Status register        */
+	__I  uint32_t ENABLE;				/*!< Enable register        */
+	__O  uint32_t CLR_STAT;				/*!< Clear register         */
+	__O  uint32_t SET_STAT;				/*!< Set register           */
+} LPC_EVRT_Type;
+
+/**
+ * @brief EVRT input sources
+ */
+typedef enum {
+	EVRT_SRC_WAKEUP0,			/*!< WAKEUP0 event router source		*/
+	EVRT_SRC_WAKEUP1,			/*!< WAKEUP1 event router source		*/
+	EVRT_SRC_WAKEUP2,			/*!< WAKEUP2 event router source		*/
+	EVRT_SRC_WAKEUP3,			/*!< WAKEUP3 event router source		*/
+	EVRT_SRC_ATIMER,			/*!< Alarm timer event router source	*/
+	EVRT_SRC_RTC,				/*!< RTC event router source			*/
+	EVRT_SRC_BOD1,				/*!< BOD event router source			*/
+	EVRT_SRC_WWDT,				/*!< WWDT event router source			*/
+	EVRT_SRC_ETHERNET,			/*!< Ethernet event router source		*/
+	EVRT_SRC_USB0,				/*!< USB0 event router source			*/
+	EVRT_SRC_USB1,				/*!< USB1 event router source			*/
+	EVRT_SRC_SDIO,				/*!< Reserved							*/
+	EVRT_SRC_CCAN,				/*!< C_CAN event router source			*/
+	EVRT_SRC_COMBINE_TIMER2,	/*!< Combined timer 2 event router source	*/
+	EVRT_SRC_COMBINE_TIMER6,	/*!< Combined timer 6 event router source	*/
+	EVRT_SRC_QEI,				/*!< QEI event router source			*/
+	EVRT_SRC_COMBINE_TIMER14,	/*!< Combined timer 14 event router source	*/
+	EVRT_SRC_RESERVED1,			/*!< Reserved                           */
+	EVRT_SRC_RESERVED2,			/*!< Reserved							*/
+	EVRT_SRC_RESET				/*!< Reset event router source			*/
+} Chip_EVRT_SRC_ENUM;
+
+/**
+ * @brief Macro for checking for a valid EVRT source
+ */
+#define PARAM_EVRT_SOURCE(n)    ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1)	\
+								 || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \
+								 || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \
+								 || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \
+								 || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \
+								 || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \
+								 || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \
+								 || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \
+								 || (n == EVRT_SRC_RESET)) \
+
+/**
+ * @brief EVRT input state detecting type
+ */
+typedef enum {
+	EVRT_SRC_ACTIVE_LOW_LEVEL,		/*!< Active low level       */
+	EVRT_SRC_ACTIVE_HIGH_LEVEL,		/*!< Active high level		*/
+	EVRT_SRC_ACTIVE_FALLING_EDGE,	/*!< Active falling edge	*/
+	EVRT_SRC_ACTIVE_RISING_EDGE		/*!< Active rising edge		*/
+} EVRT_SRC_ACTIVE_TYPE;
+
+/**
+ * @brief Macro for checking for a valid EVRT state type
+ */
+#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL)	\
+										  || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))
+
+/**
+ * @brief	Initialize the EVRT
+ * @return	Nothing
+ */
+void Chip_EVRT_Init (void);
+
+/**
+ * @brief	Set up the type of interrupt type for a source to EVRT
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @param	type		: EVRT type, should be one of EVRT_SRC_ACTIVE_TYPE type
+ * @return	Nothing
+ */
+void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
+
+/**
+ * @brief	Check if a source is sending interrupt to EVRT
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @return	true if the interrupt from the source is pending, otherwise false
+ */
+IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src);
+
+/**
+ * @brief	Enable or disable interrupt sources to EVRT
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @param	state		: ENABLE or DISABLE to enable or disable event router source
+ * @return	Nothing
+ */
+void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
+
+/**
+ * @brief	De-initializes the EVRT peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EVRT_DeInit(void)
+{
+	LPC_EVRT->CLR_EN    = 0xFFFF;
+	LPC_EVRT->CLR_STAT  = 0xFFFF;
+}
+
+/**
+ * @brief	Clear pending interrupt EVRT source
+ * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EVRT_ClrPendIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src)
+{
+	LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EVRT_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h

@@ -0,0 +1,167 @@
+/*
+ * @brief LPC18xx/43xx DMA driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPDMA_18XX_43XX_H_
+#define __GPDMA_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** Number of channels on GPDMA */
+#define GPDMA_NUMBER_CHANNELS 8
+
+/** DMA Connection number definitions */
+#define GPDMA_CONN_MEMORY           ((0UL))			/**< MEMORY             */
+#define GPDMA_CONN_MAT0_0           ((1UL))			/**< MAT0.0             */
+#define GPDMA_CONN_UART0_Tx         ((2UL))			/**< UART0 Tx           */
+#define GPDMA_CONN_MAT0_1           ((3UL))			/**< MAT0.1             */
+#define GPDMA_CONN_UART0_Rx         ((4UL))			/**< UART0 Rx           */
+#define GPDMA_CONN_MAT1_0           ((5UL))			/**< MAT1.0             */
+#define GPDMA_CONN_UART1_Tx         ((6UL))			/**< UART1 Tx           */
+#define GPDMA_CONN_MAT1_1           ((7UL))			/**< MAT1.1             */
+#define GPDMA_CONN_UART1_Rx         ((8UL))			/**< UART1 Rx           */
+#define GPDMA_CONN_MAT2_0           ((9UL))			/**< MAT2.0             */
+#define GPDMA_CONN_UART2_Tx         ((10UL))		/**< UART2 Tx           */
+#define GPDMA_CONN_MAT2_1           ((11UL))		/**< MAT2.1             */
+#define GPDMA_CONN_UART2_Rx         ((12UL))		/**< UART2 Rx           */
+#define GPDMA_CONN_MAT3_0           ((13UL))		/**< MAT3.0             */
+#define GPDMA_CONN_UART3_Tx         ((14UL))		/**< UART3 Tx           */
+#define GPDMA_CONN_SCT_0            ((15UL))		/**< SCT timer channel 0*/
+#define GPDMA_CONN_MAT3_1           ((16UL))		/**< MAT3.1             */
+#define GPDMA_CONN_UART3_Rx         ((17UL))		/**< UART3 Rx           */
+#define GPDMA_CONN_SCT_1            ((18UL))		/**< SCT timer channel 1*/
+#define GPDMA_CONN_SSP0_Rx          ((19UL))		/**< SSP0 Rx            */
+#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))		/**< I2S channel 0      */
+#define GPDMA_CONN_SSP0_Tx          ((21UL))		/**< SSP0 Tx            */
+#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))		/**< I2S channel 1      */
+#define GPDMA_CONN_SSP1_Rx          ((23UL))		/**< SSP1 Rx            */
+#define GPDMA_CONN_SSP1_Tx          ((24UL))		/**< SSP1 Tx            */
+#define GPDMA_CONN_ADC_0            ((25UL))		/**< ADC 0              */
+#define GPDMA_CONN_ADC_1            ((26UL))		/**< ADC 1              */
+#define GPDMA_CONN_DAC              ((27UL))		/**< DAC                */
+#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL))		/**< I2S channel 0      */
+#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL))		/**< I2S channel 0      */
+
+/** Burst size in Source and Destination definitions */
+#define GPDMA_BSIZE_1   ((0UL))	/**< Burst size = 1 */
+#define GPDMA_BSIZE_4   ((1UL))	/**< Burst size = 4 */
+#define GPDMA_BSIZE_8   ((2UL))	/**< Burst size = 8 */
+#define GPDMA_BSIZE_16  ((3UL))	/**< Burst size = 16 */
+#define GPDMA_BSIZE_32  ((4UL))	/**< Burst size = 32 */
+#define GPDMA_BSIZE_64  ((5UL))	/**< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL))	/**< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL))	/**< Burst size = 256 */
+
+/** Width in Source transfer width and Destination transfer width definitions */
+#define GPDMA_WIDTH_BYTE        ((0UL))	/**< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD    ((1UL))	/**< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD        ((2UL))	/**< Width = 4 bytes */
+
+/** Flow control definitions */
+#define DMA_CONTROLLER 0		/**< Flow control is DMA controller*/
+#define SRC_PER_CONTROLLER 1	/**< Flow control is Source peripheral controller*/
+#define DST_PER_CONTROLLER 2	/**< Flow control is Destination peripheral controller*/
+
+typedef struct {
+	FunctionalState ChannelStatus;
+} DMA_ChannelHandle_t;
+
+#define Chip_GPDMA_IntGetStatus(type, channel) IP_GPDMA_IntGetStatus(LPC_GPDMA, type, channel)
+
+#define Chip_GPDMA_ClearIntPending(type, channel) IP_GPDMA_ClearIntPending(LPC_GPDMA, type, channel)
+
+#define Chip_GPDMA_ChannelCmd(channelNum, NewState) IP_GPDMA_ChannelCmd(LPC_GPDMA, channelNum, NewState)
+
+/**
+ * @brief	Initialize the GPDMA
+ * @return	Nothing
+ */
+void Chip_GPDMA_Init(void);
+
+/**
+ * @brief	Stop a stream DMA transfer
+ * @param	ChannelNum	:	Channel Number to be closed
+ * @return	Nothing
+ */
+void Chip_DMA_Stop(uint8_t ChannelNum);
+
+/**
+ * @brief	The GPDMA stream interrupt status checking
+ * @param	ChannelNum		:	Channel Number to be checked on interruption
+ * @return	Status:
+ *              - SUCCESS	: DMA transfer success
+ *              - ERROR		: DMA transfer failed
+ */
+Status  Chip_DMA_Interrupt(uint8_t ChannelNum);
+
+/**
+ * @brief	Get a free GPDMA channel for one DMA connection
+ * @param	PeripheralConnection_ID		:	Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )
+ * @return	The channel number which is selected
+ */
+uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID);
+
+/**
+ * @brief	Do a DMA transfer M2M, M2P,P2M or P2P
+ * @param	ChannelNum		:	Channel used for transfer
+ * @param	src				:	Address of Memory or PeripheralConnection_ID which is the source
+ * @param	dst				:	Address of Memory or PeripheralConnection_ID which is the destination
+ * @param	TransferType	:	Select the transfer controller and the type of transfer. Should be:
+ *                               - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
+ * @param	Size			:	The number of DMA transfers
+ * @return	Nothing
+ */
+void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPDMA_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c

@@ -0,0 +1,53 @@
+/** @brief LPC18xx/43xx GPIO driver** Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "gpio_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set Direction for a GPIO port */
+void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
+{
+	if (out) {
+		LPC_GPIO_PORT->DIR[portNum] |= bitValue;
+	}
+	else {
+		LPC_GPIO_PORT->DIR[portNum] &= ~bitValue;
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c

@@ -0,0 +1,138 @@
+/*
+ * @brief LPC18xx/43xx I2S driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "i2s_18xx_43xx.h"
+#include "scu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Configure I2S for Audio Format input */
+Status Chip_I2S_Config(LPC_I2S_Type *I2Sx, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format)
+{
+	uint32_t pClk;
+	uint32_t x, y;
+	uint64_t divider;
+	uint16_t dif;
+	uint16_t x_divide = 0, y_divide = 0;
+	uint32_t N;
+	uint16_t err, ErrorOptimal = 0xFFFF;
+
+	pClk = (uint64_t)Chip_Clock_GetRate(CLK_APB1_I2S);
+
+	/* divider is a fixed point number with 16 fractional bits */
+	divider = (((uint64_t)(audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk;
+	/* find N that make x/y <= 1 -> divider <= 2^16 */
+	for (N = 64; N > 0; N--) {
+		if ((divider * N) < (1 << 16)) {
+			break;
+		}
+	}
+	if (N == 0) {
+		return ERROR;
+	}
+	divider *= N;
+	for (y = 255; y > 0; y--) {
+		x = y * divider;
+		if (x & (0xFF000000)) {
+			continue;
+		}
+		dif = x & 0xFFFF;
+		if (dif > 0x8000) {
+			err = 0x10000 - dif;
+		}
+		else {
+			err = dif;
+		}
+		if (err == 0) {
+			y_divide = y;
+			break;
+		}
+		else if (err < ErrorOptimal) {
+			ErrorOptimal = err;
+			y_divide = y;
+		}
+	}
+	x_divide = ((uint64_t)y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk;
+	if (x_divide >= 256) {
+		x_divide = 0xFF;
+	}
+	if (x_divide == 0) {
+		x_divide = 1;
+	}
+	if (audio_format->WordWidth <= 8) {
+		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_8);
+	}
+	else if (audio_format->WordWidth <= 16) {
+		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_16);
+	}
+	else {
+		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_32);
+	}
+	IP_I2S_SetMono(I2Sx, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO);
+	IP_I2S_SetMasterSlaveMode(I2Sx, TRMode, I2S_MASTER_MODE);
+	IP_I2S_SetWS_Halfperiod(I2Sx, TRMode, audio_format->WordWidth - 1);
+	IP_I2S_ModeConfig(I2Sx, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA);
+	IP_I2S_SetBitRate(I2Sx, TRMode, N - 1);
+	IP_I2S_SetXYDivider(I2Sx, TRMode, x_divide, y_divide);
+	return SUCCESS;
+}
+
+/* Enable/Disable Interrupt with a specific FIFO depth */
+void Chip_I2S_Int_Cmd(LPC_I2S_Type *I2Sx, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth)
+{
+	IP_I2S_InterruptCmd(I2Sx, TRMode, NewState);
+	IP_I2S_SetFIFODepthIRQ(I2Sx, TRMode, FIFO_Depth);
+}
+
+/* Enable/Disable DMA with a specific FIFO depth */
+void    Chip_I2S_DMA_Cmd(LPC_I2S_Type *I2Sx,
+						uint8_t TRMode,
+						uint8_t DMANum,
+						FunctionalState NewState,
+						uint8_t FIFO_Depth)
+{
+	IP_I2S_SetFIFODepthDMA(I2Sx, TRMode, (IP_I2S_DMARequestNumber_Type) DMANum, FIFO_Depth);
+	IP_I2S_DMACmd(I2Sx, (IP_I2S_DMARequestNumber_Type) DMANum, TRMode, NewState);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c

@@ -0,0 +1,118 @@
+/*
+ * @brief LPC18xx/43xx LCD chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "lcd_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+static LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Configure Cursor */
+void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync)
+{
+	LCD_Cursor_Size = cursor_size;
+	IP_LCD_Cursor_Config(LPC_LCD, cursor_size, sync);
+}
+
+/* Write Cursor Image into Internal Cursor Image Buffer */
+void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image)
+{
+	int i, j;
+	uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image;
+
+	/* Check if Cursor Size was configured as 32x32 or 64x64*/
+	if (LCD_Cursor_Size == LCD_CURSOR_32x32) {
+		i = cursor_num * 64;
+		j = i + 64;
+	}
+	else {
+		i = 0;
+		j = 256;
+	}
+	fifoptr = IP_LCD_Cursor_GetImageBufferAddress(LPC_LCD, 0);
+
+	/* Copy Cursor Image content to FIFO */
+	for (; i < j; i++) {
+
+		*fifoptr = *crsr_ptr;
+		crsr_ptr++;
+		fifoptr++;
+	}
+}
+
+/* Load LCD Palette */
+void Chip_LCD_LoadPalette(void *palette) {
+	LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry;
+	uint8_t i, *pal_ptr;
+	/* This function supports loading of the color palette from
+	   the C file generated by the bmp2c utility. It expects the
+	   palette to be passed as an array of 32-bit BGR entries having
+	   the following format:
+	   2:0 - Not used
+	   7:3 - Blue
+	   10:8 - Not used
+	   15:11 - Green
+	   18:16 - Not used
+	   23:19 - Red
+	   31:24 - Not used
+	   arg = pointer to input palette table address */
+	ptr_pal_entry = &pal_entry;
+	pal_ptr = (uint8_t *) palette;
+
+	/* 256 entry in the palette table */
+	for (i = 0; i < 256 / 2; i++) {
+		pal_entry.Bl = (*pal_ptr++) >> 3;	/* blue first */
+		pal_entry.Gl = (*pal_ptr++) >> 3;	/* get green */
+		pal_entry.Rl = (*pal_ptr++) >> 3;	/* get red */
+		pal_ptr++;	/* skip over the unused byte */
+		/* do the most significant halfword of the palette */
+		pal_entry.Bu = (*pal_ptr++) >> 3;	/* blue first */
+		pal_entry.Gu = (*pal_ptr++) >> 3;	/* get green */
+		pal_entry.Ru = (*pal_ptr++) >> 3;	/* get red */
+		pal_ptr++;	/* skip over the unused byte */
+
+		IP_LCD_Color_LoadPalette(LPC_LCD, (uint32_t *) &ptr_pal_entry, i);
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c

@@ -0,0 +1,92 @@
+/*
+ * @brief LPC18xx/43xx Reset Generator Unit driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "rgu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Trigger a peripheral reset for the selected peripheral */
+void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber)
+{
+	volatile uint32_t *p;
+
+	/* To trigger reset- write RESET_CTRLx with a 1 bit */
+	p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
+
+	/* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
+	p += ResetNumber / 32;
+
+	/* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
+	   after 1 clock cycle, so set the bit and return */
+	*p = (1 << (ResetNumber % 32));
+}
+
+/* Clears reset for the selected peripheral */
+void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber)
+{
+	volatile uint32_t *p;
+
+	/* To trigger reset- write RESET_CTRLx with a 1 bit */
+	p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
+
+	/* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
+	p += ResetNumber / 32;
+
+	/* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
+	   after 1 clock cycle, so set the bit and return */
+	*p = 0;
+}
+
+/* Checks the reset status of a peripheral */
+bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber)
+{
+	volatile uint32_t *read;
+
+	read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0);
+	read += ResetNumber / 32;
+
+	/* Reset not asserted if bit is set */
+	return (bool) ((*read & (1 << (ResetNumber % 32))) == 0);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h

@@ -0,0 +1,151 @@
+/*
+ * @brief LPC18xx/43xx Reset Generator Unit driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RGU_18XX_43XX_H_
+#define __RGU_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief RGU reset enumerations
+ */
+typedef enum {
+	RGU_CORE_RST,
+	RGU_PERIPH_RST,
+	RGU_MASTER_RST,
+	RGU_WWDT_RST = 4,
+	RGU_CREG_RST,
+	RGU_BUS_RST = 8,
+	RGU_SCU_RST,
+	RGU_M3_RST = 13,
+	RGU_LCD_RST = 16,
+	RGU_USB0_RST,
+	RGU_USB1_RST,
+	RGU_DMA_RST,
+	RGU_SDIO_RST,
+	RGU_EMC_RST,
+	RGU_ETHERNET_RST,
+	RGU_FLASHA_RST = 25,
+	RGU_EEPROM_RST = 27,
+	RGU_GPIO_RST,
+	RGU_FLASHB_RST,
+	RGU_TIMER0_RST = 32,
+	RGU_TIMER1_RST,
+	RGU_TIMER2_RST,
+	RGU_TIMER3_RST,
+	RGU_RITIMER_RST,
+	RGU_SCT_RST,
+	RGU_MOTOCONPWM_RST,
+	RGU_QEI_RST,
+	RGU_ADC0_RST,
+	RGU_ADC1_RST,
+	RGU_DAC_RST,
+	RGU_UART0_RST = 44,
+	RGU_UART1_RST,
+	RGU_UART2_RST,
+	RGU_UART3_RST,
+	RGU_I2C0_RST,
+	RGU_I2C1_RST,
+	RGU_SSP0_RST,
+	RGU_SSP1_RST,
+	RGU_I2S_RST,
+	RGU_SPIFI_RST,
+	RGU_CAN1_RST,
+	RGU_CAN0_RST,
+#ifdef CHIP_LPC43XX
+	RGU_M0APP_RST,
+	RGU_SGPIO_RST,
+	RGU_SPI_RST,
+#endif
+	RGU_LAST_RST = 63,
+} RGU_RST_TYPE;
+
+/**
+ * @brief RGU register structure
+ */
+typedef struct {							/*!< RGU Structure          */
+	__I  uint32_t  RESERVED0[64];
+	__O  uint32_t  RESET_CTRL0;				/*!< Reset control register 0 */
+	__O  uint32_t  RESET_CTRL1;				/*!< Reset control register 1 */
+	__I  uint32_t  RESERVED1[2];
+	__IO uint32_t  RESET_STATUS0;			/*!< Reset status register 0 */
+	__IO uint32_t  RESET_STATUS1;			/*!< Reset status register 1 */
+	__IO uint32_t  RESET_STATUS2;			/*!< Reset status register 2 */
+	__IO uint32_t  RESET_STATUS3;			/*!< Reset status register 3 */
+	__I  uint32_t  RESERVED2[12];
+	__I  uint32_t  RESET_ACTIVE_STATUS0;	/*!< Reset active status register 0 */
+	__I  uint32_t  RESET_ACTIVE_STATUS1;	/*!< Reset active status register 1 */
+	__I  uint32_t  RESERVED3[170];
+	__IO uint32_t  RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */
+} LPC_RGU_T;
+
+/**
+ * @brief	Trigger a peripheral reset for the selected peripheral
+ * @param	ResetNumber	: Peripheral reset number to trigger
+ * @return	Nothing
+ */
+void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber);
+
+/**
+ * @brief	Checks the reset status of a peripheral
+ * @param	ResetNumber	: Peripheral reset number to trigger
+ * @return	true if the periperal is still being reset
+ */
+bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber);
+
+/**
+ * @brief	Clears reset for the selected peripheral
+ * @param	ResetNumber	: Peripheral reset number to trigger
+ * @return	Nothing
+ * Almost all peripherals will auto clear the reset bit. Only a few peripherals
+ * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require
+ * this function to clear the reset bit.
+ */
+void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RGU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c

@@ -0,0 +1,67 @@
+/*
+ * @brief LPC18xx/43xx RITimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "ritimer_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set timer interval value */
+void Chip_RIT_SetTimerInterval(uint32_t time_interval)
+{
+	uint32_t clock_rate, cmp_value;
+
+	/* Get clock rate for RITimer */
+	clock_rate = Chip_Clock_GetRate(CLK_MX_RITIMER);
+
+	/* Determine aapproximate compare value based on clock rate and passed interval */
+	cmp_value = (clock_rate / 1000) * time_interval;
+
+	/* Set timer compare value */
+	Chip_RIT_SetCOMPVAL(cmp_value);
+	
+	/* Set timer enable clear bit to clear timer to 0 whenever
+	   counter value equals the contents of RICOMPVAL */
+	Chip_RIT_EnableCTRL(RIT_CTRL_ENCLR);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h

@@ -0,0 +1,146 @@
+/*
+ * @brief LPC18xx/43xx RITimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RITIMER_18XX_43XX_H_
+#define __RITIMER_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Initialize the RIT
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Init(void)
+{
+	IP_RIT_Init(LPC_RITIMER);
+}
+
+/**
+ * @brief	DeInitialize the RIT
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_DeInit(void)
+{
+	IP_RIT_DeInit(LPC_RITIMER);
+}
+
+/**
+ * @brief	Enable/Disable Timer
+ * @param	NewState	: ENABLE to enable timer, DISABLE to stop timer
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Cmd(FunctionalState NewState)
+{
+	IP_RIT_Enable(LPC_RITIMER, NewState);
+}
+
+/**
+ * @brief	Enable or disable timer debug
+ * @param	NewState	: ENABLE to halt timer whenever a hardware break condition occurs
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_TimerDebugCmd(FunctionalState NewState)
+{
+	IP_RIT_TimerDebugCmd(LPC_RITIMER, NewState);
+}
+
+/**
+ * @brief	Check whether interrupt flag is set or not
+ * @return	Current interrupt status, either ET or UNSET
+ */
+STATIC INLINE IntStatus Chip_RIT_GetIntStatus(void)
+{
+	return IP_RIT_GetIntStatus(LPC_RITIMER);
+}
+
+/**
+ * @brief	Set a tick value for the interrupt to time out
+ * @param	val	: value (in ticks) of the interrupt to be set
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_SetCOMPVAL(uint32_t val)
+{
+	IP_RIT_SetCOMPVAL(LPC_RITIMER, val);
+}
+
+/**
+ * @brief	Enables or clears the RIT or interrupt
+ * @param	val	: RIT to be set, one or more RIT_CTRL_* values
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_EnableCTRL(uint32_t val)
+{
+	IP_RIT_EnableCTRL(LPC_RITIMER, val);
+}
+
+/**
+ * @brief	Clears the RIT interrupt
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_ClearInt(void)
+{
+	IP_RIT_EnableCTRL(LPC_RITIMER, RIT_CTRL_INT);
+}
+
+/**
+ * @brief	Returns the current RIT Counter value
+ * @return	the current timer counter value
+ */
+STATIC INLINE uint32_t Chip_RIT_GetCounter(void)
+{
+	return IP_RIT_GetCounter(LPC_RITIMER);
+}
+
+/**
+ * @brief	Set timer interval value
+ * @param	time_interval	: timer interval value (ms)
+ * @return	None
+ */
+void Chip_RIT_SetTimerInterval(uint32_t time_interval);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RITIMER_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c

@@ -0,0 +1,57 @@
+/*
+ * @brief LPC18xx/43xx RTC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "rtc_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the RTC peripheral */
+void Chip_RTC_Init(void)
+{
+	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));	/* Reset 32Khz oscillator */
+	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);	/* Enable 32 kHz & 1 kHz on osc32k and release reset */
+	LPC_SCU->SFSCLK[0] = 1 | (0x3 << 2);/* function 1; CGU clk out, pull down */
+	IP_RTC_Init(LPC_RTC);
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c

@@ -0,0 +1,80 @@
+/*
+ * @brief LPC18xx/43xx System Control Unit (SCU) control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "scu_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Configure pin function */
+void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
+{
+	if (port == PINMUX_CLK) {
+		LPC_SCU_CLK(((uint32_t) LPC_SCU), pin) = mode + func;
+	}
+	else {
+		LPC_SCU->SFSP[port][pin] = mode + func;
+	}
+}
+
+/* GPIO Interrupt Pin Select */
+void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum)
+{
+	uint8_t  pinInt;
+	volatile uint32_t pinSel;
+
+	pinInt = ((PortNum & 0x7) << 5) | (PinNum & 0x1F);
+	if (PortSel < 4) {
+		pinSel = LPC_SCU->PINTSEL0;
+		pinSel &= ~(0xFF << (PortSel * 8));
+		pinSel |= (pinInt << (PortSel * 8));
+		LPC_SCU->PINTSEL0 = pinSel;
+	}
+	else {
+		pinSel = LPC_SCU->PINTSEL1;
+		pinSel &= ~(0xFF << ((PortSel - 4) * 8));
+		pinSel |= (pinInt << ((PortSel - 4) * 8));
+		LPC_SCU->PINTSEL1 = pinSel;
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SCU_18XX_43XX_H_
+#define __SCU_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions)
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief System Control Unit register block
+ */
+typedef struct {
+	__IO uint32_t  SFSP[16][32];
+	__I  uint32_t  RESERVED0[256];
+	__IO uint32_t  SFSCLK[4];			/*!< Pin configuration register for pins CLK0-3 */
+	__I  uint32_t  RESERVED16[28];
+	__IO uint32_t  SFSUSB;				/*!< Pin configuration register for USB */
+	__IO uint32_t  SFSI2C0;				/*!< Pin configuration register for I2C0-bus pins */
+	__IO uint32_t  ENAIO[3];			/*!< Analog function select registerS */
+	__I  uint32_t  RESERVED17[27];
+	__IO uint32_t  EMCDELAYCLK;			/*!< EMC clock delay register */
+	__I  uint32_t  RESERVED18[63];
+	__IO uint32_t  PINTSEL0;			/*!< Pin interrupt select register for pin interrupts 0 to 3. */
+	__IO uint32_t  PINTSEL1;			/*!< Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_Type;
+
+/** Port offset definition */
+#define PORT_OFFSET     0x80
+
+/** Pin offset definition */
+#define PIN_OFFSET      0x04
+
+/** Disable pull-down and pull-up resistor at resistor at pad */
+#define MD_PUP  (0x0 << 3)
+
+/** Enable pull-down resistor at pad */
+#define MD_BUK  (0x1 << 3)
+
+/** Enable pull-up resistor at pad */
+#define MD_PLN  (0x2 << 3)
+
+/** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define MD_PDN  (0x3 << 3)
+
+/** Enable fast slew rate */
+#define MD_EHS  (0x1 << 5)
+
+/** Input buffer enable */
+#define MD_EZI  (0x1 << 6)
+
+/** Disable input glitch filter */
+#define MD_ZI   (0x1 << 7)
+
+/** EHD driver strength low bit */
+#define MD_EHD0 (0x1 << 8)
+
+/** EHD driver strength high bit */
+#define MD_EHD1 (0x1 << 8)
+
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+
+/** Pin configuration for STANDARD/FAST mode I2C */
+#define I2C0_STANDARD_FAST_MODE  (1 << 3 | 1 << 11)
+
+/** Pin configuration for Fast-mode Plus I2C */
+#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
+
+#define FUNC0           0x0				/** Pin function 0 */
+#define FUNC1           0x1				/** Pin function 1 */
+#define FUNC2           0x2				/** Pin function 2 */
+#define FUNC3           0x3				/** Pin function 3 */
+#define FUNC4           0x4				/** Pin function 4 */
+#define FUNC5           0x5				/** Pin function 5 */
+#define FUNC6           0x6				/** Pin function 6 */
+#define FUNC7           0x7				/** Pin function 7 */
+
+/** Returns the SFSP register address in the SCU for a pin and port */
+#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
+
+/** Returns the address in the SCU for a SFSCLK clock register */
+#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
+
+#define PINMUX_CLK 0xFF
+
+/**
+ * @brief	Configure pin function
+ * @param	port	: Port number, should be: 0..15
+ * @param	pin		: Pin number, should be: 0..31
+ * @param	mode	: Pin mode, should be:
+ *                  - MD_PUP	:Pull-up enabled
+ *                  - MD_BUK	:Plain input
+ *                  - MD_PLN	:Repeater mode
+ *                  - MD_PDN	:Pull-down enabled
+ * @param	func	: Function mode, should be: FUNC0 to FUNC7
+ * @return	None
+ */
+void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
+
+/**
+ * @brief	GPIO Interrupt Pin Select
+ * @param	PortSel	: GPIO PINTSEL interrupt, should be: 0 to 7
+ * @param	PortNum	: GPIO port number interrupt, should be: 0 to 7
+ * @param	PinNum	: GPIO pin number Interrupt , should be: 0 to 31
+ * @return	None
+ */
+void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
+
+/**
+ * @brief	I2C Pin Configuration
+ * @param	I2C0Mode	: I2C0 mode, should be:
+ *                  - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit
+ *                  - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit
+ * @return	None
+ */
+STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
+{
+	LPC_SCU->SFSI2C0 = I2C0Mode;
+}
+
+/**
+ * @brief	ADC Pin Configuration
+ * @param	ADC_ID	: ADC number
+ * @param	channel	: ADC channel
+ * @return	None
+ */
+STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
+{
+	LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SCU_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c

@@ -0,0 +1,70 @@
+/*
+ * @brief LPC18xx/43xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "wwdt_18xx_43xx.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the Watchdog timer */
+void Chip_WWDT_Init(void)
+{
+	/* Disable watchdog */
+	LPC_WWDT->MOD       = 0;
+	LPC_WWDT->TC        = 0xFF;
+	LPC_WWDT->WARNINT   = 0xFFFF;
+	LPC_WWDT->WINDOW    = 0xFFFFFF;
+}
+
+/* Clear WWDT interrupt status flags */
+void Chip_WWDT_ClearStatusFlag(uint32_t status)
+{
+	if (status & WWDT_WDMOD_WDTOF) {
+		LPC_WWDT->MOD &= ~WWDT_WDMOD_WDTOF;
+	}
+
+	if (status & WWDT_WDMOD_WDINT) {
+		LPC_WWDT->MOD |= WWDT_WDMOD_WDINT;
+	}
+}

bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h

@@ -0,0 +1,191 @@
+/*
+ * @brief LPC18xx/43xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __WWDT_18XX_43XX_H_
+#define __WWDT_18XX_43XX_H_
+
+#include "chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx WWDT driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+/** WDT oscillator frequency value */
+#define WDT_OSC     (CGU_IRC_FREQ)
+
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDEN             ((uint32_t) (1 << 0))
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDRESET          ((uint32_t) (1 << 1))
+/** WWDT time out flag bit */
+#define WWDT_WDMOD_WDTOF            ((uint32_t) (1 << 2))
+/** WDT Time Out flag bit */
+#define WWDT_WDMOD_WDINT            ((uint32_t) (1 << 3))
+/** WWDT Protect flag bit */
+#define WWDT_WDMOD_WDPROTECT        ((uint32_t) (1 << 4))
+
+/** Minimum tick count for timer value and window value */
+#define WWDT_TICKS_MIN 0xFF
+
+/** Maximum tick count for timer value and window value */
+#define WWDT_TICKS_MAX 0xFFFFFF
+
+/**
+ * @brief	Initialize the Watchdog timer
+ * @return	None
+ */
+void Chip_WWDT_Init(void);
+
+/**
+ * @brief	Set WDT timeout constant value used for feed
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	none
+ */
+STATIC INLINE void Chip_WWDT_SetTimeOut(uint32_t timeout)
+{
+	LPC_WWDT->TC = timeout;
+}
+
+/**
+ * @brief	Feed watchdog timer
+ * @return	None
+ * If this function isn't called, a watchdog timer warning will occur.
+ * After the warning, a timeout will occur if a feed has happened.
+ */
+STATIC INLINE void Chip_WWDT_Feed(void)
+{
+	LPC_WWDT->FEED = 0xAA;
+	LPC_WWDT->FEED = 0x55;
+}
+
+/**
+ * @brief	Set WWDT warning interrupt
+ * @param	timeout	: WDT warning in ticks, between 0 and 1023
+ * @return	None
+ * This is the number of ticks after the watchdog interrupt that the
+ * warning interrupt will be generated.
+ */
+STATIC INLINE void Chip_WWDT_SetWarning(uint32_t timeout)
+{
+	LPC_WWDT->WARNINT = timeout;
+}
+
+/**
+ * @brief	Set WWDT window time
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	none
+ * The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
+ * function and this function, with this function defining the last tick before the
+ * watchdog window interrupt occurs.
+ */
+STATIC INLINE void Chip_WWDT_SetWindow(uint32_t timeout)
+{
+	LPC_WWDT->WINDOW = timeout;
+}
+
+/**
+ * @brief	Enable watchdog timer options
+ * @param	options : An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
+ * are set (or unset) with no other options.
+ */
+STATIC INLINE void Chip_WWDT_SetOption(uint32_t options)
+{
+	LPC_WWDT->MOD |= options;
+}
+
+/**
+ * @brief	Disable/clear watchdog timer options
+ * @param	options : An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDTOF).
+ */
+STATIC INLINE void Chip_WWDT_UnsetOption(uint32_t options)
+{
+	LPC_WWDT->MOD &= ~options;
+}
+
+/**
+ * @brief	Enable WWDT activity
+ * @return	None
+ */
+STATIC INLINE void Chip_WWDT_Start(void)
+{
+	Chip_WWDT_SetOption(WWDT_WDMOD_WDEN);
+	Chip_WWDT_Feed();
+}
+
+/**
+ * @brief	Read WWDT status flag
+ * @return	Watchdog status, an Or'ed value of WWDT_WDMOD_*
+ */
+STATIC INLINE uint32_t Chip_WWDT_GetStatus(void)
+{
+	return LPC_WWDT->MOD;
+}
+
+/**
+ * @brief	Clear WWDT interrupt status flags
+ * @param	flag	: Or'ed value of status flag(s) that you want to clear, should be:
+ *              - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
+ *              - WWDT_WDMOD_WDINT: Clear watchdog warning flag
+ * @return	None
+ */
+void Chip_WWDT_ClearStatusFlag(uint32_t status);
+
+/**
+ * @brief	Get the current value of WDT
+ * @return	current value of WDT
+ */
+STATIC INLINE uint32_t WWDT_GetCurrentCount(void)
+{
+	return LPC_WWDT->TV;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WWDT_18XX_43XX_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h

@@ -0,0 +1,116 @@
+/*
+ * @brief    Generic memory tests
+ *           Various memory tests for testing external memory integrity. Includes
+ *           inverse address, walking bit, and pattern tests.
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __MEM_TESTS_H_
+#define __MEM_TESTS_H_
+
+#include "lpc_types.h"
+
+/** @defgroup CHIP_Memory_Tests CHIP: Various RAM memory tests
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief Memory test address/size and result structure
+ */
+typedef struct {
+	uint32_t *start_addr;	/*!< Starting address for memory test */
+	uint32_t bytes;			/*!< Size in bytes for memory test */
+	uint32_t *fail_addr;	/*!< Failed address of test (returned only if failed) */
+	uint32_t is_val;		/*!< Failed value of test (returned only if failed) */
+	uint32_t ex_val;		/*!< Expected value of test (returned only if failed) */
+} MEM_TEST_SETUP_T;
+
+/**
+ * @brief	Walking 0 memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes a shifting 0 bit pattern to the entire memory range and
+ * verifies the result after all memory locations are written
+ */
+bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Walking 1 memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes a shifting 1 bit pattern to the entire memory range and
+ * verifies the result after all memory locations are written
+ */
+bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Address memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes the address to each memory location and verifies the
+ * result after all memory locations are written
+ */
+bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Inverse address memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes the inverse address to each memory location and verifies the
+ * result after all memory locations are written
+ */
+bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Pattern memory test
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @return	true if the test passed, or false on failure
+ * Writes the an alternating 0x55/0xAA pattern to each memory location
+ * and verifies the result after all memory locations are written
+ */
+bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup);
+
+/**
+ * @brief	Pattern memory test with seed and increment value
+ * @param	pMemSetup	: Memory test setup (and returned results)
+ * @param	seed		: Initial seed value for test
+ * @param	incr		: Increment value for each memory location
+ * @return	true if the test passed, or false on failure
+ * Writes the an alternating pattern to each memory location based on a
+ * passed seedn and increment value and verifies the result after all
+ * memory locations are written
+ */
+bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr);
+
+/**
+ * @}
+ */
+
+#endif /* __MEM_TESTS_H_ */

bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c

@@ -0,0 +1,168 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "ring_buffer.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize ring buffer */
+void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
+{
+	RingBuff->bufferBase = RingBuff->bufferIn = RingBuff->bufferOut = buffer;
+	RingBuff->bufferLast = RingBuff->bufferBase + (itemSize * count);
+	RingBuff->count = count;
+	RingBuff->itemSize = itemSize;
+	RingBuff->used = 0;
+}
+
+/* Return empty status of ring buffer */
+bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8)
+{
+	bool full = RingBuffer_IsFull(RingBuff);
+
+	if (!full) {
+		*RingBuff->bufferIn = data8;
+		RingBuff->used++;
+		RingBuff->bufferIn++;
+		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
+			RingBuff->bufferIn = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !full;
+}
+
+/* Insert 16-bit value in ring buffer */
+bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16)
+{
+	bool full = RingBuffer_IsFull(RingBuff);
+
+	if (!full) {
+		uint16_t *buff16 = (uint16_t *) RingBuff->bufferIn;
+		*buff16 = data16;
+		RingBuff->used++;
+		buff16++;
+		RingBuff->bufferIn = (uint8_t *) buff16;
+		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
+			RingBuff->bufferIn = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !full;
+}
+
+/* Insert 32-bit value in ring buffer */
+bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32)
+{
+	bool full = RingBuffer_IsFull(RingBuff);
+
+	if (!full) {
+		uint32_t *buff32 = (uint32_t *) RingBuff->bufferIn;
+		*buff32 = data32;
+		RingBuff->used++;
+		buff32++;
+		RingBuff->bufferIn = (uint8_t *) buff32;
+		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
+			RingBuff->bufferIn = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !full;
+}
+
+/* Pop a 8-bit value from the ring buffer */
+bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8)
+{
+	bool empty = RingBuffer_IsEmpty(RingBuff);
+
+	if (!empty) {
+		*data8 = *RingBuff->bufferOut;
+		RingBuff->used--;
+		RingBuff->bufferOut++;
+		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
+			RingBuff->bufferOut = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !empty;
+}
+
+/* Pop a 16-bit value from the ring buffer */
+bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16)
+{
+	bool empty = RingBuffer_IsEmpty(RingBuff);
+
+	if (!empty) {
+		uint16_t *buff16 = (uint16_t *) RingBuff->bufferOut;
+		*data16 = *buff16;
+		RingBuff->used--;
+		buff16++;
+		RingBuff->bufferOut = (uint8_t *) buff16;
+		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
+			RingBuff->bufferOut = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !empty;
+}
+
+/* Pop a 32-bit value from the ring buffer */
+bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32)
+{
+	bool empty = RingBuffer_IsEmpty(RingBuff);
+
+	if (!empty) {
+		uint32_t *buff32 = (uint32_t *) RingBuff->bufferOut;
+		*data32 = *buff32;
+		RingBuff->used--;
+		data32++;
+		RingBuff->bufferOut = (uint8_t *) data32;
+		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
+			RingBuff->bufferOut = RingBuff->bufferBase;
+		}
+	}
+
+	return (bool) !empty;
+}

bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h

@@ -0,0 +1,143 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RING_BUFFER_H_
+#define __RING_BUFFER_H_
+
+#include "lpc_types.h"
+
+/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief Ring buffer structure
+ */
+typedef struct {
+	uint8_t *bufferBase, *bufferLast;
+	uint8_t *bufferIn, *bufferOut;
+	int count, used, itemSize;
+} RINGBUFF_T;
+
+/**
+ * @brief	Initialize ring buffer
+ * @param	RingBuff	: Pointer to ring buffer to initialize
+ * @param	buffer		: Pointer to buffer to associate with RingBuff
+ * @param	itemSize	: Size of each buffer item size (1, 2 or 4 bytes)
+ * @param	count		: Size of ring buffer
+ * @return	Nothing
+ */
+void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Number of items in the ring buffer
+ */
+STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
+{
+	return RingBuff->used;
+}
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	true if the ring buffer is full, otherwise false
+ */
+STATIC INLINE bool RingBuffer_IsFull(RINGBUFF_T *RingBuff)
+{
+	return (bool) (RingBuff->used >= RingBuff->count);
+}
+
+/**
+ * @brief	Return empty status of ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	true if the ring buffer is empty, otherwise false
+ */
+STATIC INLINE bool RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
+{
+	return (bool) (RingBuff->used == 0);
+}
+
+/**
+ * @brief	Insert 8-bit value in ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data8		: Byte to insert in ring buffer
+ * @return	true if a valid byte was inserted, or false if the ring buffer was full
+ */
+bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8);
+
+/**
+ * @brief	Insert 16-bit value in ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data16		: 16-bit value to insert in ring buffer
+ * @return	true if valid data was inserted, or false if the ring buffer was full
+ */
+bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16);
+
+/**
+ * @brief	Insert 32-bit value in ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data32		: 32-bit value to insert in ring buffer
+ * @return	true if valid data was inserted, or false if the ring buffer was full
+ */
+bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32);
+
+/**
+ * @brief	Pop a 8-bit value from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data8		: Pointer to where to place value
+ * @return	true if a valid byte was popped, or false if the ring buffer was empty
+ */
+bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8);
+
+/**
+ * @brief	Pop a 16-bit value from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data16		: Pointer to where to place value
+ * @return	true if a valid byte was popped, or false if the ring buffer was empty
+ */
+bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16);
+
+/**
+ * @brief	Pop a 32-bit value from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data32		: Pointer to where to place value
+ * @return	true if a valid byte was popped, or false if the ring buffer was empty
+ */
+bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32);
+
+/**
+ * @}
+ */
+
+#endif /* __RING_BUFFER_H_ */

bsp/xplorer4330/libraries/lpc_ip/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('lpc_ip', src, depend = [], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xplorer4330/libraries/lpc_ip/adc_001.c

@@ -0,0 +1,170 @@
+/*
+ * @brief ADC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "adc_001.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Configure clock for ADC */
+static void SetClock(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy)
+{
+	uint32_t temp, adcBitRate;
+
+	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
+	   A/D converter, which should be less than or equal to 4.5MHz.
+	   A fully conversion requires (bits_accuracy+1) of these clocks.
+	   ADC clock = PCLK_ADC0 / (CLKDIV + 1);
+	   ADC rate = ADC clock / (bits_accuracy+1);
+	 */
+	adcBitRate = (adcRate * (11 - bitsAccuracy));
+
+	/* Get the round value by fomular: (2*A + B)/(2*B) */
+	temp = ((adcPerClock * 2 + adcBitRate) / (adcBitRate * 2)) - 1;
+
+	/* Enable PDN bit and clock bits */
+	pADC->CR &= ~(ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07));
+	pADC->CR |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(bitsAccuracy);
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC */
+void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy)
+{
+	pADC->INTEN = 0;		/* Disable all interrupts */
+	pADC->CR |= ADC_CR_PDN;	/* Set PDN bit for ADC*/
+	SetClock(pADC, adcRate, adcPerClock, bitsAccuracy);
+}
+
+/* Shutdown ADC */
+void IP_ADC_DeInit(IP_ADC_001_Type *pADC)
+{
+	pADC->INTEN = 0x00000100;
+	pADC->CR = 0;
+}
+
+/* Set burst mode for ADC */
+void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState)
+{
+	if (NewState == DISABLE) {
+		pADC->CR &= ~ADC_CR_BURST;
+	}
+	else {
+		pADC->CR |= ADC_CR_BURST;
+	}
+}
+
+/* Get the ADC value */
+Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data)
+{
+	uint32_t temp;
+	temp = pADC->DR[channel];
+	if (!ADC_DR_DONE(temp)) {
+		return ERROR;
+	}
+	//	if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST))
+	//	return ERROR;
+	*data = (uint16_t) ADC_DR_RESULT(temp);
+	return SUCCESS;
+}
+
+/* Get ADC Channel status from ADC data register */
+FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType)
+{
+	switch (StatusType) {
+	case ADC_DR_DONE_STAT:
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_OVERRUN_STAT:
+		channel += 8;
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_ADINT_STAT:
+		return pADC->STAT >> 16 ? SET : RESET;
+
+	default:
+		break;
+	}
+	return RESET;
+}
+
+/* Set the edge start condition */
+void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode)
+{
+	if (edge_mode) {
+		pADC->CR |= ADC_CR_EDGE;
+	}
+	else {
+		pADC->CR &= ~ADC_CR_EDGE;
+	}
+}
+
+/* Enable/Disable ADC channel number */
+void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->CR |= ADC_CR_CH_SEL(channel);
+	}
+	else {
+		pADC->CR &= ~ADC_CR_START_MASK;
+		pADC->CR &= ~ADC_CR_CH_SEL(channel);
+	}
+}
+
+/* Set start mode for ADC */
+void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode)
+{
+	pADC->CR &= ~ADC_CR_START_MASK;
+	pADC->CR |= ADC_CR_START_MODE_SEL((uint32_t) start_mode);
+}
+
+/* Enable/Disable interrupt for ADC channel */
+void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->INTEN |= (1UL << channel);
+	}
+	else {
+		pADC->INTEN &= (~(1UL << channel));
+	}
+}

bsp/xplorer4330/libraries/lpc_ip/adc_001.h

@@ -0,0 +1,182 @@
+/*
+ * @brief ADC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_001_H_
+#define __ADC_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief 10 or 12-bit ADC register block structure
+ */
+typedef struct {					/*!< ADCn Structure */
+	__IO uint32_t CR;				/*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+	__I  uint32_t GDR;				/*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+	__I  uint32_t RESERVED0;
+	__IO uint32_t INTEN;			/*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+	__I  uint32_t DR[8];			/*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+	__I  uint32_t STAT;				/*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+#if !defined(CHIP_LPC18XX) && !defined(CHIP_LPC43XX)
+	__IO uint32_t ADTRM;
+#endif
+} IP_ADC_001_Type;
+
+/**
+ * @brief ADC register support bitfields and mask
+ */
+#define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF))	/*!< Mask for getting the ADC data read value */
+#define ADC_DR_DONE(n)          (((n) >> 31))			/*!< Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL)))	/*!< Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n)        ((1UL << (n)))			/*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))	/*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST            ((1UL << 16))			/*!< Repeated conversions A/D enable bit */
+#define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))	/*!< Number of ADC accuracy bits */
+#define ADC_CR_PDN              ((1UL << 21))			/*!< ADC convert in power down mode */
+#define ADC_CR_START_MASK       ((7UL << 24))			/*!< ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))		/*!< Select Start Mode */
+#define ADC_CR_START_NOW        ((1UL << 24))			/*!< Start conversion now */
+#define ADC_CR_START_CTOUT15    ((2UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8     ((3UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0   ((4UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1   ((5UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2      ((6UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE             ((1UL << 27))			/*!< Start conversion on a falling edge on the selected CAP/MAT signal */
+
+/**
+ * @brief	ADC status register used for IP drivers
+ */
+typedef enum {
+	ADC_DR_DONE_STAT,	/*!< ADC data register staus */
+	ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
+	ADC_DR_ADINT_STAT	/*!< ADC interrupt status */
+} IP_ADC_Status;
+
+/**
+ * @brief	Initialize for ADC
+ * @param	pADC			: The base of ADC peripheral on the chip
+ * @param	adcRate			: Sample rate of A/D converter
+ * @param	adcPerClock		: The APB clock
+ * @param	bitsAccuracy	: The accuracy of LSB value, should be ADC_10BITS -> ADC_3BITS
+ * @return	 Nothing
+ * Disable all ADC interrupts, set bit PDN, set ADC clock frequency
+ * This is not the sample rate, but the clock for the ADC machine, and is usually set to
+ * maximum. Applications may choose a lower frequency if they have high-impedance sources.
+ * This is because a lower clock frequency produces a longer sampling time.
+ */
+void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy);
+
+/**
+ * @brief	Shutdown ADC
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @return	Nothing
+ * Reset the ADC control and INTEN Register to reset values (disabled)
+ */
+void IP_ADC_DeInit(IP_ADC_001_Type *pADC);
+
+/**
+ * @brief	Set burst mode for ADC
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: ENABLE for burst mode, or DISABLE for normal mode
+ * @return	Nothing
+ */
+void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState);
+
+/**
+ * @brief	Get the ADC value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel to be read value, should be 0..7
+ * @param	data		: Data buffer to store the A/D value
+ * @return	Status		: SUCCESS or ERROR
+ */
+Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data);
+
+/**
+ * @brief	Get ADC Channel status from ADC data register
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel number, should be 0..7
+ * @param	StatusType	: Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT
+ * @return	Channel status, SET or RESET
+ */
+FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType);
+
+/**
+ * @brief	Set the edge start condition
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	edge_mode	: 0 = rising, != = falling
+ * @return	Nothing
+ */
+void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode);
+
+/**
+ * @brief	Enable/Disable ADC channel number
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel number
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
+
+/**
+ * @brief	Set start mode for ADC
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	start_mode	: Start mode choose one of modes in 'ADC_START_*' enumeration type definitions
+ * @return	Nothing
+ */
+void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode);
+
+/**
+ * @brief	Enable/Disable interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel assert the interrupt
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/atimer_001.c

@@ -0,0 +1,55 @@
+/*
+ * @brief Alarm Timer Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "atimer_001.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Close ATIMER device */
+void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer)
+{
+	IP_ATIMER_ClearIntStatus(pATimer);
+	IP_ATIMER_IntDisable(pATimer);
+}

bsp/xplorer4330/libraries/lpc_ip/atimer_001.h

@@ -0,0 +1,160 @@
+/*
+ * @brief Alarm Timer Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ATIMER_001_H_
+#define __ATIMER_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_ATIMER_001 IP: ATimer register block and driver
+ * @ingroup IP_Drivers
+ * Alarm timer
+ * @{
+ */
+
+/**
+ * @brief Alarm Timer register block structure
+ */
+typedef struct {					/*!< ATIMER Structure       */
+	__IO uint32_t DOWNCOUNTER;		/*!< Downcounter register   */
+	__IO uint32_t PRESET;			/*!< Preset value register  */
+	__I  uint32_t RESERVED0[1012];
+	__O  uint32_t CLR_EN;			/*!< Interrupt clear enable register */
+	__O  uint32_t SET_EN;			/*!< Interrupt set enable register */
+	__I  uint32_t STATUS;			/*!< Status register        */
+	__I  uint32_t ENABLE;			/*!< Enable register        */
+	__O  uint32_t CLR_STAT;			/*!< Clear register         */
+	__O  uint32_t SET_STAT;			/*!< Set register           */
+} IP_ATIMER_001_Type;
+
+/**
+ * @brief	Close ATIMER device
+ * @param	pATimer	:  Pointer to timer device
+ * @return	None
+ * Important: 32KHz clock must be enabled in CREG prior to this call. See
+ * the User Manual for more information.
+ */
+void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer);
+
+/**
+ * @brief	Clear ATIMER Interrupt Status
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_ClearIntStatus(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->CLR_STAT = 1;
+}
+
+/**
+ * @brief	Set ATIMER Interrupt Status
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_SetIntStatus(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->SET_STAT = 1;
+}
+/**
+ * @brief	Enable ATIMER Interrupt
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_IntEnable(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->SET_EN = 1;
+}
+
+/**
+ * @brief	Disable ATIMER Interrupt
+ * @param	pATimer	: Pointer to timer device
+ * @return	None
+ */
+STATIC INLINE void IP_ATIMER_IntDisable(IP_ATIMER_001_Type *pATimer)
+{
+	pATimer->CLR_EN = 1;
+}
+
+/**
+ * @brief	Update Preset value
+ * @param	pATimer	: Pointer to timer device
+ * @param	PresetValue	updated preset value
+ * @return	Nothing
+ */
+STATIC INLINE void IP_ATIMER_UpdatePresetValue(IP_ATIMER_001_Type *pATimer, uint32_t PresetValue)
+{
+	pATimer->PRESET = PresetValue;
+}
+
+/**
+ * @brief	Read value of preset register
+ * @param	pATimer	: Pointer to timer/counter device
+ * @return	Value of capture register
+ */
+STATIC INLINE uint32_t IP_ATIMER_GetPresetValue(IP_ATIMER_001_Type *pATimer)
+{
+	return pATimer->PRESET;
+}
+
+/**
+ * @brief	Returns enable state of ATimer interrupt
+ * @param	pATimer	: Pointer to timer/counter device
+ * @return	!0 if the ATimer interrupt is enabled, otherwise 0
+ */
+STATIC INLINE uint32_t IP_ATIMER_GetIntEnableState(IP_ATIMER_001_Type *pATimer)
+{
+	return pATimer->ENABLE;
+}
+
+/**
+ * @brief	Returns current pending state of ATimer interrupt
+ * @param	pATimer	: Pointer to timer/counter device
+ * @return	!0 if the ATimer interrupt is asserted, otherwise 0
+ */
+STATIC INLINE uint32_t IP_ATIMER_GetIntPendingState(IP_ATIMER_001_Type *pATimer)
+{
+	return pATimer->STATUS;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ATIMER_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/ccan_001.h

@@ -0,0 +1,114 @@
+/*
+ * @brief CCAN registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CCAN_001_H_
+#define __CCAN_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_CCAN_001 IP: CCAN register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief CCAN Controller Area Network register block structure
+ */
+typedef struct {						/*!< C_CAN Structure       */
+	__IO uint32_t CNTL;					/*!< CAN control            */
+	__IO uint32_t STAT;					/*!< Status register        */
+	__I  uint32_t EC;					/*!< Error counter          */
+	__IO uint32_t BT;					/*!< Bit timing register    */
+	__I  uint32_t INT;					/*!< Interrupt register     */
+	__IO uint32_t TEST;					/*!< Test register          */
+	__IO uint32_t BRPE;					/*!< Baud rate prescaler extension register */
+	__I  uint32_t  RESERVED0;
+	__IO uint32_t IF1_CMDREQ;			/*!< Message interface command request  */
+	union {
+		__IO uint32_t IF1_CMDMSK_R;		/*!< Message interface command mask (read direction) */
+		__IO uint32_t IF1_CMDMSK_W;		/*!< Message interface command mask (write direction) */
+	};
+
+	__IO uint32_t IF1_MSK1;				/*!< Message interface mask 1 */
+	__IO uint32_t IF1_MSK2;				/*!< Message interface 1 mask 2 */
+	__IO uint32_t IF1_ARB1;				/*!< Message interface 1 arbitration 1 */
+	__IO uint32_t IF1_ARB2;				/*!< Message interface 1 arbitration 2 */
+	__IO uint32_t IF1_MCTRL;			/*!< Message interface 1 message control */
+	__IO uint32_t IF1_DA1;				/*!< Message interface data A1 */
+	__IO uint32_t IF1_DA2;				/*!< Message interface 1 data A2 */
+	__IO uint32_t IF1_DB1;				/*!< Message interface 1 data B1 */
+	__IO uint32_t IF1_DB2;				/*!< Message interface 1 data B2 */
+	__I  uint32_t  RESERVED1[13];
+	__IO uint32_t IF2_CMDREQ;			/*!< Message interface command request  */
+	union {
+		__IO uint32_t IF2_CMDMSK_R;		/*!< Message interface command mask (read direction) */
+		__IO uint32_t IF2_CMDMSK_W;		/*!< Message interface command mask (write direction) */
+	};
+
+	__IO uint32_t IF2_MSK1;				/*!< Message interface mask 1 */
+	__IO uint32_t IF2_MSK2;				/*!< Message interface 1 mask 2 */
+	__IO uint32_t IF2_ARB1;				/*!< Message interface 1 arbitration 1 */
+	__IO uint32_t IF2_ARB2;				/*!< Message interface 1 arbitration 2 */
+	__IO uint32_t IF2_MCTRL;			/*!< Message interface 1 message control */
+	__IO uint32_t IF2_DA1;				/*!< Message interface data A1 */
+	__IO uint32_t IF2_DA2;				/*!< Message interface 1 data A2 */
+	__IO uint32_t IF2_DB1;				/*!< Message interface 1 data B1 */
+	__IO uint32_t IF2_DB2;				/*!< Message interface 1 data B2 */
+	__I  uint32_t  RESERVED2[21];
+	__I  uint32_t TXREQ1;				/*!< Transmission request 1 */
+	__I  uint32_t TXREQ2;				/*!< Transmission request 2 */
+	__I  uint32_t  RESERVED3[6];
+	__I  uint32_t ND1;					/*!< New data 1             */
+	__I  uint32_t ND2;					/*!< New data 2             */
+	__I  uint32_t  RESERVED4[6];
+	__I  uint32_t IR1;					/*!< Interrupt pending 1    */
+	__I  uint32_t IR2;					/*!< Interrupt pending 2    */
+	__I  uint32_t  RESERVED5[6];
+	__I  uint32_t MSGV1;				/*!< Message valid 1        */
+	__I  uint32_t MSGV2;				/*!< Message valid 2        */
+	__I  uint32_t  RESERVED6[6];
+	__IO uint32_t CLKDIV;				/*!< CAN clock divider register */
+} IP_CCAN_001_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CCAN_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/dac_001.h

@@ -0,0 +1,64 @@
+/*
+ * @brief DAC Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __DAC_001_H_
+#define __DAC_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_DAC_001 IP: DAC register block and driver
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief DAC register block structure
+ */
+typedef struct {			/*!< DAC Structure          */
+	__IO uint32_t  CR;		/*!< DAC register. Holds the conversion data. */
+	__IO uint32_t  CTRL;	/*!< DAC control register.  */
+	__IO uint32_t  CNTVAL;	/*!< DAC counter value register. */
+} IP_DAC_001_Type;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_001_H_ */

bsp/xplorer4330/libraries/lpc_ip/fpu_init.c

@@ -0,0 +1,94 @@
+/*
+ * @brief FPU init code
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#if defined(CORE_M4)
+
+#include "stdint.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define LPC_CPACR           0xE000ED88
+
+#define SCB_MVFR0           0xE000EF40
+#define SCB_MVFR0_RESET     0x10110021
+
+#define SCB_MVFR1           0xE000EF44
+#define SCB_MVFR1_RESET     0x11000011
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Early initialization of the FPU */
+void fpuInit(void)
+{
+	// from arm trm manual:
+	//                ; CPACR is located at address 0xE000ED88
+	//                LDR.W R0, =0xE000ED88
+	//                ; Read CPACR
+	//                LDR R1, [R0]
+	//                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+	//                ORR R1, R1, #(0xF << 20)
+	//                ; Write back the modified value to the CPACR
+	//                STR R1, [R0]
+
+	volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
+	volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
+	volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
+	volatile uint32_t Cpacr;
+	volatile uint32_t Mvfr0;
+	volatile uint32_t Mvfr1;
+	char vfpPresent = 0;
+
+	Mvfr0 = *regMvfr0;
+	Mvfr1 = *regMvfr1;
+
+	vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+	if (vfpPresent) {
+		Cpacr = *regCpacr;
+		Cpacr |= (0xF << 20);
+		*regCpacr = Cpacr;	// enable CP10 and CP11 for full access
+	}
+
+}
+
+#endif /* defined(CORE_M4 */

bsp/xplorer4330/libraries/lpc_ip/fpu_init.h

@@ -0,0 +1,56 @@
+/*
+ * @brief FPU init code
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FPU_INIT_H_
+#define __FPU_INIT_H_
+
+#if defined(CORE_M4)
+
+/**
+ * @defgroup IP_FPU_CMX_001 IP: FPU initialization
+ * @ingroup IP_Drivers
+ * Cortex FPU initialization
+ * @{
+ */
+
+/**
+ * @brief	Early initialization of the FPU
+ * @return	Nothing
+ */
+void fpuInit(void);
+
+/**
+ * @}
+ */
+
+#endif /* #if defined */
+
+#endif /* __FPU_INIT_H_ */