Merge pull request #4116 from thread-liu/step4-ev1

[add] drivers for stm32mp157a-ev1
This commit is contained in:
Bernard Xiong authored and GitHub committed 2020-12-05 14:54:13 +08:00
commit 286d4f657e
37 files changed
+7757 -87

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@@ -0,0 +1,56 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
#define __QSPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_QSPI
#ifndef QSPI_BUS_CONFIG
#define QSPI_BUS_CONFIG \
{ \
.Instance = QUADSPI, \
.Init.FifoThreshold = 4, \
.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
}
#endif /* QSPI_BUS_CONFIG */
#endif /* BSP_USING_QSPI */
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance = QSPI_DMA_INSTANCE, \
.Init.Channel = QSPI_DMA_CHANNEL, \
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
.Init.PeriphInc = DMA_PINC_DISABLE, \
.Init.MemInc = DMA_MINC_ENABLE, \
.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
.Init.Mode = DMA_NORMAL, \
.Init.Priority = DMA_PRIORITY_LOW \
}
#endif /* QSPI_DMA_CONFIG */
#endif /* BSP_QSPI_USING_DMA */
#define QSPI_IRQn QUADSPI_IRQn
#define QSPI_IRQHandler QUADSPI_IRQHandler
#ifdef __cplusplus
}
#endif
#endif /* __QSPI_CONFIG_H__ */
@@ -23,7 +23,6 @@ extern "C" {
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.irq_type = SPI1_IRQn, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
@@ -58,7 +57,6 @@ extern "C" {
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_IRQn, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
@@ -93,7 +91,6 @@ extern "C" {
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.irq_type = SPI3_IRQn, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
@@ -128,7 +125,6 @@ extern "C" {
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
.irq_type = SPI4_IRQn, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
@@ -110,6 +110,7 @@ extern "C" {
#elif defined(SOC_SERIES_STM32MP1)
#include "mp1/dma_config.h"
#include "mp1/uart_config.h"
#include "mp1/qspi_config.h"
#include "mp1/spi_config.h"
#include "mp1/adc_config.h"
#include "mp1/dac_config.h"
+1 -1
View File
@@ -147,7 +147,7 @@ static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
{
return gen_random ;
}
return 0;
}
+5 -1
View File
@@ -52,8 +52,12 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
qspi_bus->QSPI_Handler = QSPI_Handler_config;
#if defined(SOC_SERIES_STM32MP1)
while (cfg->max_hz < HAL_RCC_GetACLKFreq() / (i + 1))
#else
while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
{
#endif
{
i++;
if (i == 255)
{
+16 -1
View File
@@ -66,7 +66,9 @@ if GetDepend(['RT_USING_SDIO']):
if GetDepend(['RT_USING_AUDIO']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai_ex.c']
if GetDepend(['BSP_USING_DCMI']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dcmi.c']
if GetDepend(['BSP_USING_FMC']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fsmc.c']
@@ -89,6 +91,19 @@ if GetDepend(['BSP_USING_LTDC']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma2d.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dsi.c']
if GetDepend(['BSP_USING_FDCAN']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c']
if GetDepend(['BSP_USING_QSPI']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c']
if GetDepend(['BSP_USING_SPDIFRX']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spdifrx.c']
if GetDepend(['BSP_USING_DFSDM']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm_ex.c']
if GetDepend(['BSP_USING_SDMMC']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c']
@@ -34,16 +34,16 @@
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
/*#define HAL_DCMI_MODULE_ENABLED */
#define HAL_DCMI_MODULE_ENABLED
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
#define HAL_DFSDM_MODULE_ENABLED
/*#define HAL_DTS_MODULE_ENABLED */
/*#define HAL_ETH_MODULE_ENABLED */
/*#define HAL_FDCAN_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
#define HAL_FDCAN_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
/*#define HAL_HCD_MODULE_ENABLED */
#define HAL_HSEM_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
@@ -55,14 +55,14 @@
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SPDIFRX_MODULE_ENABLED */
#define HAL_SPDIFRX_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_TAMP_MODULE_ENABLED */
File diff suppressed because it is too large. Load diff
+98 -19
View File
@@ -14,6 +14,10 @@ menu "Onboard Peripheral Drivers"
select BSP_USING_UART
select BSP_USING_UART4
default y
config BSP_USING_EXTI
bool "Enable exti sample"
default n
config BSP_USING_PMIC
bool "Enable PMIC"
@@ -21,6 +25,12 @@ menu "Onboard Peripheral Drivers"
select BSP_USING_I2C3
default y
config BSP_USING_PWR
bool "Enable PM (power control)"
select BSP_USING_LPTIM
select BSP_USING_LPTIM1
default n
config BSP_USING_NAND
bool "Enable FMC (MT29F8G08ABACAH4)"
select RT_USING_FMC
@@ -28,6 +38,13 @@ menu "Onboard Peripheral Drivers"
select RT_MTD_NAND_DEBUG
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (MX25L51245G)"
select BSP_USING_QSPI
select RT_USING_SFUD
select RT_SFUD_USING_QSPI
default n
config BSP_USING_OPENAMP
bool "Enable OpenAMP"
select RT_USING_OPENAMP
@@ -51,7 +68,7 @@ menu "Onboard Peripheral Drivers"
if BSP_USING_SD_CARD
config SD_USING_DFS
bool "sd card fatfs"
default n
default y
endif
menuconfig BSP_USING_EMMC
@@ -65,12 +82,43 @@ menu "Onboard Peripheral Drivers"
endif
config BSP_USING_AUDIO
bool "Enable Audio Device (WM8994)"
select RT_USING_AUDIO
select BSP_USING_PMIC
select BSP_USING_I2C
select BSP_USING_I2C2
default n
bool "Enable Audio Device (WM8994)"
select RT_USING_AUDIO
select BSP_USING_PMIC
select BSP_USING_SDMMC
select BSP_USING_SD_CARD
select SD_USING_DFS
select BSP_USING_I2C
select BSP_USING_I2C2
default n
config BSP_USING_DCMI
bool "Enable CAMERA (ov5640)"
select BSP_USING_MFX
select BSP_USING_PMIC
select BSP_USING_I2C
select BSP_USING_I2C2
default n
config BSP_USING_MFX
bool "Enable Multi Function eXpander"
default n
menuconfig BSP_USING_RS485
bool "Enable RS485 "
default n
if BSP_USING_RS485
comment "set rts pin number "
config BSP_RS485_RTS_PIN
int "RS485 rts pin number"
range 1 176
default 5
config RS485_UART_DEVICE_NAME
string "the uart name for rs485"
default "uart3"
endif
endmenu
@@ -80,6 +128,28 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_WWDG
bool "Enable WWDG"
select RT_USING_WWDG
select RT_USING_WDT
default n
config BSP_USING_QSPI
bool "Enable QSPI BUS"
select RT_USING_QSPI
select RT_USING_SPI
default n
config BSP_USING_SPDIFRX
bool "Enable spdifrx"
select BSP_USING_AUDIO
default n
config BSP_USING_DFSDM
bool "Enable dfsdm"
select BSP_USING_AUDIO
default n
menuconfig BSP_USING_UART
bool "Enable UART"
select RT_USING_SERIAL
@@ -133,6 +203,16 @@ menu "On-chip Peripheral Drivers"
default n
endif
menuconfig BSP_USING_LPTIM
bool "Enable lptimer"
default n
select RT_USING_LPTIMER
if BSP_USING_LPTIM
config BSP_USING_LPTIM1
bool "Enable LPTIM1"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable pwm"
default n
@@ -224,22 +304,21 @@ menu "On-chip Peripheral Drivers"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI5
bool "Enable SPI5 BUS"
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI5_TX_USING_DMA
bool "Enable SPI5 TX DMA"
depends on BSP_USING_SPI5
default n
config BSP_SPI5_RX_USING_DMA
bool "Enable SPI5 RX DMA"
depends on BSP_USING_SPI5
select BSP_SPI5_TX_USING_DMA
default n
endif
menuconfig BSP_USING_FDCAN
bool "Enable FDCAN"
default n
if BSP_USING_FDCAN
config BSP_USING_FDCAN1
bool "Enable FDCAN1"
default n
endif
source "../libraries/HAL_Drivers/Kconfig"
endmenu
@@ -13,6 +13,9 @@ CubeMX_Config/Common/System/system_stm32mp1xx.c
CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
''')
if GetDepend(['BSP_USING_SPI1']):
src += Glob('ports/spi_sample.c')
if GetDepend(['BSP_USING_PMIC']):
src += Glob('ports/drv_pmic.c')
@@ -32,6 +35,47 @@ if GetDepend(['BSP_USING_AUDIO']):
src += Glob('ports/drv_wm8994.c')
src += Glob('ports/drv_sound.c')
if GetDepend(['BSP_USING_DCMI']):
src += Glob('ports/drv_dcmi.c')
src += Glob('ports/drv_ov5640.c')
if GetDepend(['BSP_USING_MFX']):
src += Glob('ports/drv_mfx.c')
src += Glob('ports/mfxstm32l152.c')
if GetDepend(['BSP_USING_FDCAN']):
src += Glob('ports/drv_fdcan.c')
if GetDepend(['BSP_USING_QSPI']):
src += Glob('ports/drv_qspi_flash.c')
if GetDepend(['BSP_USING_SPDIFRX']):
src += Glob('ports/drv_spdifrx.c')
if GetDepend(['BSP_USING_DFSDM']):
src += Glob('ports/drv_dfsdm.c')
if GetDepend(['BSP_USING_WWDG']):
src += Glob('ports/drv_wwdg.c')
if GetDepend(['BSP_USING_EXTI']):
src += Glob('ports/drv_exti.c')
if GetDepend(['BSP_USING_RNG']) or GetDepend(['BSP_USING_HASH']) or GetDepend(['BSP_USING_CRC']) or GetDepend(['BSP_USING_CRYP']):
src += Glob('ports/crypto_sample.c')
if GetDepend(['BSP_USING_PWR']):
src += Glob('ports/drv_pwr.c')
if GetDepend(['BSP_USING_LPTIM1']):
src += Glob('ports/drv_lptim.c')
if GetDepend(['BSP_USING_RS485']):
src += Glob('ports/drv_rs485.c')
if GetDepend(['BSP_USING_TIM14']):
src += Glob('ports/timer_sample.c')
if GetDepend(['BSP_USING_OPENAMP']):
src += Glob('CubeMX_Config/CM4/Src/ipcc.c')
src += Glob('CubeMX_Config/CM4/Src/openamp.c')
+1 -6
View File
@@ -23,14 +23,9 @@ extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000)
#if defined(BSP_USING_OPENAMP)
#define STM32_FLASH_SIZE (64 * 1024)
#else
#define STM32_FLASH_SIZE (256 * 1024)
#endif
#define STM32_FLASH_SIZE (191 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(BSP_USING_OPENAMP)
#define STM32_SRAM_BEGIN (uint32_t)0x10030000
#else
File diff suppressed because it is too large. Load diff
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,22 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-27 thread-liu first version
*/
#ifndef __DRV_DCMI_H__
#define __DRV_DCMI_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-07 thread-liu first version
*/
#ifndef __DRV_DFSDM_H__
#define __DRV_DFSDM_H__
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SaturaLH(N, L, H) (((N)<(L))?(L):(((N)>(H))?(H):(N)))
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,36 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-27 thread-liu first version
*/
#include "board.h"
#ifdef BSP_USING_EXTI
//#define DRV_DEBUG
#define LOG_TAG "drv.exti"
#include <drv_log.h>
/* defined the KEY2 pin: */
#define KEY2_PIN GET_PIN(A, 13)
void key2_on(void *args)
{
rt_kprintf("press key2!\n");
}
static int exti_sample(void)
{
rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL);
rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE);
return RT_EOK;
}
INIT_DEVICE_EXPORT(exti_sample);
#endif
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,22 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-06 thread-liu first version
*/
#ifndef __DRV_FDCAN_H__
#define __DRV_FDCAN_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,163 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-19 thread-liu first version
*/
#include <board.h>
#ifdef BSP_USING_LPTIM
#include "drv_config.h"
#include <string.h>
#include <stdlib.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.lptimer"
#include <drv_log.h>
#define LED5_PIN GET_PIN(D, 9)
LPTIM_HandleTypeDef hlptim1;
extern int lptim_stop(void);
void LPTIM1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_LPTIM_IRQHandler(&hlptim1);
/* leave interrupt */
rt_interrupt_leave();
}
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
if(hlptim->Instance == LPTIM1)
{
HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9);
}
#if defined(BSP_USING_PWR)
/* All level of ITs can interrupt */
__set_BASEPRI(0U);
lptim_stop();
rt_kprintf("system returns to normal!\n");
#endif
}
static int lptim_control(uint8_t pre_value)
{
if(pre_value > 7)
{
pre_value = 7;
}
hlptim1.Instance->CFGR &= ~(7 << 9); /* clear PRESC[2:0] */
hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0] */
rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value);
return RT_EOK;
}
int lptim_start(void)
{
/* ### Start counting in interrupt mode ############################# */
if (HAL_LPTIM_Counter_Start_IT(&hlptim1, 32767) != HAL_OK)
{
LOG_D("lptim1 start counting failed!\n");
return -RT_ERROR;
}
LOG_D("lptim1 start counting success!\n");
return RT_EOK;
}
int lptim_stop(void)
{
if (HAL_LPTIM_Counter_Stop_IT(&hlptim1) != HAL_OK)
{
LOG_D("lptim1 stop failed!\n");
return -RT_ERROR;
}
LOG_D("lptim1 stop counting success!\n");
return RT_EOK;
}
int lptim_init(void)
{
rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT);
hlptim1.Instance = LPTIM1;
hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8;
hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;
hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;
hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
{
LOG_D("lptim init failed!\n");
return -RT_ERROR;
}
LOG_D("lptim init success!\n");
return RT_EOK;
}
INIT_DEVICE_EXPORT(lptim_init);
static int lptim_sample(int argc, char *argv[])
{
if (argc > 1)
{
if (!strcmp(argv[1], "start"))
{
lptim_start();
return RT_EOK;
}
else if (!strcmp(argv[1], "stop"))
{
lptim_stop();
return RT_EOK;
}
else if (!strcmp(argv[1], "set"))
{
if (argc > 2)
{
lptim_control(atoi(argv[2]));
return RT_EOK;
}
else
{
goto _exit;
}
}
else
{
goto _exit;
}
}
_exit:
{
rt_kprintf("Usage:\n");
rt_kprintf("lptim_sample start - start lptim, the LED5 will start blink\n");
rt_kprintf("lptim_sample stop - stop lptim, the LED5 will stop blink\n");
rt_kprintf("lptim_sample set - set the lptim prescaler to change LED5 blink frquency, lptim_sample set [0 - 7]\n");
}
return -RT_ERROR;
}
MSH_CMD_EXPORT(lptim_sample, low power timer sample);
#endif
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,45 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-08 thread-liu first version
*/
#ifndef __DRV_MFX_H__
#define __DRV_MFX_H__
#include "board.h"
#include "mfxstm32l152.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum
{
BSP_IO_PIN_RESET = 0,
BSP_IO_PIN_SET = 1
}BSP_IO_PinStateTypeDef;
#define CAMERA_RST1 MFXSTM32L152_AGPIO_PIN_3
#define CAMERA_XSDN MFXSTM32L152_AGPIO_PIN_2
#define CARMERA_PLUG MFXSTM32L152_GPIO_PIN_12
void rt_mfx_init(void);
rt_uint32_t BSP_IO_ITGetStatus(rt_uint32_t IoPin);
void BSP_IO_ITClear(void);
void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear);
rt_uint8_t rt_mfx_pin_mode(rt_uint32_t IoPin, IO_ModeTypedef IoMode);
rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOutPinType);
void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState);
rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin);
void rt_mfx_pin_toggle(rt_uint32_t IoPin);
#ifdef __cplusplus
}
#endif
#endif
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@@ -798,47 +798,47 @@ static rt_err_t rt_hw_pmic_init_register(void)
stpmu1_write_reg(BUCK_ICC_TURNOFF_REG, 0x30);
stpmu1_write_reg(LDO_ICC_TURNOFF_REG, 0x3b);
/* vddcore */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200);
STPMU1_Regulator_Enable(STPMU1_BUCK1);
/* vddcore */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200);
STPMU1_Regulator_Enable(STPMU1_BUCK1);
/* vddddr */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350);
STPMU1_Regulator_Enable(STPMU1_BUCK2);
/* vddddr */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350);
STPMU1_Regulator_Enable(STPMU1_BUCK2);
/* vdd */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300);
STPMU1_Regulator_Enable(STPMU1_BUCK3);
/* vdd */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300);
STPMU1_Regulator_Enable(STPMU1_BUCK3);
/* 3v3 */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300);
STPMU1_Regulator_Enable(STPMU1_BUCK4);
/* 3v3 */
STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300);
STPMU1_Regulator_Enable(STPMU1_BUCK4);
/* vdda */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900);
STPMU1_Regulator_Enable(STPMU1_LDO1);
/* vdda */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900);
STPMU1_Regulator_Enable(STPMU1_LDO1);
/* 2v8 */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800);
STPMU1_Regulator_Enable(STPMU1_LDO2);
/* 2v8 */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800);
STPMU1_Regulator_Enable(STPMU1_LDO2);
/* vtt_ddr lod3 mode buck2/2 */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF);
STPMU1_Regulator_Enable(STPMU1_LDO3);
/* vtt_ddr lod3 mode buck2/2 */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF);
STPMU1_Regulator_Enable(STPMU1_LDO3);
/* vdd_usb */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300);
STPMU1_Regulator_Enable(STPMU1_LDO4);
/* vdd_usb */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300);
STPMU1_Regulator_Enable(STPMU1_LDO4);
/* vdd_sd */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900);
STPMU1_Regulator_Enable(STPMU1_LDO5);
/* vdd_sd */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900);
STPMU1_Regulator_Enable(STPMU1_LDO5);
/* 1v8 */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800);
STPMU1_Regulator_Enable(STPMU1_LDO6);
/* 1v8 */
STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800);
STPMU1_Regulator_Enable(STPMU1_LDO6);
STPMU1_Regulator_Enable(STPMU1_VREFDDR);
STPMU1_Regulator_Enable(STPMU1_VREFDDR);
return RT_EOK;
}
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,180 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-07 thread-liu first version
*/
#include <board.h>
#include <drv_qspi.h>
#include <rtdevice.h>
#include <rthw.h>
#include <finsh.h>
#ifdef BSP_USING_QSPI_FLASH
#include "spi_flash.h"
#include "spi_flash_sfud.h"
/**
* @brief QSPI MSP Initialization
* This function configures the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hqspi->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspInit 0 */
if (IS_ENGINEERING_BOOT_MODE())
{
PeriphClkInit.Sdmmc12ClockSelection = RCC_QSPICLKSOURCE_ACLK;
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_QSPI;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE END QUADSPI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**QUADSPI GPIO Configuration
PF6 ------> QUADSPI_BK1_IO3
PF7 ------> QUADSPI_BK1_IO2
PF8 ------> QUADSPI_BK1_IO0
PF9 ------> QUADSPI_BK1_IO1
PF10 ------> QUADSPI_CLK
PB6 ------> QUADSPI_BK1_NCS
*/
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
/**QUADSPI GPIO Configuration
PC0 ------> QUADSPI_BK2_NCS
PH3 ------> QUADSPI_BK2_IO1
PG7 ------> QUADSPI_BK2_IO3
PG10 ------> QUADSPI_BK2_IO2
PH2 ------> QUADSPI_BK2_IO0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
GPIO_InitStruct.Alternate = GPIO_AF11_QUADSPI;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/* USER CODE BEGIN QUADSPI_MspInit 1 */
/* USER CODE END QUADSPI_MspInit 1 */
}
}
/**
* @brief QSPI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
{
if(hqspi->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspDeInit 0 */
/* USER CODE END QUADSPI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_QSPI_CLK_DISABLE();
/**QUADSPI GPIO Configuration
PC0 ------> QUADSPI_BK2_NCS
PF10 ------> QUADSPI_CLK
PB6 ------> QUADSPI_BK1_NCS
PH3 ------> QUADSPI_BK2_IO1
PG7 ------> QUADSPI_BK2_IO3
PG10 ------> QUADSPI_BK2_IO2
PF7 ------> QUADSPI_BK1_IO2
PF6 ------> QUADSPI_BK1_IO3
PH2 ------> QUADSPI_BK2_IO0
PF8 ------> QUADSPI_BK1_IO0
PF9 ------> QUADSPI_BK1_IO1
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3|GPIO_PIN_2);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_10);
/* USER CODE BEGIN QUADSPI_MspDeInit 1 */
/* USER CODE END QUADSPI_MspDeInit 1 */
}
}
static int rt_hw_qspi_flash_with_sfud_init(void)
{
stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, RT_NULL, RT_NULL);
/* init MX25L51245G */
if (RT_NULL == rt_sfud_flash_probe("MX25L51245G", "qspi10"))
{
return -RT_ERROR;
}
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_qspi_flash_with_sfud_init);
#endif /* BSP_USING_QSPI_FLASH */
@@ -0,0 +1,111 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-10-24 thread-liu first version
*/
#include <board.h>
#include "drv_rs485.h"
#ifdef BSP_USING_RS485
#define RS485_OUT rt_pin_write(BSP_RS485_RTS_PIN, PIN_HIGH)
#define RS485_IN rt_pin_write(BSP_RS485_RTS_PIN, PIN_LOW)
static rt_device_t serial = {0};
static struct rt_semaphore rx_sem = {0};
/* uart send data callback function */
static rt_err_t rs485_output(rt_device_t dev, void * buffer)
{
return RT_EOK;
}
/* uart receive data callback function */
static rt_err_t rs485_input(rt_device_t dev, rt_size_t size)
{
rt_sem_release(&rx_sem);
return RT_EOK;
}
/* send string */
int rs485_send_data(char *tbuf, rt_uint16_t t_len)
{
/* change rs485 mode */
RS485_OUT;
/* send data */
rt_device_write(serial, 0, tbuf, t_len);
/* change rs485 mode */
RS485_IN;
return RT_EOK;
}
static void rs485_thread_entry(void *parameter)
{
char ch;
while (1)
{
/* A byte of data is read from a serial port, and if it is not read, it waits for the received semaphore */
while (rt_device_read(serial, -1, &ch, 1) != 1)
{
rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
}
/* The data read through the serial port output dislocation */
ch = ch + 1;
/* send char */
rs485_send_data(&ch, 1);
}
}
/* rs485 rts pin init */
static int rs485_init(void)
{
/* find uart device */
serial = rt_device_find(RS485_UART_DEVICE_NAME);
if (!serial)
{
rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME);
return RT_ERROR;
}
rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
/* set receive data callback function */
rt_device_set_rx_indicate(serial, rs485_input);
/* set the send completion callback function */
rt_device_set_tx_complete(serial, rs485_output);
rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT);
RS485_IN;
rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
/* create rs485 thread */
rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
return RT_ERROR;
}
return RT_EOK;
}
INIT_DEVICE_EXPORT(rs485_init);
#endif /* bsp_using_RS485 */
@@ -0,0 +1,25 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-10-24 thread-liu first version
*/
#ifndef __DRV_RS485_H__
#define __DRV_RS485_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RS485_SEND_MODE 0
#define RS485_RECV_MODE 1
#ifdef __cplusplus
}
#endif
#endif /* drv_rs485.h */
File diff suppressed because it is too large. Load diff
Whitespace-only changes.
@@ -0,0 +1,115 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-18 thread-liu the first version
*/
#include <board.h>
#if defined(BSP_USING_WWDG)
#include "drv_config.h"
#include <string.h>
#include <stdlib.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.wwg"
#include <drv_log.h>
#define LED5_PIN GET_PIN(A, 14)
static rt_uint8_t feed_flag = 0;
static WWDG_HandleTypeDef hwwdg1;
void WWDG1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_WWDG_IRQHandler(&hwwdg1);
/* leave interrupt */
rt_interrupt_leave();
}
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
{
if(hwwdg->Instance==WWDG1)
{
if (feed_flag)
{
HAL_WWDG_Refresh(&hwwdg1);
HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_14);
}
}
}
static void wwdg_init()
{
rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT);
hwwdg1.Instance = WWDG1;
hwwdg1.Init.Prescaler = WWDG_PRESCALER_8;
hwwdg1.Init.Window = 0X5F;
hwwdg1.Init.Counter = 0x7F;
hwwdg1.Init.EWIMode = WWDG_EWI_ENABLE;
if (HAL_WWDG_Init(&hwwdg1) != HAL_OK)
{
Error_Handler();
}
feed_flag = 1;
}
static void wwdg_control(uint8_t pre_value)
{
if(pre_value > 7)
{
pre_value = 7;
}
hwwdg1.Instance->CFR &= ~(7 << 11); /* clear WDGTB[2:0] */
hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */
}
static void wwdg_stop(void)
{
feed_flag = 0;
}
static int wwdg_sample(int argc, char *argv[])
{
if (argc > 1)
{
if (!strcmp(argv[1], "run"))
{
wwdg_init();
}
else if (!strcmp(argv[1], "set"))
{
if (argc > 2)
{
wwdg_control(atoi(argv[2]));
}
}
else if (!strcmp(argv[1], "stop"))
{
wwdg_stop();
}
}
else
{
rt_kprintf("Usage:\n");
rt_kprintf("wwdg_sample run - open wwdg, when feed wwdg in wwdg irq, the LD5 will blink\n");
rt_kprintf("wwdg_sample stop - stop to feed wwdg, system will reset\n");
rt_kprintf("wwdg_sample set - set the wwdg prescaler, wwdg_sample set [0 - 7]\n");
}
return RT_EOK;
}
MSH_CMD_EXPORT(wwdg_sample, window watch dog sample);
#endif
File diff suppressed because it is too large. Load diff
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,85 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-09-15 thread-liu first version
*/
#include "board.h"
#if defined(BSP_USING_SPI1)
#include <drv_spi.h>
#define SPI_NAME "spi1"
#define SPI_DEVICE_NAME "spi10"
static struct rt_spi_device *spi_dev = RT_NULL;
/* attach spi1 device */
static int rt_spi_device_init(void)
{
struct rt_spi_configuration cfg;
rt_hw_spi_device_attach(SPI_NAME, SPI_DEVICE_NAME, NULL, NULL);
cfg.data_width = 8;
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
cfg.max_hz = 1 *1000 *1000;
spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME);
if (RT_NULL == spi_dev)
{
rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
return RT_ERROR;
}
rt_spi_configure(spi_dev, &cfg);
return RT_EOK;
}
INIT_APP_EXPORT(rt_spi_device_init);
/* spi5 loopback mode test case */
static int spi_sample(int argc, char **argv)
{
rt_uint8_t t_buf[8], r_buf[8];
int i = 0;
static struct rt_spi_message msg1;
if (argc != 9)
{
rt_kprintf("Usage:\n");
rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
return -RT_ERROR;
}
for (i = 0; i < 8; i++)
{
t_buf[i] = atoi(argv[i+1]);
}
msg1.send_buf = &t_buf;
msg1.recv_buf = &r_buf;
msg1.length = sizeof(t_buf);
msg1.cs_take = 1;
msg1.cs_release = 0;
msg1.next = RT_NULL;
rt_spi_transfer_message(spi_dev, &msg1);
rt_kprintf("spi rbuf : ");
for (i = 0; i < sizeof(t_buf); i++)
{
rt_kprintf("%x ", r_buf[i]);
}
rt_kprintf("\nspi loopback mode test over!\n");
return RT_EOK;
}
MSH_CMD_EXPORT(spi_sample, spi loopback test);
#endif /* BSP_USING_SPI5 */
@@ -0,0 +1,160 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-27 thread-liu first version
*/
#include <board.h>
#if defined(BSP_USING_TIM14) && defined(BSP_USING_ADC2)
#include <rtthread.h>
#include <rtdevice.h>
#define HWTIMER_DEV_NAME "timer14"
#define HWADC_DEV_NAME "adc2"
#define REFER_VOLTAGE 330 /* voltage reference */
#define CONVERT_BITS (1 << 12) /* Conversion digit */
#define ADC_DEV_CHANNEL 6
static rt_adc_device_t adc_dev = RT_NULL;
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
rt_uint32_t value = 0 , vol = 0;
/* read adc value */
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d \n", value);
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
return 0;
}
static int hwtimer_stop(void)
{
rt_err_t ret = RT_EOK;
rt_device_t hw_dev = RT_NULL;
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
ret = rt_device_close(hw_dev);
if (ret != RT_EOK)
{
rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
/* close adc channel */
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
static int hwtimer_start(void)
{
rt_err_t ret = RT_EOK;
rt_hwtimerval_t timeout_s;
rt_device_t hw_dev = RT_NULL;
rt_hwtimer_mode_t mode;
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
/* find adc dev */
adc_dev = (rt_adc_device_t)rt_device_find(HWADC_DEV_NAME);
if (adc_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME);
return RT_ERROR;
}
/* Open the device in read/write mode */
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
/* Set the timeout callback function */
rt_device_set_rx_indicate(hw_dev, timeout_cb);
/* Set the mode to periodic timer */
mode = HWTIMER_MODE_PERIOD;
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
if (ret != RT_EOK)
{
rt_kprintf("set mode failed! ret is :%d\n", ret);
return ret;
}
timeout_s.sec = 5;
timeout_s.usec = 0;
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
{
rt_kprintf("set timeout value failed\n");
return RT_ERROR;
}
rt_thread_mdelay(3500);
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
/* enable adc channel */
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
static int tim_sample(int argc, char *argv[])
{
if (argc > 1)
{
if (!rt_strcmp(argv[1], "start"))
{
rt_kprintf("tim14 will start\n");
hwtimer_start();
return RT_EOK;
}
else if (!rt_strcmp(argv[1], "stop"))
{
hwtimer_stop();
rt_kprintf("stop tim14 success!\n");
return RT_EOK;
}
else
{
goto _exit;
}
}
_exit:
{
rt_kprintf("Usage:\n");
rt_kprintf("tim_sample start - start TIM14 \n");
rt_kprintf("tim_sample stop - stop TIM14 \n");
}
return RT_ERROR;
}
MSH_CMD_EXPORT(tim_sample, tim sample);
#endif
+1 -1
View File
@@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil':
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
EXEC_PATH = r'D:\software\Embedded Workbench 8.3'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')