完善ART-PI BSP

This commit is contained in:
Rbb666 committed 2021-09-27 17:42:30 +08:00
1 parent 173913b96e
commit 27a8ff8d19
26 files changed
+4129 -116

No files matched your search

+2 -2
View File
@@ -24,7 +24,7 @@ static struct rt_memheap system_heap;
#endif
/**
* @brief Perform the SDRAM exernal memory inialization sequence
* @brief
* @param hsdram: SDRAM handle
* @param Command: Pointer to SDRAM command structure
* @retval None
@@ -51,7 +51,7 @@ static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM
/* Insert 100 ms delay */
/* interrupt is not enable, just to delay some time. */
for (tmpmrd = 0; tmpmrd < 0xffffff; tmpmrd ++)
for (tmpmrd = 0; tmpmrd < 0xffff; tmpmrd ++)
;
/* Configure a PALL (precharge all) command */
+1 -1
View File
@@ -56,7 +56,7 @@ if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c']
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c']
if GetDepend(['BSP_USING_ETH']):
if GetDepend(['BSP_USING_ETH']) or GetDepend(['BSP_USING_ETH_H750']):
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c']
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c']
@@ -15,10 +15,20 @@
/* defined the LED0 pin: PI8 */
#define LED0_PIN GET_PIN(I, 8)
#ifdef RT_USING_WIFI
extern void wlan_autoconnect_init(void);
#endif
int main(void)
{
/* set LED0 pin mode to output */
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
#ifdef RT_USING_WIFI
/* init Wi-Fi auto connect feature */
wlan_autoconnect_init();
/* enable auto reconnect on WLAN device */
rt_wlan_config_autoreconnect(RT_TRUE);
#endif
while (1)
{
@@ -51,7 +51,7 @@ extern "C" {
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
File diff suppressed because it is too large. Load diff
File diff suppressed because it is too large. Load diff
File diff suppressed because it is too large. Load diff
+145 -1
View File
@@ -15,6 +15,51 @@ menu "Onboard Peripheral Drivers"
select BSP_USING_UART4
default n
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (spi1)"
select BSP_USING_SPI
select BSP_USING_SPI1
select PKG_USING_FAL
select FAL_USING_SFUD_PORT
select RT_USING_SFUD
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (w25q64 qspi)"
select BSP_USING_QSPI
select FAL_USING_SFUD_PORT
select RT_USING_SFUD
select RT_SFUD_USING_QSPI
default n
menuconfig BSP_USING_FS
bool "Enable filesystem"
select RT_USING_DFS
select RT_USING_DFS_ROMFS
default n
if BSP_USING_FS
config BSP_USING_SDCARD_FS
bool "Enable SDCARD filesystem"
select BSP_USING_SDIO_ARTPI
select BSP_USING_SDIO1
select RT_USING_DFS_ELMFAT
default n
config BSP_USING_SPI_FLASH_FS
bool "Enable SPI FLASH filesystem"
select BSP_USING_SPI_FLASH
select RT_USING_MTD_NOR
select PKG_USING_LITTLEFS
default n
endif
config BSP_USING_WIFI
bool "Enable wifi (AP6212)"
select ART_PI_USING_WIFI_6212_LIB
select BSP_USING_SPI_FLASH
select RT_USING_WIFI
select RT_USING_SAL
default n
endmenu
menu "On-chip Peripheral Drivers"
@@ -116,11 +161,110 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1"
default n
endif
config BSP_USING_QSPI
bool "Enable QSPI BUS"
select RT_USING_QSPI
select RT_USING_SPI
default n
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_LCD
bool "Enable LCD"
select BSP_USING_LTDC
select BSP_USING_GPIO
select BSP_USING_SDRAM
select RT_USING_MEMHEAP
default n
menuconfig BSP_USING_SDIO_ARTPI
bool "Enable SDIO"
default n
select RT_USING_SDIO
if BSP_USING_SDIO_ARTPI
config BSP_USING_SDIO1
bool "Enable SDIO1"
default n
config BSP_USING_SDIO2
bool "Enable SDIO2"
default n
endif
config BSP_USING_USBD
bool "Enable USB Device"
select RT_USING_USB_DEVICE
default n
menuconfig BSP_USING_USBH
bool "Enable USB Host"
select RT_USING_USB_HOST
default n
if BSP_USING_USBH
menuconfig RT_USBH_MSTORAGE
bool "Enable Udisk Drivers"
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
if RT_USBH_MSTORAGE
config UDISK_MOUNTPOINT
string "Udisk mount dir"
default "/"
endif
endif
menuconfig BSP_USING_ETH_H750
bool "Enable Ethernet"
default n
select RT_USING_LWIP
if BSP_USING_ETH_H750
config ETH_RESET_PIN
string "ETH RESET PIN"
default "PA.3"
endif
if BSP_USING_ETH_H750
choice
prompt "Choose ETH PHY"
default PHY_USING_LAN8720A
config PHY_USING_LAN8720A
bool "USING LAN8720A"
default n
endchoice
endif
config BSP_USING_LTDC
bool
default n
source "../libraries/HAL_Drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
menu "External Libraries"
config ART_PI_USING_WIFI_6212_LIB
bool "Using Wifi(AP6212) Library"
select PKG_USING_EASYFLASH
select BSP_USING_SDIO_ARTPI
select BSP_USING_SDIO2
select RT_USING_LWIP
select RT_USING_WIFI
default n
endmenu
@@ -1,20 +1,47 @@
import os
import rtconfig
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
# add the general drivers.
src = Glob('board.c')
src += Glob('CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c')
if GetDepend(['BSP_USING_QSPI_FLASH']):
src += Glob('ports/drv_qspi_flash.c')
src += Glob('port/drv_qspi_flash.c')
if GetDepend('BSP_USING_SPI_LCD'):
src = src + ['ports/drv_lcd.c']
if GetDepend(['BSP_USING_SPI_LCD_ILI9488']):
src += Glob('drv_spi_ili9488.c')
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('port/spi_flash_init.c')
if GetDepend(['BSP_USING_FS']):
src += Glob('port/filesystem.c')
if GetDepend(['BSP_USING_SDIO_ARTPI']):
src += Glob('port/drv_sdio.c')
if GetDepend(['BSP_USING_WIFI']):
src += Glob('port/wifi_config.c')
src += Glob('port/drv_wlan.c')
if GetDepend(['BSP_USING_ETH_H750']):
src += Glob('port/drv_eth.c')
if GetDepend(['PKG_USING_EASYFLASH']):
src += Glob('port/ef_fal_port.c')
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
path = [cwd]
path += [cwd + '/CubeMX_Config/Core/Inc']
path += [cwd + '/port']
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s']
@@ -22,7 +49,7 @@ elif rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s']
# STM32H743xx || STM32H750xx || STM32F753xx
# You can select chips from the list above
CPPDEFINES = ['STM32H750xx']
@@ -1,13 +1,15 @@
/*
* linker script for STM32F4xx with GNU ld
* bernard.xiong 2009-10-14
* linker script for STM32H750XBHx with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K DTCM */
ROM (rx) : ORIGIN =0x90000000,LENGTH =8192k
RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
RxDecripSection (rw) : ORIGIN =0x30040000,LENGTH =32k
TxDecripSection (rw) : ORIGIN =0x30040060,LENGTH =32k
RxArraySection (rw) : ORIGIN =0x30040200,LENGTH =32k
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
@@ -40,6 +42,25 @@ SECTIONS
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for at server */
. = ALIGN(4);
__rtatcmdtab_start = .;
KEEP(*(RtAtCmdTab))
__rtatcmdtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
@@ -81,6 +102,7 @@ SECTIONS
*(.data.*)
*(.gnu.linkonce.d*)
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
@@ -119,6 +141,33 @@ SECTIONS
} > RAM
__bss_end = .;
.RxDecripSection (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
*(.RxDecripSection)
*(.RxDecripSection.*)
. = ALIGN(4);
__RxDecripSection_free__ = .;
} > RxDecripSection
.TxDecripSection (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
*(.TxDecripSection)
*(.TxDecripSection.*)
. = ALIGN(4);
__TxDecripSection_free__ = .;
} > TxDecripSection
.RxArraySection (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
*(.RxArraySection)
*(.RxArraySection.*)
. = ALIGN(4);
__RxArraySection_free__ = .;
} > RxArraySection
_end = .;
/* Stabs debugging sections. */
@@ -0,0 +1,12 @@
import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,92 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-25 zylx first version
* 2020-07-18 wanghaijing add SPECIAL_MODES_REG
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
/* The PHY basic control register */
#define PHY_BASIC_CONTROL_REG 0x00U
#define PHY_RESET_MASK (1<<15)
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
/* The PHY basic status register */
#define PHY_BASIC_STATUS_REG 0x01U
#define PHY_LINKED_STATUS_MASK (1<<2)
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
/* The PHY ID one register */
#define PHY_ID1_REG 0x02U
/* The PHY ID two register */
#define PHY_ID2_REG 0x03U
/* The PHY SPECIAL MODES REGISTER */
#define PHY_SPECIAL_MODES_REG 0x12U
/* The PHY auto-negotiate advertise register */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
#define PHY_Status_REG 0x1FU
#define PHY_FULL_DUPLEX_MASK (1<<4)
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
#ifdef PHY_USING_LAN8720A
/* The PHY interrupt source flag register. */
#define PHY_INTERRUPT_FLAG_REG 0x1DU
/* The PHY interrupt mask register. */
#define PHY_INTERRUPT_MASK_REG 0x1EU
#define PHY_LINK_DOWN_MASK (1<<4)
#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
/* The PHY status register. */
#define PHY_Status_REG 0x1FU
#define PHY_10M_MASK (1<<2)
#define PHY_100M_MASK (1<<3)
#define PHY_FULL_DUPLEX_MASK (1<<4)
#endif /* PHY_USING_LAN8720A */
#ifdef PHY_USING_DM9161CEP
#define PHY_Status_REG 0x11U
#define PHY_10M_MASK ((1<<12) || (1<<13))
#define PHY_100M_MASK ((1<<14) || (1<<15))
#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
/* The PHY interrupt source flag register. */
#define PHY_INTERRUPT_FLAG_REG 0x15U
/* The PHY interrupt mask register. */
#define PHY_INTERRUPT_MASK_REG 0x15U
#define PHY_LINK_CHANGE_FLAG (1<<2)
#define PHY_LINK_CHANGE_MASK (1<<9)
#define PHY_INT_MASK 0
#endif /* PHY_USING_DM9161CEP */
#ifdef PHY_USING_DP83848C
#define PHY_Status_REG 0x10U
#define PHY_10M_MASK (1<<1)
#define PHY_FULL_DUPLEX_MASK (1<<2)
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
#define PHY_INTERRUPT_FLAG_REG 0x12U
#define PHY_LINK_CHANGE_FLAG (1<<13)
#define PHY_INTERRUPT_CTRL_REG 0x11U
#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK (1<<5)
#endif /* PHY_USING_DP83848C */
#endif /* __DRV_ETH_H__ */
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,112 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-05-23 liuduanfei first version
* 2020-08-25 wanghaijing add sdmmmc2
*/
#ifndef __DRV_SDIO_H__
#define __DRV_SDIO_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#include <string.h>
#include <drivers/mmcsd_core.h>
#include <drivers/sdio.h>
#define SDIO_BUFF_SIZE 4096
#define SDIO_ALIGN_LEN 32
#ifndef SDIO1_BASE_ADDRESS
#define SDIO1_BASE_ADDRESS (0x52007000)
#endif
#ifndef SDIO2_BASE_ADDRESS
#define SDIO2_BASE_ADDRESS (0x48022400)
#endif
#ifndef SDIO_CLOCK_FREQ
#define SDIO_CLOCK_FREQ (200U * 1000 * 1000)
#endif
#ifndef SDIO_BUFF_SIZE
#define SDIO_BUFF_SIZE (4096)
#endif
#ifndef SDIO_ALIGN_LEN
#define SDIO_ALIGN_LEN (32)
#endif
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (25 * 1000 * 1000)
#endif
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define SDIO_ERRORS \
(SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
#define SDIO_MASKR_ALL \
(SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU)
struct stm32_sdio
{
volatile rt_uint32_t power; /* offset 0x00 */
volatile rt_uint32_t clkcr; /* offset 0x04 */
volatile rt_uint32_t arg; /* offset 0x08 */
volatile rt_uint32_t cmd; /* offset 0x0C */
volatile rt_uint32_t respcmd; /* offset 0x10 */
volatile rt_uint32_t resp1; /* offset 0x14 */
volatile rt_uint32_t resp2; /* offset 0x18 */
volatile rt_uint32_t resp3; /* offset 0x1C */
volatile rt_uint32_t resp4; /* offset 0x20 */
volatile rt_uint32_t dtimer; /* offset 0x24 */
volatile rt_uint32_t dlen; /* offset 0x28 */
volatile rt_uint32_t dctrl; /* offset 0x2C */
volatile rt_uint32_t dcount; /* offset 0x30 */
volatile rt_uint32_t sta; /* offset 0x34 */
volatile rt_uint32_t icr; /* offset 0x38 */
volatile rt_uint32_t mask; /* offset 0x3C */
volatile rt_uint32_t acktimer; /* offset 0x40 */
volatile rt_uint32_t reserved0[3]; /* offset 0x44 ~ 0x4C */
volatile rt_uint32_t idmatrlr; /* offset 0x50 */
volatile rt_uint32_t idmabsizer; /* offset 0x54 */
volatile rt_uint32_t idmabase0r; /* offset 0x58 */
volatile rt_uint32_t idmabase1r; /* offset 0x5C */
volatile rt_uint32_t reserved1[8]; /* offset 0x60 ~ 7C */
volatile rt_uint32_t fifo; /* offset 0x80 */
};
typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
struct stm32_sdio_des
{
struct stm32_sdio *hw_sdio;
sdio_clk_get clk_get;
SD_HandleTypeDef hsd;
};
/* stm32 sdio dirver class */
struct stm32_sdio_class
{
struct stm32_sdio_des *des;
const struct stm32_sdio_config *cfg;
struct rt_mmcsd_host host;
};
extern void sdcard_change(void);
#endif /* __DRV_SDIO_H__ */
File diff suppressed because it is too large. Load diff
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,54 @@
/*
* File : fal_cfg.h
* This file is part of FAL (Flash Abstraction Layer) package
* COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2018-05-17 armink the first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtconfig.h>
#include <board.h>
#define NOR_FLASH_DEV_NAME "norflash0"
/* ===================== Flash device Configuration ========================= */
extern struct fal_flash_dev nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "wifi_image", NOR_FLASH_DEV_NAME, 0, 512*1024, 0}, \
{FAL_PART_MAGIC_WORD, "bt_image", NOR_FLASH_DEV_NAME, 512*1024, 512*1024, 0}, \
{FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 1024*1024, 2*1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 3*1024*1024, 1*1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
@@ -0,0 +1,180 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-13 balanceTWK add sdcard port file
* 2019-06-11 WillianChan Add SD card hot plug detection
*/
#include <rtthread.h>
#ifdef BSP_USING_FS
#if DFS_FILESYSTEMS_MAX < 4
#error "Please define DFS_FILESYSTEMS_MAX more than 4"
#endif
#if DFS_FILESYSTEM_TYPES_MAX < 4
#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4"
#endif
#include <dfs_fs.h>
#include "dfs_romfs.h"
#ifdef BSP_USING_SDCARD_FS
#include <board.h>
#include "drv_sdio.h"
#endif
#ifdef BSP_USING_SPI_FLASH_FS
#include "fal.h"
#endif
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
static const struct romfs_dirent _romfs_root[] =
{
{ROMFS_DIRENT_DIR, "flash", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}
};
const struct romfs_dirent romfs_root =
{
ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])
};
#ifdef BSP_USING_SDCARD_FS
/* SD Card hot plug detection pin */
#define SD_CHECK_PIN GET_PIN(D, 5)
static void _sdcard_mount(void)
{
rt_device_t device;
device = rt_device_find("sd0");
if (device == NULL)
{
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
device = rt_device_find("sd0");
}
if (device != RT_NULL)
{
if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/sdcard'");
}
else
{
LOG_W("sd card mount to '/sdcard' failed!");
}
}
}
static void _sdcard_unmount(void)
{
rt_thread_mdelay(200);
dfs_unmount("/sdcard");
LOG_I("Unmount \"/sdcard\"");
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
}
static void sd_mount(void *parameter)
{
rt_uint8_t re_sd_check_pin = 1;
rt_thread_mdelay(200);
if (rt_pin_read(SD_CHECK_PIN))
{
_sdcard_mount();
}
while (1)
{
rt_thread_mdelay(200);
if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0)
{
_sdcard_mount();
}
if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) == 0)
{
_sdcard_unmount();
}
}
}
#endif /* BSP_USING_SDCARD_FS */
int mount_init(void)
{
if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0)
{
LOG_E("rom mount to '/' failed!");
}
#ifdef BSP_USING_SPI_FLASH_FS
struct rt_device *flash_dev = RT_NULL;
#ifndef RT_USING_WIFI
fal_init();
#endif
flash_dev = fal_mtd_nor_device_create("filesystem");
if (flash_dev)
{
//mount filesystem
if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) != 0)
{
LOG_W("mount to '/flash' failed! try to mkfs %s", flash_dev->parent.name);
dfs_mkfs("lfs", flash_dev->parent.name);
if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) == 0)
{
LOG_I("mount to '/flash' success!");
}
}
else
{
LOG_I("mount to '/flash' success!");
}
}
else
{
LOG_E("Can't create block device filesystem or bt_image partition.");
}
#endif
#ifdef BSP_USING_SDCARD_FS
rt_thread_t tid;
rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
}
#endif
return RT_EOK;
}
INIT_APP_EXPORT(mount_init);
#endif /* BSP_USING_FS */
@@ -0,0 +1,35 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-01-08 zylx first version
*/
#ifndef __LCD_PORT_H__
#define __LCD_PORT_H__
/* atk 4.3 inch screen, 800 * 480 */
#define LCD_WIDTH 800
#define LCD_HEIGHT 480
#define LCD_BITS_PER_PIXEL 16
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
#define LCD_HSYNC_WIDTH 1
#define LCD_VSYNC_HEIGHT 1
#define LCD_HBP 40
#define LCD_VBP 32
#define LCD_HFP 48
#define LCD_VFP 13
#define LCD_BACKLIGHT_USING_GPIO
#define LCD_BL_GPIO_NUM GET_PIN(D, 4)
#define LCD_DISP_GPIO_NUM GET_PIN(B, 5)
/* atk 4.3 inch screen, 800 * 480 */
#endif /* __LCD_PORT_H__ */
@@ -0,0 +1,39 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-10 zylx first version
*/
#ifndef __LCD_PORT_H__
#define __LCD_PORT_H__
/* rt-thread 3.5 inch screen, 320 * 480 */
#define LCD_HOR_SCREEN
#define LCD_FULL_COLOR BLACK
#ifndef LCD_FULL_COLOR
#define LCD_FULL_COLOR WHITE
#endif
#ifndef LCD_HOR_SCREEN
#define LCD_WIDTH 320
#define LCD_HEIGHT 480
#else
#define LCD_WIDTH 480
#define LCD_HEIGHT 320
#endif
#define LCD_BITS_PER_PIXEL 24
#define LCD_BYTES_PER_PIXEL (LCD_BITS_PER_PIXEL / 8)
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BYTES_PER_PIXEL)
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB888
#define LCD_BACKLIGHT_USING_GPIO
#define LCD_BL_PIN GET_PIN(C, 6)
#define LCD_RES_PIN GET_PIN(A, 3)
/* rt-thread 3.5 inch screen, 320 * 480 */
#endif /* __LCD_PORT_H__ */
@@ -0,0 +1,65 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-04 zylx The first version for STM32F4xx
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 16
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 9
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 13
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 2
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 0
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_COUNT ((uint32_t)0x02A5)
#define SDRAM_SIZE ((uint32_t)0x2000000)
/* Timing configuration for W9825G6KH-6 */
/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 8x10ns */
#define EXITSELFREFRESHDELAY 8
/* TRAS: 5x10ns */
#define SELFREFRESHTIME 6
/* TRC: 7x10ns */
#define ROWCYCLEDELAY 6
/* TWR: 2 Clock cycles */
#define WRITERECOVERYTIME 2
/* TRP: 2x10ns */
#define RPDELAY 2
/* TRCD: 2x10ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif
@@ -0,0 +1,30 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-07 wanghaijing the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <spi_flash.h>
#include <drv_spi.h>
static int rt_flash_init(void)
{
extern rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const char *spi_dev_name);
extern int fal_init(void);
rt_hw_spi_device_attach("spi1", "spi10", GPIOA, GPIO_PIN_4);
/* initialize SPI Flash device */
rt_sfud_flash_probe("norflash0", "spi10");
fal_init();
return 0;
}
INIT_ENV_EXPORT(rt_flash_init);
File diff suppressed because it is too large. Load diff
@@ -0,0 +1,20 @@
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
LIBS = []
LIBPATH = []
src = []
LIBPATH = [cwd]
if rtconfig.CROSS_TOOL == 'gcc':
LIBS += ['wifi_6212_armcm7_2.1.2_gcc']
elif rtconfig.CROSS_TOOL == 'keil':
LIBS += ['libwifi_6212_armcm7_2.1.2_armcc']
path = [cwd]
group = DefineGroup('WICED', src, depend = ['ART_PI_USING_WIFI_6212_LIB'], CPPPATH = path, LIBS = LIBS, LIBPATH = LIBPATH)
Return('group')