Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-08-21 17:24:33 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

[bsp][nxp]:keep imxrt1180 mini bsp#11629

Browse Source
This commit is contained in:
CYFS
2026-07-20 17:34:08 +08:00
committed by GitHub
parent 25212f3745
commit 1fa451feea
8 changed files with 740 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
+8 -11
View File
@@ -242,14 +242,14 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V2=y
# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_SERIAL_USING_DMA is not set
# CONFIG_RT_USING_SERIAL_BYPASS is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_CLOCK_TIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_PHY_V2 is not set
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
@@ -274,7 +274,6 @@ CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_BLK is not set
# CONFIG_RT_USING_REGULATOR is not set
# CONFIG_RT_USING_POWER_SUPPLY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_CHERRYUSB is not set
# end of Device Drivers
@@ -1467,23 +1466,21 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_DMA=y
CONFIG_BSP_USING_LPADC=y
CONFIG_BSP_USING_LPADC1=y
CONFIG_BSP_LPADC1_USING_DMA=y
# CONFIG_BSP_USING_DMA is not set
# CONFIG_BSP_USING_LPADC is not set
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_USB is not set
# CONFIG_BSP_USING_SDIO is not set
CONFIG_BSP_USING_LPUART=y
CONFIG_BSP_USING_LPUART1=y
CONFIG_BSP_LPUART1_RX_USING_DMA=y
CONFIG_BSP_LPUART1_RX_DMA_CHANNEL=0
CONFIG_BSP_LPUART1_TX_USING_DMA=y
CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1
# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_LPUART10 is not set
# CONFIG_BSP_USING_LPUART12 is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_CLOCK_TIMER is not set
# CONFIG_BSP_USING_FLEXSPI is not set
# end of On-chip Peripheral Drivers
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/peripherals.c
+526
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/peripherals.h
+100
View File
@@ -0,0 +1,100 @@
/*
* Copyright 2026 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PERIPHERALS_H_
#define _PERIPHERALS_H_
/***********************************************************************************************************************
* Included files
**********************************************************************************************************************/
#include "fsl_edma.h"
#include <stdlib.h>
#include "fsl_memory.h"
#include "fsl_common.h"
#include "fsl_lpuart.h"
#include "fsl_clock.h"
#include "fsl_rgpio.h"
#include "fsl_lpadc.h"
#include "rtconfig.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/* Definitions for BOARD_InitPeripherals functional group */
/* Used DMA device. */
#define DMA4_DMA_BASEADDR (EDMA_Type *)DMA4
/* Channel CH0 definitions */
/* DMA4 eDMA source request. */
#define DMA4_CH0_DMA_REQUEST kDma4RequestMuxADC1Request0
/* Selected eDMA channel number. */
#define DMA4_CH0_DMA_CHANNEL 0
/* TCD pool size */
#define DMA4_CH0_TCD_SIZE 1
/* DMA4 interrupt vector ID (number). */
#define DMA4_DMA_CH_INT_DONE_0_IRQN DMA4_CH0_CH1_CH32_CH33_IRQn
/* Transfer structure index 0 definition */
#define DMA4_CH0_TRANSFER0_CONFIG DMA4_CH0_Transfers_config[0]
/* Definition of peripheral ID */
#define LPUART1_PERIPHERAL LPUART1
/* Definition of the clock source frequency */
#define LPUART1_CLOCK_SOURCE 24000000UL
/* Alias for ADC1 peripheral */
#define ADC1_PERIPHERAL ADC1
/* Command 1 - GRPA */
#define ADC1_GRPA 1U
/* Command 2 - GRPB */
#define ADC1_GRPB 2U
/* Trigger 0 - TRIG */
#define ADC1_TRIG 0U
/***********************************************************************************************************************
* Global variables
**********************************************************************************************************************/
#ifdef BSP_LPADC1_USING_DMA
extern edma_config_t DMA4_config;
/* Destination address extern definition */
extern AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[], sizeof(uint32_t));
extern edma_handle_t DMA4_CH0_Handle;
/* Transactional transfer configurations */
extern edma_transfer_config_t DMA4_CH0_Transfers_config[1];
#endif
extern const lpuart_config_t LPUART1_config;
extern const lpadc_config_t ADC1_config;
extern lpadc_conv_command_config_t ADC1_commandsConfig[2];
extern lpadc_conv_trigger_config_t ADC1_triggersConfig[1];
#ifdef BSP_LPADC1_USING_DMA
/***********************************************************************************************************************
* Callback functions
**********************************************************************************************************************/
/* eDMA callback function for the 0 channel.*/
extern void DMA_Callback(edma_handle_t *, void *, bool, uint32_t);
#endif
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void);
/***********************************************************************************************************************
* BOARD_InitBootPeripherals function
**********************************************************************************************************************/
void BOARD_InitBootPeripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* _PERIPHERALS_H_ */
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c
+78 -74
View File
@@ -31,7 +31,8 @@ processor_version: 0.15.9
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
@@ -53,90 +54,93 @@ BOARD_InitPins:
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
void BOARD_InitPins(void)
{
CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_08_LPUART1_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_09_LPUART1_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_08_LPUART1_TX,
0x02U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_09_LPUART1_RX,
0x02U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_08_LPUART1_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_09_LPUART1_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_08_LPUART1_TX,
0x02U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_09_LPUART1_RX,
0x02U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_32_LPUART10_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_33_LPUART10_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_32_LPUART10_TX,
0x02U);
IOMUXC_GPIO_AD_33_LPUART10_RX,
0x02U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_32_LPUART10_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_33_LPUART10_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_32_LPUART10_TX,
0x02U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_33_LPUART10_RX,
0x02U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_19_LPUART12_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_20_LPUART12_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_19_LPUART12_TX,
0x02U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_20_LPUART12_RX,
0x02U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_19_LPUART12_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_20_LPUART12_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_19_LPUART12_TX,
0x02U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_20_LPUART12_RX,
0x02U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_16_LPI2C2_SCL,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_15_LPI2C2_SDA,
1U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_16_LPI2C2_SCL,
0x1DU);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_15_LPI2C2_SDA,
0x1DU);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_16_LPI2C2_SCL,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AON_15_LPI2C2_SDA,
1U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_16_LPI2C2_SCL,
0x1DU);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AON_15_LPI2C2_SDA,
0x1DU);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_18_LPI2C3_SCL,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_19_LPI2C3_SDA,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_18_LPI2C3_SCL,
0x1DU);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_19_LPI2C3_SDA,
0x1DU);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_18_LPI2C3_SCL,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_19_LPI2C3_SDA,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_18_LPI2C3_SCL,
0x1DU);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_19_LPI2C3_SDA,
0x1DU);
}
void BOARD_InitLeds(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
void BOARD_InitLeds(void)
{
CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
/* GPIO configuration on GPIO_AD_27 (pin M16) */
rgpio_pin_config_t gpio4_pinM16_config = {
.pinDirection = kRGPIO_DigitalOutput,
.outputLogic = 1U,
};
rgpio_pin_config_t gpio4_pinM16_config = {
.pinDirection = kRGPIO_DigitalOutput,
.outputLogic = 1U,
};
/* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */
RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config);
RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */
0U);
}
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript
+1
View File
@@ -19,6 +19,7 @@ else:
board.c
MCUX_Config/clock_config.c
MCUX_Config/pin_mux.c
MCUX_Config/peripherals.c
""")
if GetDepend(['BSP_USING_QSPI_FLASH_FS']):
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
+10 -20
View File
@@ -61,12 +61,12 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_CPUS_NR 1
#define RT_NAME_MAX 12
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
@@ -101,10 +101,10 @@
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_VER_NUM 0x50300
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
@@ -122,12 +122,12 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 4096
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
@@ -149,8 +149,6 @@
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V2
#define RT_SERIAL_BUF_STRATEGY_OVERWRITE
#define RT_SERIAL_USING_DMA
#define RT_USING_ADC
#define RT_USING_PIN
/* end of Device Drivers */
@@ -162,8 +160,8 @@
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
@@ -428,17 +426,9 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_DMA
#define BSP_USING_LPADC
#define BSP_USING_LPADC1
#define BSP_LPADC1_USING_DMA
#define BSP_USING_GPIO
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
#define BSP_LPUART1_RX_USING_DMA
#define BSP_LPUART1_RX_DMA_CHANNEL 0
#define BSP_LPUART1_TX_USING_DMA
#define BSP_LPUART1_TX_DMA_CHANNEL 1
/* end of On-chip Peripheral Drivers */
/* Onboard Peripheral Drivers */
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config
+6 -7
View File
@@ -244,11 +244,11 @@ CONFIG_RT_USING_SERIAL_V1=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_SERIAL_BYPASS is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_CLOCK_TIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_PHY_V2 is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
@@ -1467,8 +1467,8 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM7=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_DMA=y
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_DMA is not set
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_USB is not set
# CONFIG_BSP_USING_SDIO is not set
@@ -1477,16 +1477,15 @@ CONFIG_BSP_USING_LPUART1=y
# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_LPUART3 is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_CAN is not set
CONFIG_BSP_USING_FLEXSPI=y
CONFIG_BSP_USING_FLEXSPI1=y
# CONFIG_BSP_USING_FLEXSPI2 is not set
# CONFIG_BSP_USING_FLEXSPI is not set
# CONFIG_BSP_USING_CLOCK_TIMER is not set
# end of On-chip Peripheral Drivers
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_OSPI_FLASH=y
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_FS is not set
bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h
+11 -14
View File
@@ -61,12 +61,12 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_CPUS_NR 1
#define RT_NAME_MAX 12
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
@@ -100,10 +100,10 @@
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_VER_NUM 0x50300
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
@@ -121,12 +121,12 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 4096
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
@@ -159,8 +159,8 @@
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
@@ -425,16 +425,13 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
#define BSP_USING_FLEXSPI
#define BSP_USING_FLEXSPI1
/* end of On-chip Peripheral Drivers */
/* Onboard Peripheral Drivers */
#define BSP_USING_OSPI_FLASH
/* end of Onboard Peripheral Drivers */
/* Board extended module Drivers */