Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-02-06 17:12:01 +08:00
Code Issues Actions 5 Packages Projects Releases Wiki Activity

[bsp][driver][renesas] Unified Renesas SCI driver

Browse Source
This commit is contained in:
Yuqiang Wang
2024-04-15 17:13:10 +08:00
committed by Rbb666
parent 4909b87881
commit 1bb06ab6dc
136 changed files with 5083 additions and 11031 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
bsp/renesas/ebf_qi_min_6m5/.config
View File

@@ -278,16 +278,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CYW43012 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43012 is not set
#
# BL808 WiFi
#
# CONFIG_PKG_USING_WLAN_BL808 is not set
#
# CYW43439 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43439 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
@@ -309,6 +299,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -330,7 +321,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_BT_CYW43012 is not set
# CONFIG_PKG_USING_CYW43XX is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
@@ -351,7 +341,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
# CONFIG_PKG_USING_LHC_MODBUS is not set
#
# security packages
@@ -496,9 +485,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_CORE is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
# CONFIG_PKG_USING_CMSIS_NN is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
@@ -518,8 +504,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FILEX is not set
# CONFIG_PKG_USING_LEVELX is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@@ -557,35 +541,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_SFDB is not set
# CONFIG_PKG_USING_RTP is not set
# CONFIG_PKG_USING_REB is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
#
# peripheral libraries and drivers
#
#
# HAL & SDK Drivers
#
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
#
# sensors drivers
#
@@ -667,8 +627,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_CST812T is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@@ -676,6 +637,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -690,6 +659,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
@@ -712,6 +682,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
@@ -721,6 +692,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -728,6 +700,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
@@ -736,9 +709,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ST7789 is not set
# CONFIG_PKG_USING_VS1003 is not set
# CONFIG_PKG_USING_X9555 is not set
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
@@ -753,7 +723,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
#
# Signal Processing and Control Algorithm Packages
@@ -763,6 +732,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
#
# miscellaneous packages
@@ -838,9 +808,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@@ -848,13 +816,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -899,7 +867,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -938,6 +906,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -960,7 +929,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -968,7 +937,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -981,7 +950,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
#
# Display
@@ -1007,7 +975,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
#
# Data Storage
@@ -1024,11 +991,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
@@ -1051,6 +1018,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# Uncategorized
#
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
CONFIG_SOC_FAMILY_RENESAS=y
# CONFIG_SOC_SERIES_R7FA6M3 is not set
# CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1058,6 +1026,7 @@ CONFIG_SOC_FAMILY_RENESAS=y
CONFIG_SOC_SERIES_R7FA6M5=y
# CONFIG_SOC_SERIES_R7FA4M2 is not set
# CONFIG_SOC_SERIES_R7FA8M85 is not set
# CONFIG_SOC_SERIES_R9A07G0 is not set
#
# Hardware Drivers Config
@@ -1081,9 +1050,10 @@ CONFIG_BSP_USING_UART4=y
# CONFIG_BSP_UART4_TX_USING_DMA is not set
CONFIG_BSP_UART4_RX_BUFSIZE=256
CONFIG_BSP_UART4_TX_BUFSIZE=0
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_SCI_SPI is not set
# CONFIG_BSP_USING_HW_I2C is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_SCI is not set
#
# Board extended module Drivers

445
bsp/renesas/ebf_qi_min_6m5/board/Kconfig
View File

@@ -21,7 +21,6 @@ menu "Hardware Drivers Config"
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART4
bool "Enable UART4"
default n
@@ -50,96 +49,37 @@ menu "Hardware Drivers Config"
endif
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
menuconfig BSP_USING_HW_I2C
bool "Enable hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
menuconfig BSP_USING_SOFT_I2C
bool "Enable software I2C bus"
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
menuconfig BSP_USING_SCI_I2C
bool "Enable SCI I2C BUS"
default n
if BSP_USING_SCI_I2C
config BSP_USING_SCI_I2C0
bool "Enable SCI I2C0 BUS"
default n
config BSP_USING_SCI_I2C1
bool "Enable SCI I2C1 BUS"
default n
config BSP_USING_SCI_I2C2
bool "Enable SCI I2C2 BUS"
default n
config BSP_USING_SCI_I2C3
bool "Enable SCI I2C3 BUS"
default n
config BSP_USING_SCI_I2C4
bool "Enable SCI I2C4 BUS"
default n
config BSP_USING_SCI_I2C5
bool "Enable SCI I2C5 BUS"
default n
config BSP_USING_SCI_I2C6
bool "Enable SCI I2C6 BUS"
default n
config BSP_USING_SCI_I2C7
bool "Enable SCI I2C7 BUS"
default n
config BSP_USING_SCI_I2C8
bool "Enable SCI I2C8 BUS"
default n
config BSP_USING_SCI_I2C9
bool "Enable SCI I2C9 BUS"
default n
endif
config BSP_USING_HW_I2C
bool "Enable Hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
if !BSP_USING_HW_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number"
range 0x0000 0x0B0F
default 0x050C
config BSP_I2C1_SDA_PIN
hex "I2C1 sda pin number"
range 0x0000 0x0B0F
default 0x050B
endif
endif
endif
menuconfig BSP_USING_SCI_SPI
bool "Enable SCI SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SCI_SPI
config BSP_USING_SCI_SPI0
bool "Enable SCI SPI0 BUS"
default n
config BSP_USING_SCI_SPI1
bool "Enable SCI SPI1 BUS"
default n
config BSP_USING_SCI_SPI2
bool "Enable SCI SPI2 BUS"
default n
config BSP_USING_SCI_SPI3
bool "Enable SCI SPI3 BUS"
default n
config BSP_USING_SCI_SPI5
bool "Enable SCI SPI5 BUS"
default n
config BSP_USING_SCI_SPI6
bool "Enable SCI SPI6 BUS"
if BSP_USING_SOFT_I2C
config BSP_USING_SOFT_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 Bus (software simulation)"
default n
if BSP_USING_I2C1
comment "Please refer to the 'bsp_io.h' file to configure the pins"
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number (hex)"
range 0x0000 0xFFFF
default 0x050C
config BSP_I2C1_SDA_PIN
hex "i2c1 sda pin number (hex)"
range 0x0000 0xFFFF
default 0x050B
endif
endif
menuconfig BSP_USING_SPI
@@ -155,6 +95,341 @@ menu "Hardware Drivers Config"
default n
endif
menuconfig BSP_USING_SCI
bool "Enable SCI Controller"
default n
config BSP_USING_SCIn_SPI
bool
default n
depends on BSP_USING_SCI
select RT_USING_SPI
config BSP_USING_SCIn_I2C
bool
default n
depends on BSP_USING_SCI
select RT_USING_I2C
config BSP_USING_SCIn_UART
bool
default n
depends on BSP_USING_SCI
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_SCI
config BSP_USING_SCI0
bool "Enable SCI0"
default n
if BSP_USING_SCI0
choice
prompt "choice sci mode"
default BSP_USING_SCI0_SPI
config BSP_USING_SCI0_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI0_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI0_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI0_UART
config BSP_SCI0_UART_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI0_UART_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI1
bool "Enable SCI1"
default n
if BSP_USING_SCI1
choice
prompt "choice sci mode"
default BSP_USING_SCI1_SPI
config BSP_USING_SCI1_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI1_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI1_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI1_UART
config BSP_SCI1_UART_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI1_UART_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI2
bool "Enable SCI2"
default n
if BSP_USING_SCI2
choice
prompt "choice sci mode"
default BSP_USING_SCI2_SPI
config BSP_USING_SCI2_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI2_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI2_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI2_UART
config BSP_SCI2_UART_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI2_UART_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI3
bool "Enable SCI3"
default n
if BSP_USING_SCI3
choice
prompt "choice sci mode"
default BSP_USING_SCI3_SPI
config BSP_USING_SCI3_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI3_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI3_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI3_UART
config BSP_SCI3_UART_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI3_UART_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI4
bool "Enable SCI4"
default n
if BSP_USING_SCI4
choice
prompt "choice sci mode"
default BSP_USING_SCI4_SPI
config BSP_USING_SCI4_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI4_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI4_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI4_UART
config BSP_SCI4_UART_RX_BUFSIZE
int "Set UART4 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI4_UART_TX_BUFSIZE
int "Set UART4 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI5
bool "Enable SCI5"
default n
if BSP_USING_SCI5
choice
prompt "choice sci mode"
default BSP_USING_SCI5_SPI
config BSP_USING_SCI5_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI5_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI5_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI5_UART
config BSP_SCI5_UART_RX_BUFSIZE
int "Set UART5 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI5_UART_TX_BUFSIZE
int "Set UART5 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI6
bool "Enable SCI6"
default n
if BSP_USING_SCI6
choice
prompt "choice sci mode"
default BSP_USING_SCI6_SPI
config BSP_USING_SCI6_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI6_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI6_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI6_UART
config BSP_SCI6_UART_RX_BUFSIZE
int "Set UART6 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI6_UART_TX_BUFSIZE
int "Set UART6 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI7
bool "Enable SCI7"
default n
if BSP_USING_SCI7
choice
prompt "choice sci mode"
default BSP_USING_SCI7_SPI
config BSP_USING_SCI7_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI7_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI7_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI7_UART
config BSP_SCI7_UART_RX_BUFSIZE
int "Set UART7 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI7_UART_TX_BUFSIZE
int "Set UART7 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI8
bool "Enable SCI8"
default n
if BSP_USING_SCI8
choice
prompt "choice sci mode"
default BSP_USING_SCI8_SPI
config BSP_USING_SCI8_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI8_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI8_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI8_UART
config BSP_SCI8_UART_RX_BUFSIZE
int "Set UART8 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI8_UART_TX_BUFSIZE
int "Set UART8 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI9
bool "Enable SCI9"
default n
if BSP_USING_SCI9
choice
prompt "choice sci mode"
default BSP_USING_SCI9_SPI
config BSP_USING_SCI9_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI9_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI9_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI9_UART
config BSP_SCI9_UART_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI9_UART_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
endif
endmenu
menu "Board extended module Drivers"

45
bsp/renesas/ebf_qi_min_6m5/project.uvprojx
View File

@@ -333,9 +333,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal</MiscControls>
<Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Define>RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS</Define>
<Undefine />
<IncludePath>..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\include;.;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\posix\io\poll;board\ports;board;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal</IncludePath>
<IncludePath>..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m4;board;..\..\..\components\libc\posix\ipc;board\ports;..\..\..\components\libc\posix\io\eventfd;..\libraries\HAL_Drivers\config;.;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\libraries\HAL_Drivers;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\poll;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -475,6 +475,25 @@
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>condvar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> </MiscControls>
<Define>__RT_IPC_SOURCE__</Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
@@ -690,13 +709,6 @@
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
@@ -706,16 +718,23 @@
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
</Files>
</Group>

17
bsp/renesas/ebf_qi_min_6m5/rtconfig.h
View File

@@ -137,12 +137,6 @@
/* CYW43012 WiFi */
/* BL808 WiFi */
/* CYW43439 WiFi */
/* IoT Cloud */
@@ -184,20 +178,15 @@
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */

6
bsp/renesas/libraries/HAL_Drivers/SConscript
View File

@@ -32,15 +32,9 @@ if GetDepend(['BSP_USING_SOFT_I2C']):
if GetDepend(['BSP_USING_HW_I2C']):
src += ['drv_i2c.c']
if GetDepend(['BSP_USING_SCI_I2C']):
src += ['drv_sci_i2c.c']
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['BSP_USING_SCI_SPI']):
src += ['drv_sci_spi.c']
if GetDepend(['BSP_USING_SOFT_SPI']):
src += ['drv_soft_spi.c']

19
bsp/renesas/libraries/HAL_Drivers/drv_gpio.c
View File

@@ -115,6 +115,15 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{
fsp_err_t err;
/* Initialize the IOPORT module and configure the pins */
err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
if (err != FSP_SUCCESS)
{
LOG_E("GPIO open failed");
return;
}
switch (mode)
{
case PIN_MODE_OUTPUT:
@@ -346,16 +355,6 @@ int rt_hw_pin_init(void)
ra_pin_map_init();
#endif
fsp_err_t err;
/* Initialize the IOPORT module and configure the pins */
err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
if (err != FSP_SUCCESS)
{
LOG_E("GPIO open failed");
return -1;
}
return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
}

4
bsp/renesas/libraries/HAL_Drivers/drv_pwm.c
View File

@@ -10,7 +10,7 @@
#include "drv_pwm.h"
#ifdef RT_USING_PWM
#ifdef BSP_USING_PWM
/* Declare the control function first */
static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
@@ -217,4 +217,4 @@ int rt_hw_pwm_init(void)
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pwm_init);
#endif /* RT_USING_PWM */
#endif /* BSP_USING_PWM */

25
bsp/renesas/libraries/HAL_Drivers/drv_sci.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -80,7 +80,7 @@ struct ra_sci_param
#ifdef RT_USING_SPI
rt_weak const struct rt_spi_ops sci_ops_spi;
#endif
#ifdef RT_USING_UART
#ifdef RT_USING_SERIAL
rt_weak const struct rt_uart_ops sci_ops_uart;
#endif
@@ -101,7 +101,7 @@ struct ra_sci_object
struct rt_i2c_bus_device ibus;
};
#endif
#ifdef RT_USING_UART
#ifdef RT_USING_SERIAL
struct
{
struct rt_serial_device ubus;
@@ -121,12 +121,14 @@ struct ra_sci_object
#define RA_SCI_EVENT_ERROR 8
#define RA_SCI_EVENT_ALL 15
#if defined(SOC_SERIES_R7FA4M2)
#define RA_SCI_HANDLE_ITEM(idx,type,id) {.bus_name=CONCAT3STR(sci_,type,idx),.sci_ctrl=&g_sci##idx##_ctrl,.sci_cfg=&g_sci##idx##_cfg,.ops=&sci_ops_##type}
#else
#define RA_SCI_HANDLE_ITEM(idx,type,id) {.bus_name=CONCAT3STR(sci_,type,idx),.sci_ctrl=&g_##type##idx##_ctrl,.sci_cfg=&g_##type##idx##_cfg,.ops=&sci_ops_##type}
#endif
/**
* Bus name format: sci[x][y], where x=0~9 and y=s/i/u
* Example:
* - sci_spi: sci0s
* - sci_i2c: sci0i
* - sci_uart: sci0u
*/
#define RA_SCI_HANDLE_ITEM(idx,type,id) {.bus_name=CONCAT3STR(sci,idx,id),.sci_ctrl=&g_sci##idx##_ctrl,.sci_cfg=&g_sci##idx##_cfg,.ops=&sci_ops_##type}
const static struct ra_sci_param sci_param[] =
{
@@ -667,12 +669,8 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
/**< config bitrate */
#ifdef R_SCI_B_SPI_H
R_SCI_B_SPI_CalculateBitrate(obj->spi_cfg->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div);
#else
#if defined(SOC_SERIES_R7FA4M2)
R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &cfg_ext->clk_div, false);
#else
R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &spi_cfg->clk_div, false);
#endif
#endif
/**< init */
@@ -753,6 +751,7 @@ const struct rt_spi_ops sci_ops_spi =
static int ra_hw_sci_init(void)
{
int bufsz_idx = 0;
for (rt_uint8_t idx = 0; idx < RA_SCI_INDEX_MAX; idx++)
{
struct ra_sci_object *obj = &sci_obj[idx];

4
bsp/renesas/libraries/HAL_Drivers/drv_sci.h
View File

@@ -23,7 +23,9 @@
extern "C" {
#endif
rt_err_t drv_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
#ifdef BSP_USING_SCIn_SPI
rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
#endif
#ifdef __cplusplus
}

209
bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c
View File

@@ -1,209 +0,0 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-06-04 vandoul first version
*/
#include <rtdevice.h>
#include <rtthread.h>
#include "board.h"
#include <stdlib.h>
#ifdef BSP_USING_SCI_I2C
#define DBG_TAG "drv.sci2c"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#include <hal_data.h>
struct ra_sci_i2c_handle
{
struct rt_i2c_bus_device bus;
char bus_name[RT_NAME_MAX];
const i2c_master_cfg_t *i2c_cfg;
void *i2c_ctrl;
struct rt_event event;
};
enum
{
I2C_EVENT_ABORTED = 1UL<<I2C_MASTER_EVENT_ABORTED , ///< A transfer was aborted
I2C_EVENT_RX_COMPLETE = 1UL<<I2C_MASTER_EVENT_RX_COMPLETE, ///< A receive operation was completed successfully
I2C_EVENT_TX_COMPLETE = 1UL<<I2C_MASTER_EVENT_TX_COMPLETE, ///< A transmit operation was completed successfully
};
#define I2C_EVENT_ALL (I2C_EVENT_ABORTED|I2C_EVENT_RX_COMPLETE|I2C_EVENT_TX_COMPLETE)
//static volatile = I2C_MASTER_EVENT_ABORTED;
static struct ra_sci_i2c_handle ra_sci_i2cs[] =
{
#ifdef BSP_USING_SCI_I2C0
{.bus_name = "sci2c0", .i2c_cfg = &g_sci_i2c0_cfg, .i2c_ctrl = &g_sci_i2c0_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C1
{.bus_name = "sci2c1", .i2c_cfg = &g_sci_i2c1_cfg, .i2c_ctrl = &g_sci_i2c1_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C2
{.bus_name = "sci2c2", .i2c_cfg = &g_sci_i2c2_cfg, .i2c_ctrl = &g_sci_i2c2_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C3
{.bus_name = "sci2c3", .i2c_cfg = &g_sci_i2c3_cfg, .i2c_ctrl = &g_sci_i2c3_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C4
{.bus_name = "sci2c4", .i2c_cfg = &g_sci_i2c4_cfg, .i2c_ctrl = &g_sci_i2c4_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C5
{.bus_name = "sci2c5", .i2c_cfg = &g_sci_i2c5_cfg, .i2c_ctrl = &g_sci_i2c5_ctrl,},
#endif
};
void sci_i2c_master_callback(i2c_master_callback_args_t *p_args)
{
if (NULL != p_args)
{
/* capture callback event for validating the i2c transfer event*/
struct ra_sci_i2c_handle *ra_sci_i2c = (struct ra_sci_i2c_handle *)p_args->p_context;
rt_event_send(&ra_sci_i2c->event, 1UL << p_args->event);
LOG_D("event:%x", p_args->event);
}
LOG_D("p_args:%p", p_args);
}
static rt_err_t validate_i2c_event(struct ra_sci_i2c_handle *handle)
{
rt_uint32_t event = 0;
if(RT_EOK != rt_event_recv(&handle->event, I2C_EVENT_ALL, RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(10), &event))
{
return -RT_ETIMEOUT;
}
if(event != I2C_EVENT_ABORTED)
{
return RT_EOK;
}
return -RT_ERROR;
}
static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
rt_size_t i;
struct rt_i2c_msg *msg = msgs;
RT_ASSERT(bus != RT_NULL);
struct ra_sci_i2c_handle *ra_sci_i2c = rt_container_of(bus, struct ra_sci_i2c_handle, bus);
i2c_master_ctrl_t *master_ctrl = ra_sci_i2c->i2c_ctrl;
fsp_err_t err = FSP_SUCCESS;
bool restart = false;
for (i = 0; i < num; i++)
{
if (msg[i].flags & RT_I2C_NO_START)
{
restart = true;
}
if (msg[i].flags & RT_I2C_ADDR_10BIT)
{
//LOG_E("10Bit not support");
//break;
R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT);
}
else
{
//master_ctrl->slave = msg[i].addr;
R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT);
}
if (msg[i].flags & RT_I2C_RD)
{
err = R_SCI_I2C_Read(master_ctrl, msg[i].buf, msg[i].len, restart);
if (FSP_SUCCESS == err)
{
/* handle error */
if(RT_EOK != validate_i2c_event(ra_sci_i2c))
{
//LOG_E("POWER_CTL reg I2C read failed,%d", ra_sci_i2c->event);
break;
}
}
/* handle error */
else
{
/* Write API returns itself is not successful */
//LOG_E("R_IIC_MASTER_Write API failed");
break;
}
}
else
{
err = R_SCI_I2C_Write(master_ctrl, msg[i].buf, msg[i].len, restart);
if (FSP_SUCCESS == err)
{
if(RT_EOK != validate_i2c_event(ra_sci_i2c))
{
//LOG_E("POWER_CTL reg I2C write failed,%d", ra_sci_i2c->event);
break;
}
}
/* handle error */
else
{
/* Write API returns itself is not successful */
//LOG_E("R_IIC_MASTER_Write API failed");
break;
}
}
}
return (rt_ssize_t)i;
}
static const struct rt_i2c_bus_device_ops ra_i2c_ops =
{
.master_xfer = ra_i2c_mst_xfer,
.slave_xfer = RT_NULL,
.i2c_bus_control = RT_NULL
};
int ra_hw_i2c_init(void)
{
fsp_err_t err = FSP_SUCCESS;
for(rt_uint32_t i=0; i<sizeof(ra_sci_i2cs)/sizeof(ra_sci_i2cs[0]); i++)
{
ra_sci_i2cs[i].bus.ops = &ra_i2c_ops;
ra_sci_i2cs[i].bus.priv = 0;
if(RT_EOK != rt_event_init(&ra_sci_i2cs[i].event, ra_sci_i2cs[i].bus_name, RT_IPC_FLAG_FIFO))
{
LOG_E("init event failed");
continue;
}
/* opening IIC master module */
err = R_SCI_I2C_Open(ra_sci_i2cs[i].i2c_ctrl, ra_sci_i2cs[i].i2c_cfg);
if(err != FSP_SUCCESS)
{
LOG_E("R_IIC_MASTER_Open API failed,%d", err);
continue;
}
err = R_SCI_I2C_CallbackSet(ra_sci_i2cs[i].i2c_ctrl, sci_i2c_master_callback, &ra_sci_i2cs[i], RT_NULL);
/* handle error */
if (FSP_SUCCESS != err)
{
LOG_E("R_SCI_I2C_CallbackSet API failed,%d", err);
continue;
}
rt_i2c_bus_device_register(&ra_sci_i2cs[i].bus, ra_sci_i2cs[i].bus_name);
}
return 0;
}
INIT_DEVICE_EXPORT(ra_hw_i2c_init);
#endif /* BSP_USING_I2C */

391
bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.c
View File

@@ -1,391 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
* 2021-11-04 Sherman ADD complete_event
* 2022-12-7 Vandoul ADD sci spi
*/
/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
#include "drv_sci_spi.h"
#ifdef RT_USING_SPI
//#define DRV_DEBUG
#define DBG_TAG "drv.scispi"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#ifdef R_SCI_B_SPI_H
#define R_SCI_SPI_Write R_SCI_B_SPI_Write
#define R_SCI_SPI_Read R_SCI_B_SPI_Read
#define R_SCI_SPI_WriteRead R_SCI_B_SPI_WriteRead
#define R_SCI_SPI_Open R_SCI_B_SPI_Open
#define R_SCI_SPI_Close R_SCI_B_SPI_Close
#endif
#define RA_SCI_SPI0_EVENT 0x0001
#define RA_SCI_SPI1_EVENT 0x0002
#define RA_SCI_SPI2_EVENT 0x0004
#define RA_SCI_SPI3_EVENT 0x0008
#define RA_SCI_SPI4_EVENT 0x0010
#define RA_SCI_SPI5_EVENT 0x0020
#define RA_SCI_SPI6_EVENT 0x0040
#define RA_SCI_SPI7_EVENT 0x0080
#define RA_SCI_SPI8_EVENT 0x0100
#define RA_SCI_SPI9_EVENT 0x0200
static struct rt_event complete_event = {0};
static struct ra_sci_spi_handle spi_handle[] =
{
#ifdef BSP_USING_SCI_SPI0
{.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI1
{.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI2
{.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI3
{.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI4
{.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI5
{.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI6
{.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI7
{.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI8
{.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI9
{.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,},
#endif
};
static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
#define SCI_SPIx_CALLBACK(n) \
void sci_spi##n##_callback(spi_callback_args_t *p_args) \
{ \
rt_interrupt_enter(); \
if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \
{ \
rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \
} \
rt_interrupt_leave(); \
}
SCI_SPIx_CALLBACK(0);
SCI_SPIx_CALLBACK(1);
SCI_SPIx_CALLBACK(2);
SCI_SPIx_CALLBACK(3);
SCI_SPIx_CALLBACK(4);
SCI_SPIx_CALLBACK(5);
SCI_SPIx_CALLBACK(6);
SCI_SPIx_CALLBACK(7);
SCI_SPIx_CALLBACK(8);
SCI_SPIx_CALLBACK(9);
#define SCI_SPIx_EVENT_RECV(n) \
rt_event_recv(event, \
RA_SCI_SPI##n##_EVENT, \
RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \
rt_tick_from_millisecond(1000), \
&recved);
static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
{
rt_uint32_t recved = 0x00;
rt_err_t ret = RT_EOK;
switch (bus_name[4])
{
case '0':
ret = SCI_SPIx_EVENT_RECV(0);
break;
case '1':
ret = SCI_SPIx_EVENT_RECV(1);
break;
case '2':
ret = SCI_SPIx_EVENT_RECV(2);
break;
case '3':
ret = SCI_SPIx_EVENT_RECV(3);
break;
case '4':
ret = SCI_SPIx_EVENT_RECV(4);
break;
case '5':
ret = SCI_SPIx_EVENT_RECV(5);
break;
case '6':
ret = SCI_SPIx_EVENT_RECV(6);
break;
case '7':
ret = SCI_SPIx_EVENT_RECV(7);
break;
case '8':
ret = SCI_SPIx_EVENT_RECV(8);
break;
case '9':
ret = SCI_SPIx_EVENT_RECV(9);
break;
default:
break;
}
if (ret != RT_EOK)
{
LOG_D("%s ra_wait_complete failed!", bus_name);
return ret;
}
return -RT_EINVAL;
}
static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
{
spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
if(data_width == 1)
bit_width = SPI_BIT_WIDTH_8_BITS;
else if(data_width == 2)
bit_width = SPI_BIT_WIDTH_16_BITS;
else if(data_width == 4)
bit_width = SPI_BIT_WIDTH_32_BITS;
return bit_width;
}
static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
RT_ASSERT(send_buf != NULL);
RT_ASSERT(len > 0);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< send msessage */
err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
return len;
}
static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
RT_ASSERT(recv_buf != NULL);
RT_ASSERT(len > 0);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< receive message */
err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
return len;
}
static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(message->length > 0);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< write and receive message */
err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
return message->length;
}
/**< init spi TODO : MSB does not support modification */
static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != NULL);
RT_ASSERT(configuration != NULL);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
/**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
rt_uint8_t data_width = configuration->data_width / 8;
RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
configuration->data_width = configuration->data_width / 8;
spi_dev->rt_spi_cfg_t = configuration;
#ifdef R_SCI_B_SPI_H
sci_b_spi_extended_cfg_t spi_cfg = *(sci_b_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
#else
sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
#endif
/**< Configure Select Line */
rt_pin_write(device->cs_pin, PIN_HIGH);
/**< config bitrate */
#ifdef R_SCI_B_SPI_H
R_SCI_B_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div);
#else
R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false);
#endif
/**< init */
err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
/* handle error */
if(err == FSP_ERR_IN_USE) {
R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t);
err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
}
if (RT_EOK != err)
{
LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
return RT_EOK;
}
static rt_ssize_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(message != RT_NULL);
rt_err_t err = RT_EOK;
if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
{
if (device->config.mode & RT_SPI_CS_HIGH)
rt_pin_write(device->cs_pin, PIN_HIGH);
else
rt_pin_write(device->cs_pin, PIN_LOW);
}
if (message->length > 0)
{
if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
{
/**< receive message */
err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
}
else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
{
/**< send message */
err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
}
else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
{
/**< send and receive message */
err = ra_write_read_message(device, message);
}
}
if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
{
if (device->config.mode & RT_SPI_CS_HIGH)
rt_pin_write(device->cs_pin, PIN_LOW);
else
rt_pin_write(device->cs_pin, PIN_HIGH);
}
return err;
}
static const struct rt_spi_ops ra_spi_ops =
{
.configure = ra_hw_spi_configure,
.xfer = ra_spixfer,
};
int ra_hw_sci_spi_init(void)
{
for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
{
spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
/**< register spi bus */
rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
if (RT_EOK != err)
{
LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
}
if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO))
{
LOG_E("SPI transfer event init fail!");
return -RT_ERROR;
}
return RT_EOK;
}
INIT_BOARD_EXPORT(ra_hw_sci_spi_init);
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
LOG_D("%s attach to %s done", device_name, bus_name);
return result;
}
#endif /* RT_USING_SPI */

56
bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.h
View File

@@ -1,56 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
* 2022-12-7 Vandoul ADD sci spi
*/
#ifndef __DRV_SCI_SPI_H__
#define __DRV_SCI_SPI_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#include "board.h"
#include <rthw.h>
#include <drv_common.h>
#include <drv_config.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(R_SCI_SPI_H) || defined(R_SCI_B_SPI_H)
struct ra_sci_spi_handle
{
const char bus_name[RT_NAME_MAX];
const spi_cfg_t *spi_cfg_t;
#ifdef R_SCI_B_SPI_H
const sci_b_spi_instance_ctrl_t *spi_ctrl_t;
#else
const sci_spi_instance_ctrl_t *spi_ctrl_t;
#endif
};
struct ra_sci_spi
{
rt_uint32_t cs_pin;
struct ra_sci_spi_handle *ra_spi_handle_t;
struct rt_spi_configuration *rt_spi_cfg_t;
struct rt_spi_bus bus;
};
#endif
rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
#ifdef __cplusplus
}
#endif
/* stm32 spi dirver class */
#endif /*__DRV_SPI_H__ */

4
bsp/renesas/libraries/HAL_Drivers/drv_spi.c
View File

@@ -13,7 +13,7 @@
#include "drv_spi.h"
#ifdef RT_USING_SPI
#ifdef BSP_USING_SPI
//#define DRV_DEBUG
#define DBG_TAG "drv.spi"
@@ -310,4 +310,4 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
return result;
}
#endif /* RT_USING_SPI */
#endif /* BSP_USING_SPI */

87
bsp/renesas/ra2l1-cpk/.config
View File

@@ -294,16 +294,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CYW43012 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43012 is not set
#
# BL808 WiFi
#
# CONFIG_PKG_USING_WLAN_BL808 is not set
#
# CYW43439 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43439 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
@@ -325,6 +315,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -346,7 +337,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_BT_CYW43012 is not set
# CONFIG_PKG_USING_CYW43XX is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
@@ -367,7 +357,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
# CONFIG_PKG_USING_LHC_MODBUS is not set
#
# security packages
@@ -512,9 +501,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_CORE is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
# CONFIG_PKG_USING_CMSIS_NN is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
@@ -534,8 +520,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FILEX is not set
# CONFIG_PKG_USING_LEVELX is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@@ -573,35 +557,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_SFDB is not set
# CONFIG_PKG_USING_RTP is not set
# CONFIG_PKG_USING_REB is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
#
# peripheral libraries and drivers
#
#
# HAL & SDK Drivers
#
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
#
# sensors drivers
#
@@ -683,8 +643,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_CST812T is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@@ -692,6 +653,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -706,6 +675,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
@@ -728,6 +698,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
@@ -737,6 +708,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -744,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
@@ -752,9 +725,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ST7789 is not set
# CONFIG_PKG_USING_VS1003 is not set
# CONFIG_PKG_USING_X9555 is not set
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
@@ -769,7 +739,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
#
# Signal Processing and Control Algorithm Packages
@@ -779,6 +748,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
#
# miscellaneous packages
@@ -854,9 +824,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@@ -864,13 +832,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -915,7 +883,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -954,6 +922,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -976,7 +945,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -984,7 +953,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -997,7 +966,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
#
# Display
@@ -1023,7 +991,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
#
# Data Storage
@@ -1040,11 +1007,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
@@ -1067,6 +1034,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# Uncategorized
#
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
CONFIG_SOC_FAMILY_RENESAS=y
# CONFIG_SOC_SERIES_R7FA6M3 is not set
# CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1074,6 +1042,7 @@ CONFIG_SOC_SERIES_R7FA2L1=y
# CONFIG_SOC_SERIES_R7FA6M5 is not set
# CONFIG_SOC_SERIES_R7FA4M2 is not set
# CONFIG_SOC_SERIES_R7FA8M85 is not set
# CONFIG_SOC_SERIES_R9A07G0 is not set
#
# Hardware Drivers Config
@@ -1102,13 +1071,15 @@ CONFIG_BSP_USING_UART9=y
# CONFIG_BSP_UART9_TX_USING_DMA is not set
CONFIG_BSP_UART9_RX_BUFSIZE=256
CONFIG_BSP_UART9_TX_BUFSIZE=0
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_HW_I2C is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_LPM is not set
# CONFIG_BSP_USING_SCI is not set
#
# Board extended module Drivers

16
bsp/renesas/ra2l1-cpk/.settings/standalone.prefs
View File

@@ -1,21 +1,19 @@
#Fri Jul 22 15:41:36 CST 2022
#Sat Apr 13 23:24:56 CST 2024
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=2985489297,ra/board/ra2l1_cpk/board_init.h|383876238,ra/board/ra2l1_cpk/board_leds.h|2918861270,ra/board/ra2l1_cpk/board_leds.c|586415029,ra/board/ra2l1_cpk/board.h|1521504391,ra/board/ra2l1_cpk/board_init.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2425160085,ra/fsp/inc/api/bsp_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2208590403,ra/fsp/inc/instances/r_ioport.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3297195641,ra/fsp/inc/fsp_version.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1728953905,ra/fsp/inc/fsp_features.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=ra/board/ra2l1_cpk/board_init.h|ra/board/ra2l1_cpk/board_leds.h|ra/board/ra2l1_cpk/board_leds.c|ra/board/ra2l1_cpk/board.h|ra/board/ra2l1_cpk/board_init.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3297195641,ra/fsp/inc/fsp_version.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1728953905,ra/fsp/inc/fsp_features.h|2425160085,ra/fsp/inc/api/bsp_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|546480625,ra/fsp/inc/fsp_common_api.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#R7FA2L1AB2DFM\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|1906465970,ra/fsp/inc/api/r_external_irq_api.h|3018483678,ra/fsp/src/r_icu/r_icu.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.629312687=false
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=

370
bsp/renesas/ra2l1-cpk/board/Kconfig
View File

@@ -161,36 +161,37 @@ menu "Hardware Drivers Config"
endif
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
menuconfig BSP_USING_HW_I2C
bool "Enable hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
menuconfig BSP_USING_SOFT_I2C
bool "Enable software I2C bus"
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_HW_I2C
bool "Enable Hardware I2C BUS"
default n
if BSP_USING_SOFT_I2C
config BSP_USING_SOFT_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 Bus (software simulation)"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
if !BSP_USING_HW_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number"
range 0x0000 0x0B0F
default 0x050C
config BSP_I2C1_SDA_PIN
hex "I2C1 sda pin number"
range 0x0000 0x0B0F
default 0x050B
endif
endif
if BSP_USING_I2C1
comment "Please refer to the 'bsp_io.h' file to configure the pins"
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number (hex)"
range 0x0000 0xFFFF
default 0x050C
config BSP_I2C1_SDA_PIN
hex "i2c1 sda pin number (hex)"
range 0x0000 0xFFFF
default 0x050B
endif
endif
menuconfig BSP_USING_SPI
@@ -305,6 +306,325 @@ menu "Hardware Drivers Config"
default n
endif
menuconfig BSP_USING_SCI
bool "Enable SCI Controller"
default n
if BSP_USING_SCI
config BSP_USING_SCI0
bool "Enable SCI0"
default n
if BSP_USING_SCI0
choice
prompt "choice sci mode"
default BSP_USING_SCI0_SPI
config BSP_USING_SCI0_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI0_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI0_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI0_UART
config BSP_SCI0_UART_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI0_UART_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI1
bool "Enable SCI1"
default n
if BSP_USING_SCI1
choice
prompt "choice sci mode"
default BSP_USING_SCI1_SPI
config BSP_USING_SCI1_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI1_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI1_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI1_UART
config BSP_SCI1_UART_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI1_UART_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI2
bool "Enable SCI2"
default n
if BSP_USING_SCI2
choice
prompt "choice sci mode"
default BSP_USING_SCI2_SPI
config BSP_USING_SCI2_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI2_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI2_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI2_UART
config BSP_SCI2_UART_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI2_UART_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI3
bool "Enable SCI3"
default n
if BSP_USING_SCI3
choice
prompt "choice sci mode"
default BSP_USING_SCI3_SPI
config BSP_USING_SCI3_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI3_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI3_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI3_UART
config BSP_SCI3_UART_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI3_UART_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI4
bool "Enable SCI4"
default n
if BSP_USING_SCI4
choice
prompt "choice sci mode"
default BSP_USING_SCI4_SPI
config BSP_USING_SCI4_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI4_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI4_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI4_UART
config BSP_SCI4_UART_RX_BUFSIZE
int "Set UART4 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI4_UART_TX_BUFSIZE
int "Set UART4 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI5
bool "Enable SCI5"
default n
if BSP_USING_SCI5
choice
prompt "choice sci mode"
default BSP_USING_SCI5_SPI
config BSP_USING_SCI5_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI5_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI5_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI5_UART
config BSP_SCI5_UART_RX_BUFSIZE
int "Set UART5 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI5_UART_TX_BUFSIZE
int "Set UART5 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI6
bool "Enable SCI6"
default n
if BSP_USING_SCI6
choice
prompt "choice sci mode"
default BSP_USING_SCI6_SPI
config BSP_USING_SCI6_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI6_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI6_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI6_UART
config BSP_SCI6_UART_RX_BUFSIZE
int "Set UART6 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI6_UART_TX_BUFSIZE
int "Set UART6 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI7
bool "Enable SCI7"
default n
if BSP_USING_SCI7
choice
prompt "choice sci mode"
default BSP_USING_SCI7_SPI
config BSP_USING_SCI7_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI7_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI7_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI7_UART
config BSP_SCI7_UART_RX_BUFSIZE
int "Set UART7 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI7_UART_TX_BUFSIZE
int "Set UART7 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI8
bool "Enable SCI8"
default n
if BSP_USING_SCI8
choice
prompt "choice sci mode"
default BSP_USING_SCI8_SPI
config BSP_USING_SCI8_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI8_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI8_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI8_UART
config BSP_SCI8_UART_RX_BUFSIZE
int "Set UART8 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI8_UART_TX_BUFSIZE
int "Set UART8 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI9
bool "Enable SCI9"
default n
if BSP_USING_SCI9
choice
prompt "choice sci mode"
default BSP_USING_SCI9_SPI
config BSP_USING_SCI9_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI9_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI9_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI9_UART
config BSP_SCI9_UART_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI9_UART_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
endif
endmenu
menu "Board extended module Drivers"

22
bsp/renesas/ra2l1-cpk/buildinfo.gpdsc
View File

@@ -56,45 +56,56 @@
<file category="source" name="ra/board/ra2l1_cpk/board_leds.c"/>
<file category="header" name="ra/board/ra2l1_cpk/board_leds.h" path=""/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h" path=""/>
@@ -102,9 +113,12 @@
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h" path=""/>
<file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
<file category="other" name="ra/fsp/src/r_dtc/r_dtc.o"/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
<file category="other" name="ra/fsp/src/r_sci_spi/r_sci_spi.o"/>
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
<file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
@@ -112,13 +126,11 @@
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>

17
bsp/renesas/ra2l1-cpk/configuration.xml
View File

@@ -150,10 +150,6 @@
<description>SCI UART</description>
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_icu" variant="" vendor="Renesas" version="3.5.0">
<description>External Interrupt</description>
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
<raIcuConfiguration/>
@@ -192,26 +188,13 @@
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority2"/>
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority2"/>
</module>
<module id="module.driver.external_irq_on_icu.832378872">
<property id="module.driver.external_irq.name" value="g_external_irq3"/>
<property id="module.driver.external_irq.channel" value="3"/>
<property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
<property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
<property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
<property id="module.driver.external_irq.p_callback" value="irq_callback"/>
<property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority2"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.uart_on_sci_uart.629312687"/>
<stack module="module.driver.external_irq_on_icu.832378872"/>
</context>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
<config id="config.driver.icu">
<property id="config.driver.icu.param_checking_enable" value="config.driver.icu.param_checking_enable.bsp"/>
</config>
<config id="config.driver.sci_uart">
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>

59
bsp/renesas/ra2l1-cpk/project.uvprojx
View File

@@ -334,9 +334,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
<Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Define>RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __RTTHREAD__</Define>
<Undefine />
<IncludePath>..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m23;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;ra_cfg\fsp_cfg\bsp;.;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;board\ports;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;ra_cfg\fsp_cfg;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;board;..\..\..\components\libc\posix\io\epoll;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh</IncludePath>
<IncludePath>ra_cfg\fsp_cfg\bsp;..\..\..\components\libc\posix\ipc;board;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m23;.;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;board\ports;..\..\..\components\drivers\include;..\..\..\components\drivers\include;ra_cfg\fsp_cfg;..\..\..\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\finsh;..\libraries\HAL_Drivers</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -476,6 +476,25 @@
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>condvar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> </MiscControls>
<Define>__RT_IPC_SOURCE__</Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
@@ -698,6 +717,13 @@
<FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_posix.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_file.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_fs.c</FileName>
@@ -712,21 +738,14 @@
<FilePath>..\..\..\components\dfs\dfs_v1\src\dfs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\dfs_v1\src\dfs_file.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
</Files>
<Files>
@@ -738,9 +757,16 @@
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
@@ -750,13 +776,6 @@
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>

177
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h
View File

@@ -1,177 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup EXTERNAL_IRQ_API External IRQ Interface
* @brief Interface for detecting external interrupts.
*
* @section EXTERNAL_IRQ_API_Summary Summary
* The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an
* external IRQ pin.
*
* The External IRQ Interface can be implemented by:
* - @ref ICU
*
* @{
**********************************************************************************************************************/
#ifndef R_EXTERNAL_IRQ_API_H
#define R_EXTERNAL_IRQ_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
*********************************************************************************************************************/
/*********************************************************************************************************************
* Typedef definitions
*********************************************************************************************************************/
/** Callback function parameter data */
typedef struct st_external_irq_callback_args
{
/** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */
void const * p_context;
uint32_t channel; ///< The physical hardware channel that caused the interrupt.
} external_irq_callback_args_t;
/** Condition that will trigger an interrupt when detected. */
typedef enum e_external_irq_trigger
{
EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger
EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger
EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger
EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger
} external_irq_trigger_t;
/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger
* conditions that are shorter than 3 periods of the filter clock.
*/
typedef enum e_external_irq_pclk_div
{
EXTERNAL_IRQ_PCLK_DIV_BY_1 = 0, ///< Filter using PCLK divided by 1
EXTERNAL_IRQ_PCLK_DIV_BY_8 = 1, ///< Filter using PCLK divided by 8
EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2, ///< Filter using PCLK divided by 32
EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3, ///< Filter using PCLK divided by 64
} external_irq_pclk_div_t;
/** User configuration structure, used in open function */
typedef struct st_external_irq_cfg
{
uint8_t channel; ///< Hardware channel used.
uint8_t ipl; ///< Interrupt priority
IRQn_Type irq; ///< NVIC interrupt number assigned to this instance
external_irq_trigger_t trigger; ///< Trigger setting.
external_irq_pclk_div_t pclk_div; ///< Digital filter clock divisor setting.
bool filter_enable; ///< Digital filter enable/disable setting.
/** Callback provided external input trigger occurs. */
void (* p_callback)(external_irq_callback_args_t * p_args);
/** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */
void const * p_context;
void const * p_extend; ///< External IRQ hardware dependent configuration.
} external_irq_cfg_t;
/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls.
* @par Implemented as
* - icu_instance_ctrl_t
*/
typedef void external_irq_ctrl_t;
/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */
typedef struct st_external_irq_api
{
/** Initial configuration.
* @par Implemented as
* - @ref R_ICU_ExternalIrqOpen()
*
* @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user.
*/
fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg);
/** Enable callback when an external trigger condition occurs.
* @par Implemented as
* - @ref R_ICU_ExternalIrqEnable()
*
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
*/
fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl);
/** Disable callback when external trigger condition occurs.
* @par Implemented as
* - @ref R_ICU_ExternalIrqDisable()
*
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
*/
fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl);
/**
* Specify callback function and optional context pointer and working memory pointer.
* @par Implemented as
* - R_ICU_ExternalIrqCallbackSet()
*
* @param[in] p_ctrl Pointer to the Extneral IRQ control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_api_ctrl,
void ( * p_callback)(external_irq_callback_args_t *),
void const * const p_context,
external_irq_callback_args_t * const p_callback_memory);
/** Allow driver to be reconfigured. May reduce power consumption.
* @par Implemented as
* - @ref R_ICU_ExternalIrqClose()
*
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
*/
fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl);
} external_irq_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_external_irq_instance
{
external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance
} external_irq_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
/*******************************************************************************************************************//**
* @} (end defgroup EXTERNAL_IRQ_API)
**********************************************************************************************************************/
#endif

95
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h
View File

@@ -1,95 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup ICU
* @{
**********************************************************************************************************************/
#ifndef R_ICU_H
#define R_ICU_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_external_irq_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/*********************************************************************************************************************
* Typedef definitions
*********************************************************************************************************************/
/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */
typedef struct st_icu_instance_ctrl
{
uint32_t open; ///< Used to determine if channel control block is in use
IRQn_Type irq; ///< NVIC interrupt number
uint8_t channel; ///< Channel
#if BSP_TZ_SECURE_BUILD
external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
#endif
void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin.
/** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */
void const * p_context;
} icu_instance_ctrl_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const external_irq_api_t g_external_irq_on_icu;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg);
fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl);
fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl);
fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl,
void ( * p_callback)(external_irq_callback_args_t *),
void const * const p_context,
external_irq_callback_args_t * const p_callback_memory);
fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl);
/*******************************************************************************************************************//**
* @} (end defgroup ICU)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif // R_ICU_H

370
bsp/renesas/ra2l1-cpk/ra/fsp/src/r_icu/r_icu.c
View File

@@ -1,370 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "r_icu.h"
#include "r_icu_cfg.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** "ICU" in ASCII, used to determine if channel is open. */
#define ICU_OPEN (0x00494355U)
#define ICU_IRQMD_OFFSET (0)
#define ICU_FCLKSEL_OFFSET (4)
#define ICU_FLTEN_OFFSET (7)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
typedef void (BSP_CMSE_NONSECURE_CALL * icu_prv_ns_callback)(external_irq_callback_args_t * p_args);
#elif defined(__GNUC__)
typedef BSP_CMSE_NONSECURE_CALL void (*volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args);
#endif
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
void r_icu_isr(void);
/***********************************************************************************************************************
* Private global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Global Variables
**********************************************************************************************************************/
/* ICU implementation of External IRQ API. */
const external_irq_api_t g_external_irq_on_icu =
{
.open = R_ICU_ExternalIrqOpen,
.enable = R_ICU_ExternalIrqEnable,
.disable = R_ICU_ExternalIrqDisable,
.callbackSet = R_ICU_ExternalIrqCallbackSet,
.close = R_ICU_ExternalIrqClose,
};
/*******************************************************************************************************************//**
* @addtogroup ICU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Configure an IRQ input pin for use with the external interrupt interface. Implements @ref external_irq_api_t::open.
*
* The Open function is responsible for preparing an external IRQ pin for operation.
*
* @retval FSP_SUCCESS Open successful.
* @retval FSP_ERR_ASSERTION One of the following is invalid:
* - p_ctrl or p_cfg is NULL
* @retval FSP_ERR_ALREADY_OPEN The channel specified has already been opened. No configurations were changed.
* Call the associated Close function to reconfigure the channel.
* @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in
* r_bsp_cfg.h.
* @retval FSP_ERR_INVALID_ARGUMENT p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to
* use callback function.
*
* @note This function is reentrant for different channels. It is not reentrant for the same channel.
**********************************************************************************************************************/
fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg)
{
icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
#if ICU_CFG_PARAM_CHECKING_ENABLE
FSP_ASSERT(NULL != p_ctrl);
FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
FSP_ASSERT(NULL != p_cfg);
FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
/* Callback must be used with a valid interrupt priority otherwise it will never be called. */
if (p_cfg->p_callback)
{
FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT);
}
#endif
p_ctrl->irq = p_cfg->irq;
/* IELSR Must be zero when modifying the IRQCR bits.
* (See ICU Section 14.2.1 of the RA6M3 manual R01UH0886EJ0100). */
uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq];
R_ICU->IELSR[p_ctrl->irq] = 0;
#if BSP_TZ_SECURE_BUILD
/* If this is a secure build, the callback provided in p_cfg must be secure. */
p_ctrl->p_callback_memory = NULL;
#endif
/* Initialize control block. */
p_ctrl->p_callback = p_cfg->p_callback;
p_ctrl->p_context = p_cfg->p_context;
p_ctrl->channel = p_cfg->channel;
/* Disable digital filter */
R_ICU->IRQCR[p_ctrl->channel] = 0U;
/* Set the digital filter divider. */
uint8_t irqcr = (uint8_t) (p_cfg->pclk_div << ICU_FCLKSEL_OFFSET);
/* Enable/Disable digital filter. */
irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET);
/* Set the IRQ trigger. */
irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET);
/* Write IRQCR */
R_ICU->IRQCR[p_ctrl->channel] = irqcr;
/* Restore IELSR. */
R_ICU->IELSR[p_ctrl->irq] = ielsr;
/* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases
* where the external IRQ driver is used to generate ELC events only (without CPU interrupts).
* In such cases we will not set the IRQ priority but will continue with the processing.
*/
if (p_ctrl->irq >= 0)
{
R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl);
}
/* Mark the control block as open */
p_ctrl->open = ICU_OPEN;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable.
*
* @retval FSP_SUCCESS Interrupt Enabled successfully.
* @retval FSP_ERR_ASSERTION The p_ctrl parameter was null.
* @retval FSP_ERR_NOT_OPEN The channel is not opened.
* @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system
**********************************************************************************************************************/
fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl)
{
icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
#if ICU_CFG_PARAM_CHECKING_ENABLE
FSP_ASSERT(NULL != p_ctrl);
FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
#endif
/* Clear the interrupt status and Pending bits, before the interrupt is enabled. */
R_BSP_IrqEnable(p_ctrl->irq);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable.
*
* @retval FSP_SUCCESS Interrupt disabled successfully.
* @retval FSP_ERR_ASSERTION The p_ctrl parameter was null.
* @retval FSP_ERR_NOT_OPEN The channel is not opened.
* @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system
**********************************************************************************************************************/
fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl)
{
icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
#if ICU_CFG_PARAM_CHECKING_ENABLE
FSP_ASSERT(NULL != p_ctrl);
FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
#endif
/* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
R_BSP_IrqDisable(p_ctrl->irq);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Updates the user callback and has option of providing memory for callback structure.
* Implements external_irq_api_t::callbackSet
*
* @retval FSP_SUCCESS Callback updated successfully.
* @retval FSP_ERR_ASSERTION A required pointer is NULL.
* @retval FSP_ERR_NOT_OPEN The control block has not been opened.
* @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL.
**********************************************************************************************************************/
fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl,
void ( * p_callback)(
external_irq_callback_args_t *),
void const * const p_context,
external_irq_callback_args_t * const p_callback_memory)
{
icu_instance_ctrl_t * p_ctrl = p_api_ctrl;
#if BSP_TZ_SECURE_BUILD
/* cmse_check_address_range returns NULL if p_callback is located in secure memory */
bool callback_is_secure =
(NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
#else
FSP_PARAMETER_NOT_USED(p_callback_memory);
#endif
#if ICU_CFG_PARAM_CHECKING_ENABLE
FSP_ASSERT(NULL != p_ctrl);
FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_callback);
#if BSP_TZ_SECURE_BUILD
/* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
external_irq_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
CMSE_AU_NONSECURE);
FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
#endif
#endif
#if BSP_TZ_SECURE_BUILD
p_ctrl->p_callback_memory = p_callback_memory;
p_ctrl->p_callback = callback_is_secure ? p_callback :
(void (*)(external_irq_callback_args_t *))cmse_nsfptr_create(p_callback);
#else
p_ctrl->p_callback = p_callback;
#endif
p_ctrl->p_context = p_context;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Close the external interrupt channel. Implements @ref external_irq_api_t::close.
*
* @retval FSP_SUCCESS Successfully closed.
* @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL.
* @retval FSP_ERR_NOT_OPEN The channel is not opened.
**********************************************************************************************************************/
fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl)
{
icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
#if ICU_CFG_PARAM_CHECKING_ENABLE
FSP_ASSERT(NULL != p_ctrl);
FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
#endif
/* Cleanup. Disable interrupt */
if (p_ctrl->irq >= 0)
{
/* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
R_BSP_IrqDisable(p_ctrl->irq);
R_FSP_IsrContextSet(p_ctrl->irq, NULL);
}
p_ctrl->open = 0U;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* @} (end addtogroup ICU)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* ICU External Interrupt ISR.
**********************************************************************************************************************/
void r_icu_isr (void)
{
/* Save context if RTOS is used */
FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
bool level_irq = false;
if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD)
{
level_irq = true;
}
else
{
/* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active
* it will not be missed. */
R_BSP_IrqStatusClear(irq);
}
if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback))
{
#if BSP_TZ_SECURE_BUILD
/* p_callback can point to a secure function or a non-secure function. */
external_irq_callback_args_t args;
if (!cmse_is_nsfptr(p_ctrl->p_callback))
{
/* If p_callback is secure, then the project does not need to change security state. */
args.channel = p_ctrl->channel;
args.p_context = p_ctrl->p_context;
p_ctrl->p_callback(&args);
}
else
{
/* Save current state of p_callback_args so that it can be shared between interrupts. */
args = *p_ctrl->p_callback_memory;
/* Set the callback args passed to the Non-secure calback. */
p_ctrl->p_callback_memory->channel = p_ctrl->channel;
p_ctrl->p_callback_memory->p_context = p_ctrl->p_context;
/* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
icu_prv_ns_callback p_callback = (icu_prv_ns_callback) (p_ctrl->p_callback);
p_callback(p_ctrl->p_callback_memory);
/* Restore the state of p_callback_args. */
*p_ctrl->p_callback_memory = args;
}
#else
/* Set data to identify callback to user, then call user callback. */
external_irq_callback_args_t args;
args.channel = p_ctrl->channel;
args.p_context = p_ctrl->p_context;
p_ctrl->p_callback(&args);
#endif
}
if (level_irq)
{
/* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not
* be called again. */
R_BSP_IrqStatusClear(irq);
}
/* Restore context if RTOS is used */
FSP_CONTEXT_RESTORE
}

5
bsp/renesas/ra2l1-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h
View File

@@ -1,5 +0,0 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

29
bsp/renesas/ra2l1-cpk/ra_gen/hal_data.c
View File

@@ -1,34 +1,5 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
icu_instance_ctrl_t g_external_irq3_ctrl;
const external_irq_cfg_t g_external_irq3_cfg =
{
.channel = 3,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = irq_callback,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = NULL,
.ipl = (2),
#if defined(VECTOR_NUMBER_ICU_IRQ3)
.irq = VECTOR_NUMBER_ICU_IRQ3,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq3 =
{
.p_ctrl = &g_external_irq3_ctrl,
.p_cfg = &g_external_irq3_cfg,
.p_api = &g_external_irq_on_icu
};
sci_uart_instance_ctrl_t g_uart9_ctrl;
baud_setting_t g_uart9_baud_setting =

12
bsp/renesas/ra2l1-cpk/ra_gen/hal_data.h
View File

@@ -4,21 +4,9 @@
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq3;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq3_ctrl;
extern const external_irq_cfg_t g_external_irq3_cfg;
#ifndef irq_callback
void irq_callback(external_irq_callback_args_t * p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart9;

4
bsp/renesas/ra2l1-cpk/ra_gen/vector_data.c
View File

@@ -4,15 +4,13 @@
#if VECTOR_DATA_IRQ_COUNT > 0
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
{
[3] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */
[4] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
[4] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
[5] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
[6] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
[7] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
[3] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */
[4] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */
[5] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
[6] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */

5
bsp/renesas/ra2l1-cpk/ra_gen/vector_data.h
View File

@@ -3,18 +3,15 @@
#define VECTOR_DATA_H
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (5)
#define VECTOR_DATA_IRQ_COUNT (4)
#endif
/* ISR prototypes */
void r_icu_isr(void);
void sci_uart_rxi_isr(void);
void sci_uart_txi_isr(void);
void sci_uart_tei_isr(void);
void sci_uart_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type) 3) /* ICU IRQ3 (External pin interrupt 3) */
#define ICU_IRQ3_IRQn ((IRQn_Type) 3) /* ICU IRQ3 (External pin interrupt 3) */
#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */
#define SCI9_RXI_IRQn ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */
#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 5) /* SCI9 TXI (Transmit data empty) */

17
bsp/renesas/ra2l1-cpk/rtconfig.h
View File

@@ -145,12 +145,6 @@
/* CYW43012 WiFi */
/* BL808 WiFi */
/* CYW43439 WiFi */
/* IoT Cloud */
@@ -192,20 +186,15 @@
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */

100
bsp/renesas/ra4m2-eco/.config
View File

@@ -160,13 +160,7 @@ CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@@ -299,16 +293,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CYW43012 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43012 is not set
#
# BL808 WiFi
#
# CONFIG_PKG_USING_WLAN_BL808 is not set
#
# CYW43439 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43439 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
@@ -330,6 +314,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -351,7 +336,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_BT_CYW43012 is not set
# CONFIG_PKG_USING_CYW43XX is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
@@ -372,7 +356,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
# CONFIG_PKG_USING_LHC_MODBUS is not set
#
# security packages
@@ -519,9 +502,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_CORE is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
# CONFIG_PKG_USING_CMSIS_NN is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
@@ -541,8 +521,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FILEX is not set
# CONFIG_PKG_USING_LEVELX is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@@ -580,35 +558,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_SFDB is not set
# CONFIG_PKG_USING_RTP is not set
# CONFIG_PKG_USING_REB is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
#
# peripheral libraries and drivers
#
#
# HAL & SDK Drivers
#
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
#
# sensors drivers
#
@@ -690,8 +644,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_CST812T is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@@ -699,6 +654,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -713,6 +676,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
@@ -735,6 +699,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
@@ -744,6 +709,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -751,6 +717,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
@@ -759,9 +726,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ST7789 is not set
# CONFIG_PKG_USING_VS1003 is not set
# CONFIG_PKG_USING_X9555 is not set
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
@@ -776,7 +740,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
#
# Signal Processing and Control Algorithm Packages
@@ -786,6 +749,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
#
# miscellaneous packages
@@ -861,9 +825,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@@ -871,13 +833,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -922,7 +884,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -961,6 +923,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -983,7 +946,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -991,7 +954,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -1004,7 +967,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
#
# Display
@@ -1030,7 +992,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
#
# Data Storage
@@ -1047,11 +1008,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
@@ -1074,6 +1035,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# Uncategorized
#
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
CONFIG_SOC_FAMILY_RENESAS=y
# CONFIG_SOC_SERIES_R7FA6M3 is not set
# CONFIG_SOC_SERIES_R7FA6M4 is not set
@@ -1081,6 +1043,7 @@ CONFIG_SOC_FAMILY_RENESAS=y
# CONFIG_SOC_SERIES_R7FA6M5 is not set
CONFIG_SOC_SERIES_R7FA4M2=y
# CONFIG_SOC_SERIES_R7FA8M85 is not set
# CONFIG_SOC_SERIES_R9A07G0 is not set
#
# Hardware Drivers Config
@@ -1090,6 +1053,7 @@ CONFIG_SOC_R7FA4M2AD=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_FS is not set
#
# On-chip Peripheral Drivers
@@ -1114,13 +1078,7 @@ CONFIG_BSP_UART4_RX_BUFSIZE=256
CONFIG_BSP_UART4_TX_BUFSIZE=0
# CONFIG_BSP_USING_UART9 is not set
# CONFIG_BSP_USING_SPI is not set
CONFIG_BSP_USING_SCI_SPI=y
# CONFIG_BSP_USING_SCI_SPI0 is not set
# CONFIG_BSP_USING_SCI_SPI1 is not set
# CONFIG_BSP_USING_SCI_SPI2 is not set
# CONFIG_BSP_USING_SCI_SPI3 is not set
# CONFIG_BSP_USING_SCI_SPI4 is not set
CONFIG_BSP_USING_SCI_SPI9=y
# CONFIG_BSP_USING_SCI is not set
#
# Board extended module Drivers

5
bsp/renesas/ra4m2-eco/.secure_azone
View File

@@ -22,7 +22,6 @@
</peripheral>
<peripheral name="SCI0" group="SCI" security=""/>
<peripheral name="SCI4" group="SCI" security=""/>
<peripheral name="SCI9" group="SCI" security=""/>
<peripheral name="ICU">
<slot name="IRQ0" secure="false"/>
<slot name="IRQ1" secure="false"/>
@@ -32,10 +31,6 @@
<slot name="IRQ5" secure="false"/>
<slot name="IRQ6" secure="false"/>
<slot name="IRQ7" secure="false"/>
<slot name="IRQ8" secure="false"/>
<slot name="IRQ9" secure="false"/>
<slot name="IRQ10" secure="false"/>
<slot name="IRQ11" secure="false"/>
</peripheral>
</partition>
</azone>

2
bsp/renesas/ra4m2-eco/.secure_xml
View File

@@ -9,7 +9,7 @@
<option key="#DeviceCommand#" value="R7FA4M2AD"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA4M2AD3CFP.pincfg"/>
<option key="#FSPVersion#" value="4.1.0"/>
<option key="#FSPVersion#" value="4.2.0"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raClockConfiguration>

43
bsp/renesas/ra4m2-eco/.settings/standalone.prefs
View File

@@ -1,28 +1,23 @@
#Wed Dec 07 23:22:04 CST 2022
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.1.0/all=3347489174,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.1.0/all=500387124,ra/fsp/src/r_ioport/r_ioport.c|2537229576,ra/fsp/inc/api/r_ioport_api.h|2490905981,ra/fsp/inc/instances/r_ioport.h
com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=true
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.1.0/all=3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.1.0/all=545907899,ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h|2766481316,ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h|1942810345,ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_sci_spi.342272802=false
#Mon Apr 15 16:00:07 CST 2024
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.788093718=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.1.0/all=2970687511,ra/fsp/inc/api/r_transfer_api.h|428353588,ra/fsp/inc/instances/r_dtc.h|1071048478,ra/fsp/src/r_dtc/r_dtc.c
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.1.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.1.0/all=3958601320,ra/fsp/inc/instances/r_sci_uart.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|134969800,ra/fsp/inc/api/r_uart_api.h|2640391634,ra/fsp/src/r_sci_uart/r_sci_uart.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.2.0/all=3710703039,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.2.0/all=2490905981,ra/fsp/inc/instances/r_ioport.h|500387124,ra/fsp/src/r_ioport/r_ioport.c|3837163319,ra/fsp/inc/api/r_ioport_api.h
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.1.0/all=2999473418,ra/fsp/src/r_sci_spi/r_sci_spi.c|2970687511,ra/fsp/inc/api/r_transfer_api.h|2516469150,ra/fsp/inc/api/r_spi_api.h|57267461,ra/fsp/inc/instances/r_sci_spi.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.1.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.1.0/all=2136566490,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1564775820,ra/fsp/src/bsp/mcu/all/bsp_security.h|2222043441,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1844233273,ra/fsp/src/bsp/mcu/all/bsp_common.c|1844682318,ra/fsp/src/bsp/mcu/all/bsp_io.h|502753616,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2635614327,ra/fsp/src/bsp/mcu/all/bsp_security.c|2537229576,ra/fsp/inc/api/r_ioport_api.h|1799272679,ra/fsp/inc/fsp_features.h|805765460,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2015535075,ra/fsp/inc/fsp_common_api.h|2461896614,ra/fsp/src/bsp/mcu/all/bsp_io.c|175812246,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2854226690,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|29339077,ra/fsp/inc/fsp_version.h|547852917,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|604332916,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2074918554,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|371081032,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1303542530,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|571584658,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2922574965,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2906265047,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1218854983,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3954882015,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|715820739,ra/fsp/inc/api/bsp_api.h|539993079,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1374997543,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3748852695,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2294599662,ra/fsp/src/bsp/mcu/all/bsp_common.h|3035603422,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2644177141,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2273123320,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2490905981,ra/fsp/inc/instances/r_ioport.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.2.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.2.0/all=134969800,ra/fsp/inc/api/r_uart_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|2640391634,ra/fsp/src/r_sci_uart/r_sci_uart.c|3958601320,ra/fsp/inc/instances/r_sci_uart.h
com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=true
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.2.0/all=1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.2.0/all=547852917,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1234378052,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1564775820,ra/fsp/src/bsp/mcu/all/bsp_security.h|816208395,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|502753616,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1623877800,ra/fsp/src/bsp/mcu/all/bsp_security.c|2973649161,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2136566490,ra/fsp/src/bsp/mcu/all/bsp_guard.h|2490905981,ra/fsp/inc/instances/r_ioport.h|2294599662,ra/fsp/src/bsp/mcu/all/bsp_common.h|1303542530,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2854226690,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2906265047,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|76443894,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|539993079,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1799272679,ra/fsp/inc/fsp_features.h|3837163319,ra/fsp/inc/api/r_ioport_api.h|270846514,ra/fsp/inc/fsp_version.h|1218854983,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1844682318,ra/fsp/src/bsp/mcu/all/bsp_io.h|2922574965,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2461896614,ra/fsp/src/bsp/mcu/all/bsp_io.c|371081032,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|175812246,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2273123320,ra/fsp/src/bsp/mcu/all/bsp_guard.c|604332916,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1844233273,ra/fsp/src/bsp/mcu/all/bsp_common.c|715820739,ra/fsp/inc/api/bsp_api.h|2222043441,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2795027356,ra/fsp/inc/fsp_common_api.h|805765460,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3748852695,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3035603422,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2644177141,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.2.0/all=1942810345,ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h|1974362915,ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h|2766481316,ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1802976382=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.2.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.2.0/all=

394
bsp/renesas/ra4m2-eco/board/Kconfig
View File

@@ -9,6 +9,20 @@ menu "Hardware Drivers Config"
menu "Onboard Peripheral Drivers"
menuconfig BSP_USING_FS
bool "Enable filesystem"
default n
if BSP_USING_FS
config BSP_USING_SPICARD_FS
bool "Enable SPI FLASH filesystem"
select BSP_USING_SCI
select BSP_USING_SCI9
select BSP_USING_SCI9_SPI
select RT_USING_SPI_MSD
select RT_USING_DFS_ELMFAT
default n
endif
endmenu
menu "On-chip Peripheral Drivers"
@@ -185,46 +199,358 @@ menu "Hardware Drivers Config"
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
menuconfig BSP_USING_SPI
bool "Enable SPI"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
endif
menuconfig BSP_USING_SCI
bool "Enable SCI Controller"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SCIn_SPI
bool
depends on BSP_USING_SCI
select RT_USING_SPI
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
config BSP_USING_SCIn_I2C
bool
depends on BSP_USING_SCI
select RT_USING_I2C
default n
config BSP_USING_SCIn_UART
bool
depends on BSP_USING_SCI
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
default n
if BSP_USING_SCI
config BSP_USING_SCI0
bool "Enable SCI0"
default n
if BSP_USING_SCI0
choice
prompt "choice sci mode"
default BSP_USING_SCI0_SPI
config BSP_USING_SCI0_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI0_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI0_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI0_UART
config BSP_SCI0_UART_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI0_UART_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI1
bool "Enable SCI1"
default n
if BSP_USING_SCI1
choice
prompt "choice sci mode"
default BSP_USING_SCI1_SPI
config BSP_USING_SCI1_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI1_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI1_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI1_UART
config BSP_SCI1_UART_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI1_UART_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI2
bool "Enable SCI2"
default n
if BSP_USING_SCI2
choice
prompt "choice sci mode"
default BSP_USING_SCI2_SPI
config BSP_USING_SCI2_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI2_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI2_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI2_UART
config BSP_SCI2_UART_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI2_UART_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI3
bool "Enable SCI3"
default n
if BSP_USING_SCI3
choice
prompt "choice sci mode"
default BSP_USING_SCI3_SPI
config BSP_USING_SCI3_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI3_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI3_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI3_UART
config BSP_SCI3_UART_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI3_UART_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI4
bool "Enable SCI4"
default n
if BSP_USING_SCI4
choice
prompt "choice sci mode"
default BSP_USING_SCI4_SPI
config BSP_USING_SCI4_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI4_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI4_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI4_UART
config BSP_SCI4_UART_RX_BUFSIZE
int "Set UART4 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI4_UART_TX_BUFSIZE
int "Set UART4 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI5
bool "Enable SCI5"
default n
if BSP_USING_SCI5
choice
prompt "choice sci mode"
default BSP_USING_SCI5_SPI
config BSP_USING_SCI5_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI5_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI5_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI5_UART
config BSP_SCI5_UART_RX_BUFSIZE
int "Set UART5 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI5_UART_TX_BUFSIZE
int "Set UART5 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI6
bool "Enable SCI6"
default n
if BSP_USING_SCI6
choice
prompt "choice sci mode"
default BSP_USING_SCI6_SPI
config BSP_USING_SCI6_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI6_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI6_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI6_UART
config BSP_SCI6_UART_RX_BUFSIZE
int "Set UART6 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI6_UART_TX_BUFSIZE
int "Set UART6 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI7
bool "Enable SCI7"
default n
if BSP_USING_SCI7
choice
prompt "choice sci mode"
default BSP_USING_SCI7_SPI
config BSP_USING_SCI7_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI7_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI7_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI7_UART
config BSP_SCI7_UART_RX_BUFSIZE
int "Set UART7 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI7_UART_TX_BUFSIZE
int "Set UART7 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI8
bool "Enable SCI8"
default n
if BSP_USING_SCI8
choice
prompt "choice sci mode"
default BSP_USING_SCI8_SPI
config BSP_USING_SCI8_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI8_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI8_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI8_UART
config BSP_SCI8_UART_RX_BUFSIZE
int "Set UART8 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI8_UART_TX_BUFSIZE
int "Set UART8 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI9
bool "Enable SCI9"
default n
if BSP_USING_SCI9
choice
prompt "choice sci mode"
default BSP_USING_SCI9_SPI
config BSP_USING_SCI9_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI9_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI9_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI9_UART
config BSP_SCI9_UART_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI9_UART_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
endif
endmenu
menuconfig BSP_USING_SCI_SPI
bool "Enable SCI SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SCI_SPI
config BSP_USING_SCI_SPI0
bool "Enable SCI SPI0 BUS"
default n
config BSP_USING_SCI_SPI1
bool "Enable SCI SPI1 BUS"
default n
config BSP_USING_SCI_SPI2
bool "Enable SCI SPI2 BUS"
default n
config BSP_USING_SCI_SPI3
bool "Enable SCI SPI3 BUS"
default n
config BSP_USING_SCI_SPI4
bool "Enable SCI SPI4 BUS"
default n
config BSP_USING_SCI_SPI9
bool "Enable SCI SPI9 BUS"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

38
bsp/renesas/ra4m2-eco/board/ports/mnt.c Normal file
View File

@@ -0,0 +1,38 @@
#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_FS
#include <dfs_fs.h>
#include <spi_msd.h>
#include "drv_sci.h"
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void)
{
uint32_t cs_pin = BSP_IO_PORT_06_PIN_03;
rt_hw_sci_spi_device_attach("sci9s", "scpi90", cs_pin);
msd_init("sd0", "scpi90");
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
return 0;
}
int mount_init(void)
{
sd_mount();
return RT_EOK;
}
INIT_ENV_EXPORT(mount_init);
#endif /* BSP_USING_FS */

26
bsp/renesas/ra4m2-eco/buildinfo.gpdsc
View File

@@ -11,7 +11,7 @@
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.cpp"/>
<file category="source" name="src/hal_entry.c"/>
</project_files>
</generator>
</generators>
@@ -55,53 +55,65 @@
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_spi_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_dtc.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_spi.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h" path=""/>
<file category="source" name="ra/fsp/src/r_dtc/r_dtc.c"/>
<file category="other" name="ra/fsp/src/r_dtc/r_dtc.o"/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="source" name="ra/fsp/src/r_sci_spi/r_sci_spi.c"/>
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
<file category="other" name="ra/fsp/src/r_sci_spi/r_sci_spi.o"/>
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
<file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
@@ -115,9 +127,7 @@
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_dtc_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_spi_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>

110
bsp/renesas/ra4m2-eco/configuration.xml
View File

@@ -9,7 +9,7 @@
<option key="#DeviceCommand#" value="R7FA4M2AD"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA4M2AD3CFP.pincfg"/>
<option key="#FSPVersion#" value="4.1.0"/>
<option key="#FSPVersion#" value="4.2.0"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration>
@@ -123,45 +123,37 @@
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="4.1.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.4.1.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="4.1.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.4.1.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.9.0+renesas.0.fsp.4.1.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.9.0+renesas.0.fsp.4.1.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="R7FA4M2AD3CFP" vendor="Renesas" version="4.1.0">
<component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="R7FA4M2AD3CFP" vendor="Renesas" version="4.2.0">
<description>Board support package for R7FA4M2AD3CFP</description>
<originalPack>Renesas.RA_mcu_ra4m2.4.1.0.pack</originalPack>
<originalPack>Renesas.RA_mcu_ra4m2.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="" vendor="Renesas" version="4.1.0">
<component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="device" variant="" vendor="Renesas" version="4.2.0">
<description>Board support package for RA4M2</description>
<originalPack>Renesas.RA_mcu_ra4m2.4.1.0.pack</originalPack>
<originalPack>Renesas.RA_mcu_ra4m2.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="fsp" variant="" vendor="Renesas" version="4.1.0">
<component apiversion="" class="BSP" condition="" group="ra4m2" subgroup="fsp" variant="" vendor="Renesas" version="4.2.0">
<description>Board support package for RA4M2 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra4m2.4.1.0.pack</originalPack>
<originalPack>Renesas.RA_mcu_ra4m2.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="4.1.0">
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.9.0+renesas.0.fsp.4.2.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.9.0+renesas.0.fsp.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="4.2.0">
<description>Custom Board Support Files</description>
<originalPack>Renesas.RA_board_custom.4.1.0.pack</originalPack>
<originalPack>Renesas.RA_board_custom.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="4.1.0">
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="4.2.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="4.2.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.4.2.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="4.2.0">
<description>SCI UART</description>
<originalPack>Renesas.RA.4.1.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_dtc" variant="" vendor="Renesas" version="4.1.0">
<description>Data Transfer Controller</description>
<originalPack>Renesas.RA.4.1.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_spi" variant="" vendor="Renesas" version="4.1.0">
<description>Serial Peripheral Interface on Serial Communications Interface</description>
<originalPack>Renesas.RA.4.1.0.pack</originalPack>
<originalPack>Renesas.RA.4.2.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
@@ -227,70 +219,14 @@
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
</module>
<module id="module.driver.spi_on_sci_spi.342272802">
<property id="module.driver.spi.name" value="g_sci_spi9"/>
<property id="module.driver.spi.channel" value="9"/>
<property id="module.driver.spi.operating_mode" value="module.driver.spi.operating_mode.mode_master"/>
<property id="module.driver.spi.clk_phase" value="module.driver.spi.clk_phase.clk_phase_edge_odd"/>
<property id="module.driver.spi.clk_polarity" value="module.driver.spi.clk_polarity.clk_polarity_low"/>
<property id="module.driver.spi.mode_fault" value="module.driver.spi.mode_fault.mode_fault_error_disable"/>
<property id="module.driver.spi.bit_order" value="module.driver.spi.bit_order.bit_order_msb_first"/>
<property id="module.driver.spi.p_callback" value="sci_spi9_callback"/>
<property id="module.driver.spi.rxi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.spi.txi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.spi.tei_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.spi.eri_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.spi.bitrate" value="8000000"/>
<property id="module.driver.spi.bitrate_modulation" value="module.driver.spi.bitrate_modulation.disabled"/>
</module>
<module id="module.driver.transfer_on_dtc.351428579">
<property id="module.driver.transfer.name" value="g_transfer0"/>
<property id="module.driver.transfer.mode" value="module.driver.transfer.mode.mode_normal"/>
<property id="module.driver.transfer.size" value="module.driver.transfer.size.size_2_byte"/>
<property id="module.driver.transfer.dest_addr_mode" value="module.driver.transfer.dest_addr_mode.addr_mode_fixed"/>
<property id="module.driver.transfer.src_addr_mode" value="module.driver.transfer.src_addr_mode.addr_mode_fixed"/>
<property id="module.driver.transfer.repeat_area" value="module.driver.transfer.repeat_area.repeat_area_source"/>
<property id="module.driver.transfer.p_dest" value="NULL"/>
<property id="module.driver.transfer.p_src" value="NULL"/>
<property id="module.driver.transfer.interrupt" value="module.driver.transfer.interrupt.interrupt_end"/>
<property id="module.driver.transfer.length" value="0"/>
<property id="module.driver.transfer.num_blocks" value="0"/>
<property id="module.driver.transfer.activation_source" value="_disabled"/>
</module>
<module id="module.driver.transfer_on_dtc.2037472890">
<property id="module.driver.transfer.name" value="g_transfer1"/>
<property id="module.driver.transfer.mode" value="module.driver.transfer.mode.mode_normal"/>
<property id="module.driver.transfer.size" value="module.driver.transfer.size.size_2_byte"/>
<property id="module.driver.transfer.dest_addr_mode" value="module.driver.transfer.dest_addr_mode.addr_mode_fixed"/>
<property id="module.driver.transfer.src_addr_mode" value="module.driver.transfer.src_addr_mode.addr_mode_fixed"/>
<property id="module.driver.transfer.repeat_area" value="module.driver.transfer.repeat_area.repeat_area_source"/>
<property id="module.driver.transfer.p_dest" value="NULL"/>
<property id="module.driver.transfer.p_src" value="NULL"/>
<property id="module.driver.transfer.interrupt" value="module.driver.transfer.interrupt.interrupt_end"/>
<property id="module.driver.transfer.length" value="0"/>
<property id="module.driver.transfer.num_blocks" value="0"/>
<property id="module.driver.transfer.activation_source" value="_disabled"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.uart_on_sci_uart.1802976382"/>
<stack module="module.driver.uart_on_sci_uart.788093718"/>
<stack module="module.driver.spi_on_sci_spi.342272802">
<stack module="module.driver.transfer_on_dtc.351428579" requires="module.driver.spi_on_sci_spi.requires.transfer_tx"/>
<stack module="module.driver.transfer_on_dtc.2037472890" requires="module.driver.spi_on_sci_spi.requires.transfer_rx"/>
</stack>
</context>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
<config id="config.driver.sci_spi">
<property id="config.driver.sci_spi.param_checking_enable" value="config.driver.sci_spi.param_checking_enable.bsp"/>
<property id="config.driver.sci_spi.dtc_support_enable" value="config.driver.sci_spi.dtc_support_enable.enabled"/>
</config>
<config id="config.driver.dtc">
<property id="config.driver.dtc.param_checking_enable" value="config.driver.dtc.param_checking_enable.bsp"/>
<property id="config.driver.dtc.vector_table" value=".fsp_dtc_vector_table"/>
</config>
<config id="config.driver.sci_uart">
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>

6
bsp/renesas/ra4m2-eco/memory_regions.scat
View File

@@ -12,11 +12,11 @@
#define OPTION_SETTING_S_LENGTH 0x100
#define ID_CODE_START 0x00000000
#define ID_CODE_LENGTH 0x0
#define SDRAM_START 0x00000000
#define SDRAM_START 0x80010000
#define SDRAM_LENGTH 0x0
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x4000000
#define OSPI_DEVICE_0_START 0x00000000
#define OSPI_DEVICE_0_START 0x80020000
#define OSPI_DEVICE_0_LENGTH 0x0
#define OSPI_DEVICE_1_START 0x00000000
#define OSPI_DEVICE_1_START 0x80030000
#define OSPI_DEVICE_1_LENGTH 0x0

121
bsp/renesas/ra4m2-eco/project.uvprojx
View File

@@ -334,9 +334,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
<Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Define>__RTTHREAD__, RT_USING_ARMLIBC, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, RT_USING_LIBC</Define>
<Undefine />
<IncludePath>..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\libraries\HAL_Drivers;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\dfs\dfs_v1\filesystems\devfs;board\ports;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;.;board;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\libc\posix\ipc</IncludePath>
<IncludePath>..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\epoll;..\libraries\HAL_Drivers\config;board\ports;..\libraries\HAL_Drivers;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\libcpu\arm\common;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;board;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\ipc;.;..\..\..\components\dfs\dfs_v1\filesystems\devfs</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -476,6 +476,25 @@
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>condvar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\condvar.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> </MiscControls>
<Define>__RT_IPC_SOURCE__</Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
@@ -628,63 +647,6 @@
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>spi_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> </MiscControls>
<Define>__RT_IPC_SOURCE__</Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>spi_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> </MiscControls>
<Define>__RT_IPC_SOURCE__</Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>spi_msd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_msd.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> </MiscControls>
<Define>__RT_IPC_SOURCE__</Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
@@ -726,25 +688,6 @@
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>drv_sci_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_sci_spi.c</FilePath>
<FileOption>
<FileArmAds>
<Cads>
<VariousControls>
<MiscControls> -std=c99</MiscControls>
<Define> </Define>
<Undefine> </Undefine>
<IncludePath> </IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
</Files>
<Files>
<File>
<FileName>drv_usart_v2.c</FileName>
@@ -807,16 +750,9 @@
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
@@ -828,9 +764,9 @@
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
@@ -840,6 +776,13 @@
<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>

6
bsp/renesas/ra4m2-eco/ra/fsp/inc/api/r_ioport_api.h
View File

@@ -69,6 +69,12 @@ typedef enum e_ioport_peripheral
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),

299
bsp/renesas/ra4m2-eco/ra/fsp/inc/api/r_spi_api.h
View File

@@ -1,299 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_SPI_API_H
#define R_SPI_API_H
/*****************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup SPI_API SPI Interface
* @brief Interface for SPI communications.
*
* @section SPI_API_SUMMARY Summary
* Provides a common interface for communication using the SPI Protocol.
*
* Implemented by:
* - @ref SPI
* - @ref SCI_SPI
*
* @{
********************************************************************************************************************/
/*********************************************************************************************************************
* Includes
********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "r_transfer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*********************************************************************************************************************
* Macro definitions
********************************************************************************************************************/
/*********************************************************************************************************************
* Typedef definitions
********************************************************************************************************************/
/** Data bit width */
typedef enum e_spi_bit_width
{
SPI_BIT_WIDTH_4_BITS = (3), ///< Data bit width is 4 bits (byte)
SPI_BIT_WIDTH_5_BITS = (4), ///< Data bit width is 5 bits (byte)
SPI_BIT_WIDTH_6_BITS = (5), ///< Data bit width is 6 bits (byte)
SPI_BIT_WIDTH_7_BITS = (6), ///< Data bit width is 7 bits (byte)
SPI_BIT_WIDTH_8_BITS = (7), ///< Data bit width is 8 bits (byte)
SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits (word)
SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits (word)
SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits (word)
SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits (word)
SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits (word)
SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits (word)
SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits (word)
SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits (word)
SPI_BIT_WIDTH_17_BITS = (16), ///< Data bit width is 17 bits (word)
SPI_BIT_WIDTH_18_BITS = (17), ///< Data bit width is 18 bits (word)
SPI_BIT_WIDTH_19_BITS = (18), ///< Data bit width is 19 bits (word)
SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits (longword)
SPI_BIT_WIDTH_21_BITS = (20), ///< Data bit width is 21 bits (word)
SPI_BIT_WIDTH_22_BITS = (21), ///< Data bit width is 22 bits (word)
SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits (longword)
SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits (longword)
SPI_BIT_WIDTH_25_BITS = (25), ///< Data bit width is 25 bits (longword)
SPI_BIT_WIDTH_26_BITS = (25), ///< Data bit width is 26 bits (word)
SPI_BIT_WIDTH_27_BITS = (26), ///< Data bit width is 27 bits (word)
SPI_BIT_WIDTH_28_BITS = (27), ///< Data bit width is 28 bits (word)
SPI_BIT_WIDTH_29_BITS = (28), ///< Data bit width is 29 bits (word)
SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits (longword)
SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits (longword)
SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits (longword)
} spi_bit_width_t;
/** Master or slave operating mode */
typedef enum e_spi_mode
{
SPI_MODE_MASTER, ///< Channel operates as SPI master
SPI_MODE_SLAVE ///< Channel operates as SPI slave
} spi_mode_t;
/** Clock phase */
typedef enum e_spi_clk_phase
{
SPI_CLK_PHASE_EDGE_ODD, ///< 0: Data sampling on odd edge, data variation on even edge
SPI_CLK_PHASE_EDGE_EVEN ///< 1: Data variation on odd edge, data sampling on even edge
} spi_clk_phase_t;
/** Clock polarity */
typedef enum e_spi_clk_polarity
{
SPI_CLK_POLARITY_LOW, ///< 0: Clock polarity is low when idle
SPI_CLK_POLARITY_HIGH ///< 1: Clock polarity is high when idle
} spi_clk_polarity_t;
/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be
* controlled by the master. This usually happens when the connecting device is also acting as master.
* A similar situation can also happen when configured as a slave. */
typedef enum e_spi_mode_fault
{
SPI_MODE_FAULT_ERROR_ENABLE, ///< Mode fault error flag on
SPI_MODE_FAULT_ERROR_DISABLE ///< Mode fault error flag off
} spi_mode_fault_t;
/** Bit order */
typedef enum e_spi_bit_order
{
SPI_BIT_ORDER_MSB_FIRST, ///< Send MSB first in transmission
SPI_BIT_ORDER_LSB_FIRST ///< Send LSB first in transmission
} spi_bit_order_t;
/** SPI events */
typedef enum e_spi_event
{
SPI_EVENT_TRANSFER_COMPLETE = 1, ///< The data transfer was completed
SPI_EVENT_TRANSFER_ABORTED, ///< The data transfer was aborted
SPI_EVENT_ERR_MODE_FAULT, ///< Mode fault error
SPI_EVENT_ERR_READ_OVERFLOW, ///< Read overflow error
SPI_EVENT_ERR_PARITY, ///< Parity error
SPI_EVENT_ERR_OVERRUN, ///< Overrun error
SPI_EVENT_ERR_FRAMING, ///< Framing error
SPI_EVENT_ERR_MODE_UNDERRUN ///< Underrun error
} spi_event_t;
/** Common callback parameter definition */
typedef struct st_spi_callback_args
{
uint32_t channel; ///< Device channel number
spi_event_t event; ///< Event code
void const * p_context; ///< Context provided to user during callback
} spi_callback_args_t;
/** Non-secure arguments for write-read guard function */
typedef struct st_spi_write_read_guard_args
{
void const * p_src;
void * p_dest;
uint32_t const length;
spi_bit_width_t const bit_width;
} spi_write_read_guard_args_t;
/** SPI interface configuration */
typedef struct st_spi_cfg
{
uint8_t channel; ///< Channel number to be used
IRQn_Type rxi_irq; ///< Receive Buffer Full IRQ number
IRQn_Type txi_irq; ///< Transmit Buffer Empty IRQ number
IRQn_Type tei_irq; ///< Transfer Complete IRQ number
IRQn_Type eri_irq; ///< Error IRQ number
uint8_t rxi_ipl; ///< Receive Interrupt priority
uint8_t txi_ipl; ///< Transmit Interrupt priority
uint8_t tei_ipl; ///< Transfer Complete Interrupt priority
uint8_t eri_ipl; ///< Error Interrupt priority
spi_mode_t operating_mode; ///< Select master or slave operating mode
spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge
spi_clk_polarity_t clk_polarity; ///< Clock level when idle
spi_mode_fault_t mode_fault; ///< Mode fault error (master/slave conflict) flag
spi_bit_order_t bit_order; ///< Select to transmit MSB/LSB first
transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMA write transfer, link a DTC/DMA instance here. Set to NULL if unused.
transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMA read transfer, link a DTC/DMA instance here. Set to NULL if unused.
void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function
void const * p_context; ///< User defined context passed to callback function
void const * p_extend; ///< Extended SPI hardware dependent configuration
} spi_cfg_t;
/** SPI control block. Allocate an instance specific control block to pass into the SPI API calls.
* @par Implemented as
* - spi_instance_ctrl_t
* - spi_b_instance_ctrl_t
* - sci_spi_instance_ctrl_t
*/
typedef void spi_ctrl_t;
/** Shared Interface definition for SPI */
typedef struct st_spi_api
{
/** Initialize a channel for SPI communication mode.
* @par Implemented as
* - @ref R_SPI_Open()
* - @ref R_SPI_B_Open()
* - @ref R_SCI_SPI_Open()
*
* @param[in, out] p_ctrl Pointer to user-provided storage for the control block.
* @param[in] p_cfg Pointer to SPI configuration structure.
*/
fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg);
/** Receive data from a SPI device.
* @par Implemented as
* - @ref R_SPI_Read()
* - @ref R_SPI_B_Read()
* - @ref R_SCI_SPI_Read()
*
* @param[in] p_ctrl Pointer to the control block for the channel.
* @param[in] length Number of units of data to be transferred (unit size specified by the
* bit_width).
* @param[in] bit_width Data bit width to be transferred.
* @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI
* device. It is the responsibility of the caller to ensure that adequate space is available
* to hold the requested data count.
*/
fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length,
spi_bit_width_t const bit_width);
/** Transmit data to a SPI device.
* @par Implemented as
* - @ref R_SPI_Write()
* - @ref R_SPI_B_Write()
* - @ref R_SCI_SPI_Write()
*
* @param[in] p_ctrl Pointer to the control block for the channel.
* @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device.
* The argument must not be NULL.
* @param[in] length Number of units of data to be transferred (unit size specified by the
* bit_width).
* @param[in] bit_width Data bit width to be transferred.
*/
fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length,
spi_bit_width_t const bit_width);
/** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex).
* @par Implemented as
* - @ref R_SPI_WriteRead()
* - @ref R_SPI_B_WriteRead()
* - @ref R_SCI_SPI_WriteRead()
*
* @param[in] p_ctrl Pointer to the control block for the channel.
* @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device.
* The argument must not be NULL.
* @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI
* device. It is the responsibility of the caller to ensure that adequate space is available
* to hold the requested data count. The argument must not be NULL.
* @param[in] length Number of units of data to be transferred (unit size specified by the bit_width).
* @param[in] bit_width Data bit width to be transferred.
*/
fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length,
spi_bit_width_t const bit_width);
/**
* Specify callback function and optional context pointer and working memory pointer.
* @par Implemented as
* - @ref R_SPI_CallbackSet()
* - @ref R_SPI_B_CallbackSet()
* - @ref R_SCI_SPI_CallbackSet()
*
* @param[in] p_ctrl Pointer to the SPI control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *),
void const * const p_context, spi_callback_args_t * const p_callback_memory);
/** Remove power to the SPI channel designated by the handle and disable the associated interrupts.
* @par Implemented as
* - @ref R_SPI_Close()
* - @ref R_SPI_B_Close()
* - @ref R_SCI_SPI_Close()
*
* @param[in] p_ctrl Pointer to the control block for the channel.
*/
fsp_err_t (* close)(spi_ctrl_t * const p_ctrl);
} spi_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_spi_instance
{
spi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
spi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
spi_api_t const * p_api; ///< Pointer to the API structure for this instance
} spi_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
/*****************************************************************************************************************//**
* @} (end defgroup SPI_API)
********************************************************************************************************************/
#endif

11
bsp/renesas/ra4m2-eco/ra/fsp/inc/fsp_common_api.h
View File

@@ -297,6 +297,17 @@ typedef enum e_fsp_err
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.

6
bsp/renesas/ra4m2-eco/ra/fsp/inc/fsp_version.h
View File

@@ -45,7 +45,7 @@ extern "C" {
#define FSP_VERSION_MAJOR (4U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (1U)
#define FSP_VERSION_MINOR (2U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
@@ -54,10 +54,10 @@ extern "C" {
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("4.1.0")
#define FSP_VERSION_STRING ("4.2.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.1.0")
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.2.0")
/**********************************************************************************************************************
* Typedef definitions

106
bsp/renesas/ra4m2-eco/ra/fsp/inc/instances/r_dtc.h
View File

@@ -1,106 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup DTC
* @{
**********************************************************************************************************************/
#ifndef R_DTC_H
#define R_DTC_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_transfer_api.h"
#include "r_dtc_cfg.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** Max configurable number of transfers in NORMAL MODE */
#define DTC_MAX_NORMAL_TRANSFER_LENGTH (0x10000)
/** Max number of transfers per repeat for REPEAT MODE */
#define DTC_MAX_REPEAT_TRANSFER_LENGTH (0x100)
/** Max number of transfers per block in BLOCK MODE */
#define DTC_MAX_BLOCK_TRANSFER_LENGTH (0x100)
/** Max configurable number of blocks to transfer in BLOCK MODE */
#define DTC_MAX_BLOCK_COUNT (0x10000)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** DTC transfer configuration extension. This extension is required. */
typedef struct st_dtc_extended_cfg
{
/** Select which IRQ will trigger the transfer. */
IRQn_Type activation_source;
} dtc_extended_cfg_t;
/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */
typedef struct st_dtc_instance_ctrl
{
uint32_t open; // Driver ID
IRQn_Type irq; // Transfer activation IRQ number.
} dtc_instance_ctrl_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const transfer_api_t g_transfer_on_dtc;
/** @endcond */
/**********************************************************************************************************************
* Public Function Prototypes
**********************************************************************************************************************/
fsp_err_t R_DTC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg);
fsp_err_t R_DTC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info);
fsp_err_t R_DTC_Reset(transfer_ctrl_t * const p_api_ctrl,
void const * volatile p_src,
void * volatile p_dest,
uint16_t const num_transfers);
fsp_err_t R_DTC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode);
fsp_err_t R_DTC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl);
fsp_err_t R_DTC_Enable(transfer_ctrl_t * const p_api_ctrl);
fsp_err_t R_DTC_Disable(transfer_ctrl_t * const p_api_ctrl);
fsp_err_t R_DTC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties);
fsp_err_t R_DTC_Close(transfer_ctrl_t * const p_api_ctrl);
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup DTC)
**********************************************************************************************************************/

120
bsp/renesas/ra4m2-eco/ra/fsp/inc/instances/r_sci_spi.h
View File

@@ -1,120 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_SCI_SPI_H
#define R_SCI_SPI_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "r_spi_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*****************************************************************************************************************//**
* @ingroup SCI_SPI
* @{
********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Settings for adjusting the SPI CLK. */
typedef struct
{
uint8_t brr;
uint8_t cks : 2;
uint8_t mddr; ///< Set to 0 to disable MDDR.
} sci_spi_div_setting_t;
/** SCI SPI extended configuration */
typedef struct st_sci_spi_extended_cfg
{
sci_spi_div_setting_t clk_div;
} sci_spi_extended_cfg_t;
/** SPI instance control block. DO NOT INITIALIZE. */
typedef struct st_sci_spi_instance_ctrl
{
uint32_t open;
spi_cfg_t const * p_cfg;
R_SCI0_Type * p_reg;
uint8_t * p_src;
uint8_t * p_dest;
uint32_t tx_count;
uint32_t rx_count;
uint32_t count;
/* Pointer to callback and optional working memory */
void (* p_callback)(spi_callback_args_t *);
spi_callback_args_t * p_callback_memory;
/* Pointer to context to be passed into callback function */
void const * p_context;
} sci_spi_instance_ctrl_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const spi_api_t g_spi_on_sci;
/** @endcond */
/**********************************************************************************************************************
* Public Function Prototypes
**********************************************************************************************************************/
fsp_err_t R_SCI_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg);
fsp_err_t R_SCI_SPI_Read(spi_ctrl_t * const p_api_ctrl,
void * p_dest,
uint32_t const length,
spi_bit_width_t const bit_width);
fsp_err_t R_SCI_SPI_Write(spi_ctrl_t * const p_api_ctrl,
void const * p_src,
uint32_t const length,
spi_bit_width_t const bit_width);
fsp_err_t R_SCI_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl,
void const * p_src,
void * p_dest,
uint32_t const length,
spi_bit_width_t const bit_width);
fsp_err_t R_SCI_SPI_Close(spi_ctrl_t * const p_api_ctrl);
fsp_err_t R_SCI_SPI_CalculateBitrate(uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr);
fsp_err_t R_SCI_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl,
void ( * p_callback)(spi_callback_args_t *),
void const * const p_context,
spi_callback_args_t * const p_callback_memory);
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end ingroup SCI_SPI)
**********************************************************************************************************************/

1031
bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
View File

File diff suppressed because it is too large Load Diff

51
bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
View File

@@ -116,7 +116,15 @@
#endif
#endif
#endif
#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ
#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB source clock by 1
#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB source clock by 2
#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB source clock by 3
#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB source clock by 4
#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB source clock by 5
#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB source clock by 6
#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB source clock by 8
#endif /* BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ*/
/* Choose the value to write to FLLCR2 (if applicable). */
#if BSP_PRV_HOCO_USE_FLL
#if 1U == BSP_CFG_HOCO_FREQUENCY
@@ -267,6 +275,24 @@
BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT) | \
(BSP_CFG_PLODIVP & BSP_PRV_PLLCCR2_PLL_DIV_MASK))
#endif
#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
#if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_PLL_SOURCE
#define BSP_PRV_PLL_USED (1)
#else
#define BSP_PRV_PLL_USED (0)
#endif
#define BSP_PRV_PLLCCR_PLLMUL_MASK (0xFFU) // PLLMUL is 8 bits wide
#define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL starts at bit 8
#define BSP_PRV_PLSET_MASK (0x01U) // PLSET is 1 bit wide
#define BSP_PRV_PLSET_BIT (6) // PLSET starts at bit 6
#define BSP_PRV_PLLCCR_RESET (0x0008U) // Bit 3 must be written as 1
#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
BSP_PRV_PLLCCR_PLLMUL_BIT) | \
((BSP_CFG_PLSET & BSP_PRV_PLSET_MASK) << \
BSP_PRV_PLSET_BIT) | \
BSP_PRV_PLLCCR_RESET
#endif
#endif
#if BSP_FEATURE_CGC_HAS_PLL2
@@ -338,13 +364,15 @@
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_CECCLK_SOURCE) && (BSP_CFG_CECCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
#define BSP_PRV_MAIN_OSC_USED (1)
@@ -352,7 +380,7 @@
#define BSP_PRV_MAIN_OSC_USED (0)
#endif
/* All clocks with configurable source can use HOCO except the I3CCLK. */
/* All clocks with configurable source can use HOCO except the CECCLK and I3CCLK. */
#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
#define BSP_PRV_HOCO_USED (1)
#define BSP_PRV_STABILIZE_HOCO (1)
@@ -383,7 +411,7 @@
#define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
#define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
#define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
#define BSP_PRV_HOCO_USED (1)
@@ -418,7 +446,7 @@
#define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
#define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
#define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
#define BSP_PRV_MOCO_USED (1)
@@ -476,8 +504,10 @@
(BSP_FEATURE_BSP_HAS_SPI_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
(BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED))
#define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (1U)
@@ -1132,6 +1162,8 @@ static void bsp_clock_freq_var_init (void)
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ;
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ;
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ;
#elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U;
#else
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >>
BSP_CFG_PLL_DIV;
@@ -1583,6 +1615,11 @@ void bsp_clock_init (void)
bsp_peripheral_clock_set(&R_SYSTEM->IICCKCR, &R_SYSTEM->IICCKDIVCR, BSP_CFG_IICCLK_DIV, BSP_CFG_IICCLK_SOURCE);
#endif
/* Set the CEC clock if it exists on the MCU */
#if BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
bsp_peripheral_clock_set(&R_SYSTEM->CECCKCR, &R_SYSTEM->CECCKDIVCR, BSP_CFG_CECCLK_DIV, BSP_CFG_CECCLK_SOURCE);
#endif
/* Set the I3C clock if it exists on the MCU */
#if BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
bsp_peripheral_clock_set(&R_SYSTEM->I3CCKCR, &R_SYSTEM->I3CCKDIVCR, BSP_CFG_I3CCLK_DIV, BSP_CFG_I3CCLK_SOURCE);
@@ -1599,8 +1636,8 @@ void bsp_clock_init (void)
#endif
/* Set the USB-HS clock if it exists on the MCU */
#if BSP_FEATURE_BSP_HAS_USBHS_CLOCK && (BSP_CFG_UHSCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
bsp_peripheral_clock_set(&R_SYSTEM->USBHSCKCR, &R_SYSTEM->USBHSCKDIVCR, BSP_CFG_UHSCK_DIV, BSP_CFG_UHSCK_SOURCE);
#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, &R_SYSTEM->USB60CKDIVCR, BSP_CFG_U60CK_DIV, BSP_CFG_U60CK_SOURCE);
#endif
/* Lock CGC and LPM protection registers. */

29
bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
View File

@@ -61,7 +61,10 @@ FSP_HEADER
* - When the PLL only accepts the main oscillator as a source and XTAL is not used
*/
#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \
!((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
!((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \
(3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \
(4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \
!BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
#define BSP_PRV_PLL_SUPPORTED (1)
#if BSP_FEATURE_CGC_HAS_PLL2
#define BSP_PRV_PLL2_SUPPORTED (1)
@@ -169,14 +172,14 @@ FSP_HEADER
#define BSP_CLOCKS_USB_CLOCK_DIV_6 (3) // Divide USB source clock by 6
#define BSP_CLOCKS_USB_CLOCK_DIV_8 (4) // Divide USB source clock by 8
/* USBHS clock divider options. */
#define BSP_CLOCKS_USBHS_CLOCK_DIV_1 (0) // Divide USBHS source clock by 1
#define BSP_CLOCKS_USBHS_CLOCK_DIV_2 (1) // Divide USBHS source clock by 2
#define BSP_CLOCKS_USBHS_CLOCK_DIV_3 (5) // Divide USBHS source clock by 3
#define BSP_CLOCKS_USBHS_CLOCK_DIV_4 (2) // Divide USBHS source clock by 4
#define BSP_CLOCKS_USBHS_CLOCK_DIV_5 (6) // Divide USBHS source clock by 5
#define BSP_CLOCKS_USBHS_CLOCK_DIV_6 (3) // Divide USBHS source clock by 6
#define BSP_CLOCKS_USBHS_CLOCK_DIV_8 (4) // Divide USBHS source clock by 8
/* USB60 clock divider options. */
#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1
#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2
#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3
#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4
#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5
#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6
#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8
/* GLCD clock divider options. */
#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1
@@ -197,7 +200,9 @@ FSP_HEADER
/* CANFD clock divider options. */
#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1
#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2
#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3
#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4
#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5
#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6
#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8
@@ -242,6 +247,10 @@ FSP_HEADER
#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6
#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8
/* CEC clock divider options. */
#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1
#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2
/* I3C clock divider options. */
#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1
#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2
@@ -1044,6 +1053,8 @@ typedef enum e_cgc_pll_mul
CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33
CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50
CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66
CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00
CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00
} cgc_pll_mul_t;
/***********************************************************************************************************************

2
bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
View File

@@ -90,6 +90,8 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U);
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
#define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel));
#else
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));

54
bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
View File

@@ -62,6 +62,27 @@
#if !BSP_CFG_BOOT_IMAGE
#if BSP_FEATURE_BSP_HAS_OSIS_REG == 1
/** ID code definitions defined here. */
BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
{
BSP_CFG_ID_CODE_LONG_1,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_2,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_3,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_4
};
#endif
#if 33U != __CORTEX_M && 85U != __CORTEX_M // NOLINT(readability-magic-numbers)
/** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
@@ -84,23 +105,22 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION
(uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
};
/** ID code definitions defined here. */
BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
{
BSP_CFG_ID_CODE_LONG_1,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_2,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_3,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_4
};
#elif BSP_FEATURE_BSP_HAS_OSIS_REG == 1
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
BSP_CFG_ROM_REG_OFS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
BSP_ROM_REG_OFS1_SETTING;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
BSP_CFG_ROM_REG_BPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
BSP_CFG_ROM_REG_PBPS0;
#else /* CM33 parts */

32
bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/bsp_security.c
View File

@@ -55,37 +55,9 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
#endif
#if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD
#pragma section=".tz_flash_nsc_start"
#pragma section=".tz_ram_nsc_start"
#pragma section=".tz_ram_ns_start"
#pragma section=".tz_data_flash_ns_start"
#pragma section=".tz_sdram_ns_start"
#pragma section=".tz_qspi_flash_ns_start"
#pragma section=".tz_ospi_device_0_ns_start"
#pragma section=".tz_ospi_device_1_ns_start"
#pragma section=".tz_flash_ns_start"
/* &__tz_<REGION>_C is the address of the non-secure callable section. Must assign value to this variable or
* linker will give error. */
/* &__tz_<REGION>_N is the start address of the non-secure region. */
BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
BSP_DONT_REMOVE void * __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
BSP_DONT_REMOVE void * __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
BSP_DONT_REMOVE void * __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
#if BSP_FEATURE_SDRAM_START_ADDRESS
BSP_DONT_REMOVE void * __tz_SDRAM_N @".tz_sdram_ns_start";
#endif
BSP_DONT_REMOVE void * __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
#if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS
BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
#endif
#if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS
BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
#endif
extern void const * const __tz_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start");
#elif defined(__ARMCC_VERSION)
#if BSP_FEATURE_BSP_HAS_ITCM
extern const uint32_t Image$$__tz_ITCM_N$$Base;

Some files were not shown because too many files have changed in this diff Show More