Merge branch 'master' of https://github.com/RT-Thread/rt-thread

libcpu/risc-v/common/context_gcc.S

@@ -48,7 +48,7 @@ rt_hw_context_switch_to:
 
 #ifdef RT_USING_SMP
     mv   a0,   a1
-    jal  rt_cpus_lock_status_restore
+    call  rt_cpus_lock_status_restore
 #endif
     LOAD a0,   2 * REGBYTES(sp)
     csrw mstatus, a0
@@ -161,7 +161,7 @@ save_mpie:
 
 #ifdef RT_USING_SMP
     mv   a0,   a2
-    jal  rt_cpus_lock_status_restore
+    call  rt_cpus_lock_status_restore
 #endif /*RT_USING_SMP*/
 
     j rt_hw_context_switch_exit

libcpu/risc-v/k210/interrupt_gcc.S

@@ -119,7 +119,7 @@ trap_entry:
     mv  sp, s0
     mv  a0, s0
     call rt_scheduler_do_irq_switch
-    j   rt_hw_context_switch_exit
+    tail   rt_hw_context_switch_exit
 
 #else
 
@@ -143,4 +143,4 @@ trap_entry:
 #endif
 
 spurious_interrupt:
-    j rt_hw_context_switch_exit
+    tail rt_hw_context_switch_exit

libcpu/risc-v/k210/startup_gcc.S

@@ -116,18 +116,21 @@ _start:
 
   /* other cpu core, jump to cpu entry directly */
   bnez a0, secondary_cpu_entry
-  j primary_cpu_entry
+  tail primary_cpu_entry
 
 secondary_cpu_entry:
 #ifdef RT_USING_SMP
   la a0, secondary_boot_flag
   ld a0, 0(a0)
   li a1, 0xa55a
-  beq a0, a1, secondary_cpu_c_start
+  beq a0, a1, 1f
 #endif
   j secondary_cpu_entry
 
 #ifdef RT_USING_SMP
+1:
+  tail secondary_cpu_c_start
+
 .data
 .global secondary_boot_flag
 .align 3