Merge branch 'master' of https://github.com/RT-Thread/rt-thread

2026-10-07 00:59:00 +08:00 · 2020-12-07 09:44:37 +08:00
parent 7258328923 cc9374f052
commit 1af5b72a99
161 changed files with 26397 additions and 1266 deletions
@@ -1,145 +0,0 @@
-language: c
-
-notifications:
-  email: false
-
-before_script:
-# travis has changed to 64-bit and we require 32-bit compatibility libraries
-  - sudo apt-get update
-  # clang
-  - "sudo apt-get -qq install gcc-multilib libc6:i386 libgcc1:i386 libstdc++5:i386 libstdc++6:i386 libsdl-dev scons || true"
-  # - sudo apt-get -qq install gcc-arm-none-eabi
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && export RTT_EXEC_PATH=/usr/bin && arm-none-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2014.05-28-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2014.05/bin && /opt/arm-2014.05/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 && sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin && /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 && sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/mips-2016.05/bin && /opt/mips-2016.05/bin/mips-sde-elf-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
-  - export RTT_ROOT=`pwd`
-  - "[ x$RTT_CC == x ] && export RTT_CC='gcc' || true"
-
-env:
-#  - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
-  - RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
-#  - RTT_BSP='bf533' # no scons
-  - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='es32f0334' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-#  - RTT_BSP='es32f0654' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-  - RTT_BSP='gd32e230k-start' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gd32303e-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-atk-commander' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-fire-pro' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-nxp-evk' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='tm4c123bsp' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc1114' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc824' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-  - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc5410x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc54114-lite' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
-#  - RTT_BSP='m16c62p' # m32c
-  - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='microblaze' # no scons
-  - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='mini4020' # no scons
-#  - RTT_BSP='mm32l07x' # not support gcc
-#  - RTT_BSP='nios_ii' # no scons
-#  - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='pic32ethernet' # no scons
-  - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='simulator' # x86
-  - RTT_BSP='stm32/stm32f072-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-dofly-M3S' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-onenet-nbiot' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-yf-ufun' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f410-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f411-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f411-weact-MiniF4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f413-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f427-robomaster-a' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f446-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f469-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f746-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g070-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g431-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h747-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l412-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l433-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l496-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32mp157a-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32mp157a-st-ev1' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32wb55-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
-#  - RTT_BSP='upd70f3454' # iar
-#  - RTT_BSP='x86' # x86
-  - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='at32/at32f403a-start' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='at32/at32f407-start' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='smartfusion2' RTT_TOOL_CHAIN='sourcery-arm'
-
-stage: compile
-script:
-  - scons -C bsp/$RTT_BSP
@@ -120,8 +120,8 @@ int rt_hw_uart_init(void)
        uart->irqno        = UART1_INTERRUPT; // IRQ_UART1;
        uart->gpio_rx_port = GPIO_PORT_A;
        uart->gpio_tx_port = GPIO_PORT_A;
-        uart->gpio_rx_pin  = GPIO_PIN_3;
-        uart->gpio_tx_pin  = GPIO_PIN_2;
+        uart->gpio_rx_pin  = GPIO_PIN_2;
+        uart->gpio_tx_pin  = GPIO_PIN_3;
        uart->gpio_rx_fun  = IO_FUN_4;
        uart->gpio_tx_fun  = IO_FUN_4;

@@ -12,8 +12,6 @@

 #ifdef RT_USING_ADC

-#define ADC_NAME "adc"
-
 struct rt_adc_device nrf5x_adc_device;

 drv_nrfx_saadc_result_t results;
@@ -16,6 +16,8 @@
 #include <hal/nrf_saadc.h>
 #include <drivers/include/nrfx_saadc.h>

+#define ADC_NAME "adc"
+
 /* 
    previous definition in application
    
@@ -14,7 +14,7 @@ CONFIG_RT_ALIGN_SIZE=4
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
 CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
@@ -54,6 +54,7 @@ CONFIG_RT_USING_MEMPOOL=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y

@@ -65,7 +66,7 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
 CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_ARMV8=y
@@ -141,14 +142,20 @@ CONFIG_RT_USING_DFS_DEVFS=y
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_SERIAL_USING_DMA=y
-CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_SERIAL_RB_BUFSZ=512
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
@@ -173,7 +180,7 @@ CONFIG_RT_USING_SPI=y
 CONFIG_RT_USING_WDT=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
-# CONFIG_RT_USING_TOUCH is not set
+CONFIG_RT_USING_TOUCH=y
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
@@ -204,7 +211,13 @@ CONFIG_RT_USING_POSIX=y
 #
 # Socket abstraction layer
 #
-# CONFIG_RT_USING_SAL is not set
+CONFIG_RT_USING_SAL=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y

 #
 # Network interface device
@@ -376,6 +389,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set

 #
 # security packages
@@ -402,6 +416,8 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
 # CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set

 #
 # tools packages
@@ -416,6 +432,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
@@ -423,6 +440,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_GPS_RMC is not set
 # CONFIG_PKG_USING_URLENCODE is not set
 # CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set

 #
 # system packages
@@ -449,7 +467,16 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_RAMDISK is not set
 # CONFIG_PKG_USING_MININI is not set
 # CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
 # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set

 #
@@ -505,6 +532,8 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_WK2124 is not set
 # CONFIG_PKG_USING_LY68L6400 is not set
 # CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set

 #
 # miscellaneous packages
@@ -534,6 +563,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_NNOM is not set
 # CONFIG_PKG_USING_LIBANN is not set
 # CONFIG_PKG_USING_ELAPACK is not set
@@ -542,8 +572,13 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
 # CONFIG_PKG_USING_THREES is not set
 # CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set

@@ -584,6 +619,9 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_DCM is not set
 # CONFIG_PKG_USING_EMQ is not set
 # CONFIG_PKG_USING_CFGM is not set
+# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
+# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set
+# CONFIG_PKG_USING_SMODULE is not set
 CONFIG_BCM2711_SOC=y
 # CONFIG_BSP_SUPPORT_FPU is not set

@@ -596,10 +634,10 @@ CONFIG_BCM2711_SOC=y
 #
 CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART0=y
-# CONFIG_RT_USING_UART1 is not set
+CONFIG_RT_USING_UART1=y
 CONFIG_RT_USING_UART3=y
-CONFIG_RT_USING_UART4=y
-# CONFIG_RT_USING_UART5 is not set
+# CONFIG_RT_USING_UART4 is not set
+CONFIG_RT_USING_UART5=y
 CONFIG_BSP_USING_GIC=y
 CONFIG_BSP_USING_GIC400=y
 # CONFIG_BSP_USING_GIC500 is not set
@@ -607,10 +645,19 @@ CONFIG_BSP_USING_PIN=y
 CONFIG_BSP_USING_SPI=y
 CONFIG_BSP_USING_SPI0_BUS=y
 CONFIG_BSP_USING_SPI0_DEVICE0=y
-# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
+CONFIG_BSP_USING_SPI0_DEVICE1=y
+CONFIG_BSP_USING_I2C=y
+# CONFIG_BSP_USING_I2C0 is not set
+# CONFIG_BSP_USING_I2C1 is not set
+CONFIG_BSP_USING_I2C3=y
+# CONFIG_BSP_USING_I2C4 is not set
+# CONFIG_BSP_USING_I2C5 is not set
+# CONFIG_BSP_USING_I2C6 is not set
 CONFIG_BSP_USING_CORETIMER=y
 # CONFIG_BSP_USING_SYSTIMER is not set
 CONFIG_BSP_USING_WDT=y
+CONFIG_BSP_USING_ETH=y
+# CONFIG_BSP_USING_BULETOOTH is not set
 # CONFIG_BSP_USING_RTC is not set
 CONFIG_BSP_USING_SDIO=y
 CONFIG_BSP_USING_SDIO0=y
@@ -618,5 +665,11 @@ CONFIG_BSP_USING_SDIO0=y
 #
 # Board Peripheral Drivers
 #
-CONFIG_BSP_USING_HDMI=y
-CONFIG_BSP_USING_HDMI_DISPLAY=y
+CONFIG_BSP_USING_LCD=y
+# CONFIG_BSP_USING_HDMI_DISPLAY is not set
+CONFIG_BSP_USING_DSI_DISPLAY=y
+# CONFIG_BSP_USING_ILI9486 is not set
+CONFIG_BSP_USING_TOUCH=y
+CONFIG_BSP_USING_DSI_TOUCH_DEV=y
+# CONFIG_BSP_USING_XPT_TOUCH_DEV is not set
+# CONFIG_USING_LCD_CONSOLE is not set
@@ -129,6 +129,12 @@ msh />
 | HDMI | 支持 | - |
 | SDIO | 支持 | - |
 | ETH | 支持 | - |
+| BSC | 支持 | - |
+| DMA | 支持 | - |
+| DSI LCD/TOUCH | 支持     | DSI接口的LCD和TOUCH |
+| ILI9486 SPI LCD | 支持 | - |
+| XPT2046 TOUCH | 支持     | - |
+| BULETOOTH | 正在完善 | 支持reset，loadfirmware |

 ## 5. 注意事项

@@ -50,7 +50,7 @@ menu "Hardware Drivers Config"
            select RT_USING_PIN
            default y

-            menuconfig BSP_USING_SPI
+        menuconfig BSP_USING_SPI
            bool "Enable SPI"
            select RT_USING_SPI
            default n
@@ -69,6 +69,32 @@ menu "Hardware Drivers Config"
                default n
        endif

+        menuconfig BSP_USING_I2C
+            bool "Enable I2C"
+            select RT_USING_I2C
+            default n
+
+        if BSP_USING_I2C   
+            config BSP_USING_I2C0
+                bool "Enable I2C0 BUS"
+                default n
+            config BSP_USING_I2C1
+                bool "Enable I2C1 BUS"
+                default n
+            config BSP_USING_I2C3
+                bool "Enable I2C3 BUS"
+                default n
+            config BSP_USING_I2C4
+                bool "Enable I2C4 BUS"
+                default n
+            config BSP_USING_I2C5
+                bool "Enable I2C5 BUS"
+                default n
+            config BSP_USING_I2C6
+                bool "Enable I2C6 BUS"
+                default n
+        endif
+
        config BSP_USING_CORETIMER
            bool "Using core timer"
            select RT_USING_CORETIMER
@@ -93,6 +119,14 @@ menu "Hardware Drivers Config"
            select RT_USING_WDT
            default n

+        config BSP_USING_ETH
+            bool "Enable ETH"
+            default n
+
+        config BSP_USING_BULETOOTH
+            bool "Enable BULETOOTH"
+            default n
+
        menuconfig BSP_USING_RTC
            bool "Enable RTC"
            select RT_USING_RTC
@@ -119,14 +153,37 @@ menu "Hardware Drivers Config"
    endmenu

    menu "Board Peripheral Drivers"
-        menuconfig BSP_USING_HDMI
-            bool "Enable HDMI"
+        menuconfig BSP_USING_LCD
+            bool "Enable LCD"
            default n

-        if BSP_USING_HDMI
+        if BSP_USING_LCD
            config BSP_USING_HDMI_DISPLAY
                bool "HDMI DISPLAY"
                default n
+            config BSP_USING_DSI_DISPLAY
+                bool "DSI DISPLAY"
+                default n
+            config BSP_USING_ILI9486
+                bool "ILI9486 DISPLAY"
+                default n
        endif
+
+        menuconfig BSP_USING_TOUCH
+            bool "Enable Touch"
+            default n
+
+        if BSP_USING_TOUCH
+            config BSP_USING_DSI_TOUCH_DEV
+                bool "DSI TOUCH"
+                default n
+            config BSP_USING_XPT_TOUCH_DEV
+                bool "XPT TOUCH"
+                default n
+        endif
+
+        config USING_LCD_CONSOLE
+            bool "LCD CONSOLE"
+            default n
    endmenu
 endmenu
@@ -1,9 +1,19 @@
+# RT-Thread building script for component
 from building import *

 cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.a')
 CPPPATH = [cwd, str(Dir('#'))]

+if not GetDepend('BSP_USING_ETH'):
+    SrcRemove(src, ['drv_eth.c'])
+if not GetDepend('BSP_USING_SPI'):
+    SrcRemove(src, ['drv_spi.c'])
+if not GetDepend('BSP_USING_WDT'):
+    SrcRemove(src, ['drv_wdt.c'])
+if not GetDepend('BSP_USING_BULETOOTH'):
+    SrcRemove(src, ['drv_bluetooth.c'])
+
 group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH)

 # build for sub-directory
@@ -16,13 +16,15 @@

 #include "cp15.h"
 #include "mmu.h"
+#include "mbox.h"

 struct mem_desc platform_mem_desc[] = {
    {0x0, 0x6400000, 0x0, NORMAL_MEM},
    {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM},    //mbox msg
-    {0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer
+    {0x0E000000, 0x0EE00000, 0x0E000000, DEVICE_MEM}, //framebuffer
+    {0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch 
    {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
-    {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral
+    {0xFE000000, 0xFF000000, 0xFE000000, DEVICE_MEM}, //peripheral
    {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM}  //gic
 };

@@ -36,21 +38,25 @@ void rt_hw_timer_isr(int vector, void *parameter)

 void rt_hw_timer_init(void)
 {
-    rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
-    rt_hw_interrupt_umask(ARM_TIMER_IRQ);
+    rt_uint32_t apb_clock = 0;
+    rt_uint32_t timer_clock = 1000000;
    /* timer_clock = apb_clock/(pre_divider + 1) */
-    ARM_TIMER_PREDIV = (250 - 1);
+    apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
+    ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);

    ARM_TIMER_RELOAD = 0;
    ARM_TIMER_LOAD   = 0;
    ARM_TIMER_IRQCLR = 0;
    ARM_TIMER_CTRL   = 0;

-    ARM_TIMER_RELOAD = 10000;
-    ARM_TIMER_LOAD   = 10000;
+    ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND;
+    ARM_TIMER_LOAD   = 1000000/RT_TICK_PER_SECOND;

    /* 23-bit counter, enable interrupt, enable timer */
    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+
+    rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(ARM_TIMER_IRQ);
 }

 void idle_wfi(void)
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-29     bigmagic       first version
+ */
+#ifndef __DRV_BT_H__
+#define __DRV_BT_H__
+
+#define     BT_HCI_COMMAND_PKT          (0x01)
+#define     BT_OGF_HOST_CONTROL         (0x03)
+#define     BT_OGF_LE_CONTROL           (0x08)
+#define     BT_OGF_VENDOR               (0x3f)
+#define     BT_COMMAND_SET_BDADDR       (0x01)
+#define     BT_COMMAND_RESET_CHIP       (0x03)
+#define     BT_COMMAND_SET_BAUD         (0x18)
+#define     BT_COMMAND_LOAD_FIRMWARE    (0x2e)
+#define     BT_HCI_ACL_PKT              (0x02)
+#define     BT_HCI_EVENT_PKT            (0x04)
+#define     BT_COMMAND_COMPLETE_CODE    (0x0e)
+#define     BT_CONNECT_COMPLETE_CODE    (0x0f)
+#define     BT_LL_SCAN_ACTIVE           (0x01)
+#define     BT_LL_ADV_NONCONN_IND       (0x03)
+
+#endif
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-12-02     bigmagic       first version
+ */
+#include "drv_dma.h"
+#include "raspi4.h"
+
+volatile unsigned int __attribute__((aligned(256))) dma_disc[32];
+//https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=10276
+static struct rt_semaphore dma_sem;
+
+//DMA 0 1 2 3 4 5 6
+typedef struct _dma_ctrl_block
+{
+    unsigned int TI;                   // Transfer information
+    unsigned int SOURCE_AD;            // source address
+    unsigned int DEST_AD;              // destination address
+    unsigned int TXFR_LEN;             // transfer length
+    unsigned int STRIDE;               // 2D mode stride
+    struct _dma_ctrl_block *NEXTCONBK; // Next control block address
+    unsigned int DEBUG;
+    unsigned int reserved1;
+
+} dma_ctrl_block_t;
+
+//DMA 7 8 9 10
+typedef struct _dma_lite_ctrl_block
+{
+    unsigned int TI;                        // Transfer information
+    unsigned int SOURCE_AD;                 // source address
+    unsigned int DEST_AD;                   // destination address
+    unsigned int TXFR_LEN;                  // transfer length
+    struct _dma_lite_ctrl_block *NEXTCONBK; // Next control block address
+    unsigned int DEBUG;
+    unsigned int reserved1;
+    unsigned int reserved2;
+
+} dma_lite_ctrl_block_t;
+
+//DMA 11 12 13 14 15
+typedef struct _dma4_ctrl_block
+{
+    unsigned int TI;                    // Transfer information
+    unsigned int SOURCE_AD0;            // source address0
+    unsigned int SOURCE_AD1;            // source address1
+    unsigned int DEST_AD0;              // destination address0
+    unsigned int DEST_AD1;              // destination address1
+    unsigned int TXFR_LEN;              // transfer length
+    unsigned int STRIDE;                // 2D mode stride
+    struct _dma4_ctrl_block *NEXTCONBK; // Next control block address
+} dma4_ctrl_block_t;
+
+static dma_lite_ctrl_block_t *ctr_blocks;
+
+static void dma_irq(int irq, void *param)
+{
+    if (DMA_INT_STATUS_REG & DMA_INT7)
+    {
+        DMA_CS(7) = DMA_CS_INT;
+        rt_sem_release(&dma_sem);
+    }
+}
+
+//dma 7 8 9 10:XLENGTH
+rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout)
+{
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, dst, size);
+
+    /* Stop DMA, if it was already started */
+    DMA_CS(dch) = DMA_CS_RESET;
+
+    /* Clear DMA status flags */
+    DMA_CS(dch) = DMA_CS_INT | DMA_CS_END; /* Interrupted flag & Transmission ended flag*/
+    //cb info
+    ctr_blocks->TI = DMA_TI_SRC_INC | DMA_TI_DEST_INC | DMA_TI_INTEN;
+    ctr_blocks->SOURCE_AD = (unsigned int)src;
+    ctr_blocks->DEST_AD = (unsigned int)dst;
+    ctr_blocks->TXFR_LEN = size;
+    ctr_blocks->NEXTCONBK = 0;
+    ctr_blocks->reserved1 = 0;
+    ctr_blocks->reserved2 = 0;
+
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ctr_blocks, sizeof(dma_lite_ctrl_block_t) * 8);
+
+    DMA_CONBLK_AD(dch) = (rt_uint32_t)ctr_blocks;
+    DMA_CS(dch) = DMA_CS_INT | DMA_CS_END | DMA_CS_ACTIVE;
+
+    if(rt_sem_take(&dma_sem, timeout) != RT_EOK)
+    {
+        rt_kprintf("dma transfer timeout!\n");
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+void dma_init(unsigned char dch)
+{
+    rt_sem_init(&dma_sem, "dma_sem", 0, RT_IPC_FLAG_FIFO);
+
+    ctr_blocks = (dma_lite_ctrl_block_t *)&dma_disc[0]; //rt_malloc(sizeof(DMA_Lite_Control_Block));
+    //Make sure DMA channel is enabled by
+    //writing the corresponding bit in DMA_ENABLE in the DMA register to 1
+    DMA_ENABLE_REG = (1 << dch);
+
+    rt_hw_interrupt_install(IRQ_DMA7_DMA8, dma_irq, RT_NULL, "dma_irq");
+    rt_hw_interrupt_umask(IRQ_DMA7_DMA8);
+}
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-12-02    bigmagic       first version
+ */
+#ifndef __DRV_DMA_H__
+#define __DRV_DMA_H__
+
+#include <rthw.h>
+
+#define DMA_PER_BASE                    (0xFE000000)
+
+//DMA
+#define DMA_BASE        (DMA_PER_BASE+0x7000)
+#define DMA_INT_STATUS  (DMA_BASE + 0xFE0)          //Interrupt Status of each DMA Channel
+#define DMA_ENABLE      (DMA_BASE + 0xFF0)          //Global Enable bits for each DMA Channel */
+#define DMA15_BASE      (DMA_PER_BASE+0xE05000)     //DMA Channel 15 Register Set */
+
+
+#define DMA_INT_STATUS_REG          __REG32(DMA_INT_STATUS)
+#define DMA_ENABLE_REG              __REG32(DMA_ENABLE)
+//DMA dch 1~14
+#define DMA_CS(dch)                 __REG32(DMA_BASE + dch*0x100 + 0x000)    /* Control and Status */
+#define DMA_CONBLK_AD(dch)          __REG32(DMA_BASE + dch*0x100 + 0x004)    /* Control Block Address */
+#define DMA_TI(dch)                 __REG32(DMA_BASE + dch*0x100 + 0x008)    /* CB Word 0(Transfer Information) */
+#define DMA_SOURCE_AD(dch)          __REG32(DMA_BASE + dch*0x100 + 0x00c)    /* CB Word 1(Source Address) */
+#define DMA_DEST_AD(dch)            __REG32(DMA_BASE + dch*0x100 + 0x010)    /* CB Word 2(Destination Address) */
+#define DMA_TXFR_LEN(dch)           __REG32(DMA_BASE + dch*0x100 + 0x014)    /* CB Word 3(Transfer Length) */
+#define DMA_STRIDE(dch)             __REG32(DMA_BASE + dch*0x100 + 0x018)    /* CB Word 4(2D Stride) */
+#define DMA_NEXTCONBK(dch)          __REG32(DMA_BASE + dch*0x100 + 0x01c)    /* CB Word 5(Next CB Address) */
+#define DMA_DEBUG(dch)              __REG32(DMA_BASE + dch*0x100 + 0x01c)    /* Debug */
+
+//DMA dch 15
+#define DMA15_CS                    __REG32(DMA15_BASE + 0x000)    /* Control and Status */
+#define DMA15_CONBLK_AD             __REG32(DMA15_BASE + 0x004)    /* Control Block Address */
+#define DMA15_TI                    __REG32(DMA15_BASE + 0x008)    /* CB Word 0(Transfer Information) */
+#define DMA15_SOURCE_AD             __REG32(DMA15_BASE + 0x00c)    /* CB Word 1(Source Address) */
+#define DMA15_DEST_AD               __REG32(DMA15_BASE + 0x010)    /* CB Word 2(Destination Address) */
+#define DMA15_TXFR_LEN              __REG32(DMA15_BASE + 0x014)    /* CB Word 3(Transfer Length) */
+#define DMA15_STRIDE                __REG32(DMA15_BASE + 0x018)    /* CB Word 4(2D Stride) */
+#define DMA15_NEXTCONBK             __REG32(DMA15_BASE + 0x01c)    /* CB Word 5(Next CB Address) */
+#define DMA15_DEBUG                 __REG32(DMA15_BASE + 0x01c)    /* Debug */
+
+#define DMA15_ENABLE             (1 << 15)
+#define DMA14_ENABLE             (1 << 14)
+#define DMA13_ENABLE             (1 << 13)
+#define DMA12_ENABLE             (1 << 12)
+#define DMA11_ENABLE             (1 << 11)
+#define DMA10_ENABLE             (1 << 10)
+#define DMA9_ENABLE              (1 << 9)
+#define DMA8_ENABLE              (1 << 8)
+#define DMA7_ENABLE              (1 << 7)
+#define DMA6_ENABLE              (1 << 6)
+#define DMA5_ENABLE              (1 << 5)
+#define DMA4_ENABLE              (1 << 4)
+#define DMA3_ENABLE              (1 << 3)
+#define DMA2_ENABLE              (1 << 2)
+#define DMA1_ENABLE              (1 << 1)
+#define DMA0_ENABLE              (1 << 0)
+
+//Peripheral DREQ Signals
+#define DREQ_DSI0_PWM1        (1)
+#define DREQ_PCM_TX           (2)
+#define DREQ_PCM_RX           (3)
+#define DREQ_SMI              (4)
+#define DREQ_PWM0             (5)
+#define DREQ_SPI0_TX          (6)
+#define DREQ_SPI0_RX          (7)
+#define DREQ_BSC_SPI_SLAVE_TX (8)
+#define DREQ_BSC_SPI_SLAVE_RX (9)
+#define DREQ_HSMI0            (10)
+#define DREQ_EMMC             (11)
+#define DREQ_UART0_TX         (12)
+#define DREQ_SD_HOST          (13)
+#define DREQ_UART0_RX         (14)
+#define DREQ_DSI1             (15)
+#define DREQ_SPI1_TX          (16)
+#define DREQ_HDMI1            (17)
+#define DREQ_SPI1_RX          (18)
+#define DREQ_UART3_TX_SPI4_TX (19)
+#define DREQ_UART3_RX_SPI4_RX (20)
+#define DREQ_UART5_TX_SPI5_TX (21)
+#define DREQ_UART5_RX_SPI5_RX (22)
+#define DREQ_SPI6_TX          (23)
+#define DREQ_SCALER_FIFO0_SMI (24)
+#define DREQ_SCALER_FIFO1_SMI (25)
+#define DREQ_SCALER_FIFO2_SMI (26)
+#define DREQ_SPI6_RX          (27)
+#define DREQ_UART2_TX         (28)
+#define DREQ_UART2_RX         (29)
+#define DREQ_UART4_TX         (30)
+#define DREQ_UART4_RX         (31)
+
+//IRQ
+#define DMA_INT15           (1 << 15)
+#define DMA_INT14           (1 << 14)
+#define DMA_INT13           (1 << 13)
+#define DMA_INT12           (1 << 12)
+#define DMA_INT11           (1 << 11)
+#define DMA_INT10           (1 << 10)
+#define DMA_INT9            (1 << 9)
+#define DMA_INT8            (1 << 8)
+#define DMA_INT7            (1 << 7)
+#define DMA_INT6            (1 << 6)
+#define DMA_INT5            (1 << 5)
+#define DMA_INT4            (1 << 4)
+#define DMA_INT3            (1 << 3)
+#define DMA_INT2            (1 << 2)
+#define DMA_INT1            (1 << 1)
+#define DMA_INT0            (1 << 0)
+
+//IRQ_NUMBER
+#define IRQ_DMA0            (96 + 16)
+#define IRQ_DMA1            (96 + 17)
+#define IRQ_DMA2            (96 + 18)
+#define IRQ_DMA3            (96 + 19)
+#define IRQ_DMA4            (96 + 20)
+#define IRQ_DMA5            (96 + 21)
+#define IRQ_DMA6            (96 + 22)
+#define IRQ_DMA7_DMA8       (96 + 23)
+#define IRQ_DMA9_DMA10      (96 + 24)
+#define IRQ_DMA11           (96 + 25)
+#define IRQ_DMA12           (96 + 26)
+#define IRQ_DMA13           (96 + 27)
+#define IRQ_DMA14           (96 + 28)
+#define IRQ_DMA15           (96 + 31)
+
+//CS
+#define DMA_CS_RESET            (1 << 31)
+#define DMA_CS_ABORT            (1 << 30)
+#define DMA_CS_DISDEBUG         (1 << 29)
+#define DMA_CS_DREQ_STOPS_DMA   (1 << 5)
+#define DMA_CS_PAUSED           (1 << 4)
+#define DMA_CS_DREQ             (1 << 3)
+#define DMA_CS_INT              (1 << 2)
+#define DMA_CS_END              (1 << 1)
+#define DMA_CS_ACTIVE           (1 << 0)
+
+//CONBLK_AD
+//The address must be256-bit aligned, so the bottom 5 bits of the address mustbe zero.
+
+//TI
+//DMA Transfer Information.
+#define DMA_TI_SRC_IGNORE       (1 << 11)
+#define DMA_TI_SRC_DREQ         (1 << 10)
+#define DMA_TI_SRC_WIDTH        (1 << 9)
+#define DMA_TI_SRC_INC          (1 << 8)
+#define DMA_TI_DEST_IGNORE      (1 << 7)
+#define DMA_TI_DEST_DREQ        (1 << 6)
+#define DMA_TI_DEST_WIDTH       (1 << 5)
+#define DMA_TI_DEST_INC         (1 << 4)
+#define DMA_TI_WAIT_RESP        (1 << 3)
+#define DMA_TI_TDMODE           (1 << 1)
+#define DMA_TI_INTEN            (1 << 0)
+
+//SOURCE_AD
+//DMA Source Address
+
+//DEST_AD
+//DMA Destination Address
+
+//TXFR_LEN
+//DMA Transfer Length
+
+void dma_init(unsigned char dch);
+rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout);
+
+#endif
@@ -53,6 +53,17 @@
 #define MDIO_REG_SHIFT              (16)
 #define MDIO_REG_MASK               (0x1f)

+#define  GENET_INTRL2_OFF               (0x0200)
+#define  GENET_INTRL2_CPU_STAT          (GENET_INTRL2_OFF + 0x00)
+#define  GENET_INTRL2_CPU_CLEAR         (GENET_INTRL2_OFF + 0x08)
+#define  GENET_INTRL2_CPU_STAT_MASK     (GENET_INTRL2_OFF + 0x0c)
+#define  GENET_INTRL2_CPU_SET_MASK      (GENET_INTRL2_OFF + 0x10)
+#define  GENET_INTRL2_CPU_CLEAR_MASK    (GENET_INTRL2_OFF + 0x14)
+#define  GENET_IRQ_MDIO_ERROR           BIT(24)
+#define  GENET_IRQ_MDIO_DONE            BIT(23)
+#define  GENET_IRQ_TXDMA_DONE           BIT(16)
+#define  GENET_IRQ_RXDMA_DONE           BIT(13)
+
 #define CMD_TX_EN                   BIT(0)
 #define CMD_RX_EN                   BIT(1)
 #define UMAC_SPEED_10               (0)
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-28     bigmagic       first version
+ */
+
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+
+#include <rthw.h>
+
+#define BSC_C(BASE)         __REG32(BASE + 0x0000)    /* BSC Master Control */
+#define BSC_S(BASE)         __REG32(BASE + 0x0004)    /* BSC Master Status */
+#define BSC_DLEN(BASE)      __REG32(BASE + 0x0008)    /* BSC Master Data Length */
+#define BSC_A(BASE)         __REG32(BASE + 0x000c)    /* BSC Master Slave Address */
+#define BSC_FIFO(BASE)      __REG32(BASE + 0x0010)    /* BSC Master Data FIFO */
+#define BSC_DIV(BASE)       __REG32(BASE + 0x0014)    /* BSC Master Clock Divider */
+#define BSC_DEL(BASE)       __REG32(BASE + 0x0018)    /* BSC Master Data Delay */
+#define BSC_CLKT(BASE)      __REG32(BASE + 0x001c)    /* BSC Master Clock Stretch Timeout */
+
+/* Register masks for C Register */
+#define BSC_C_I2CEN         (0x00008000) /* I2C Enable, 0 = disabled, 1 = enabled */
+#define BSC_C_INTR          (0x00000400) /* Interrupt on RX */
+#define BSC_C_INTT          (0x00000200) /* Interrupt on TX */
+#define BSC_C_INTD          (0x00000100) /* Interrupt on DONE */
+#define BSC_C_ST            (0x00000080) /* Start transfer, 1 = Start a new transfer */
+#define BSC_C_CLEAR_1       (0x00000020) /* Clear FIFO Clear */
+#define BSC_C_CLEAR_2       (0x00000010) /* Clear FIFO Clear */
+#define BSC_C_READ          (0x00000001) /* Read transfer */
+
+/* Register masks for S Register */
+#define BSC_S_CLKT          (0x00000200) /* Clock stretch timeout */
+#define BSC_S_ERR           (0x00000100) /* ACK error */
+#define BSC_S_RXF           (0x00000080) /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BSC_S_TXE           (0x00000040) /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BSC_S_RXD           (0x00000020) /* RXD FIFO contains data */
+#define BSC_S_TXD           (0x00000010) /* TXD FIFO can accept data */
+#define BSC_S_RXR           (0x00000008) /* RXR FIFO needs reading (full) */
+#define BSC_S_TXW           (0x00000004) /* TXW FIFO needs writing (full) */
+#define BSC_S_DONE          (0x00000002) /* Transfer DONE */
+#define BSC_S_TA            (0x00000001) /* Transfer Active */
+
+#define BSC_FIFO_SIZE  (16)  /* BSC FIFO size */
+
+typedef enum
+{
+    I2C_REASON_OK           = 0x00,      /* Success */
+    I2C_REASON_ERROR_NACK   = 0x01,      /* Received a NACK */
+    I2C_REASON_ERROR_CLKT   = 0x02,      /* Received Clock Stretch Timeout */
+    I2C_REASON_ERROR_DATA   = 0x04       /* Not all data is sent / received */
+} i2c_reason_codes;
+
+int rt_hw_i2c_init(void);
+
+#endif
@@ -103,8 +103,8 @@ rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask)
    {
        write32(pdat->virt + EMMC_INTERRUPT, r);
        //qemu maybe can not use sdcard
-        //rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
-        //return -RT_ETIMEOUT;
+        rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
+        return -RT_ETIMEOUT;
    }
    else if (r & INT_ERROR_MASK)
    {
@@ -552,9 +552,8 @@ static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat)

    // Clear control2
    write32(pdat->virt + EMMC_CONTROL2, 0);
-
-    // Get the base clock rate
-    mmc_base_clock = bcm271x_mbox_clock_get_rate(12);
+    // Get the base clock rate //12
+    mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID);
    if(mmc_base_clock == 0)
    {
        rt_kprintf("EMMC: assuming clock rate to be 100MHz\n");
@@ -590,7 +589,6 @@ int raspi_sdmmc_init(void)
    struct rt_mmcsd_host * host = RT_NULL;
    struct sdhci_pdata_t * pdat = RT_NULL;
    struct sdhci_t * sdhci = RT_NULL;
-
 #ifdef BSP_USING_SDIO0
    host = mmcsd_alloc_host();
    if (!host)
@@ -598,7 +596,6 @@ int raspi_sdmmc_init(void)
        rt_kprintf("alloc host failed");
        goto err;
    }
-
    sdhci = rt_malloc(sizeof(struct sdhci_t));
    if (!sdhci)
    {
@@ -608,17 +605,15 @@ int raspi_sdmmc_init(void)
    rt_memset(sdhci, 0, sizeof(struct sdhci_t));

    virt = MMC2_BASE_ADDR;
-
    pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
    RT_ASSERT(pdat != RT_NULL);

    pdat->virt = (rt_uint32_t)virt;
    reset_emmc(pdat);
-
    sdhci->name = "sd0";
    sdhci->voltages = VDD_33_34;
    sdhci->width = MMCSD_BUSWIDTH_4;
-    sdhci->clock = 250 * 1000 * 1000;
+    sdhci->clock = 1000 * 1000 * 1000;
    sdhci->removeable = RT_TRUE;

    sdhci->detect = sdhci_detect;
@@ -634,10 +629,9 @@ int raspi_sdmmc_init(void)
    host->max_seg_size = 2048;
    host->max_dma_segs = 10;
    host->max_blk_size = 512;
-    host->max_blk_count = 4096;
+    host->max_blk_count = 1;

    host->private_data = sdhci;
-
    write32((pdat->virt + EMMC_IRPT_EN),0xffffffff);
    write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff);
 #ifdef RT_MMCSD_DBG
@@ -16,8 +16,7 @@

 #ifdef RT_USING_SPI

-#define RPI_CORE_CLK_HZ        (250000000)
-#define BSP_SPI_MAX_HZ         (30* 1000 *1000)
+#define RPI_CORE_CLK_HZ        (500 * 1000 * 1000)
 #define SPITIMEOUT             0x0FFF

 static rt_uint8_t raspi_byte_reverse_table[] =
@@ -76,35 +75,35 @@ static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_
 {
    RT_ASSERT(cfg != RT_NULL);
    RT_ASSERT(device != RT_NULL);
-    rt_uint16_t divider;
    struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data);
    struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
    // spi clear fifo
-    SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
+    SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
    if(cfg->mode & RT_SPI_CPOL)
    {
        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL;
    }
+    else
+    {
+        SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CPOL;
+    }

    if(cfg->mode & RT_SPI_CPHA)
    {
        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA;
+    }else
+    {
+        SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CPHA;
    }

    if(cfg->mode & RT_SPI_CS_HIGH)
    {
        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH;   
    }
-
-    //set clk
-    if (cfg->max_hz > BSP_SPI_MAX_HZ)
-        cfg->max_hz = BSP_SPI_MAX_HZ;
-
-    divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz);
-    divider &= 0xFFFE;
-
-    SPI_REG_CLK(hwcfg->hw_base) = divider;
-
+    else
+    {
+        SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CSPOL_HIGH;   
+    }
    return RT_EOK;
 }

@@ -120,13 +119,6 @@ static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tb
 {
    rt_uint32_t TXCnt=0;
    rt_uint32_t RXCnt=0;
-    
-    /* Clear TX and RX fifos */
-    SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
-
-    /* Set TA = 1 */
-    SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA;
-
    /* Use the FIFO's to reduce the interbyte times */
    while ((TXCnt < len) || (RXCnt < len))
    {
@@ -145,9 +137,6 @@ static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tb
    }
    /* Wait for DONE to be set */
    while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE));
-    /* Set TA = 0, and also set the barrier */
-    SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA);
-
    return RT_EOK;
 }

@@ -159,31 +148,54 @@ static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
    RT_ASSERT(device->bus != RT_NULL);
    RT_ASSERT(device->parent.user_data != RT_NULL);
    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
-
    struct rt_spi_configuration config = device->config;
    struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data;
    GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin;
    struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;

+    //mode MSB
    if (config.mode & RT_SPI_MSB)
    {
-        flag = 0;
+        flag = 1;
    }   
    else
    {
-        flag = 1;
+        flag = 0;
    }

+    //max_hz
+    if(config.max_hz == 0)
+    {
+        SPI_REG_CLK(hwcfg->hw_base) = 0;
+    }
+    else
+    {
+        SPI_REG_CLK(hwcfg->hw_base) = (RPI_CORE_CLK_HZ / (config.max_hz));
+    }
+    
+    //cs_pin spi0.0
+    if(cs_pin == GPIO_PIN_8)
+    {
+        SPI_REG_CS(hwcfg->hw_base) &= (~(3 << 0));
+    }
+    else if(cs_pin == GPIO_PIN_7)//spi0.1
+    {
+        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1;
+    }
+
+    //Clear TX and RX fifos
+    SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
    if (message->cs_take)
    {
-        (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0);
+        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA;
    }
-
    res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag);
    if (message->cs_release)
    {
-        (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1);
+        //Set TA = 0, and also set the barrier
+        SPI_REG_CS(hwcfg->hw_base) &= (~SPI_CS_TA);
    }
+
    if (res != RT_EOK)
           return RT_ERROR;

@@ -212,18 +224,6 @@ rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg)
 #endif
    //clear rx and tx
    SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
-    //enable chip select
-#if defined (BSP_USING_SPI0_DEVICE0)
-    SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0;
-#endif
-
-#if defined (BSP_USING_SPI0_DEVICE1)
-    SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1;
-#endif
-    
-#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
-    HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1);
-#endif
    return RT_EOK;
 }

@@ -273,6 +273,7 @@ struct raspi_spi_device raspi_spi0_device1 =
    .device_name = SPI0_DEVICE1_NAME,
    .spi_bus = &spi0_bus,
    .spi_device = &spi0_device1,
+    .spi_hw_config = &raspi_spi0_hw,
    .cs_pin = GPIO_PIN_7,
 };
 #endif
@@ -63,15 +63,22 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
        AUX_MU_LCR_REG(uart->hw_base)   = 3;    /* Works in 8-bit mode */
        AUX_MU_MCR_REG(uart->hw_base)   = 0;    /* Disable RTS */
        AUX_MU_IIR_REG(uart->hw_base)   = 0xC6; /* Enable FIFO, Clear FIFO */
-        AUX_MU_BAUD_REG(uart->hw_base)  = 270;  /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
+        AUX_MU_BAUD_REG(uart->hw_base)  = 541;  /* 115200 = system clock 500MHz / (8 * (baud + 1)), baud = 541 */
        AUX_MU_CNTL_REG(uart->hw_base)  = 3;    /* Enable Transmitter and Receiver */
        return RT_EOK;
    }

    if(uart->hw_base == UART0_BASE)
    {
+#ifndef BSP_USING_BULETOOTH
        prev_raspi_pin_mode(GPIO_PIN_14, ALT0);
        prev_raspi_pin_mode(GPIO_PIN_15, ALT0);
+#else
+        prev_raspi_pin_mode(GPIO_PIN_30, ALT3);
+        prev_raspi_pin_mode(GPIO_PIN_31, ALT3);
+        prev_raspi_pin_mode(GPIO_PIN_32, ALT3);
+        prev_raspi_pin_mode(GPIO_PIN_33, ALT3);
+#endif
    }

    if(uart->hw_base == UART3_BASE)
@@ -92,13 +99,21 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
        prev_raspi_pin_mode(GPIO_PIN_13, ALT4);
    }

-    PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
-    PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+    PL011_REG_IMSC(uart->hw_base) = 0;     /* mask all interrupt */
+    PL011_REG_ICR(uart->hw_base) = 0x7ff;  /* clear all interrupt */
+    //PL011 clock 480MHz 480x10^6/baudrate/16
    PL011_REG_IBRD(uart->hw_base) = ibrd;
    PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
-    PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
-    PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
-
+#ifdef BSP_USING_BULETOOTH
+    PL011_REG_IFLS(uart->hw_base) = 0x08;
+    PL011_REG_LCRH(uart->hw_base) = 0x70;
+    PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE | PL011_CR_RTS;
+#else
+    PL011_REG_IFLS(uart->hw_base) = 0x0;
+    PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;
+    PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;
+#endif
+    PL011_REG_IMSC(uart->hw_base) = 0;
    return RT_EOK;
 }

@@ -0,0 +1,18 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if not (GetDepend('BSP_USING_HDMI_DISPLAY') or GetDepend('BSP_USING_DSI_DISPLAY')):
+    SrcRemove(src, ['drv_hdmi.c'])
+if not GetDepend('BSP_USING_ILI9486'):
+    SrcRemove(src, ['drv_ili9486.c'])
+if not GetDepend('USING_LCD_CONSOLE'):
+    SrcRemove(src, ['lcd_console.c'])
+
+group = DefineGroup('drv_lcd', src, depend = ['BSP_USING_LCD'], CPPPATH = CPPPATH)
+
+Return('group')
@@ -13,10 +13,14 @@
 #include "mbox.h"
 #include "drv_hdmi.h"

-#ifdef BSP_USING_HDMI
+#ifdef USING_LCD_CONSOLE
+#include "lcd_console.h"
+#endif
+
+#if defined(BSP_USING_HDMI_DISPLAY) || defined(BSP_USING_DSI_DISPLAY)
 #define LCD_WIDTH     (800)
 #define LCD_HEIGHT    (480)
-#define LCD_DEPTH     (32)
+#define LCD_DEPTH     (4)
 #define LCD_BPP       (32)

 #define TAG_ALLOCATE_BUFFER         0x00040001
@@ -84,6 +88,9 @@ rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)

 rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
+#ifdef USING_LCD_CONSOLE
+    fb_print((char*)buffer);
+#endif
    return size;
 }

@@ -105,7 +112,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)

            RT_ASSERT(info != RT_NULL);
            info->pixel_format  = RTGRAPHIC_PIXEL_FORMAT_RGB888;
-            info->bits_per_pixel= LCD_DEPTH;
+            info->bits_per_pixel= 32;
            info->width         = lcd->width;
            info->height        = lcd->height;
            info->framebuffer   = lcd->fb;
@@ -285,12 +292,18 @@ void *bcm271x_mbox_fb_alloc(int width, int height, int bpp, int nrender)
    mbox[34] = TAG_END;

    mbox_call(8, MMU_DISABLE);
+
    return (void *)((rt_uint32_t)(mbox[5] & 0x3fffffff));
 }

 int hdmi_fb_init(void)
 {
    _hdmi.fb = (rt_uint8_t *)bcm271x_mbox_fb_alloc(LCD_WIDTH, LCD_HEIGHT, LCD_BPP, 1);
+    if(_hdmi.fb == RT_NULL)
+    {
+        rt_kprintf("init dsi or hdmi err!\n");
+        return 0;
+    }
    bcm271x_mbox_fb_setoffset(0, 0);
    bcm271x_mbox_fb_set_porder(0);
    _hdmi.width = LCD_WIDTH;
@@ -299,8 +312,9 @@ int hdmi_fb_init(void)
    _hdmi.pitch = 0;
    _hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;

+    rt_memset(_hdmi.fb, 0, LCD_WIDTH*LCD_HEIGHT*(LCD_BPP/8));
    //rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb);
-    rt_hdmi_fb_device_init(&_hdmi, "lcd");
+    rt_hdmi_fb_device_init(&_hdmi, "hdmi");

    return 0;
 }
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-08     bigmagic       first version
+ */
+#ifndef __DRV_ILI9486_H__
+#define __DRV_ILI9486_H__
+
+#endif//ILI9486
@@ -0,0 +1,59 @@
+
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-09     bigmagic       first version
+ */
+#ifndef __LCD_CONSOLE_H__
+#define __LCD_CONSOLE_H__
+
+#include <rtthread.h>
+
+#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
+#define COLOR_BLACK RGB(0, 0, 0)
+#define COLOR_GREEN RGB(0, 255, 0)  
+#define COLOR_CYAN RGB(0, 255, 255) 
+#define COLOR_RED RGB(255, 0, 0)  
+#define COLOR_YELLOW RGB(255, 255, 0) 
+#define COLOR_WHITE RGB(255, 255, 255)
+
+#define CONSOLE_WHITE_32 COLOR_WHITE
+#define CONSOLE_BLACK_32 COLOR_BLACK
+#define CONSOLE_GREEN_32 COLOR_GREEN
+#define CONSOLE_CYAN_32 COLOR_CYAN
+#define CONSOLE_RED_32 COLOR_RED
+
+
+#define RGB16(r, g, b) ((((r))<<11) | (((g))<<5) | ((b)))
+#define CONSOLE_YELLOW_16 RGB16(0x1f,0x3f,0)
+#define CONSOLE_WHITE_16 RGB16(0x1f,0x3f,0x1f)
+#define CONSOLE_BLACK_16 RGB16(0,0,0)
+#define CONSOLE_GREEN_16 RGB16(0,0x3f,0)
+#define CONSOLE_CYAN_16 RGB16(0,0x3f,0x1f)
+#define CONSOLE_RED_16 RGB16(0x1f,0,0)
+
+typedef struct
+{
+    rt_uint32_t width;
+    rt_uint32_t height;
+    rt_uint32_t vwidth;
+    rt_uint32_t vheight;
+    rt_uint32_t pitch;
+    rt_uint32_t depth;
+    rt_uint32_t fore;
+    rt_uint32_t back;
+    rt_uint32_t x;
+    rt_uint32_t y;
+    rt_uint32_t vaddr;
+    rt_uint32_t paddr;
+    rt_uint32_t size;
+} fb_t;
+
+void fb_print(char *s);
+int lcd_console_init(void);
+
+#endif//CONSOLE
@@ -49,6 +49,24 @@ int mbox_call(unsigned char ch, int mmu_enable)
    return 0;
 }

+int bcm271x_mbox_get_touch(void)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_GET_TOUCHBUF; 
+    mbox[3] = 4;                        // buffer size
+    mbox[4] = 0;                        // len
+
+    mbox[5] = 0;                       // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    return (int)(mbox[5] &  ~0xC0000000);
+}
+
 int bcm271x_notify_reboot(void)
 {
    mbox[0] = 7*4;                          // length of the message
@@ -132,9 +132,27 @@ enum {
 #define MBOX_TAG_NOTIFY_REBOOT         0x00030048
 #define MBOX_TAG_NOTIFY_XHCI_RESET     0x00030058

+/*
+* touch
+*/
+#define MBOX_TAG_GET_TOUCHBUF          (0x0004000F)
+
 #define MBOX_ADDR 0x08000000

+#define    RES_CLK_ID           (0x000000000)
+#define    EMMC_CLK_ID          (0x000000001)
+#define    UART_CLK_ID          (0x000000002)
+#define    ARM_CLK_ID           (0x000000003)
+#define    CORE_CLK_ID          (0x000000004)
+#define    V3D_CLK_ID           (0x000000005)
+#define    H264_CLK_ID          (0x000000006)
+#define    ISP_CLK_ID           (0x000000007)
+#define    SDRAM_CLK_ID         (0x000000008)
+#define    PIXEL_CLK_ID         (0x000000009)
+#define    PWM_CLK_ID           (0x00000000a)
+
 int mbox_call(unsigned char ch, int mmu_enable);
+int bcm271x_mbox_get_touch(void);
 int bcm271x_notify_reboot(void);
 int bcm271x_notify_xhci_reset(void);
 int bcm271x_gpu_enable(void);
@@ -150,7 +150,26 @@ typedef enum {

 //External Mass Media Controller (SD Card)
 #define MMC0_BASE_ADDR		(PER_BASE+0x300000)   
-#define MMC2_BASE_ADDR		(PER_BASE+0x340000)  
+#define MMC2_BASE_ADDR		(PER_BASE+0x340000)
+
+#define ETH_IRQ                 (160+29)
+
+//I2C
+#define BSC0_BASE_OFFSET            (0x205000)
+#define BSC1_BASE_OFFSET            (0x804000)
+#define BSC3_BASE_OFFSET            (0x205600)
+#define BSC4_BASE_OFFSET            (0x205800)
+#define BSC5_BASE_OFFSET            (0x205A80)
+#define BSC6_BASE_OFFSET            (0x205C00)
+
+//BSC2 and BSC7 masters are dedicated for use by the 
+//HDMI interfaces and should not be accessed byuser programs.
+#define BSC0_BASE                   (PER_BASE + BSC0_BASE_OFFSET)
+#define BSC1_BASE                   (PER_BASE + BSC1_BASE_OFFSET)
+#define BSC3_BASE                   (PER_BASE + BSC3_BASE_OFFSET)
+#define BSC4_BASE                   (PER_BASE + BSC4_BASE_OFFSET)
+#define BSC5_BASE                   (PER_BASE + BSC5_BASE_OFFSET)
+#define BSC6_BASE                   (PER_BASE + BSC6_BASE_OFFSET)

 /* the basic constants and interfaces needed by gic */
 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
@@ -0,0 +1,16 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if not GetDepend('BSP_USING_XPT_TOUCH_DEV'):
+    SrcRemove(src, ['drv_xpt2046.c'])
+if not GetDepend('BSP_USING_DSI_TOUCH_DEV'):
+    SrcRemove(src, ['drv_dsi_touch.c'])
+
+group = DefineGroup('drv_touch', src, depend = ['BSP_USING_TOUCH'], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-26     bigmagic       first version
+ */
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <touch.h>
+
+#include "mbox.h"
+#include "drv_dsi_touch.h"
+
+#define DBG_TAG "dsi_touch"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+static rt_touch_t touch_device = RT_NULL;
+static struct rt_semaphore dsi_touch_ack;
+
+static rt_uint32_t touch_x;
+static rt_uint32_t touch_y;
+static rt_uint32_t touch_state;
+
+static rt_thread_t dsi_touch_tid = RT_NULL;
+#define DSI_TOUCH_THREAD_STACK_SIZE     (4096)
+#define DSI_TOUCH_THREAD_PRIORITY       (25)
+#define DSI_TOUCH_THREAD_TIMESLICE      (10)
+
+#define MAXIMUM_SUPPORTED_POINTS        (10)
+
+struct touch_regs
+{
+    uint8_t device_mode;
+    uint8_t gesture_id;
+    uint8_t num_points;
+    struct touch
+    {
+        uint8_t xh;
+        uint8_t xl;
+        uint8_t yh;
+        uint8_t yl;
+        uint8_t res1;
+        uint8_t res2;
+    } point[MAXIMUM_SUPPORTED_POINTS];
+};
+
+static void dsi_touch_thread_entry(void *param)
+{
+    static volatile uint32_t touchbuf;
+    touchbuf = bcm271x_mbox_get_touch(); //0x0f436000
+
+    if(touchbuf == RT_NULL)
+    {
+        rt_kprintf("init dsi touch err!\n");
+        return;
+    }
+    
+    while (1)
+    {
+        struct touch_regs *regs = (struct touch_regs *)touchbuf;
+        if ((regs->num_points > 0) && (regs->num_points < MAXIMUM_SUPPORTED_POINTS))
+        {
+            //only one touch point
+            touch_x = (((int)regs->point[0].xh & 0xf) << 8) + regs->point[0].xl;
+            touch_y = (((int)regs->point[0].yh & 0xf) << 8) + regs->point[0].yl;
+            touch_state = 1;
+        }
+        else
+        {
+            touch_state = 0;
+        }
+        rt_thread_mdelay(50); 
+    }
+}
+
+static rt_size_t dsi_read_point(struct rt_touch_device *touch, void *buf, rt_size_t read_num)
+{
+    rt_uint16_t* touchxy = (rt_uint16_t *)buf;
+    if((read_num != 0) && (touch_state == 1))
+    {
+        touchxy[0] = touch_x;
+        touchxy[1] = touch_y;
+        touch_state = 0;
+        return read_num;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+static rt_err_t dsi_control(struct rt_touch_device *device, int cmd, void *data)
+{
+    return RT_EOK;
+}
+
+static struct rt_touch_ops dsi_touch_ops =
+{
+    .touch_readpoint = dsi_read_point,
+    .touch_control = dsi_control,
+};
+
+static int hw_dsi_touch_init(void)
+{
+    //touch sem
+    rt_sem_init(&dsi_touch_ack, "dsi_touch_ack", 0, RT_IPC_FLAG_FIFO);
+
+    dsi_touch_tid = rt_thread_create("dsi_touch",
+                            dsi_touch_thread_entry, RT_NULL,
+                            DSI_TOUCH_THREAD_STACK_SIZE,
+                            DSI_TOUCH_THREAD_PRIORITY, DSI_TOUCH_THREAD_TIMESLICE);
+    if (dsi_touch_tid != RT_NULL)
+        rt_thread_startup(dsi_touch_tid);
+
+    touch_device = (rt_touch_t)rt_calloc(1, sizeof(struct rt_touch_device));
+
+    if (touch_device == RT_NULL)
+        return -RT_ERROR;
+
+    /* register touch device */
+    touch_device->info.type = RT_TOUCH_TYPE_RESISTANCE;
+    touch_device->info.vendor = RT_TOUCH_VENDOR_UNKNOWN;
+    //rt_memcpy(&touch_device->config, cfg, sizeof(struct rt_touch_config));
+    touch_device->ops = &dsi_touch_ops;
+    rt_hw_touch_register(touch_device, "dsi_touch", RT_DEVICE_FLAG_INT_RX, RT_NULL);
+    return 0;
+}
+INIT_DEVICE_EXPORT(hw_dsi_touch_init);
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-26     bigmagic       first version
+ */
+#ifndef __DRV_DSI_TOUCH_H__
+#define __DRV_DSI_TOUCH_H__
+
+#endif//DSI TOUCH
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-11-08     bigmagic       first version
+ */
+#ifndef __DRV_XPT2046_H__
+#define __DRV_XPT2046_H__
+
+#endif//XPT2046
@@ -63,6 +63,14 @@ SECTIONS
        _etext = .;
    }

+    __exidx_start = .;
+    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+    __exidx_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
    .eh_frame_hdr :
    {
         *(.eh_frame_hdr)
@@ -10,7 +10,7 @@
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
+#define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_USING_IDLE_HOOK
@@ -40,7 +40,7 @@
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_CONSOLE_DEVICE_NAME "uart1"
 #define RT_VER_NUM 0x40003
 #define ARCH_ARMV8

@@ -94,9 +94,14 @@

 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 64
+#define RT_SERIAL_RB_BUFSZ 512
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
 #define RT_USING_SDIO
 #define RT_SDIO_STACK_SIZE 512
@@ -106,6 +111,7 @@
 #define RT_MMCSD_MAX_PARTITION 16
 #define RT_USING_SPI
 #define RT_USING_WDT
+#define RT_USING_TOUCH

 /* Using USB */

@@ -119,6 +125,12 @@

 /* Socket abstraction layer */

+#define RT_USING_SAL
+
+/* protocol stack implement */
+
+#define SAL_USING_LWIP
+#define SAL_USING_POSIX

 /* Network interface device */

@@ -214,6 +226,9 @@
 /* system packages */


+/* Micrium: Micrium software products porting for RT-Thread */
+
+
 /* peripheral libraries and drivers */


@@ -223,6 +238,9 @@
 /* samples: kernel and components samples */


+/* games: games run on RT-Thread console */
+
+
 /* Privated Packages of RealThread */


@@ -236,22 +254,29 @@

 #define BSP_USING_UART
 #define RT_USING_UART0
+#define RT_USING_UART1
 #define RT_USING_UART3
-#define RT_USING_UART4
+#define RT_USING_UART5
 #define BSP_USING_GIC
 #define BSP_USING_GIC400
 #define BSP_USING_PIN
 #define BSP_USING_SPI
 #define BSP_USING_SPI0_BUS
 #define BSP_USING_SPI0_DEVICE0
+#define BSP_USING_SPI0_DEVICE1
+#define BSP_USING_I2C
+#define BSP_USING_I2C3
 #define BSP_USING_CORETIMER
 #define BSP_USING_WDT
+#define BSP_USING_ETH
 #define BSP_USING_SDIO
 #define BSP_USING_SDIO0

 /* Board Peripheral Drivers */

-#define BSP_USING_HDMI
-#define BSP_USING_HDMI_DISPLAY
+#define BSP_USING_LCD
+#define BSP_USING_DSI_DISPLAY
+#define BSP_USING_TOUCH
+#define BSP_USING_DSI_TOUCH_DEV

 #endif
@@ -40,7 +40,21 @@ config BSP_USING_RNG
    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
                SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
    default n
-    
+
+config BSP_USING_HASH
+    bool "Enable HASH (Hash House Harriers)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_HASH
+    depends on (SOC_SERIES_STM32MP1)
+    default n
+
+config BSP_USING_CRYP
+    bool "Enable CRYP (Encrypt And Decrypt Data)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRYP
+    depends on (SOC_SERIES_STM32MP1)
+    default n
+
 config BSP_USING_UDID
    bool "Enable UDID (Unique Device Identifier)"
    select RT_USING_HWCRYPTO
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */
@@ -1,13 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
- * 2019-01-02     zylx         first version
- * 2019-01-08     SummerGift   clean up the code
- * 2020-06-20     thread-liu   add stm32mp1
+ * 2020-06-20     thread-liu   first version
 */

 #ifndef __DMA_CONFIG_H__
@@ -19,6 +17,22 @@
 extern "C" {
 #endif

+/* DMA1 stream0 */
+
+/* DMA1 stream1 */
+
+/* DMA1 stream2 */
+
+/* DMA1 stream3 */
+
+/* DMA1 stream4 */
+
+/* DMA1 stream5 */
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+
 /* DMA2 stream0 */
 #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
 #define UART3_RX_DMA_IRQHandler          DMA2_Stream0_IRQHandler
@@ -26,18 +40,12 @@ extern "C" {
 #define UART3_RX_DMA_INSTANCE            DMA2_Stream0
 #define UART3_RX_DMA_CHANNEL             DMA_REQUEST_USART3_RX
 #define UART3_RX_DMA_IRQ                 DMA2_Stream0_IRQn
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
-#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
-#define SPI4_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
-#define SPI4_RX_DMA_CHANNEL              DMA_REQUEST_SPI4_RX
-#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
-#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
-#define UART5_DMA_RX_IRQHandler          DMA2_Stream0_IRQHandler
-#define UART5_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
-#define UART5_RX_DMA_INSTANCE            DMA2_Stream0
-#define UART5_RX_DMA_CHANNEL             DMA_REQUEST_UART5_RX
-#define UART5_RX_DMA_IRQ                 DMA2_Stream0_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI5_RX_DMA_CHANNEL              DMA_REQUEST_SPI5_RX
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
    
 /* DMA2 stream1 */
@@ -47,12 +55,12 @@ extern "C" {
 #define UART3_TX_DMA_INSTANCE             DMA2_Stream1
 #define UART3_TX_DMA_CHANNEL              DMA_REQUEST_USART3_TX
 #define UART3_TX_DMA_IRQ                  DMA2_Stream1_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
-#define SPI4_TX_DMA_CHANNEL              DMA_REQUEST_SPI4_TX
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI5_TX_DMA_CHANNEL              DMA_REQUEST_SPI5_TX
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream1_IRQn
 #endif

 /* DMA2 stream2 */
@@ -65,48 +73,48 @@ extern "C" {
 #endif

 /* DMA2 stream3 */
-#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
-#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI5_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
-#define SPI5_RX_DMA_CHANNEL              DMA_REQUEST_SPI5_RX
-#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA2_Stream3_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART4_RX_DMA_INSTANCE            DMA2_Stream3
+#define UART4_RX_DMA_CHANNEL             DMA_REQUEST_UART4_RX
+#define UART4_RX_DMA_IRQ                 DMA2_Stream3_IRQn        
 #endif

 /* DMA2 stream4 */
-#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
-#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
-#define SPI5_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
-#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
-#define SPI5_TX_DMA_CHANNEL              DMA_REQUEST_SPI5_TX
-#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA2_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART4_TX_DMA_INSTANCE            DMA2_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_REQUEST_UART4_TX
+#define UART4_TX_DMA_IRQ                 DMA2_Stream4_IRQn   
 #endif

 /* DMA2 stream5 */
-#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
-#define UART4_DMA_TX_IRQHandler          DMA2_Stream5_IRQHandler
-#define UART4_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
-#define UART4_TX_DMA_INSTANCE            DMA2_Stream5
-#define UART4_TX_DMA_CHANNEL             DMA_REQUEST_UART4_TX
-#define UART4_TX_DMA_IRQ                 DMA2_Stream5_IRQn    
+#if defined(BSP_USING_CRYP) && !defined(CRYP2_OUT_DMA_INSTANCE)
+#define CRYP2_DMA_OUT_IRQHandler           DMA2_Stream5_IRQHandler
+#define CRYP2_OUT_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define CRYP2_OUT_DMA_INSTANCE             DMA2_Stream5
+#define CRYP2_OUT_DMA_CHANNEL              DMA_REQUEST_CRYP2_OUT
+#define CRYP2_OUT_DMA_IRQ                  DMA2_Stream5_IRQn
 #endif

 /* DMA2 stream6 */
-#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
-#define UART4_DMA_RX_IRQHandler          DMA2_Stream6_IRQHandler
-#define UART4_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
-#define UART4_RX_DMA_INSTANCE            DMA2_Stream6
-#define UART4_RX_DMA_CHANNEL             DMA_REQUEST_UART4_RX
-#define UART4_RX_DMA_IRQ                 DMA2_Stream6_IRQn        
+#if defined(BSP_USING_CRYP) && !defined(CRYP2_IN_DMA_INSTANCE)
+#define CRYP2_DMA_IN_IRQHandler          DMA2_Stream6_IRQHandler
+#define CRYP2_IN_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define CRYP2_IN_DMA_INSTANCE            DMA2_Stream6
+#define CRYP2_IN_DMA_CHANNEL             DMA_REQUEST_CRYP2_IN
+#define CRYP2_IN_DMA_IRQ                 DMA2_Stream6_IRQn    
 #endif

 /* DMA2 stream7 */
-#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
-#define UART5_DMA_TX_IRQHandler          DMA2_Stream7_IRQHandler
-#define UART5_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
-#define UART5_TX_DMA_INSTANCE            DMA2_Stream7
-#define UART5_TX_DMA_CHANNEL             DMA_REQUEST_UART5_TX
-#define UART5_TX_DMA_IRQ                 DMA2_Stream7_IRQn
+#if defined(BSP_USING_HASH) && !defined(HASH2_IN_DMA_INSTANCE)
+#define HASH2_DMA_IN_IRQHandler          DMA2_Stream7_IRQHandler
+#define HASH2_IN_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define HASH2_IN_DMA_INSTANCE            DMA2_Stream7
+#define HASH2_IN_DMA_CHANNEL             DMA_REQUEST_HASH2_IN
+#define HASH2_IN_DMA_IRQ                 DMA2_Stream7_IRQn  
 #endif
    
 #ifdef __cplusplus
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */
@@ -23,7 +23,6 @@ extern "C" {
    {                                               \
        .Instance = SPI1,                           \
        .bus_name = "spi1",                         \
-        .irq_type = SPI1_IRQn,                      \
    }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
@@ -58,7 +57,6 @@ extern "C" {
    {                                               \
        .Instance = SPI2,                           \
        .bus_name = "spi2",                         \
-        .irq_type = SPI2_IRQn,                      \
    }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
@@ -93,7 +91,6 @@ extern "C" {
    {                                               \
        .Instance = SPI3,                           \
        .bus_name = "spi3",                         \
-        .irq_type = SPI3_IRQn,                      \
    }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
@@ -128,7 +125,6 @@ extern "C" {
    {                                               \
        .Instance = SPI4,                           \
        .bus_name = "spi4",                         \
-        .irq_type = SPI4_IRQn,                      \
    }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
@@ -73,6 +73,7 @@ extern "C" {
 #include "l4/spi_config.h"
 #include "l4/qspi_config.h"
 #include "l4/adc_config.h"
+#include "l4/dac_config.h"
 #include "l4/tim_config.h"
 #include "l4/sdio_config.h"
 #include "l4/pwm_config.h"
@@ -109,6 +110,7 @@ extern "C" {
 #elif  defined(SOC_SERIES_STM32MP1)
 #include "mp1/dma_config.h"
 #include "mp1/uart_config.h"
+#include "mp1/qspi_config.h"
 #include "mp1/spi_config.h"
 #include "mp1/adc_config.h"
 #include "mp1/dac_config.h"    
@@ -43,7 +43,7 @@ static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t chan
    RT_ASSERT(device != RT_NULL);
    stm32_dac_handler = device->parent.user_data;

-#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4)
        HAL_DAC_Start(stm32_dac_handler, channel);
 #endif
    
@@ -56,7 +56,7 @@ static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t cha
    RT_ASSERT(device != RT_NULL);
    stm32_dac_handler = device->parent.user_data;
    
-#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4)
    HAL_DAC_Stop(stm32_dac_handler, channel);
 #endif
    
@@ -96,7 +96,7 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch

    rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf));
    
-#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4)
    if ((channel <= 2) && (channel > 0))
    {
        /* set stm32 dac channel */
@@ -109,7 +109,7 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch
    }
 #endif  
    
-#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4)
    DAC_ChanConf.DAC_Trigger      = DAC_TRIGGER_NONE;             
    DAC_ChanConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
 #endif    
@@ -52,8 +52,12 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
    QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
    qspi_bus->QSPI_Handler = QSPI_Handler_config;

+#if defined(SOC_SERIES_STM32MP1)
+    while (cfg->max_hz < HAL_RCC_GetACLKFreq() / (i + 1))
+#else
    while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
-    {
+#endif
+   {
        i++;
        if (i == 255)
        {
@@ -353,7 +353,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)

 /**
  * @brief  This function send sdio request.
-  * @param  sdio  rthw_sdio
+  * @param  host  rt_mmcsd_host
  * @param  req   request
  * @retval None
  */
@@ -525,11 +525,11 @@ void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
 }

 /**
-  * @brief  This function delect sdcard.
+  * @brief  This function detect sdcard.
  * @param  host    rt_mmcsd_host
  * @retval 0x01
  */
-static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host)
+static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
 {
    LOG_D("try to detect device");
    return 0x01;
@@ -605,7 +605,7 @@ static const struct rt_mmcsd_host_ops ops =
 {
    rthw_sdio_request,
    rthw_sdio_iocfg,
-    rthw_sd_delect,
+    rthw_sd_detect,
    rthw_sdio_irq_update,
 };

@@ -44,7 +44,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f0xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32F0xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@ extern "C" {

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f1xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32F1xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32F2xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32F4xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32F7xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@ extern "C" {

 /* Includes ------------------------------------------------------------------*/
 #include "stm32g0xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32G0xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@ extern "C" {

 /* Includes ------------------------------------------------------------------*/
 #include "stm32g4xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32G4xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32H7xx_HAL_Driver
  * @{
@@ -28,7 +28,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32l0xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32L0xx_HAL_Driver
  * @{
@@ -59,6 +59,10 @@ if GetDepend(['RT_USING_ADC']):
    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c']
    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c']

+if GetDepend(['RT_USING_DAC']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c']
+
 if GetDepend(['RT_USING_RTC']):
    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c']
    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c']
@@ -28,7 +28,6 @@

 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx_hal_conf.h"
-#include <rtthread.h>

 /** @addtogroup STM32L4xx_HAL_Driver
  * @{
@@ -35,10 +35,6 @@ if GetDepend(['RT_USING_SERIAL']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c']

-#if GetDepend(['RT_USING_SPI']):
-#    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c']
-#    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c']
-
 if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pccard.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pcd.c']
@@ -49,14 +45,6 @@ if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
 if GetDepend(['RT_USING_CAN']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_can.c']

-#if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
-#    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c']
-#    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c']
-#    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c']
-
-if GetDepend(['BSP_USING_ETH']):
-    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c']
-
 if GetDepend(['BSP_USING_WWDG']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c']

@@ -73,13 +61,14 @@ if GetDepend(['RT_USING_WDT']):
 if GetDepend(['RT_USING_SDIO']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_delayblock.c']

 if GetDepend(['RT_USING_AUDIO']):
-    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s.c']
-    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s_ex.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai_ex.c']
-
+if GetDepend(['BSP_USING_DCMI']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dcmi.c']
+    
 if GetDepend(['BSP_USING_FMC']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fsmc.c']
@@ -102,6 +91,38 @@ if GetDepend(['BSP_USING_LTDC']):
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma2d.c']
    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dsi.c']

+if GetDepend(['BSP_USING_FDCAN']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c']
+
+if GetDepend(['BSP_USING_QSPI']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c']
+
+if GetDepend(['BSP_USING_SPDIFRX']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spdifrx.c']
+
+if GetDepend(['BSP_USING_DFSDM']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm_ex.c']
+
+if GetDepend(['BSP_USING_SDMMC']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c']
+
+if GetDepend(['BSP_USING_HASH']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hash.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hash_ex.c']
+
+if GetDepend(['BSP_USING_CRC']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c']
+
+if GetDepend(['BSP_USING_RNG']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rng.c']
+
+if GetDepend(['BSP_USING_CRYP']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp_ex.c']
+
 path = [cwd + '/STM32MP1xx_HAL_Driver/Inc',
    cwd + '/CMSIS/Device/ST/STM32MP1xx/Include',
    cwd + '/CMSIS/Core/Include',
@@ -3236,7 +3236,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
        {
          SD_hs[(8U*loop)+count]  = SDMMC_ReadFIFO(hsd->Instance);
        }
-        loop += 8U;
+        loop ++;
      }

      if((HAL_GetTick()-Timeout) >=  SDMMC_DATATIMEOUT)
@@ -3351,7 +3351,7 @@ uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
        {
          SD_hs[(8U*loop)+count]  = SDMMC_ReadFIFO(hsd->Instance);
        }
-        loop += 8U;
+        loop ++;
      }
      
      if((HAL_GetTick()-Timeout) >=  SDMMC_DATATIMEOUT)
@@ -41,6 +41,13 @@ menu "Onboard Peripheral Drivers"
        select RT_USING_DFS_ELMFAT
        default n

+    config BSP_USING_OV2640
+        bool "Enable camera (ov2640)"
+        select BSP_USING_DCMI
+        select BSP_USING_I2C
+        select BSP_USING_I2C2
+        default n
+
 endmenu

 menu "On-chip Peripheral Drivers"
@@ -98,28 +105,55 @@ menu "On-chip Peripheral Drivers"
        select RT_USING_SPI
        default n

-    menuconfig BSP_USING_I2C1
-        bool "Enable I2C1 BUS (software simulation)"
-        default n
-        select RT_USING_I2C
-        select RT_USING_I2C_BITOPS
-        select RT_USING_PIN
-        if BSP_USING_I2C1
-            comment "Notice: PH4 --> 116; PH5 --> 117"
-            config BSP_I2C1_SCL_PIN
-                int "i2c1 scl pin number"
-                range 1 176
-                default 116
-            config BSP_I2C1_SDA_PIN
-                int "I2C1 sda pin number"
-                range 1 176
-                default 117
-        endif
+    menuconfig BSP_USING_I2C
+    bool "Enable I2C BUS (software simulation)"
+    select RT_USING_I2C
+    select RT_USING_I2C_BITOPS
+    select RT_USING_PIN
+    default n
+    if BSP_USING_I2C
+        menuconfig BSP_USING_I2C1
+            bool "Enable I2C1 BUS (software simulation)"
+            default n
+            if BSP_USING_I2C1
+                comment "Notice: PH4 --> 116; PH5 --> 117"
+                config BSP_I2C1_SCL_PIN
+                    int "i2c1 scl pin number"
+                    range 1 176
+                    default 116
+                config BSP_I2C1_SDA_PIN
+                    int "I2C1 sda pin number"
+                    range 1 176
+                    default 117
+                        menuconfig BSP_USING_I2C2
+                    bool "Enable I2C2 BUS (software simulation)"
+                    default n
+            endif
+
+            menuconfig BSP_USING_I2C2
+            bool "Enable I2C2 BUS (software simulation)"
+            default n
+            if BSP_USING_I2C2
+                comment "Notice: PH13 --> 125; PH15 --> 127"
+                config BSP_I2C2_SCL_PIN
+                    int "i2c2 scl pin number"
+                    range 1 176
+                    default 127
+                config BSP_I2C2_SDA_PIN
+                    int "I2C2 sda pin number"
+                    range 1 176
+                    default 125
+            endif
+    endif

    config BSP_USING_ON_CHIP_FLASH
        bool "Enable on-chip FLASH"
        default n

+    config BSP_USING_DCMI
+        bool "Enable DCMI"
+        default n
+
    menuconfig BSP_USING_ONCHIP_RTC
        bool "Enable RTC"
        select RT_USING_RTC
@@ -17,6 +17,10 @@ if GetDepend(['BSP_USING_QSPI_FLASH']):
    src += Glob('ports/drv_qspi_flash.c')
 if GetDepend(['BSP_USING_SDMMC']):
    src += Glob('ports/drv_sdio.c')
+if GetDepend(['BSP_USING_DCMI']):
+    src += Glob('ports/drv_dcmi.c')
+if GetDepend(['BSP_USING_OV2640']):
+    src += Glob('ports/drv_ov2640.c')

 path = [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-07-27     thread-liu        the first version
+ */
+
+#ifndef __DRV_DCMI_H__
+#define __DRV_DCMI_H__
+
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct rt_dcmi_device
+{
+    struct rt_device parent;
+};
+
+extern DMA_HandleTypeDef hdma_dcmi;
+extern void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len);
+extern void DCMI_Start(void);
+extern void DCMI_Stop(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -39,7 +39,7 @@

 #ifdef __cplusplus
 extern "C" {
-#endif 
+#endif

 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -77,7 +77,7 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
 /* USER CODE END EV */

 /******************************************************************************/
-/*           Cortex-M4 Processor Interruption and Exception Handlers          */ 
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
 /******************************************************************************/
 /**
  * @brief This function handles Non maskable interrupt.
@@ -308,6 +308,16 @@ menu "On-chip Peripheral Drivers"
                default n
        endif

+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "Enable DAC1"
+                default n
+        endif
+
    menuconfig BSP_USING_ONCHIP_RTC
        bool "Enable RTC"
        select RT_USING_RTC
@@ -123,6 +123,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
@@ -199,12 +200,15 @@ CONFIG_RT_USING_PIN=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -231,6 +235,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -243,7 +248,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
@@ -265,6 +270,11 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set

 #
 # security packages
@@ -273,6 +283,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set

 #
 # language packages
@@ -289,6 +300,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set

 #
 # tools packages
@@ -307,6 +320,9 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set

 #
 # system packages
@@ -318,6 +334,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -330,6 +347,19 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set

 #
 # peripheral libraries and drivers
@@ -367,6 +397,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
@@ -374,6 +405,17 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_BEEP is not set
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set

 #
 # miscellaneous packages
@@ -403,13 +445,20 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_NNOM is not set
 # CONFIG_PKG_USING_LIBANN is not set
 # CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32MP1=y

@@ -427,6 +476,10 @@ CONFIG_BSP_USING_STLINK_TO_USART=y
 # CONFIG_BSP_USING_PWR is not set
 # CONFIG_BSP_USING_RCC is not set
 # CONFIG_BSP_USING_OPENAMP is not set
+# CONFIG_BSP_USING_RS485 is not set
+# CONFIG_BSP_USING_GBE is not set
+# CONFIG_BSP_USING_SDMMC is not set
+# CONFIG_BSP_USING_AUDIO is not set

 #
 # On-chip Peripheral Drivers
@@ -435,7 +488,6 @@ CONFIG_BSP_USING_GPIO=y
 # CONFIG_BSP_USING_WWDG is not set
 CONFIG_BSP_USING_UART=y
 # CONFIG_BSP_USING_UART3 is not set
-# CONFIG_BSP_UART3_RX_USING_DMA is not set
 CONFIG_BSP_USING_UART4=y
 # CONFIG_BSP_UART4_RX_USING_DMA is not set
 # CONFIG_BSP_UART4_TX_USING_DMA is not set
@@ -448,6 +500,8 @@ CONFIG_BSP_USING_UART4=y
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_CRC is not set
 # CONFIG_BSP_USING_RNG is not set
+# CONFIG_BSP_USING_HASH is not set
+# CONFIG_BSP_USING_CRYP is not set
 # CONFIG_BSP_USING_UDID is not set

 #
@@ -34,8 +34,8 @@
 #define HAL_MODULE_ENABLED  
 #define HAL_ADC_MODULE_ENABLED
 /*#define HAL_CEC_MODULE_ENABLED   */
-/*#define HAL_CRC_MODULE_ENABLED   */
-/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
 #define HAL_DAC_MODULE_ENABLED
 /*#define HAL_DCMI_MODULE_ENABLED   */
 /*#define HAL_DSI_MODULE_ENABLED   */
@@ -43,7 +43,7 @@
 /*#define HAL_DTS_MODULE_ENABLED   */
 /*#define HAL_ETH_MODULE_ENABLED   */
 /*#define HAL_FDCAN_MODULE_ENABLED   */
-/*#define HAL_HASH_MODULE_ENABLED   */
+#define HAL_HASH_MODULE_ENABLED
 /*#define HAL_HCD_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
@@ -56,9 +56,9 @@
 /*#define HAL_NOR_MODULE_ENABLED   */
 /*#define HAL_PCD_MODULE_ENABLED   */
 /*#define HAL_QSPI_MODULE_ENABLED   */
-/*#define HAL_RNG_MODULE_ENABLED   */
-/*#define HAL_SAI_MODULE_ENABLED   */
-/*#define HAL_SD_MODULE_ENABLED   */
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
 /*#define HAL_MMC_MODULE_ENABLED   */
 /*#define HAL_RTC_MODULE_ENABLED   */
 /*#define HAL_SMBUS_MODULE_ENABLED   */
@@ -50,7 +50,37 @@ menu "Onboard Peripheral Drivers"
            config RS485_UART_DEVICE_NAME
            string "the uart name for rs485"
            default "uart3"
+        endif
+    
+    config BSP_USING_GBE
+        bool "Enable Ethernet"
+        default n
+        select RT_USING_LWIP
+        
+    config BSP_USING_SDMMC
+        bool "Enable SDMMC (SD card)"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        default n

+    menuconfig BSP_USING_AUDIO
+        bool "Enable Audio Device"
+        select RT_USING_AUDIO
+        select BSP_USING_PMIC
+        select BSP_USING_SDMMC
+        select BSP_USING_I2C
+        select BSP_USING_I2C4
+        default n
+
+        if BSP_USING_AUDIO
+            config BSP_USING_AUDIO_PLAY
+            bool "Enable Audio Play"
+            default y
+
+            config BSP_USING_AUDIO_RECORD
+            bool "Enable Audio Record"
+            default n
        endif

 endmenu
@@ -196,7 +226,7 @@ menu "On-chip Peripheral Drivers"
                        range 1 176
                        default 117
                endif
-	    menuconfig BSP_USING_I2C3
+            menuconfig BSP_USING_I2C3
                bool "Enable I2C3 BUS (software simulation)"
                default n
                if BSP_USING_I2C3
@@ -210,6 +240,21 @@ menu "On-chip Peripheral Drivers"
                        range 1 191
                        default 181
                endif
+            menuconfig BSP_USING_I2C4
+                bool "Enable I2C4 BUS (software simulation)"
+                default n
+                if BSP_USING_I2C4
+                    comment "Notice: PD12 --> 60; PF15 --> 95" 
+                    config BSP_I2C4_SCL_PIN
+                        int "i2c4 scl pin number"
+                        range 1 191
+                        default 60
+                    config BSP_I2C4_SDA_PIN
+                        int "I2C4 sda pin number"
+                        range 1 191
+                        default 95
+                endif
+
        endif

    menuconfig BSP_USING_SPI
@@ -40,6 +40,23 @@ if GetDepend(['BSP_USING_PMIC']):
 if GetDepend(['BSP_USING_RS485']):
    src += Glob('ports/drv_rs485.c')

+if GetDepend(['BSP_USING_GBE']):
+    src += Glob('ports/drv_eth.c')
+
+if GetDepend(['BSP_USING_SDMMC']):
+    src += Glob('ports/drv_sdio.c')
+
+if GetDepend(['BSP_USING_AUDIO']):
+    src += Glob('ports/audio/drv_cs42l51.c')
+    src += Glob('ports/audio/drv_sound.c')
+    src += Glob('ports/audio/audio_play.c')
+
+if GetDepend(['BSP_USING_AUDIO_RECORD']):
+    src += Glob('ports/audio/drv_mic.c')
+
+if GetDepend(['(BSP_USING_RNG)']) or GetDepend(['(BSP_USING_HASH)']) or GetDepend(['(BSP_USING_CRC)']) or GetDepend(['BSP_USING_CRYP']):
+    src += Glob('ports/crypto/crypto_sample.c')
+
 if GetDepend(['BSP_USING_OPENAMP']):
    src +=  Glob('CubeMX_Config/CM4/Src/ipcc.c')
    src +=  Glob('CubeMX_Config/CM4/Src/openamp.c')
@@ -58,6 +75,7 @@ if GetDepend(['BSP_USING_OPENAMP']):
 path =  [cwd]
 path += [cwd + '/CubeMX_Config/CM4/Inc']
 path += [cwd + '/ports']
+path += [cwd + '/ports/audio']

 if GetDepend(['BSP_USING_OPENAMP']):
    path += [cwd + '/ports/OpenAMP']
@@ -32,7 +32,7 @@ extern "C" {

    
 #if defined(BSP_USING_OPENAMP)    
-#define STM32_SRAM_BEGIN             (uint32_t)0x10020000 
+#define STM32_SRAM_BEGIN             (uint32_t)0x10030000 
 #else
 #define STM32_SRAM_BEGIN             (uint32_t)0x2FFF0000     
 #endif
@@ -42,8 +42,6 @@ extern "C" {
 #define HEAP_BEGIN                    STM32_SRAM_BEGIN
 #define HEAP_END                      STM32_SRAM_END

-#define HEAP_END        STM32_SRAM_END
-
 void SystemClock_Config(void);

 extern void _Error_Handler(char *s, int num);
@@ -5,7 +5,7 @@
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 /*-Memory Regions-*/
 define symbol __ICFEDIT_region_text_start__ = 0x10000000;
-define symbol __ICFEDIT_region_text_end__   = 0x1001FFFF;
+define symbol __ICFEDIT_region_text_end__   = 0x1002FFFF;
 define symbol __ICFEDIT_region_data_start__ = 0x10030000;
 define symbol __ICFEDIT_region_data_end__   = 0x1003FFFF;
 /*-Sizes-*/
@@ -27,11 +27,6 @@ define symbol __OPENAMP_region_size__   = 0x8000;
 export symbol __OPENAMP_region_start__;
 export symbol __OPENAMP_region_size__;

-define symbol __SDMMC_region_start__   = 0x10048000;
-define symbol __SDMMC_region_size__    = 0x1FFFF;
-export symbol __SDMMC_region_start__;
-export symbol __SDMMC_region_size__;
-
 define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
 define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };

@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-07-02     thread-liu   first version
+ */
+
+#ifndef __DRV_CS42L51_H__
+#define __DRV_CS42L51_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+    
+typedef struct
+{
+  rt_err_t  (*init)(uint16_t , const char *, uint8_t);
+  void      (*deinit)(void);
+  uint32_t  (*read_id)(void);
+  uint32_t  (*play)(void);
+  uint32_t  (*pause)(void);
+  uint32_t  (*resume)(void);
+  uint32_t  (*stop)(void);
+  uint32_t  (*set_frequency)(uint32_t);
+  uint32_t  (*set_volume)(uint8_t);
+  uint32_t  (*get_volume)(void);
+  uint32_t  (*set_mute)(uint32_t);
+  uint32_t  (*set_output_mode)(uint8_t);
+  uint32_t  (*reset)(void);
+}AUDIO_DrvTypeDef;
+
+extern AUDIO_DrvTypeDef cs42l51_drv;
+
+/* CS42L51 register space */
+#define CS42L51_CHIP_ID			            0x1B
+#define CS42L51_CHIP_REV_A		            0x00
+#define CS42L51_CHIP_REV_B		            0x01
+
+#define CS42L51_CHIP_REV_ID		            0x01
+#define CS42L51_MK_CHIP_REV(a, b)	        ((a)<<3|(b))
+
+#define CS42L51_POWER_CTL1		            0x02
+#define CS42L51_POWER_CTL1_PDN_DACB	        (1<<6)
+#define CS42L51_POWER_CTL1_PDN_DACA	        (1<<5)
+#define CS42L51_POWER_CTL1_PDN_PGAB	        (1<<4)
+#define CS42L51_POWER_CTL1_PDN_PGAA	        (1<<3)
+#define CS42L51_POWER_CTL1_PDN_ADCB	        (1<<2)
+#define CS42L51_POWER_CTL1_PDN_ADCA	        (1<<1)
+#define CS42L51_POWER_CTL1_PDN		        (1<<0)
+
+#define CS42L51_MIC_POWER_CTL		        0x03
+#define CS42L51_MIC_POWER_CTL_AUTO	        (1<<7)
+#define CS42L51_MIC_POWER_CTL_SPEED(x)	    (((x)&3)<<5)
+#define CS42L51_QSM_MODE		            3
+#define CS42L51_HSM_MODE		            2
+#define	CS42L51_SSM_MODE		            1
+#define CS42L51_DSM_MODE		            0
+#define CS42L51_MIC_POWER_CTL_3ST_SP	    (1<<4)
+#define CS42L51_MIC_POWER_CTL_PDN_MICB	    (1<<3)
+#define CS42L51_MIC_POWER_CTL_PDN_MICA	    (1<<2)
+#define CS42L51_MIC_POWER_CTL_PDN_BIAS	    (1<<1)
+#define CS42L51_MIC_POWER_CTL_MCLK_DIV2	    (1<<0)
+
+#define CS42L51_INTF_CTL		            0x04
+#define CS42L51_INTF_CTL_LOOPBACK	        (1<<7)
+#define CS42L51_INTF_CTL_MASTER		        (1<<6)
+#define CS42L51_INTF_CTL_DAC_FORMAT(x)	    (((x)&7)<<3)
+#define CS42L51_DAC_DIF_LJ24		        0x00
+#define CS42L51_DAC_DIF_I2S		            0x01
+#define CS42L51_DAC_DIF_RJ24		        0x02
+#define CS42L51_DAC_DIF_RJ20		        0x03
+#define CS42L51_DAC_DIF_RJ18		        0x04
+#define CS42L51_DAC_DIF_RJ16		        0x05
+#define CS42L51_INTF_CTL_ADC_I2S	        (1<<2)
+#define CS42L51_INTF_CTL_DIGMIX		        (1<<1)
+#define CS42L51_INTF_CTL_MICMIX		        (1<<0)
+
+#define CS42L51_MIC_CTL			            0x05
+#define CS42L51_MIC_CTL_ADC_SNGVOL	        (1<<7)
+#define CS42L51_MIC_CTL_ADCD_DBOOST	        (1<<6)
+#define CS42L51_MIC_CTL_ADCA_DBOOST	        (1<<5)
+#define CS42L51_MIC_CTL_MICBIAS_SEL	        (1<<4)
+#define CS42L51_MIC_CTL_MICBIAS_LVL(x)	    (((x)&3)<<2)
+#define CS42L51_MIC_CTL_MICB_BOOST	        (1<<1)
+#define CS42L51_MIC_CTL_MICA_BOOST	        (1<<0)
+
+#define CS42L51_ADC_CTL			            0x06
+#define CS42L51_ADC_CTL_ADCB_HPFEN	        (1<<7)
+#define CS42L51_ADC_CTL_ADCB_HPFRZ	        (1<<6)
+#define CS42L51_ADC_CTL_ADCA_HPFEN	        (1<<5)
+#define CS42L51_ADC_CTL_ADCA_HPFRZ	        (1<<4)
+#define CS42L51_ADC_CTL_SOFTB		        (1<<3)
+#define CS42L51_ADC_CTL_ZCROSSB		        (1<<2)
+#define CS42L51_ADC_CTL_SOFTA		        (1<<1)
+#define CS42L51_ADC_CTL_ZCROSSA		        (1<<0)
+
+#define CS42L51_ADC_INPUT		            0x07
+#define CS42L51_ADC_INPUT_AINB_MUX(x)	    (((x)&3)<<6)
+#define CS42L51_ADC_INPUT_AINA_MUX(x)	    (((x)&3)<<4)
+#define CS42L51_ADC_INPUT_INV_ADCB	        (1<<3)
+#define CS42L51_ADC_INPUT_INV_ADCA	        (1<<2)
+#define CS42L51_ADC_INPUT_ADCB_MUTE	        (1<<1)
+#define CS42L51_ADC_INPUT_ADCA_MUTE	        (1<<0)
+
+#define CS42L51_DAC_OUT_CTL		            0x08
+#define CS42L51_DAC_OUT_CTL_HP_GAIN(x)	    (((x)&7)<<5)
+#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL	    (1<<4)
+#define CS42L51_DAC_OUT_CTL_INV_PCMB	    (1<<3)
+#define CS42L51_DAC_OUT_CTL_INV_PCMA	    (1<<2)
+#define CS42L51_DAC_OUT_CTL_DACB_MUTE	    (1<<1)
+#define CS42L51_DAC_OUT_CTL_DACA_MUTE	    (1<<0)
+
+#define CS42L51_DAC_CTL			            0x09
+#define CS42L51_DAC_CTL_DATA_SEL(x)	        (((x)&3)<<6)
+#define CS42L51_DAC_CTL_FREEZE		        (1<<5)
+#define CS42L51_DAC_CTL_DEEMPH		        (1<<3)
+#define CS42L51_DAC_CTL_AMUTE		        (1<<2)
+#define CS42L51_DAC_CTL_DACSZ(x)	        (((x)&3)<<0)
+
+#define CS42L51_ALC_PGA_CTL		            0x0A
+#define CS42L51_ALC_PGB_CTL		            0x0B
+#define CS42L51_ALC_PGX_ALCX_SRDIS	        (1<<7)
+#define CS42L51_ALC_PGX_ALCX_ZCDIS	        (1<<6)
+#define CS42L51_ALC_PGX_PGX_VOL(x)	        (((x)&0x1f)<<0)
+
+#define CS42L51_ADCA_ATT		            0x0C
+#define CS42L51_ADCB_ATT		            0x0D
+
+#define CS42L51_ADCA_VOL		            0x0E
+#define CS42L51_ADCB_VOL		            0x0F
+#define CS42L51_PCMA_VOL		            0x10
+#define CS42L51_PCMB_VOL		            0x11
+#define CS42L51_MIX_MUTE_ADCMIX		        (1<<7)
+#define CS42L51_MIX_VOLUME(x)		        (((x)&0x7f)<<0)
+
+#define CS42L51_BEEP_FREQ		            0x12
+#define CS42L51_BEEP_VOL		            0x13
+#define CS42L51_BEEP_CONF		            0x14
+
+#define CS42L51_TONE_CTL		            0x15
+#define CS42L51_TONE_CTL_TREB(x)	        (((x)&0xf)<<4)
+#define CS42L51_TONE_CTL_BASS(x)	        (((x)&0xf)<<0)
+
+#define CS42L51_AOUTA_VOL		            0x16
+#define CS42L51_AOUTB_VOL		            0x17
+#define CS42L51_PCM_MIXER		            0x18
+#define CS42L51_LIMIT_THRES_DIS		        0x19
+#define CS42L51_LIMIT_REL		            0x1A
+#define CS42L51_LIMIT_ATT		            0x1B
+#define CS42L51_ALC_EN			            0x1C
+#define CS42L51_ALC_REL			            0x1D
+#define CS42L51_ALC_THRES		            0x1E
+#define CS42L51_NOISE_CONF		            0x1F
+
+#define CS42L51_STATUS			            0x20
+#define CS42L51_STATUS_SP_CLKERR	        (1<<6)
+#define CS42L51_STATUS_SPEA_OVFL	        (1<<5)
+#define CS42L51_STATUS_SPEB_OVFL	        (1<<4)
+#define CS42L51_STATUS_PCMA_OVFL	        (1<<3)
+#define CS42L51_STATUS_PCMB_OVFL	        (1<<2)
+#define CS42L51_STATUS_ADCA_OVFL	        (1<<1)
+#define CS42L51_STATUS_ADCB_OVFL	        (1<<0)
+
+#define CS42L51_CHARGE_FREQ		            0x21
+#define CS42L51_FIRSTREG	                0x01
+
+enum play_type {
+    NONE,
+    OUT_HEADPHONE,
+    IN_MIC1,
+    IN_MIC2,
+    IN_LINE1,
+    IN_LINE2,
+    IN_LINE3,
+};
+
+/*
+ * Hack: with register 0x21, it makes 33 registers. Looks like someone in the
+ * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using
+ * 32 regs
+ */
+#define CS42L51_LASTREG		                0x20
+#define CS42L51_NUMREGS		                (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
+
+#define VOLUME_CONVERT(Volume)              ((Volume >= 100) ? 0 : ((uint8_t)(((Volume * 2) + 56))))
+#define VOLUME_INVERT(Volume)               (((Volume) == 0U) ? 100U : ((uint8_t)(((Volume) - 56U) / 2U)))
+     
+/* MUTE commands */
+#define AUDIO_MUTE_ON                       1
+#define AUDIO_MUTE_OFF                      0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -19,6 +19,8 @@
 #define LOG_TAG              "drv.pmic"
 #include <drv_log.h>

+#define I2C_NAME  "i2c3"
+
 static struct rt_i2c_bus_device *pmic_dev = RT_NULL;

 /* i2c read reg */
@@ -796,47 +798,47 @@ static rt_err_t rt_hw_pmic_init_register(void)
    stpmu1_write_reg(BUCK_ICC_TURNOFF_REG, 0x30);
    stpmu1_write_reg(LDO_ICC_TURNOFF_REG, 0x3b);

-  /* vddcore */
-  STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200);
-  STPMU1_Regulator_Enable(STPMU1_BUCK1);
+    /* vddcore */
+    STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200);
+    STPMU1_Regulator_Enable(STPMU1_BUCK1);

-  /* vddddr */
-  STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350);
-  STPMU1_Regulator_Enable(STPMU1_BUCK2);
+    /* vddddr */
+    STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350);
+    STPMU1_Regulator_Enable(STPMU1_BUCK2);

-  /* vdd */
-  STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300);
-  STPMU1_Regulator_Enable(STPMU1_BUCK3);
+    /* vdd */
+    STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300);
+    STPMU1_Regulator_Enable(STPMU1_BUCK3);

-  /* 3v3 */
-  STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300);
-  STPMU1_Regulator_Enable(STPMU1_BUCK4);
+//    /* 3v3 */
+//    STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300);
+//    STPMU1_Regulator_Enable(STPMU1_BUCK4);

-  /* vdda */
-  STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900);
-  STPMU1_Regulator_Enable(STPMU1_LDO1);
+    /* 1v8_audio */
+    STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 1800);
+    STPMU1_Regulator_Enable(STPMU1_LDO1);

-  /* 2v8 */
-  STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800);
-  STPMU1_Regulator_Enable(STPMU1_LDO2);
+    /* vdd_emmc */
+    STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2900);
+    STPMU1_Regulator_Enable(STPMU1_LDO2);

-  /* vtt_ddr  lod3 mode buck2/2 */
-  STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF);
-  STPMU1_Regulator_Enable(STPMU1_LDO3);
+    /* vdd1_ddr */
+    STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF);
+    STPMU1_Regulator_Enable(STPMU1_LDO3);

-  /* vdd_usb */
-  STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300);
-  STPMU1_Regulator_Enable(STPMU1_LDO4);
+    /* vdd_usb */
+    STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300);
+    STPMU1_Regulator_Enable(STPMU1_LDO4);

-  /* vdd_sd */
-  STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900);
-  STPMU1_Regulator_Enable(STPMU1_LDO5);
+    /* vdda */
+    STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900);
+    STPMU1_Regulator_Enable(STPMU1_LDO5);

-  /* 1v8 */
-  STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800);
-  STPMU1_Regulator_Enable(STPMU1_LDO6);
+    /* 2v8 */
+    STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 2800);
+    STPMU1_Regulator_Enable(STPMU1_LDO6);

-  STPMU1_Regulator_Enable(STPMU1_VREFDDR);
+    STPMU1_Regulator_Enable(STPMU1_VREFDDR);

    return RT_EOK;
 }
@@ -884,7 +886,7 @@ static int pmic_init(void)
    {
        BSP_PMIC_MspInit();
        
-        result = rt_hw_pmic_init("i2c3");
+        result = rt_hw_pmic_init(I2C_NAME);
        if(result != RT_EOK)
        {
            LOG_D("stpmic init failed: %02x", result);
@@ -893,10 +895,7 @@ static int pmic_init(void)
        }
        
        rt_hw_pmic_init_register();
-    }
-    
-    if(IS_ENGINEERING_BOOT_MODE())
-    {
+        
        __HAL_RCC_VREF_CLK_ENABLE();
        HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE);
        HAL_SYSCFG_EnableVREFBUF();
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-16     thread-liu   first version
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+#include <string.h>
+#include <drivers/mmcsd_core.h>
+#include <drivers/sdio.h>
+
+#define SDIO_BUFF_SIZE       4096
+#define SDIO_ALIGN_LEN       32
+
+#ifndef SDIO_BASE_ADDRESS
+#define SDIO_BASE_ADDRESS    (SDMMC1)
+#endif
+
+#ifndef SDIO_CLOCK_FREQ
+#define SDIO_CLOCK_FREQ      (99U * 1000 * 1000)
+#endif
+
+#ifndef SDIO_BUFF_SIZE
+#define SDIO_BUFF_SIZE       (4096)
+#endif
+
+#ifndef SDIO_ALIGN_LEN
+#define SDIO_ALIGN_LEN       (32)
+#endif
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ        (50 * 1000 * 1000)
+#endif
+
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+
+#define SDMMC_POWER_OFF                      (0x00U)
+#define SDMMC_POWER_UP                       (0x02U)
+#define SDMMC_POWER_ON                       (0x03U)
+
+#define SDIO_ERRORS \
+    (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
+     SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
+     SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
+     SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
+
+#define SDIO_MASKR_ALL \
+    (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
+     SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
+     SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
+
+#define HW_SDIO_DATATIMEOUT                 (0xFFFFFFFFU)
+
+struct stm32_sdio
+{
+    volatile rt_uint32_t power;         /* offset 0x00 */
+    volatile rt_uint32_t clkcr;         /* offset 0x04 */
+    volatile rt_uint32_t arg;           /* offset 0x08 */
+    volatile rt_uint32_t cmd;           /* offset 0x0C */
+    volatile rt_uint32_t respcmd;       /* offset 0x10 */
+    volatile rt_uint32_t resp1;         /* offset 0x14 */
+    volatile rt_uint32_t resp2;         /* offset 0x18 */
+    volatile rt_uint32_t resp3;         /* offset 0x1C */
+    volatile rt_uint32_t resp4;         /* offset 0x20 */
+    volatile rt_uint32_t dtimer;        /* offset 0x24 */
+    volatile rt_uint32_t dlen;          /* offset 0x28 */
+    volatile rt_uint32_t dctrl;         /* offset 0x2C */
+    volatile rt_uint32_t dcount;        /* offset 0x30 */
+    volatile rt_uint32_t sta;           /* offset 0x34 */
+    volatile rt_uint32_t icr;           /* offset 0x38 */
+    volatile rt_uint32_t mask;          /* offset 0x3C */
+    volatile rt_uint32_t acktimer;      /* offset 0x40 */
+    volatile rt_uint32_t reserved0[3];  /* offset 0x44 ~ 0x4C */
+    volatile rt_uint32_t idmatrlr;      /* offset 0x50 */
+    volatile rt_uint32_t idmabsizer;    /* offset 0x54 */
+    volatile rt_uint32_t idmabase0r;    /* offset 0x58 */
+    volatile rt_uint32_t idmabase1r;    /* offset 0x5C */
+    volatile rt_uint32_t reserved1[1];  /* offset 0x60 */
+    volatile rt_uint32_t idmalar;
+    volatile rt_uint32_t idmabar;
+    volatile rt_uint32_t reserved2[5];
+    volatile rt_uint32_t fifo;          
+    volatile rt_uint32_t reserved3[220];
+    volatile rt_uint32_t verr;
+    volatile rt_uint32_t ipidr;
+    volatile rt_uint32_t sidr;
+};
+
+typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
+
+struct stm32_sdio_des
+{
+    struct stm32_sdio *hw_sdio;
+    sdio_clk_get clk_get;
+};
+
+/* stm32 sdio dirver class */
+struct stm32_sdio_class
+{
+    struct stm32_sdio_des *des;
+    const struct stm32_sdio_config *cfg;
+    struct rt_mmcsd_host host;
+};
+
+extern void stm32_mmcsd_change(void);
+
+#endif /* __DRV_SDIO_H__ */
@@ -34,16 +34,16 @@
 #define HAL_MODULE_ENABLED  
 #define HAL_ADC_MODULE_ENABLED
 /*#define HAL_CEC_MODULE_ENABLED   */
-/*#define HAL_CRC_MODULE_ENABLED   */
-/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
 #define HAL_DAC_MODULE_ENABLED
-/*#define HAL_DCMI_MODULE_ENABLED   */
+#define HAL_DCMI_MODULE_ENABLED
 /*#define HAL_DSI_MODULE_ENABLED   */
-/*#define HAL_DFSDM_MODULE_ENABLED   */
+#define HAL_DFSDM_MODULE_ENABLED
 /*#define HAL_DTS_MODULE_ENABLED   */
 /*#define HAL_ETH_MODULE_ENABLED   */
-/*#define HAL_FDCAN_MODULE_ENABLED   */
-/*#define HAL_HASH_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
 /*#define HAL_HCD_MODULE_ENABLED   */
 #define HAL_HSEM_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
@@ -55,14 +55,14 @@
 /*#define HAL_NAND_MODULE_ENABLED   */
 /*#define HAL_NOR_MODULE_ENABLED   */
 /*#define HAL_PCD_MODULE_ENABLED   */
-/*#define HAL_QSPI_MODULE_ENABLED   */
-/*#define HAL_RNG_MODULE_ENABLED   */
-/*#define HAL_SAI_MODULE_ENABLED   */
-/*#define HAL_SD_MODULE_ENABLED   */
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
 /*#define HAL_MMC_MODULE_ENABLED   */
 /*#define HAL_RTC_MODULE_ENABLED   */
 /*#define HAL_SMBUS_MODULE_ENABLED   */
-/*#define HAL_SPDIFRX_MODULE_ENABLED   */
+#define HAL_SPDIFRX_MODULE_ENABLED
 #define HAL_SPI_MODULE_ENABLED
 /*#define HAL_SRAM_MODULE_ENABLED   */
 /*#define HAL_TAMP_MODULE_ENABLED   */
@@ -153,6 +153,8 @@
  #define CSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
 #endif /* CSI_VALUE */

+#define  USE_SD_TRANSCEIVER           1U
+   
 /**
  * @brief External clock source for I2S peripheral
  *        This value is used by the I2S HAL module to compute the I2S clock source 
@@ -13,12 +13,69 @@ CubeMX_Config/Common/System/system_stm32mp1xx.c
 CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
 ''')

+if GetDepend(['BSP_USING_SPI1']):
+    src += Glob('ports/spi_sample.c')
+
 if GetDepend(['BSP_USING_PMIC']):
    src += Glob('ports/drv_pmic.c')

 if GetDepend(['BSP_USING_NAND']):
    src += Glob('ports/drv_nand.c')

+if GetDepend(['BSP_USING_GBE']):
+    src += Glob('ports/eth/drv_eth.c')
+
+if GetDepend(['BSP_USING_SD_CARD']):
+    src += Glob('ports/drv_sdcard.c')
+
+if GetDepend(['BSP_USING_EMMC']):
+    src += Glob('ports/drv_emmc.c')
+
+if GetDepend(['BSP_USING_AUDIO']):
+    src += Glob('ports/drv_wm8994.c')
+    src += Glob('ports/drv_sound.c')
+
+if GetDepend(['BSP_USING_DCMI']):
+    src += Glob('ports/drv_dcmi.c')
+    src += Glob('ports/drv_ov5640.c')
+
+if GetDepend(['BSP_USING_MFX']):
+    src += Glob('ports/drv_mfx.c')
+    src += Glob('ports/mfxstm32l152.c')
+
+if GetDepend(['BSP_USING_FDCAN']):
+    src += Glob('ports/drv_fdcan.c')
+
+if GetDepend(['BSP_USING_QSPI']):
+    src += Glob('ports/drv_qspi_flash.c')
+
+if GetDepend(['BSP_USING_SPDIFRX']):
+    src += Glob('ports/drv_spdifrx.c')
+
+if GetDepend(['BSP_USING_DFSDM']):
+    src += Glob('ports/drv_dfsdm.c')
+
+if GetDepend(['BSP_USING_WWDG']):
+    src += Glob('ports/drv_wwdg.c')
+
+if GetDepend(['BSP_USING_EXTI']):
+    src += Glob('ports/drv_exti.c')
+
+if GetDepend(['BSP_USING_RNG']) or GetDepend(['BSP_USING_HASH']) or GetDepend(['BSP_USING_CRC']) or GetDepend(['BSP_USING_CRYP']):
+    src += Glob('ports/crypto_sample.c')
+
+if GetDepend(['BSP_USING_PWR']):
+    src += Glob('ports/drv_pwr.c')
+
+if GetDepend(['BSP_USING_LPTIM1']):
+    src += Glob('ports/drv_lptim.c')
+
+if GetDepend(['BSP_USING_RS485']):
+    src += Glob('ports/drv_rs485.c')
+
+if GetDepend(['BSP_USING_TIM14']):
+    src += Glob('ports/timer_sample.c')
+
 if GetDepend(['BSP_USING_OPENAMP']):
    src +=  Glob('CubeMX_Config/CM4/Src/ipcc.c')
    src +=  Glob('CubeMX_Config/CM4/Src/openamp.c')
@@ -45,6 +102,9 @@ if GetDepend(['BSP_USING_OPENAMP']):
    path += [cwd + '/ports/OpenAMP/virtual_driver']
    path += [cwd + '/CubeMX_Config/CM4/Inc']

+if GetDepend(['BSP_USING_GBE']):
+    path += [cwd + '/ports/eth']
+
 startup_path_prefix = SDK_LIB

 if rtconfig.CROSS_TOOL == 'gcc':
@@ -23,16 +23,11 @@ extern "C" {
 #endif

 #define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)  
-#if defined(BSP_USING_OPENAMP)
-#define STM32_FLASH_SIZE             (64 * 1024)
-#else
-#define STM32_FLASH_SIZE             (256 * 1024)    
-#endif
+#define STM32_FLASH_SIZE             (191 * 1024)
 #define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))

-    
 #if defined(BSP_USING_OPENAMP)    
-#define STM32_SRAM_BEGIN             (uint32_t)0x10020000 
+#define STM32_SRAM_BEGIN             (uint32_t)0x10030000 
 #else
 #define STM32_SRAM_BEGIN             (uint32_t)0x2FFF0000     
 #endif
@@ -5,7 +5,7 @@
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 /*-Memory Regions-*/
 define symbol __ICFEDIT_region_text_start__ = 0x10000000;
-define symbol __ICFEDIT_region_text_end__   = 0x1001FFFF;
+define symbol __ICFEDIT_region_text_end__   = 0x1002FFFF;
 define symbol __ICFEDIT_region_data_start__ = 0x10030000;
 define symbol __ICFEDIT_region_data_end__   = 0x1003FFFF;
 /*-Sizes-*/
@@ -28,11 +28,6 @@ define symbol __OPENAMP_region_size__   = 0x8000;
 export symbol __OPENAMP_region_start__;
 export symbol __OPENAMP_region_size__;

-define symbol __SDMMC_region_start__   = 0x10048000;
-define symbol __SDMMC_region_size__    = 0x1FFFF;
-export symbol __SDMMC_region_start__;
-export symbol __SDMMC_region_size__;
-
 define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
 define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };

--- a/Show More
+++ b/Show More