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[components][drivers]add pic-gic (#8388)

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This commit is contained in:
zms123456
2024-02-29 09:39:56 +08:00
committed by GitHub
parent 3816d9fba4
commit 195f94ef1d
20 changed files with 2656 additions and 236 deletions
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libcpu/aarch64/common/SConscript
+3
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@@ -10,6 +10,9 @@ CPPPATH = [cwd]
if GetDepend('RT_USING_OFW') == False:
SrcRemove(src, ['setup.c', 'cpu_psci.c', 'psci.c'])
if GetDepend('RT_USING_PIC') == True:
SrcRemove(src, ['gicv3.c', 'gic.c', 'interrupt.c', 'gtimer.c'])
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
libcpu/aarch64/common/cpu.h
+59
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@@ -27,7 +27,66 @@ struct cpu_ops_t
int (*cpu_boot)(rt_uint32_t id, rt_uint64_t entry);
void (*cpu_shutdown)(void);
};
#define sysreg_32(op1, crn, crm, op2) s3_##op1 ##_##crn ##_##crm ##_##op2
#define sysreg_64(op1, crn, crm, op2) sysreg_32(op1, crn, crm, op2)
#define MPIDR_AFFINITY_MASK 0x000000ff00ffffffUL
#define MPIDR_LEVEL_BITS_SHIFT 3
#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
#define MPIDR_LEVEL_SHIFT(level) (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
#define MPIDR_AFFINITY_LEVEL(mpidr, level) (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
/* GIC registers */
#define ICC_IAR0_SYS sysreg_64(0, c12, c8, 0)
#define ICC_IAR1_SYS sysreg_64(0, c12, c12, 0)
#define ICC_EOIR0_SYS sysreg_64(0, c12, c8, 1)
#define ICC_EOIR1_SYS sysreg_64(0, c12, c12, 1)
#define ICC_HPPIR0_SYS sysreg_64(0, c12, c8, 2)
#define ICC_HPPIR1_SYS sysreg_64(0, c12, c12, 2)
#define ICC_BPR0_SYS sysreg_64(0, c12, c8, 3)
#define ICC_BPR1_SYS sysreg_64(0, c12, c12, 3)
#define ICC_DIR_SYS sysreg_64(0, c12, c11, 1)
#define ICC_PMR_SYS sysreg_64(0, c4, c6, 0)
#define ICC_RPR_SYS sysreg_64(0, c12, c11, 3)
#define ICC_CTLR_SYS sysreg_64(0, c12, c12, 4)
#define ICC_SRE_SYS sysreg_64(0, c12, c12, 5)
#define ICC_IGRPEN0_SYS sysreg_64(0, c12, c12, 6)
#define ICC_IGRPEN1_SYS sysreg_64(0, c12, c12, 7)
#define ICC_SGI0R_SYS sysreg_64(0, c12, c11, 7)
#define ICC_SGI1R_SYS sysreg_64(0, c12, c11, 5)
#define ICC_ASGI1R_SYS sysreg_64(0, c12, c11, 6)
/* Arch timer registers */
#define CNTP_CTL CNTP_CTL_EL0 /* EL1 Physical Timer */
#define CNTHP_CTL CNTHP_CTL_EL2 /* EL2 Non-secure Physical Timer */
#define CNTHPS_CTL CNTHPS_CTL_EL2 /* EL2 Secure Physical Timer */
#define CNTPS_CTL CNTPS_CTL_EL1 /* EL3 Physical Timer */
#define CNTV_CTL CNTV_CTL_EL0 /* EL1 Virtual Timer */
#define CNTHV_CTL CNTHV_CTL_EL2 /* EL2 Non-secure Virtual Timer */
#define CNTHVS_CTL CNTHVS_CTL_EL2 /* EL2 Secure Virtual Timer */
#define CNTP_CVAL CNTP_CVAL_EL0
#define CNTHP_CVAL CNTHP_CVAL_EL2
#define CNTHPS_CVAL CNTHPS_CVAL_EL2
#define CNTPS_CVAL CNTPS_CVAL_EL1
#define CNTV_CVAL CNTV_CVAL_EL0
#define CNTHV_CVAL CNTHV_CVAL_EL2
#define CNTHVS_CVAL CNTHVS_CVAL_EL2
#define CNTP_TVAL CNTP_TVAL_EL0
#define CNTHP_TVAL CNTHP_TVAL_EL2
#define CNTHPS_TVAL CNTHPS_TVAL_EL2
#define CNTPS_TVAL CNTPS_TVAL_EL1
#define CNTV_TVAL CNTV_TVAL_EL0
#define CNTHV_TVAL CNTHV_TVAL_EL2
#define CNTHVS_TVAL CNTHVS_TVAL_EL2
#define CNTPCT CNTPCT_EL0
#define CNTVCT CNTVCT_EL0
#define CNTFRQ CNTFRQ_EL0
extern rt_uint64_t rt_cpu_mpidr_table[];
#endif /* __RT_HW_CPU_H__ */
libcpu/aarch64/common/cpuport.h
+6
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@@ -37,6 +37,12 @@ typedef struct {
#define rt_hw_cpu_relax() rt_hw_barrier(yield)
#define rt_hw_sysreg_write(sysreg, val) \
__asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
#define rt_hw_sysreg_read(sysreg, val) \
__asm__ volatile ("mrs %0, "RT_STRINGIFY(sysreg)"":"=r"((val)))
void _thread_start(void);
#ifdef RT_USING_CPU_FFS
libcpu/aarch64/common/setup.c
+14 -5
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@@ -22,10 +22,7 @@
#include <setup.h>
#include <stdlib.h>
#include <ioremap.h>
#include <drivers/ofw.h>
#include <drivers/ofw_fdt.h>
#include <drivers/ofw_raw.h>
#include <drivers/core/dm.h>
#include <rtdevice.h>
#define rt_sysreg_write(sysreg, val) \
__asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
@@ -166,6 +163,8 @@ void rt_hw_common_setup(void)
static struct mem_desc platform_mem_desc;
void *kernel_start, *kernel_end, *memheap_start = RT_NULL, *memheap_end = RT_NULL;
system_vectors_init();
#ifdef RT_USING_SMART
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
#else
@@ -336,6 +335,10 @@ void rt_hw_common_setup(void)
cpu_info_init();
#ifdef RT_USING_PIC
rt_pic_init();
rt_pic_irq_init();
#else
/* initialize hardware interrupt */
rt_hw_interrupt_init();
@@ -344,8 +347,9 @@ void rt_hw_common_setup(void)
/* initialize timer for os tick */
rt_hw_gtimer_init();
#endif
#ifdef RT_USING_COMPONENTS_INIT
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
@@ -421,9 +425,14 @@ rt_weak void rt_hw_secondary_cpu_bsp_start(void)
rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
#ifdef RT_USING_PIC
rt_pic_irq_init();
#else
rt_hw_interrupt_init();
#endif
rt_dm_secondary_cpu_init();
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
rt_hw_interrupt_umask(RT_STOP_IPI);
libcpu/aarch64/common/trap.c
+14
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@@ -166,6 +166,7 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc);
}
#ifndef RT_USING_PIC
void rt_hw_trap_irq(void)
{
#ifdef SOC_BCM283x
@@ -267,6 +268,12 @@ void rt_hw_trap_irq(void)
rt_hw_interrupt_ack(ir);
#endif
}
#else
void rt_hw_trap_irq(void)
{
rt_pic_do_traps();
}
#endif
#ifdef RT_USING_SMART
#define DBG_CHECK_EVENT(regs, esr) dbg_check_event(regs, esr)
@@ -274,6 +281,7 @@ void rt_hw_trap_irq(void)
#define DBG_CHECK_EVENT(regs, esr) (0)
#endif
#ifndef RT_USING_PIC
void rt_hw_trap_fiq(void)
{
void *param;
@@ -296,6 +304,12 @@ void rt_hw_trap_fiq(void)
/* end of interrupt */
rt_hw_interrupt_ack(ir);
}
#else
void rt_hw_trap_fiq(void)
{
rt_pic_do_traps();
}
#endif
void print_exception(unsigned long esr, unsigned long epc);
void SVC_Handler(struct rt_hw_exp_stack *regs);