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[components][drivers]add pic-gic (#8388)

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This commit is contained in:
zms123456
2024-02-29 09:39:56 +08:00
committed by GitHub
parent 3816d9fba4
commit 195f94ef1d
20 changed files with 2656 additions and 236 deletions
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8
components/drivers/core/dm.c
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@@ -263,7 +263,7 @@ int rt_dm_dev_get_irq_count(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
#if defined(RT_USING_OFW) && defined(RT_USING_PIC)
if (dev->ofw_node)
{
return ofw_api_call(get_irq_count, dev->ofw_node);
@@ -277,7 +277,7 @@ int rt_dm_dev_get_irq(rt_device_t dev, int index)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
#if defined(RT_USING_OFW) && defined(RT_USING_PIC)
if (dev->ofw_node)
{
return ofw_api_call(get_irq, dev->ofw_node, index);
@@ -291,7 +291,7 @@ int rt_dm_dev_get_irq_by_name(rt_device_t dev, const char *name)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
#if defined(RT_USING_OFW) && defined(RT_USING_PIC)
if (dev->ofw_node)
{
return ofw_api_call(get_irq_by_name, dev->ofw_node, name);
@@ -327,7 +327,7 @@ void rt_dm_dev_unbind_fwdata(rt_device_t dev, void *fw_np)
RT_ASSERT(dev!= RT_NULL);
#ifdef RT_USING_OFW
void *dev_fw_np;
void *dev_fw_np = RT_NULL;
if (!dev->ofw_node && fw_np)
{

48
components/drivers/include/drivers/pic.h
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@@ -25,6 +25,19 @@ struct rt_pic_irq;
struct rt_pic
{
/*
* Other IC is not implemented with PIC but rt_device/object, we need to
* identify with this object:
*
* struct rt_ic_XYZ_device
* {
* struct rt_device parent;
* struct rt_pic pic;
* ...
* };
*/
struct rt_object parent;
rt_list_t list;
struct rt_pic_ops *ops;
@@ -32,8 +45,6 @@ struct rt_pic
void *priv_data;
void *user_data;
struct rt_pic *parent;
int irq_start;
rt_size_t irq_nr;
struct rt_pic_irq *pirqs;
@@ -66,6 +77,9 @@ struct rt_pic_ops
int (*irq_map)(struct rt_pic *pic, int hwirq, rt_uint32_t mode);
rt_err_t (*irq_parse)(struct rt_pic *pic, struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq);
#define RT_PIC_F_IRQ_ROUTING RT_BIT(0) /* Routing ISR when cascade */
rt_ubase_t flags;
};
struct rt_pic_isr
@@ -95,6 +109,9 @@ struct rt_pic_irq
rt_uint32_t priority;
RT_DECLARE_BITMAP(affinity, RT_CPUS_NR);
rt_list_t list;
rt_list_t children_nodes;
struct rt_pci_msi_desc *msi_desc;
struct rt_pic_isr isr;
@@ -102,8 +119,12 @@ struct rt_pic_irq
struct rt_spinlock rw_lock;
struct rt_pic *pic;
struct rt_pic_irq *parent;
};
void rt_pic_default_name(struct rt_pic *pic);
struct rt_pic *rt_pic_dynamic_cast(void *ptr);
rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr);
int rt_pic_config_ipi(struct rt_pic *pic, int ipi_index, int hwirq);
@@ -120,9 +141,10 @@ rt_inline struct rt_pic_irq *rt_pic_find_irq(struct rt_pic *pic, int irq_index)
}
struct rt_pic_irq *rt_pic_find_ipi(struct rt_pic *pic, int ipi_index);
struct rt_pic_irq *rt_pic_find_pirq(struct rt_pic *pic, int irq);
int rt_pic_cascade(struct rt_pic *pic, struct rt_pic *parent_pic, int hwirq, rt_uint32_t mode);
void rt_pic_uncascade(struct rt_pic *pic, int irq);
rt_err_t rt_pic_cascade(struct rt_pic_irq *pirq, int parent_irq);
rt_err_t rt_pic_uncascade(struct rt_pic_irq *pirq);
rt_err_t rt_pic_attach_irq(int irq, rt_isr_handler_t handler, void *uid, const char *name, int flags);
rt_err_t rt_pic_detach_irq(int irq, void *uid);
@@ -150,15 +172,15 @@ rt_err_t rt_pic_irq_set_triger_mode(int irq, rt_uint32_t mode);
rt_uint32_t rt_pic_irq_get_triger_mode(int irq);
void rt_pic_irq_send_ipi(int irq, rt_bitmap_t *cpumask);
void rt_pic_irq_parent_enable(struct rt_pic *ppic, struct rt_pic_irq *pirq);
void rt_pic_irq_parent_disable(struct rt_pic *ppic, struct rt_pic_irq *pirq);
void rt_pic_irq_parent_ack(struct rt_pic *ppic, struct rt_pic_irq *pirq);
void rt_pic_irq_parent_mask(struct rt_pic *ppic, struct rt_pic_irq *pirq);
void rt_pic_irq_parent_unmask(struct rt_pic *ppic, struct rt_pic_irq *pirq);
void rt_pic_irq_parent_eoi(struct rt_pic *ppic, struct rt_pic_irq *pirq);
rt_err_t rt_pic_irq_parent_set_priority(struct rt_pic *ppic, struct rt_pic_irq *pirq, rt_uint32_t priority);
rt_err_t rt_pic_irq_parent_set_affinity(struct rt_pic *ppic, struct rt_pic_irq *pirq, rt_bitmap_t *affinity);
rt_err_t rt_pic_irq_parent_set_triger_mode(struct rt_pic *ppic, struct rt_pic_irq *pirq, rt_uint32_t mode);
void rt_pic_irq_parent_enable(struct rt_pic_irq *pirq);
void rt_pic_irq_parent_disable(struct rt_pic_irq *pirq);
void rt_pic_irq_parent_ack(struct rt_pic_irq *pirq);
void rt_pic_irq_parent_mask(struct rt_pic_irq *pirq);
void rt_pic_irq_parent_unmask(struct rt_pic_irq *pirq);
void rt_pic_irq_parent_eoi(struct rt_pic_irq *pirq);
rt_err_t rt_pic_irq_parent_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority);
rt_err_t rt_pic_irq_parent_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity);
rt_err_t rt_pic_irq_parent_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode);
#define RT_PIC_OFW_DECLARE(name, ids, handler) RT_OFW_STUB_EXPORT(name, ids, pic, handler)

17
components/drivers/include/dt-bindings/size.h Normal file
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@@ -0,0 +1,17 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DT_BINDINGS_SIZE_H__
#define __DT_BINDINGS_SIZE_H__
#define SIZE_KB 1024
#define SIZE_MB (1024 * SIZE_KB)
#define SIZE_GB (1024 * SIZE_MB)
#define SIZE_ALIGN(size, align) (((size) + (align) - 1) & ~((align) - 1))
#define SIZE_ALIGN_DOWN(size, align) ((size) & ~((align) - 1))
#endif /* __DT_BINDINGS_SIZE_H__ */

3
components/drivers/ofw/SConscript
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@@ -11,6 +11,9 @@ CPPPATH = [cwd, cwd + '/../include']
src = Glob('*.c')
if GetDepend('RT_USING_PIC') == False:
SrcRemove(src, ['irq.c'])
group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
for d in list:

26
components/drivers/ofw/irq.c
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@@ -196,6 +196,9 @@ static rt_err_t ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_arg
break;
}
map_len = sizeof(fdt32_t);
map_mask_len = sizeof(fdt32_t);
err = -RT_EINVAL;
addr = irq_args->data;
@@ -491,7 +494,7 @@ rt_err_t rt_ofw_parse_irq_cells(struct rt_ofw_node *np, int index, struct rt_ofw
struct rt_ofw_node *rt_ofw_find_irq_parent(struct rt_ofw_node *np, int *out_interrupt_cells)
{
rt_ofw_foreach_parent_node(np)
for (np = rt_ofw_node_get(np); np; np = rt_ofw_get_next_parent(np))
{
rt_phandle ic_phandle;
@@ -523,7 +526,7 @@ static int ofw_map_irq(struct rt_ofw_cell_args *irq_args)
{
int irq;
struct rt_ofw_node *ic_np = irq_args->data;
struct rt_pic *pic = rt_ofw_data(ic_np);
struct rt_pic *pic = rt_pic_dynamic_cast(rt_ofw_data(ic_np));
/* args.data is "interrupt-controller" */
if (pic)
@@ -611,7 +614,26 @@ int rt_ofw_get_irq(struct rt_ofw_node *np, int index)
if (irq >= 0)
{
rt_phandle cpu_phandle;
irq = ofw_map_irq(&irq_args);
if (irq >= 0 && !rt_ofw_prop_read_u32_index(np, "interrupt-affinity", index, &cpu_phandle))
{
rt_uint64_t cpuid = rt_ofw_get_cpu_id(rt_ofw_find_node_by_phandle(cpu_phandle));
if ((rt_int64_t)cpuid >= 0)
{
RT_DECLARE_BITMAP(affinity, RT_CPUS_NR) = { 0 };
rt_bitmap_set_bit(affinity, cpuid);
if (rt_pic_irq_set_affinity(irq, affinity) == -RT_ENOSYS)
{
LOG_W("%s irq affinity init fail", np->full_name);
}
}
}
}
}
else

19
components/drivers/pic/Kconfig
View File

@@ -9,3 +9,22 @@ config MAX_HANDLERS
depends on RT_USING_PIC
range 1 4294967294
default 256
config RT_PIC_ARM_GIC
bool "ARM GICv2/v1"
depends on RT_USING_PIC
select RT_USING_OFW
default n
config RT_PIC_ARM_GIC_V3
bool "ARM GICv3"
depends on RT_USING_PIC
select RT_USING_OFW
default n
config RT_PIC_ARM_GIC_MAX_NR
int
depends on RT_USING_PIC
depends on RT_PIC_ARM_GIC
default 2 if SOC_REALVIEW
default 1

11
components/drivers/pic/SConscript
View File

@@ -8,7 +8,16 @@ if not GetDepend(['RT_USING_PIC']):
cwd = GetCurrentDir()
CPPPATH = [cwd + '/../include']
src = ['pic.c']
src = ['pic.c', 'pic_rthw.c']
if GetDepend(['RT_PIC_ARM_GIC']) or GetDepend(['RT_PIC_ARM_GIC_V3']):
src += ['pic-gic-common.c']
if GetDepend(['RT_PIC_ARM_GIC']):
src += ['pic-gicv2.c']
if GetDepend(['RT_PIC_ARM_GIC_V3']):
src += ['pic-gicv3.c']
group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)

175
components/drivers/pic/pic-gic-common.c Normal file
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@@ -0,0 +1,175 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-01-30 GuEe-GUI first version
*/
#include <rthw.h>
#include <rtthread.h>
#define DBG_TAG "pic.gic*"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#include <drivers/pic.h>
#include "pic-gicv2.h"
#include "pic-gic-common.h"
void gic_common_init_quirk_ofw(const struct rt_ofw_node *ic_np, const struct gic_quirk *quirks, void *data)
{
for (; quirks->desc; ++quirks)
{
if (!quirks->compatible || !rt_ofw_node_is_compatible(ic_np, quirks->compatible))
{
continue;
}
RT_ASSERT(quirks->init != RT_NULL);
if (!quirks->init(data))
{
LOG_I("Enable workaround for %s", quirks->desc);
}
}
}
void gic_common_init_quirk_hw(rt_uint32_t iidr, const struct gic_quirk *quirks, void *data)
{
for (; quirks->desc; ++quirks)
{
if (quirks->compatible)
{
continue;
}
if (quirks->iidr == (iidr & quirks->iidr_mask))
{
RT_ASSERT(quirks->init != RT_NULL);
if (!quirks->init(data))
{
LOG_I("Enable workaround for %s", quirks->desc);
}
}
}
}
void gic_common_sgi_config(void *base, void *data, int irq_base)
{
#ifdef RT_USING_SMP
if (irq_base < 2)
{
struct rt_pic_irq *pirq;
#define DECLARE_GIC_IPI(ipi, hwirq) \
rt_pic_config_ipi(data, ipi, hwirq); \
pirq = rt_pic_find_ipi(data, ipi); \
pirq->mode = RT_IRQ_MODE_EDGE_RISING; \
DECLARE_GIC_IPI(RT_SCHEDULE_IPI, 0);
DECLARE_GIC_IPI(RT_STOP_IPI, 1);
#undef DECLARE_GIC_IPI
}
#endif /* RT_USING_SMP */
}
rt_err_t gic_common_configure_irq(void *base, int irq, rt_uint32_t mode, void (*sync_access)(void *), void *data)
{
rt_err_t err = RT_EOK;
rt_ubase_t level;
rt_uint32_t val, oldval;
rt_uint32_t confoff = (irq / 16) * 4;
rt_uint32_t confmask = 0x2 << ((irq % 16) * 2);
static struct rt_spinlock ic_lock = { 0 };
level = rt_spin_lock_irqsave(&ic_lock);
val = oldval = HWREG32(base + confoff);
if (mode & RT_IRQ_MODE_LEVEL_MASK)
{
/* Level-sensitive */
val &= ~confmask;
}
else if (mode & RT_IRQ_MODE_EDGE_BOTH)
{
/* Edge-triggered */
val |= confmask;
}
if (val != oldval)
{
HWREG32(base + confoff) = val;
if (HWREG32(base + confoff) != val)
{
err = -RT_EINVAL;
}
if (sync_access)
{
sync_access(data);
}
}
rt_spin_unlock_irqrestore(&ic_lock, level);
return err;
}
void gic_common_dist_config(void *base, int max_irqs, void (*sync_access)(void *), void *data)
{
rt_uint32_t i;
/* Set all global interrupts to be level triggered, active low. */
for (i = 32; i < max_irqs; i += 16)
{
HWREG32(base + GIC_DIST_CONFIG + i / 4) = GICD_INT_ACTLOW_LVLTRIG;
}
/* Set priority on all global interrupts. */
for (i = 32; i < max_irqs; i += 4)
{
HWREG32(base + GIC_DIST_PRI + i * 4 / 4) = GICD_INT_DEF_PRI_X4;
}
/* Disable all SPIs. */
for (i = 32; i < max_irqs; i += 32)
{
HWREG32(base + GIC_DIST_ACTIVE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
HWREG32(base + GIC_DIST_ENABLE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
}
if (sync_access)
{
sync_access(data);
}
}
void gic_common_cpu_config(void *base, int nr, void (*sync_access)(void *), void *data)
{
rt_uint32_t i;
/* Disable all SGIs, PPIs. */
for (i = 0; i < nr; i += 32)
{
HWREG32(base + GIC_DIST_ACTIVE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
HWREG32(base + GIC_DIST_ENABLE_CLEAR + i / 8) = GICD_INT_EN_CLR_X32;
}
/* Set priority on all PPI and SGI. */
for (i = 0; i < nr; i += 4)
{
HWREG32(base + GIC_DIST_PRI + i * 4 / 4) = GICD_INT_DEF_PRI_X4;
}
if (sync_access)
{
sync_access(data);
}
}

57
components/drivers/pic/pic-gic-common.h Normal file
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@@ -0,0 +1,57 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-01-30 GuEe-GUI first version
*/
#ifndef __IRQ_GIC_COMMON_H__
#define __IRQ_GIC_COMMON_H__
#include <rtdef.h>
#ifdef RT_PCI_MSI
#include <drivers/pci_msi.h>
#endif
#include <drivers/ofw.h>
#define GIC_SGI_NR 16
#define GICD_INT_DEF_PRI 0xa0
#define GICD_INT_DEF_PRI_X4 \
( \
(GICD_INT_DEF_PRI << 24) | \
(GICD_INT_DEF_PRI << 16) | \
(GICD_INT_DEF_PRI << 8) | \
GICD_INT_DEF_PRI \
)
struct gic_quirk
{
const char *desc;
const char *compatible;
rt_err_t (*init)(void *data);
rt_uint32_t iidr;
rt_uint32_t iidr_mask;
};
void gic_common_init_quirk_ofw(const struct rt_ofw_node *ic_np, const struct gic_quirk *quirks, void *data);
void gic_common_init_quirk_hw(rt_uint32_t iidr, const struct gic_quirk *quirks, void *data);
void gic_common_sgi_config(void *base, void *data, int irq_base);
rt_err_t gic_common_configure_irq(void *base, int irq, rt_uint32_t mode, void (*sync_access)(void *), void *data);
void gic_common_dist_config(void *base, int max_irqs, void (*sync_access)(void *), void *data);
void gic_common_cpu_config(void *base, int nr, void (*sync_access)(void *), void *data);
#ifdef RT_PIC_ARM_GIC_V2M
rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id);
#endif
#ifdef RT_PIC_ARM_GIC_V3_ITS
rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id);
#endif
#endif /* __IRQ_GIC_COMMON_H__ */

576
components/drivers/pic/pic-gicv2.c Normal file
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File diff suppressed because it is too large Load Diff

83
components/drivers/pic/pic-gicv2.h Normal file
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@@ -0,0 +1,83 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
* 2023-02-01 GuEe-GUI move macros to header
*/
#ifndef __PIC_GICV2_H__
#define __PIC_GICV2_H__
#include <rtdef.h>
#include <drivers/pic.h>
#define GIC_DIST_CTRL 0x000
#define GIC_DIST_TYPE 0x004
#define GIC_DIST_IIDR 0x008
#define GIC_DIST_IGROUP 0x080
#define GIC_DIST_ENABLE_SET 0x100
#define GIC_DIST_ENABLE_CLEAR 0x180
#define GIC_DIST_PENDING_SET 0x200
#define GIC_DIST_PENDING_CLEAR 0x280
#define GIC_DIST_ACTIVE_SET 0x300
#define GIC_DIST_ACTIVE_CLEAR 0x380
#define GIC_DIST_PRI 0x400
#define GIC_DIST_TARGET 0x800
#define GIC_DIST_CONFIG 0xc00
#define GIC_DIST_SOFTINT 0xf00
#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
#define GIC_DIST_SGI_PENDING_SET 0xf20
#define GIC_DIST_ICPIDR2 0xfe8
#define GICD_ENABLE 0x1
#define GICD_DISABLE 0x0
#define GICD_INT_ACTLOW_LVLTRIG 0x0
#define GICD_INT_EN_CLR_X32 0xffffffff
#define GICD_INT_EN_SET_SGI 0x0000ffff
#define GICD_INT_EN_CLR_PPI 0xffff0000
#define GICD_GROUP0 0
#define GICD_GROUP1 (~GICD_GROUP0)
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_PRIMASK 0x04
#define GIC_CPU_BINPOINT 0x08
#define GIC_CPU_INTACK 0x0c
#define GIC_CPU_EOI 0x10
#define GIC_CPU_RUNNINGPRI 0x14
#define GIC_CPU_HIGHPRI 0x18
#define GIC_CPU_ALIAS_BINPOINT 0x1c
#define GIC_CPU_ACTIVEPRIO 0xd0
#define GIC_CPU_IIDR 0xfc
#define GIC_CPU_DIR 0x1000
#define GICC_ENABLE 0x1
#define GICC_INT_PRI_THRESHOLD 0xf0 /* priority levels 16 */
#define GIC_CPU_CTRL_ENABLE_GRP0 (1 << 0)
#define GIC_CPU_CTRL_ENABLE_GRP1 (1 << 1)
#define GIC_CPU_CTRL_EOI_MODE_NS (1 << 9)
struct gicv2
{
struct rt_pic parent;
int version;
int max_irq;
void *dist_base;
rt_size_t dist_size;
void *cpu_base;
rt_size_t cpu_size;
void *hyp_base;
rt_size_t hyp_size;
void *vcpu_base;
rt_size_t vcpu_size;
};
#endif /* __IRQ_GICV2_H__ */

994
components/drivers/pic/pic-gicv3.c Normal file
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File diff suppressed because it is too large Load Diff

299
components/drivers/pic/pic-gicv3.h Normal file
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@@ -0,0 +1,299 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
* 2014-04-03 Grissiom many enhancements
* 2018-11-22 Jesven add rt_hw_ipi_send()
* add rt_hw_ipi_handler_install()
* 2023-02-01 GuEe-GUI move macros to header
*/
#ifndef __IRQ_GICV3_H__
#define __IRQ_GICV3_H__
#include <rtdef.h>
#include <cpuport.h>
#include <drivers/pic.h>
#include <drivers/core/dm.h>
#include <dt-bindings/size.h>
/* Distributor registers */
#define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004
#define GICD_IIDR 0x0008
#define GICD_TYPER2 0x000C
#define GICD_STATUSR 0x0010
#define GICD_SETSPI_NSR 0x0040
#define GICD_CLRSPI_NSR 0x0048
#define GICD_SETSPI_SR 0x0050
#define GICD_CLRSPI_SR 0x0058
#define GICD_IGROUPR 0x0080
#define GICD_ISENABLER 0x0100
#define GICD_ICENABLER 0x0180
#define GICD_ISPENDR 0x0200
#define GICD_ICPENDR 0x0280
#define GICD_ISACTIVER 0x0300
#define GICD_ICACTIVER 0x0380
#define GICD_IPRIORITYR 0x0400
#define GICD_ICFGR 0x0C00
#define GICD_IGRPMODR 0x0D00
#define GICD_NSACR 0x0E00
#define GICD_IGROUPRnE 0x1000
#define GICD_ISENABLERnE 0x1200
#define GICD_ICENABLERnE 0x1400
#define GICD_ISPENDRnE 0x1600
#define GICD_ICPENDRnE 0x1800
#define GICD_ISACTIVERnE 0x1A00
#define GICD_ICACTIVERnE 0x1C00
#define GICD_IPRIORITYRnE 0x2000
#define GICD_ICFGRnE 0x3000
#define GICD_IROUTER 0x6000
#define GICD_IROUTERnE 0x8000
#define GICD_IDREGS 0xFFD0
#define GICD_PIDR2 0xFFE8
#define GICD_ITARGETSR 0x0800
#define GICD_SGIR 0x0F00
#define GICD_CPENDSGIR 0x0F10
#define GICD_SPENDSGIR 0x0F20
#define GICD_CTLR_RWP (1U << 31)
#define GICD_CTLR_nASSGIreq (1U << 8)
#define GICD_CTLR_DS (1U << 6)
#define GICD_CTLR_ARE_NS (1U << 4)
#define GICD_CTLR_ENABLE_G1A (1U << 1)
#define GICD_CTLR_ENABLE_G1 (1U << 0)
#define GICD_TYPER_RSS (1U << 26)
#define GICD_TYPER_LPIS (1U << 17)
#define GICD_TYPER_MBIS (1U << 16)
#define GICD_TYPER_ESPI (1U << 8)
#define GICD_TYPER_ID_BITS(t) ((((t) >> 19) & 0x1f) + 1)
#define GICD_TYPER_NUM_LPIS(t) ((((t) >> 11) & 0x1f) + 1)
#define GICD_TYPER_SPIS(t) ((((t) & 0x1f) + 1) * 32)
#define GICD_TYPER_ESPIS(t) (((t) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((t) >> 27) : 0)
/* Redistributor registers */
#define GICR_CTLR 0x0000
#define GICR_IIDR 0x0004
#define GICR_TYPER 0x0008
#define GICR_STATUSR 0x0010
#define GICR_WAKER 0x0014
#define GICR_MPAMIDR 0x0018
#define GICR_PARTIDR 0x001C
#define GICR_SETLPIR 0x0040
#define GICR_CLRLPIR 0x0048
#define GICR_PROPBASER 0x0070
#define GICR_PENDBASER 0x0078
#define GICR_INVLPIR 0x00A0
#define GICR_INVALLR 0x00B0
#define GICR_SYNCR 0x00C0
#define GICR_PIDR2 GICD_PIDR2
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
#define GICR_CTLR_CES (1UL << 1)
#define GICR_CTLR_IR (1UL << 2)
#define GICR_CTLR_RWP (1UL << 3)
#define GICR_RD_BASE_SIZE (64 * SIZE_KB)
#define GICR_SGI_OFFSET (64 * SIZE_KB)
#define GICR_SGI_BASE_SIZE GICR_SGI_OFFSET
/* Re-Distributor registers, offsets from SGI_base */
#define GICR_IGROUPR0 GICD_IGROUPR
#define GICR_ISENABLER0 GICD_ISENABLER
#define GICR_ICENABLER0 GICD_ICENABLER
#define GICR_ISPENDR0 GICD_ISPENDR
#define GICR_ICPENDR0 GICD_ICPENDR
#define GICR_ISACTIVER0 GICD_ISACTIVER
#define GICR_ICACTIVER0 GICD_ICACTIVER
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
#define GICR_ICFGR0 GICD_ICFGR
#define GICR_IGRPMODR0 GICD_IGRPMODR
#define GICR_NSACR GICD_NSACR
#define GICR_TYPER_PLPIS (1U << 0)
#define GICR_TYPER_VLPIS (1U << 1)
#define GICR_TYPER_DIRTY (1U << 2)
#define GICR_TYPER_DirectLPIS (1U << 3)
#define GICR_TYPER_LAST (1U << 4)
#define GICR_TYPER_RVPEID (1U << 7)
#define GICR_TYPER_COM_LPI_AFF RT_GENMASK_ULL(25, 24)
#define GICR_TYPER_AFFINITY RT_GENMASK_ULL(63, 32)
#define GICR_INVLPIR_INTID RT_GENMASK_ULL(31, 0)
#define GICR_INVLPIR_VPEID RT_GENMASK_ULL(47, 32)
#define GICR_INVLPIR_V RT_GENMASK_ULL(63, 63)
#define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID
#define GICR_INVALLR_V GICR_INVLPIR_V
#define GICR_VLPI_BASE_SIZE (64 * SIZE_KB)
#define GICR_RESERVED_SIZE (64 * SIZE_KB)
#define GIC_V3_REDIST_SIZE 0x20000
#define GICR_TYPER_NR_PPIS(t) (16 + ({ int __ppinum = (((t) >> 27) & 0x1f); __ppinum <= 2 ? __ppinum : 0; }) * 32)
#define GICR_WAKER_ProcessorSleep (1U << 1)
#define GICR_WAKER_ChildrenAsleep (1U << 2)
#define GICR_PROPBASER_IDBITS_MASK (0x1f)
#define GICR_PROPBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 12))
#define GICR_PENDBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 16))
/* ITS registers */
#define GITS_CTLR 0x0000
#define GITS_IIDR 0x0004
#define GITS_TYPER 0x0008
#define GITS_MPAMIDR 0x0010
#define GITS_PARTIDR 0x0014
#define GITS_MPIDR 0x0018
#define GITS_STATUSR 0x0040
#define GITS_UMSIR 0x0048
#define GITS_CBASER 0x0048
#define GITS_CWRITER 0x0088
#define GITS_CREADR 0x0090
#define GITS_BASER 0x0100 /* 0x0100~0x0138 */
/*
* ITS commands
*/
#define GITS_CMD_MAPD 0x08
#define GITS_CMD_MAPC 0x09
#define GITS_CMD_MAPTI 0x0a
#define GITS_CMD_MAPI 0x0b
#define GITS_CMD_MOVI 0x01
#define GITS_CMD_DISCARD 0x0f
#define GITS_CMD_INV 0x0c
#define GITS_CMD_MOVALL 0x0e
#define GITS_CMD_INVALL 0x0d
#define GITS_CMD_INT 0x03
#define GITS_CMD_CLEAR 0x04
#define GITS_CMD_SYNC 0x05
/* ITS Config Area */
#define GITS_LPI_CFG_GROUP1 (1 << 1)
#define GITS_LPI_CFG_ENABLED (1 << 0)
/* ITS Command Queue Descriptor */
#define GITS_CBASER_VALID (1UL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
#define GITS_TRANSLATION_TABLE_DESCRIPTORS_NR 8
#define GITS_BASER_CACHEABILITY(reg, inner_outer, type) \
(GITS_CBASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
#define GITS_BASER_SHAREABILITY(reg, type) \
(GITS_CBASER_##type << reg##_SHAREABILITY_SHIFT)
#define GITS_CBASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */
#define GITS_CBASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */
#define GITS_CBASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */
#define GITS_CBASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */
#define GITS_CBASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */
#define GITS_CBASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */
#define GITS_CBASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */
#define GITS_CBASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */
#define GITS_CBASER_CACHE_MASK 0x7UL
#define GITS_CBASER_SHARE_NS 0x0UL /* Non-shareable. */
#define GITS_CBASER_SHARE_IS 0x1UL /* Inner Shareable. */
#define GITS_CBASER_SHARE_OS 0x2UL /* Outer Shareable. */
#define GITS_CBASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */
#define GITS_CBASER_SHARE_MASK 0x3UL
#define GITS_CBASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_IS)
#define GITS_CBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_MASK)
#define GITS_CBASER_nCnB GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, DnGnRnE)
#define GITS_CBASER_nC GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIN)
#define GITS_CBASER_RaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWT)
#define GITS_CBASER_RaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWB)
#define GITS_CBASER_WaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWT)
#define GITS_CBASER_WaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWB)
#define GITS_CBASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWT)
#define GITS_CBASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWB)
#define GIC_EPPI_BASE_INTID 1056
#define GIC_ESPI_BASE_INTID 4096
#define GIC_IRQ_TYPE_LPI 0xa110c8ed
#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
#define read_gicreg(reg, out) rt_hw_sysreg_read(reg, out)
#define write_gicreg(reg, in) rt_hw_sysreg_write(reg, in)
#define ICC_CTLR_EOImode 0x2
#define ICC_PMR_MASK 0xff
#define ICC_PMR_DEFAULT 0xf0
#define ICC_IGRPEN1_EN 0x1
#define ICC_SGIR_AFF3_SHIFT 48
#define ICC_SGIR_AFF2_SHIFT 32
#define ICC_SGIR_AFF1_SHIFT 16
#define ICC_SGIR_TARGET_MASK 0xffff
#define ICC_SGIR_IRQN_SHIFT 24
#define ICC_SGIR_ROUTING_BIT (1ULL << 40)
#define ICC_SGI1R_TARGET_LIST_SHIFT 0
#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
#define ICC_SGI1R_TARGET_LIST_MAX 16
#define ICC_SGI1R_AFFINITY_1_SHIFT 16
#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
#define ICC_SGI1R_SGI_ID_SHIFT 24
#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
#define ICC_SGI1R_AFFINITY_2_SHIFT 32
#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
#define ICC_SGI1R_RS_SHIFT 44
#define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
#define ICC_SGI1R_AFFINITY_3_SHIFT 48
#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
#define ICC_CTLR_EL1_CBPR_SHIFT 0
#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
#define ICC_CTLR_EL1_EOImode_SHIFT (1)
#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
#define ICC_CTLR_EL1_PRI_BITS_SHIFT (8)
#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
#define ICC_CTLR_EL1_RSS (0x1 << 18)
#define ICC_CTLR_EL1_ExtRange (0x1 << 19)
struct gicv3
{
struct rt_pic parent;
int version;
int irq_nr;
rt_uint32_t gicd_typer;
rt_size_t line_nr;
rt_size_t espi_nr;
rt_size_t lpi_nr;
rt_ubase_t flags;
void *dist_base;
rt_size_t dist_size;
void *redist_percpu_base[RT_CPUS_NR];
rt_size_t percpu_ppi_nr[RT_CPUS_NR];
struct
{
void *base;
void *base_phy;
rt_size_t size;
} *redist_regions;
rt_uint64_t redist_flags;
rt_size_t redist_stride;
rt_size_t redist_regions_nr;
};
#endif /* __IRQ_GICV3_H__ */

396
components/drivers/pic/pic.c
View File

File diff suppressed because it is too large Load Diff

79
components/drivers/pic/pic_rthw.c Normal file
View File

@@ -0,0 +1,79 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-24 GuEe-GUI first version
*/
#include <rtthread.h>
#include <rtdevice.h>
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
/* initialize pic */
rt_pic_irq_init();
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
rt_pic_irq_mask(vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
rt_pic_irq_unmask(vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_pic_attach_irq(vector, handler, param, name, RT_IRQ_F_NONE);
return RT_NULL;
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_uninstall(int vector, rt_isr_handler_t handler, void *param)
{
rt_pic_detach_irq(vector, param);
}
#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
{
RT_DECLARE_BITMAP(cpu_masks, RT_CPUS_NR) = { cpu_mask };
rt_pic_irq_send_ipi(ipi_vector, cpu_masks);
}
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
}
#endif

3
libcpu/aarch64/common/SConscript
View File

@@ -10,6 +10,9 @@ CPPPATH = [cwd]
if GetDepend('RT_USING_OFW') == False:
SrcRemove(src, ['setup.c', 'cpu_psci.c', 'psci.c'])
if GetDepend('RT_USING_PIC') == True:
SrcRemove(src, ['gicv3.c', 'gic.c', 'interrupt.c', 'gtimer.c'])
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)

59
libcpu/aarch64/common/cpu.h
View File

@@ -27,7 +27,66 @@ struct cpu_ops_t
int (*cpu_boot)(rt_uint32_t id, rt_uint64_t entry);
void (*cpu_shutdown)(void);
};
#define sysreg_32(op1, crn, crm, op2) s3_##op1 ##_##crn ##_##crm ##_##op2
#define sysreg_64(op1, crn, crm, op2) sysreg_32(op1, crn, crm, op2)
#define MPIDR_AFFINITY_MASK 0x000000ff00ffffffUL
#define MPIDR_LEVEL_BITS_SHIFT 3
#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
#define MPIDR_LEVEL_SHIFT(level) (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
#define MPIDR_AFFINITY_LEVEL(mpidr, level) (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
/* GIC registers */
#define ICC_IAR0_SYS sysreg_64(0, c12, c8, 0)
#define ICC_IAR1_SYS sysreg_64(0, c12, c12, 0)
#define ICC_EOIR0_SYS sysreg_64(0, c12, c8, 1)
#define ICC_EOIR1_SYS sysreg_64(0, c12, c12, 1)
#define ICC_HPPIR0_SYS sysreg_64(0, c12, c8, 2)
#define ICC_HPPIR1_SYS sysreg_64(0, c12, c12, 2)
#define ICC_BPR0_SYS sysreg_64(0, c12, c8, 3)
#define ICC_BPR1_SYS sysreg_64(0, c12, c12, 3)
#define ICC_DIR_SYS sysreg_64(0, c12, c11, 1)
#define ICC_PMR_SYS sysreg_64(0, c4, c6, 0)
#define ICC_RPR_SYS sysreg_64(0, c12, c11, 3)
#define ICC_CTLR_SYS sysreg_64(0, c12, c12, 4)
#define ICC_SRE_SYS sysreg_64(0, c12, c12, 5)
#define ICC_IGRPEN0_SYS sysreg_64(0, c12, c12, 6)
#define ICC_IGRPEN1_SYS sysreg_64(0, c12, c12, 7)
#define ICC_SGI0R_SYS sysreg_64(0, c12, c11, 7)
#define ICC_SGI1R_SYS sysreg_64(0, c12, c11, 5)
#define ICC_ASGI1R_SYS sysreg_64(0, c12, c11, 6)
/* Arch timer registers */
#define CNTP_CTL CNTP_CTL_EL0 /* EL1 Physical Timer */
#define CNTHP_CTL CNTHP_CTL_EL2 /* EL2 Non-secure Physical Timer */
#define CNTHPS_CTL CNTHPS_CTL_EL2 /* EL2 Secure Physical Timer */
#define CNTPS_CTL CNTPS_CTL_EL1 /* EL3 Physical Timer */
#define CNTV_CTL CNTV_CTL_EL0 /* EL1 Virtual Timer */
#define CNTHV_CTL CNTHV_CTL_EL2 /* EL2 Non-secure Virtual Timer */
#define CNTHVS_CTL CNTHVS_CTL_EL2 /* EL2 Secure Virtual Timer */
#define CNTP_CVAL CNTP_CVAL_EL0
#define CNTHP_CVAL CNTHP_CVAL_EL2
#define CNTHPS_CVAL CNTHPS_CVAL_EL2
#define CNTPS_CVAL CNTPS_CVAL_EL1
#define CNTV_CVAL CNTV_CVAL_EL0
#define CNTHV_CVAL CNTHV_CVAL_EL2
#define CNTHVS_CVAL CNTHVS_CVAL_EL2
#define CNTP_TVAL CNTP_TVAL_EL0
#define CNTHP_TVAL CNTHP_TVAL_EL2
#define CNTHPS_TVAL CNTHPS_TVAL_EL2
#define CNTPS_TVAL CNTPS_TVAL_EL1
#define CNTV_TVAL CNTV_TVAL_EL0
#define CNTHV_TVAL CNTHV_TVAL_EL2
#define CNTHVS_TVAL CNTHVS_TVAL_EL2
#define CNTPCT CNTPCT_EL0
#define CNTVCT CNTVCT_EL0
#define CNTFRQ CNTFRQ_EL0
extern rt_uint64_t rt_cpu_mpidr_table[];
#endif /* __RT_HW_CPU_H__ */

6
libcpu/aarch64/common/cpuport.h
View File

@@ -37,6 +37,12 @@ typedef struct {
#define rt_hw_cpu_relax() rt_hw_barrier(yield)
#define rt_hw_sysreg_write(sysreg, val) \
__asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
#define rt_hw_sysreg_read(sysreg, val) \
__asm__ volatile ("mrs %0, "RT_STRINGIFY(sysreg)"":"=r"((val)))
void _thread_start(void);
#ifdef RT_USING_CPU_FFS

19
libcpu/aarch64/common/setup.c
View File

@@ -22,10 +22,7 @@
#include <setup.h>
#include <stdlib.h>
#include <ioremap.h>
#include <drivers/ofw.h>
#include <drivers/ofw_fdt.h>
#include <drivers/ofw_raw.h>
#include <drivers/core/dm.h>
#include <rtdevice.h>
#define rt_sysreg_write(sysreg, val) \
__asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
@@ -166,6 +163,8 @@ void rt_hw_common_setup(void)
static struct mem_desc platform_mem_desc;
void *kernel_start, *kernel_end, *memheap_start = RT_NULL, *memheap_end = RT_NULL;
system_vectors_init();
#ifdef RT_USING_SMART
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
#else
@@ -336,6 +335,10 @@ void rt_hw_common_setup(void)
cpu_info_init();
#ifdef RT_USING_PIC
rt_pic_init();
rt_pic_irq_init();
#else
/* initialize hardware interrupt */
rt_hw_interrupt_init();
@@ -344,8 +347,9 @@ void rt_hw_common_setup(void)
/* initialize timer for os tick */
rt_hw_gtimer_init();
#endif
#ifdef RT_USING_COMPONENTS_INIT
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
@@ -421,9 +425,14 @@ rt_weak void rt_hw_secondary_cpu_bsp_start(void)
rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
#ifdef RT_USING_PIC
rt_pic_irq_init();
#else
rt_hw_interrupt_init();
#endif
rt_dm_secondary_cpu_init();
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
rt_hw_interrupt_umask(RT_STOP_IPI);

14
libcpu/aarch64/common/trap.c
View File

@@ -166,6 +166,7 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc);
}
#ifndef RT_USING_PIC
void rt_hw_trap_irq(void)
{
#ifdef SOC_BCM283x
@@ -267,6 +268,12 @@ void rt_hw_trap_irq(void)
rt_hw_interrupt_ack(ir);
#endif
}
#else
void rt_hw_trap_irq(void)
{
rt_pic_do_traps();
}
#endif
#ifdef RT_USING_SMART
#define DBG_CHECK_EVENT(regs, esr) dbg_check_event(regs, esr)
@@ -274,6 +281,7 @@ void rt_hw_trap_irq(void)
#define DBG_CHECK_EVENT(regs, esr) (0)
#endif
#ifndef RT_USING_PIC
void rt_hw_trap_fiq(void)
{
void *param;
@@ -296,6 +304,12 @@ void rt_hw_trap_fiq(void)
/* end of interrupt */
rt_hw_interrupt_ack(ir);
}
#else
void rt_hw_trap_fiq(void)
{
rt_pic_do_traps();
}
#endif
void print_exception(unsigned long esr, unsigned long epc);
void SVC_Handler(struct rt_hw_exp_stack *regs);