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add atmel SAM D21 bsp support

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This commit is contained in:
xieyangrun
2017-08-30 12:18:28 +08:00
parent f3f523d22f
commit 189c999f8e
1412 changed files with 599447 additions and 1 deletions
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3
bsp/samd21/README.txt Normal file
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使用SAMD21-Xplained-Pro开发板
scons:只支持scons --target=mdk5,其他命令没有支持
demo代码演示了串口、外部中断、RTC低功耗唤醒

14
bsp/samd21/SConscript Normal file
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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

34
bsp/samd21/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'SAM_D2X_RTT.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

14
bsp/samd21/applications/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
#remove other no use files
#SrcRemove(src, '*.c')
group = DefineGroup('Application', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

141
bsp/samd21/applications/application.c Normal file
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#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "port.h"
#include "extint.h"
#include "sleep_timer.h"
void LED_Init(void)
{
struct port_config config_port_pin;
port_get_config_defaults(&config_port_pin);
config_port_pin.direction = PORT_PIN_DIR_INPUT;
config_port_pin.input_pull = PORT_PIN_PULL_UP;
port_pin_set_config(PIN_PA15, &config_port_pin);
config_port_pin.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(PIN_PB30, &config_port_pin);
}
void LED_ON(void)
{
port_pin_set_output_level(PIN_PB30, false);
}
void LED_OFF(void)
{
port_pin_set_output_level(PIN_PB30, true);
}
void extint_detection_callback(void);
void configure_extint_channel(void)
{
//! [setup_1]
struct extint_chan_conf config_extint_chan;
//! [setup_1]
//! [setup_2]
extint_chan_get_config_defaults(&config_extint_chan);
//! [setup_2]
//! [setup_3]
config_extint_chan.gpio_pin = PIN_PA15A_EIC_EXTINT15;
config_extint_chan.gpio_pin_mux = MUX_PA15A_EIC_EXTINT15;
config_extint_chan.gpio_pin_pull = EXTINT_PULL_UP;
config_extint_chan.detection_criteria = EXTINT_DETECT_BOTH;
//! [setup_3]
//! [setup_4]
extint_chan_set_config(15, &config_extint_chan);
//! [setup_4]
}
void configure_extint_callbacks(void)
{
//! [setup_5]
extint_register_callback(extint_detection_callback, 15, EXTINT_CALLBACK_TYPE_DETECT);
//! [setup_5]
//! [setup_6]
extint_chan_enable_callback(15, EXTINT_CALLBACK_TYPE_DETECT);
//! [setup_6]
}
//! [setup_7]
void extint_detection_callback(void)
{
bool pin_state = port_pin_get_input_level(PIN_PA15);
port_pin_set_output_level(PIN_PB30, pin_state);
}
static struct rt_semaphore _rx_sem;
static rt_err_t _rx_ind(rt_device_t dev, rt_size_t size)
{
return rt_sem_release(&_rx_sem);
}
void rt_init_thread_entry(void* parameter)
{
rt_thread_t thread;
rt_device_t dev;
rt_kprintf("SYSTEM running at %uhz\n", SystemCoreClock);
sleep_timer_init();
// sleep_timer_start(1500);
LED_Init();
configure_extint_channel();
configure_extint_callbacks();
while (1)
{
rt_kprintf("init thread running tick:%u\n", rt_tick_get());
rt_thread_delay(2*RT_TICK_PER_SECOND);
}
#if 0
dev = rt_device_find("uart3");
if (dev != RT_NULL)
{
rt_sem_init(&_rx_sem, "rxsem", 0, RT_IPC_FLAG_FIFO);
rt_device_set_rx_indicate(dev, _rx_ind);
rt_device_open(dev, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
}
while (1)
{
rt_size_t r_size;
rt_uint8_t r_buf[1];
// rt_kprintf("SAMD2xJ18A hello thread\n");
// rt_thread_delay(RT_TICK_PER_SECOND);
rt_sem_take(&_rx_sem, RT_WAITING_FOREVER);
while ((r_size = rt_device_read(dev, 0, r_buf, 1)) > 0)
{
rt_device_write(dev, 0, r_buf, r_size);
if (r_buf[0] == '\r')
{
r_buf[0] = '\n';
rt_device_write(dev, 0, r_buf, r_size);
}
}
}
#endif
}
int rt_application_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL,
512, RT_THREAD_PRIORITY_MAX / 3, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}

127
bsp/samd21/applications/startup.c Normal file
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/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
/**
* @addtogroup STM32
*/
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern void finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#elif __ICCARM__
#pragma section="HEAP"
#else
extern int __bss_end;
#endif
#ifdef DEBUG
/*******************************************************************************
* Function Name : assert_failed
* Description : Reports the name of the source file and the source line number
* where the assert error has occurred.
* Input : - file: pointer to the source file name
* - line: assert error line source number
* Output : None
* Return : None
*******************************************************************************/
void assert_failed(uint8_t* file, uint32_t line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
}
#endif
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)CHIP_SRAM_END);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)CHIP_SRAM_END);
#else
/* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)CHIP_SRAM_END);
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
/*@}*/

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bsp/samd21/asflib_config/clock_samd20/conf_clocks.h Normal file
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/**
* \file
*
* \brief SAM D20 Clock configuration
*
* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_FLASH_WAIT_STATES 0
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
# define CONF_CLOCK_OSC8M_ON_DEMAND true
# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND true
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE false
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND false
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (512)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 1465 /* (48000000 / 32768) */
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE false
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 (RTC) */
# define CONF_CLOCK_GCLK_2_ENABLE false
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K
# define CONF_CLOCK_GCLK_2_PRESCALER 32
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

198
bsp/samd21/asflib_config/clock_samd21_r21_da_ha1/conf_clocks.h Normal file
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/**
* \file
*
* \brief SAM D21/R21/DA/HA Clock configuration
*
* Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 1
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
# define CONF_CLOCK_OSC8M_ON_DEMAND true
# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE true
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_2048
# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL true
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND false
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE true
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND true
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE ((*((uint32_t*)(0x806020 + 8))) & 0x3FF)/*(512)*/
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_2
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768)
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE ((*((uint8_t*)(0x806020 + 7))) >> 2)/*(0x1f / 4)*/
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE ((*((uint32_t*)(0x806020 + 8))) & 0x3FF)/*(0xff / 4)*/
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND true
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE false
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 (RTC) */
# define CONF_CLOCK_GCLK_2_ENABLE true
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_2_PRESCALER 1
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

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/**
* \file
*
* \brief SAM D21 External Interrupt Driver Configuration Header
*
* Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_EXTINT_H_INCLUDED
#define CONF_EXTINT_H_INCLUDED
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_2
#endif

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
path = [cwd]
#remove other no use files
#SrcRemove(src, 'i2c_iomaster.c')
#SrcRemove(src, 'delay.c')
if rtconfig.DEVICE_SERIES == 'SAMD20':
path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd20']
elif rtconfig.DEVICE_SERIES == 'SAMD21':
path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd21_r21_da_ha1']
group = DefineGroup('Board', src, depend = [''], CPPPATH = path)
Return('group')

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#include "board.h"
#include <clock.h>
#include <gclk.h>
#include <system.h>
#include <rtthread.h>
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
void configure_extosc32k(void);
void configure_dfll_open_loop(void);
//! [setup]
//! [config_extosc32k]
void configure_extosc32k(void)
{
//! [config_extosc32k_config]
struct system_clock_source_xosc32k_config config_ext32k;
//! [config_extosc32k_config]
//! [config_extosc32k_get_defaults]
system_clock_source_xosc32k_get_config_defaults(&config_ext32k);
//! [config_extosc32k_get_defaults]
//! [config_extosc32k_change_defaults]
config_ext32k.startup_time = SYSTEM_XOSC32K_STARTUP_4096;
config_ext32k.on_demand = false;
//! [config_extosc32k_change_defaults]
//! [config_extosc32k_set_config]
system_clock_source_xosc32k_set_config(&config_ext32k);
//! [config_extosc32k_set_config]
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
}
//! [config_extosc32k]
#if (!SAMC21)
//! [config_dfll]
void configure_dfll_open_loop(void)
{
//! [config_dfll_config]
struct system_clock_source_dfll_config config_dfll;
//! [config_dfll_config]
//! [config_dfll_get_defaults]
system_clock_source_dfll_get_config_defaults(&config_dfll);
//! [config_dfll_get_defaults]
config_dfll.coarse_value = (*((uint8_t*)(0x806020 + 7))) >> 2;// 0x1f / 4; /* Midpoint */
config_dfll.fine_value = (*((uint32_t*)(0x806020 + 8))) & 0x3FF;//0xff / 4; /* Midpoint */
//! [config_dfll_set_config]
system_clock_source_dfll_set_config(&config_dfll);
//! [config_dfll_set_config]
//! [enable_dfll_main]
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
// while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
//! [enable_dfll_main]
/* Configure flash wait states before switching to high frequency clock */
//! [set_sys_wait_states]
system_flash_set_waitstates(2);
//! [set_sys_wait_states]
/* Change system clock to DFLL */
//! [set_sys_clk_src]
struct system_gclk_gen_config config_gclock_gen;
system_gclk_gen_get_config_defaults(&config_gclock_gen);
config_gclock_gen.source_clock = SYSTEM_CLOCK_SOURCE_DFLL;
config_gclock_gen.division_factor = 1;
system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);
//! [set_sys_clk_src]
}
//! [config_dfll]
#endif
void rt_board_init(void)
{
extern void uart_init(void);
// configure_extosc32k();
// configure_dfll_open_loop();
system_init();
/* initialize systick */
SystemCoreClock = system_gclk_gen_get_hz(0);
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
}

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/* This is a template file for board configuration created by MCUXpresso Project Generator. Enjoy! */
#ifndef _BOARD_H_
#define _BOARD_H_
/*******************************************************************************
* Definitions
******************************************************************************/
#include <stdint.h>
#include "samd21.h"
#include "system_samd21.h"
#include "core_cm0plus.h" /* Core Peripheral Access Layer */
/* The board name */
#define BOARD_NAME "###-not-specified-###"
#define CHIP_SRAM_END (0x20000000 + 32*1024)
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @brief initialize debug console to enable printf for this demo/example
*/
void rt_board_init(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */

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// From module: RTC - Real Time Counter in Count Mode (Polled APIs)
#include <rtc_count.h>
#include <rtc_count_interrupt.h>
// #include <rtc_tamper.h>
#include <power.h>
#include <port.h>
#include <rtthread.h>
/* RTC module instance */
static struct rtc_module rtc_instance;
static void _rtc_timer_int_cb(void)
{
port_pin_toggle_output_level(PIN_PB30);
}
/* Init RTC as ADC sample timer */
static void _rtc_timer_init(void)
{
struct rtc_count_config conf;
rtc_count_get_config_defaults(&conf);
conf.prescaler = RTC_COUNT_PRESCALER_DIV_1;
conf.mode = RTC_COUNT_MODE_32BIT;
conf.clear_on_match = false;
conf.compare_values[0] = 0;
// struct rtc_count_events evconfig;
// evconfig.generate_event_on_compare[0] = true;
rtc_count_init(&rtc_instance, RTC, &conf);
// rtc_count_enable_events(&rtc_instance, &evconfig);
// rtc_count_enable(&rtc_instance);
rtc_count_set_count(&rtc_instance, 0);
rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
// rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
}
static void _rtc_timer_start(uint32_t ms)
{
uint32_t compare = 0;
compare = (uint32_t)(32.768 * ms);
// rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
rtc_count_set_count(&rtc_instance, 0);
rtc_count_set_compare(&rtc_instance, compare, RTC_COUNT_COMPARE_0);
rtc_count_enable(&rtc_instance);
}
static void sleep_tick_adjust(uint32_t ms)
{
uint32_t diff;
diff = rt_tick_from_millisecond(ms);
rt_tick_set(rt_tick_get() + diff);
{
struct rt_thread *thread;
/* check time slice */
thread = rt_thread_self();
if (thread->remaining_tick <= diff)
{
/* change to initialized tick */
thread->remaining_tick = thread->init_tick;
/* yield */
rt_thread_yield();
}
else
{
thread->remaining_tick -= diff;
}
/* check timer */
rt_timer_check();
}
}
static void _sleep_entry(void)
{
rt_tick_t timeout;
rt_uint32_t ms;
rt_uint32_t count;
system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
timeout = rt_timer_next_timeout_tick() - rt_tick_get();
ms = timeout * (1000 / RT_TICK_PER_SECOND);
rt_kprintf("os tick:%u entry sleep:%u tick\r\n", rt_tick_get(), timeout);
_rtc_timer_start(ms);
system_sleep();
rt_enter_critical();
count = rtc_count_get_count(&rtc_instance);
ms = (count + 32) / 32.768;
rtc_count_disable(&rtc_instance);
sleep_tick_adjust(ms);
timeout = rt_tick_get();
rt_exit_critical();
rt_kprintf("sleep exited, os tick:%u\n", timeout);
}
void sleep_timer_init(void)
{
_rtc_timer_init();
rt_thread_idle_sethook(_sleep_entry);
}
void sleep_timer_start(uint32_t ms)
{
_rtc_timer_start(ms);
}
void sleep_timer_stop(void)
{
rtc_count_disable(&rtc_instance);
}

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#ifndef _SLEEP_TIMER_H_
#define _SLEEP_TIMER_H_
void sleep_timer_init(void);
void sleep_timer_start(uint32_t ms);
#endif

321
bsp/samd21/board/uart.c Normal file
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// From module: SERCOM Callback API
#include <samd21.h>
#include <sercom.h>
// #include <sercom_interrupt.h>
// From module: SERCOM USART - Serial Communications (Callback APIs)
#include <usart.h>
// #include <usart_interrupt.h>
#include <rtdevice.h>
typedef struct _samd2x_uart_t
{
struct rt_serial_device *serial;
struct usart_module *instance;
Sercom *com;
enum usart_signal_mux_settings mux_setting;
uint32_t pinmux_pad0;
uint32_t pinmux_pad1;
uint32_t pinmux_pad2;
uint32_t pinmux_pad3;
enum system_interrupt_vector vector;
} SAMD2x_UART_T;
static struct rt_serial_device _serial3;
static struct usart_module _uart3_instance;
static SAMD2x_UART_T _uart3 = {
&_serial3,
&_uart3_instance,
SERCOM3,
USART_RX_1_TX_0_XCK_1,
PINMUX_PA22C_SERCOM3_PAD0,
PINMUX_PA23C_SERCOM3_PAD1,
PINMUX_UNUSED,
PINMUX_UNUSED,
SYSTEM_INTERRUPT_MODULE_SERCOM3
};
// static struct rt_serial_device _serial2;
// static struct rt_serial_device _serial3;
// static struct rt_serial_device _serial4;
static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
{
SAMD2x_UART_T *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (SAMD2x_UART_T *)serial->parent.user_data;
//! [setup_config]
struct usart_config config_usart;
//! [setup_config]
//! [setup_config_defaults]
usart_get_config_defaults(&config_usart);
//! [setup_config_defaults]
config_usart.baudrate = cfg->baud_rate;
switch (cfg->data_bits )
{
case DATA_BITS_8:
config_usart.character_size = USART_CHARACTER_SIZE_8BIT;
break;
case DATA_BITS_5:
config_usart.character_size = USART_CHARACTER_SIZE_5BIT;
break;
case DATA_BITS_6:
config_usart.character_size = USART_CHARACTER_SIZE_6BIT;
break;
case DATA_BITS_7:
config_usart.character_size = USART_CHARACTER_SIZE_7BIT;
break;
case DATA_BITS_9:
config_usart.character_size = USART_CHARACTER_SIZE_9BIT;
break;
default:
config_usart.character_size = USART_CHARACTER_SIZE_8BIT;
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
config_usart.parity = USART_PARITY_NONE;
break;
case PARITY_EVEN:
config_usart.parity = USART_PARITY_EVEN;
break;
case PARITY_ODD:
config_usart.parity = USART_PARITY_ODD;
break;
default:
config_usart.parity = USART_PARITY_NONE;
break;
}
config_usart.stopbits = USART_STOPBITS_1;
if (cfg->stop_bits != USART_STOPBITS_1)
{
config_usart.stopbits = USART_STOPBITS_2;
}
config_usart.data_order = USART_DATAORDER_LSB;
if (cfg->bit_order != BIT_ORDER_LSB)
{
config_usart.data_order = USART_DATAORDER_MSB;
}
config_usart.mux_setting = uart->mux_setting;
config_usart.pinmux_pad0 = uart->pinmux_pad0;
config_usart.pinmux_pad1 = uart->pinmux_pad1;
config_usart.pinmux_pad2 = uart->pinmux_pad2;
config_usart.pinmux_pad3 = uart->pinmux_pad3;
config_usart.receiver_enable = false;
config_usart.transmitter_enable = true;
while (usart_init(uart->instance, uart->com, &config_usart) != STATUS_OK) {
}
usart_enable(uart->instance);
/* Wait for the synchronization to complete */
_usart_wait_for_sync(uart->instance);
return RT_EOK;
}
static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
{
SAMD2x_UART_T *uart;
RT_ASSERT(serial != RT_NULL);
uart = (SAMD2x_UART_T *)(serial->parent.user_data);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
uart->com->USART.INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
usart_disable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
system_interrupt_disable(uart->vector);
/* Wait for the synchronization to complete */
_usart_wait_for_sync(uart->instance);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* Enable RX interrupt. */
/* Enable the RX Complete Interrupt */
uart->com->USART.INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
usart_enable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
system_interrupt_enable(uart->vector);
/* Wait for the synchronization to complete */
_usart_wait_for_sync(uart->instance);
break;
default:
return RT_ERROR;
}
return RT_EOK;
}
static int _uart_putc(struct rt_serial_device *serial, char c)
{
SAMD2x_UART_T *uart;
RT_ASSERT(serial != RT_NULL);
// while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
// }
uart = (SAMD2x_UART_T *)(serial->parent.user_data);
/* Write data to USART module */
uart->com->USART.DATA.reg = c;
while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
/* Wait until data is sent */
}
return 1;
}
static int _uart_getc(struct rt_serial_device *serial)
{
int ch;
SAMD2x_UART_T *uart;
RT_ASSERT(serial != RT_NULL);
uart = (SAMD2x_UART_T *)(serial->parent.user_data);
/* Check if USART has new data */
if (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
/* Return error code */
return -1;
}
ch = uart->com->USART.DATA.reg & 0x1FF;
return ch;
}
static struct rt_uart_ops _uart_ops = {
_uart_cfg,
_uart_ctrl,
_uart_putc,
_uart_getc
};
static void uart_int_cb(SAMD2x_UART_T *uart_handle)
{
/* Temporary variables */
uint16_t interrupt_status;
uint8_t error_code;
struct usart_module *module = uart_handle->instance;
/* Pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Read and mask interrupt flag register */
interrupt_status = usart_hw->INTFLAG.reg;
interrupt_status &= usart_hw->INTENSET.reg;
/* Check if the Receive Complete interrupt has occurred, and that
* there's more data to receive */
if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
/* Read out the status code and mask away all but the 4 LSBs*/
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
#if !SAMD20
/* CTS status should not be considered as an error */
if(error_code & SERCOM_USART_STATUS_CTS) {
error_code &= ~SERCOM_USART_STATUS_CTS;
}
#endif
#ifdef FEATURE_USART_LIN_MASTER
/* TXE status should not be considered as an error */
if(error_code & SERCOM_USART_STATUS_TXE) {
error_code &= ~SERCOM_USART_STATUS_TXE;
}
#endif
/* Check if an error has occurred during the receiving */
if (error_code) {
/* Check which error occurred */
if (error_code & SERCOM_USART_STATUS_FERR) {
/* clear flag by writing 1 to it */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
/* clear flag by writing 1 to it */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
} else if (error_code & SERCOM_USART_STATUS_PERR) {
/* clear flag by writing 1 to it */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
}
#ifdef FEATURE_USART_LIN_SLAVE
else if (error_code & SERCOM_USART_STATUS_ISF) {
/* clear flag by writing 1 to it */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
}
#endif
#ifdef FEATURE_USART_COLLISION_DECTION
else if (error_code & SERCOM_USART_STATUS_COLL) {
/* clear flag by writing 1 to it */
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
}
#endif
} else {
rt_hw_serial_isr(uart_handle->serial, RT_SERIAL_EVENT_RX_IND);
}
}
#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
}
#endif
#ifdef FEATURE_USART_LIN_SLAVE
if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
}
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
}
#endif
}
void SERCOM3_Handler(void)
{
uart_int_cb(&_uart3);
}
void uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
config.bufsz = 512;
_serial3.config = config;
_serial3.ops = &_uart_ops;
rt_hw_serial_register(&_serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_uart3);
}

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94
bsp/samd21/rtconfig.h Normal file
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/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 6
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 8
/* Tick per Second */
#define RT_TICK_PER_SECOND 200
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
//#define RT_DEBUG_INIT 1
#define RT_USING_OVERFLOW_CHECK
/* Using Hook */
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 512
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 100
/* SECTION: IPC */
/* Using Semaphore*/
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
/* #define RT_USING_MAILBOX */
/* Using Message Queue */
/* #define RT_USING_MESSAGEQUEUE */
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
/* #define RT_USING_MEMPOOL */
/* Using Dynamic Heap Management */
#define RT_USING_HEAP
/* Using Small MM */
#define RT_USING_SMALL_MEM
#define RT_USING_TINY_SIZE
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
//#define RT_USING_COMPONENTS_INIT
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
#define RT_USING_DEVICE_IPC
// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
#define RT_USING_SERIAL
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
#define RT_CONSOLE_DEVICE_NAME "uart3"
// #define RT_USING_SPI
/* SECTION: finsh, a C-Express shell */
// #define RT_USING_FINSH
/* configure finsh parameters */
#define FINSH_THREAD_PRIORITY 6
#define FINSH_THREAD_STACK_SIZE 512
#define FINSH_HISTORY_LINES 1
/* Using symbol table */
// #define FINSH_USING_SYMTAB
// #define FINSH_USING_DESCRIPTION
// #define FINSH_USING_MSH
// #define FINSH_USING_MSH_ONLY
#endif

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import os
# toolchains options
ARCH='arm'
CPU='cortex-m0'
CROSS_TOOL='keil'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
#DEVICE_SERIES = 'SAMD20'
DEVICE_SERIES = 'SAMD21'
#DEVICE_TYPE = '__SAMD20G18A__'
DEVICE_TYPE = '__SAMD21J18A__'
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil'
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support iar yet!'
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'axf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m0+ -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-MKL15Z128.map,-cref,-u,Reset_Handler -T MKL15Z128_FLASH.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMSTM'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-SAM_D2x.map --strict --scatter SAM_D2X_RTT.scf'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
//extern const q31_t realCoefAQ31[1024];
//extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
# get current directory
cwd = GetCurrentDir()
#var defined
CPPDEFINES = []
src = []
path = []
#common lib define
CPPDEFINES += [rtconfig.DEVICE_TYPE, 'DEBUG']
#CMSIS/Include/ common/ common2/service/delay
path += [cwd + '/CMSIS/Include/']
path += [cwd + '/common/utils/', cwd + '/common/utils/interrupt/']
path += [cwd + '/common/boards/']
path += [cwd + '/common2/services/delay/', cwd + '/common2/services/delay/sam0/']
src += Glob('./common/utils/interrupt/interrupt_sam_nvic.c')
#sam0/ sam0/utils/
path += [cwd + '/sam0/', cwd + '/sam0/utils/']
path += [cwd + '/sam0/utils/preprocessor']
path += [cwd + '/sam0/utils/header_files']
#sam0/utils/cmsis/
if rtconfig.DEVICE_SERIES == 'SAMD20':
#D20
path += [cwd + '/sam0/', cwd + '/sam0/utils/cmsis/samd20/include/']
path += [cwd + '/sam0/utils/cmsis/samd20/source/']
src += Glob('./sam0/utils/cmsis/samd20/source/*.c')
src += Glob('./sam0/utils/cmsis/samd20/source/arm/*.s')
elif rtconfig.DEVICE_SERIES == 'SAMD21':
#D21
path += [cwd + '/sam0/utils/cmsis/samd21/include/']
path += [cwd + '/sam0/utils/cmsis/samd21/source/']
src += Glob('./sam0/utils/cmsis/samd21/source/*.c')
src += Glob('./sam0/utils/cmsis/samd21/source/arm/*.s')
#sam0/drivers/system
path += [cwd + '/sam0/drivers/system/']
src += Glob('./sam0/drivers/system/system.c')
path += [cwd + '/sam0/drivers/system/pinmux']
src += Glob('./sam0/drivers/system/pinmux/*.c')
path += [cwd + '/sam0/drivers/system/power/power_sam_d_r_h']
path += [cwd + '/sam0/drivers/system/reset/reset_sam_d_r_h']
path += [cwd + '/sam0/drivers/system/clock']
path += [cwd + '/sam0/drivers/system/interrupt/']
src += Glob('./sam0/drivers/system/interrupt/*.c')
if rtconfig.DEVICE_SERIES == 'SAMD20':
path += [cwd + '/sam0/drivers/system/interrupt/system_interrupt_samd20/']
elif rtconfig.DEVICE_SERIES == 'SAMD21':
path += [cwd + '/sam0/drivers/system/interrupt/system_interrupt_samd21/']
#sam0/drivers/system/clock
if rtconfig.DEVICE_SERIES == 'SAMD20':
path += [cwd + '/sam0/drivers/system/clock/clock_samd20']
#path += [cwd + '/sam0/drivers/system/clock/clock_samd20/module_config']
src += Glob('./sam0/drivers/system/clock/clock_samd20/*.c')
elif rtconfig.DEVICE_SERIES == 'SAMD21':
#path += [cwd + '/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/module_config']
path += [cwd + '/sam0/drivers/system/clock/clock_samd21_r21_da_ha1']
src += Glob('./sam0/drivers/system/clock/clock_samd21_r21_da_ha1/*.c')
#sam0/drivers/sercom
path += [cwd + '/sam0/drivers/sercom', cwd + '/sam0/drivers/sercom/usart']
src += Glob('./sam0/drivers/sercom/*.c')
src += Glob('./sam0/drivers/sercom/usart/*.c')
SrcRemove(src, 'sercom_interrupt.c')
SrcRemove(src, 'usart_interrupt.c')
CPPDEFINES += ['USART_CALLBACK_MODE=false']
#sam0/drivers/port
path += [cwd + '/sam0/drivers/port']
src += Glob('./sam0/drivers/port/port.c')
#sam0/drivers/rtc
path += [cwd + '/sam0/drivers/rtc']
src += Glob('./sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count*.c')
CPPDEFINES += ['RTC_COUNT_ASYNC=true']
#sam0/drivers/extint
path += [cwd + '/sam0/drivers/extint', cwd + '/sam0/drivers/extint/extint_sam_d_r_h']
src += Glob('./sam0/drivers/extint/extint_callback.c')
src += Glob('./sam0/drivers/extint/extint_sam_d_r_h/extint.c')
CPPDEFINES += ['EXTINT_CALLBACK_MODE=true']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/**
* \file
*
* \brief Standard board header file.
*
* This file includes the appropriate board header file according to the
* defined board (parameter BOARD).
*
* Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/**
* \defgroup group_common_boards Generic board support
*
* The generic board support module includes board-specific definitions
* and function prototypes, such as the board initialization function.
*
* \{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/*! \name Base Boards
*/
//! @{
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
#define EVK1105 5 //!< AT32UC3A EVK1105 board.
#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
#define UC3L_EK 7 //!< AT32UC3L-EK board.
#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board.
#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board.
#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board.
#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards.
#define RZ600 31 //!< AT32UC3A RZ600 MCU board.
#define SAM3S_EK 32 //!< SAM3S-EK board.
#define SAM3U_EK 33 //!< SAM3U-EK board.
#define SAM3X_EK 34 //!< SAM3X-EK board.
#define SAM3N_EK 35 //!< SAM3N-EK board.
#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
#define SAM4S_EK 37 //!< SAM4S-EK board.
#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
#define STK600_MEGA 39 //!< STK600 MEGA board.
#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board.
#define SAM4L_EK 45 //!< SAM4L-EK board.
#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
#define SAM4E_EK 51 //!< SAM4E-EK board.
#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit.
#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit.
#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit.
#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board.
#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB.
#define SAM4C_EK 64 //!< SAM4C-EK board.
#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
#define ATPL230AMB 73 //!< ATPL230AMB board.
#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board.
#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board.
#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board.
#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board.
#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board.
#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board.
#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board.
#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board.
#define SAME70_XPLAINED 85 //!< SAME70 Xplained board.
#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board.
#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board.
#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board.
#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board.
#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board.
#define SAMB11CSP_XPLAINED_PRO 91 //!< SAM B11 CSP Xplained Pro board.
#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board.
#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board.
#define SAMHA1G16A_XPLAINED_PRO 94 //!< SAM HA1G16A Xplained Pro board.
#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices.
#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
#define USER_BOARD 99 //!< User-reserved board (if any).
#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader).
//! @}
/*! \name Extension Boards
*/
//! @{
#define EXT1102 1 //!< AT32UC3B EXT1102 board
#define MC300 2 //!< AT32UC3 MC300 board
#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
//! @}
#if BOARD == EVK1100
# include "evk1100/evk1100.h"
#elif BOARD == EVK1101
# include "evk1101/evk1101.h"
#elif BOARD == UC3C_EK
# include "uc3c_ek/uc3c_ek.h"
#elif BOARD == EVK1104
# include "evk1104/evk1104.h"
#elif BOARD == EVK1105
# include "evk1105/evk1105.h"
#elif BOARD == STK600_RCUC3L0
# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
#elif BOARD == UC3L_EK
# include "uc3l_ek/uc3l_ek.h"
#elif BOARD == STK600_RCUC3L4
# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
#elif BOARD == XPLAIN
# include "xplain/xplain.h"
#elif BOARD == STK600_MEGA
/*No header-file to include*/
#elif BOARD == STK600_MEGA_RF
# include "stk600.h"
#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
#elif BOARD == ATMEGA256RFR2_ZIGBIT
# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
#elif BOARD == STK600_RC032X
# include "stk600/rc032x/stk600_rc032x.h"
#elif BOARD == STK600_RC044X
# include "stk600/rc044x/stk600_rc044x.h"
#elif BOARD == STK600_RC064X
# include "stk600/rc064x/stk600_rc064x.h"
#elif BOARD == STK600_RC100X
# include "stk600/rc100x/stk600_rc100x.h"
#elif BOARD == UC3_A3_XPLAINED
# include "uc3_a3_xplained/uc3_a3_xplained.h"
#elif BOARD == UC3_L0_XPLAINED
# include "uc3_l0_xplained/uc3_l0_xplained.h"
#elif BOARD == STK600_RCUC3B0
# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
#elif BOARD == STK600_RCUC3D
# include "stk600/rcuc3d/stk600_rcuc3d.h"
#elif BOARD == STK600_RCUC3C0
# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
#elif BOARD == SAMG53_XPLAINED_PRO
# include "samg53_xplained_pro/samg53_xplained_pro.h"
#elif BOARD == SAMG55_XPLAINED_PRO
# include "samg55_xplained_pro/samg55_xplained_pro.h"
#elif BOARD == XMEGA_B1_XPLAINED
# include "xmega_b1_xplained/xmega_b1_xplained.h"
#elif BOARD == STK600_RC064X_LCDX
# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
#elif BOARD == STK600_RC100X_LCDX
# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
#elif BOARD == XMEGA_A1_XPLAINED
# include "xmega_a1_xplained/xmega_a1_xplained.h"
#elif BOARD == XMEGA_A1U_XPLAINED_PRO
# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
#elif BOARD == UC3_L0_XPLAINED_BC
# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
#elif BOARD == SAM3S_EK
# include "sam3s_ek/sam3s_ek.h"
# include "system_sam3s.h"
#elif BOARD == SAM3S_EK2
# include "sam3s_ek2/sam3s_ek2.h"
# include "system_sam3sd8.h"
#elif BOARD == SAM3U_EK
# include "sam3u_ek/sam3u_ek.h"
# include "system_sam3u.h"
#elif BOARD == SAM3X_EK
# include "sam3x_ek/sam3x_ek.h"
# include "system_sam3x.h"
#elif BOARD == SAM3N_EK
# include "sam3n_ek/sam3n_ek.h"
# include "system_sam3n.h"
#elif BOARD == SAM4S_EK
# include "sam4s_ek/sam4s_ek.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_WPIR_RD
# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_XPLAINED
# include "sam4s_xplained/sam4s_xplained.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_EK2
# include "sam4s_ek2/sam4s_ek2.h"
# include "system_sam4s.h"
#elif BOARD == MEGA_1284P_XPLAINED
/*No header-file to include*/
#elif BOARD == ARDUINO_DUE_X
# include "arduino_due_x/arduino_due_x.h"
# include "system_sam3x.h"
#elif BOARD == SAM4L_EK
# include "sam4l_ek/sam4l_ek.h"
#elif BOARD == SAM4E_EK
# include "sam4e_ek/sam4e_ek.h"
#elif BOARD == SAMD20_XPLAINED_PRO
# include "samd20_xplained_pro/samd20_xplained_pro.h"
#elif BOARD == SAMD21_XPLAINED_PRO
# include "samd21_xplained_pro/samd21_xplained_pro.h"
#elif BOARD == SAMR21_XPLAINED_PRO
# include "samr21_xplained_pro/samr21_xplained_pro.h"
#elif BOARD == SAMR30_XPLAINED_PRO
# include "samr30_xplained_pro/samr30_xplained_pro.h"
#elif BOARD == SAMR21ZLL_EK
# include "samr21zll_ek/samr21zll_ek.h"
#elif BOARD == SAMD11_XPLAINED_PRO
# include "samd11_xplained_pro/samd11_xplained_pro.h"
#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
# include "saml21_xplained_pro/saml21_xplained_pro.h"
#elif BOARD == SAML22_XPLAINED_PRO
# include "saml22_xplained_pro/saml22_xplained_pro.h"
#elif BOARD == SAML22_XPLAINED_PRO_B
# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
# include "saml21_xplained_pro_b/saml21_xplained_pro.h"
#elif BOARD == SAMD10_XPLAINED_MINI
# include "samd10_xplained_mini/samd10_xplained_mini.h"
#elif BOARD == SAMDA1_XPLAINED_PRO
# include "samda1_xplained_pro/samda1_xplained_pro.h"
#elif BOARD == SAMHA1G16A_XPLAINED_PRO
# include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
#elif BOARD == SAMC21_XPLAINED_PRO
# include "samc21_xplained_pro/samc21_xplained_pro.h"
#elif BOARD == SAM4N_XPLAINED_PRO
# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
#elif BOARD == SAMW25_XPLAINED_PRO
# include "samw25_xplained_pro/samw25_xplained_pro.h"
#elif BOARD == SAMV71_XPLAINED_ULTRA
# include "samv71_xplained_ultra/samv71_xplained_ultra.h"
#elif BOARD == MEGA1284P_XPLAINED_BC
# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
#elif BOARD == UC3_L0_QT600
# include "uc3_l0_qt600/uc3_l0_qt600.h"
#elif BOARD == XMEGA_A3BU_XPLAINED
# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
#elif BOARD == XMEGA_E5_XPLAINED
# include "xmega_e5_xplained/xmega_e5_xplained.h"
#elif BOARD == UC3B_BOARD_CONTROLLER
# include "uc3b_board_controller/uc3b_board_controller.h"
#elif BOARD == RZ600
# include "rz600/rz600.h"
#elif BOARD == STK600_RCUC3A0
# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
#elif BOARD == ATXMEGA128A1_QT600
# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
#elif BOARD == STK600_RCUC3L3
# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
#elif BOARD == SAM4S_XPLAINED_PRO
# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
#elif BOARD == SAM4L_XPLAINED_PRO
# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
#elif BOARD == SAM4L8_XPLAINED_PRO
# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
#elif BOARD == SAM4C_EK
# include "sam4c_ek/sam4c_ek.h"
#elif BOARD == SAM4CMP_DB
# include "sam4cmp_db/sam4cmp_db.h"
#elif BOARD == SAM4CMS_DB
# include "sam4cms_db/sam4cms_db.h"
#elif BOARD == SAM4CP16BMB
# include "sam4cp16bmb/sam4cp16bmb.h"
#elif BOARD == ATPL230AMB
# include "atpl230amb/atpl230amb.h"
#elif BOARD == XMEGA_C3_XPLAINED
# include "xmega_c3_xplained/xmega_c3_xplained.h"
#elif BOARD == XMEGA_RF233_ZIGBIT
# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
#elif BOARD == XMEGA_A3_REB_CBB
# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
#elif BOARD == ATMEGARFX_RCB
# include "atmegarfx_rcb/atmegarfx_rcb.h"
#elif BOARD == RCB256RFR2_XPRO
# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
#elif BOARD == XMEGA_RF212B_ZIGBIT
# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
#elif BOARD == SAM4E_XPLAINED_PRO
# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
#elif BOARD == ATMEGA328P_XPLAINED_MINI
# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
#elif BOARD == ATMEGA328PB_XPLAINED_MINI
# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
#elif BOARD == SAMB11_XPLAINED_PRO
# include "samb11_xplained_pro/samb11_xplained_pro.h"
#elif BOARD == SAME70_XPLAINED
# include "same70_xplained/same70_xplained.h"
#elif BOARD == ATMEGA168PB_XPLAINED_MINI
# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
#elif BOARD == ATMEGA324PB_XPLAINED_PRO
# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
#elif BOARD == SAMB11CSP_XPLAINED_PRO
# include "samb11csp_xplained_pro/samb11csp_xplained_pro.h"
#elif BOARD == SAMB11ZR_XPLAINED_PRO
# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
#elif BOARD == SIMULATOR_XMEGA_A1
# include "simulator/xmega_a1/simulator_xmega_a1.h"
#elif BOARD == AVR_SIMULATOR_UC3
# include "avr_simulator_uc3/avr_simulator_uc3.h"
#elif BOARD == USER_BOARD
// User-reserved area: #include the header file of your board here (if any).
# include "user_board.h"
#elif BOARD == DUMMY_BOARD
# include "dummy/dummy_board.h"
#else
# error No known Atmel board defined
#endif
#if (defined EXT_BOARD)
# if EXT_BOARD == MC300
# include "mc300/mc300.h"
# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
(EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
(EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
(EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
# include "sensors_xplained/sensors_xplained.h"
# elif EXT_BOARD == RZ600_AT86RF231
# include "at86rf231/at86rf231.h"
# elif EXT_BOARD == RZ600_AT86RF230B
# include "at86rf230b/at86rf230b.h"
# elif EXT_BOARD == RZ600_AT86RF212
# include "at86rf212/at86rf212.h"
# elif EXT_BOARD == SECURITY_XPLAINED
# include "security_xplained.h"
# elif EXT_BOARD == USER_EXT_BOARD
// User-reserved area: #include the header file of your extension board here
// (if any).
# endif
#endif
#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
/*! \brief This function initializes the board target resources
*
* This function should be called to ensure proper initialization of the target
* board hardware connected to the part.
*/
extern void board_init(void);
#endif // #ifdef __AVR32_ABI_COMPILER__
#else
/*! \brief This function initializes the board target resources
*
* This function should be called to ensure proper initialization of the target
* board hardware connected to the part.
*/
extern void board_init(void);
#endif
#ifdef __cplusplus
}
#endif
/**
* \}
*/
#endif // _BOARD_H_

76
bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c Normal file
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@@ -0,0 +1,76 @@
/**
* \file
*
* \brief SECURITY_XPLAINED extension board adaptation.
*
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "security_xplained.h"
#include "sha204_physical.h"
#include "conf_atsha204.h"
//! TWI address used at SHA204 library startup
#define SHA204_I2C_DEFAULT_ADDRESS (0xCA)
/** \brief This function initializes peripherals needed to communicate with
* the I2C security devices (ATSHA204 and ATAES132).
*/
void security_board_init(void)
{
sha204p_init();
}
/** \brief This function returns the I2C address of a chosen SHA204 device.
* \param[in] index the selected device on the Security Xplained board
* \return I2C address of chosen device
*/
uint8_t sha204_i2c_address(uint8_t index)
{
static uint8_t i2c_addresses[SHA204_DEVICE_COUNT] = {SHA204_I2C_DEFAULT_ADDRESS, 0xCC, 0xCE, 0xF8};
return i2c_addresses[index % SHA204_DEVICE_COUNT];
}

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/**
* \file
*
* \brief SECURITY_XPLAINED_BOARD board header file.
*
* This file contains definitions and services related to the features of the
* SECURITY_XPLAINED Xplained board.
*
* To use the board, define EXT_BOARD=SECURITY_XPLAINED.
*
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef SECURITY_XPLAINED_H_
# define SECURITY_XPLAINED_H_
#include <compiler.h>
//! number of ATSHA204 I2C devices on Security Xplained extension board
#define SHA204_DEVICE_COUNT (4)
void security_board_init(void);
uint8_t sha204_i2c_address(uint8_t index);
#endif /* SECURITY_XPLAINED_H_ */

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/**
* \file
*
* \brief SENSORS_XPLAINED_BOARD extension board adaptation.
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "sensors_xplained.h"
#include <sysclk.h>
#if UC3
# include <eic.h>
#endif
#if UC3
# define PIN_OUTPUT_FLAGS (GPIO_DIR_OUTPUT | GPIO_INIT_HIGH)
# define PIN_INPUT_FLAGS (GPIO_DIR_INPUT)
#elif XMEGA
# define PIN_OUTPUT_FLAGS (IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH)
# define PIN_INPUT_FLAGS (IOPORT_DIR_INPUT)
#endif
#if defined(__AVR32__) || defined(__ICCAVR32__)
# if !defined(AVR32_GPIO_IRQ_GROUP)
# define AVR32_GPIO_IRQ_GROUP (AVR32_GPIO_IRQ_0 / 32)
# endif
# if defined(CONFIG_GPIO_INT_LVL)
# define GPIO_INT_LVL CONFIG_GPIO_INT_LVL
# else
# define GPIO_INT_LVL 0
# endif
# if !defined(AVR32_EIC_IRQ_GROUP)
# if UC3L
# define AVR32_EIC_IRQ_GROUP (AVR32_EIC_IRQ_1 / 32)
# else
# define AVR32_EIC_IRQ_GROUP (AVR32_EIC_IRQ_0 / 32)
# endif
# endif
# if defined(CONFIG_EIC_INT_LVL)
# define EIC_INT_LVL CONFIG_EIC_INT_LVL
# else
# define EIC_INT_LVL 0
# endif
#endif /* (__AVR32__) || (__ICCAVR32__) */
/* Don't include interrupt definitions without a valid board configuration. */
#if defined(SENSORS_XPLAINED_BOARD) && defined(COMMON_SENSOR_PLATFORM)
/*! \internal
* \name Sensor Board GPIO interrupt handler callback pointers
* @{
*/
static SENSOR_IRQ_HANDLER sensor_pin3_handler;
static volatile void *sensor_pin3_arg;
static SENSOR_IRQ_HANDLER sensor_pin4_handler;
static volatile void *sensor_pin4_arg;
static SENSOR_IRQ_HANDLER sensor_pin5_handler;
static volatile void *sensor_pin5_arg;
/*! @} */
#if UC3
/*! \internal Sensor Board GPIO interrupt handler
*
* This is the default ISR for the Xplained Sensor board GPIO pins. If
* an external interrupt interface is available, the corresponding
* eic_pinX_handler will be used instead.
*
* \return Nothing.
*/
ISR(gpio_irq_handler, AVR32_GPIO_IRQ_GROUP, GPIO_INT_LVL)
{
if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN3)) {
sensor_pin3_handler(sensor_pin3_arg);
gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN3);
} else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN4)) {
sensor_pin4_handler(sensor_pin4_arg);
gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN4);
} else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN5)) {
sensor_pin5_handler(sensor_pin5_arg);
gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN5);
}
}
#elif XMEGA
/*! \internal Sensor Board GPIO interrupt handler
*
* This is the default ISR for the Xplained Sensor board GPIO pins. The
* installed handler routine for the particular pin will be called with
* the argument specified when the handler was installed..
*
* \return Nothing.
*/
ISR(SENSOR_BOARD_PORT_vect)
{
PORT_t *const port = &(SENSOR_BOARD_PORT);
/* Call the interrupt handler (if any). */
if (sensor_pin3_handler && (port->IN & PIN2_bm)) {
/* Note: header pin 3 = io port pin 2 */
sensor_pin3_handler(sensor_pin3_arg);
} else if (sensor_pin4_handler && (port->IN & PIN3_bm)) {
/* Note: header pin 4 = io port pin 3 */
sensor_pin4_handler(sensor_pin4_arg);
} else if (sensor_pin5_handler && (port->IN & PIN4_bm)) {
/* Note: header pin 5 = io port pin 4 */
sensor_pin5_handler(sensor_pin5_arg);
}
/* Clear the port interrupt flag */
port->INTFLAGS = PORT_INT0IF_bm;
}
#endif
#if defined(SENSOR_PIN3_EIC_LINE)
/*! \internal Sensor Board external interrupt handler - PIN3
*
* This is the ISR for the Xplained Sensor board GPIO PIN3 for configurations
* in which it can generate an external interrupt.
*
* \return Nothing.
*/
ISR(eic_pin3_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
{
sensor_pin3_handler(sensor_pin3_arg); /* call handler in driver */
eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN3_EIC_LINE);
}
#endif
#if defined(SENSOR_PIN4_EIC_LINE)
/*! \internal Sensor Board external interrupt handler - PIN4
*
* This is the ISR for the Xplained Sensor board GPIO PIN4 for configurations
* in which it can generate an external interrupt.
*
* \return Nothing.
*/
ISR(eic_pin4_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
{
sensor_pin4_handler(sensor_pin4_arg); /* call handler in driver */
eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN4_EIC_LINE);
}
#endif
#if defined(SENSOR_PIN5_EIC_LINE)
/*! \internal Sensor Board external interrupt handler - PIN5
*
* This is the ISR for the Xplained Sensor board GPIO PIN5 for configurations
* in which it can generate an external interrupt.
*
* \return Nothing.
*/
ISR(eic_pin5_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
{
sensor_pin5_handler(sensor_pin5_arg); /* call handler in driver */
eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN5_EIC_LINE);
}
#endif
#if UC3
/*! \internal Enable a general purpose I/O pin interrupt.
*
* This routine enables interrupts on a specified general purpose I/O pin.
*
* \param gpio_pin GPIO pin interface to the MCU
* \param gpio_irq IRQ of the interrupt handler
*/
static void gpio_irq_connect(uint32_t gpio_pin, uint32_t gpio_irq)
{
irq_register_handler(gpio_irq_handler, gpio_irq, GPIO_INT_LVL);
gpio_enable_pin_interrupt(gpio_pin, GPIO_RISING_EDGE);
}
#endif
#if defined(SYSCLK_EIC)
/*! \brief Enable an EIC interrupt line.
*
* This routine maps a GPIO pin and peripheral function to a specified EIC line.
*
* \param eic_line Line number to enable
* \param eic_pin GPIO module pin
* \param eic_func GPIO module function
* \param eic_irq IRQ of the interrupt handler
* \param eic_handler Interrupt handler to register
*/
static void eic_irq_connect(uint32_t eic_line, uint32_t eic_pin,
uint32_t eic_func, uint32_t eic_irq, __int_handler eic_handler)
{
eic_options_t const eic_options = {
.eic_line = eic_line,
.eic_mode = EIC_MODE_EDGE_TRIGGERED,
.eic_edge = EIC_EDGE_RISING_EDGE,
.eic_level = EIC_LEVEL_HIGH_LEVEL,
.eic_filter = EIC_FILTER_ENABLED,
.eic_async = EIC_ASYNCH_MODE
};
sysclk_enable_pba_module(SYSCLK_EIC);
gpio_enable_module_pin(eic_pin, eic_func);
irq_register_handler(eic_handler, eic_irq, 0);
eic_init(&AVR32_EIC, &eic_options, 1);
eic_enable_line(&AVR32_EIC, eic_line);
eic_enable_interrupt_line(&AVR32_EIC, eic_line);
}
#endif
/*! \brief Install a sensor interrupt handler
*
* The Sensors Xplained add-on boards route sensor device I/O pins to GPIO
* pins for the MCU installed on an Xplained platform board. Some sensor
* devices can be configured to generate interrupts on these pins to indicate
* the availability of new sensor data or the occurrence of configurable
* events related to sensor data thresholds, for example.
*
* This routine will enable interrupts on the GPIO pin specified by the
* \c gpio_pin parameter and call a user-defined callback \c handler when an
* interrupt is detected. The \c arg parameter is used to pass the address
* of user-defined input and output storage for the callback handler. Calling
* the routine with the \c handler parameter set to 0 (the NULL pointer) will
* fail with \c false returned to the caller.
*
* \param gpio_pin Board-specific GPIO pin interface to the MCU.
* \param handler The address of a driver-defined interrupt handler.
* \param arg An optional address passed to the interrupt handler.
*
* \return bool true if the call succeeds, else false.
*/
bool sensor_board_irq_connect(uint32_t gpio_pin,
SENSOR_IRQ_HANDLER handler, void *arg)
{
bool status = false;
#if XMEGA
PORT_t *sensor_port;
#endif
/* Ensure that the caller has specified a function address. */
if (handler == NULL) {
return status;
}
/* Save the interrupt flag state and disable MCU interrupts. */
irqflags_t const irq_flags = cpu_irq_save();
cpu_irq_disable();
/* Initialize an interrupt for a specified I/O pin. */
if (SENSOR_BOARD_PIN3 == gpio_pin) {
sensor_pin3_handler = handler;
sensor_pin3_arg = arg;
#if UC3
# if defined(SENSOR_PIN3_EIC_LINE)
eic_irq_connect(SENSOR_PIN3_EIC_LINE, SENSOR_PIN3_EIC_PIN,
SENSOR_PIN3_EIC_FUNC, SENSOR_PIN3_EIC_IRQ,
eic_pin3_handler);
# else
gpio_irq_connect(gpio_pin, SENSOR_PIN3_IRQ);
# endif
#elif XMEGA
sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN3);
sensor_port->INTCTRL = PORT_INT0LVL_LO_gc;
sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN3);
/* Some Xplained kits have limited asynchronous sensing on most
* pins, which requires them to be sensing on both edges.
*/
ioport_set_pin_sense_mode(SENSOR_BOARD_PIN3,
IOPORT_SENSE_BOTHEDGES);
#endif
status = true;
} else if (SENSOR_BOARD_PIN4 == gpio_pin) {
sensor_pin4_handler = handler;
sensor_pin4_arg = arg;
#if UC3
# if defined(SENSOR_PIN4_EIC_LINE)
eic_irq_connect(SENSOR_PIN4_EIC_LINE, SENSOR_PIN4_EIC_PIN,
SENSOR_PIN4_EIC_FUNC, SENSOR_PIN4_EIC_IRQ,
eic_pin4_handler);
# else
gpio_irq_connect(gpio_pin, SENSOR_PIN4_IRQ);
# endif
#elif XMEGA
sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN4);
sensor_port->INTCTRL = PORT_INT0LVL_LO_gc;
sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN4);
/* Some Xplained kits have limited asynchronous sensing on most
* pins, which requires them to be sensing on both edges.
*/
ioport_set_pin_sense_mode(SENSOR_BOARD_PIN4,
IOPORT_SENSE_BOTHEDGES);
#endif
status = true;
} else if (SENSOR_BOARD_PIN5 == gpio_pin) {
sensor_pin5_handler = handler;
sensor_pin5_arg = arg;
#if UC3
# if defined(SENSOR_PIN5_EIC_LINE)
eic_irq_connect(SENSOR_PIN5_EIC_LINE, SENSOR_PIN5_EIC_PIN,
SENSOR_PIN5_EIC_FUNC, SENSOR_PIN5_EIC_IRQ,
eic_pin5_handler);
# else
gpio_irq_connect(gpio_pin, SENSOR_PIN5_IRQ);
# endif
#elif XMEGA
sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN5);
sensor_port->INTCTRL = PORT_INT0LVL_LO_gc;
sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN5);
/* Some Xplained kits have limited asynchronous sensing on most
* pins, which requires them to be sensing on both edges.
*/
ioport_set_pin_sense_mode(SENSOR_BOARD_PIN5,
IOPORT_SENSE_BOTHEDGES);
#endif
status = true;
}
/* Restore the MCU interrupt flag state. */
cpu_irq_restore(irq_flags);
return status;
}
#endif /* defined(SENSORS_XPLAINED_BOARD) && defined(COMMON_SENSOR_PLATFORM) */
/*! \brief Initialize sensor board target resources
*
* This function should be called to ensure proper initialization
* of sensor hardware connected to an Atmel AVR32 or XMEGA platform.
*
* \return Nothing.
*/
void sensor_board_init(void)
{
/* Configure all defined Xplained Sensor board I/O pins.
*
* \todo
* Determine whether the interrupt event flag (rising edge, falling
* edge, toggle, etc.) should be a statically configurable parameter
* for devices requiring more flexibility in how events are detected.
*/
#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
gpio_configure_pin(SENSOR_BOARD_PIN5, PIN_INPUT_FLAGS);
#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_OUTPUT_FLAGS);
gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
#endif
/* Global Interrupt Disable */
cpu_irq_disable();
/* Initialize interrupt vector table support. */
irq_initialize_vectors();
/* Global Interrupt Enable */
cpu_irq_enable();
}

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/**
* \file
*
* \brief SENSORS_XPLAINED_BOARD board header file.
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _sensors_xplained_h_
#define _sensors_xplained_h_
/**
* \defgroup group_common_boards_sensors_xplained Sensors Xplained Extension Boards
*
* This file contains definitions and services related to the features of the
* SENSORS_XPLAINED_XXX Xplained boards.
*
* To use these boards, define EXT_BOARD=SENSORS_XPLAINED_XXX, where \c 'XXX'
* is a place holder for the specific sensor extension board as defined in
* the board.h file. For example, \ref SENSORS_XPLAINED_INERTIAL_1 selects a
* configuration supporting the Atmel Inertial Sensor Board #1.
*
* When this header file is included in a platform build, the
* \ref SENSORS_XPLAINED_BOARD configuration constant will be defined so
* that conditionally built pieces of platform functionality can be invoked
* to make the sensor board usable to the system. For example, the
* platform board_init() routine can conditionally compile calls to
* sensor_board_init().
*
* \{
*/
#include "xplained_headers.h"
#include "conf_board.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup atavrsb_config Sensors Xplained Extension Board Configuration
* @brief
* The extension board configuration defines constants identifying the sensors,
* bus interface, I/O pin mappings, and sensor device signals from an Atmel
* Sensor board (\p ATAVRSBPR1, \p ATAVARSBIN1, \p ATAVARSBIN2, and so on)
* to the development platform.
*
* @sa atavrpb_config
* @{
*/
/**
* \name Common Sensor Service Configuration Constants
*
* \brief
* This module defines \ref mems_sensor_api configuration constants based
* upon a user-specified \b EXT_BOARD value. The Sensor Service determines
* which drivers and bus interface modules to use based upon these definitions.
* When \b EXT_BOARD defines a valid Sensors Xplained board constant, a
* catch-all constant named SENSORS_XPLAINED_BOARD is defined so that platform,
* service, and other code can be conditionally configured without testing for
* every particular Sensors Xplained board constant.
*
* All of the following boards are compatible with the Atmel Xplained MCU
* boards provided the required I/O peripheral pin mapping has been added
* and a call to the sensor_board_init() routine has been included in the
* board_init() routine.
*
* \par ATAVRSBIN1 Inertial Sensor Board No. 1
*
* This sensor board includes an InvenSense 3-axis gyro (ITG-3200), Bosch
* 3-axis accelerometer (BMA150), and AKM 3-axis magnetometer (AK8975).
* These sensors are interfaced via a TWI master bus mapped to pins on the
* J1 I/O expansion header on an Xplained development platform. When the
* EXT_BOARD value is set to \ref SENSORS_XPLAINED_INERTIAL_1, the following
* are defined:
*
* - \c CONF_SENSOR_BUS_TWI
* - \c INCLUDE_AK8975
* - \c INCLUDE_BMA150
* - \c INCLUDE_ITG3200
*
* \par ATAVRSBIN2 Inertial Sensor Board No. 2
*
* This sensor board includes an InvenSense 3-axis gyro (IMU-3000), Kionix
* 3-axis accelerometer (KXTF9), and Honeywell 3-axis magnetometer (HMC5883).
* These sensors are interfaced via a TWI master bus mapped to pins on the
* J1 I/O expansion header on an Xplained development platform. When the
* EXT_BOARD value is set to \ref SENSORS_XPLAINED_INERTIAL_2, the following
* are defined:
*
* - \c CONF_SENSOR_BUS_TWI
* - \c INCLUDE_HMC5883L
* - \c INCLUDE_IMU3000
* - \c INCLUDE_KXTF9
*
* \par ATAVRSBPR1 Barometric Pressure Sensor Board No. 1
*
* This sensor board includes a Bosch barometric pressure sensor (BMP085).
* This sensor is interfaced via a TWI master bus mapped to pins on the
* J1 I/O expansion header on an Xplained development platform. When the
* EXT_BOARD value is set to \ref SENSORS_XPLAINED_PRESSURE_1, the following
* are defined:
*
* - \c CONF_SENSOR_BUS_TWI
* - \c INCLUDE_BMP085
*
* \par ATAVRSBLP1 Ambient Light & IR Proximity Sensor Board No. 1
*
* This sensor board includes an Osram IR light/proximity sensor (SFH7770).
* This sensor is interfaced via a TWI master bus mapped to pins on the
* J1 I/O expansion header on an Xplained development platform. When the
* EXT_BOARD value is set to \ref SENSORS_XPLAINED_LIGHTPROX_1, the following
* are defined:
*
* - \c CONF_SENSOR_BUS_TWI
* - \c INCLUDE_SFH7770
*
* The following list summarizes available sensor service configuration
* constants that are specified by board configurations defined in this
* module.
* @{
*/
#define SENSORS_XPLAINED_BOARD
#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)
# define CONF_SENSOR_BUS_TWI
# define INCLUDE_AK8975
# define INCLUDE_BMA150
# define INCLUDE_ITG3200
#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)
# define CONF_SENSOR_BUS_TWI
# define INCLUDE_HMC5883L
# define INCLUDE_IMU3000
# define INCLUDE_KXTF9
#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
# define CONF_SENSOR_BUS_TWI
# define INCLUDE_AK8975
# define INCLUDE_IMU3000
# define INCLUDE_KXTF9
#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
# define CONF_SENSOR_BUS_TWI
# define INCLUDE_BMP085
#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
# define CONF_SENSOR_BUS_TWI
# define INCLUDE_SFH7770
#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
# define CONF_SENSOR_BUS_TWI
# define INCLUDE_BMA222
#else
# undef SENSORS_XPLAINED_BOARD
# warning "The EXT_BOARD constant does not define a Sensors Xplained board."
#endif
// @}
/*! \name Xplained Board J1 Connector Pin Mapping
*
* \internal
* These constants map AVR & AVR32 ports to pins on the Xplained board J1
* connector where pins on the 10-pin header correspond to the following
* functions:
*
* \code
10-pin Header Function
-------------------------------------------
Pin 1 SDA
Pin 2 SCL
Pin 3 RXD
Pin 4 TXD
Pin 5 SS
Pin 6 MOSI
Pin 7 MISO
Pin 8 SCK
\endcode
* @{
*/
#define SENSOR_BOARD_PIN1 XPLD_HEADER_J1_PIN1
#define SENSOR_BOARD_PIN2 XPLD_HEADER_J1_PIN2
#define SENSOR_BOARD_PIN3 XPLD_HEADER_J1_PIN3
#define SENSOR_BOARD_PIN4 XPLD_HEADER_J1_PIN4
#define SENSOR_BOARD_PIN5 XPLD_HEADER_J1_PIN5
#define SENSOR_BOARD_PIN6 XPLD_HEADER_J1_PIN6
#define SENSOR_BOARD_PIN7 XPLD_HEADER_J1_PIN7
#define SENSOR_BOARD_PIN8 XPLD_HEADER_J1_PIN8
#if XMEGA
# define SENSOR_BOARD_PORT XPLD_HEADER_J1_PORT
# define SENSOR_BOARD_PORT_vect XPLD_HEADER_J1_INT0_vect
#endif
// @}
/*! \name Sensor Device Interrupt Routing
*
* \internal
* The following constants map I/O expansion header pins that are used as
* sensor event signal inputs to the MCU interrupt controller lines and IRQ
* numbers.
*
* These definitions are provided as a board-level description for the
* sensor drivers and are not used directly in sensor service client
* applications.
* @{
*/
#define INVALID_IRQ_NUMBER ((unsigned int) -1)
#if UC3
# define SENSOR_PIN1_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN1 / 8))
# define SENSOR_PIN2_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN2 / 8))
# define SENSOR_PIN3_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN3 / 8))
# define SENSOR_PIN4_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN4 / 8))
# define SENSOR_PIN5_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN5 / 8))
# define SENSOR_PIN6_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN6 / 8))
# define SENSOR_PIN7_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN7 / 8))
# define SENSOR_PIN8_IRQ (AVR32_GPIO_IRQ_0 + (SENSOR_BOARD_PIN8 / 8))
#else
# define SENSOR_PIN1_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN2_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN3_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN4_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN5_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN6_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN7_IRQ (INVALID_IRQ_NUMBER)
# define SENSOR_PIN8_IRQ (INVALID_IRQ_NUMBER)
#endif
#ifdef XPLD_HEADER_J1_PIN1_EIC_LINE
# define SENSOR_PIN1_EIC_LINE XPLD_HEADER_J1_PIN1_EIC_LINE
# define SENSOR_PIN1_EIC_IRQ XPLD_HEADER_J1_PIN1_EIC_IRQ
# define SENSOR_PIN1_EIC_PIN XPLD_HEADER_J1_PIN1_EIC_PIN
# define SENSOR_PIN1_EIC_FUNC XPLD_HEADER_J1_PIN1_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN2_EIC_LINE
# define SENSOR_PIN2_EIC_LINE XPLD_HEADER_J1_PIN2_EIC_LINE
# define SENSOR_PIN2_EIC_IRQ XPLD_HEADER_J1_PIN2_EIC_IRQ
# define SENSOR_PIN2_EIC_PIN XPLD_HEADER_J1_PIN2_EIC_PIN
# define SENSOR_PIN2_EIC_FUNC XPLD_HEADER_J1_PIN2_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN3_EIC_LINE
# define SENSOR_PIN3_EIC_LINE XPLD_HEADER_J1_PIN3_EIC_LINE
# define SENSOR_PIN3_EIC_IRQ XPLD_HEADER_J1_PIN3_EIC_IRQ
# define SENSOR_PIN3_EIC_PIN XPLD_HEADER_J1_PIN3_EIC_PIN
# define SENSOR_PIN3_EIC_FUNC XPLD_HEADER_J1_PIN3_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN4_EIC_LINE
# define SENSOR_PIN4_EIC_LINE XPLD_HEADER_J1_PIN4_EIC_LINE
# define SENSOR_PIN4_EIC_IRQ XPLD_HEADER_J1_PIN4_EIC_IRQ
# define SENSOR_PIN4_EIC_PIN XPLD_HEADER_J1_PIN4_EIC_PIN
# define SENSOR_PIN4_EIC_FUNC XPLD_HEADER_J1_PIN4_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN5_EIC_LINE
# define SENSOR_PIN5_EIC_LINE XPLD_HEADER_J1_PIN5_EIC_LINE
# define SENSOR_PIN5_EIC_IRQ XPLD_HEADER_J1_PIN5_EIC_IRQ
# define SENSOR_PIN5_EIC_PIN XPLD_HEADER_J1_PIN5_EIC_PIN
# define SENSOR_PIN5_EIC_FUNC XPLD_HEADER_J1_PIN5_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN6_EIC_LINE
# define SENSOR_PIN6_EIC_LINE XPLD_HEADER_J1_PIN6_EIC_LINE
# define SENSOR_PIN6_EIC_IRQ XPLD_HEADER_J1_PIN6_EIC_IRQ
# define SENSOR_PIN6_EIC_PIN XPLD_HEADER_J1_PIN6_EIC_PIN
# define SENSOR_PIN6_EIC_FUNC XPLD_HEADER_J1_PIN6_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN7_EIC_LINE
# define SENSOR_PIN7_EIC_LINE XPLD_HEADER_J1_PIN7_EIC_LINE
# define SENSOR_PIN7_EIC_IRQ XPLD_HEADER_J1_PIN7_EIC_IRQ
# define SENSOR_PIN7_EIC_PIN XPLD_HEADER_J1_PIN7_EIC_PIN
# define SENSOR_PIN7_EIC_FUNC XPLD_HEADER_J1_PIN7_EIC_FUNC
#endif
#ifdef XPLD_HEADER_J1_PIN8_EIC_LINE
# define SENSOR_PIN8_EIC_LINE XPLD_HEADER_J1_PIN8_EIC_LINE
# define SENSOR_PIN8_EIC_IRQ XPLD_HEADER_J1_PIN8_EIC_IRQ
# define SENSOR_PIN8_EIC_PIN XPLD_HEADER_J1_PIN8_EIC_PIN
# define SENSOR_PIN8_EIC_FUNC XPLD_HEADER_J1_PIN8_EIC_FUNC
#endif
// @}
/*! \name Sensor Device I/O Pins
*
* \internal
* The following constants specify I/O expansion header pins that are used as
* sensor event signal inputs to the MCU and, in some cases, control signal
* outputs from the MCU to the sensor device. For example, the \c BMP085
* pressure sensor on the \c ATAVRSBPR1 board provides a pressure sample
* End-of-Conversion (EOC) input signal to the MCU and a device "master clear"
* and reset signal (XCLR) output from the MCU to the sensor.
*
* These definitions are provided as a board-level description for the
* sensor drivers and are not used directly in sensor service client
* applications.
* @{
*/
#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)
# define ak8975_sigint (SENSOR_BOARD_PIN3)
# define bma150_sigint (SENSOR_BOARD_PIN4)
# define itg3200_sigint (SENSOR_BOARD_PIN5)
# define ak8975_sigout (INVALID_PIN_NUMBER)
# define bma150_sigout (INVALID_PIN_NUMBER)
# define itg3200_sigout (INVALID_PIN_NUMBER)
#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)
# define hmc5883l_sigint (SENSOR_BOARD_PIN3)
# define kxtf9_sigint (SENSOR_BOARD_PIN4)
# define imu3000_sigint (SENSOR_BOARD_PIN5)
# define hmc5883l_sigout (INVALID_PIN_NUMBER)
# define kxtf9_sigout (INVALID_PIN_NUMBER)
# define imu3000_sigout (INVALID_PIN_NUMBER)
#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
# define ak8975_sigint (SENSOR_BOARD_PIN3)
# define kxtf9_sigint (SENSOR_BOARD_PIN4)
# define imu3000_sigint (SENSOR_BOARD_PIN5)
# define ak8975_sigout (INVALID_PIN_NUMBER)
# define kxtf9_sigout (INVALID_PIN_NUMBER)
# define imu3000_sigout (INVALID_PIN_NUMBER)
#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
# define bmp085_sigint (SENSOR_BOARD_PIN4)
# define bmp085_sigout (SENSOR_BOARD_PIN3)
#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
# define sfh7770_sigint (SENSOR_BOARD_PIN3)
# define sfh7770_sigout (INVALID_PIN_NUMBER)
#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
# define bma222_sigint (SENSOR_BOARD_PIN4)
# define bma222_sigout (INVALID_PIN_NUMBER)
#endif
// @}
/*! \name Sensor Physical Orientation
*
* \internal
* The following constants describe the physical orientation of multi-axis
* sensor devices, relative to the standardized axes of the sensors API.
* This allows for devices to be mounted in different configurations but
* provide consistent output to applications in terms of each axis.
* For each sensor device, the orientation description consists of a set
* of three values in X, Y, Z order, which specify which sensor axis and sign
* corresponds to the standard axis positive direction.
*
* These definitions are provided as a board-level description for the
* sensor drivers and are not used directly in sensor service client
* applications.
* @{
*/
#define NON_DIRECTIONAL_DEV {AXIS_NONE, AXIS_NONE, AXIS_NONE}
#if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)
# define ak8975_orientation {AXIS_X_NEG, AXIS_Y_POS, AXIS_Z_NEG}
# define bma150_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
# define itg3200_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)
# define hmc5883l_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
# define kxtf9_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
# define imu3000_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
#elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
# define ak8975_orientation {AXIS_X_NEG, AXIS_Y_POS, AXIS_Z_NEG}
# define kxtf9_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
# define imu3000_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
#elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
# define bmp085_orientation NON_DIRECTIONAL_DEV
#elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
# define sfh7770_orientation NON_DIRECTIONAL_DEV
#elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
# define bma222_orientation {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
#endif
// @}
/** @} */ // atavrsb_config group
//! \brief Sensor Pin Interrupt Handler Callback Type
typedef void (*SENSOR_IRQ_HANDLER)(volatile void *);
/*! \brief Initialize sensor board target resources
*
* This function is called to ensure proper initialization
* of sensor hardware connected to an Atmel AVR32 or XMEGA platform.
*
* \return Nothing.
*/
extern void sensor_board_init(void);
/*! \brief Install a sensor interrupt handler
*
* The Sensors Xplained add-on boards route sensor device I/O pins to GPIO
* pins for the MCU installed on an Xplained platform board. Some sensor
* devices can be configured to generate interrupts on these pins to indicate
* the availability of new sensor data or the occurrence of configurable
* events related to sensor data thresholds, for example.
*
* This routine will enable interrupts on the GPIO pin specified by the
* \c gpio_pin parameter and call a user-defined callback \c handler when an
* interrupt is detected. The \c arg parameter is used to pass the address
* of user-defined input and output storage for the callback handler. Calling
* the routine with the \c handler parameter set to 0 (the NULL pointer) will
* fail with \c false returned to the caller.
*
* \param gpio_pin Board-specific GPIO pin interface to the MCU.
* \param handler The address of a driver-defined interrupt handler.
* \param arg An optional address passed to the interrupt handler.
*
* \return bool true if the call succeeds, else false.
*/
extern bool sensor_board_irq_connect
(uint32_t gpio_pin, SENSOR_IRQ_HANDLER handler, void *arg);
#ifdef __cplusplus
}
#endif
/**
* \}
*/
#endif /* _sensors_xplained_h_ */

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bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h Normal file
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/**
* \file
*
* \brief Xplained I/O Expansion Header Pin Mapping
*
* The Atmel Xplained evaluation boards have four 10-pin, 100mil headers that
* are used to access spare analog and digital pins on the board
* microcontroller. This file provides a common set of definitions mapping
* the Xplained expansion header \c J1, \c J2, \c J3, and \c J4 pins to spare
* pins on the board microcontroller. Software can then use these common
* definitions to configure I/O for peripherals and expansion boards connected
* to the Xplained header blocks.
*
* For each board type, the pin definitions are specified for the pins in
* each of the four headers. For UC3 based boards, if a pin can be used as
* an external interrupt source, the interrupt and GPIO pin mapping settings
* that are needed for initializing the external interrupt controller (EIC)
* are also provided.
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _xplained_headers_h_
#define _xplained_headers_h_
#include <board.h>
#include <gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
#define INVALID_PIN_NUMBER ((unsigned int) -1)
//! \name Xplained I/O Expansion Header Pin Mapping
// @{
#if (BOARD == UC3_A3_XPLAINED)
# define XPLD_HEADER_J1_PIN1 (AVR32_PIN_PA25)
# define XPLD_HEADER_J1_PIN2 (AVR32_PIN_PA26)
# define XPLD_HEADER_J1_PIN3 (AVR32_PIN_PX57)
# define XPLD_HEADER_J1_PIN4 (AVR32_PIN_PX58)
# define XPLD_HEADER_J1_PIN5 (AVR32_PIN_PB09)
# define XPLD_HEADER_J1_PIN6 (AVR32_PIN_PB10)
# define XPLD_HEADER_J1_PIN7 (AVR32_PIN_PB08)
# define XPLD_HEADER_J1_PIN8 (AVR32_PIN_PB07)
# define XPLD_HEADER_J2_PIN1 (AVR32_PIN_PA21)
# define XPLD_HEADER_J2_PIN2 (AVR32_PIN_PA22)
# define XPLD_HEADER_J2_PIN3 (AVR32_PIN_PA23)
# define XPLD_HEADER_J2_PIN4 (AVR32_PIN_PA24)
# define XPLD_HEADER_J2_PIN5 (AVR32_PIN_PA20)
# define XPLD_HEADER_J2_PIN6 (AVR32_PIN_PA19)
# define XPLD_HEADER_J2_PIN7 (AVR32_PIN_PA18)
# define XPLD_HEADER_J2_PIN8 (AVR32_PIN_PA17)
# define XPLD_HEADER_J3_PIN1 (AVR32_PIN_PA31)
# define XPLD_HEADER_J3_PIN2 (AVR32_PIN_PA30)
# define XPLD_HEADER_J3_PIN3 (AVR32_PIN_PA29)
# define XPLD_HEADER_J3_PIN4 (AVR32_PIN_PA28)
# define XPLD_HEADER_J3_PIN5 (AVR32_PIN_PA27)
# define XPLD_HEADER_J3_PIN6 (AVR32_PIN_PB00)
# define XPLD_HEADER_J3_PIN7 (AVR32_PIN_PB04)
# define XPLD_HEADER_J3_PIN8 (AVR32_PIN_PX19)
# define XPLD_HEADER_J4_PIN1 (AVR32_PIN_PA15)
# define XPLD_HEADER_J4_PIN2 (AVR32_PIN_PA14)
# define XPLD_HEADER_J4_PIN3 (AVR32_PIN_PA05)
# define XPLD_HEADER_J4_PIN4 (AVR32_PIN_PA06)
# define XPLD_HEADER_J4_PIN5 (AVR32_PIN_PA07)
# define XPLD_HEADER_J4_PIN6 (AVR32_PIN_PA10)
# define XPLD_HEADER_J4_PIN7 (AVR32_PIN_PA11)
# define XPLD_HEADER_J4_PIN8 (AVR32_PIN_PA08)
#elif (BOARD == UC3_L0_XPLAINED)
# define XPLD_HEADER_J1_PIN1 (AVR32_PIN_PA21)
# define XPLD_HEADER_J1_PIN2 (AVR32_PIN_PB05)
# define XPLD_HEADER_J1_PIN3 (AVR32_PIN_PB11)
# define XPLD_HEADER_J1_PIN4 (AVR32_PIN_PB10)
# define XPLD_HEADER_J1_PIN5 (AVR32_PIN_PA08)
# define XPLD_HEADER_J1_PIN6 (AVR32_PIN_PB03)
# define XPLD_HEADER_J1_PIN7 (AVR32_PIN_PB02)
# define XPLD_HEADER_J1_PIN8 (AVR32_PIN_PB01)
# define XPLD_HEADER_J2_PIN1 (AVR32_PIN_PA14)
# define XPLD_HEADER_J2_PIN2 (AVR32_PIN_PA15)
# define XPLD_HEADER_J2_PIN3 (AVR32_PIN_PA16)
# define XPLD_HEADER_J2_PIN4 (AVR32_PIN_PA18)
# define XPLD_HEADER_J2_PIN5 (AVR32_PIN_PB07)
# define XPLD_HEADER_J2_PIN6 (AVR32_PIN_PB08)
# define XPLD_HEADER_J2_PIN7 (AVR32_PIN_PB06)
# define XPLD_HEADER_J2_PIN8 (AVR32_PIN_PA19)
# define XPLD_HEADER_J3_PIN1 (AVR32_PIN_PA13)
# define XPLD_HEADER_J3_PIN2 (AVR32_PIN_PA17)
# define XPLD_HEADER_J3_PIN3 (AVR32_PIN_PA20)
# define XPLD_HEADER_J3_PIN4 (AVR32_PIN_PA22)
# define XPLD_HEADER_J3_PIN5 (AVR32_PIN_PB12)
# define XPLD_HEADER_J3_PIN6 (AVR32_PIN_PB09)
# define XPLD_HEADER_J3_PIN7 (AVR32_PIN_PB04)
# define XPLD_HEADER_J3_PIN8 (AVR32_PIN_PA11)
# define XPLD_HEADER_J4_PIN1 (AVR32_PIN_PA21)
# define XPLD_HEADER_J4_PIN2 (AVR32_PIN_PB05)
# define XPLD_HEADER_J4_PIN3 (AVR32_PIN_PB11)
# define XPLD_HEADER_J4_PIN4 (AVR32_PIN_PB10)
# define XPLD_HEADER_J4_PIN5 (AVR32_PIN_PB00)
# define XPLD_HEADER_J4_PIN6 (AVR32_PIN_PB03)
# define XPLD_HEADER_J4_PIN7 (AVR32_PIN_PB02)
# define XPLD_HEADER_J4_PIN8 (AVR32_PIN_PB01)
#elif (BOARD == XMEGA_A1_XPLAINED)
# define XPLD_HEADER_J1_PIN1 IOPORT_CREATE_PIN(PORTF,0)
# define XPLD_HEADER_J1_PIN2 IOPORT_CREATE_PIN(PORTF,1)
# define XPLD_HEADER_J1_PIN3 IOPORT_CREATE_PIN(PORTF,2)
# define XPLD_HEADER_J1_PIN4 IOPORT_CREATE_PIN(PORTF,3)
# define XPLD_HEADER_J1_PIN5 IOPORT_CREATE_PIN(PORTF,4)
# define XPLD_HEADER_J1_PIN6 IOPORT_CREATE_PIN(PORTF,5)
# define XPLD_HEADER_J1_PIN7 IOPORT_CREATE_PIN(PORTF,6)
# define XPLD_HEADER_J1_PIN8 IOPORT_CREATE_PIN(PORTF,7)
# define XPLD_HEADER_J2_PIN1 IOPORT_CREATE_PIN(PORTA,0)
# define XPLD_HEADER_J2_PIN2 IOPORT_CREATE_PIN(PORTA,1)
# define XPLD_HEADER_J2_PIN3 IOPORT_CREATE_PIN(PORTA,2)
# define XPLD_HEADER_J2_PIN4 IOPORT_CREATE_PIN(PORTA,3)
# define XPLD_HEADER_J2_PIN5 IOPORT_CREATE_PIN(PORTA,4)
# define XPLD_HEADER_J2_PIN6 IOPORT_CREATE_PIN(PORTA,5)
# define XPLD_HEADER_J2_PIN7 IOPORT_CREATE_PIN(PORTA,6)
# define XPLD_HEADER_J2_PIN8 IOPORT_CREATE_PIN(PORTA,7)
# define XPLD_HEADER_J3_PIN1 IOPORT_CREATE_PIN(PORTD,0)
# define XPLD_HEADER_J3_PIN2 IOPORT_CREATE_PIN(PORTD,1)
# define XPLD_HEADER_J3_PIN3 IOPORT_CREATE_PIN(PORTD,2)
# define XPLD_HEADER_J3_PIN4 IOPORT_CREATE_PIN(PORTD,3)
# define XPLD_HEADER_J3_PIN5 IOPORT_CREATE_PIN(PORTD,4)
# define XPLD_HEADER_J3_PIN6 IOPORT_CREATE_PIN(PORTD,5)
# define XPLD_HEADER_J3_PIN7 IOPORT_CREATE_PIN(PORTR,0)
# define XPLD_HEADER_J3_PIN8 IOPORT_CREATE_PIN(PORTR,1)
# define XPLD_HEADER_J4_PIN1 IOPORT_CREATE_PIN(PORTC,0)
# define XPLD_HEADER_J4_PIN2 IOPORT_CREATE_PIN(PORTC,1)
# define XPLD_HEADER_J4_PIN3 IOPORT_CREATE_PIN(PORTC,2)
# define XPLD_HEADER_J4_PIN4 IOPORT_CREATE_PIN(PORTC,3)
# define XPLD_HEADER_J4_PIN5 IOPORT_CREATE_PIN(PORTC,4)
# define XPLD_HEADER_J4_PIN6 IOPORT_CREATE_PIN(PORTC,5)
# define XPLD_HEADER_J4_PIN7 IOPORT_CREATE_PIN(PORTC,6)
# define XPLD_HEADER_J4_PIN8 IOPORT_CREATE_PIN(PORTC,7)
#elif (BOARD == XMEGA_B1_XPLAINED)
# define XPLD_HEADER_J1_PIN1 IOPORT_CREATE_PIN(PORTC,0)
# define XPLD_HEADER_J1_PIN2 IOPORT_CREATE_PIN(PORTC,1)
# define XPLD_HEADER_J1_PIN3 IOPORT_CREATE_PIN(PORTC,2)
# define XPLD_HEADER_J1_PIN4 IOPORT_CREATE_PIN(PORTC,3)
# define XPLD_HEADER_J1_PIN5 IOPORT_CREATE_PIN(PORTC,4)
# define XPLD_HEADER_J1_PIN6 IOPORT_CREATE_PIN(PORTC,5)
# define XPLD_HEADER_J1_PIN7 IOPORT_CREATE_PIN(PORTC,6)
# define XPLD_HEADER_J1_PIN8 IOPORT_CREATE_PIN(PORTC,7)
# define XPLD_HEADER_J2_PIN1 IOPORT_CREATE_PIN(PORTA,0)
# define XPLD_HEADER_J2_PIN2 IOPORT_CREATE_PIN(PORTA,1)
# define XPLD_HEADER_J2_PIN3 IOPORT_CREATE_PIN(PORTA,2)
# define XPLD_HEADER_J2_PIN4 IOPORT_CREATE_PIN(PORTA,3)
# define XPLD_HEADER_J2_PIN5 IOPORT_CREATE_PIN(PORTA,4)
# define XPLD_HEADER_J2_PIN6 IOPORT_CREATE_PIN(PORTA,5)
# define XPLD_HEADER_J2_PIN7 IOPORT_CREATE_PIN(PORTA,6)
# define XPLD_HEADER_J2_PIN8 IOPORT_CREATE_PIN(PORTA,7)
# define XPLD_HEADER_J3_PIN1 IOPORT_CREATE_PIN(PORTB,0)
# define XPLD_HEADER_J3_PIN2 IOPORT_CREATE_PIN(PORTB,1)
# define XPLD_HEADER_J3_PIN3 IOPORT_CREATE_PIN(PORTB,2)
# define XPLD_HEADER_J3_PIN4 IOPORT_CREATE_PIN(PORTB,3)
# define XPLD_HEADER_J3_PIN5 IOPORT_CREATE_PIN(PORTB,4)
# define XPLD_HEADER_J3_PIN6 IOPORT_CREATE_PIN(PORTB,5)
# define XPLD_HEADER_J3_PIN7 IOPORT_CREATE_PIN(PORTB,6)
# define XPLD_HEADER_J3_PIN8 IOPORT_CREATE_PIN(PORTB,7)
# define XPLD_HEADER_J4_PIN1 IOPORT_CREATE_PIN(PORTE,0)
# define XPLD_HEADER_J4_PIN2 IOPORT_CREATE_PIN(PORTE,1)
# define XPLD_HEADER_J4_PIN3 IOPORT_CREATE_PIN(PORTE,2)
# define XPLD_HEADER_J4_PIN4 IOPORT_CREATE_PIN(PORTE,3)
# define XPLD_HEADER_J4_PIN5 IOPORT_CREATE_PIN(PORTE,4)
# define XPLD_HEADER_J4_PIN6 IOPORT_CREATE_PIN(PORTE,5)
# define XPLD_HEADER_J4_PIN7 IOPORT_CREATE_PIN(PORTE,6)
# define XPLD_HEADER_J4_PIN8 IOPORT_CREATE_PIN(PORTE,7)
#elif (BOARD == XMEGA_A3BU_XPLAINED)
# define XPLD_HEADER_J1_PIN1 IOPORT_CREATE_PIN(PORTC,0)
# define XPLD_HEADER_J1_PIN2 IOPORT_CREATE_PIN(PORTC,1)
# define XPLD_HEADER_J1_PIN3 IOPORT_CREATE_PIN(PORTC,2)
# define XPLD_HEADER_J1_PIN4 IOPORT_CREATE_PIN(PORTC,3)
# define XPLD_HEADER_J1_PIN5 IOPORT_CREATE_PIN(PORTC,4)
# define XPLD_HEADER_J1_PIN6 IOPORT_CREATE_PIN(PORTC,5)
# define XPLD_HEADER_J1_PIN7 IOPORT_CREATE_PIN(PORTC,6)
# define XPLD_HEADER_J1_PIN8 IOPORT_CREATE_PIN(PORTC,7)
# define XPLD_HEADER_J2_PIN1 IOPORT_CREATE_PIN(PORTB,0)
# define XPLD_HEADER_J2_PIN2 IOPORT_CREATE_PIN(PORTB,1)
# define XPLD_HEADER_J2_PIN3 IOPORT_CREATE_PIN(PORTB,2)
# define XPLD_HEADER_J2_PIN4 IOPORT_CREATE_PIN(PORTB,3)
# define XPLD_HEADER_J2_PIN5 IOPORT_CREATE_PIN(PORTA,4)
# define XPLD_HEADER_J2_PIN6 IOPORT_CREATE_PIN(PORTA,5)
# define XPLD_HEADER_J2_PIN7 IOPORT_CREATE_PIN(PORTA,6)
# define XPLD_HEADER_J2_PIN8 IOPORT_CREATE_PIN(PORTA,7)
# define XPLD_HEADER_J3_PIN1 IOPORT_CREATE_PIN(PORTA,0)
# define XPLD_HEADER_J3_PIN2 IOPORT_CREATE_PIN(PORTA,1)
# define XPLD_HEADER_J3_PIN3 IOPORT_CREATE_PIN(PORTA,2)
# define XPLD_HEADER_J3_PIN4 IOPORT_CREATE_PIN(PORTA,3)
# define XPLD_HEADER_J3_PIN5 IOPORT_CREATE_PIN(PORTB,4)
# define XPLD_HEADER_J3_PIN6 IOPORT_CREATE_PIN(PORTB,5)
# define XPLD_HEADER_J3_PIN7 IOPORT_CREATE_PIN(PORTB,6)
# define XPLD_HEADER_J3_PIN8 IOPORT_CREATE_PIN(PORTB,7)
# define XPLD_HEADER_J4_PIN1 IOPORT_CREATE_PIN(PORTE,0)
# define XPLD_HEADER_J4_PIN2 IOPORT_CREATE_PIN(PORTE,1)
# define XPLD_HEADER_J4_PIN3 IOPORT_CREATE_PIN(PORTE,2)
# define XPLD_HEADER_J4_PIN4 IOPORT_CREATE_PIN(PORTE,3)
# define XPLD_HEADER_J4_PIN5 IOPORT_CREATE_PIN(PORTD,0)
# define XPLD_HEADER_J4_PIN6 IOPORT_CREATE_PIN(PORTD,3)
# define XPLD_HEADER_J4_PIN7 IOPORT_CREATE_PIN(PORTD,2)
# define XPLD_HEADER_J4_PIN8 IOPORT_CREATE_PIN(PORTD,1)
#else
# warning "The BOARD constant does not define a supported Xplained board."
# define XPLD_HEADER_J1_PIN1 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN2 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN3 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN4 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN5 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN6 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN7 INVALID_PIN_NUMBER
# define XPLD_HEADER_J1_PIN8 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN1 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN2 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN3 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN4 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN5 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN6 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN7 INVALID_PIN_NUMBER
# define XPLD_HEADER_J2_PIN8 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN1 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN2 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN3 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN4 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN5 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN6 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN7 INVALID_PIN_NUMBER
# define XPLD_HEADER_J3_PIN8 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN1 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN2 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN3 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN4 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN5 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN6 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN7 INVALID_PIN_NUMBER
# define XPLD_HEADER_J4_PIN8 INVALID_PIN_NUMBER
#endif
// @}
//! \name Xplained Expansion Header External Interrupt Controller Pin Mapping
// @{
#if (BOARD == UC3_A3_XPLAINED)
# define XPLD_HEADER_J2_PIN1_EIC_LINE (AVR32_EIC_INT0)
# define XPLD_HEADER_J2_PIN1_EIC_IRQ (AVR32_EIC_IRQ_0)
# define XPLD_HEADER_J2_PIN1_EIC_PIN (AVR32_EIC_EXTINT_0_PIN)
# define XPLD_HEADER_J2_PIN1_EIC_FUNC (AVR32_EIC_EXTINT_0_FUNCTION)
# define XPLD_HEADER_J2_PIN2_EIC_LINE (AVR32_EIC_INT1)
# define XPLD_HEADER_J2_PIN2_EIC_IRQ (AVR32_EIC_IRQ_1)
# define XPLD_HEADER_J2_PIN2_EIC_PIN (AVR32_EIC_EXTINT_1_PIN)
# define XPLD_HEADER_J2_PIN2_EIC_FUNC (AVR32_EIC_EXTINT_1_FUNCTION)
# define XPLD_HEADER_J2_PIN3_EIC_LINE (AVR32_EIC_INT2)
# define XPLD_HEADER_J2_PIN3_EIC_IRQ (AVR32_EIC_IRQ_2)
# define XPLD_HEADER_J2_PIN3_EIC_PIN (AVR32_EIC_EXTINT_2_PIN)
# define XPLD_HEADER_J2_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_2_FUNCTION)
# define XPLD_HEADER_J2_PIN4_EIC_LINE (AVR32_EIC_INT3)
# define XPLD_HEADER_J2_PIN4_EIC_IRQ (AVR32_EIC_IRQ_3)
# define XPLD_HEADER_J2_PIN4_EIC_PIN (AVR32_EIC_EXTINT_3_PIN)
# define XPLD_HEADER_J2_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_3_FUNCTION)
# define XPLD_HEADER_J2_PIN5_EIC_LINE (8) // NMI
# define XPLD_HEADER_J2_PIN5_EIC_IRQ (0) // NMI - special handler required
# define XPLD_HEADER_J2_PIN5_EIC_PIN (AVR32_EIC_EXTINT_8_PIN)
# define XPLD_HEADER_J2_PIN5_EIC_FUNC (AVR32_EIC_EXTINT_8_FUNCTION)
#elif (BOARD == UC3_L0_XPLAINED)
# define XPLD_HEADER_J1_PIN3_EIC_LINE (AVR32_EIC_INT5)
# define XPLD_HEADER_J1_PIN3_EIC_IRQ (AVR32_EIC_IRQ_5)
# define XPLD_HEADER_J1_PIN3_EIC_PIN (AVR32_EIC_EXTINT_5_1_PIN)
# define XPLD_HEADER_J1_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_5_1_FUNCTION)
# define XPLD_HEADER_J1_PIN4_EIC_LINE (AVR32_EIC_INT4)
# define XPLD_HEADER_J1_PIN4_EIC_IRQ (AVR32_EIC_IRQ_4)
# define XPLD_HEADER_J1_PIN4_EIC_PIN (AVR32_EIC_EXTINT_4_1_PIN)
# define XPLD_HEADER_J1_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_4_1_FUNCTION)
# define XPLD_HEADER_J2_PIN2_EIC_LINE (AVR32_EIC_INT3)
# define XPLD_HEADER_J2_PIN2_EIC_IRQ (AVR32_EIC_IRQ_3)
# define XPLD_HEADER_J2_PIN2_EIC_PIN (AVR32_EIC_EXTINT_3_0_PIN)
# define XPLD_HEADER_J2_PIN2_EIC_FUNC (AVR32_EIC_EXTINT_3_0_FUNCTION)
# define XPLD_HEADER_J2_PIN3_EIC_LINE (AVR32_EIC_INT4)
# define XPLD_HEADER_J2_PIN3_EIC_IRQ (AVR32_EIC_IRQ_4)
# define XPLD_HEADER_J2_PIN3_EIC_PIN (AVR32_EIC_EXTINT_4_0_PIN)
# define XPLD_HEADER_J2_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_4_0_FUNCTION)
# define XPLD_HEADER_J2_PIN4_EIC_LINE (AVR32_EIC_INT5)
# define XPLD_HEADER_J2_PIN4_EIC_IRQ (AVR32_EIC_IRQ_5)
# define XPLD_HEADER_J2_PIN4_EIC_PIN (AVR32_EIC_EXTINT_5_0_PIN)
# define XPLD_HEADER_J2_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_5_0_FUNCTION)
# define XPLD_HEADER_J2_PIN5_EIC_LINE (AVR32_EIC_INT1)
# define XPLD_HEADER_J2_PIN5_EIC_IRQ (AVR32_EIC_IRQ_1)
# define XPLD_HEADER_J2_PIN5_EIC_PIN (AVR32_EIC_EXTINT_1_1_PIN)
# define XPLD_HEADER_J2_PIN5_EIC_FUNC (AVR32_EIC_EXTINT_1_1_FUNCTION)
# define XPLD_HEADER_J2_PIN6_EIC_LINE (AVR32_EIC_INT2)
# define XPLD_HEADER_J2_PIN6_EIC_IRQ (AVR32_EIC_IRQ_2)
# define XPLD_HEADER_J2_PIN6_EIC_PIN (AVR32_EIC_EXTINT_2_1_PIN)
# define XPLD_HEADER_J2_PIN6_EIC_FUNC (AVR32_EIC_EXTINT_2_1_FUNCTION)
# define XPLD_HEADER_J2_PIN7_EIC_LINE (AVR32_EIC_INT0)
# define XPLD_HEADER_J2_PIN7_EIC_IRQ (AVR32_EIC_IRQ_0)
# define XPLD_HEADER_J2_PIN7_EIC_PIN (AVR32_EIC_EXTINT_0_1_PIN)
# define XPLD_HEADER_J2_PIN7_EIC_FUNC (AVR32_EIC_EXTINT_0_1_FUNCTION)
# define XPLD_HEADER_J3_PIN1_EIC_LINE (AVR32_EIC_INT2)
# define XPLD_HEADER_J3_PIN1_EIC_IRQ (AVR32_EIC_IRQ_2)
# define XPLD_HEADER_J3_PIN1_EIC_PIN (AVR32_EIC_EXTINT_2_0_PIN)
# define XPLD_HEADER_J3_PIN1_EIC_FUNC (AVR32_EIC_EXTINT_2_0_FUNCTION)
# define XPLD_HEADER_J3_PIN6_EIC_LINE (AVR32_EIC_INT3)
# define XPLD_HEADER_J3_PIN6_EIC_IRQ (AVR32_EIC_IRQ_3)
# define XPLD_HEADER_J3_PIN6_EIC_PIN (AVR32_EIC_EXTINT_3_1_PIN)
# define XPLD_HEADER_J3_PIN6_EIC_FUNC (AVR32_EIC_EXTINT_3_1_FUNCTION)
# define XPLD_HEADER_J4_PIN3_EIC_LINE (AVR32_EIC_INT5)
# define XPLD_HEADER_J4_PIN3_EIC_IRQ (AVR32_EIC_IRQ_5)
# define XPLD_HEADER_J4_PIN3_EIC_PIN (AVR32_EIC_EXTINT_5_1_PIN)
# define XPLD_HEADER_J4_PIN3_EIC_FUNC (AVR32_EIC_EXTINT_5_1_FUNCTION)
# define XPLD_HEADER_J4_PIN4_EIC_LINE (AVR32_EIC_INT4)
# define XPLD_HEADER_J4_PIN4_EIC_IRQ (AVR32_EIC_IRQ_4)
# define XPLD_HEADER_J4_PIN4_EIC_PIN (AVR32_EIC_EXTINT_4_1_PIN)
# define XPLD_HEADER_J4_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_4_1_FUNCTION)
#elif (BOARD == XMEGA_A1_XPLAINED)
# define XPLD_HEADER_J1_PORT (PORTF)
# define XPLD_HEADER_J1_INT0_vect (PORTF_INT0_vect)
# define XPLD_HEADER_J1_INT1_vect (PORTF_INT1_vect)
# define XPLD_HEADER_J2_PORT (PORTA)
# define XPLD_HEADER_J2_INT0_vect (PORTA_INT0_vect)
# define XPLD_HEADER_J2_INT1_vect (PORTA_INT1_vect)
# define XPLD_HEADER_J3_PORT (PORTD)
# define XPLD_HEADER_J3_INT0_vect (PORTD_INT0_vect)
# define XPLD_HEADER_J3_INT1_vect (PORTD_INT1_vect)
# define XPLD_HEADER_J4_PORT (PORTC)
# define XPLD_HEADER_J4_INT0_vect (PORTC_INT0_vect)
# define XPLD_HEADER_J4_INT1_vect (PORTC_INT1_vect)
#elif (BOARD == XMEGA_B1_XPLAINED)
# define XPLD_HEADER_J1_PORT (PORTC)
# define XPLD_HEADER_J1_INT0_vect (PORTC_INT0_vect)
# define XPLD_HEADER_J1_INT1_vect (PORTC_INT1_vect)
# define XPLD_HEADER_J2_PORT (PORTA)
# define XPLD_HEADER_J2_INT0_vect (PORTA_INT0_vect)
# define XPLD_HEADER_J2_INT1_vect (PORTA_INT1_vect)
# define XPLD_HEADER_J3_PORT (PORTB)
# define XPLD_HEADER_J3_INT0_vect (PORTB_INT0_vect)
# define XPLD_HEADER_J3_INT1_vect (PORTB_INT1_vect)
# define XPLD_HEADER_J4_PORT (PORTE)
# define XPLD_HEADER_J4_INT0_vect (PORTE_INT0_vect)
# define XPLD_HEADER_J4_INT1_vect (PORTE_INT1_vect)
#elif (BOARD == XMEGA_A3BU_XPLAINED)
# define XPLD_HEADER_J1_PORT (PORTC)
# define XPLD_HEADER_J1_INT0_vect (PORTC_INT0_vect)
# define XPLD_HEADER_J1_INT1_vect (PORTC_INT1_vect)
#endif
// @}
#ifdef __cplusplus
}
#endif
#endif /* _xplained_headers_h_ */

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bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h Normal file
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/**
* \file
*
* \brief User board configuration template
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_BOARD_H
#define CONF_BOARD_H
#endif // CONF_BOARD_H

1
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# This file needs to be customized to your MCU and is intentionally left blank

3
bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.mac Normal file
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// This file needs to be customized to your MCU and is intentionally left blank /**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/

1
bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.gdb Normal file
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# This file needs to be customized to your MCU and is intentionally left blank

3
bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.mac Normal file
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// This file needs to be customized to your MCU and is intentionally left blank /**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/

21
bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c Normal file
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/**
* \file
*
* \brief User board initialization template
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <asf.h>
#include <board.h>
#include <conf_board.h>
void board_init(void)
{
/* This function is meant to contain board-specific initialization code
* for, e.g., the I/O pins. The initialization can rely on application-
* specific board configuration, found in conf_board.h.
*/
}

40
bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h Normal file
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/**
* \file
*
* \brief User board definition template
*
*/
/* This file is intended to contain definitions and configuration details for
* features and devices that are available on the board, e.g., frequency and
* startup time for an external crystal, external memory devices, LED and USART
* pins.
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef USER_BOARD_H
#define USER_BOARD_H
#include <conf_board.h>
// External oscillator settings.
// Uncomment and set correct values if external oscillator is used.
// External oscillator frequency
//#define BOARD_XOSC_HZ 8000000
// External oscillator type.
//!< External clock signal
//#define BOARD_XOSC_TYPE XOSC_TYPE_EXTERNAL
//!< 32.768 kHz resonator on TOSC
//#define BOARD_XOSC_TYPE XOSC_TYPE_32KHZ
//!< 0.4 to 16 MHz resonator on XTALS
//#define BOARD_XOSC_TYPE XOSC_TYPE_XTAL
// External oscillator startup time
//#define BOARD_XOSC_STARTUP_US 500000
#endif // USER_BOARD_H

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/**
* \file
*
* \brief ATSHA204 CryptoAuth driver configuration file
*
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_ATSHA204_H_INCLUDED
#define CONF_ATSHA204_H_INCLUDED
#include <board.h>
#if BOARD == XMEGA_A1_XPLAINED
// Interface configuration for XMEGA-A1 Xplained
# define ATSHA204_TWI_PORT (&TWIC)
#else
// Interface configuration for other boards
# warning ATSHA204 TWI port is not set for your board. Please see conf_atsha204.h.
# define ATSHA204_TWI_PORT (&TWIC)
#endif // BOARD
// Xplain board independent configuration
#define ATSHA204_TWI_SPEED (400000)
//! TWI address used at SHA204 library startup
#define SHA204_I2C_DEFAULT_ADDRESS (0xCA)
#endif /* CONF_ATSHA204_H_INCLUDED */

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/*
* \file
*
* \brief ATSHA204 file that implements the communication layer for the device
*
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "sha204_comm.h" //!< definitions and declarations for the Communication module
#include "sha204_timer.h" //!< definitions for timer functions
#include "sha204_lib_return_codes.h" //!< declarations of function return codes
uint8_t sha204c_check_crc(uint8_t *response);
uint8_t sha204c_resync(uint8_t size, uint8_t *response);
/** \brief This function calculates CRC.
*
* \param[in] length number of bytes in buffer
* \param[in] data pointer to data for which CRC should be calculated
* \param[out] crc pointer to 16-bit CRC
*/
void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc) {
uint8_t counter;
uint16_t crc_register = 0;
uint16_t polynom = 0x8005;
uint8_t shift_register;
uint8_t data_bit, crc_bit;
for (counter = 0; counter < length; counter++) {
for (shift_register = 0x01; shift_register > 0x00; shift_register <<= 1) {
data_bit = (data[counter] & shift_register) ? 1 : 0;
crc_bit = crc_register >> 15;
// Shift CRC to the left by 1.
crc_register <<= 1;
if ((data_bit ^ crc_bit) != 0)
crc_register ^= polynom;
}
}
crc[0] = (uint8_t) (crc_register & 0x00FF);
crc[1] = (uint8_t) (crc_register >> 8);
}
/** \brief This function checks the consistency of a response.
* \param[in] response pointer to response
* \return status of the consistency check
*/
uint8_t sha204c_check_crc(uint8_t *response)
{
uint8_t crc[SHA204_CRC_SIZE];
uint8_t count = response[SHA204_BUFFER_POS_COUNT];
count -= SHA204_CRC_SIZE;
sha204c_calculate_crc(count, response, crc);
return (crc[0] == response[count] && crc[1] == response[count + 1])
? SHA204_SUCCESS : SHA204_BAD_CRC;
}
/** \brief This function wakes up a SHA204 device
* and receives a response.
* \param[out] response pointer to four-byte response
* \return status of the operation
*/
uint8_t sha204c_wakeup(uint8_t *response)
{
uint8_t ret_code = sha204p_wakeup();
if (ret_code != SHA204_SUCCESS)
return ret_code;
ret_code = sha204p_receive_response(SHA204_RSP_SIZE_MIN, response);
if (ret_code != SHA204_SUCCESS)
return ret_code;
// Verify status response.
if (response[SHA204_BUFFER_POS_COUNT] != SHA204_RSP_SIZE_MIN)
ret_code = SHA204_INVALID_SIZE;
else if (response[SHA204_BUFFER_POS_STATUS] != SHA204_STATUS_BYTE_WAKEUP)
ret_code = SHA204_COMM_FAIL;
else {
if ((response[SHA204_RSP_SIZE_MIN - SHA204_CRC_SIZE] != 0x33)
|| (response[SHA204_RSP_SIZE_MIN + 1 - SHA204_CRC_SIZE] != 0x43))
ret_code = SHA204_BAD_CRC;
}
if (ret_code != SHA204_SUCCESS)
sha204h_delay_ms(SHA204_COMMAND_EXEC_MAX);
return ret_code;
}
/** \brief This function re-synchronizes communication.
*
Be aware that succeeding only after waking up the
device could mean that it had gone to sleep and lost
its TempKey in the process.\n
Re-synchronizing communication is done in a maximum of
three steps:
<ol>
<li>
Try to re-synchronize without sending a Wake token.
This step is implemented in the Physical layer.
</li>
<li>
If the first step did not succeed send a Wake token.
</li>
<li>
Try to read the Wake response.
</li>
</ol>
*
* \param[in] size size of response buffer
* \param[out] response pointer to Wake-up response buffer
* \return status of the operation
*/
uint8_t sha204c_resync(uint8_t size, uint8_t *response)
{
// Try to re-synchronize without sending a Wake token
// (step 1 of the re-synchronization process).
uint8_t ret_code = sha204p_resync(size, response);
if (ret_code == SHA204_SUCCESS)
return ret_code;
// We lost communication. Send a Wake pulse and try
// to receive a response (steps 2 and 3 of the
// re-synchronization process).
(void) sha204p_sleep();
ret_code = sha204c_wakeup(response);
// Translate a return value of success into one
// that indicates that the device had to be woken up
// and might have lost its TempKey.
return (ret_code == SHA204_SUCCESS ? SHA204_RESYNC_WITH_WAKEUP : ret_code);
}
/** \brief This function runs a communication sequence:
* Append CRC to tx buffer, send command, delay, and verify response after receiving it.
*
* The first byte in tx buffer must be the byte count of the packet.
* If CRC or count of the response is incorrect, or a command byte got "nacked" (TWI),
* this function requests re-sending the response.
* If the response contains an error status, this function resends the command.
*
* \param[in, out] args pointer to parameter structure
* \return status of the operation
*/
uint8_t sha204c_send_and_receive(struct sha204_send_and_receive_parameters *args)
{
uint8_t ret_code = SHA204_FUNC_FAIL;
uint8_t ret_code_resync;
uint8_t n_retries_send;
uint8_t n_retries_receive;
uint8_t i;
uint8_t status_byte;
uint8_t count = args->tx_buffer[SHA204_BUFFER_POS_COUNT];
uint8_t count_minus_crc = count - SHA204_CRC_SIZE;
// Append CRC.
sha204c_calculate_crc(count_minus_crc, args->tx_buffer, args->tx_buffer + count_minus_crc);
// Retry loop for sending a command and receiving a response.
n_retries_send = SHA204_RETRY_COUNT + 1;
while ((n_retries_send-- > 0) && (ret_code != SHA204_SUCCESS)) {
// Send command.
ret_code = sha204p_send_command(count, args->tx_buffer);
if (ret_code != SHA204_SUCCESS) {
if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
// The device seems to be dead in the water.
return ret_code;
else
continue;
}
// Wait typical command execution time and then start polling for a response.
sha204h_delay_ms(args->poll_delay);
// Retry loop for receiving a response.
n_retries_receive = SHA204_RETRY_COUNT + 1;
while (n_retries_receive-- > 0) {
// Reset response buffer.
for (i = 0; i < args->rx_size; i++)
args->rx_buffer[i] = 0;
sha204h_start_timeout_timer_ms(args->poll_timeout);
do {
ret_code = sha204p_receive_response(args->rx_size, args->rx_buffer);
} while (!sha204_timer_expired && (ret_code == SHA204_RX_NO_RESPONSE));
if (ret_code == SHA204_RX_NO_RESPONSE) {
// We did not receive a response. Re-synchronize and send command again.
if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
// The device seems to be dead in the water.
return ret_code;
else
break;
}
// Check whether we received a valid response.
if (ret_code == SHA204_INVALID_SIZE) {
// We see 0xFF for the count when communication got out of sync.
ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
if (ret_code_resync == SHA204_SUCCESS)
// We did not have to wake up the device. Try receiving response again.
continue;
if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
// We could re-synchronize, but only after waking up the device.
// Re-send command.
break;
else
// We failed to re-synchronize.
return ret_code;
}
// We received a response of valid size.
// Check the consistency of the response.
ret_code = sha204c_check_crc(args->rx_buffer);
if (ret_code == SHA204_SUCCESS) {
// Received valid response.
if (args->rx_buffer[SHA204_BUFFER_POS_COUNT] > SHA204_RSP_SIZE_MIN)
// Received non-status response. We are done.
return ret_code;
// Received status response.
status_byte = args->rx_buffer[SHA204_BUFFER_POS_STATUS];
// Translate the three possible device status error codes
// into library return codes.
if (status_byte == SHA204_STATUS_BYTE_PARSE)
return SHA204_PARSE_ERROR;
if (status_byte == SHA204_STATUS_BYTE_EXEC)
return SHA204_CMD_FAIL;
if (status_byte == SHA204_STATUS_BYTE_COMM) {
// In case of the device status byte indicating a communication
// error this function exits the retry loop for receiving a response
// and enters the overall retry loop
// (send command / receive response).
ret_code = SHA204_STATUS_CRC;
break;
}
// Received status response from CheckMAC, DeriveKey, GenDig,
// Lock, Nonce, Pause, UpdateExtra, or Write command.
return ret_code;
}
else {
// Received response with incorrect CRC.
ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
if (ret_code_resync == SHA204_SUCCESS)
// We did not have to wake up the device. Try receiving response again.
continue;
if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
// We could re-synchronize, but only after waking up the device.
// Re-send command.
break;
else
// We failed to re-synchronize.
return ret_code;
} // block end of check response consistency
} // block end of receive retry loop
} // block end of send and receive retry loop
return ret_code;
}

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/*
* \file
*
* \brief ATSHA204 header file for the communication layer for the device
*
*
* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef SHA204_COMM_H
# define SHA204_COMM_H
#include <compiler.h> //!< compiler dependent definitions
#include "sha204_physical.h" //!< declarations that are common to all interface implementations
//! maximum command delay
#define SHA204_COMMAND_EXEC_MAX (69)
//! minimum number of bytes in command (from count byte to second CRC byte)
#define SHA204_CMD_SIZE_MIN ((uint8_t) 7)
//! maximum size of command packet (CheckMac)
#define SHA204_CMD_SIZE_MAX ((uint8_t) 84)
//! number of CRC bytes
#define SHA204_CRC_SIZE ((uint8_t) 2)
//! buffer index of status byte in status response
#define SHA204_BUFFER_POS_STATUS (1)
//! buffer index of first data byte in data response
#define SHA204_BUFFER_POS_DATA (1)
//! status byte after wake-up
#define SHA204_STATUS_BYTE_WAKEUP ((uint8_t) 0x11)
//! command parse error
#define SHA204_STATUS_BYTE_PARSE ((uint8_t) 0x03)
//! command execution error
#define SHA204_STATUS_BYTE_EXEC ((uint8_t) 0x0F)
//! communication error
#define SHA204_STATUS_BYTE_COMM ((uint8_t) 0xFF)
/**
* \brief This structure contains the parameters for the \ref sha204c_send_and_receive function.
*/
struct sha204_send_and_receive_parameters {
uint8_t *tx_buffer; //!< pointer to send buffer
uint8_t rx_size; //!< size of receive buffer
uint8_t *rx_buffer; //!< pointer to receive buffer
uint8_t poll_delay; //!< how long to wait before polling for response-ready
uint8_t poll_timeout; //!< how long to poll before timing out
};
/**
* \defgroup sha204_communication_group SHA204 Service - hardware independent communication functions
* @{
*/
void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc);
uint8_t sha204c_wakeup(uint8_t *response);
uint8_t sha204c_send_and_receive(struct sha204_send_and_receive_parameters *args);
//! @}
#endif

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