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[bsp][yichip] add yc3122-pos (#7526)

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Co-authored-by: supperthomas <78900636@qq.com>
This commit is contained in:
zhiqiandeng
2023-05-23 16:07:16 +08:00
committed by GitHub
parent 662aa1b7e2
commit 17ce4a462b
82 changed files with 64931 additions and 0 deletions
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1
.github/workflows/action.yml vendored
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@@ -63,6 +63,7 @@ jobs:
- "at32/at32f425-start"
- "at32/at32f435-start"
- "at32/at32f437-start"
- "yichip/yc3122-pos"
- "hc32/ev_hc32f4a0_lqfp176"
- "hc32/ev_hc32f460_lqfp100_v2"
- "hc32l196"

998
bsp/yichip/yc3122-pos/.config Normal file
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bsp/yichip/yc3122-pos/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_YC3122
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "drivers/Kconfig"

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bsp/yichip/yc3122-pos/Libraries/.ignore_format.yml Normal file
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# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- CMSIS
- core
- sdk
- startup

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bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/YC3122.svd Normal file
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bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/system_yc3122.h Normal file
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/**************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
* Device <Device>
* @version V3.10
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_YC3122_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_YC3122_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "yc3122.h"
#include "type.h"
#include "rom_api.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

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bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/yc3122.h Normal file
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284
bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/arm/startup_yc3122.s Normal file
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;/*
; * Copyright (c) 2006-2020, YICHIP Development Team
; * @file yc_startup.s
; * @brief source file for setting startup
; *
; * Change Logs:
; * Date Author Version Notes
; * 2020-11-06 wushengyan V1.0.0 the first version
; * 2021-03-11 wushengyan V1.0.2 Change for New ROM
; */
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=4
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=4
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset Rom code change to 0x1000200
AREA RESET, CODE, READONLY ,ALIGN=4
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp
DCD Reset_Handler ;//reset 1
DCD 0x00000000 ;//NMI 2
DCD hard_fault_handler ;//HARD 3
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD svc_handler ;//SVC 11
DCD 0 ;
DCD 0 ;
DCD pendsv_handler ;//PENDSV 14
DCD systick_handler ;//SYSTICK 15
DCD USB_IRQHandler ;//IQR0
DCD I2C0_IRQHandler ;//IQR1
DCD I2C1_IRQHandler ;//IQR2
DCD QSPI_IRQHandler ;//IQR3
DCD SPI0_IRQHandler ;//IQR4
DCD SPI1_IRQHandler ;
DCD HSPI_IRQHandler ;
DCD SEC_IRQHandler ;
DCD UART0_IRQHandler ;
DCD UART1_IRQHandler ;
DCD UART2_IRQHandler ;
DCD UART3_IRQHandler ;
DCD MEMCP_IRQHandler ;
DCD SCI0_IRQHandler ;
DCD SCI1_IRQHandler ;
DCD MSR_IRQHandler ;
DCD GPIO_IRQHandler ;
DCD TMRG0_IRQHandler ;
DCD TMRG1_IRQHandler ;
DCD SDIO_IRQHandler ;
DCD PSARM_IRQHandler ;
DCD RSA_IRQHandler ;
DCD SM4_IRQHandler ;
DCD TRNG_IRQHandler ;
DCD WDT_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD ADC_IRQHandler ;
DCD RTC_IRQHandler ;
DCD BIN_IRQHandler ;
DCD POWER_IRQHandler ;
DCD SOFTWARE_IRQHandler ;
DCD RISCV_IRQHandler ;
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
isr PROC
LDR R1,=0x1000200
LDR R0,[R0,R1]
BX R0
NOP
NOP
NOP
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
hard_fault_handler PROC
EXPORT hard_fault_handler
IMPORT HardFault_Handler
ldr r0,=HardFault_Handler
bx r0
nop
ENDP
svc_handler PROC
EXPORT svc_handler
ldr r0,=SVC_IRQHandler
bx r0
nop
ENDP
pendsv_handler PROC
EXPORT pendsv_handler
IMPORT PendSV_Handler
ldr r0,=PendSV_Handler
bx r0
nop
ENDP
systick_handler PROC
EXPORT systick_handler
IMPORT SysTick_Handler
ldr r0,=SysTick_Handler
bx r0
nop
ENDP
ALIGN
Default_Handler PROC
; ToDo: Add here the export definition for the device specific external interrupts handler
EXPORT HARD_FAULT_IRQHandler [WEAK]
EXPORT SVC_IRQHandler [WEAK]
EXPORT PENDSV_IRQHandler [WEAK]
EXPORT SYSTICK_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT TIMER5_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT TIMER7_IRQHandler [WEAK]
EXPORT TIMER8_IRQHandler [WEAK]
EXPORT CHGRIN_IRQHandler [WEAK]
EXPORT VBAT_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT HSPI_IRQHandler [WEAK]
EXPORT SEC_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT MEMCP_IRQHandler [WEAK]
EXPORT SCI0_IRQHandler [WEAK]
EXPORT SCI1_IRQHandler [WEAK]
EXPORT MSR_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT TMRG0_IRQHandler [WEAK]
EXPORT TMRG1_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT PSARM_IRQHandler [WEAK]
EXPORT RSA_IRQHandler [WEAK]
EXPORT SM4_IRQHandler [WEAK]
EXPORT TRNG_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT BIN_IRQHandler [WEAK]
EXPORT POWER_IRQHandler [WEAK]
EXPORT SOFTWARE_IRQHandler [WEAK]
EXPORT RISCV_IRQHandler [WEAK]
; ToDo: Add here the names for the device specific external interrupts handler
HARD_FAULT_IRQHandler
SVC_IRQHandler
PENDSV_IRQHandler
SYSTICK_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
EXTI5_IRQHandler
EXTI6_IRQHandler
EXTI7_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
TIMER5_IRQHandler
TIMER6_IRQHandler
TIMER7_IRQHandler
TIMER8_IRQHandler
CHGRIN_IRQHandler
VBAT_IRQHandler
USB_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
QSPI_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
HSPI_IRQHandler
SEC_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
MEMCP_IRQHandler
SCI0_IRQHandler
SCI1_IRQHandler
MSR_IRQHandler
GPIO_IRQHandler
TMRG0_IRQHandler
TMRG1_IRQHandler
SDIO_IRQHandler
PSARM_IRQHandler
RSA_IRQHandler
SM4_IRQHandler
TRNG_IRQHandler
WDT_IRQHandler
DCMI_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
BIN_IRQHandler
POWER_IRQHandler
SOFTWARE_IRQHandler
RISCV_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = __initial_sp
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

214
bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/gcc/startup_yc3122.S Normal file
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;/*
; * Copyright (c) 2006-2020, YICHIP Development Team
; * @file yc_flash_start_gcc.s
; * @brief source file for setting flash_start_gcc
; *
; * Change Logs:
; * Date Author Version Notes
; * 2020-11-06 wushengyan V1.0.0 the first version
; */
.org 0x200
.global Reset_Handler,HARD_FAULT_IRQHandler,SVC_IRQHandler,PENDSV_IRQHandler,SYSTICK_IRQHandler
vectors:
.long 0x00030000
.long Reset_Handler ;//reset 1
.long 0x00000000 ;//NMI 2
.long hard_fault_handler ;//HARD 3
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long svc_handler ;//SVC 11
.long 0 ;
.long 0 ;
.long pendsv_handler ;//PENDSV 14
.long systick_handler ;//SYSTICK 15
.long USB_IRQHandler ;//IQR0
.long I2C0_IRQHandler ;//IQR1
.long I2C1_IRQHandler ;//IQR2
.long QSPI_IRQHandler ;//IQR3
.long SPI0_IRQHandler ;//IQR4
.long SPI1_IRQHandler ;
.long HSPI_IRQHandler ;
.long SEC_IRQHandler ;
.long UART0_IRQHandler ;
.long UART1_IRQHandler ;
.long UART2_IRQHandler ;
.long UART3_IRQHandler ;
.long MEMCP_IRQHandler ;
.long SCI0_IRQHandler ;
.long SCI1_IRQHandler ;
.long MSR_IRQHandler ;
.long GPIO_IRQHandler ;
.long TMRG0_IRQHandler ;
.long TMRG1_IRQHandler ;
.long SDIO_IRQHandler ;
.long PSARM_IRQHandler ;
.long RSA_IRQHandler ;
.long SM4_IRQHandler ;
.long TRNG_IRQHandler ;
.long WDT_IRQHandler ;
.long DCMI_IRQHandler ;
.long ADC_IRQHandler ;
.long RTC_IRQHandler ;
.long BIN_IRQHandler ;
.long POWER_IRQHandler ;
.long SOFTWARE_IRQHandler ;
.long RISCV_IRQHandler ;
.thumb_func
isr:
LDR R1,=0x1000200
LDR R0,[R0,R1]
BX R0
NOP
NOP
NOP
.thumb_func
Reset_Handler:
LDR R0,=SystemInit
BLX R0
LDR R0,=hardware_init
BX R0
hard_fault_handler:
ldr r0,=HardFault_Handler
bx r0
svc_handler:
ldr r0,=SVC_IRQHandler
bx r0
pendsv_handler:
ldr r0,=PendSV_Handler
bx r0
systick_handler:
ldr r0,=SysTick_Handler
bx r0
.thumb
.thumb_func
hardware_init:
ldr r1, =__exidx_start
ldr r2, =__data_start__
ldr r3, =__data_end__
sub r3, r2
ble .L_loop1_done
.L_loop1:
sub r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
;/* Single BSS section scheme.
; *
; * The BSS section is specified by following symbols
; * _sbss: start of the BSS section.
; * _ebss: end of the BSS section.
; *
; * Both addresses must be aligned to 4 bytes boundary.
; */
ldr r1, =__bss_start__
ldr r2, =__bss_end__
mov r0, #0
sub r2, r1
ble .L_loop3_done
.L_loop3:
sub r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
ldr r0,=0x12345
ldr r3,=0x1111
bl main
.globl delay
.syntax unified
delay:
subs r0,#1
bne delay
nop
bx lr
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler HARD_FAULT_IRQHandler
def_irq_handler SVC_IRQHandler
def_irq_handler PENDSV_IRQHandler
def_irq_handler SYSTICK_IRQHandler
def_irq_handler EXTI0_IRQHandler
def_irq_handler EXTI1_IRQHandler
def_irq_handler EXTI2_IRQHandler
def_irq_handler EXTI3_IRQHandler
def_irq_handler EXTI4_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler TIMER4_IRQHandler
def_irq_handler TIMER5_IRQHandler
def_irq_handler TIMER6_IRQHandler
def_irq_handler TIMER7_IRQHandler
def_irq_handler TIMER8_IRQHandler
def_irq_handler CHGRIN_IRQHandler
def_irq_handler VBAT_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler QSPI_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler HSPI_IRQHandler
def_irq_handler SEC_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler MEMCP_IRQHandler
def_irq_handler SCI0_IRQHandler
def_irq_handler SCI1_IRQHandler
def_irq_handler MSR_IRQHandler
def_irq_handler GPIO_IRQHandler
def_irq_handler TMRG0_IRQHandler
def_irq_handler TMRG1_IRQHandler
def_irq_handler SDIO_IRQHandler
def_irq_handler PSARM_IRQHandler
def_irq_handler RSA_IRQHandler
def_irq_handler SM4_IRQHandler
def_irq_handler TRNG_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler DCMI_IRQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BIN_IRQHandler
def_irq_handler POWER_IRQHandler
def_irq_handler SOFTWARE_IRQHandler
def_irq_handler RISCV_IRQHandler

225
bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/iar/startup_yc3122.s Normal file
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;/*
; * Copyright (c) 2006-2020, YICHIP Development Team
; * @file startup_yc3122.s
; * @brief source file for setting startup
; *
; * Change Logs:
; * Date Author Version Notes
; * 2022-11-08 kiven V1.0.0 the first version
; */
MODULE ?cstartup ; // 定义模块名称
;Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start ; // IAR 入口函数
EXTERN SystemInit ; // 系统初始化函数
PUBLIC _vector_table ; // 中断向量表地址
ALIGNROM 2
DATA ; // 定义数据段
_vector_table ;中断向量表
DCD sfe(CSTACK)
DCD Reset_Handler ;//reset 1
DCD 0x00000000 ;//NMI 2
DCD hard_fault_handler ;//HARD 3
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD svc_handler ;//SVC 11
DCD 0 ;
DCD 0 ;
DCD pendsv_handler ;//PENDSV 14
DCD systick_handler ;//SYSTICK 15
DCD USB_IRQHandler ;//IQR0
DCD I2C0_IRQHandler ;//IQR1
DCD I2C1_IRQHandler ;//IQR2
DCD QSPI_IRQHandler ;//IQR3
DCD SPI0_IRQHandler ;//IQR4
DCD SPI1_IRQHandler ;
DCD HSPI_IRQHandler ;
DCD SEC_IRQHandler ;
DCD UART0_IRQHandler ;
DCD UART1_IRQHandler ;
DCD UART2_IRQHandler ;
DCD UART3_IRQHandler ;
DCD MEMCP_IRQHandler ;
DCD SCI0_IRQHandler ;
DCD SCI1_IRQHandler ;
DCD MSR_IRQHandler ;
DCD GPIO_IRQHandler ;
DCD TMRG0_IRQHandler ;
DCD TMRG1_IRQHandler ;
DCD SDIO_IRQHandler ;
DCD PSARM_IRQHandler ;
DCD RSA_IRQHandler ;
DCD SM4_IRQHandler ;
DCD TRNG_IRQHandler ;
DCD WDT_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD ADC_IRQHandler ;
DCD RTC_IRQHandler ;
DCD BIN_IRQHandler ;
DCD POWER_IRQHandler ;
DCD SOFTWARE_IRQHandler ;
DCD RISCV_IRQHandler ;
THUMB ;//进入THUMB模式（THUMB-2指令集）
SECTION .intvec:CODE:REORDER(2)
CODE
PUBLIC isr
isr
LDR R1,=_vector_table
LDR R0,[R0,R1]
BX R0
NOP
NOP
NOP
PUBLIC Reset_Handler
Reset_Handler
LDR R0, =sfe(CSTACK)
mov sp, R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
hard_fault_handler PROC
EXPORT hard_fault_handler
IMPORT HardFault_Handler
LDR r0,=HardFault_Handler
BX r0
nop
ENDP
svc_handler PROC
EXPORT svc_handler
ldr r0,=SVC_IRQHandler
BX r0
nop
ENDP
pendsv_handler PROC
EXPORT pendsv_handler
IMPORT PendSV_Handler
LDR r0,=PendSV_Handler
BX r0
nop
ENDP
systick_handler PROC
EXPORT systick_handler
IMPORT SysTick_Handler
LDR r0,=SysTick_Handler
BX r0
nop
ENDP
; // 定义默认的中断函数，这里只是弱定义，可以被用户自己定义的中断向量函数覆盖
PUBWEAK HARD_FAULT_IRQHandler
PUBWEAK SVC_IRQHandler
PUBWEAK PENDSV_IRQHandler
PUBWEAK SYSTICK_IRQHandler
PUBWEAK EXTI_IRQHandler
PUBWEAK TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
PUBWEAK TIMER4_IRQHandler
PUBWEAK TIMER5_IRQHandler
PUBWEAK TIMER6_IRQHandler
PUBWEAK TIMER7_IRQHandler
PUBWEAK TIMER8_IRQHandler
PUBWEAK CHGRIN_IRQHandler
PUBWEAK VBAT_IRQHandler
PUBWEAK USB_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK QSPI_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK HSPI_IRQHandler
PUBWEAK SEC_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK MEMCP_IRQHandler
PUBWEAK SCI0_IRQHandler
PUBWEAK SCI1_IRQHandler
PUBWEAK MSR_IRQHandler
PUBWEAK GPIO_IRQHandler
PUBWEAK TMRG0_IRQHandler
PUBWEAK TMRG1_IRQHandler
PUBWEAK SDIO_IRQHandler
PUBWEAK PSARM_IRQHandler
PUBWEAK RSA_IRQHandler
PUBWEAK SM4_IRQHandler
PUBWEAK TRNG_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK DCMI_IRQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK BIN_IRQHandler
PUBWEAK POWER_IRQHandler
PUBWEAK SOFTWARE_IRQHandler
PUBWEAK RISCV_IRQHandler
; ToDo: Add here the names for the device specific external interrupts handler
HARD_FAULT_IRQHandler
SVC_IRQHandler
PENDSV_IRQHandler
SYSTICK_IRQHandler
EXTI_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
TIMER5_IRQHandler
TIMER6_IRQHandler
TIMER7_IRQHandler
TIMER8_IRQHandler
CHGRIN_IRQHandler
VBAT_IRQHandler
USB_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
QSPI_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
HSPI_IRQHandler
SEC_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
MEMCP_IRQHandler
SCI0_IRQHandler
SCI1_IRQHandler
MSR_IRQHandler
GPIO_IRQHandler
TMRG0_IRQHandler
TMRG1_IRQHandler
SDIO_IRQHandler
PSARM_IRQHandler
RSA_IRQHandler
SM4_IRQHandler
TRNG_IRQHandler
WDT_IRQHandler
DCMI_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
BIN_IRQHandler
POWER_IRQHandler
SOFTWARE_IRQHandler
RISCV_IRQHandler
B .
END

99
bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Source/Templates/system_yc3122.c Normal file
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/**************************************************************************//**
* @file system_<Device>.c
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for
* Device <Device>
* @version V3.10
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include <stdint.h>
#include "system_yc3122.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define __HSI (192000000UL)
#define __SYSTEM_CLOCK (__HSI / 4)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* Write access code "0x55->0xaa->0x17" to set or clear "access_en" */
MLPM->ACCESS_CODE.reg = 0x55;
MLPM->ACCESS_CODE.reg = 0xaa;
MLPM->ACCESS_CODE.reg = 0x17;
if (MLPM->ACCESS_EN.reg != ENABLE)
{
MLPM->ACCESS_EN.reg = ENABLE;
}
MLPM->BAKEUP_REG1.reg = 0xaaaaaaaa;
}

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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bsp/yichip/yc3122-pos/Libraries/SConscript Normal file
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from building import *
import rtconfig
import os
cwd = GetCurrentDir()
path_sdk = os.path.join(cwd,'sdk')
path_core = os.path.join(cwd,'core')
path_cmin = os.path.join(cwd,'CMSIS','Include')
path_cmde = os.path.join(cwd,'CMSIS','Device','YICHIP','YC3122')
src = Glob('sdk/*.c')
CPPPATH = [path_sdk,path_core,path_cmin,os.path.join(path_cmde,'Include'),cwd]
src += Glob(path_cmde + '/Source/Templates/*.c')
src += ['core/system.c']
if rtconfig.PLATFORM in ['gcc']:
src += ['sdk/libyc_qspi.a']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += ['sdk/yc_qspi.lib']
if rtconfig.PLATFORM in ['gcc']:
src += [path_cmde + '/Source/Templates/gcc/startup_yc3122.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [path_cmde + '/Source/Templates/arm/startup_yc3122.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [path_cmde + '/Source/Templates/iar/startup_yc3122.s']
group = DefineGroup('Libraries', src, depend = [''],CPPPATH = CPPPATH, CPPDEFINES = ['__USE_YC_M0__'])
Return('group')

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bsp/yichip/yc3122-pos/Libraries/core/board_config.h Normal file
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bsp/yichip/yc3122-pos/Libraries/core/core_rv_31xx.h Normal file
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/*
* Copyright (c) 2006-2021, YICHIP Development Team
* @file yc_rom_api.h
* @brief source file for setting rom_api
*
* Change Logs:
* Date Author Version Notes
* 2021-06-23 wushengyan V1.0.0 the first version
*/
#ifndef __RV_31XX_H__
#define __RV_31XX_H__
#ifdef __USE_YC_RISC_V__
#include "type.h"
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*end IO definitions*/
#define __STATIC_INLINE static __inline
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC PLIC
- Core SysTick Register
******************************************************************************/
/******************** RISC-V REG START **************************************/
typedef struct
{
__IO uint32_t RV_PAUSE_EN : 1;
__IO uint32_t RV_PAUSE_START : 1;
__IO uint32_t RV_DCLK_EN : 1;
__IO uint32_t RV_QSORTCLK_EN : 1;
__IO uint32_t RV_BINCLK_EN : 1;
__IO uint32_t DBG_STEP_EN : 1;
__IO uint32_t FPU_STEP_DIS : 1;
__IO uint32_t LONGP_STEP_EN : 1;
__IO uint32_t RV_CORECLK_EN : 8;
__I uint32_t RV_CTRL_RSVD : 16;
__IO uint32_t RV_WKUP_SRC_EN : 32;
__IO uint32_t RV_PC_RTVEC : 32;
__IO uint32_t RV_STACK_ADDR : 32;
} RVCtrl_TypeDef;
typedef struct
{
__IO uint32_t ICE_CTRL : 16;
__IO uint32_t ICE_CMD : 4;
__I uint32_t ICE_CTRL_RSVD : 12;
__IO uint32_t ICE_BREAK0 : 25;
__I uint32_t ICE_BREAK0_RSVD : 7;
__IO uint32_t ICE_BREAK1 : 25;
__I uint32_t ICE_BREAK1_RSVD : 7;
__IO uint32_t ICE_REG_WDATA : 32;
__I uint32_t ICE_REG_RDATA : 32;
__IO uint32_t TRACE_ADDR : 25;
__I uint32_t TRACE_ADDR_RSVD : 7;
__I uint32_t TRACE_FIFO_RDATA : 25;
__I uint32_t TRACE_FIFO_RDATA_RSVD : 7;
__I uint32_t EXE_ADDR : 32;
__I uint32_t ICE_STATUS : 8;
__I uint32_t ICE_STATUS_RSVD : 24; //RV_CTRL
} RVIce_TypeDef;
typedef struct
{
__IO uint32_t BIN_CTRL_BLOCK_ENABLE : 1;
__IO uint32_t BIN_CTRL_GRID_MODE : 1;
__IO uint32_t BIN_CTRL_CUT_ENABLE : 1;
__IO uint32_t BIN_CTRL_SCALER_ENABLE : 1;
__IO uint32_t BIN_CTRL_INV_BIT_ENABLE : 1;
__I uint32_t BIN_CTRL_RSVD : 3;
__IO uint32_t RANGE : 8;
__IO uint32_t SUB_HEIGHT : 8;
__IO uint32_t SUB_WIDTH : 8;
__IO uint32_t RAW_BIN_BASEADDR : 24;
__I uint32_t RAW_BIN_BASEADDR_RSVD : 8;
__IO uint32_t RGB_BASEADDR : 24;
__I uint32_t RGB_BASEADDR_RSVD : 8;
__IO uint32_t AVG_BASEADDR : 24;
__I uint32_t AVG_BASEADDR_RSVD : 8;
__IO uint32_t SCA_BIN_BASEADDR : 24;
__I uint32_t SCA_BIN_BASEADDR_RSVD : 8;
__I uint32_t BIN_STATUS : 32;
__I uint32_t RAW_DOUT_ADDR_LOCK : 24;
__I uint32_t RAW_DOUT_ADDR_LOCK_RSVD : 8;
__I uint32_t SCA_DOUT_ADDR_LOCK : 24;
__I uint32_t SCA_DOUT_ADDR_LOCK_RSVD : 8;
__IO uint32_t QSORT_CTRL : 32;
__IO uint32_t QSORT_BASEADDR : 24;
__I uint32_t QSORT_BASEADDR_RSVD : 8;
__I uint32_t QSORT_DONE : 1;
__I uint32_t QSORT_DONE_RSVD : 31;
__IO uint32_t ONE_RGB_BASEADDR : 24;
__I uint32_t ONE_RGB_BASEADDR_RSVD : 8;
__IO uint32_t FAST_BIN_BASEADDR : 24;
__I uint32_t FAST_BIN_BASEADDR_RSVD : 8;
__IO uint32_t CANNY_BIN_BASEADDR : 24;
__I uint32_t CANNY_BIN_BASEADDR_RSVD : 8;
__IO uint32_t ONE_BIN_CTRL : 13;
__I uint32_t ONE_BIN_CTRL_RSVD : 19;
__IO uint32_t FAST_BIN_CTRL : 24;
__I uint32_t FAST_BIN_CTRL_RSVD : 8;
__IO uint32_t CANNY_BIN_CTRL : 23;
__I uint32_t CANNY_BIN_CTRL_RSVD : 9;
__IO uint32_t CANNY_BIN_CTRL1 : 12;
__I uint32_t CANNY_BIN_CTRL1_RSVD : 20;
__IO uint32_t ONE_BIN_STATUS : 21;
__I uint32_t ONE_BIN_STATUS_RSVD : 11;
__IO uint32_t FAST_BIN_BASEADDR_USED : 24;
__I uint32_t FAST_BIN_BASEADDR_USED_RSVD : 8;
__IO uint32_t CANNY_BIN_BASEADDR_USED : 24;
__I uint32_t CANNY_BIN_BASEADDR_USED_RSVD : 8;
} RVBin_TypeDef;
typedef struct
{
__IO uint32_t JTAG_SW_SEL :1;
__I uint32_t JTAG_SW_SEL_RSVD :3;
__IO uint32_t DAP_REG_BASE_ADDR :4;
__I uint32_t DAP_CTRL_RSVD :24;
__IO uint32_t RV_TM_EN :1;
__IO uint32_t RV_TM_EN_RSVD :31;
__IO uint32_t RV_TM_CNT :32;
__IO uint32_t M0_TO_RV_IE :1;
__I uint32_t M0_TO_RV_IE_RSVD :7;
__IO uint32_t M0_TO_RV_IRQ :1;
__I uint32_t M0_TO_RV_IRQ_RSVD :7;
__IO uint32_t RV_TO_M0_IRQ_TRIG :1;
__I uint32_t RV_TO_M0_IRQ_TRIG_RSVD :15;
__IO uint32_t IRQ_SW_EN :1;
__IO uint32_t IRQ_SW_PEND :1;
__I uint32_t IRQ_SW_RSVD :6;
__IO uint32_t IRQ_SW_CODE :8;
__I uint32_t RV_SW_IRQ_RSVD :16;
}RVIrq_TypeDef;
#define MPU_REGION_NUM 4
typedef struct
{
__IO uint8_t Protect_region[MPU_REGION_NUM];
} RVMPUREGION_TypeDef;
typedef struct
{
__IO uint32_t BaseAndLimit[MPU_REGION_NUM];
} RVMPUBASE_TypeDef;
#define BASE_LIMIT_REGION_NUM 4
typedef struct
{
__IO uint32_t MPU_ENABLE_CODE : 4;
__IO RVMPUREGION_TypeDef ICB_PROTECT;
__IO RVMPUREGION_TypeDef DTCM_PROTECT;
__IO RVMPUREGION_TypeDef ITCM_PROTECT;
__IO uint32_t USER_START : 24;
__IO uint32_t MPU_STS_CLR;
__I uint32_t FAULT_STATUS;
__I uint32_t FAULT_ADDR_ICB;
__I uint32_t FAULT_ADDR_DTCM;
__I uint32_t FAULT_ADDR_ITCM;
__IO RVMPUBASE_TypeDef ICB_BASE;
__IO RVMPUBASE_TypeDef DTCM_BASE;
__IO RVMPUBASE_TypeDef ITCM_BASE;
__IO RVMPUBASE_TypeDef ICB_LIMIT;
__IO RVMPUBASE_TypeDef DTCM_LIMIT;
__IO RVMPUBASE_TypeDef ITCM_LIMIT;
} RVMPU_TypeDef;
typedef struct
{
__IO uint32_t WDT_EN : 1;
__IO uint32_t WDT_EN_LOCK : 1;
__IO uint32_t WDT_ACT : 1;
__I uint32_t WDT_CTRL_RSVD1 : 5;
__IO uint32_t WDT_DIV : 4;
__I uint32_t WDT_CTRL_RSVD2 : 20;
__IO uint32_t WDT_KEY : 16;
__I uint32_t WDT_KEY_RSVD : 16;
__IO uint32_t WDT_RELOAD_VALUE : 32;
__I uint32_t WDT_CNT : 32;
__IO uint32_t WDT_IRQ_EN : 1;
__I uint32_t WDT_IRQ_EN_RSVD : 31;
__IO uint32_t WDT_IRQ : 1;
__I uint32_t WDT_IRQ_RSVD : 31;
} RVWdt_TypeDef;
#define YC3122_RV_BASE (0x000E0000UL) /* RV Base Address */
#define RV_CTRL_BASEADDR (YC3122_RV_BASE + 0x00000) //0xe0000
#define RV_ICE_BASEADDR (YC3122_RV_BASE + 0x00004) //0xe0004
#define RV_BIN_BASEADDR (YC3122_RV_BASE + 0x00034) //0xe0034
#define RV_IRQ_BASEADDR (YC3122_RV_BASE + 0x000D0) //0xe00d0
#define RV_SYSTICK_BASEADDR (YC3122_RV_BASE + 0x000D0) //0xe00d4
#define RV_MPU_BASEADDR (YC3122_RV_BASE + 0x00100) //0xe0100
#define RV_IRQ_PRIO_BASEADDR (YC3122_RV_BASE + 0x01000) //0xe1000
#define RV_IRQ_PEND_BASEADDR (YC3122_RV_BASE + 0x02000) //0xe2000
#define RV_IRQ_ENAB_BASEADDR (YC3122_RV_BASE + 0x03000) //0xe3000
#define RV_IRQ_THRD_BASEADDR (YC3122_RV_BASE + 0x04000) //0xe4000
#define RV_IRQ_CLAM_BASEADDR (YC3122_RV_BASE + 0x04004) //0xe4004
#define RV_WDT_BASEADDR (0xfb700) //0xfb700
#define RV_CTRL1 ((RVCtrl_TypeDef *)RV_CTRL_BASEADDR)
#define RV_ICE ((RVIce_TypeDef *)RV_ICE_BASEADDR)
#define RV_BIN ((RVBin_TypeDef *)RV_BIN_BASEADDR)
#define RISC_IRQ ((RVIrq_TypeDef *)RV_IRQ_BASEADDR)
/*risc-v mpu map start*/
#define RV_MPU_ICB_PROTECT_BASE (RV_MPU_BASEADDR + 0x0004)
#define RV_MPU_DTCM_PROTECT_BASE (RV_MPU_ICB_PROTECT_BASE + 0x0004)
#define RV_MPU_ITCM_PROTECT_BASE (RV_MPU_DTCM_PROTECT_BASE + 0x0004)
#define RV_MPU_ICB_BASE_BASE (RV_MPU_BASEADDR + 0x0040)
#define RV_MPU_DTCM_BASE_BASE (RV_MPU_ICB_BASE_BASE + 0x0010)
#define RV_MPU_ITCM_BASE_BASE (RV_MPU_DTCM_BASE_BASE + 0x0010)
#define RV_MPU_ICB_LIMIT_BASE (RV_MPU_BASEADDR + 0x0080)
#define RV_MPU_DTCM_LIMIT_BASE (RV_MPU_ICB_LIMIT_BASE + 0x0010)
#define RV_MPU_ITCM_LIMIT_BASE (RV_MPU_DTCM_LIMIT_BASE + 0x0010)
/*risc-v mpu reg start*/
#define RVMPU ((RVMPU_TypeDef *)RV_MPU_BASEADDR)
#define ICB_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_ICB_PROTECT_BASE)
#define DTCM_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_DTCM_PROTECT_BASE)
#define ITCM_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_ITCM_PROTECT_BASE)
#define ICB_BASE ((RVMPUBASE_TypeDef *)RV_MPU_ICB_BASE_BASE)
#define DTCM_BASE ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_BASE_BASE)
#define ITCM_BASE ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_BASE_BASE)
#define ICB_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_ICB_LIMIT_BASE)
#define DTCM_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_LIMIT_BASE)
#define ITCM_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_LIMIT_BASE)
#define RV_WDT ((RVWdt_TypeDef *)RV_WDT_BASEADDR)
#define RV_IRQ_PRIO(x) *(volatile uint8_t*)(RV_IRQ_PRIO_BASEADDR + ((uint8_t)((uint8_t)(x)/2)))
#define RV_IRQ_PEND(x) *(volatile uint8_t*)(RV_IRQ_PEND_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
#define RV_IRQ_ENAB(x) *(volatile uint8_t*)(RV_IRQ_ENAB_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
#define RV_IRQ_THOD *(volatile int*)(RV_IRQ_THRD_BASEADDR)
#define RV_IRQ_CLAM *(volatile int*)(RV_IRQ_CLAM_BASEADDR)
/******************** RISC-V REG END **************************************/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
uint32_t TM_EN; /*!< Offset: 0x000 (R/W) SysTick Enable */
uint32_t TM_CNT; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
} SysTick_Type;
#define SysTick ((SysTick_Type *) RV_SYSTICK_BASEADDR ) /*!< SysTick configuration struct */
/******************************************************************************/
/**
* @method RV EnableIRQ
* @brief Enable IRQ
* @param IRQn : USB_IRQn...
* @retval NULL
*/
__STATIC_INLINE void RV_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
RV_IRQ_ENAB(IRQn) |= (uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
}
}
/**
* @method RV DisableIRQ
* @brief Disable IRQ
* @param IRQn : USB_IRQn...
* @retval NULL
*/
__STATIC_INLINE void RV_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
RV_IRQ_ENAB(IRQn) &= ~(uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
}
}
/**
* @method RV SetPriority
* @brief SetPriority IRQ
* @param IRQn : USB_IRQn...
* @param priority : 0~15
* @retval NULL
*/
__STATIC_INLINE void RV_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0 && priority > 0 && priority < 16)
{
RV_IRQ_PRIO(IRQn) |= (priority << (uint8_t)((uint8_t)(IRQn)%2)*4);
}
}
/**
* @method RV Get Pending Interrupt
* @brief Reads The PLIC pending register returns the pending bit
* @param IRQn : USB_IRQn...
* @retval 0: Interrupt status is not pending.
* 1: Interrupt status is pending
*/
__STATIC_INLINE uint32_t RV_GetPendingIRQ(IRQn_Type IRQn)
{
}
/**
* @method RV Get Interrupt Priority
* @brief Reads the priority of a device specific interrupt
* @param IRQn : USB_IRQn...
* @retval Interrupt Priority.
*/
__STATIC_INLINE uint32_t RV_GetPriority(IRQn_Type IRQn)
{
}
/**
* @method NVIC_Configuration
* @brief NVIC initialization function for risc-v.
* @param IRQn: Interrupt vector numbers could be 0~31.
* @param priority: Interrupt priority numbers could be 1~15.
* @param newstate: enable or disable
* @retval None
*/
__STATIC_INLINE void NVIC_Configuration(IRQn_Type IRQn, uint32_t priority,FunctionalState newstate)
{
if(newstate == ENABLE )
{
RV_EnableIRQ(IRQn);
RV_SetPriority(IRQn, priority);
}
else
{
RV_DisableIRQ(IRQn);
RV_SetPriority(IRQn, priority);
}
}
/**
* @method SysTick_Config
* @brief Initializes the System Timer and its interrupt (priority default 1)
* @param ticks: Number of ticks between two interrupts. (0~0xffffffff)
* @retval 0: FuncTion succeeded.
* 1: Function failed.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
SysTick->TM_CNT = ticks;
RV_EnableIRQ(34); /*set systick priority*/
RV_SetPriority(34,15);
SysTick->TM_EN = 1;
return (0UL);
}
/**
* @method __enable_irq
* @brief Enable IRQ Interrupts
* @retval NONE.
*/
__STATIC_INLINE void __enable_irq(void)
{
__asm("csrs mstatus,0x00000008");
}
/**
* @method __disable_irq
* @brief Disable IRQ Interrupts
* @retval NONE.
*/
__STATIC_INLINE void __disable_irq(void)
{
__asm("csrc mstatus,0x00000008");
}
/*make M0 and RV IRQ equ*/
#define NVIC_EnableIRQ RV_EnableIRQ
#define NVIC_DisableIRQ RV_DisableIRQ
#define NVIC_SetPriority RV_SetPriority
#define NVIC_GetPendingIRQ RV_GetPendingIRQ
/*end*/
#ifdef __cplusplus
}
#endif
#endif
#endif

77
bsp/yichip/yc3122-pos/Libraries/core/rom_api.h Normal file
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_rom_api.h
* @brief source file for setting rom_api
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#ifndef __ROM_API_H__
#define __ROM_API_H__
#define YC3122_AA (0)
#define YC3122_AB (1)
#define IC_DEVICE YC3122_AB
#if (IC_DEVICE == YC3122_AA)
/* TIMER */
#define FUNC_DELAY_US_ADDR (0x5030 + 1)
#define FUNC_DELAY_MS_ADDR (0x5068 + 1)
/* OTP */
#define FUNC_INIT_OTP_ADDR (0x5468 + 1)
#define FUNC_DEINIT_OTP_ADDR (0x54c8 + 1)
#define FUNC_READ_OTP_ADDR (0x5510 + 1)
#define FUNC_WRITE_OTP_ADDR (0x5648 + 1)
#define FUNC_READ_CHIPID_ADDR (0x56ac + 1)
#define FUNC_READ_CHIPLF_ADDR (0x56ba + 1)
/* LPM */
#define FUNC_LIGHT_SLEEP_ADDR (0x5338 + 1)
#define FUNC_DEEP_SLEEP_ADDR (0x535c + 1)
/* QSPI */
#define FUNC_ENC_WRITE_FLASH_ADDR (0x67c0 + 1)
#define FUNC_QSPI_FLASH_SECTORERASE_ADDR (0x59a8 + 1)
#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR (0x59b4 + 1)
#define FUNC_QSPI_FLASH_BLOCK64ERASE_ADDR (0x59c0 + 1)
#define FUNC_QSPI_FLASH_WRITE_ADDR (0x58e8 + 1)
#define FUNC_QSPI_FLASH_READ_ADDR (0x59ea + 1)
#define FUNC_FLASH_BLANK_CHECK (0x670c + 1)
#define FUNC_PREFETCH (0x5398 + 1)
#define FUNC_READ_FLASH_ID (0x5a54 + 1)
#elif (IC_DEVICE == YC3122_AB)
/* TIMER */
#define FUNC_DELAY_US_ADDR (0x5020 + 1)
#define FUNC_DELAY_MS_ADDR (0x5058 + 1)
/* OTP */
#define FUNC_INIT_OTP_ADDR (0x5458 + 1)
#define FUNC_DEINIT_OTP_ADDR (0x54b8 + 1)
#define FUNC_READ_OTP_ADDR (0x5500 + 1)
#define FUNC_WRITE_OTP_ADDR (0x5638 + 1)
#define FUNC_READ_CHIPID_ADDR (0x569c + 1)
#define FUNC_READ_CHIPLF_ADDR (0x56aa + 1)
/* LPM */
#define FUNC_LIGHT_SLEEP_ADDR (0x5328 + 1)
#define FUNC_DEEP_SLEEP_ADDR (0x534c + 1)
/* QSPI */
#define FUNC_ENC_WRITE_FLASH_ADDR (0x6798 + 1)
#define FUNC_QSPI_FLASH_SECTORERASE_ADDR (0x5998 + 1)
#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR (0x59a4 + 1)
#define FUNC_QSPI_FLASH_BLOCK64ERASE_ADDR (0x59b0 + 1)
#define FUNC_QSPI_FLASH_WRITE_ADDR (0x58d8 + 1)
#define FUNC_QSPI_FLASH_READ_ADDR (0x59da + 1)
#define FUNC_FLASH_BLANK_CHECK (0x66e4 + 1)
#define FUNC_PREFETCH (0x5388 + 1)
#define FUNC_READ_FLASH_ID (0x5a44 + 1)
#define FUNC_QSPI_FLASH_CMD (0x57ec + 1)
#endif
#endif

391
bsp/yichip/yc3122-pos/Libraries/core/system.c Normal file
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_system.c
* @brief source file for setting system
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#include <stdarg.h>
#include "system.h"
//*****************************************************************************
//
//! A simple MyPrintf function supporting \%c, \%d, \%p, \%s, \%u,\%x, and \%X.
//!
//! \param format is the format string.
//! \param ... are the optional arguments, which depend on the contents of the
//! \return None.
//
//*****************************************************************************
typedef struct _PrintPort_TypeDef_
{
UART_TypeDef *PrintUart;
GPIO_TypeDef PrintRX_Port;
GPIO_Pin_TypeDef PrintRX_Pin;
GPIO_TypeDef PrintTX_Port;
GPIO_Pin_TypeDef PrintTX_Pin;
} PrintPort_TypeDef;
static PrintPort_TypeDef PrintPort_Struct =
{
.PrintUart = PRINTPORT,
.PrintRX_Port = PRINTRX_PORT,
.PrintRX_Pin = PRINTRX_IO_PIN,
.PrintTX_Port = PRINTTX_PORT,
.PrintTX_Pin = PRINTTX_IO_PIN,
};
//#define SIM_PLATFORM
void print_char(int data)
{
volatile int *ptr;
ptr = (volatile int *)0xE0300;
*ptr = data;
}
void printfsend(uint8_t *buf, int len)
{
uint8_t printbuf[256];
for (int i = 0; i < len; i++)
{
printbuf[i] = buf[i];
#ifdef SIM_PLATFORM
print_char(buf[i]);
#endif
}
#ifndef SIM_PLATFORM
//UART_SendBuf(PrintPort_Struct.PrintUart, printbuf, len);
UART_SendBuf(PRINTPORT, printbuf, len);
#endif
}
void MyPrintf(char *format, ...)
{
static const int8_t *const g_pcHex1 = "0123456789abcdef";
static const int8_t *const g_pcHex2 = "0123456789ABCDEF";
uint32_t ulIdx = 0, ulValue = 0, ulPos = 0, ulCount = 0, ulBase = 0, ulNeg = 0;
int8_t *pcStr = NULL, pcBuf[16] = {0}, cFill = 0;
char HexFormat;
va_list vaArgP;
va_start(vaArgP, format);
while (*format)
{
/* Find the first non-% character, or the end of the string. */
for (ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); ulIdx++)
{}
/* Write this portion of the string. */
if (ulIdx > 0)
{
printfsend((uint8_t *)format, ulIdx);
}
format += ulIdx;
if (*format == '%')
{
format++;
/* Set the digit count to zero, and the fill character to space */
/* (i.e. to the defaults) */
ulCount = 0;
cFill = ' ';
again:
switch (*format++)
{
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
if ((format[-1] == '0') && (ulCount == 0))
{
cFill = '0';
}
ulCount *= 10;
ulCount += format[-1] - '0';
goto again;
}
case 'c':
{
ulValue = va_arg(vaArgP, unsigned long);
printfsend((uint8_t *)&ulValue, 1);
break;
}
case 'd':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
if ((long)ulValue < 0)
{
ulValue = -(long)ulValue;
ulNeg = 1;
}
else
{
ulNeg = 0;
}
ulBase = 10;
goto convert;
}
case 's':
{
pcStr = (int8_t *)va_arg(vaArgP, char *);
for (ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
{}
printfsend((uint8_t *)pcStr, ulIdx);
if (ulCount > ulIdx)
{
ulCount -= ulIdx;
while (ulCount--)
{
printfsend((uint8_t *)" ", 1);
}
}
break;
}
case 'u':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
ulBase = 10;
ulNeg = 0;
goto convert;
}
case 'X':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
ulBase = 16;
ulNeg = 0;
HexFormat = 'X';
goto convert;
}
case 'x':
case 'p':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
ulBase = 16;
ulNeg = 0;
HexFormat = 'x';
convert:
for (ulIdx = 1;
(((ulIdx * ulBase) <= ulValue) &&
(((ulIdx * ulBase) / ulBase) == ulIdx));
ulIdx *= ulBase, ulCount--)
{
}
if (ulNeg)
{
ulCount--;
}
if (ulNeg && (cFill == '0'))
{
pcBuf[ulPos++] = '-';
ulNeg = 0;
}
if ((ulCount > 1) && (ulCount < 16))
{
for (ulCount--; ulCount; ulCount--)
{
pcBuf[ulPos++] = cFill;
}
}
if (ulNeg)
{
pcBuf[ulPos++] = '-';
}
for (; ulIdx; ulIdx /= ulBase)
{
if (HexFormat == 'x')
pcBuf[ulPos++] = g_pcHex1[(ulValue / ulIdx) % ulBase];//x
else
pcBuf[ulPos++] = g_pcHex2[(ulValue / ulIdx) % ulBase];//X
}
printfsend((uint8_t *)pcBuf, ulPos);
break;
}
case '%':
{
printfsend((uint8_t *)format - 1, 1);
break;
}
default:
{
printfsend((uint8_t *)"ERROR", 5);
break;
}
}/* switch */
}/* if */
}/* while */
va_end(vaArgP);
}
void printv(uint8_t *buf, uint32_t len, char *s)
{
uint32_t i = 0;
uint32_t n = 0;
MyPrintf("\r\n%s:", s);
for (i = 0; i < len; i++)
{
if (i % 16 == 0)
{
MyPrintf("\r\n%08x:", n);
n += 16;
}
MyPrintf("%02x ", buf[i]);
}
MyPrintf("\r\n");
}
static void PrintPort_Init(void)
{
UART_InitTypeDef UART_InitStruct;
UART_InitStruct.BaudRate = PRINT_BAUD; //Configure serial port baud rate, the baud rate defaults to 128000.
UART_InitStruct.DataBits = DATABITS_8B;
UART_InitStruct.StopBits = STOPBITS_1;
UART_InitStruct.Parity = YC_PARITY_NONE;
UART_InitStruct.FlowCtrl = FLOWCTRL_NONE;
UART_InitStruct.RxMode = MODE_RX_ENABLE;
UART_InitStruct.SmartCard = SMARTCARD_DISABLE;
UART_InitStruct.CommMode = MODE_DUPLEX;
if (PrintPort_Struct.PrintUart == MUART0)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART0_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART0_TXD);
}
else if (PrintPort_Struct.PrintUart == MUART1)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART1_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART1_TXD);
}
else if (PrintPort_Struct.PrintUart == MUART2)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART2_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART2_TXD);
}
else if (PrintPort_Struct.PrintUart == MUART3)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART3_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART3_TXD);
}
UART_Init(PrintPort_Struct.PrintUart, &UART_InitStruct);
uint8_t print_irq = (PrintPort_Struct.PrintUart - MUART0) / (MUART1 - MUART0);
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + print_irq));
NVIC_SetPriority((IRQn_Type)(UART0_IRQn + print_irq),1);
}
void PrintPort_Set(UART_TypeDef *UARTx)
{
PrintPort_Struct.PrintUart = UARTx;
// if(UARTx == MUART1)
// {
// PrintPort_Struct.PrintRX_Port = UART1RX_PORT;
// PrintPort_Struct.PrintRX_Pin = UART1RX_IO_PIN;
// PrintPort_Struct.PrintTX_Port = UART1TX_PORT;
// PrintPort_Struct.PrintTX_Pin = UART1TX_IO_PIN;
// }
}
void Board_Init(void)
{
/*fpga io func sel*/
#if (BOARD_TYPE == FPGA_BOARD)
uint8_t fpga_io_func_sel_list[][2] =
{
#ifdef __SPI0_FLASH_FPGA__
{0x02,0x01},
{0x08,0x01},
{0x21,0x40},
#endif
{0x00,0x00},
#ifdef __SPI1_FLASH_FPGA__
{0x05,0x01},
{0x08,0x01},
{0x21,0x80},
#endif
#ifdef __SCANNER_BF3007_BCTC_FPGA__
{0x01,0x01}, //func_sel1: ALT1 psram
{0x08,0x01}, //func_sel8: ALT1 tft
{0x09,0x01}, //func_sel9: ALT1 tft led
{0x02,0x01}, //func_sel9: ALT1 spia
{0x21,0x04}, //spi_sel:tft_spi_sel: SPIy
{0x20,0x02}, //iic_sel:iic0_sel: fingerprint i2c
{0x04,0x01}, //sel iica
{0x06,0x02}, //func_sel6: ALT2 fingerprint DCMI
{0x07,0x01}, //alt1 buzzer
#endif
};
for(uint8_t i = 0; i < (sizeof(fpga_io_func_sel_list)/2); i ++)
{
FPGA_reg_write(fpga_io_func_sel_list[i][0],fpga_io_func_sel_list[i][1]);
}
#endif
/*print init*/
PrintPort_Init();
}
void _assert_handler(const char *file, int line, const char *func)
{
#if defined (SDK_DEBUG)
if(PRINTPORT->CTRL.bit.RX_EN == MODE_RX_ENABLE) /*check printuart is init*/
{
MyPrintf("Assert trigger at file: %s line:%d func: %s\n ", file, line, func);
}
#endif
while (1);
}

59
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_system.h
* @brief source file for setting system
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#ifndef __SYSTEM_H__
#define __SYSTEM_H__
#define SDK_DEBUG //Debug switch
#include <string.h>
#include "yc_uart.h"
#include "rom_api.h"
#include "board_config.h"
#define BIT_SET(a,b) ((a) |= (1<<(b)))
#define BIT_CLEAR(a,b) ((a) &= ~(1<<(b)))
#define BIT_FLIP(a,b) ((a) ^= (1<<(b))) //bit Negation
#define BIT_GET(a,b) (((a) & (1<<(b)))>>(b))
/**
* @brief Print format string to serial port 0.You need to initialize the serial port 0 before you use MyPrintf.
*
* @param format : format string
* @param ...: format parameter
*/
void MyPrintf(char *format, ...);
void printv(uint8_t *buf, uint32_t len, char *s);
void PrintPort_Set(UART_TypeDef *UARTx);
void Board_Init(void);
void _assert_handler(const char *file, int line, const char *func);
#ifdef SDK_DEBUG
#define _ASSERT(x) \
if (!(x)) \
{ \
_assert_handler(__FILE__,__LINE__,__FUNCTION__);\
}
#else
#define _ASSERT(x)
#endif
#define YC_DEBUG_LOG(type, message) \
do \
{ \
if (type) \
MyPrintf message; \
} \
while (0)
#endif /*__SYSTEM_H__*/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_type.h
* @brief source file for setting type
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#ifndef __TYPE_H__
#define __TYPE_H__
#if defined (__CC_ARM) || defined ( __ICCARM__ )
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
typedef unsigned char byte;
typedef unsigned short word;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long long int64_t;
#else
#include "stdio.h"
typedef unsigned char byte;
typedef unsigned short word;
#endif
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE noinline
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifndef Boolean
typedef enum {FALSE = 0, TRUE =1} Boolean;
#define IS_BOOLEAN(bool) ((bool == FALSE) || (bool == TRUE))
#endif
#ifndef FunctionalState
typedef enum {DISABLE = 0, ENABLE =1} FunctionalState;
#define IS_FUNCTIONAL_STATE(state) ((state== DISABLE) || (state == ENABLE))
#endif
#ifndef FunctionalState
typedef enum {ERROR = 0, SUCCESS = 1} ErrorStatus;
#define IS_ERROR_STATE(status) ((status== ERROR) || (status == SUCCESS))
#endif
#ifndef FlagStatus
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#endif
#ifndef YC_NULL
#define YC_NULL (0)
#endif
#ifndef NULL
#define NULL (0)
#endif
#endif /*__TYPE_H__*/

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bsp/yichip/yc3122-pos/Libraries/sdk/libyc_qspi.a Normal file
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_exit.c
* @brief source file for setting exit
*
* Change Logs:
* Date Author Version Notes
* 2021-12-24 yangzhengfeng V1.0.0 Modify the register module configuration
* 2021-01-03 wangjingfan V1.0.1 Compile error correction
* 2021-01-20 yangzhengfeng V1.0.2 Update library function
*/
#include "yc_exti.h"
/**
* @brief Clear interrupt flag
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @param EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
* @retval none
*/
void EXTI_ClearITPendingBit(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
_ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
MGPIO->IRQ_STATUS.reg[EXTI_Line] |= EXTI_PinSource;
}
/**
* @brief Deinitializes the EXTI registers to default reset values.
* @param none
* @retval none
*/
void EXTI_DeInit()
{
uint32_t i;
for (i = 0; i < EXIT_Num; i++)
{
MGPIO->INTR.reg[i] = 0;
MGPIO->IRQ_LEVEL.reg[i] = 0;
MGPIO->IRQ_RISE.reg[i] = 0;
MGPIO->IRQ_FALL.reg[i] = 0;
}
}
/**
* @brief get interrupt status
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @retval none
*/
uint16_t EXTI_GetITLineStatus(EXTI_LineTypeDef EXTI_Line)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
return MGPIO->INTR.reg[EXTI_Line];
}
/**
* @brief get interrupt pinsource status
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @param EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
* @retval none
*/
uint16_t EXTI_GetITEXTI_PinSourceStatus(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
_ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
if(MGPIO->INTR.reg[EXTI_Line] & EXTI_PinSource)
{
return ENABLE;
}
else
{
return DISABLE;
}
}
/**
* @brief EXTI LineConfig
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @param EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
* @param EXTI_Trigger:EXTI Trigger mode
* @retval none
*/
void EXTI_LineConfig(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
_ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
_ASSERT(IS_TRIG_TYPEDEF(EXTI_Trigger));
uint16_t val_intr_lts,val_intr_rts,val_intr_fts,val_intr_en;
switch (EXTI_Trigger)
{
case EXTI_Trigger_Off:
val_intr_en = ~EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_HighLev:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_LowLev:
val_intr_en = EXTI_PinSource;
val_intr_lts = EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_Rising:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_Falling:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = EXTI_PinSource;
break;
case EXTI_Trigger_Rising_Falling:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = EXTI_PinSource;
val_intr_fts = EXTI_PinSource;
break;
default:
break;
}
if (EXTI_Trigger == EXTI_Trigger_Off)
{
MGPIO->INTR.reg[EXTI_Line] &= val_intr_en;
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
}
else if (EXTI_Trigger == EXTI_Trigger_HighLev )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_LowLev )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] |= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_Rising )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] |= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_Falling )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] |= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_Rising_Falling )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] |= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] |= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
}
//extern void VBAT_IRQHandler(void);
//extern void EXTI0_IRQHandler(void);
//extern void EXTI1_IRQHandler(void);
//extern void EXTI2_IRQHandler(void);
//extern void EXTI3_IRQHandler(void);
//extern void EXTI4_IRQHandler(void);
//void GPIO_IRQHandler()
//{
// uint8_t Exti_irq_index;
// NVIC_DisableIRQ(GPIO_IRQn);
// if (MSYSCTRL->CHGR_EVENT_IRQ.bit.VBAT_OV & MSYSCTRL->CHGR_EVENT_ICTRL.bit.VBAT_OV_IE)
// {
// //VBAT_IRQHandler();
// }
// Exti_irq_index = MGPIO->IRQ_NUM.reg;
// if(MGPIO->INTR.reg[Exti_irq_index/EXIT_Pin_Num] &(1 << (Exti_irq_index%EXIT_Pin_Num)))
// {
// switch (Exti_irq_index/EXIT_Pin_Num)
// {
// case EXTI_Line_0:
// EXTI0_IRQHandler();
// break;
// case EXTI_Line_1:
// EXTI1_IRQHandler();
// break;
// case EXTI_Line_2:
// EXTI2_IRQHandler();
// break;
// case EXTI_Line_3:
// EXTI3_IRQHandler();
// break;
// case EXTI_Line_4:
// EXTI4_IRQHandler();
// break;
// default:
// break;
// }
// EXTI_ClearITPendingBit((EXTI_LineTypeDef)(Exti_irq_index/EXIT_Pin_Num),(EXTI_PIN_TypeDef)(BIT(Exti_irq_index%EXIT_Pin_Num)));
// }
// NVIC_EnableIRQ(GPIO_IRQn);
//}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_exit.h
* @brief source file for setting exit
*
* Change Logs:
* Date Author Version Notes
* 2021-12-24 yangzhengfeng V1.0.0 Modify the register module configuration
* 2021-01-03 wangjingfan V1.0.1 Compile error correction
*/
#ifndef __YC_EXTI_H__
#define __YC_EXTI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "yc3122.h"
#include "yc_gpio.h"
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Off = 0,
EXTI_Trigger_HighLev = 1,
EXTI_Trigger_LowLev = 2,
EXTI_Trigger_Rising = 3,
EXTI_Trigger_Falling = 4,
EXTI_Trigger_Rising_Falling = 5,
EXTI_Trigger_DEFAULT_VAL = 0xff
} EXTI_TriggerTypeDef;
#define IS_TRIG_TYPEDEF(TRIGTYPE) ((TRIGTYPE) == EXTI_Trigger_Off || \
(TRIGTYPE) == EXTI_Trigger_HighLev || \
(TRIGTYPE) == EXTI_Trigger_LowLev || \
(TRIGTYPE) == EXTI_Trigger_Rising || \
(TRIGTYPE) == EXTI_Trigger_Falling || \
(TRIGTYPE) == EXTI_Trigger_Rising_Falling)
/**
* @brief EXTI Trigger source
*/
typedef enum
{
EXTI_Line_0 = 0,
EXTI_Line_1 = 1,
EXTI_Line_2 = 2,
EXTI_Line_3 = 3,
EXTI_Line_4 = 4,
EXTI_Line_DEFAULT_VAL = 0xff
} EXTI_LineTypeDef;
#define IS_EXTI_LINE(LINE) (((LINE) == EXTI_Line_0) || \
((LINE) == EXTI_Line_1) || \
((LINE) == EXTI_Line_2) || \
((LINE) == EXTI_Line_3) || \
((LINE) == EXTI_Line_4))
#define IS_EXTI_PIN_SOURCE(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
#define EXTI_MODE_TypeDef GPIO_MODULE_TypeDef
#define EXTI_PIN_TypeDef GPIO_Pin_TypeDef
#define EXIT_Num GPIO_PORT_NUM
#define EXIT_Pin_Num GPIO_PIN_NUM
void EXTI_ClearITPendingBit(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource);
void EXTI_DeInit(void);
uint16_t EXTI_GetITLineStatus(EXTI_LineTypeDef EXTI_Line);
uint16_t EXTI_GetITEXTI_PinSourceStatus(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource);
void EXTI_LineConfig(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger);
#ifdef __cplusplus
}
#endif
#endif /* __YC_EXTI_H__ */
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_gpio.c
* @brief source file for setting gpio
*
* Change Logs:
* Date Author Version Notes
* 2021-01-20 yangzhengfeng V1.0.2 Update library function
* 2021-07-29 xubo V1.0.3 Update library function
*/
#include "yc_gpio.h"
uint8_t const UnMapTb[256] = {
0u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x00 to 0x0F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x10 to 0x1F */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x20 to 0x2F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x30 to 0x3F */
6u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x40 to 0x4F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x50 to 0x5F */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x60 to 0x6F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x70 to 0x7F */
7u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x80 to 0x8F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x90 to 0x9F */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xA0 to 0xAF */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xB0 to 0xBF */
6u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xC0 to 0xCF */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xD0 to 0xDF */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xE0 to 0xEF */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u /* 0xF0 to 0xFF */
};
uint8_t UnMap(uint16_t x)
{
uint8_t lx = x;
uint8_t hx = x >> 8;
if(lx)
{
return UnMapTb[lx];
}
else
{
return UnMapTb[hx] + 8;
}
}
/**
* @method GPIO_Config
* @brief config gpio function(Only one can be configured at a time)
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)(Only one can be configured at a time)
* @param function:gpio function
* @retval none
*/
void GPIO_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_FUN_TYPEDEF function)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
_ASSERT(IS_GPIO_FUN(function));
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = function;
}
/**
* @method GPIO_Init
* @brief gpio mode Init
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_InitStruct:GPIO_InitStruct
* @retval none
*/
void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
_ASSERT(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
{
if(GPIO_InitStruct->GPIO_Pin & (BIT0<<i))
{
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = GPIO_InitStruct->GPIO_Mode << 6;
}
}
}
/**
* @method GPIO_PullUpCmd
* @brief gpio pull up
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_7)
* @param NewState: new state of the port pin Pull Up.(ENABLE or DISABLE)
* @retval none
*/
void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
_ASSERT(IS_FUNCTIONAL_STATE(NewState));
uint8_t i = 0;
if (ENABLE == NewState)
{
for(i = 0; i<GPIO_PIN_NUM; i++)
{
MGPIO->CTRL.bit[GPIO_GetNum(GPIOx,(GPIO_Pin_TypeDef)(BIT0 << i))].MODE = GPIO_Mode_IPU;
}
}
else if (DISABLE == NewState)
{
for(i = 0; i<GPIO_PIN_NUM; i++)
{
MGPIO->CTRL.bit[GPIO_GetNum(GPIOx, (GPIO_Pin_TypeDef)(BIT0 << i))].MODE = GPIO_Mode_IN_FLOATING;
}
}
}
/**
* @method GPIO_ReadInputData
* @brief Reads the GPIO input data for 2byte.
* @param GPIOx_IN: where x can be (GPIOA_IN...GPIOF_IN) to select the GPIO group.
* @retval GPIO input data.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
return MGPIO->IN_LEVEL.reg[GPIOx];
}
/**
* @method GPIO_ReadInputDataBit
* @brief Reads the GPIO input data(status) for bit.
* @param GPIOx_IN: where x can be (GPIOA_IN...GPIOF_IN) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval The input bit
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
if (((MGPIO->IN_LEVEL.reg[GPIOx]) & GPIO_Pin) != (uint32_t)Bit_RESET)
{
return (uint8_t)Bit_SET;
}
return (uint8_t)Bit_RESET;
}
/**
* @method GPIO_ReadOutputData
* @brief Reads the GPIO output data(status) for byte.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @retval GPIO output data(status).
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
return MGPIO->IN_LEVEL.reg[GPIOx];
}
/**
* @method GPIO_ReadOutputDataBit
* @brief Reads the GPIO output data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval The output status
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
if (((MGPIO->IN_LEVEL.reg[GPIOx]) & GPIO_Pin) != (uint32_t)Bit_RESET)
{
return (uint8_t)Bit_SET;
}
return (uint8_t)Bit_RESET;
}
/**
* @method GPIO_ResetBit
* @brief Reset the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to reset.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_ResetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = OUTPUT_LOW;
}
/**
* @method GPIO_ResetBits
* @brief Reset the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to reset.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
{
if(GPIO_Pin & (BIT0<<i))
{
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = OUTPUT_LOW;
}
}
}
/**
* @method GPIO_SetBit
* @brief Set the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_SetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = OUTPUT_HIGH;
}
/**
* @method GPIO_SetBits
* @brief Set the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
{
if(GPIO_Pin & (BIT0<<i))
{
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = OUTPUT_HIGH;
}
}
}
/**
* @method GPIO_Write
* @brief Write the GPIO group data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param value: select the value to read.(0 or 1)
* @retval none
*/
void GPIO_Write(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
GPIO_SetBits(GPIOx, GPIO_Pin);
GPIO_ResetBits(GPIOx, (GPIO_Pin_TypeDef)(~GPIO_Pin));
}
/**
* @method GPIO_WriteBit
* @brief Write the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @param BitVal: select the value to read.(0 or 1)
* @retval none
*/
void GPIO_WriteBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction BitVal)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
if (BitVal == Bit_SET)
GPIO_SetBit(GPIOx, GPIO_Pin);
else if (BitVal == Bit_RESET)
GPIO_ResetBit(GPIOx, GPIO_Pin);
}
/**
* @method GPIO_ODSet
* @brief Set the GPIO OD MODE
* @param GPIOx_Drv: where x can be (GPIOA_Drv...GPIOE_Drv) to select the GPIO_Drv group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @param Drvtype: select the value to set DRV value.(0x00....0x11)
* @retval none
*/
void GPIO_ODSet(GPIO_OD_TypeDef GPIOx_OD, GPIO_ODTypeDef GPIO_OD_Set)
{
_ASSERT(IS_GPIO_OD(GPIOx_OD));
_ASSERT(IS_GPIO_MODE_OUT(GPIO_OD_Set));
(MGPIO->OD_CTRL.reg) |= (GPIO_OD_Set << GPIOx_OD);
}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_gpio.h
* @brief source file for setting gpio
*
* Change Logs:
* Date Author Version Notes
* 2020-12-23 yangzhengfeng V1.1.0 Modify the register module configuration
*/
#ifndef __YC_GPIO_H__
#define __YC_GPIO_H__
#include "yc3122.h"
#include "system.h"
#ifdef __cplusplus
extern "C" {
#endif
uint8_t UnMap(uint16_t x);
#define GPIO_CONFIG(x) *((volatile uint8_t*)(MGPIO_BASE + x))
#define GPIO_GetNum(port, pin) ((port * GPIO_PIN_NUM) + UnMap(pin))
#define GPIO_OD_TypeDef uint8_t
#define GPIO_FUN_TYPEDEF uint8_t
#define GPIO_PORT_NUM 5
#define GPIO_PIN_NUM 16
#define GPIO_OD_PORTA_10 ((GPIO_OD_TypeDef)0x00) /*!< Pin 10 selected */
#define GPIO_OD_PORTB_06 ((GPIO_OD_TypeDef)0x01) /*!< Pin 20 selected */
#define GPIO_OD_PORTC_01 ((GPIO_OD_TypeDef)0x02) /*!< Pin 33 selected */
#define GPIO_OD_PORTC_08 ((GPIO_OD_TypeDef)0x03) /*!< Pin 40 selected */
#define GPIO_OD_PORTD_00 ((GPIO_OD_TypeDef)0x04) /*!< Pin 48 selected */
#define GPIO_OD_PORTD_12 ((GPIO_OD_TypeDef)0x05) /*!< Pin 60 selected */
#define GPIO_OD_PORTE_06 ((GPIO_OD_TypeDef)0x06) /*!< Pin 76 selected */
#define GPIO_OD_PORTE_12 ((GPIO_OD_TypeDef)0x07) /*!< Pin 70 selected */
#define IS_GPIO_OD(port_od) ((port_od == GPIO_OD_PORTA_10) || \
(port_od == GPIO_OD_PORTB_06) || \
(port_od == GPIO_OD_PORTC_01) || \
(port_od == GPIO_OD_PORTC_08) || \
(port_od == GPIO_OD_PORTD_00) || \
(port_od == GPIO_OD_PORTD_12) || \
(port_od == GPIO_OD_PORTE_06) || \
(port_od == GPIO_OD_PORTE_12))
typedef enum
{
GPIO_Pin_0 = BIT0,
GPIO_Pin_1 = BIT1,
GPIO_Pin_2 = BIT2,
GPIO_Pin_3 = BIT3,
GPIO_Pin_4 = BIT4,
GPIO_Pin_5 = BIT5,
GPIO_Pin_6 = BIT6,
GPIO_Pin_7 = BIT7,
GPIO_Pin_8 = BIT8,
GPIO_Pin_9 = BIT9,
GPIO_Pin_10 = BIT10,
GPIO_Pin_11 = BIT11,
GPIO_Pin_12 = BIT12,
GPIO_Pin_13 = BIT13,
GPIO_Pin_14 = BIT14,
GPIO_Pin_15 = BIT15
} GPIO_Pin_TypeDef;
#define IS_GPIO_PIN(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GPIO_PIN_SINGLE(PIN) ((PIN == GPIO_Pin_0) || \
(PIN == GPIO_Pin_1) || \
(PIN == GPIO_Pin_2) || \
(PIN == GPIO_Pin_3) || \
(PIN == GPIO_Pin_4) || \
(PIN == GPIO_Pin_5) || \
(PIN == GPIO_Pin_6) || \
(PIN == GPIO_Pin_7) || \
(PIN == GPIO_Pin_8) || \
(PIN == GPIO_Pin_9) || \
(PIN == GPIO_Pin_10) || \
(PIN == GPIO_Pin_11) || \
(PIN == GPIO_Pin_12) || \
(PIN == GPIO_Pin_13) || \
(PIN == GPIO_Pin_14) || \
(PIN == GPIO_Pin_15))
typedef enum
{
GPIOA = 0,
GPIOB,
GPIOC,
GPIOD,
GPIOE
} GPIO_TypeDef;
#define IS_GPIO_PORT(port) (port <= GPIOE)
/******************* Bit definition for gpio funaction **********************/
#define INPUT ((GPIO_FUN_TYPEDEF) 0)
#define QSPI_NCS ((GPIO_FUN_TYPEDEF) 2) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_SCK ((GPIO_FUN_TYPEDEF) 3) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO0 ((GPIO_FUN_TYPEDEF) 4) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO1 ((GPIO_FUN_TYPEDEF) 5) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO2 ((GPIO_FUN_TYPEDEF) 6) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO3 ((GPIO_FUN_TYPEDEF) 7) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define UART0_TXD ((GPIO_FUN_TYPEDEF) 8)
#define UART0_RXD ((GPIO_FUN_TYPEDEF) 9)
#define UART0_RTS ((GPIO_FUN_TYPEDEF)10)
#define UART0_CTS ((GPIO_FUN_TYPEDEF)11)
#define UART1_TXD ((GPIO_FUN_TYPEDEF)12) /*Mapping the scope GPIO[47:0]*/
#define UART1_RXD ((GPIO_FUN_TYPEDEF)13) /*Mapping the scope GPIO[47:0]*/
#define UART1_RTS ((GPIO_FUN_TYPEDEF)14) /*Mapping the scope GPIO[47:0]*/
#define UART1_CTS ((GPIO_FUN_TYPEDEF)15) /*Mapping the scope GPIO[47:0]*/
#define UART2_TXD ((GPIO_FUN_TYPEDEF)36) /*Mapping the scope GPIO[79:40]*/
#define UART2_RXD ((GPIO_FUN_TYPEDEF)37) /*Mapping the scope GPIO[79:40]*/
#define UART2_RTS ((GPIO_FUN_TYPEDEF)38) /*Mapping the scope GPIO[79:40]*/
#define UART2_CTS ((GPIO_FUN_TYPEDEF)39) /*Mapping the scope GPIO[79:40]*/
#define UART3_TXD ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define UART3_RXD ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define UART3_RTS ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define UART3_CTS ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define PWM_OUT ((GPIO_FUN_TYPEDEF)16) /*Each group of 8 GPIOs is mapped to PWM0~7*/
#define PWM_OUT8 ((GPIO_FUN_TYPEDEF)17) /*Mapping the scope GPIO[79:48]*/
#define PWM_OUT01 ((GPIO_FUN_TYPEDEF)40) /*GPIO_INDEX%8 is not a 0 and 1 pin, each two is a group, respectively mapped to PWM0/PWM1*/
#define PWM_OUT23 ((GPIO_FUN_TYPEDEF)41) /*GPIO_INDEX%8 is not a 2 and 3 pin, each two is a group, respectively mapped to PWM2/PWM3*/
#define DCMI_PCLK ((GPIO_FUN_TYPEDEF)18)
#define DCMI_VSYNC ((GPIO_FUN_TYPEDEF)19)
#define DCMI_HSYNC ((GPIO_FUN_TYPEDEF)20)
#define DCMI_D0 ((GPIO_FUN_TYPEDEF)21)
#define DCMI_D1 ((GPIO_FUN_TYPEDEF)22)
#define DCMI_D0_D13 ((GPIO_FUN_TYPEDEF)23) /*GPIO[7] to GPIO[76] is a group of 14, which are mapped to D13 to D0 respectively*/
#define SPID_SDIO ((GPIO_FUN_TYPEDEF)27) /*Every 3 GPIOs are a group, which are respectively mapped to SPI0_SDIO/SPI1_SDIO/SPI2_SDIO*/
#define SPID0_NCS ((GPIO_FUN_TYPEDEF)24) /*Mapping the scope GPIO[79:0]*/
#define SPID0_SCK ((GPIO_FUN_TYPEDEF)25) /*Mapping the scope GPIO[79:0]*/
#define SPID0_MOSI ((GPIO_FUN_TYPEDEF)26) /*Mapping the scope GPIO[79:0]*/
#define SPID0_MISO ((GPIO_FUN_TYPEDEF)28) /*Mapping the scope GPIO[79:0]*/
#define SPID1_NCS ((GPIO_FUN_TYPEDEF)48) /*Mapping the scope GPIO[79:0]*/
#define SPID1_SCK ((GPIO_FUN_TYPEDEF)49) /*Mapping the scope GPIO[79:0]*/
#define SPID1_MOSI ((GPIO_FUN_TYPEDEF)50) /*Mapping the scope GPIO[79:0]*/
#define SPID1_MISO ((GPIO_FUN_TYPEDEF)52) /*Mapping the scope GPIO[79:0]*/
#define SPID_SLV_IN ((GPIO_FUN_TYPEDEF)29) /*Each of 6 GPIOs is a group, which are mapped to MSPI0~2 NCS_IN/SCK_IN respectively*/
#define XTAL32K ((GPIO_FUN_TYPEDEF)30) /*Mapping the scope GPIO[15:0] and [74:48]*/
#define HSPI_NCS ((GPIO_FUN_TYPEDEF)31) /*Map to all pins*/
#define HSPI_SCK ((GPIO_FUN_TYPEDEF)32) /*Map to all pins*/
#define HSPI_MOSI ((GPIO_FUN_TYPEDEF)33) /*Map to all pins*/
#define HSPI_MISO ((GPIO_FUN_TYPEDEF)34) /*Map to all pins*/
#define DAC_OUT ((GPIO_FUN_TYPEDEF)35) /*Each group of 2 GPIOs is mapped to Out P/Out N respectively*/
#define SDIO ((GPIO_FUN_TYPEDEF)42) /*Each of 6 GPIOs is a group mapped to SDIO_CLK/SDIO_CMD/DAT0/DAT1/DAT2/DAT3*/
#define PSRAM_NCS ((GPIO_FUN_TYPEDEF)43)
#define PSRAM_SCK ((GPIO_FUN_TYPEDEF)44)
#define PSRAM_DATA_0 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define PSRAM_DATA_1 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define PSRAM_DATA_2 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define PSRAM_DATA_3 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define JTAG_RV_TCK ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define JTAG_RV_TMS ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define JTAG_RV_TDI ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define JTAG_RV_TDO ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define I2C0_SCL ((GPIO_FUN_TYPEDEF)58)
#define I2C0_SDA ((GPIO_FUN_TYPEDEF)59)
#define I2C1_SCL ((GPIO_FUN_TYPEDEF)47)
#define I2C1_SDA ((GPIO_FUN_TYPEDEF)47)
#define SCI7816_IO ((GPIO_FUN_TYPEDEF)56)
#define SCI7816_IO2 ((GPIO_FUN_TYPEDEF)51)
#define NFC_CLK_OUT ((GPIO_FUN_TYPEDEF)55)
#define ICE ((GPIO_FUN_TYPEDEF)57)
#define JTAG_SWCLK ((GPIO_FUN_TYPEDEF)60) /*The first 16 pins are mapped to SWCLK, and the latter pins are mapped to SWCLK/SWDIO for a group of 2 GPIOs*/
#define JTAG_SWDIO ((GPIO_FUN_TYPEDEF)61) /*The first 16 pins are mapped to SWDIO*/
#define OUTPUT_LOW ((GPIO_FUN_TYPEDEF)62)
#define OUTPUT_HIGH ((GPIO_FUN_TYPEDEF)63)
#define PULL_PU ((GPIO_FUN_TYPEDEF)64)
#define PULL_PD ((GPIO_FUN_TYPEDEF)128)
#define ANALOG ((GPIO_FUN_TYPEDEF)192)
#define IS_GPIO_FUN(fun) (fun <= 0xff)
#define IS_GPIO_MODE(mode) (((mode) == GPIO_Mode_IN_FLOATING) || \
((mode) == GPIO_Mode_IPU) || \
((mode) == GPIO_Mode_IPD) || \
((mode) == GPIO_Mode_AIN) || \
((mode) == GPIO_Mode_Out_PP))
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET = 1
} BitAction;
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_Mode_IN_FLOATING = 0x00,
GPIO_Mode_IPU = 0x01,
GPIO_Mode_IPD = 0x02,
GPIO_Mode_AIN = 0x03,
GPIO_Mode_Out_PP = 0x3E /*!< analog signal mode */
} GPIO_ModeTypeDef;
/**
* @brief Configuration GPIO OD enumeration
*/
typedef enum
{
GPIO_Mode_OD_RESET = 0x0,
GPIO_Mode_OD_SET = 0x1
} GPIO_ODTypeDef;
#define IS_GPIO_MODE_OUT(mode) (((mode) == GPIO_Mode_OD_RESET) || \
((mode) == GPIO_Mode_OD_SET))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
GPIO_Pin_TypeDef GPIO_Pin;
GPIO_ModeTypeDef GPIO_Mode;
} GPIO_InitTypeDef;
uint32_t GPIO_GetGPIONum(GPIO_TypeDef GPIOx);
void GPIO_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_FUN_TYPEDEF function);
void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState);
uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_ResetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin);
void GPIO_SetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin);
void GPIO_Write(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction BitVal);
void GPIO_ODSet(uint8_t GPIOx_OD, GPIO_ODTypeDef GPIO_OD_Set);
#ifdef __cplusplus
}
#endif
#endif /* __YC_GPIO_H__ */
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_qspi.h
* @brief This file contains all the functions prototypes for the IFlash library.
*
* Change Logs:
* Date Author Version Notes
* 2021-08-14 wushengyan V1.0.0 the first version
*/
#ifndef __YC_QSPI_H__
#define __YC_QSPI_H__
#include "yc3122.h"
#define BOOT_UART_DOWNLOAD_FLAG 0x5a5aa5a5
#define BOOT_USB_DOWNLOAD_FLAG 0xaa5555aa
#define BOOT_AUTO_SELECT_FLAG 0xffffffff
#define ENC_BULK_BUF_SIZE 0x9000
typedef enum {
YC_QFLASH_SIZE_UNKNOW = 0,
YC_QFLASH_SIZE_512KB = 1,
YC_QFLASH_SIZE_1MB = 2,
YC_QFLASH_SIZE_4MB = 3,
} yc_qspi_flash_size_enum;
typedef struct
{
uint16_t is_end;
uint16_t enc_index;
uint8_t enc_buf[ENC_BULK_BUF_SIZE];
} ENC_BulkTypeDef;
/**
* @method qspi_flash_pageerase
* @brief page erase (256byte)
* @param flash_addr
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_pageerase(uint32_t flash_addr);
/**
* @method qspi_flash_sectorerase
* @brief sector erase (4K)
* @param flash_addr:flash addr (4k Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_sectorerase(uint32_t flash_addr);
/**
* @method qspi_flash_blockerase32k
* @brief block erase (32K)
* @param flash_addr:flash addr (32k Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_blockerase32k(uint32_t flash_addr);
/**
* @method qspi_flash_blockerase64k
* @brief block erase (64K)
* @param flash_addr:flash addr (64k Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_blockerase64k(uint32_t flash_addr);
/**
* @method qspi_flash_write
* @brief write flash
* @param flash_addr:flash addr (when flash_addr%256!=0,256-(flash_addr%256)+len must less than 256)
* @param buf
* @param len
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_write(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method qspi_flash_read
* @brief read flash
* @param flash_addr:flash addr
* @param buf
* @param len
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_read(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method flash_blank_check
* @brief check logical addr data is blank
* @param startaddr:cpu addr
* @param len
* @retval TRUE: blank
* FALSE: not blank
*/
Boolean flash_blank_check(uint32_t startaddr, uint32_t len);
/**
* @method enc_write_flash
* @brief write data to flash with enc
* @param flash_addr:cpu addr (must 32 Bytes align)
* @param buf
* @param len:(must 32 Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t enc_write_flash(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method enc_read_flash
* @brief read flash data with enc
* @param flash_addr:cpu addr
* @param buf
* @param len
* @retval ERROR,SUCCESS
*/
uint8_t enc_read_flash(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method enc_read_flash_fast
* @brief enc read flash fast(You must sure that the read area is written by enc)
* @param flash_addr:cpu addr
* @param buf
* @param len
* @return SUCCESS or ERROR
*/
uint8_t enc_read_flash_fast(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method enc_erase_flash_32byte
* @brief erase 32 Bytes
* @param flash_addr : cpu addr (must 32 Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t enc_erase_flash_32byte(uint32_t flash_addr);
/**
* @method enc_erase_flash_32k
* @brief enc erase 32K Bytes
* @param flash_addr : cpu addr (must 32K Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t enc_erase_flash_32k(uint32_t flash_addr);
/**
* @brief enc erase flash app area
* @param addr:align at 32k for CPU addr
* @param len:erase len
* @return ERROR,SUCCESS
*/
uint8_t enc_earse_flash_app_area(uint32_t addr,uint32_t len);
/**
* @brief enc write download flag
* @param addr:BOOT_UART_DOWNLOAD_FLAG,BOOT_USB_DOWNLOAD_FLAG or BOOT_AUTO_SELECT_FLAG
* @return ERROR,SUCCESS
*/
uint8_t enc_write_download_flag(uint32_t flag);
/**
* @method enc_write_flash_bulk
* @brief write bulk data to flash with enc
* @param EncBulkStruct:enc buf struct
* @param flash_addr:cpu addr(start addr must 32k Bytes align)
* @param buf
* @param len: Integer multiple of 32 bytes
* @retval ERROR,SUCCESS
*/
uint8_t enc_write_flash_bulk(ENC_BulkTypeDef *EncBulkStruct,uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method prefetch
* @brief fetch code to cache
* @param start_addr: code start addr
* @param end_addr : code end addr
* @retval NULL
*/
void prefetch(void *start_addr, void *end_addr);
/**
* @method read_flash_size
* @brief read the chip flash size
* @param NULL
* @retval yc_qspi_flash_size_enum
*/
yc_qspi_flash_size_enum read_flash_size(void);
/**
* @method qspi_GetVersion
* @brief get qspi lib version
* @param NULL
* @retval version
*/
uint32_t qspi_GetVersion(void);
#endif

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_uart.c
* @brief source file for setting uart
*
* Change Logs:
* Date Author Version Notes
* 2020-11-06 wushengyan V1.0.0 the first version
*/
#include "yc_uart.h"
#define uart_DMA_buf_len 1024
const UART_TypeDef * const UARTs[] = {MUART0, MUART1, MUART2, MUART3};
uint8_t uart0_DMA_buf[uart_DMA_buf_len] = {0};
uint8_t uart1_DMA_buf[uart_DMA_buf_len] = {0};
uint8_t uart2_DMA_buf[uart_DMA_buf_len] = {0};
uint8_t uart3_DMA_buf[uart_DMA_buf_len] = {0};
#define RX_ENABLE BIT0
#define UART_DMA_ENABLE BIT31
#define TX_INTR_ENABLE BIT31
#define Set_RxITNum_Mask 0xff00
#define Statu_RxNum_Mask (uint32_t)0xffff0000
/**
* @method UART_Buffer_Select
* @brief select UART buffer
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval NULL
*/
static uint8_t *UART_Buffer_Select(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
uint8_t *buffers[] = {uart0_DMA_buf, uart1_DMA_buf, uart2_DMA_buf, uart3_DMA_buf};
for (int i = 0; i < sizeof(UARTs) / sizeof(UARTs[0]); i++)
{
if ((void *)UARTs[i] == (void *)UARTx)
{
return buffers[i];
}
}
return NULL;
}
/**
* @method UART_DeInit
* @brief DeInit UART
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval None
*/
void UART_DeInit(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
UARTx->CTRL.reg = 0;
UARTx->RX_INT_LEN.reg = 0;
}
/**
* @method UART_Init
* @brief Initializes the UARTx peripheral according to
* the specified parameters.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param UART_InitStruct: pointer to a UART_InitTypeDef structure that
* contains the configuration information.
*/
void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct)
{
DMA_TypeDef *DMAx = NULL;
uint8_t *uartx_DMA_buf = NULL;
uint32_t temp_baudrate = 0;
_ASSERT(IS_UART(UARTx));
_ASSERT(IS_UART_RX_MODE(UART_InitStruct->RxMode));
_ASSERT(IS_UART_PARITY(UART_InitStruct->Parity));
_ASSERT(IS_UART_WORD_LENGTH(UART_InitStruct->DataBits));
_ASSERT(IS_UART_STOPBITS(UART_InitStruct->StopBits));
_ASSERT(IS_UART_FLOW_CTRL(UART_InitStruct->FlowCtrl));
_ASSERT(IS_UART_SMART_CARD(UART_InitStruct->SmartCard));
_ASSERT(IS_UART_COMM_MODE(UART_InitStruct->CommMode));
_ASSERT(IS_UART_BAUDRATE(UART_InitStruct->BaudRate));
DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
uartx_DMA_buf = UART_Buffer_Select(UARTx);
temp_baudrate = (48000000 / UART_InitStruct->BaudRate);
UART_DeInit(UARTx);
DMAx->DEST_ADDR.reg = (uint32_t)uartx_DMA_buf;
DMAx->LEN_LOW.bit.RX_LEN_L = uart_DMA_buf_len;
DMAx->CTRL.bit.LOOPBACK = 1;
DMAx->CTRL.bit.RESET = 1;
DMAx->CTRL.bit.RESET = 0;
UARTx->CTRL.bit.RX_EN = UART_InitStruct->RxMode;
UARTx->CTRL.bit.PARITY = UART_InitStruct->Parity;
UARTx->CTRL.bit.DATA_BITS = UART_InitStruct->DataBits;
UARTx->CTRL.bit.STOP_BITS = UART_InitStruct->StopBits;
UARTx->CTRL.bit.FLOW_CTRL = UART_InitStruct->FlowCtrl;
UARTx->CTRL.bit.SMART_CARD = UART_InitStruct->SmartCard;
UARTx->CTRL.bit.HDX_EN = UART_InitStruct->CommMode;
UARTx->CTRL.bit.RESET_BAUD = ENABLE;
UARTx->BAUD.bit.BAUD_RATE = temp_baudrate;
}
/**
* @method UART_StructInit
* @brief Fills each USART_InitStruct member with its default value.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
* which will be initialized.
* @retval None
*/
void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
{
UART_InitStruct->BaudRate = 9600;
UART_InitStruct->RxMode = MODE_RX_ENABLE;
UART_InitStruct->Parity = YC_PARITY_NONE;
UART_InitStruct->DataBits = DATABITS_8B;
UART_InitStruct->StopBits = STOPBITS_1;
UART_InitStruct->FlowCtrl = FLOWCTRL_NONE;
UART_InitStruct->SmartCard = SMARTCARD_DISABLE;
UART_InitStruct->CommMode = MODE_DUPLEX;
}
/**
* @method UART_ITConfig
* @brief Enable or disable the specified UART interrupt.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param UART_IT: specifies the UART interrupt sources
* This parameter can be one of the following values:
* @arg UART_IT_TX:interrupt trigger after send data completed.
* @arg UART_IT_RX:interrupt trigger when received data.
* @param NewState: new state of the specified UART interrupt
* This parameter can be ENABLE or DISABLE
*/
void UART_ITConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState)
{
_ASSERT(IS_UART(UARTx));
_ASSERT(IS_UART_IT(UART_IT));
if (UART_IT == UART_IT_TX)
{
UARTx->BAUD.bit.TX_INT_EN = NewState;
}
else if (UART_IT == UART_IT_RX)
{
UARTx->RX_INT_LEN.bit.VAL = NewState;
}
}
/**
* @method UART_SendData
* @brief UART Send One Data
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval None
*/
void UART_SendData(UART_TypeDef *UARTx, uint8_t Data)
{
_ASSERT(IS_UART(UARTx));
volatile uint8_t buf[1];
buf[0] = Data;
DMA_TypeDef *DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
DMAx->SRC_ADDR.reg = (uint32_t)buf;
DMAx->LEN_LOW.bit.TX_LEN_L = 1;
DMAx->CTRL.bit.START = 1;
while (DMAx->STATUS.bit.DONE != 1);
}
/**
* @method UART_SendBuf
* @brief Transmits datas via UART DMA, the function will return after datas is sent.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param buf: pointer to a buf that contains the data you want transmit.
* @param len: the buf length
* @retval None
*/
void UART_SendBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len)
{
_ASSERT(IS_UART(UARTx));
_ASSERT(NULL != buf);
_ASSERT(len < 0xfffff);
DMA_TypeDef *DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
DMAx->SRC_ADDR.reg = (uint32_t)buf;
DMAx->LEN_LOW.bit.TX_LEN_L = len & 0xffff;
DMAx->CTRL.bit.TX_LEN_H = len >> 16;
DMAx->CTRL.bit.START = 1;
while (DMAx->STATUS.bit.DONE != 1);
}
/**
* @method UART_ReceiveData
* @brief Receive single data through the USARTx peripheral.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval An one byte received data.
*/
uint8_t UART_ReceiveData(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return UARTx->RX_DATA.bit.VAL;
}
/**
* @method UART_ReceiveBuf
* @brief Receives datas through the UART DMA.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param buf: pointer to a buf that contains the data you want receive.
* @param len: the buf length, which size should be less than 20 bit (len < 0xfffff)
* @retval The length of received data before return.
*/
uint32_t UART_ReceiveBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len)
{
_ASSERT(IS_UART(UARTx));
_ASSERT(NULL != buf);
_ASSERT(len < 0xfffff);
uint32_t rcv_len = 0;
while ((UART_ReceiveDataLen(UARTx) > 0) && (rcv_len < len))
{
buf[rcv_len++] = UARTx->RX_DATA.bit.VAL;
}
return rcv_len;
}
/**
* @method UART_AutoFlowCtrlCmd
* @brief ENABLE or DISABLE UARTx auto flow control
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param NewState: ENABLE or DISABLE auto flow control
* @retval None
*/
void UART_AutoFlowCtrlCmd(UART_TypeDef *UARTx, FunctionalState NewState)
{
_ASSERT(IS_UART(UARTx));
UARTx->CTRL.bit.FLOW_CTRL = NewState;
}
/**
* @method UART_GetITIdentity
* @brief Get IT Identity
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval IT Identity
*/
uint8_t UART_GetITIdentity(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
//return (0 || (UARTx->BAUD.bit.TX_INT_EN) || (UARTx->RX_INT_LEN.bit.VAL));
if((UARTx->RX_INT_LEN.reg > 0)&& (UARTx->STATUS.bit.RX_ITEMS_L >=UARTx->RX_INT_LEN.reg))
{
return UART_IT_RX;
}
else if(UARTx->BAUD.bit.TX_INT_EN)
{
return UART_IT_TX;
}
return 0;
}
/**
* @method UART_IsRXFIFOFull
* @brief Check if the Rx fifo is full or not.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval TRUE: Rx fifo is full.
* FALSE: Rx fifo is not full
*/
Boolean UART_IsRXFIFOFull(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (Boolean)(UARTx->STATUS.bit.RX_FULL);
}
/**
* @method UART_IsRXFIFONotEmpty
* @brief Check if the Rx fifo is empty or not.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval TRUE: Rx fifo is not empty.
* FALSE: Rx fifo is empty
*/
Boolean UART_IsRXFIFONotEmpty(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (Boolean)(!(UARTx->STATUS.bit.RX_EMPTY));
}
/**
* @method UART_IsBusy
* @brief Check if the UARTx is busy or not.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval TRUE: UARTx is busy.
* FALSE: UARTx is not busy.
*/
Boolean UART_IsBusy(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (Boolean)(!(UARTx->STATUS.bit.RX_EMPTY));
}
/**
* @method UART_SetITTimeout
* @brief Sets the interruption time for serial port timeout.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param timeout: 0x00~0xff
* @retval None
*/
void UART_SetITTimeout(UART_TypeDef *UARTx, uint16_t timeout)
{
_ASSERT(IS_UART(UARTx));
UARTx->TIMEOUT_INT.reg = timeout;
}
/**
* @method UART_SetRxITNum
* @brief Set the number of uart receive data intterupt trigger
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param Bcnt: if the number of receive datas greater than Bcnt,interrupt trigger
* @retval None
*/
void UART_SetRxITNum(UART_TypeDef *UARTx, uint8_t Bcnt)
{
_ASSERT(IS_UART(UARTx));
UARTx->RX_INT_LEN.reg = Bcnt;
}
/**
* @method UART_ReceiveDataLen
* @brief Return the length of received data
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval Data len
*/
uint32_t UART_ReceiveDataLen(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (UARTx->STATUS.bit.RX_ITEMS_H << 16) + UARTx->STATUS.bit.RX_ITEMS_L;
}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c); 2006-2020, YICHIP Development Team
* @file yc_uart.h
* @brief source file for setting uart
*
* Change Logs:
* Date Author Version Notes
* 2020-11-06 wushengyan V1.0.0 the first version
*/
#ifndef __YC_UART_H__
#define __YC_UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "yc3122.h"
#include "system.h"
/**
* @defgroup UARTx
*/
#define IS_UART(UARTx) (((UARTx) == MUART0) ||\
((UARTx) == MUART1) ||\
((UARTx) == MUART2) ||\
((UARTx) == MUART3))
/**
* @defgroup UART_RxMode
*/
#define MODE_RX_ENABLE 1
#define MODE_RX_DISABLE 0
#define IS_UART_RX_MODE(MODE) (((MODE) == MODE_RX_ENABLE) ||\
((MODE) == MODE_RX_DISABLE))
/**
* @defgroup USART_Parity
*/
#define YC_PARITY_NONE 0
#define YC_PARITY_EVEN 0
#define YC_PARITY_ODD 1
#define IS_UART_PARITY(PARITY) (((PARITY) == YC_PARITY_NONE) ||\
((PARITY) == YC_PARITY_EVEN) ||\
((PARITY) == YC_PARITY_ODD))
/**
* @defgroup UART_DataBits
*/
#define DATABITS_8B 0
#define DATABITS_9B 1
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == DATABITS_8B) || \
((LENGTH) == DATABITS_9B))
/**
* @defgroup UART_Stop_Bits
*/
#define STOPBITS_1 0
#define STOPBITS_2 1
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == STOPBITS_1) || \
((STOPBITS) == STOPBITS_2) )
/**
* @defgroup UART_Hardware_Flow_Control
*/
#define FLOWCTRL_NONE 0
#define FLOWCTRL_ENABLE 1
#define IS_UART_FLOW_CTRL(CTRL) (((CTRL) == FLOWCTRL_NONE) || \
((CTRL) == FLOWCTRL_ENABLE))
/**
* @defgroup UART_Smart_Card_Control
*/
#define SMARTCARD_ENABLE 1
#define SMARTCARD_DISABLE 0
#define IS_UART_SMART_CARD(CTRL) (((CTRL) == SMARTCARD_ENABLE) || \
((CTRL) == SMARTCARD_DISABLE))
/**
* @defgroup UART_CommMode
*/
#define MODE_SINGLE_LINE 1
#define MODE_DUPLEX 0
#define IS_UART_COMM_MODE(MODE) (((MODE) == MODE_SINGLE_LINE) ||\
((MODE) == MODE_DUPLEX))
/**
* @defgroup USART_BaudRate
*/
#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0x5B8) &&\
((BAUDRATE) < 0x0044AA21))
/**
* @defgroup UART_Interrupt_Type_definition
*/
#define UART_IT_TX 0x01
#define UART_IT_RX 0x02
#define IS_UART_IT(ITx) (((ITx) == UART_IT_TX) || ((ITx) == UART_IT_RX))
typedef struct
{
uint8_t RxMode; /*!< Specifies wether the Receive or Transmit mode
is enabled or disabled. This parameter can be
a value of @ref UART_Mode */
uint8_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of
@ref UART_Parity @note When parity is enabled,
the computed parity is inserted at
the MSB position of the transmitted data
(9th bit when the word length is set to
9 data bits; 8th bit when the word length is
set to 8 data bits);. */
uint8_t DataBits; /*!< Specifies the number of data bits transmitted
or received in a frame. This parameter can be
a value of @ref UART_DataBits */
uint8_t StopBits; /*!< Specifies the number of stop bits transmitted.
parameter can be a value of @ref UART_Stop_Bits */
uint8_t FlowCtrl; /*!< Specifies wether the hardware flow control mode
is enabled or disabled. This parameter can be
a value of @ref UART_Hardware_Flow_Control */
uint8_t SmartCard;
uint8_t CommMode;
uint32_t BaudRate; /*!< This member configures the USART
communication baud rate. */
} UART_InitTypeDef;
void UART_DeInit(UART_TypeDef *UARTx);
void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
void UART_StructInit(UART_InitTypeDef *UART_InitStruct);
void UART_ITConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState);
void UART_SendData(UART_TypeDef *UARTx, uint8_t Data);
void UART_SendBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len);
uint8_t UART_ReceiveData(UART_TypeDef *UARTx);
uint32_t UART_ReceiveBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len);
void UART_AutoFlowCtrlCmd(UART_TypeDef *UARTx, FunctionalState NewState);
uint8_t UART_GetITIdentity(UART_TypeDef *UARTx);
Boolean UART_IsRXFIFOFull(UART_TypeDef *UARTx);
Boolean UART_IsRXFIFONotEmpty(UART_TypeDef *UARTx);
Boolean UART_IsBusy(UART_TypeDef *UARTx);
void UART_SetITTimeout(UART_TypeDef *UARTx, uint16_t timeout);
void UART_SetRxITNum(UART_TypeDef *UARTx, uint8_t Bcnt);
uint32_t UART_ReceiveDataLen(UART_TypeDef *UARTx);
#ifdef __cplusplus
}
#endif
#endif
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_wdt.c
* @brief This file provides all the WDT firmware functions.
*
* Change Logs:
* Date Author Version Notes
* 2021-01-04 yangzhengfeng V1.0.0 the first version
*/
#include "yc_wdt.h"
/**
* @brief Set WDT Clk Div
* @param Wdtclkdiv: Wdtclkdiv value equal 1 to 16
* @retval none
*/
void WDT_CLKDIV(uint32_t Wdtclkdiv)
{
_ASSERT(IS_WDT_CLKDI(Wdtclkdiv));
MWDT->CONFIG.bit.CLK_DIV = Wdtclkdiv;
}
/**
* @brief Set reload counter
* @param Reload: Reload counter equal to 2 to 31
* @retval none
*/
void WDT_SetReload(uint32_t Reload)
{
_ASSERT(IS_WDT_RELOAD(Reload));
MWDT->CONFIG.bit.RELOAD = Reload;
}
/**
* @brief Feed the watchdog function
* @param none
* @retval none
*/
void WDT_ReloadCounter(void)
{
MWDT->KICK.reg = COUNTER_RELOAD_KEY;
}
/**
* @brief Enable WDT
* @param none
* @retval none
*/
void WDT_Enable(void)
{
MWDT->CONFIG.bit.EN = ENABLE;
}
/**
* @brief Set WDT mode
* @param WDT_Mode : Select the following values :
* WDT_CPUReset
* WDT_Interrupt.
* @retval none
* @description If Select WDT_CPUReset Mode,the bit for WDT RESET will be set;if
* Select WDT_Interrupt the bit for WDT RESET will
*/
void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode)
{
_ASSERT(IS_WDT_MODE(WDT_Mode));
if(WDT_CPUReset == WDT_Mode)
{
MWDT->CONFIG.bit.MODE = WDT_CPUReset;
MRSTGEN->RST_EN.bit.WDT = ENABLE;
}
else if(WDT_Interrupt == WDT_Mode)
{
MWDT->CONFIG.bit.MODE = WDT_Interrupt;
MRSTGEN->RST_EN.bit.WDT = DISABLE;
}
}
/**
* @brief Get interrupt Status
* @param none
* @retval SET:interrupt ocuured.
*/
uint8_t WDT_GetITStatus(void)
{
uint16_t ret;
ret = MWDT->IRQ_STATUS.bit.STATE;
return ret ;
}
/**
* @brief Clear interrupt
* @param none
* @retval none
*/
void WDT_ClearITPendingBit(void)
{
MWDT->CLEAR.reg = 1;
}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

66
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_wdt.h
* @brief This file provides all the WDT firmware functions.
*
* Change Logs:
* Date Author Version Notes
* 2021-01-04 yangzhengfeng V1.0.0 the first version
*/
#ifndef __YC_WDT_H__
#define __YC_WDT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "yc3122.h"
#include "system.h"
typedef enum
{
WDT_CPUReset = 0,
WDT_Interrupt,
} WDT_ModeTypeDef;
#define WDTCLKDIV_1 0x00
#define WDTCLKDIV_2 0x01
#define WDTCLKDIV_3 0x02
#define WDTCLKDIV_4 0x03
#define WDTCLKDIV_5 0x04
#define WDTCLKDIV_6 0x05
#define WDTCLKDIV_7 0x06
#define WDTCLKDIV_8 0x07
#define WDTCLKDIV_9 0x08
#define WDTCLKDIV_10 0x09
#define WDTCLKDIV_11 0x0A
#define WDTCLKDIV_12 0x0B
#define WDTCLKDIV_13 0x0c
#define WDTCLKDIV_14 0x0D
#define WDTCLKDIV_15 0x0E
#define WDTCLKDIV_16 0x0F
/**************the value of feed dog************/
#define COUNTER_RELOAD_KEY 0x5937
#define ITSTATUS 0x01
#define IS_WDT_CLKDI(wdtclkdiv) (wdtclkdiv < 16)
#define IS_WDT_RELOAD(load) (load <= 0x1f)
#define IS_WDT_MODE(mode) ((mode == WDT_CPUReset) || (mode == WDT_Interrupt))
void WDT_CLKDIV(uint32_t Wdtclkdiv);
void WDT_SetReload(uint32_t Reload);
void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode);
void WDT_ClearITPendingBit(void);
void WDT_Enable(void);
void WDT_ReloadCounter(void);
uint8_t WDT_GetITStatus(void);
#ifdef __cplusplus
}
#endif
#endif /*__YC_WDT_H__*/
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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