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arm926内容整理

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This commit is contained in:
shaojinchun
2019-03-14 15:45:20 +08:00
parent 377bbdc833
commit 159def753f
8 changed files with 399 additions and 340 deletions
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1
libcpu/arm/arm926/context_gcc.S
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@@ -10,6 +10,7 @@
#define NOINT 0xC0
.text
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */

44
libcpu/arm/arm926/cpuport.c
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@@ -23,30 +23,30 @@ rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
: "r"(bit) \
: "memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
: "r"(bit) \
: "memory");
}
#endif
@@ -152,7 +152,7 @@ void rt_hw_cpu_reset()
rt_kprintf("Restarting system...\n");
machine_reset();
while(1); /* loop forever and wait for reset to happen */
while (1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
@@ -206,21 +206,7 @@ int __rt_ffs(int value)
#elif defined(__GNUC__) || defined(__ICCARM__)
int __rt_ffs(int value)
{
register rt_uint32_t x;
if (value == 0)
return value;
__asm
(
"rsb %[temp], %[val], #0\n"
"and %[temp], %[temp], %[val]\n"
"clz %[temp], %[temp]\n"
"rsb %[temp], %[temp], #32\n"
:[temp] "=r"(x)
:[val] "r"(value)
);
return x;
return __builtin_ffs(value);
}
#endif

41
libcpu/arm/arm926/machine.c Normal file
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@@ -0,0 +1,41 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2018-02-08 RT-Thread the first version
*/
#include <rthw.h>
#include <rtthread.h>
RT_WEAK void machine_reset(void)
{
rt_kprintf("reboot system...\n");
rt_hw_interrupt_disable();
while (1);
}
RT_WEAK void machine_shutdown(void)
{
rt_kprintf("shutdown...\n");
rt_hw_interrupt_disable();
while (1);
}

40
libcpu/arm/arm926/mmu.c
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@@ -140,7 +140,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
while(ptr < buffer + size)
while (ptr < buffer + size)
{
__asm volatile { MCR p15, 0, ptr, c7, c14, 1 }
ptr += CACHE_LINE_SIZE;
@@ -211,18 +211,18 @@ void mmu_setttbase(register rt_uint32_t i)
* set by page table entry
*/
value = 0;
asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
value = 0x55555555;
asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
asm volatile("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
asm volatile("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
}
void mmu_set_domain(register rt_uint32_t i)
{
asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
asm volatile("mcr p15,0, %0, c3, c0, 0": :"r"(i));
}
void mmu_enable()
@@ -321,7 +321,7 @@ void mmu_disable_alignfault()
void mmu_clean_invalidated_cache_index(int index)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
asm volatile("mcr p15, 0, %0, c7, c14, 2": :"r"(index));
}
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -330,9 +330,9 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
while(ptr < buffer + size)
while (ptr < buffer + size)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
asm volatile("mcr p15, 0, %0, c7, c14, 1": :"r"(ptr));
ptr += CACHE_LINE_SIZE;
}
@@ -347,7 +347,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
while (ptr < buffer + size)
{
asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr));
ptr += CACHE_LINE_SIZE;
}
@@ -361,7 +361,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
while (ptr < buffer + size)
{
asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr));
ptr += CACHE_LINE_SIZE;
}
@@ -369,19 +369,19 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
void mmu_invalidate_tlb()
{
asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
asm volatile("mcr p15, 0, %0, c8, c7, 0": :"r"(0));
}
void mmu_invalidate_icache()
{
asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0));
}
void mmu_invalidate_dcache_all()
{
asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
asm volatile("mcr p15, 0, %0, c7, c6, 0": :"r"(0));
}
#endif
@@ -389,10 +389,10 @@ void mmu_invalidate_dcache_all()
/* level1 page table */
#if defined(__ICCARM__)
#pragma data_alignment=(16*1024)
static volatile rt_uint32_t _page_table[4*1024];
static volatile rt_uint32_t _page_table[4 * 1024];
#else
static volatile rt_uint32_t _page_table[4*1024] \
__attribute__((aligned(16*1024)));
static volatile rt_uint32_t _page_table[4 * 1024] \
__attribute__((aligned(16 * 1024)));
#endif
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
@@ -401,11 +401,11 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
volatile rt_uint32_t *pTT;
volatile int nSec;
int i = 0;
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
for(i=0; i<=nSec; i++)
pTT = (rt_uint32_t *)_page_table + (vaddrStart >> 20);
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
for (i = 0; i <= nSec; i++)
{
*pTT = attr |(((paddrStart>>20)+i)<<20);
*pTT = attr | (((paddrStart >> 20) + i) << 20);
pTT++;
}
}

5
libcpu/arm/arm926/mmu.h
View File

@@ -5,6 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-02-08 RT-Thread the first version
*/
#ifndef __MMU_H__
@@ -45,5 +46,7 @@ struct mem_desc
};
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size);
void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
#endif

2
libcpu/arm/arm926/stack.c
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@@ -38,7 +38,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
stk = (rt_uint32_t *)stack_addr;
*(--stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */

515
libcpu/arm/arm926/start_gcc.S
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File diff suppressed because it is too large Load Diff

91
libcpu/arm/arm926/trap.c
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@@ -41,14 +41,18 @@ struct rt_hw_register
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
};
static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
{
rt_exception_hook = exception_handle;
}
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register (struct rt_hw_register *regs)
void rt_hw_show_register(struct rt_hw_register *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
@@ -74,6 +78,13 @@ void rt_hw_show_register (struct rt_hw_register *regs)
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
{
if (rt_exception_hook != RT_NULL)
{
rt_err_t result;
result = rt_exception_hook(regs);
if (result == RT_EOK) return;
}
rt_hw_show_register(regs);
rt_kprintf("undefined instruction\n");
@@ -96,6 +107,13 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
{
if (rt_exception_hook != RT_NULL)
{
rt_err_t result;
result = rt_exception_hook(regs);
if (result == RT_EOK) return;
}
rt_hw_show_register(regs);
rt_kprintf("software interrupt\n");
@@ -112,6 +130,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
{
if (rt_exception_hook != RT_NULL)
{
rt_err_t result;
result = rt_exception_hook(regs);
if (result == RT_EOK) return;
}
rt_hw_show_register(regs);
rt_kprintf("prefetch abort\n");
@@ -133,6 +158,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
{
if (rt_exception_hook != RT_NULL)
{
rt_err_t result;
result = rt_exception_hook(regs);
if (result == RT_EOK) return;
}
rt_hw_show_register(regs);
rt_kprintf("data abort\n");
@@ -153,55 +185,26 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
{
if (rt_exception_hook != RT_NULL)
{
rt_err_t result;
result = rt_exception_hook(regs);
if (result == RT_EOK) return;
}
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
}
extern struct rt_irq_desc irq_desc[];
extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
void rt_hw_trap_irq()
extern void rt_interrupt_dispatch(void);
void rt_hw_trap_irq(void)
{
rt_isr_handler_t isr_func;
rt_uint32_t irq;
void *param;
/* get irq number */
irq = rt_hw_interrupt_get_active(INT_IRQ);
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(INT_IRQ, irq);
#ifdef RT_USING_INTERRUPT_INFO
irq_desc[irq].counter ++;
#endif
rt_interrupt_dispatch();
}
void rt_hw_trap_fiq()
void rt_hw_trap_fiq(void)
{
rt_isr_handler_t isr_func;
rt_uint32_t irq;
void *param;
/* get irq number */
irq = rt_hw_interrupt_get_active(INT_FIQ);
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(INT_FIQ, irq);
#ifdef RT_USING_INTERRUPT_INFO
irq_desc[irq].counter ++;
#endif
rt_interrupt_dispatch();
}