[bsp/phytium] add phytium bsp to support e2000 bootup with smp (#6566)

add phytium board (E2000) bsp
support usart
support SMP with demo

bsp/phytium/.gitignore

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+*.dis

bsp/phytium/README.md

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+
+# PHYTIUM BSP 说明
+
+## 简介
+
+本文档为基于 RT-THREAD 的 Phytium 系列 CPU 相关 BSP 说明。
+
+本文的主要内容如下:
+
+- BSP 简介
+- 移植支持情况
+- 如何在 Ubuntu/Windows 环境下使用此 BSP
+- 如何进行编译与实验
+- 维护人信息
+- 注意事项
+
+
+## BSP简介
+
+- 飞腾芯片产品具有谱系全、性能高、生态完善、自主化程度高等特点，目前主要包括高性能服务器CPU（飞腾腾云S系列）、高效能桌面CPU（飞腾腾锐D系列）、高端嵌入式CPU（飞腾腾珑E系列）和飞腾套片四大系列，为从端到云的各型设备提供核心算力支撑。
+
+
+
+- 本BSP目前支持飞腾腾锐D系列、飞腾腾珑E系列 相关CPU,基于 Phytium-Standalone-SDK 进行开发。开发者能够使用
+
+- 本BSP 支持Phytium系列CPU 工作在 aarch32/aarch64 两种执行状态 ，开发者能够根据自己的应用场景灵活选择CPU 工作状态。
+
+
+
+## 移植支持情况
+
+| **片上外设**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| UART              |     支持     | uart1 打印输出|
+
+| **芯片**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| E2000D              |     支持     | 支持SMP |
+| E2000Q              |     支持     | 支持SMP |
+| E2000S              |     支持     | |
+
+
+##  如何在Ubuntu/Windows 环境下使用此BSP
+
+
+### Ubuntu 环境
+
+1. 根据 [Linux x86_64 SDK安装方法](https://gitee.com/phytium_embedded/phytium-standalone-sdk/blob/release/doc/reference/usr/install_linux_x86_64.md) 中1.1  - 1.2 节中介绍，先安装 SDK 编译环境
+2. 参考[RT-Thread/env](https://github.com/RT-Thread/env) 中Tutorial 在ubuntu 环境下安装 env 环境
+3. 在编译环境下执行 ```source ~/.env/env.sh```
+4. 以aarch32 执行状态为例，```cd bsp/phytium/aarch32```
+
+
+### Windows 环境
+
+1. 根据[Windows 10 SDK安装方法](https://gitee.com/phytium_embedded/phytium-standalone-sdk/blob/release/doc/reference/usr/install_windows.md)，安装 SDK 编译环境，编辑新建 Windows 环境变量 AARCH32_CROSS_PATH 和 AARCH64_CROSS_PATH
+2. 参考[RT-Thread/env](https://github.com/RT-Thread/env) 中Tutorial 在 Windows 环境下解压 env 压缩包
+3. 以aarch32 执行状态为例，```cd bsp/phytium/aarch32```
+4. 使用 export_project.py 导出 BSP 工程到其他目录进行开发
+5. 使用 RT-Studio 导入 BSP 工程进行开发
+
+
+## 如何进行编译与实验
+
+### 编译说明
+
+- [AARCH32](./aarch32/README.md)
+- [AARCH64](./aarch64/README.md)
+
+###  烧写及执行
+
+#### Ubuntu 环境配置 tftp 服务
+
+- 在开发环境`host`侧安装`tftp`服务
+
+```
+sudo apt-get install tftp-hpa tftpd-hpa
+sudo apt-get install xinetd
+```
+
+- 新建 tftboot 目录, 以`/mnt/d/tftboot`为例, 此目录应与项目编译脚本makefile中的USR_BOOT_DIR一致, 并确保 tftboot 目录有执行权限`chmod 777 /**/tftboot`
+
+- 配置主机 tftpboot 服务, 新建并配置文件`/etc/xinetd.d/tftp`
+
+```
+# /etc/xinetd.d/tftp
+
+server tftp
+{
+  socket_type = dgram
+  protocol = udp
+  wait = yes
+  user = root
+  server =  /usr/sbin/in.tftpd
+  server_args = -s /mnt/d/tftboot
+  disable = no
+  per_source = 11
+  cps = 100 2
+  flags = IPv4
+}
+```
+
+- 启动主机`tftp`服务，生成默认配置
+
+```
+$ sudo service tftpd-hpa start
+```
+
+- 修改主机`tftp`配置，指向`tftboot`目录
+  修改/etc/default/tftpd-hpa
+
+```
+$ sudo nano /etc/default/tftpd-hpa
+# /etc/default/tftpd-hpa
+
+TFTP_USERNAME="tftp"
+TFTP_DIRECTORY="/mnt/d/tftboot"
+TFTP_ADDRESS=":69"
+TFTP_OPTIONS="-l -c -s"
+```
+
+- 重启主机`tftp`服务
+
+```
+$ sudo service tftpd-hpa restart
+```
+
+- 测试主机`tftp`服务的可用性
+  > 登录`tftp`服务，获取`tftboot`目录下的一个文件
+
+```
+$ tftp 192.168.4.50
+tftp> get test1234
+tftp> q
+```
+
+#### Windows环境下配置 tftp 服务
+
+- 下载Tftpd64 工具 ，并安装Tftpd64 工具
+
+![输入图片说明](./figures/tftp32_srv.png)
+
+- 之后每次使用前，进入Windows服务，手动将一下服务打开
+
+![输入图片说明](./figures/config_tftp32.png)
+
+#### 利用uboot 上tftp 服务加载镜像
+
+- 进入`u-boot`界面，输入如下指令，配置开发板ip，`host`侧ip和网关地址
+  ```
+  setenv ipaddr 192.168.4.20  
+  setenv serverip 192.168.4.50 
+  setenv gatewayip 192.168.4.1 
+  ```
+- 将编译好的elf 或者bin 文件拷贝至Tftpd64所设置文件夹下
+- 随后烧录的文件到开发板，输入以下指令
+  
+  ```
+  tftpboot 0x90100000 rtthread.elf
+  bootelf -p 0x90100000
+  ```
+
+### 运行结果
+
+![运行结果](./figures/result.png)
+
+
+## 维护人信息
+
+- huanghe:  huanghe@phytium.com.cn
+- zhugengyu:  zhugengyu@phytium.com.cn

bsp/phytium/aarch32/Kconfig

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+mainmenu "RT-Thread Project Configuration"
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "../."
+
+config STANDALONE_DIR
+    string
+    option env="STANDALONE_DIR"
+    default ".././libraries/standalone"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$BSP_DIR/libraries/drivers/Kconfig"
+
+config PHYTIUM_ARCH_AARCH32
+    bool
+    select ARCH_ARM_CORTEX_A
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select RT_USING_GIC_V3
+    select TARGET_ARMV8_AARCH32
+    select USE_AARCH64_L1_TO_AARCH32
+    default y
+
+menu "Standalone Setting"
+    config TARGET_ARMV8_AARCH32
+        bool "Armv8 Aarch32"
+        default y
+    
+    config USE_AARCH64_L1_TO_AARCH32
+        bool
+        prompt "Use Aarch64 L1 to Aarch32 code"
+        default y
+        help
+            Use the Aarch64 to Aarch32 mode function
+    
+    source "$STANDALONE_DIR/board/Kconfig"
+    source "$STANDALONE_DIR/drivers/Kconfig"
+    source "$STANDALONE_DIR/common/Kconfig"
+
+endmenu
+

bsp/phytium/aarch32/README.md

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+
+# AARCH32 工作模式使用
+
+- 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
+
+
+## 1. 如何选择芯片
+
+- Windows Env 环境下
+
+```shell
+    menuconfig
+```
+
+- Linux 环境下
+
+```shell
+    scons --menuconfig
+```
+
+开发者通过以下选择进行配置
+
+```
+Standalone Setting > Board Configuration > Chip 
+```
+
+![](./figures/chip_select.png)
+![](./figures/phytium_cpu_select.png)
+
+## 2. 如何选择驱动
+
+
+```shell
+    scons --menuconfig
+```
+
+开发者通过以下选项进行驱动的使能
+
+```
+Hardware Drivers > On-chip Peripheral Drivers
+```
+
+![](./figures/select_driver.png)
+
+
+## 3. 开启SDK中内部调试信息
+
+
+```shell
+    scons --menuconfig
+```
+
+开发者通过以下选项进行调试信息等级的设置
+
+![](./figures/select_debug_info.png)
+
+
+
+## 4. 编译程序
+
+```shell
+    scons -c
+    scons
+```
+
+- 完成编译之后目录下将会生成以下几个文件
+
+```
+rtthread_a32.bin
+rtthread_a32.elf
+rtthread_a32.map
+```
+
+## 5. 打包导出工程源代码
+
+
+- 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
+```
+python ./export_project.py -n=phytium-a32 -o=D:/proj/rt-thread-e2000/phytium-a32
+```
+
+![](./figures/export_project.png)
+
+
+- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR 
+> env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
+
+```
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config STANDALONE_DIR
+    string
+    option env="STANDALONE_DIR"
+    default "libraries/standalone"
+```
+
+- 输入 menuconfig 和 scons 完成编译
+
+
+## 6. 将工程导入 RT-Studio
+
+- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
+- 设置 BSP 工程的交叉编译链后进行后续开发
+
+![](./figures/import_project.png)

bsp/phytium/aarch32/SConscript

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+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/phytium/aarch32/SConstruct

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+import os
+import sys
+import rtconfig
+
+IS_EXPORTED = False
+
+# setup RT-Thread Root Path
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.getcwd() + '/../../..'
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+if RTT_ROOT == 'rt-thread':
+    IS_EXPORTED = True # if kenrel and bsp has been exported by export_project.py
+
+# setup Phytium BSP Root Path
+if IS_EXPORTED:
+    BSP_ROOT = '.'
+else:
+    BSP_ROOT = RTT_ROOT + '/bsp/phytium'
+
+TARGET = 'rtthread_a32.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('BSP_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+if not IS_EXPORTED: # if project is not exported, libraries and board need to manually add
+    # include libraries
+    objs.extend(SConscript(os.path.join(BSP_ROOT + '/libraries', 'SConscript')))
+
+    # include board
+    objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
+

bsp/phytium/aarch32/applications/SConscript

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+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/phytium/aarch32/applications/main.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe       first commit
+ *
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+#ifdef RT_USING_SMP
+
+struct rt_thread test_core[RT_CPUS_NR];
+static char *core_thread_name[8] =
+{
+    "core0_test",
+    "core1_test",
+    "core2_test",
+    "core3_test",
+    "core4_test",
+    "core5_test",
+    "core6_test",
+    "core7_test"
+};
+static rt_uint8_t core_stack[RT_CPUS_NR][1024];
+
+static void demo_core_thread(void *parameter)
+{
+    rt_base_t level;
+    while (1)
+    {
+        /* code */
+        level = rt_cpus_lock();
+        rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id());
+        rt_cpus_unlock(level);
+        rt_thread_mdelay(2000000);
+    }
+}
+
+void demo_core(void)
+{
+    rt_ubase_t i;
+    rt_ubase_t cpu_id = 0;
+    for (i = 0; i < RT_CPUS_NR; i++)
+    {
+        cpu_id = i;
+        rt_thread_init(&test_core[i],
+                       core_thread_name[i],
+                       demo_core_thread,
+                       RT_NULL,
+                       &core_stack[i],
+                       1024,
+                       20,
+                       32);
+
+        rt_thread_control(&test_core[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id);
+        rt_thread_startup(&test_core[i]);
+    }
+}
+#endif
+
+int main(void)
+{
+#ifdef RT_USING_SMP
+    demo_core();
+#endif
+    return RT_EOK;
+}
+

bsp/phytium/aarch32/boot/SConscript

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+from building import *
+
+cwd  = GetCurrentDir()
+src  = Glob('*.S') + Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('AARCH32-BOOT', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/phytium/aarch32/boot/aarch32_boot.S

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ * 
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe       first commit 
+ *
+ */
+ 
+.global _boot
+.set FPEXC_EN,		0x40000000		/* FPU enable bit, (1 << 30) */
+.org 0
+.text
+
+.section .boot,"ax"
+
+/* switch from aarch64-el2 to aarch32-el1 */
+_boot:
+Startup_Aarch32:
+    .long 0xd5384240 	/* mrs	x0, currentel                      */
+    .long 0xd342fc00 	/* lsr	x0, x0, #2                         */
+    .long 0x92400400 	/* and	x0, x0, #0x3                       */
+    .long 0xf1000c1f 	/* cmp	x0, #0x3                           */
+    .long 0x540003a1 	/* b.ne	1d0080c4 <el2_mode>                */
+
+el3_mode:
+    .long 0xd53ecca0 	/* mrs	x0, s3_6_c12_c12_5 - ICC_SRE_EL3   */
+    .long 0xb2400c00 	/* orr	x0, x0, #0xf                       */
+    .long 0xd51ecca0 	/* msr	s3_6_c12_c12_5, x0                 */
+    .long 0xd5033fdf 	/* isb                                     */
+    .long 0xd53cc9a0 	/* mrs	x0, s3_4_c12_c9_5 - ICC_SRE_EL2    */
+    .long 0xb2400c00 	/* orr	x0, x0, #0xf                       */
+    .long 0xd51cc9a0 	/* msr	s3_4_c12_c9_5, x0                  */
+    .long 0xd5033fdf 	/* isb                                     */
+    .long 0xd538cca0 	/* mrs	x0, s3_0_c12_c12_5 - ICC_SRE_EL1   */
+    .long 0xb2400000 	/* orr	x0, x0, #0x1                       */
+    .long 0xd518cca0 	/* msr	s3_0_c12_c12_5, x0                 */
+    .long 0xd5033fdf 	/* isb                                     */
+
+    .long 0xd2803620 	/* mov	x0, #0x1b1                         */
+    .long 0xd51e1100 	/* msr	scr_el3, x0                        */
+    .long 0xd2867fe0 	/* mov	x0, #0x33ff                        */
+    .long 0xd51c1140 	/* msr	cptr_el2, x0                       */
+    .long 0xd2810000 	/* mov	x0, #0x800                         */
+    .long 0xf2a61a00 	/* movk	x0, #0x30d0, lsl #16               */
+    .long 0xd5181000 	/* msr	sctlr_el1, x0                      */
+    .long 0x910003e0 	/* mov	x0, sp                             */
+    .long 0xd51c4100 	/* msr	sp_el1, x0                         */
+    .long 0xd53ec000 	/* mrs	x0, vbar_el3                       */
+    .long 0xd518c000 	/* msr	vbar_el1, x0                       */
+    .long 0xd2803a60 	/* mov	x0, #0x1d3                         */
+    .long 0xd51e4000 	/* msr	spsr_el3, x0                       */
+    .long 0x10000500 	/* adr	x0, 1d008158 <el1_mode>            */
+    .long 0xd51e4020 	/* msr	elr_el3, x0                        */
+    .long 0xd69f03e0 	/* eret                                    */
+
+el2_mode:
+    .long 0xd53cc9a0 	/* mrs	x0, s3_4_c12_c9_5 - ICC_SRE_EL2    */
+    .long 0xb2400c00 	/* orr	x0, x0, #0xf                       */
+    .long 0xd51cc9a0 	/* msr	s3_4_c12_c9_5, x0                  */
+    .long 0xd5033fdf 	/* isb                                     */
+    .long 0xd538cca0 	/* mrs	x0, s3_0_c12_c12_5 - ICC_SRE_EL1   */
+    .long 0xb2400000 	/* orr	x0, x0, #0x1                       */
+    .long 0xd518cca0 	/* msr	s3_0_c12_c12_5, x0                 */
+    .long 0xd5033fdf 	/* isb                                     */
+    .long 0xd53ce100 	/* mrs	x0, cnthctl_el2                    */
+    .long 0xb2400400 	/* orr	x0, x0, #0x3                       */
+    .long 0xd51ce100 	/* msr	cnthctl_el2, x0                    */
+    .long 0xd51ce07f 	/* msr	cntvoff_el2, xzr                   */
+    .long 0xd5380000 	/* mrs	x0, midr_el1                       */
+    .long 0xd53800a1 	/* mrs	x1, mpidr_el1                      */
+    .long 0xd51c0000 	/* msr	vpidr_el2, x0                      */
+    .long 0xd51c00a1 	/* msr	vmpidr_el2, x1                     */
+    .long 0xd2867fe0 	/* mov	x0, #0x33ff                        */
+    .long 0xd51c1140 	/* msr	cptr_el2, x0                       */
+    .long 0xd51c117f 	/* msr	hstr_el2, xzr                      */
+    .long 0xd2a00600 	/* mov	x0, #0x300000                      */
+    .long 0xd5181040 	/* msr	cpacr_el1, x0                      */
+    .long 0xd2800000 	/* mov	x0, #0x0                           */
+    .long 0xb2630000 	/* orr	x0, x0, #0x20000000                */
+    .long 0xd51c1100 	/* msr	hcr_el2, x0                        */
+    .long 0xd53c1100 	/* mrs	x0, hcr_el2                        */
+    .long 0xd2810000 	/* mov	x0, #0x800                         */
+    .long 0xf2a61a00 	/* movk	x0, #0x30d0, lsl #16               */
+    .long 0xd5181000 	/* msr	sctlr_el1, x0                      */
+    .long 0x910003e0 	/* mov	x0, sp                             */
+    .long 0xd51c4100 	/* msr	sp_el1, x0                         */
+    .long 0xd53cc000 	/* mrs	x0, vbar_el2                       */
+    .long 0xd518c000 	/* msr	vbar_el1, x0                       */
+    .long 0xd2803a60 	/* mov	x0, #0x1d3                         */
+    .long 0xd51c4000 	/* msr	spsr_el2, x0                       */
+    .long 0x10000060 	/* adr	x0, 1d008158 <el1_mode>            */
+    .long 0xd51c4020 	/* msr	elr_el2, x0                        */
+    .long 0xd69f03e0 	/* eret                                    */
+
+el1_mode:
+    mov      r0, #0
+    mov      r1, #0
+    mov      r2, #0
+    mov      r3, #0
+    mov      r4, #0
+    mov      r5, #0
+    mov      r6, #0
+    mov      r7, #0
+    mov      r8, #0
+    mov      r9, #0
+    mov      r10, #0
+    mov      r11, #0
+    mov      r12, #0
+    mcr      p15, 0, r0, c1, c0, 0  /* reset control register */
+    isb
+
+    /* enable vfp, therefore f_prink workable */
+    vmrs	r1, FPEXC			/* read the exception register */
+    orr	    r1,r1, #FPEXC_EN	/* set VFP enable bit, leave the others in orig state */
+    vmsr	FPEXC, r1			/* write back the exception register */
+
+    bl      system_vectors      /* jump to libcpu/arm/cortex-a/vector_gcc.S */
+

bsp/phytium/aarch32/export_project.py

@@ -0,0 +1,37 @@
+import os
+import shutil
+import argparse
+
+parser = argparse.ArgumentParser()
+parser.description='please enter two parameters <project-name> and <export-path> ...'
+parser.add_argument("-n", "--name", help="project name", type=str, default="phytium-a32")
+parser.add_argument("-o", "--output", help="export path",  type=str, default="./phytium-a32")
+args = parser.parse_args()
+
+print('=== Exporting Phytium BSP for RT-Studio ====')
+
+board_src_path = os.path.abspath(r'../board')
+librs_src_path = os.path.abspath(r'../libraries')
+
+board_dst_path = os.path.abspath(r'./board')
+librs_dst_path = os.path.abspath(r'./libraries')
+
+print(' Copying BSP board from {} to {}'.format(board_src_path, board_dst_path))
+print(' Copying BSP libraries from {} to {}'.format(librs_src_path, librs_dst_path))
+
+if os.path.exists(board_dst_path):
+    shutil.rmtree(board_dst_path)
+
+if os.path.exists(librs_dst_path):
+    shutil.rmtree(librs_dst_path)
+
+shutil.copytree(board_src_path, board_dst_path)
+shutil.copytree(librs_src_path, librs_dst_path)
+
+os.system('scons --dist-ide --project-name={} --project-path={}'.format(args.name, args.output))
+
+if os.path.exists(board_dst_path):
+    shutil.rmtree(board_dst_path)
+
+if os.path.exists(librs_dst_path):
+    shutil.rmtree(librs_dst_path)

bsp/phytium/aarch32/link.lds

@@ -0,0 +1,116 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+ENTRY(_boot)
+
+SECTIONS
+{
+    . = 0x80100000;
+
+    .text :
+    {
+
+        *(.boot)
+        . = ALIGN(64);
+        
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        /* new GCC version uses .init_array */
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16 * 1024);
+    .l1_page_table :
+    {
+        __l1_page_table_start = .;
+        . += 16K;
+    }
+
+    . = ALIGN(8);
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(8);
+    __bss_start = .;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    .heap :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        . += 0x400;
+        __HeapLimit = .;
+        __heap_limit = .; /* Add for _sbrk */
+    }
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}

bsp/phytium/aarch32/rtconfig.h

@@ -0,0 +1,261 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define SYSTEM_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50000
+#define ARCH_ARM
+#define RT_USING_CPU_FFS
+#define ARCH_ARM_CORTEX_A
+#define RT_USING_GIC_V3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define PHYTIUM_ARCH_AARCH32
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH32
+#define USE_AARCH64_L1_TO_AARCH32
+
+/* Board Configuration */
+
+#define TARGET_E2000Q
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_GIC
+#define ENABLE_GICV3
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+#define USE_DEFAULT_INTERRUPT_CONFIG
+#define INTERRUPT_ROLE_MASTER
+
+#endif

bsp/phytium/aarch32/rtconfig.py

@@ -0,0 +1,68 @@
+import os
+import rtconfig
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-a'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# only support GNU GCC compiler.
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/usr/lib/arm-none-eabi/bin'
+if os.getenv('AARCH32_CROSS_PATH'):
+    EXEC_PATH = os.getenv('AARCH32_CROSS_PATH')
+    print('EXEC_PATH = {}'.format(EXEC_PATH))
+else:
+    print('AARCH32_CROSS_PATH not found')
+
+BUILD = 'debug'
+
+LIBPATH = EXEC_PATH + r'/../lib'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    DEVICE = ' -g -DGUEST  -ffreestanding  -Wextra -g -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -march=armv8-a -fdiagnostics-color=always'
+
+    # CFLAGS = DEVICE + ' -Wall'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c'+ DEVICE + ' -fsingle-precision-constant  -fno-builtin -x assembler-with-cpp -D__ASSEMBLY__'    
+    LINK_SCRIPT = 'link.lds'
+    LFLAGS = DEVICE + '  -Wl,--gc-sections,-Map=rtthread_a32.map,-cref,-u,system_vectors'+\
+                      ' -T %s' % LINK_SCRIPT
+
+    CPATH = ''
+    LPATH = LIBPATH
+
+    # generate debug info in all cases
+    AFLAGS += ' -gdwarf-2'
+    CFLAGS += ' -g -gdwarf-2'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a32.bin\n' +\
+                  SIZE + ' $TARGET \n'

bsp/phytium/aarch32/sdkconfig.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: sdkconfig.h
+ * Date: 2022-10-13 15:53:46
+ * LastEditTime: 2022-10-13 15:53:46
+ * Description:  This file is for
+ *
+ * Modify History:
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ */
+
+#ifndef SDK_CONFIG_H__
+#define SDK_CONFIG_H__
+
+#include "rtconfig.h"
+
+
+/* arch */
+
+#if defined(TARGET_ARMV8_AARCH32)
+    #define CONFIG_TARGET_ARMV8_AARCH32
+#endif
+
+#if defined(USE_AARCH64_L1_TO_AARCH32)
+    #define CONFIG_USE_AARCH64_L1_TO_AARCH32
+#endif
+
+/* board */
+
+/*  E2000 */
+
+#if defined(TARGET_E2000)
+    #define CONFIG_TARGET_E2000
+#endif
+
+
+/* debug */
+
+#ifdef LOG_VERBOS
+    #define CONFIG_LOG_VERBOS
+#endif
+
+#ifdef LOG_ERROR
+    #define CONFIG_LOG_ERROR
+#endif
+
+#ifdef LOG_WARN
+    #define CONFIG_LOG_WARN
+#endif
+
+#ifdef LOG_INFO
+    #define CONFIG_LOG_INFO
+#endif
+
+#ifdef LOG_DEBUG
+    #define CONFIG_LOG_DEBUG
+#endif
+
+#ifdef BOOTUP_DEBUG_PRINTS
+    #define CONFIG_BOOTUP_DEBUG_PRINTS
+#endif
+
+#endif

bsp/phytium/aarch64/Kconfig

@@ -0,0 +1,55 @@
+mainmenu "RT-Thread Project Configuration"
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "../."
+
+config STANDALONE_DIR
+    string
+    option env="STANDALONE_DIR"
+    default ".././libraries/standalone"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$BSP_DIR/libraries/drivers/Kconfig"
+
+config BSP_USING_GIC
+    bool
+    default y
+    config BSP_USING_GICV3
+        bool
+        default y
+
+config PHYTIUM_ARCH_AARCH64
+    bool
+    select ARCH_ARMV8
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_CPU_64BIT
+    select TARGET_ARMV8_AARCH64
+    default y
+
+menu "Standalone Setting"
+    config TARGET_ARMV8_AARCH64
+        bool "Armv8 Aarch64"
+        default y
+
+    source "$STANDALONE_DIR/board/Kconfig"
+    source "$STANDALONE_DIR/drivers/Kconfig"
+    source "$STANDALONE_DIR/common/Kconfig"
+
+endmenu
+
+
+

bsp/phytium/aarch64/README.md

@@ -0,0 +1,121 @@
+<!--
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: README.md
+ * Date: 2022-10-17 15:16:12
+ * LastEditTime: 2022-10-17 15:16:12
+ * Description:  This file is for 
+ * 
+ * Modify History: 
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+-->
+
+# AARCH64 工作模式使用
+
+- 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
+
+## 1. 如何选择芯片
+
+```shell
+    scons --menuconfig
+```
+
+开发者通过以下选择进行配置
+
+```
+Standalone Setting > Board Configuration > Chip 
+```
+
+![](./figures/chip_select.png)
+![](./figures/phytium_cpu_select.png)
+
+## 2. 如何选择驱动
+
+
+```shell
+    scons --menuconfig
+```
+
+开发者通过以下选项进行驱动的使能
+
+```
+Hardware Drivers Config > On-chip Peripheral Drivers
+```
+
+![](./figures/select_driver.png)
+
+
+## 3. 开启SDK中内部调试信息
+
+
+```shell
+    scons --menuconfig
+```
+
+开发者通过以下选项进行调试信息等级的设置
+
+![](./figures/select_debug_info.png)
+
+
+
+## 4. 编译程序
+
+```shell
+    scons -c
+    scons
+```
+
+- 完成编译之后目录下将会生成以下几个文件
+
+```
+rtthread_a64.bin
+rtthread_a64.elf
+rtthread_a64.map
+```
+
+## 5. 打包导出工程源代码
+
+
+- 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
+```
+python ./export_project.py -n=phytium-a64 -o=D:/proj/rt-thread-e2000/phytium-a64
+```
+
+![](./figures/export_project.png)
+
+
+- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR 
+> env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
+
+```
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config STANDALONE_DIR
+    string
+    option env="STANDALONE_DIR"
+    default "libraries/standalone"
+```
+
+- 输入 menuconfig 和 scons 完成编译
+
+
+## 6. 将工程导入 RT-Studio
+
+- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
+- 设置 BSP 工程的交叉编译链后进行后续开发
+
+![](./figures/import_project.png)

bsp/phytium/aarch64/SConscript

@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/phytium/aarch64/SConstruct

@@ -0,0 +1,58 @@
+import os
+import sys
+import rtconfig
+
+IS_EXPORTED = False
+
+# setup RT-Thread Root Path
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.getcwd() + '/../../..'
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+if RTT_ROOT == 'rt-thread':
+    IS_EXPORTED = True # if kenrel and bsp has been exported by export_project.py
+
+# setup Phytium BSP Root Path
+if IS_EXPORTED:
+    BSP_ROOT = '.'
+else:
+    BSP_ROOT = RTT_ROOT + '/bsp/phytium'
+
+TARGET = 'rtthread_a64.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('BSP_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+if not IS_EXPORTED: # if project is not exported, libraries and board need to manually add
+    # include libraries
+    objs.extend(SConscript(os.path.join(BSP_ROOT + '/libraries', 'SConscript')))
+
+    # include board
+    objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
+

bsp/phytium/aarch64/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/phytium/aarch64/applications/main.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+#ifdef RT_USING_SMP
+
+struct rt_thread test_core[RT_CPUS_NR];
+static char *core_thread_name[8] =
+{
+    "core0_test",
+    "core1_test",
+    "core2_test",
+    "core3_test",
+    "core4_test",
+    "core5_test",
+    "core6_test",
+    "core7_test"
+};
+static rt_uint8_t core_stack[RT_CPUS_NR][1024];
+
+static void demo_core_thread(void *parameter)
+{
+    rt_base_t level;
+    while (1)
+    {
+        /* code */
+        level = rt_cpus_lock();
+        rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id());
+        rt_cpus_unlock(level);
+        rt_thread_mdelay(2000000);
+    }
+}
+
+void demo_core(void)
+{
+    rt_ubase_t i;
+    rt_ubase_t cpu_id = 0;
+    for (i = 0; i < RT_CPUS_NR; i++)
+    {
+        cpu_id = i;
+        rt_thread_init(&test_core[i],
+                       core_thread_name[i],
+                       demo_core_thread,
+                       RT_NULL,
+                       &core_stack[i],
+                       1024,
+                       20,
+                       32);
+
+        rt_thread_control(&test_core[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id);
+        rt_thread_startup(&test_core[i]);
+    }
+}
+#endif
+
+int main(void)
+{
+#ifdef RT_USING_SMP
+    demo_core();
+#endif
+    return RT_EOK;
+}
+

bsp/phytium/aarch64/export_project.py

@@ -0,0 +1,37 @@
+import os
+import shutil
+import argparse
+
+parser = argparse.ArgumentParser()
+parser.description='please enter two parameters <project-name> and <export-path> ...'
+parser.add_argument("-n", "--name", help="project name", type=str, default="phytium-a64")
+parser.add_argument("-o", "--output", help="export path",  type=str, default="./phytium-a64")
+args = parser.parse_args()
+
+print('=== Exporting Phytium BSP for RT-Studio ====')
+
+board_src_path = os.path.abspath(r'../board')
+librs_src_path = os.path.abspath(r'../libraries')
+
+board_dst_path = os.path.abspath(r'./board')
+librs_dst_path = os.path.abspath(r'./libraries')
+
+print(' Copying BSP board from {} to {}'.format(board_src_path, board_dst_path))
+print(' Copying BSP libraries from {} to {}'.format(librs_src_path, librs_dst_path))
+
+if os.path.exists(board_dst_path):
+    shutil.rmtree(board_dst_path)
+
+if os.path.exists(librs_dst_path):
+    shutil.rmtree(librs_dst_path)
+
+shutil.copytree(board_src_path, board_dst_path)
+shutil.copytree(librs_src_path, librs_dst_path)
+
+os.system('scons --dist-ide --project-name={} --project-path={}'.format(args.name, args.output))
+
+if os.path.exists(board_dst_path):
+    shutil.rmtree(board_dst_path)
+
+if os.path.exists(librs_dst_path):
+    shutil.rmtree(librs_dst_path)

bsp/phytium/aarch64/link.lds

@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x80100000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+    . = ALIGN(4);
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        /* new GCC version uses .init_array */
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    }
+    . = ALIGN(4);
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        . = ALIGN(32);
+        PROVIDE(__bss_end = .);
+    }
+
+    . = ALIGN(4);
+    .heap :
+    {
+        PROVIDE(__heap_start = .);
+        . = ALIGN(8);
+        PROVIDE(end = .);
+    } 
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = SIZEOF(.bss);

bsp/phytium/aarch64/rtconfig.h

@@ -0,0 +1,260 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+#define SYSTEM_THREAD_STACK_SIZE 4096
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50000
+#define ARCH_CPU_64BIT
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 4096
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define BSP_USING_GIC
+#define BSP_USING_GICV3
+#define PHYTIUM_ARCH_AARCH64
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH64
+
+/* Board Configuration */
+
+#define TARGET_E2000Q
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+
+#endif

bsp/phytium/aarch64/rtconfig.py

@@ -0,0 +1,52 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' 
+if os.getenv('AARCH64_CROSS_PATH'):
+    EXEC_PATH = os.getenv('AARCH64_CROSS_PATH')
+    print('EXEC_PATH = {}'.format(EXEC_PATH))
+else:
+    print('AARCH64_CROSS_PATH not found')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'aarch64-none-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds -fdiagnostics-color=always'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a64.dis\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a64.bin\n' + SIZE + ' $TARGET \n'

bsp/phytium/aarch64/sdkconfig.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: sdkconfig.h
+ * Date: 2022-10-09 15:04:36
+ * LastEditTime: 2022-10-09 15:04:37
+ * Description:  This file is for
+ *
+ * Modify History:
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ */
+
+#ifndef SDK_CONFIG_H__
+#define SDK_CONFIG_H__
+
+#include "rtconfig.h"
+
+/* board */
+
+/*  E2000 */
+
+#if defined(TARGET_E2000)
+    #define CONFIG_TARGET_E2000
+#endif
+
+#if defined(TARGET_E2000Q)
+    #define CONFIG_TARGET_E2000Q
+#endif
+
+#if defined(TARGET_ARMV8_AARCH64)
+    #define CONFIG_TARGET_ARMV8_AARCH64
+#endif
+
+/* debug */
+
+#ifdef LOG_VERBOS
+    #define CONFIG_LOG_VERBOS
+#endif
+
+#ifdef LOG_ERROR
+    #define CONFIG_LOG_ERROR
+#endif
+
+#ifdef LOG_WARN
+    #define CONFIG_LOG_WARN
+#endif
+
+#ifdef LOG_INFO
+    #define CONFIG_LOG_INFO
+#endif
+
+#ifdef LOG_DEBUG
+    #define CONFIG_LOG_DEBUG
+#endif
+
+#ifdef BOOTUP_DEBUG_PRINTS
+    #define CONFIG_BOOTUP_DEBUG_PRINTS
+#endif
+
+#endif

bsp/phytium/board/SConscript

@@ -0,0 +1,25 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.S')
+src	+= Glob('*.c')
+
+if GetDepend(['TARGET_E2000']):
+    if GetDepend(['TARGET_E2000Q']):
+        src	+= Glob(cwd + '/e2000/q/parameters.c')
+    elif GetDepend(['TARGET_E2000D']):
+        src	+= Glob(cwd + '/e2000/d/parameters.c')
+    elif GetDepend(['TARGET_E2000S']):
+        src	+= Glob(cwd + '/e2000/s/parameters.c')
+
+if GetDepend(['TARGET_F2000_4']):
+    src	+= Glob(cwd + '/d2000/parameters.c')
+
+if GetDepend(['TARGET_D2000']):
+    src	+= Glob(cwd + '/ft2004/parameters.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/phytium/board/board.c

@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ * 2022-10-26  zhugengyu    support aarch64
+ *
+ */
+
+#include "rtconfig.h"
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <mmu.h>
+
+#include <gicv3.h>
+#if defined(TARGET_ARMV8_AARCH64)
+    #include <psci.h>
+    #include <gtimer.h>
+    #include <cpuport.h>
+#else
+    #include "fgeneric_timer.h" /* for aarch32 */
+#endif
+#include <interrupt.h>
+#include <board.h>
+
+#include "fdebug.h"
+#include "fprintk.h"
+#include "fearly_uart.h"
+#include "fcpu_info.h"
+#include "fpsci.h"
+
+#define LOG_DEBUG_TAG "BOARD"
+#define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
+#define BSP_LOG_WARN(format, ...)  FT_DEBUG_PRINT_W(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
+#define BSP_LOG_INFO(format, ...)  FT_DEBUG_PRINT_I(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
+#define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/* mmu config */
+struct mem_desc platform_mem_desc[] =
+#if defined(TARGET_E2000)
+{
+    {
+        0x00U,
+        0x00U + 0x40000000U,
+        0x00U,
+        DEVICE_MEM
+    },
+    {
+        0x40000000U,
+        0x40000000U + 0x10000000U,
+        0x40000000U,
+        DEVICE_MEM
+    },
+    {
+        0x50000000U,
+        0x50000000U + 0x30000000U,
+        0x50000000U,
+        DEVICE_MEM
+    },
+    {
+        0x80000000U,
+        0xffffffffU,
+        0x80000000U,
+        NORMAL_MEM
+    },
+#if defined(TARGET_ARMV8_AARCH64)
+    {
+        0x1000000000,
+        0x1000000000 + 0x1000000000,
+        0x1000000000,
+        DEVICE_MEM
+    },
+    {
+        0x2000000000,
+        0x2000000000 + 0x2000000000,
+        0x2000000000,
+        NORMAL_MEM
+    },
+#endif
+};
+#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
+{
+    {
+        0x80000000,
+        0xFFFFFFFF,
+        0x80000000,
+        DDR_MEM
+    },
+    {
+        0, //< QSPI
+        0x1FFFFFFF,
+        0,
+        DEVICE_MEM
+    },
+    {
+        0x20000000, //<! LPC
+        0x27FFFFFF,
+        0x20000000,
+        DEVICE_MEM
+    },
+    {
+        FT_DEV_BASE_ADDR, //<! Device register
+        FT_DEV_END_ADDR,
+        FT_DEV_BASE_ADDR,
+        DEVICE_MEM
+    },
+    {
+        0x30000000, //<! debug
+        0x39FFFFFF,
+        0x30000000,
+        DEVICE_MEM
+    },
+    {
+        0x3A000000, //<! Internal register space in the on-chip network
+        0x3AFFFFFF,
+        0x3A000000,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_CONFIG_BASEADDR,
+        FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
+        FT_PCI_CONFIG_BASEADDR,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_IO_CONFIG_BASEADDR,
+        FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
+        FT_PCI_IO_CONFIG_BASEADDR,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_MEM32_BASEADDR,
+        FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
+        FT_PCI_MEM32_BASEADDR,
+        DEVICE_MEM
+    }
+#if defined(TARGET_ARMV8_AARCH64)
+    {
+        0x1000000000,
+        0x1000000000 + 0x1000000000,
+        0x1000000000,
+        DEVICE_MEM
+    },
+    {
+        0x2000000000,
+        0x2000000000 + 0x2000000000,
+        0x2000000000,
+        NORMAL_MEM
+    },
+#endif
+};
+#endif
+
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
+
+
+
+#if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
+
+/* aarch64 use kernel gtimer */
+
+void idle_wfi(void)
+{
+    asm volatile("wfi");
+}
+
+#else /* AARCH32 */
+
+static rt_uint32_t timerStep;
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    GenericTimerCompare(timerStep);
+    rt_tick_increase();
+}
+
+int rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(GENERIC_TIMER_NS_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(GENERIC_TIMER_NS_IRQ_NUM);
+    timerStep = GenericTimerFrequecy();
+    timerStep /= RT_TICK_PER_SECOND;
+
+    GenericTimerCompare(timerStep);
+    GenericTimerInterruptEnable();
+    GenericTimerStart();
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+#endif
+
+
+#ifdef RT_USING_SMP
+    void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
+#endif
+
+/**
+ * This function will initialize hardware board
+ */
+void rt_hw_board_init(void)
+{
+
+    /* mmu init */
+#if defined(TARGET_ARMV8_AARCH64)
+    rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
+    rt_hw_mmu_init();
+#endif
+
+    /* interrupt init */
+#if defined(TARGET_ARMV8_AARCH64)
+    f_printk("aarch64 interrupt init \r\n");
+#else
+    f_printk("aarch32 interrupt init \r\n");
+
+    extern int rt_hw_cpu_id(void);
+
+    u32 cpu_id, cpu_offset = 0;
+    GetCpuId(&cpu_id);
+    f_printk("cpu_id is %d \r\n", cpu_id);
+
+#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
+    cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
+#endif
+    f_printk("cpu_offset  is %d \r\n", cpu_offset);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
+
+#if defined(TARGET_E2000Q)
+
+#if RT_CPUS_NR == 2
+    f_printk("arm_gic_redist_address_set is 2 \r\n");
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
+#elif RT_CPUS_NR == 3
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
+#elif RT_CPUS_NR == 4
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + GICV3_RD_OFFSET, 3);
+#endif
+
+#else
+
+#if RT_CPUS_NR == 2
+    f_printk("arm_gic_redist_address_set is 2 \r\n");
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+#elif RT_CPUS_NR == 3
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
+#elif RT_CPUS_NR == 4
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
+    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
+#endif
+
+#endif
+
+#endif
+    rt_hw_interrupt_init();
+
+
+    /* gtimer init  */
+#if defined(TARGET_ARMV8_AARCH64)
+    rt_hw_gtimer_init();
+#endif
+
+    /* compoent init */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+    /* shell init */
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* init memory pool */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+#ifdef RT_USING_SMP
+    /* install IPI handle */
+    rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
+    rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
+    rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
+#endif
+}
+
+
+static void ft_reset(void)
+{
+    PsciCpuReset();
+}
+MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
+
+/*@}*/

bsp/phytium/board/board.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "fparameters.h"
+#include "phytium_cpu.h"
+
+#if defined(__CC_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+    extern int __bss_end;
+    #define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+
+#define HEAP_END (void *)(0x80000000 + 1024 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/phytium/board/d2000/parameters.c

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include "rtconfig.h"
+#include <rtthread.h>
+
+#include "fcpu_info.h"
+#include "fparameters.h"
+
+
+/**
+ * @name: GetCpuMaskToAffval
+ * @msg:  Convert information in cpu_mask to cluster_ID and target_list
+ * @param {u32} *cpu_mask is each bit of cpu_mask represents a selected CPU, for example, 0x3 represents core0 and CORE1 .
+ * @param {u32} *cluster_id is information about the cluster in which core resides ,format is
+ * |--------[bit31-24]-------[bit23-16]-------------[bit15-8]-----------[bit7-0]
+ * |--------Affinity level3-----Affinity level2-----Affinity level1-----Affinity level0
+ * @param {u32} *target_list  is core mask in cluster
+ * @return {u32} 0 indicates that the conversion was not successful , 1 indicates that the conversion was successful
+ */
+u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
+{
+    if (*cpu_mask == 0)
+    {
+        return 0;
+    }
+
+    *target_list = 0;
+    *cluster_id = 0;
+
+    if (*cpu_mask & 0x3)
+    {
+        if ((*cpu_mask & 0x3) == 0x3)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x1))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0x3;
+    }
+    else if (*cpu_mask & 0xc)
+    {
+        *cluster_id = 0x100;
+        if ((*cpu_mask & 0xc) == 0xc)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x4))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0xc;
+    }
+    else if (*cpu_mask & 0x30)
+    {
+        *cluster_id = 0x200;
+        if ((*cpu_mask & 0x30) == 0x30)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x10))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0x30;
+    }
+    else if (*cpu_mask & 0xc0)
+    {
+        *cluster_id = 0x300;
+        if ((*cpu_mask & 0xc0) == 0xc0)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x40))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0xc0;
+    }
+    else
+    {
+        *cpu_mask = 0;
+        return 0;
+    }
+
+    return 1;
+}

bsp/phytium/board/e2000/d/parameters.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include "rtconfig.h"
+#include <rtthread.h>
+
+#include "fcpu_info.h"
+#include "fparameters.h"
+
+u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
+{
+    if (*cpu_mask == 0)
+    {
+        return 0;
+    }
+
+    *target_list = 0;
+    *cluster_id = 0;
+
+    if (*cpu_mask & 0x3)
+    {
+        *cluster_id = 0x200;
+        if ((*cpu_mask & 0x3) == 0x3)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x1))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0x3; /* clear all mask */
+    }
+    else
+    {
+        *cpu_mask = 0;
+        return 0;
+    }
+
+    return 1;
+}

bsp/phytium/board/e2000/q/parameters.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include "rtconfig.h"
+#include <rtthread.h>
+
+#include "fcpu_info.h"
+#include "fparameters.h"
+
+
+/**
+ * @name: GetCpuMaskToAffval
+ * @msg:  参考 GetCpuMaskToAffval 进行参数的重新定义 ，两个小核心定义的id 为0，1 ，两个大核的id 为 2，3
+ * @return {*}
+ * @note:
+ * @param {u32} *cpu_mask
+ * @param {u32} *cluster_id
+ * @param {u32} *target_list
+ */
+u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
+{
+    if (*cpu_mask == 0)
+    {
+        return 0;
+    }
+
+    *target_list = 0;
+    *cluster_id = 0;
+
+    if (*cpu_mask & 0x4)
+    {
+        *target_list = 1;
+        *cpu_mask &= ~0x4;
+    }
+    else if (*cpu_mask & 0x8)
+    {
+        *cluster_id = 0x100;
+        *target_list = 1;
+        *cpu_mask &= ~0x8;
+    }
+    else if (*cpu_mask & 0x3)
+    {
+        *cluster_id = 0x200;
+        if ((*cpu_mask & 0x3) == 0x3)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x4))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0x3;
+    }
+    else
+    {
+        *cpu_mask = 0;
+        return 0;
+    }
+
+    return 1;
+}

bsp/phytium/board/e2000/s/parameters.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include "rtconfig.h"
+#include <rtthread.h>
+
+#include "fcpu_info.h"
+#include "fparameters.h"
+
+u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
+{
+    if (*cpu_mask == 0)
+    {
+        return 0;
+    }
+
+    *target_list = 0;
+    *cluster_id = 0;
+
+    if (*cpu_mask & 0x1)
+    {
+        *target_list = 1;
+        *cluster_id = 0x200;
+        *cpu_mask &= ~0x1;
+    }
+    else
+    {
+        *cpu_mask = 0;
+        return 0;
+    }
+
+    return 1;
+}

bsp/phytium/board/ft2004/parameters.c

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include "rtconfig.h"
+#include <rtthread.h>
+
+#include "fcpu_info.h"
+#include "fparameters.h"
+
+
+u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
+{
+    if (*cpu_mask == 0)
+    {
+        return 0;
+    }
+
+    *target_list = 0;
+    *cluster_id = 0;
+
+    if (*cpu_mask & 0x3)
+    {
+        if ((*cpu_mask & 0x3) == 0x3)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x1))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0x3;
+    }
+    else if (*cpu_mask & 0xc)
+    {
+        *cluster_id = 0x100;
+        if ((*cpu_mask & 0xc) == 0xc)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x4))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0xc;
+    }
+    else
+    {
+        *cpu_mask = 0;
+        return 0;
+    }
+
+    return 1;
+}

bsp/phytium/board/phytium_cpu.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#include "rtconfig.h"
+#include <rtthread.h>
+#include "gicv3.h"
+
+#include "fparameters.h"
+#include "fcpu_info.h"
+
+#include "phytium_cpu.h"
+
+int phytium_cpu_id_mapping(int cpu_id)
+{
+#if defined(TARGET_E2000Q)
+    switch (cpu_id)
+    {
+    case 0:
+        return 2;
+    case 1:
+        return 3;
+    case 2:
+        return 0;
+    case 3:
+        return 1;
+    default:
+        RT_ASSERT(0);
+        return 0;
+        break;
+    }
+#else
+    return (int)cpu_id;
+#endif
+}
+
+#if defined(TARGET_ARMV8_AARCH64)
+
+int phytium_cpu_id(void)
+{
+    FError ret;
+    u32 cpu_id;
+    ret = GetCpuId(&cpu_id);
+
+    if (ret != ERR_SUCCESS)
+    {
+        RT_ASSERT(0);
+    }
+    return phytium_cpu_id_mapping(cpu_id);
+};
+
+#else
+
+int rt_hw_cpu_id(void)
+{
+    FError ret;
+    u32 cpu_id;
+    ret = GetCpuId(&cpu_id);
+
+    if (ret != ERR_SUCCESS)
+    {
+        RT_ASSERT(0);
+    }
+
+    return phytium_cpu_id_mapping(cpu_id);
+};
+
+
+
+rt_uint64_t get_main_cpu_affval(void)
+{
+#if defined(TARGET_E2000Q)
+    return CORE2_AFF;
+#else
+    return CORE0_AFF;
+#endif
+}
+
+
+extern u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list);
+rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list)
+{
+    return GetCpuMaskToAffval(cpu_mask, cluster_id, target_list);
+}
+
+
+#ifdef RT_USING_SMP
+
+void send_core_isg(void)
+{
+    for (rt_size_t i = 0; i <= 0xf; i++)
+    {
+        /* code */
+        rt_kprintf("i %x \r\n", i);
+        arm_gic_send_affinity_sgi(0, 0, i, 0);
+        rt_thread_mdelay(100);
+    }
+}
+MSH_CMD_EXPORT(send_core_isg, send_core_isg);
+
+#endif
+
+
+#endif

bsp/phytium/board/phytium_cpu.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-10-26  huanghe      first commit
+ *
+ */
+
+#ifndef __PHYTIUM_CPU_H__
+#define __PHYTIUM_CPU_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "fparameters.h"
+
+#define ARM_GIC_MAX_NR 1
+#define MAX_HANDLERS 160
+#define GIC_IRQ_START 0
+#define GIC_ACK_INTID_MASK 0x000003ff
+
+
+rt_uint64_t get_main_cpu_affval(void);
+
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return GICV3_DISTRIBUTOR_BASEADDRESS;
+}
+
+#if defined(TARGET_ARMV8_AARCH64)
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_redist_base(void)
+{
+    extern int phytium_cpu_id(void);
+
+    s32 cpu_offset = 0;
+#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
+    cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
+#endif
+
+#if defined(TARGET_E2000Q)
+    u32 cpu_id = 0;
+    cpu_id = phytium_cpu_id();
+
+    switch (cpu_id)
+    {
+    case 0:
+    case 1:
+        cpu_offset = 2;
+        break;
+    case 2:
+    case 3:
+        cpu_offset = -2;
+    default:
+        break;
+    }
+#endif
+
+    rt_kprintf("offset  is %x\n",  cpu_offset);
+    return (GICV3_RD_BASEADDRESS + (cpu_offset) * GICV3_RD_OFFSET);
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    return 0U; /* unused in gicv3 */
+}
+
+#endif
+
+
+int phytium_cpu_id_mapping(int cpu_id);
+
+
+
+#endif // !