Merge branch 'RT-Thread:master' into hal

bsp/acm32f4xx-nucleo/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/acm32f4xx-nucleo/Kconfig

@@ -1,4 +1,4 @@
-mainmenu "RT-Thread Configuration"
+mainmenu "RT-Thread Project Configuration"
 
 config BSP_DIR
     string
@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../../.."
+    default "../.."
 
 config PKGS_DIR
     string
@@ -18,10 +18,5 @@ config PKGS_DIR
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 
-config SOC_ES32F0271LT
-    bool
-    select RT_USING_COMPONENTS_INIT
-    select RT_USING_USER_MAIN
-    default y
+source "$BSP_DIR/drivers/Kconfig"
 
-source "drivers/Kconfig"

bsp/acm32f4xx-nucleo/README.md

@@ -0,0 +1,56 @@
+# acm32f0x0板级支持包
+
+## 1. 简介
+
+ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
+
+|--------------------------|--------------------|
+|         硬件             |         描述       |
+| -------------------------|--------------------|
+|芯片型号                  | ACM32F4XX系列      |
+|CPU                       | ARM Cortex-M33     |
+|主频                      | 180MHz             |
+|片内SRAM                  | 192K               |
+|片内Flash                 | 512K               |
+|--------------------------|--------------------|
+
+具体型号及资源请参考上海航芯官方网站[ACM32F4](www.aisinochip.com/index.php/product/child1/id/219.html)。
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f4xx-nucleo`目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。
+
+## 3. 烧写及执行
+
+开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| ------------- | ------------ | ------------------------------------- |
+| GPIO          |     支持     | PA0, PA1... PF4 ---> PIN: 0, 1...83  |
+| UART          |     支持     |              UART1/UART2              |
+| LED           |     支持     |              LED1                     |
+
+## 5. 联系人信息
+
+维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
+
+## 6. 参考
+
+* 板子[数据手册][2]
+* 芯片[数据手册][3]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: www.aisinochip.com/index.php/product/detail/id/50.html
+  [3]: www.aisinochip.com/index.php/product/detail/id/50.html

bsp/acm32f4xx-nucleo/SConscript

@@ -1,9 +1,9 @@
 # for module compiling
 import os
-Import('RTT_ROOT')
+from building import *
 
+cwd  = GetCurrentDir()
 objs = []
-cwd = str(Dir('#'))
 list = os.listdir(cwd)
 
 for d in list:

bsp/acm32f4xx-nucleo/SConstruct

@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/acm32f4xx-nucleo/applications/SConscript

@@ -2,10 +2,10 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
-
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
 CPPPATH = [cwd, str(Dir('#'))]
+
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')

bsp/acm32f4xx-nucleo/applications/main.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-17     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <drivers/pin.h>
+
+#define LED_PIN_NUM    83     /* PF3 */
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN_NUM, PIN_LOW);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+        rt_pin_write(LED_PIN_NUM, PIN_HIGH);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+    }
+}

bsp/acm32f4xx-nucleo/drivers/Kconfig

@@ -0,0 +1,387 @@
+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_ACM32F403RET7
+
+    config SOC_ACM32F403KCU7
+    bool "SOC_ACM32F403KCU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403KEU7
+    bool "SOC_ACM32F403KEU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CCT7
+    bool "SOC_ACM32F403CCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CET7
+    bool "SOC_ACM32F403CET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RCT7
+    bool "SOC_ACM32F403RCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RET7
+    bool "SOC_ACM32F403RET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VCT7
+    bool "SOC_ACM32F403VCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VET7
+    bool "SOC_ACM32F403VET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+endchoice
+
+menu "ACM32F403RET7"
+    depends on SOC_ACM32F403RET7
+
+    config SOC_SRAM_START_ADDR
+        hex "sram start address"
+        default 0x20000000
+
+    config SOC_SRAM_SIZE
+        hex "sram size(KBytes)"
+        default 0xC0
+
+    config SOC_FLASH_START_ADDR
+        hex "EFlash Start Address"
+        default 0x00000000
+
+    config SOC_FLASH_SIZE
+        hex "EFlash Size(KBytes)"
+        default 0x8000
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menu "Hardware GPIO"
+        config BSP_USING_GPIO1
+            bool "Enable GPIOAB"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO2
+            bool "Enable GPIOCD"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO3
+            bool "Enable GPIOEF"
+            default y
+            select RT_USING_PIN
+    endmenu
+
+    config BSP_USING_ADC
+        bool "Enable ADC"
+        select RT_USING_ADC
+        default n
+
+    config BSP_USING_DAC
+        bool "Enable DAC"
+        select RT_USING_DAC
+        default n
+
+    menu "Hardware UART"
+        config BSP_USING_UART1
+            bool "Enable UART1 (PA9/PA10)"
+            default y
+            select RT_USING_SERIAL
+
+        config BSP_USING_UART2
+            bool "Enable UART2 (PA2/PA3)"
+            default y
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART2
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART2_TX_USING_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART3
+            bool "Enable UART3 (PC4/PC5)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART3
+            config BSP_UART3_RX_USING_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART3_TX_USING_DMA
+                bool "Enable UART3 TX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART4
+            bool "Enable UART4 (PC11/PC10)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART4
+            config BSP_UART4_RX_USING_DMA
+                bool "Enable UART4 RX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART4_TX_USING_DMA
+                bool "Enable UART4 TX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+    endmenu
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    config BSP_USING_LPUART
+        bool "Enable LPUART"
+        select RT_USING_UART
+        default n
+
+    menu "Hardware I2C"
+        config BSP_USING_I2C1
+            bool "Enable I2C1"
+            default n
+            select RT_USING_I2C
+        config BSP_USING_I2C2
+            bool "Enable I2C2"
+            default n
+            select RT_USING_I2C
+    endmenu
+
+    menu "Hardware I2S"
+        config BSP_USING_I2S1
+            bool "Enable I2S1"
+            default n
+            select RT_USING_I2S
+    endmenu
+
+    menu "Hardware CAN"
+        config BSP_USING_CAN1
+            bool "Enable CAN1"
+            default n
+            select RT_USING_CAN
+        config BSP_USING_CAN2
+            bool "Enable CAN2"
+            default n
+            select RT_USING_CAN
+    endmenu
+
+    menu "Hardware TIMER"
+        config BSP_USING_TIM1
+            bool "Enable Timer1"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM2
+            bool "Enable Timer2"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM3
+            bool "Enable Timer3"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM4
+            bool "Enable Timer4"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM6
+            bool "Enable Timer6"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM7
+            bool "Enable Timer7"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM14
+            bool "Enable Timer14"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM15
+            bool "Enable Timer15"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM16
+            bool "Enable Timer16"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM17
+            bool "Enable Timer17"
+            default n
+            select RT_USING_HWTIMER
+    endmenu
+
+    menu "Hardware WDT"
+        config BSP_USING_WDT
+            bool "Enable Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+        config BSP_USING_IWDT
+            bool "Enable Independent Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+    endmenu
+
+    config BSP_USING_LCD
+        bool "Enable LCD"
+        default n
+
+    menu "Hardware SPI"
+        config BSP_USING_SPI1
+            bool "Enable SPI1"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI1
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI2
+            bool "Enable SPI2"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI2
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                default n
+
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI3
+            bool "Enable SPI3"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI3
+            config BSP_SPI3_RX_USING_DMA
+                bool "Enable SPI3 RX DMA"
+                default n
+
+            config BSP_SPI3_TX_USING_DMA
+                bool "Enable SPI3 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI4
+            bool "Enable SPI4"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI4
+            config BSP_SPI4_RX_USING_DMA
+                bool "Enable SPI4 RX DMA"
+                default n
+
+            config BSP_SPI4_TX_USING_DMA
+                bool "Enable SPI4 TX DMA"
+                default n
+        endif
+    endmenu
+
+    menu "Hardware CRYPTO"
+        config BSP_USING_CRC
+            select RT_HWCRYPTO_USING_CRC
+            bool "Enable CRC"
+            default n
+            select RT_USING_HWCRYPTO
+        config BSP_USING_AES
+            select RT_HWCRYPTO_USING_AES
+            bool "Enable AES"
+            default n
+            select RT_USING_HWCRYPTO
+
+        config BSP_USING_HRNG
+            select RT_HWCRYPTO_USING_RNG
+            bool "Enable HRNG"
+            default n
+            select RT_USING_HWCRYPTO
+    endmenu
+
+    config BSP_USING_CMP
+        bool "Enable Analog Voltage Comparer"
+        default n
+
+    config BSP_USING_OPA
+        bool "Enable Operational Amplifier"
+        default n
+
+    config BSP_USING_TKEY
+        bool "Enable Touch Key"
+        select RT_USING_TOUCH
+        default n
+
+    config BSP_USING_RPMU
+        bool "Enable RTC PMU"
+        select RT_USING_PM
+        default n
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB
+        default n
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
+

bsp/acm32f4xx-nucleo/drivers/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
+

bsp/acm32f4xx-nucleo/drivers/board.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-25     AisinoChip   first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <rtdevice.h>
+
+#define SOC_SRAM_END_ADDR   (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
+
+extern int  rt_application_init(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+    #pragma section="HEAP"
+#else
+    extern int __bss_end;
+#endif
+
+extern void rt_hw_uart_init(void);
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial EVB board.
+ */
+void rt_hw_board_init(void)
+{
+    /* system init, clock, NVIC */
+    System_Init();
+
+    /* Configure the SysTick */
+    SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_HEAP
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
+#endif
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/acm32f4xx-nucleo/drivers/board.h

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-22     AisinoCip    add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtconfig.h>
+#include "ACM32Fxx_HAL.h"
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+  *
+  * STEP 1, define macro define related to the serial port opening based on the serial port number
+  *                 such as     #define BSP_USING_UATR1
+  *
+  * STEP 2, according to the corresponding pin of serial port, modify the related serial port information
+  *                 such as     #define UART1_TX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_RX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_TX_PIN        GPIO_PIN_X   ->   GPIO_PIN_9
+  *                             #define UART1_RX_PIN        GPIO_PIN_X   ->   GPIO_PIN_10
+  *
+  * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+  *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+  *
+  * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+  *                 such as     #define BSP_UART1_RX_USING_DMA
+  *
+  */
+
+#if defined(BSP_USING_UART1)
+    #define UART1_TX_PORT           GPIOA
+    #define UART1_RX_PORT           GPIOA
+    #define UART1_TX_PIN            GPIO_PIN_9
+    #define UART1_RX_PIN            GPIO_PIN_10
+
+    #if defined(BSP_UART1_RX_USING_DMA)
+        #define UART1_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART1_RX_DMA_RCC        BIT12
+        #define UART1_RX_DMA_IRQ        DMA_IRQn
+        #define UART1_RX_DMA_CHANNEL    0
+        #define UART1_RX_DMA_REQUEST    REQ6_UART1_RECV
+    #endif /* BSP_UART1_RX_USING_DMA */
+
+    #if defined(BSP_UART1_TX_USING_DMA)
+        #define UART1_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART1_TX_DMA_RCC        BIT12
+        #define UART1_TX_DMA_IRQ        DMA_IRQn
+        #define UART1_TX_DMA_CHANNEL    1
+        #define UART1_TX_DMA_REQUEST    REQ5_UART1_SEND
+    #endif /* BSP_UART1_TX_USING_DMA */
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+    #define UART2_TX_PORT           GPIOA
+    #define UART2_RX_PORT           GPIOA
+    #define UART2_TX_PIN            GPIO_PIN_2
+    #define UART2_RX_PIN            GPIO_PIN_3
+
+    #if defined(BSP_UART2_RX_USING_DMA)
+        #define UART2_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART2_RX_DMA_RCC        BIT12
+        #define UART2_RX_DMA_IRQ        DMA_IRQn
+        #define UART2_RX_DMA_CHANNEL    0
+        #define UART2_RX_DMA_REQUEST    REQ8_UART2_RECV
+    #endif /* BSP_UART2_RX_USING_DMA */
+
+    #if defined(BSP_UART2_TX_USING_DMA)
+        #define UART2_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART2_TX_DMA_RCC        BIT12
+        #define UART2_TX_DMA_IRQ        DMA_IRQn
+        #define UART2_TX_DMA_CHANNEL    1
+        #define UART2_TX_DMA_REQUEST    REQ7_UART2_SEND
+    #endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+    #define UART3_TX_PORT           GPIOB
+    #define UART3_RX_PORT           GPIOB
+    #define UART3_TX_PIN            GPIO_PIN_10
+    #define UART3_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART3_RX_USING_DMA)
+        #define UART3_RX_DMA_INSTANCE   DMA_Channel2
+        #define UART3_RX_DMA_RCC        BIT12
+        #define UART3_RX_DMA_IRQ        DMA_IRQn
+        #define UART3_RX_DMA_CHANNEL    2
+        #define UART3_RX_DMA_REQUEST    REQ29_UART3_RECV
+    #endif /* BSP_UART3_RX_USING_DMA */
+
+    #if defined(BSP_UART3_TX_USING_DMA)
+        #define UART3_TX_DMA_INSTANCE   DMA_Channel3
+        #define UART3_TX_DMA_RCC        BIT12
+        #define UART3_TX_DMA_IRQ        DMA_IRQn
+        #define UART3_TX_DMA_CHANNEL    3
+        #define UART3_TX_DMA_REQUEST    REQ27_UART3_SEND
+    #endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+    #define UART4_TX_PORT           GPIOC
+    #define UART4_RX_PORT           GPIOC
+    #define UART4_TX_PIN            GPIO_PIN_10
+    #define UART4_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART4_RX_USING_DMA)
+        #define UART4_RX_DMA_INSTANCE   DMA_Channel4
+        #define UART4_RX_DMA_RCC        BIT12
+        #define UART4_RX_DMA_IRQ        DMA_IRQn
+        #define UART4_RX_DMA_CHANNEL    4
+        #define UART4_RX_DMA_REQUEST    REQ46_UART4_RECV
+    #endif /* BSP_UART4_RX_USING_DMA */
+
+    #if defined(BSP_UART4_TX_USING_DMA)
+        #define UART4_TX_DMA_INSTANCE   DMA_Channel5
+        #define UART4_TX_DMA_RCC        BIT12
+        #define UART4_TX_DMA_IRQ        DMA_IRQn
+        #define UART4_TX_DMA_CHANNEL    5
+        #define UART4_TX_DMA_REQUEST    REQ45_UART4_SEND
+    #endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+/*-------------------------- UART CONFIG END --------------------------*/
+
+/* board configuration */
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+

bsp/acm32f4xx-nucleo/drivers/drv_gpio.c

@@ -0,0 +1,479 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-09-18     AisinoChip        first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+
+#ifdef RT_USING_PIN
+
+#define __ACM32_PIN(index, gpio, gpio_index)                                \
+    {                                                                       \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                            \
+    }
+
+#define __ACM32_PIN_RESERVE                                                 \
+    {                                                                       \
+        -1, 0, 0                                                            \
+    }
+
+/* ACM32 GPIO driver */
+struct pin_index
+{
+    int             index;
+    enum_GPIOx_t    gpio;
+    uint32_t        pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t         line;
+    EXTI_HandleTypeDef  handle;
+};
+
+static const struct pin_index pins[] =
+{
+#if defined(BSP_USING_GPIO1)
+    __ACM32_PIN(0,   A, 0),
+    __ACM32_PIN(1,   A, 1),
+    __ACM32_PIN(2,   A, 2),
+    __ACM32_PIN(3,   A, 3),
+    __ACM32_PIN(4,   A, 4),
+    __ACM32_PIN(5,   A, 5),
+    __ACM32_PIN(6,   A, 6),
+    __ACM32_PIN(7,   A, 7),
+    __ACM32_PIN(8,   A, 8),
+    __ACM32_PIN(9,   A, 9),
+    __ACM32_PIN(10,  A, 10),
+    __ACM32_PIN(11,  A, 11),
+    __ACM32_PIN(12,  A, 12),
+    __ACM32_PIN(13,  A, 13),
+    __ACM32_PIN(14,  A, 14),
+    __ACM32_PIN(15,  A, 15),
+    __ACM32_PIN(16,  B, 0),
+    __ACM32_PIN(17,  B, 1),
+    __ACM32_PIN(18,  B, 2),
+    __ACM32_PIN(19,  B, 3),
+    __ACM32_PIN(20,  B, 4),
+    __ACM32_PIN(21,  B, 5),
+    __ACM32_PIN(22,  B, 6),
+    __ACM32_PIN(23,  B, 7),
+    __ACM32_PIN(24,  B, 8),
+    __ACM32_PIN(25,  B, 9),
+    __ACM32_PIN(26,  B, 10),
+    __ACM32_PIN(27,  B, 11),
+    __ACM32_PIN(28,  B, 12),
+    __ACM32_PIN(29,  B, 13),
+    __ACM32_PIN(30,  B, 14),
+    __ACM32_PIN(31,  B, 15),
+#if defined(BSP_USING_GPIO2)
+    __ACM32_PIN(32,  C, 0),
+    __ACM32_PIN(33,  C, 1),
+    __ACM32_PIN(34,  C, 2),
+    __ACM32_PIN(35,  C, 3),
+    __ACM32_PIN(36,  C, 4),
+    __ACM32_PIN(37,  C, 5),
+    __ACM32_PIN(38,  C, 6),
+    __ACM32_PIN(39,  C, 7),
+    __ACM32_PIN(40,  C, 8),
+    __ACM32_PIN(41,  C, 9),
+    __ACM32_PIN(42,  C, 10),
+    __ACM32_PIN(43,  C, 11),
+    __ACM32_PIN(44,  C, 12),
+    __ACM32_PIN(45,  C, 13),
+    __ACM32_PIN(46,  C, 14),
+    __ACM32_PIN(47,  C, 15),
+    __ACM32_PIN(48,  D, 0),
+    __ACM32_PIN(49,  D, 1),
+    __ACM32_PIN(50,  D, 2),
+    __ACM32_PIN(51,  D, 3),
+    __ACM32_PIN(52,  D, 4),
+    __ACM32_PIN(53,  D, 5),
+    __ACM32_PIN(54,  D, 6),
+    __ACM32_PIN(55,  D, 7),
+    __ACM32_PIN(56,  D, 8),
+    __ACM32_PIN(57,  D, 9),
+    __ACM32_PIN(58,  D, 10),
+    __ACM32_PIN(59,  D, 11),
+    __ACM32_PIN(60,  D, 12),
+    __ACM32_PIN(61,  D, 13),
+    __ACM32_PIN(62,  D, 14),
+    __ACM32_PIN(63,  D, 15),
+#if defined(BSP_USING_GPIO3)
+    __ACM32_PIN(64,  E, 0),
+    __ACM32_PIN(65,  E, 1),
+    __ACM32_PIN(66,  E, 2),
+    __ACM32_PIN(67,  E, 3),
+    __ACM32_PIN(68,  E, 4),
+    __ACM32_PIN(69,  E, 5),
+    __ACM32_PIN(70,  E, 6),
+    __ACM32_PIN(71,  E, 7),
+    __ACM32_PIN(72,  E, 8),
+    __ACM32_PIN(73,  E, 9),
+    __ACM32_PIN(74,  E, 10),
+    __ACM32_PIN(75,  E, 11),
+    __ACM32_PIN(76,  E, 12),
+    __ACM32_PIN(77,  E, 13),
+    __ACM32_PIN(78,  E, 14),
+    __ACM32_PIN(79,  E, 15),
+    __ACM32_PIN(80,  F, 0),
+    __ACM32_PIN(81,  F, 1),
+    __ACM32_PIN(82,  F, 2),
+    __ACM32_PIN(83,  F, 3),
+    __ACM32_PIN(84,  F, 4),
+#endif /* defined(BSP_USING_GPIO3) */
+#endif /* defined(BSP_USING_GPIO2) */
+#endif /* defined(BSP_USING_GPIO1) */
+};
+
+static struct pin_irq_map pin_irq_map[] =
+{
+    {EXTI_LINE_0,  {0}},
+    {EXTI_LINE_1,  {0}},
+    {EXTI_LINE_2,  {0}},
+    {EXTI_LINE_3,  {0}},
+    {EXTI_LINE_4,  {0}},
+    {EXTI_LINE_5,  {0}},
+    {EXTI_LINE_6,  {0}},
+    {EXTI_LINE_7,  {0}},
+    {EXTI_LINE_8,  {0}},
+    {EXTI_LINE_9,  {0}},
+    {EXTI_LINE_10, {0}},
+    {EXTI_LINE_11, {0}},
+    {EXTI_LINE_12, {0}},
+    {EXTI_LINE_13, {0}},
+    {EXTI_LINE_14, {0}},
+    {EXTI_LINE_15, {0}},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
+}
+
+static int _pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = HAL_GPIO_ReadPin(index->gpio, index->pin);
+
+    return value;
+}
+
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.Pin = index->pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+
+    /* special PIN process */
+    __HAL_RTC_PC13_DIGIT();
+
+    HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+}
+
+#define     PIN2INDEX(pin)      ((pin) % 16)
+
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+    irqmap = &pin_irq_map[irqindex];
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStruct.Pin = index->pin;
+        GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+
+        irqmap->handle.u32_Line = irqmap->line;
+        irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT;
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            GPIO_InitStruct.Pull = GPIO_PULLUP;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            GPIO_InitStruct.Pull = GPIO_NOPULL;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING;
+            break;
+        }
+        HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+
+        irqmap->handle.u32_GPIOSel = pin / 16;
+
+        HAL_EXTI_SetConfigLine(&irqmap->handle);
+
+        pin_irq_enable_mask |= 1 << irqindex;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        if ((pin_irq_enable_mask & (1 << irqindex)) == 0)
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        EXTI->IENR &= ~irqmap->line;
+        EXTI->EENR &= ~irqmap->line;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _acm32_pin_ops =
+{
+    _pin_mode,
+    _pin_write,
+    _pin_read,
+    _pin_attach_irq,
+    _pin_dettach_irq,
+    _pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+void EXTI_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < 16; i++)
+    {
+        if (EXTI->PDR & pin_irq_map[i].line)
+        {
+            EXTI->PDR = pin_irq_map[i].line;
+            pin_irq_hdr(i);
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_PIN */
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf

@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds

@@ -0,0 +1,156 @@
+/*
+ * linker script for ACM32F4xx with GNU ld
+ */
+
+/* describes the location and size of blocks of memory in the target. */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
+}
+/* Program Entry, set to mark it as "used" and avoid gc */
+ENTRY(Reset_Handler)
+_system_stack_size = 0x800;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(8);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct

@@ -2,13 +2,14 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x00000000 0x00020000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x00020000  {  ; load address = execution address
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
+   .ANY (+XO)
   }
-  RW_IRAM1 0x20000000 0x00006000  {  ; RW data
+  RW_IRAM1 0x20000000 0x00030000  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

bsp/acm32f4xx-nucleo/drivers/uart_config.h

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_SERIAL)
+
+#if defined(BSP_USING_UART1)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                          \
+        .irq_type = UART1_IRQn,                                     \
+        .enable_id = EN_UART1,                                      \
+        .tx_port  = UART1_TX_PORT,                                  \
+        .rx_port  = UART1_RX_PORT,                                  \
+        .tx_pin   = UART1_TX_PIN,                                   \
+        .rx_pin   = UART1_RX_PIN,                                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+        .channel  = UART2_RX_DMA_CHANNEL,                           \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+        .channel  = UART2_TX_DMA_CHANNEL,                           \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                          \
+        .irq_type = UART2_IRQn,                                     \
+        .enable_id = EN_UART2,                                      \
+        .tx_port  = UART2_TX_PORT,                                  \
+        .rx_port  = UART2_RX_PORT,                                  \
+        .tx_pin   = UART2_TX_PIN,                                   \
+        .rx_pin   = UART2_RX_PIN,                                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+        .channel  = UART3_RX_DMA_CHANNEL,                           \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+        .channel  = UART3_TX_DMA_CHANNEL,                           \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                          \
+        .irq_type = UART3_IRQn,                                     \
+        .enable_id = EN_UART3,                                      \
+        .tx_port  = UART3_TX_PORT,                                  \
+        .rx_port  = UART3_RX_PORT,                                  \
+        .tx_pin   = UART3_TX_PIN,                                   \
+        .rx_pin   = UART3_RX_PIN,                                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+        .channel  = UART4_RX_DMA_CHANNEL,                           \
+        .request  = UART4_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+        .channel  = UART4_TX_DMA_CHANNEL,                           \
+        .request  = UART4_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+        .enable_id = EN_UART4,                                      \
+        .tx_port  = UART4_TX_PORT,                                  \
+        .rx_port  = UART4_RX_PORT,                                  \
+        .tx_pin   = UART4_TX_PIN,                                   \
+        .rx_pin   = UART4_RX_PIN,                                   \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_SERIAL */
+
+#endif /* __UART_CONFIG_H__ */
+

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     09. October 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,9 +35,15 @@
 
 
 /*
- * Arm Compiler 6 (armclang)
+ * Arm Compiler 6.6 LTM (armclang)
  */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
   #include "cmsis_armclang.h"
 
 
@@ -115,8 +121,11 @@
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
   #endif
   #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
   #endif
 
 
@@ -187,6 +196,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 /*
@@ -255,6 +268,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 #else

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h

@@ -1,13 +1,16 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.5
- * @date     10. January 2018
+ * @version  V5.2.0
+ * @date     28. January 2020
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017-2018 IAR Systems
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
+//
+// SPDX-License-Identifier: Apache-2.0
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.
@@ -110,6 +113,10 @@
   #define __ASM __asm
 #endif
 
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
 #ifndef __INLINE
   #define __INLINE inline
 #endif
@@ -150,7 +157,12 @@
 #endif
 
 #ifndef   __RESTRICT
-  #define __RESTRICT            restrict
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
 #endif
 
 #ifndef   __STATIC_INLINE
@@ -234,6 +246,25 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 #endif
 
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
 
 #ifndef __ICCARM_INTRINSICS_VERSION__
   #define __ICCARM_INTRINSICS_VERSION__  0
@@ -340,8 +371,17 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
-  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
 
@@ -558,7 +598,7 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t __RRX(uint32_t value)
     {
       uint32_t result;
-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
       return(result);
     }
 
@@ -716,12 +756,25 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
     {
       uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
       return res;
     }
+
     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
     {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
     }
 
     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
@@ -784,37 +837,37 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
   {
     uint32_t res;
-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
   {
     uint32_t res;
-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
   {
     uint32_t res;
-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return res;
   }
 
   __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
   {
-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
   {
-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
   {
-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
   }
 
 #endif /* (__CORTEX_M >= 0x03) */
@@ -826,78 +879,78 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
   {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
   {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
   {
-    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
@@ -910,4 +963,6 @@ __packed struct  __iar_u32 { uint32_t v; };
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
 #endif /* __CMSIS_ICCARM_H__ */

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_version.h
  * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.3
+ * @date     24. June 2019
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,7 +33,7 @@
 
 /*  CMSIS Version definitions */
 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
 #endif

bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cm33.h
  * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.0.5
- * @date     08. January 2018
+ * @version  V5.1.0
+ * @date     12. November 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -61,14 +61,14 @@
  */
 
 #include "cmsis_version.h"
- 
-/*  CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
-                                     __CM33_CMSIS_VERSION_SUB           )     /*!< \deprecated CMSIS HAL version number */
 
-#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
@@ -90,14 +90,14 @@
       #define __DSP_USED       1U
     #else
       #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
+      #define __DSP_USED         0U
     #endif
   #else
     #define __DSP_USED         0U
   #endif
 
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined (__ARM_PCS_VFP)
+  #if defined (__ARM_FP)
     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
@@ -113,7 +113,7 @@
       #define __DSP_USED       1U
     #else
       #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
+      #define __DSP_USED         0U
     #endif
   #else
     #define __DSP_USED         0U
@@ -136,7 +136,7 @@
       #define __DSP_USED       1U
     #else
       #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
+      #define __DSP_USED         0U
     #endif
   #else
     #define __DSP_USED         0U
@@ -159,7 +159,7 @@
       #define __DSP_USED       1U
     #else
       #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
+      #define __DSP_USED         0U
     #endif
   #else
     #define __DSP_USED         0U
@@ -254,7 +254,7 @@
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
+    #define __Vendor_SysTickConfig    1U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -538,14 +538,6 @@ typedef struct
   __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
   __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
   __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
@@ -568,6 +560,9 @@ typedef struct
 #define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
 #define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
 
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
 #define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
 #define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
 
@@ -918,78 +913,6 @@ typedef struct
 #define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
 #define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
 
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
 /*@} end of group CMSIS_SCB */
 
 
@@ -1094,10 +1017,7 @@ typedef struct
   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
         uint32_t RESERVED2[15U];
   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED3[32U];
         uint32_t RESERVED4[43U];
   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
@@ -1160,18 +1080,6 @@ typedef struct
 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
 /* ITM Lock Status Register Definitions */
 #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
@@ -1383,7 +1291,7 @@ typedef struct
  */
 typedef struct
 {
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
         uint32_t RESERVED0[2U];
   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
@@ -1392,29 +1300,26 @@ typedef struct
         uint32_t RESERVED2[131U];
   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
         uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
         uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
         uint32_t RESERVED5[39U];
   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
         uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
 } TPI_Type;
 
 /* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< @Deprecated TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< @Deprecated TPI ACPR: PRESCALER Mask */
-
-#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
 
 /* TPI Selected Pin Protocol Register Definitions */
 #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
@@ -1437,6 +1342,9 @@ typedef struct
 #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
 #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 
@@ -1444,61 +1352,79 @@ typedef struct
 #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
 
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
 
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
 
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
 
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
 
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
 
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
 
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
 
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
 
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
 
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
 
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
 
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
 
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
 
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
 
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
 
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
 
 /* TPI Integration Mode Control Register Definitions */
 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
@@ -1510,22 +1436,19 @@ typedef struct
 #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
 
 #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
@@ -1590,8 +1513,8 @@ typedef struct
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
 /* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
 
 #define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
 #define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
@@ -2139,6 +2062,27 @@ typedef struct
 #define NVIC_USER_IRQ_OFFSET          16
 
 
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
 
 /**
   \brief   Set Priority Grouping
@@ -2158,7 +2102,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
   SCB->AIRCR =  reg_value;
 }
 
@@ -2184,7 +2128,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
   if ((int32_t)(IRQn) >= 0)
   {
+    __COMPILER_BARRIER();
     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
   }
 }
 
@@ -2476,6 +2422,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
   uint32_t *vectors = (uint32_t *)SCB->VTOR;
   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
 }
 
 
@@ -2498,7 +2445,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */

bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h

@@ -1,11 +1,11 @@
 /******************************************************************************
  * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for Armv8-M MPU
- * @version  V5.0.4
- * @date     10. January 2018
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
  ******************************************************************************/
 /*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -87,7 +87,7 @@
 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
 */
 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
-  ((BASE & MPU_RBAR_BASE_Pos) | \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
   ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
   ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
   ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
@@ -101,6 +101,21 @@
   ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
   (MPU_RLAR_EN_Msk))
 
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
 /**
 * Struct for a single MPU Region
 */
@@ -114,20 +129,19 @@ typedef struct {
 */
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
+  __DSB();
+  __ISB();
 }
 
 /** Disable the MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
@@ -140,20 +154,19 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
 */
 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
   MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
+  __DSB();
+  __ISB();
 }
 
 /** Disable the Non-secure MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
@@ -267,7 +280,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 * \param src Source data is copied from.
 * \param len Amount of data words to be copied.
 */
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
   for (i = 0U; i < len; ++i) 
@@ -287,7 +300,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   if (cnt == 1U) {
     mpu->RNR = rnr;
-    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
   } else {
     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
@@ -295,7 +308,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
     mpu->RNR = rnrBase;
     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
-      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
       table += c;
       cnt -= c;
       rnrOffset = 0U;
@@ -303,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
       mpu->RNR = rnrBase;
     }
     
-    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
   }
 }
 

bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s

@@ -0,0 +1,271 @@
+;* File Name          : Startup_ACM32F4.s
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F4 Devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* All rights reserved.
+;*******************************************************************************
+
+Stack_Size      EQU     0x00000800
+Heap_Size       EQU     0x00000000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT __Vectors
+
+__Vectors       
+                DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler                  ; 0:  WDT_IRQHandler
+                DCD     RTC_IRQHandler                  ; 1:  RTC_IRQHandler
+                DCD     EFC_IRQHandler                  ; 2:  EFC_IRQHandler
+                DCD     GPIOAB_IRQHandler               ; 3:  GPIOAB_IRQHandler
+                DCD     GPIOCD_IRQHandler               ; 4:  GPIOCD_IRQHandler
+                DCD     EXTI_IRQHandler                 ; 5:  EXTI_IRQHandler 
+                DCD     SRAM_PARITY_IRQHandler          ; 6:  SRAM_PARITY_IRQHandler
+                DCD     CLKRDY_IRQHandler               ; 7:  CLKRDY_IRQHandler
+                DCD     UART4_IRQHandler                ; 8:  UART4_IRQHandler
+                DCD     DMA_IRQHandler                  ; 9:  DMA_IRQHandler
+                DCD     UART3_IRQHandler                ; 10: UART3_IRQHandler
+                DCD     RSV_IRQHandler                  ; 11: RSV
+                DCD     ADC_IRQHandler                  ; 12: ADC_IRQHandler
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler  ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler
+                DCD     TIM1_CC_IRQHandler              ; 14: TIM1_CC_IRQHandler
+                DCD     TIM2_IRQHandler                 ; 15: TIM2_IRQHandler
+                DCD     TIM3_IRQHandler                 ; 16: TIM3_IRQHandler 
+                DCD     TIM6_IRQHandler                 ; 17: TIM6_IRQHandler
+                DCD     TIM7_IRQHandler                 ; 18: TIM7_IRQHandler
+                DCD     TIM14_IRQHandler                ; 19: TIM14_IRQHandler
+                DCD     TIM15_IRQHandler                ; 20: TIM15_IRQHandler
+                DCD     TIM16_IRQHandler                ; 21: TIM16_IRQHandler
+                DCD     TIM17_IRQHandler                ; 22: TIM17_IRQHandler
+                DCD     I2C1_IRQHandler                 ; 23: I2C1_IRQHandler
+                DCD     I2C2_IRQHandler                 ; 24: I2C2_IRQHandler
+                DCD     SPI1_IRQHandler                 ; 25: SPI1_IRQHandler
+                DCD     SPI2_IRQHandler                 ; 26: SPI2_IRQHandler
+                DCD     UART1_IRQHandler                ; 27: UART1_IRQHandler
+                DCD     UART2_IRQHandler                ; 28: UART2_IRQHandler
+                DCD     LPUART_IRQHandler               ; 29: LPUART_IRQHandler
+                DCD     SPI3_IRQHandler                 ; 30: SPI3_IRQHandler
+                DCD     AES_IRQHandler                  ; 31: AES_IRQHandler
+                DCD     USB_IRQHandler                  ; 32: USB_IRQHandler
+                DCD     DAC_IRQHandler                  ; 33: DAC_IRQHandler
+                DCD     I2S_IRQHandler                  ; 34: I2S_IRQHandler
+                DCD     GPIOEF_IRQHandler               ; 35: GPIOEF_IRQHandler
+                DCD     CAN1_IRQHandler                 ; 36: CAN1_IRQHandler
+                DCD     CAN2_IRQHandler                 ; 37: CAN2_IRQHandler
+                DCD     FPU_IRQHandler                  ; 38: FPU_IRQHandler
+                DCD     TIM4_IRQHandler                 ; 39: TIM4_IRQHandler 
+                DCD     SPI4_IRQHandler                 ; 40: SPI4_IRQHandler
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  System_Core_Config
+                IMPORT  __main
+                LDR     R0, =System_Core_Config
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT   WDT_IRQHandler                 [WEAK]
+                EXPORT   RTC_IRQHandler                 [WEAK]
+                EXPORT   EFC_IRQHandler                 [WEAK]
+                EXPORT   GPIOAB_IRQHandler              [WEAK]
+                EXPORT   GPIOCD_IRQHandler              [WEAK]
+                EXPORT   EXTI_IRQHandler                [WEAK]
+                EXPORT   SRAM_PARITY_IRQHandler         [WEAK]
+                EXPORT   CLKRDY_IRQHandler              [WEAK]
+                EXPORT   UART4_IRQHandler               [WEAK]
+                EXPORT   DMA_IRQHandler                 [WEAK]
+                EXPORT   UART3_IRQHandler               [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+                EXPORT   ADC_IRQHandler                 [WEAK]
+                EXPORT   TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT   TIM1_CC_IRQHandler             [WEAK]
+                EXPORT   TIM2_IRQHandler                [WEAK]
+                EXPORT   TIM3_IRQHandler                [WEAK]
+                EXPORT   TIM6_IRQHandler                [WEAK]
+                EXPORT   TIM7_IRQHandler                [WEAK]
+                EXPORT   TIM14_IRQHandler               [WEAK]
+                EXPORT   TIM15_IRQHandler               [WEAK]
+                EXPORT   TIM16_IRQHandler               [WEAK]
+                EXPORT   TIM17_IRQHandler               [WEAK]
+                EXPORT   I2C1_IRQHandler                [WEAK]
+                EXPORT   I2C2_IRQHandler                [WEAK]
+                EXPORT   SPI1_IRQHandler                [WEAK]
+                EXPORT   SPI2_IRQHandler                [WEAK]
+                EXPORT   UART1_IRQHandler               [WEAK]
+                EXPORT   UART2_IRQHandler               [WEAK]
+                EXPORT   LPUART_IRQHandler              [WEAK]
+                EXPORT   SPI3_IRQHandler                [WEAK]
+                EXPORT   AES_IRQHandler                 [WEAK]
+                EXPORT   USB_IRQHandler                 [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+                EXPORT   DAC_IRQHandler                 [WEAK]
+                EXPORT   I2S_IRQHandler                 [WEAK]
+                EXPORT   GPIOEF_IRQHandler              [WEAK]
+                EXPORT   CAN1_IRQHandler                [WEAK]
+                EXPORT   CAN2_IRQHandler                [WEAK]
+                EXPORT   FPU_IRQHandler                 [WEAK]
+                EXPORT   TIM4_IRQHandler                [WEAK]
+                EXPORT   SPI4_IRQHandler                [WEAK]
+WDT_IRQHandler
+RTC_IRQHandler
+EFC_IRQHandler
+GPIOAB_IRQHandler
+GPIOCD_IRQHandler
+EXTI_IRQHandler
+SRAM_PARITY_IRQHandler
+CLKRDY_IRQHandler
+UART4_IRQHandler
+DMA_IRQHandler
+UART3_IRQHandler
+ADC_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+LPUART_IRQHandler
+SPI3_IRQHandler
+AES_IRQHandler
+USB_IRQHandler
+RSV_IRQHandler
+DAC_IRQHandler
+I2S_IRQHandler
+GPIOEF_IRQHandler
+CAN1_IRQHandler
+CAN2_IRQHandler
+FPU_IRQHandler
+TIM4_IRQHandler
+SPI4_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 
+                IF      :DEF:__MICROLIB
+                 
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                 
+                ELSE
+                 
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+                 
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                END

bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4_iar.s

@@ -0,0 +1,362 @@
+;********************************************************************************
+;* File Name          : Startup_ACM32F4.s
+;* Description        : This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2021 Aisinochip.
+;* All rights reserved.</center></h2>
+;*
+;*******************************************************************************
+
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler              ; Reset Handler
+        DCD     NMI_Handler                ; NMI Handler
+        DCD     HardFault_Handler          ; Hard Fault Handler
+        DCD     MemManage_Handler          ; MPU Fault Handler
+        DCD     BusFault_Handler           ; Bus Fault Handler
+        DCD     UsageFault_Handler         ; Usage Fault Handler
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     SVC_Handler                ; SVCall Handler
+        DCD     DebugMon_Handler           ; Debug Monitor Handler
+        DCD     0                          ; Reserved
+        DCD     PendSV_Handler             ; PendSV Handler
+        DCD     SysTick_Handler            ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WDT_IRQHandler                    ; WDT_IRQHandle
+        DCD     RTC_IRQHandler                    ; RTC_IRQHandler
+        DCD     EFC_IRQHandler                    ; EFC_IRQHandler
+        DCD     GPIOAB_IRQHandler                 ; GPIOAB_IRQHandler
+        DCD     GPIOCD_IRQHandler                 ; GPIOCD_IRQHandler
+        DCD     EXTI_IRQHandler                   ; EXTI_IRQHandler
+        DCD     SRAM_PARITY_IRQHandler            ; SRAM_PARITY_IRQHandler
+        DCD     CLKRDY_IRQHandler                 ; CLKRDY_IRQHandler
+        DCD     UART4_IRQHandler                  ; UART4_IRQHandler
+        DCD     DMA_IRQHandler                    ; DMA_IRQHandler
+        DCD     UART3_IRQHandler                  ; UART3_IRQHandler
+        DCD     RSV_IRQHandler                    ; RSV_IRQHandler
+        DCD     ADC_IRQHandler                    ; ADC_IRQHandler
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler    ; TIM1_BRK_UP_TRG_COM_IRQHandler
+        DCD     TIM1_CC_IRQHandler                ; TIM1_CC_IRQHandler
+        DCD     TIM2_IRQHandler                   ; TIM2_IRQHandler
+        DCD     TIM3_IRQHandler                   ; TIM3_IRQHandler
+        DCD     TIM6_IRQHandler                   ; TIM6_IRQHandler
+        DCD     TIM7_IRQHandler                   ; TIM7_IRQHandler
+        DCD     TIM14_IRQHandler                  ; TIM14_IRQHandler
+        DCD     TIM15_IRQHandler                  ; TIM15_IRQHandler
+        DCD     TIM16_IRQHandler                  ; TIM16_IRQHandler
+        DCD     TIM17_IRQHandler                  ; TIM17_IRQHandler
+        DCD     I2C1_IRQHandler                   ; I2C1_IRQHandler
+        DCD     I2C2_IRQHandler                   ; I2C2_IRQHandler
+        DCD     SPI1_IRQHandler                   ; SPI1_IRQHandler
+        DCD     SPI2_IRQHandler                   ; SPI2_IRQHandler
+        DCD     UART1_IRQHandler                  ; UART1_IRQHandler
+        DCD     UART2_IRQHandler                  ; UART2_IRQHandler
+        DCD     LPUART_IRQHandler                 ; LPUART_IRQHandler
+        DCD     SPI3_IRQHandler                   ; SPI3_IRQHandler
+        DCD     AES_IRQHandler                    ; AES_IRQHandler
+        DCD     USB_IRQHandler                    ; USB_IRQHandler
+        DCD     DAC_IRQHandler                    ; DAC_IRQHandler
+        DCD     I2S_IRQHandler                    ; I2S_IRQHandler
+        DCD     GPIOEF_IRQHandler                 ; GPIOEF_IRQHandler
+        DCD     CAN1_IRQHandler                   ; CAN1_IRQHandler
+        DCD     CAN2_IRQHandler                   ; CAN2_IRQHandler
+        DCD     FPU_IRQHandler                    ; FPU_IRQHandler
+        DCD     TIM4_IRQHandler                   ; TIM4_IRQHandler
+        DCD     SPI4_IRQHandler                   ; SPI4_IRQHandler
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK EFC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EFC_IRQHandler
+        B EFC_IRQHandler
+
+        PUBWEAK GPIOAB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOAB_IRQHandler
+        B GPIOAB_IRQHandler
+
+        PUBWEAK GPIOCD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOCD_IRQHandler
+        B GPIOCD_IRQHandler
+
+        PUBWEAK EXTI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI_IRQHandler
+        B EXTI_IRQHandler
+
+        PUBWEAK SRAM_PARITY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SRAM_PARITY_IRQHandler
+        B SRAM_PARITY_IRQHandler
+
+        PUBWEAK CLKRDY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CLKRDY_IRQHandler
+        B CLKRDY_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK RSV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RSV_IRQHandler
+        B RSV_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK LPUART_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART_IRQHandler
+        B LPUART_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+
+        PUBWEAK I2S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2S_IRQHandler
+        B I2S_IRQHandler
+
+        PUBWEAK GPIOEF_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOEF_IRQHandler
+        B GPIOEF_IRQHandler
+
+        PUBWEAK CAN1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_IRQHandler
+        B CAN1_IRQHandler
+
+        PUBWEAK CAN2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_IRQHandler
+        B CAN2_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+
+        END
+/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/

bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h

@@ -0,0 +1,28 @@
+/*
+  ******************************************************************************
+  * @file    System_Accelerate.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   MCU Accelerate Peripheral Access Layer System header File.
+  ******************************************************************************
+*/
+#ifndef __SYSTEM_ACCELERATE_H__
+#define __SYSTEM_ACCELERATE_H__
+
+
+
+/* System_EnableIAccelerate */ 
+void System_EnableIAccelerate(void);
+
+/* System_DisableIAccelerate */
+void System_DisableIAccelerate(void);
+
+/* System_EnableDAccelerate */
+void System_EnableDAccelerate(void);
+
+/* System_DisableDAccelerate */
+void System_DisableDAccelerate(void);
+
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/Device/startup_ACM32F4_gcc.s

@@ -0,0 +1,344 @@
+/*********************** (C) COPYRIGHT 2020 Aisinochip *************************
+;* File Name          : Startup_ACM32F4.s
+;* Author             : AisinoChip Firmware Team
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F4 Devices vector table for GCC toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 AisinoChip.
+;* All rights reserved.
+;*******************************************************************************/
+
+  .syntax unified
+  .cpu cortex-m33
+  .fpu softvfp 
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/*.equ  BootRAM, 0xF108F85F */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+  /*  bl  SystemInit */
+/* Call static constructors */
+  /*  bl __libc_init_array */
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+
+  /* External Interrupts */
+  .word WDT_IRQHandler
+  .word RTC_IRQHandler
+  .word EFC_IRQHandler
+  .word GPIOAB_IRQHandler
+  .word GPIOCD_IRQHandler
+  .word EXIT_IRQHandler
+  .word SRAM_PAPITY_IRQHandler
+  .word CLKRDY_IRQHandler
+  .word UART4_IRQHandler
+  .word DMA_IRQHandler
+  .word UART3_IRQHandler
+  .word RSV_IRQHandler
+  .word ADC_IRQHandler
+  .word TIM1_BRK_UP_TRG_COM_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word TIM14_IRQHandler
+  .word TIM15_IRQHandler
+  .word TIM16_IRQHandler
+  .word TIM17_IRQHandler
+  .word I2C1_IRQHandler
+  .word I2C2_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word UART1_IRQHandler
+  .word UART2_IRQHandler
+  .word LPUART_IRQHandler
+  .word SPI3_IRQHandler
+  .word AES_IRQHandler
+  .word USB_IRQHandler
+  .word DAC_IRQHandler
+  .word I2S_IRQHandler
+  .word GPIOEF_IRQHandler
+  .word CAN1_IRQHandler
+  .word CAN2_IRQHandler
+  .word FPU_IRQHandler
+  .word TIM4_IRQHandler
+  .word SPI4_IRQHandler
+
+                          
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WDT_IRQHandler
+  .thumb_set WDT_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak EFC_IRQHandler
+  .thumb_set EFC_IRQHandler,Default_Handler
+
+  .weak GPIOAB_IRQHandler
+  .thumb_set GPIOAB_IRQHandler,Default_Handler
+
+  .weak GPIOCD_IRQHandler
+  .thumb_set GPIOCD_IRQHandler,Default_Handler
+
+  .weak EXIT_IRQHandler
+  .thumb_set EXIT_IRQHandler,Default_Handler
+
+  .weak SRAM_PAPITY_IRQHandler
+  .thumb_set SRAM_PAPITY_IRQHandler,Default_Handler
+
+  .weak CLKRDY_IRQHandler
+  .thumb_set CLKRDY_IRQHandler,Default_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak DMA_IRQHandler
+  .thumb_set DMA_IRQHandler,Default_Handler
+
+  .weak UART3_IRQHandler
+  .thumb_set UART3_IRQHandler,Default_Handler
+
+  .weak RSV_IRQHandler
+  .thumb_set RSV_IRQHandler,Default_Handler
+
+  .weak ADC_IRQHandler
+  .thumb_set ADC_IRQHandler,Default_Handler
+
+  .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak TIM15_IRQHandler
+  .thumb_set TIM15_IRQHandler,Default_Handler
+
+  .weak TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Default_Handler
+
+  .weak UART2_IRQHandler
+  .thumb_set UART2_IRQHandler,Default_Handler
+
+  .weak LPUART_IRQHandler
+  .thumb_set LPUART_IRQHandler,Default_Handler
+
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+  .weak USB_IRQHandler
+  .thumb_set USB_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak I2S_IRQHandler
+  .thumb_set I2S_IRQHandler,Default_Handler
+
+  .weak GPIOEF_IRQHandler
+  .thumb_set GPIOEF_IRQHandler,Default_Handler
+
+  .weak CAN1_IRQHandler
+  .thumb_set CAN1_IRQHandler,Default_Handler
+
+  .weak CAN2_IRQHandler
+  .thumb_set CAN2_IRQHandler,Default_Handler
+
+  .weak FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak SPI4_IRQHandler
+  .thumb_set SPI4_IRQHandler,Default_Handler
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h

@@ -0,0 +1,207 @@
+/*
+  ******************************************************************************
+  * @file    ACM32Fxx_HAL.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   HAL Config header file.
+  ******************************************************************************
+*/
+#ifndef __ACM32FXX_HAL_H__
+#define __ACM32FXX_HAL_H__
+
+/* 
+    Uncomment the line below according to the target device used in your application 
+*/
+/* #define ACM32F3XX */    /*!< ACM32F303xx */
+   #define ACM32F4XX       /*!< ACM32F403xx */
+/* #define ACM32FPXX */    /*!< ACM32FP400xx ACM32FP401xx */
+
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(ACM32F3XX)
+    #include "ACM32F3.h"
+#elif defined(ACM32F4XX)
+    #include "ACM32F4.h"
+#elif defined(ACM32FPXX)
+    #include "ACM32FP.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+/**
+  * @}
+  */
+
+
+/*
+ * @brief  HAL Status structures definition
+ */
+typedef enum
+{
+    HAL_OK       = 0x00U,
+    HAL_ERROR    = 0x01U,
+    HAL_BUSY     = 0x02U,
+    HAL_TIMEOUT  = 0x03U
+}HAL_StatusTypeDef;
+
+
+//#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+//#endif
+
+
+/* USE FULL ASSERT */
+#define USE_FULL_ASSERT    (1)
+
+
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDT_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_EFLASH_MODULE_ENABLED
+#ifdef  ACM32F4XX
+#define HAL_OPA_MODULE_ENABLED
+#endif
+#ifndef ACM32FPXX
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#endif
+#define HAL_LPUART_MODULE_ENABLED
+#define HAL_WDT_MODULE_ENABLED 
+#define HAL_FSUSB_MODULE_ENABLED
+#define HAL_SYSTICK_ENABLED
+#define HAL_CRC_ENABLED  
+#define HAL_FAU_ENABLED  
+#define HAL_AES_ENABLED  
+#define HAL_HASH_SHA1_ENABLED 
+#define HAL_HASH_SHA256_ENABLED 
+#define HAL_HRNG_ENABLED  
+
+#if defined(ACM32F3XX)
+    #include "System_ACM32F3.h"
+#elif defined(ACM32F4XX)
+    #include "System_ACM32F4.h"
+#elif defined(ACM32FPXX)
+    #include "System_ACM32FP.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+
+#include "System_Accelerate.h"
+
+#ifdef HAL_DMA_MODULE_ENABLED
+    #include "HAL_DMA.h"
+#endif
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+    #include "HAL_GPIO.h"
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+    #include "HAL_UART.h"
+    #include "HAL_UART_EX.h"
+#endif
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    #include "HAL_ADC.h"
+#endif
+
+#ifdef HAL_DAC_MODULE_ENABLED
+    #include "HAL_DAC.h"
+#endif
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+    #include "HAL_EXTI.h"
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+    #include "HAL_I2C.h"
+#endif
+
+#ifdef HAL_I2S_MODULE_ENABLED
+    #include "HAL_I2S.h"
+#endif
+
+#ifdef HAL_RTC_MODULE_ENABLED
+    #include "HAL_RTC.h"
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+    #include "HAL_SPI.h"
+#endif
+
+#ifdef HAL_IWDT_MODULE_ENABLED
+    #include "HAL_IWDT.h"
+#endif
+
+#ifdef HAL_EFLASH_MODULE_ENABLED
+    #include "HAL_EFlash.h"
+    #include "HAL_EFlash_EX.h"
+#endif
+
+#ifdef HAL_OPA_MODULE_ENABLED
+    #include "HAL_OPA.h"
+#endif
+
+#ifdef HAL_COMP_MODULE_ENABLED
+    #include "HAL_COMP.h"
+#endif
+
+#ifdef HAL_CAN_MODULE_ENABLED
+    #include "HAL_CAN.h"
+#endif
+
+#ifdef HAL_LPUART_MODULE_ENABLED
+    #include "HAL_LPUART.h"
+#endif
+
+#ifdef HAL_WDT_MODULE_ENABLED
+    #include "HAL_WDT.h"
+#endif
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+    #include "HAL_TIMER.h"  
+    #include "HAL_TIMER_EX.h"
+#endif  
+
+#ifdef HAL_FSUSB_MODULE_ENABLED
+    #include "HAL_FSUSB.h"
+#endif
+
+#ifdef HAL_CRC_ENABLED  
+#include  "HAL_CRC.h"
+#endif  
+
+#ifdef  HAL_AES_ENABLED
+#include  "HAL_AES.h"  
+#endif    
+
+#ifdef HAL_FAU_ENABLED    
+#include  "HAL_FAU.h"       
+#endif 
+
+#ifdef HAL_HASH_SHA1_ENABLED 
+#include "HAL_SHA1.h"  
+#endif 
+
+#ifdef HAL_HASH_SHA256_ENABLED 
+#include "HAL_SHA256.h"  
+#endif  
+
+#ifdef HAL_HRNG_ENABLED     
+#include "HAL_HRNG.h"    
+#endif    
+
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h

@@ -0,0 +1,94 @@
+/***********************************************************************
+ * All rights reserved.
+ * Filename    : aes.h
+ * Description : aes driver header file
+ * Author(s)   : Eric  
+ * version     : V1.0
+ * Modify date : 2016-03-24
+ ***********************************************************************/
+#ifndef __AES_H__
+#define __AES_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define AES_ENCRYPTION   		1
+#define AES_DECRYPTION   		0
+#define AES_ECB_MODE	   		0
+#define AES_CBC_MODE	   		1 
+#define AES_SWAP_ENABLE  		1
+#define AES_SWAP_DISABLE 		0
+
+#define AES_NORMAL_MODE   	0x12345678
+#define AES_SECURITY_MODE 	0
+
+#define AES_KEY_128     0
+#define AES_KEY_192     1
+#define AES_KEY_256     2
+
+#define AES_FAIL   0x00
+#define AES_PASS   0xa59ada68
+
+#define BIT_AES        (1<<28)
+
+/************************************************************************
+ * function   : delay
+ * Description: delay for a while.  
+ * input : 
+ *         count: count to decrease 
+ * return: none 
+ ************************************************************************/
+ extern void delay(uint32_t count);
+ 
+
+/******************************************************************************
+ * Name:     HAL_AES_SetKey
+ * Function: set key of AES
+ * Input:
+		     keyin		 --	pointer to buffer of key 
+		     key_len     --	select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) 					
+		     swap_en     -- AES_SWAP_ENABLE, AES_SWAP_DISABLE						
+ * Return:	 None
+*******************************************************************************/
+void HAL_AES_SetKey(UINT32 *keyin, UINT8 key_len, UINT8 swap_en);
+void HAL_AES_SetKey_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en);
+
+
+/******************************************************************************
+Name:		 HAL_AES_Crypt
+Function:	 Function for AES encryption and decryption
+Input:
+         indata		       --   pointer to buffer of input
+         outdata	       --	pointer to buffer of result
+         block_len	       --	block(128bit) length for aes cryption
+         operation	       --	AES_ENCRYPTION,AES_DECRYPTION
+         mode              --   AES_ECB_MODE, AES_CBC_MODE,
+         iv                --   initial vector for CBC mode
+         security_mode     --   AES_NORMAL_MODE, AES_SECURITY_MDOE£¬
+Return:	 None
+
+*******************************************************************************/
+uint32_t HAL_AES_Crypt(
+    uint32_t *indata,
+    uint32_t *outdata,
+    uint32_t block_len,
+    uint8_t  operation,
+    uint8_t  mode,
+    uint32_t *iv,
+    uint32_t security_mode
+);
+
+
+uint32_t HAL_AES_Crypt_U8(
+    uint8_t *indata,
+    uint8_t *outdata,
+    uint32_t block_len,
+    uint8_t  operation,
+    uint8_t  mode,
+    uint8_t *iv,
+    uint32_t security_mode
+);
+
+#endif
+/******************************************************************************
+ * end of file
+*******************************************************************************/

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h

@@ -0,0 +1,394 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Can.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CAN_H__
+#define __HAL_CAN_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/**
+  * @}
+  */
+	
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+/******************************************************************************/
+/*                                    (CAN)                                   */
+/******************************************************************************/
+
+/****************  Bit definition for CAN MOD register  ***********************/
+#define CAN_MOD_RM                      BIT0
+#define CAN_MOD_LOM                     BIT1
+#define CAN_MOD_STM                     BIT2
+#define CAN_MOD_AFM                     BIT3
+#define CAN_MOD_SM                      BIT4
+/****************  Bit definition for CAN CMR register  ***********************/
+#define CAN_CMR_TR                      BIT0
+#define CAN_CMR_AT                      BIT1
+#define CAN_CMR_RRB                     BIT2
+#define CAN_CMR_CDO                     BIT3
+#define CAN_CMR_SRR                     BIT4
+/****************  Bit definition for CAN SR register  ***********************/
+#define CAN_SR_RBS                      BIT0
+#define CAN_SR_DOS                      BIT1
+#define CAN_SR_TBS                      BIT2
+#define CAN_SR_TCS                      BIT3
+#define CAN_SR_RS                       BIT4
+#define CAN_SR_TS                       BIT5
+#define CAN_SR_ES                       BIT6
+#define CAN_SR_BS                       BIT7
+/****************  Bit definition for CAN IR register  ***********************/
+#define CAN_IR_RI                       BIT0  
+#define CAN_IR_TI                       BIT1 
+#define CAN_IR_EI                       BIT2 
+#define CAN_IR_DOI                      BIT3 
+#define CAN_IR_WUI                      BIT4 
+#define CAN_IR_EPI                      BIT5 
+#define CAN_IR_ALI                      BIT6 
+#define CAN_IR_BEI                      BIT7 
+/****************  Bit definition for CAN IER register  ***********************/
+#define CAN_IER_RIE                     BIT0  
+#define CAN_IER_TIE                     BIT1 
+#define CAN_IER_EIE                     BIT2 
+#define CAN_IER_DOIE                    BIT3 
+#define CAN_IER_WUIE                    BIT4 
+#define CAN_IER_EPIE                    BIT5 
+#define CAN_IER_ALIE                    BIT6 
+#define CAN_IER_BEIE                    BIT7 
+
+/** 
+  * @brief  CAN  init structure definition
+  */
+typedef struct
+{
+    uint32_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                This parameter can be a value of 
+                                @ref CAN_mode  e.g:CAN_Mode_Normal   CAN_Mode_Normal*/ 
+    
+    uint32_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                the CAN hardware is allowed to lengthen or 
+                                shorten a bit to perform resynchronization.
+                                This parameter can be a value of 
+                                @ref CAN_SJW  e.g:CAN_SJW_1tq--CAN_SJW_4tq*/
+    
+    uint32_t CAN_BRP ;          /*!< Specifies the number of time quanta in Bit 
+                                Segment 1. This parameter can be a value between 0 and 63 */
+    
+    uint32_t CAN_TSEG1;          /*!< Specifies the number of time quanta in Bit 
+                                Segment 1. This parameter can be a value of 
+                                @ref CAN_TSEG1  e.g: CAN_TSEG1_1tq-CAN_TSEG1_16tq*/
+    
+    uint32_t CAN_TSEG2;          /*!< Specifies the number of time quanta in Bit 
+                                Segment 2.This parameter can be a value of 
+                                @ref CAN_TSEG2  e.g:CAN_TSEG1_1tq-CAN_TSEG16_tq*/
+    
+    uint32_t CAN_SAM ;           /*!< Specifies the CAN operating mode.
+                                This parameter can be a value of 
+                                @ref CAN_SAM e.g:CAN_SAM_1time  CAN_SAM_3time*/
+} CAN_InitTypeDef;
+
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+    uint32_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                        This parameter can be a value of 
+                                        @ref CAN_filter_mode  e.g:CAN_FilterMode_Dual    CAN_FilterMode_Single*/
+    
+    uint32_t CAN_FilterId1;             /*!< Specifies the filter identification number 
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+    
+    uint32_t CAN_FilterId2;             /*!< Specifies the filter identification number 
+                                        only CAN_FilterMode=CAN_FilterMode_Dual Enable
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+    
+    uint32_t CAN_FilterMaskId1;         /*!< Specifies the filter identification mask number 
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+    
+    uint32_t CAN_FilterMaskId2;         /*!< Specifies the filter identification mask number 
+                                        only CAN_FilterMode=CAN_FilterMode_Dual Enable
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+} CAN_FilterInitTypeDef;
+
+
+
+/** 
+  * @brief  CAN RxTxMessege structure definition
+  */
+typedef struct
+{
+    uint32_t StdId;                     /*!< Specifies the standard identifier.
+                                        This parameter can be a value between 0 to 0x7FF. */
+    
+    uint32_t ExtId;                     /*!< Specifies the extended identifier.
+                                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+    
+    uint32_t IDE;                        /*!< Specifies the type of identifier for the message that 
+                                        will be transmitted. This parameter can be a value 
+                                        of @ref CAN_identifier_type  e.g: CAN_Id_Standard  CAN_Id_Extended*/
+    
+    uint32_t RTR;                        /*!< Specifies the type of frame for the message that will 
+                                        be transmitted. This parameter can be a value of 
+                                        @ref CAN_remote_transmission    e.g: CAN_RTR_Data  CAN_RTR_Remote */
+    
+    uint32_t DLC;                        /*!< Specifies the length of the frame that will be 
+                                        transmitted. This parameter can be a value between 0 to 8 */
+    
+    uint8_t Data[8];                    /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
+} CanTxRxMsg;
+
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct __CAN_HandleTypeDef
+{
+    CAN_TypeDef         *Instance;                 /*!< Register base address */
+    
+    CAN_InitTypeDef      Init;                      /*!< CAN required parameters */
+    
+    CanTxRxMsg          *RxMessage;                 /*!< CAN RxMessage */
+    
+    void (*CAN_ReceiveIT_Callback)(struct __CAN_HandleTypeDef *hcan);     /* CAN  ReceiveIT complete callback */ 
+    
+    void (*CAN_TransmitIT_Callback)(struct __CAN_HandleTypeDef *hcan);     /* CAN TransmitIT complete callback */ 
+    
+} CAN_HandleTypeDef;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000001)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+/** @defgroup CAN_remote_transmission
+  * @{
+  */
+
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000001)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+/** @defgroup CAN_TxRxMessege 
+  * @{
+  */
+
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_SR_RBS)  || ((FLAG) == CAN_SR_DOS)   || \
+                               ((FLAG) == CAN_SR_TBS)  || ((FLAG) == CAN_SR_TCS)   || \
+                               ((FLAG) == CAN_SR_RS)  || ((FLAG) == CAN_SR_TS)  || \
+                               ((FLAG) == CAN_SR_ES)  || ((FLAG) == CAN_SR_BS))	
+
+#define IS_CAN_BRP(BRP) 	(((BRP) >= 0) && ((BRP) <= 63))
+
+/**
+  * @defgroup CAN_Mode 
+  * @{
+  */  
+#define CAN_Mode_Normal         ((uint8_t)0x00) /*!< Normal mode */
+#define CAN_Mode_SlefTest       ((uint8_t)0x01) /*!< SlefTest mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) ||\
+                            ((MODE) == CAN_Mode_SlefTest))
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Operating_Mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Normal           ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Initialization   ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Listen           ((uint8_t)0x02) /*!< Listen mode */
+#define CAN_OperatingMode_SelfTest           ((uint8_t)0x04) /*!< Listen mode */
+#define CAN_OperatingMode_Sleep            ((uint8_t)0x10) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+                                    ((MODE) == CAN_OperatingMode_Sleep)|| \
+                                    ((MODE) == CAN_OperatingMode_SelfTest)|| \
+                                    ((MODE) == CAN_OperatingMode_Listen))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_SAM 
+  * @{
+  */
+
+#define CAN_SAM_1time       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SAM_3time       ((uint8_t)0x01)  /*!< 2 time quantum */
+
+#define IS_CAN_SAM(SAM)     (((SAM) == CAN_SAM_1time) || ((SAM) == CAN_SAM_3time))
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+
+#define CAN_SJW_1tq         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq         ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+	
+	/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+
+#define CAN_TSEG1_1tq       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_TSEG1_2tq       ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_TSEG1_3tq       ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_TSEG1_4tq       ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_TSEG1_5tq       ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_TSEG1_6tq       ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_TSEG1_7tq       ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_TSEG1_8tq       ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_TSEG1_9tq       ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_TSEG1_10tq      ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_TSEG1_11tq      ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_TSEG1_12tq      ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_TSEG1_13tq      ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_TSEG1_14tq      ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_TSEG1_15tq      ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_TSEG1_16tq      ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_TSEG1(TSEG1) ((TSEG1) <= CAN_TSEG1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+
+#define CAN_TSEG2_1tq       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_TSEG2_2tq       ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_TSEG2_3tq       ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_TSEG2_4tq       ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_TSEG2_5tq       ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_TSEG2_6tq       ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_TSEG2_7tq       ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_TSEG2_8tq       ((uint8_t)0x07)  /*!< 8 time quantum */
+#define IS_CAN_TSEG2(TSEG) ((TSEG) <= CAN_TSEG2_8tq)
+/**
+  * @}
+  */
+
+	  
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FilterMode_Dual         ((uint8_t)0x00)  /*!< identifier list mode */
+#define CAN_FilterMode_Single       ((uint8_t)0x01)  /*!< identifier/mask mode */
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_Dual) || \
+                                  ((MODE) == CAN_FilterMode_Single))
+
+	/**
+  * @}
+  */
+
+/** @defgroup CAN_ErrorCode 
+  * @{
+  */
+#define CAN_ErrorType_ErrCode         ((uint8_t)0xC0)  /*!< identifier list mode */
+#define CAN_ErrorType_Direction       ((uint8_t)0x20)  /*!< identifier/mask mode */
+#define CAN_ErrorType_SegCode      		 ((uint8_t)0x1F)  /*!< identifier/mask mode */
+#define IS_CAN_ErrorType(ErrorType) (((ErrorType) == CAN_ErrorType_ErrCode) || \
+                                    ((ErrorType) == CAN_ErrorType_Direction)|| \
+                                    ((ErrorType) == CAN_ErrorType_SegCode))
+/**
+  * @}
+  */
+/* Initialization and Configuration functions *********************************/
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+
+/* Transmit functions *********************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage);
+
+void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan);
+
+/* Receive functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+/* Operation modes functions **************************************************/
+HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode);
+
+void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+/* Error Code management functions **********************************/
+int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type);
+
+int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h

@@ -0,0 +1,216 @@
+/*
+  ******************************************************************************
+  * @file    HAL_COMP.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_COMP_H__
+#define __HAL_COMP_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define COMP1        (0x01)
+#define COMP2        (0x02)
+
+/****************  Bit definition for COMP_CR1 and COMP_CR2 register  **************************/
+#define COMP_CR_LOCK                            (BIT31)
+#define COMP_CR_BLANKTIME_POS                   (29U)
+#define COMP_CR_BLANKTIME_MASK                  (BIT30|BIT29)
+#define COMP_CR_CRV_CFG_POS                     (25U)
+#define COMP_CR_CRV_CFG_MASK                    (BIT28|BIT27|BIT26|BIT25)
+#define COMP_CR_CRV_SEL                         (BIT24)
+#define COMP_CR_CRV_EN                          (BIT23)
+#define COMP_CR_WINMODE                         (BIT22)
+#define COMP_CR_WINOUT                          (BIT21)
+#define COMP_CR_POLARITY                        (BIT20)
+#define COMP_CR_FLTEN                           (BIT19)
+#define COMP_CR_FLTTIME_POS                     (16U)
+#define COMP_CR_FLTTIME_MASK                    (BIT18|BIT17|BIT16)
+#define COMP_CR_BLANKSEL_POS                    (12U)
+#define COMP_CR_BLANKSEL_MASK                   (BIT15|BIT14|BIT13|BIT12)
+#define COMP_CR_INPSEL_POS                      (8U)
+#define COMP_CR_INPSEL_MASK                     (BIT11|BIT10|BIT9|BIT8)
+#define COMP_CR_INMSEL_POS                      (4U)
+#define COMP_CR_INMSEL_MASK                     (BIT7|BIT6|BIT5|BIT4)
+#define COMP_CR_HYS_POS                         (1U)
+#define COMP_CR_HYS_MASK                        (BIT3|BIT2|BIT1)
+#define COMP_CR_EN                              (BIT0)
+
+/****************  Bit definition for COMP_SR register  **************************/
+#define COMP_SR_VCOUT2_ORG                      (BIT3)
+#define COMP_SR_VCOUT1_ORG                      (BIT2)
+#define COMP_SR_VCOUT2                          (BIT1)
+#define COMP_SR_VCOUT1                          (BIT0)
+
+/**
+  * @brief  COMP Configuration Structure definition
+  */
+typedef struct
+{
+    uint8_t             Comparator;        /*!< Specify witch comparator be selected */
+    uint32_t            Crv_En;        
+    uint32_t            BlankTime;        
+    uint32_t            Crv_Sel;        
+    uint32_t            Crv_Cfg;
+    uint32_t            WinMode;
+    uint32_t            WinOut;
+    uint32_t            Polarity;
+    uint32_t            FltEn;
+    uint32_t            FltTime;
+    uint32_t            BlankSel;
+    uint32_t            InPSel;
+    uint32_t            InMSel;
+    uint32_t            HYS;
+}COMP_InitTypeDef;
+
+/**
+  * @brief  COMP handle Structure definition
+  */
+typedef struct
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  uint8_t            OutputLevel_Org; /*!< COMP OutputLevel original */
+  uint8_t            OutputLevel;     /*!< COMP OutputLevel with filter */
+} COMP_HandleTypeDef;
+
+#define COMP_CR_CRV_EN_DISABLE           (0U)       
+#define COMP_CR_CRV_EN_ENABLE            (1U)   
+
+#define COMP_CR_CRV_SEL_AVDD             (0U)       
+#define COMP_CR_CRV_SEL_VREF             (1U)  
+
+#define COMP_CR1_WINMODE_COMP1_INPSEL           (0U)       
+#define COMP_CR1_WINMODE_COMP2_INPSEL           (1U)   
+
+#define COMP_CR2_WINMODE_COMP2_INPSEL           (0U)       
+#define COMP_CR2_WINMODE_COMP1_INPSEL           (1U)   
+
+#define COMP_CR1_WINOUT_VCOUT1                 (0U)       
+#define COMP_CR2_WINOUT_VCOUT2                 (0U)       
+#define COMP_CR_WINOUT_VCOUT12                 (1U)   
+
+#define COMP_CR_POLARITY_P                     (0U)   
+#define COMP_CR_POLARITY_N                     (1U)   
+
+#define COMP_CR_FLTEN_DISABLE                  (0U)       
+#define COMP_CR_FLTEN_ENABLE                   (1U)   
+
+#define COMP_CR_FLTTIME_1_CLK                  (0U)   
+#define COMP_CR_FLTTIME_2_CLK                  (1U)   
+#define COMP_CR_FLTTIME_4_CLK                  (2U)   
+#define COMP_CR_FLTTIME_16_CLK                 (3U)   
+#define COMP_CR_FLTTIME_64_CLK                 (4U)   
+#define COMP_CR_FLTTIME_256_CLK                (5U)   
+#define COMP_CR_FLTTIME_1024_CLK               (6U)   
+#define COMP_CR_FLTTIME_4095_CLK               (7U)   
+
+#define COMP_CR_BLANKTIME_32_CLK               (0U)   
+#define COMP_CR_BLANKTIME_64_CLK               (1U)   
+#define COMP_CR_BLANKTIME_128_CLK              (2U)   
+#define COMP_CR_BLANKTIME_256_CLK              (3U)   
+
+#define COMP_CR_BLANKSEL_NONE                  (0U)   
+#define COMP_CR_BLANKSEL_1                     (1U)   
+#define COMP_CR_BLANKSEL_2                     (2U)   
+#define COMP_CR_BLANKSEL_3                     (4U)   
+#define COMP_CR_BLANKSEL_4                     (8U)   
+
+#define COMP_CR_INPSEL_0                      (0U)   
+#define COMP_CR_INPSEL_1                      (1U)   
+#define COMP_CR_INPSEL_2                      (2U)   
+
+#define COMP_CR_INMSEL_0                      (0U)   
+#define COMP_CR_INMSEL_1                      (1U)   
+#define COMP_CR_INMSEL_2                      (2U)   
+#define COMP_CR_INMSEL_3                      (3U)   
+
+#define COMP_CR_HYS_DISABLE                   (0U) 
+#define COMP_CR_HYS_1                         (4U) 
+#define COMP_CR_HYS_2                         (5U) 
+#define COMP_CR_HYS_3                         (6U) 
+#define COMP_CR_HYS_4                         (7U) 
+
+/******************************** COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE)    ((INSTANCE) == COMP)
+#define IS_COMP_ALL_COMP(_COMP)     (((_COMP) == COMP1) || \
+                                  ((_COMP) == COMP2))
+
+#define IS_COMP_ALL_CRV_EN(_CRV_EN)        (((_CRV_EN) == COMP_CR_CRV_EN_DISABLE) || \
+                                           ((_CRV_EN) == COMP_CR_CRV_EN_ENABLE))
+
+#define IS_COMP_ALL_CRV_SEL(_CRV_SEL)      (((_CRV_SEL) == COMP_CR_CRV_SEL_AVDD) || \
+                                           ((_CRV_SEL) == COMP_CR_CRV_SEL_VREF))
+
+#define IS_COMP_ALL_CRV_CFG(_CRV_CFG)      ((_CRV_CFG) <= 15U)
+                                           
+#define IS_COMP_ALL_WINMODE(WINMODE)       (((WINMODE) == COMP_CR1_WINMODE_COMP1_INPSEL) || \
+                                           ((WINMODE) == COMP_CR1_WINMODE_COMP2_INPSEL) || \
+                                           ((WINMODE) == COMP_CR2_WINMODE_COMP2_INPSEL) || \
+                                           ((WINMODE) == COMP_CR2_WINMODE_COMP1_INPSEL))
+                                           
+#define IS_COMP_ALL_WINOUT(_WINOUT)        (((_WINOUT) == COMP_CR1_WINOUT_VCOUT1) || \
+                                           ((_WINOUT) == COMP_CR2_WINOUT_VCOUT2) || \
+                                           ((_WINOUT) == COMP_CR_WINOUT_VCOUT12))
+                                           
+#define IS_COMP_ALL_POLARITY(POLARITY)     (((POLARITY) == COMP_CR_POLARITY_N) || \
+                                           ((POLARITY) == COMP_CR_POLARITY_P))
+
+#define IS_COMP_ALL_FLTEN(FLTEN)           (((FLTEN) == COMP_CR_FLTEN_DISABLE) || \
+                                           ((FLTEN) == COMP_CR_FLTEN_ENABLE))
+
+#define IS_COMP_ALL_FLTTIME(FLTTIME)       (((FLTTIME) == COMP_CR_FLTTIME_1_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_2_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_4_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_16_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_64_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_256_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_1024_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_4095_CLK))
+
+#define IS_COMP_ALL_BLANKTIME(BLANKTIME)   (((BLANKTIME) == COMP_CR_BLANKTIME_32_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_64_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_128_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_256_CLK))
+
+#define IS_COMP_ALL_BLANKSEL(BLANKSEL)     (((BLANKSEL) == COMP_CR_BLANKSEL_NONE) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_1) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_2) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_3) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_4))
+
+#define IS_COMP_ALL_INPSEL(INPSEL)         (((INPSEL) == COMP_CR_INPSEL_0) || \
+                                           ((INPSEL) == COMP_CR_INPSEL_1) || \
+                                           ((INPSEL) == COMP_CR_INPSEL_2))   
+
+#define IS_COMP_ALL_INMSEL(INMSEL)         (((INMSEL) == COMP_CR_INMSEL_0 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_1 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_2 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_3 ))
+
+#define IS_COMP_ALL_HYS(_HYS)              (((_HYS) == COMP_CR_HYS_DISABLE) || \
+                                           ((_HYS) == COMP_CR_HYS_1) || \
+                                           ((_HYS) == COMP_CR_HYS_2) || \
+                                           ((_HYS) == COMP_CR_HYS_3) || \
+                                           ((_HYS) == COMP_CR_HYS_4))
+
+/* Function */
+void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+
+#endif
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h

@@ -0,0 +1,154 @@
+/*
+  ******************************************************************************
+  * @file    HAL_CRC.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CRC_H__
+#define __HAL_CRC_H__
+#include  "ACM32Fxx_HAL.h"
+
+/** @defgroup CRC POLY Reverse
+  * @{
+  */ 
+ #define CRC_POLY_REV_EN                    (0x00000400U)    /*!< Poly Reverse Enable */
+ #define CRC_POLY_REV_DIS                   (0x00000000U)    /*!< Poly Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC OUTXOR Reverse
+  * @{
+  */ 
+ #define CRC_OUTXOR_REV_EN                   (0x00000200U)    /*!< OUTXOR Reverse Enable */
+ #define CRC_OUTXOR_REV_DIS                  (0x00000000U)    /*!< OUTXOR Reverse Disable */
+/**
+  * @}
+  */
+ 
+/** @defgroup CRC INIT Reverse
+  * @{
+  */ 
+ #define CRC_INIT_REV_EN                     (0x00000100U)    /*!< INIT Reverse Enable */
+ #define CRC_INIT_REV_DIS                    (0x00000000U)    /*!< INIT Reverse Disable */
+/**
+  * @}
+  */
+  
+/** @defgroup CRC RSLT Reverse
+  * @{
+  */ 
+ #define CRC_RSLT_REV_EN                     (0x00000080U)    /*!< RSLT Reverse Enable */
+ #define CRC_RSLT_REV_DIS                    (0x00000000U)    /*!< RSLT Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC DATA Reverse
+  * @{
+  */ 
+ #define CRC_DATA_REV_DISABLE                (0x00000000U)    /*!< DATA Reverse Disable */
+ #define CRC_DATA_REV_BY_BYTE                (0x00000020U)    /*!< DATA Reverse By Byte */
+ #define CRC_DATA_REV_BY_HALFWORD            (0x00000040U)    /*!< DATA Reverse By HalfWord */
+ #define CRC_DATA_REV_BY_WORD                (0x00000060U)    /*!< DATA Reverse By Word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Poly Len
+  * @{
+  */ 
+ #define CRC_POLTY_LEN_32                    (0x00000000U)    /*!< POLY len = 32bit */
+ #define CRC_POLTY_LEN_16                    (0x00000008U)    /*!< POLY len = 16bit */
+ #define CRC_POLTY_LEN_8                     (0x00000010U)    /*!< POLY len = 8bit  */
+ #define CRC_POLTY_LEN_7                     (0x00000018U)    /*!< POLY len = 7bit  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Data Len
+  * @{
+  */ 
+ #define CRC_DATA_LEN_1B                    (0x00000000U)    /*!< DATA len = 1 Byte */
+ #define CRC_DATA_LEN_2B                    (0x00000002U)    /*!< DATA len = 2 Byte */
+ #define CRC_DATA_LEN_3B                    (0x00000004U)    /*!< DATA len = 3 Byte */
+ #define CRC_DATA_LEN_4B                    (0x00000006U)    /*!< DATA len = 4 Byte */
+/**
+  * @}
+  */
+
+/** @defgroup CRC RST
+  * @{
+  */ 
+ #define CRC_RST_EN                          (0x00000001U)    /*!< RST CRC_DATA To CRC_INIT */
+ #define CRC_RST_DIS                         (0x00000000U)    /*!< RST CRC_DATA To CRC_INIT */
+
+/**
+  * @}
+  */
+  
+/*
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+    uint32_t PolyRev;                  /*!< Specifies if the Poly is reversed in CRC
+                                            This parameter can be a value of @ref CRC POLY Reverse. */
+    uint32_t OutxorRev;                /*!< Specifies if the Outxor is reversed in CRC
+                                            This parameter can be a value of @ref CRC OUTXOR Reverse. */
+    uint32_t InitRev;                  /*!< Specifies if the Init is reversed in CRC
+                                            This parameter can be a value of @ref CRC INIT Reverse. */
+    uint32_t RsltRev;                  /*!< Specifies if the Result is reversed in CRC
+                                            This parameter can be a value of @ref CRC RSLT Reverse. */
+    uint32_t DataRev;                  /*!< Specifies if the Data is reversed in CRC
+                                            This parameter can be a value of @ref CRC DATA Reverse. */
+    uint32_t PolyLen;                  /*!< Specifies the Poly Len in CRC
+                                            This parameter can be a value of @ref CRC Poly Len. */
+    uint32_t DataLen;                  /*!< Specifies the Data Len in CRC
+                                            This parameter can be a value of @ref CRC Data Len. */
+    uint32_t RST;                      /*!< Specifies if CRC is reset
+                                            This parameter can be a value of @ref CRC RST. */
+	
+    uint32_t InitData;                 /*!< This member configures the InitData. */
+	
+    uint32_t OutXorData;               /*!< This member configures the OutXorData. */
+	
+    uint32_t PolyData;                 /*!< This member configures the PolyData. */
+	
+    uint32_t FData;                    /*!< This member configures the FData. */
+	
+}CRC_InitTypeDef;
+
+/*
+ * @brief  UART handle Structure definition
+ */
+typedef struct
+{
+    CRC_TypeDef           *Instance;                /*!< CRC registers base address  */
+
+    CRC_InitTypeDef        Init;                    /*!< CRC calculate parameters  */
+	
+    uint8_t* CRC_Data_Buff;                         /*!< CRC databuff base address */
+	
+    uint32_t CRC_Data_Len;                          /*!< amount of CRC data to be calculated */
+    
+}CRC_HandleTypeDef;  
+  
+ 
+/*********************************************************************************
+* Function    : HAL_CRC_Calculate
+* Description : Calculate the crc calue of input data.
+* Input       : hcrc: CRC handle.
+* Output      : CRC value
+* Author      : cl                        Data : 2021 
+**********************************************************************************/
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc);  
+
+
+#endif
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h

@@ -0,0 +1,297 @@
+/*
+  ******************************************************************************
+  * @file    HAL_DMA.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_DMA_H__
+#define __HAL_DMA_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define DMA_CHANNEL_NUM     (8)
+
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+
+/****************  Bit definition for DMA CONFIG register  ***********************/
+#define DMA_CONFIG_M2ENDIAN             BIT2
+#define DMA_CONFIG_M1ENDIAN             BIT1
+#define DMA_CONFIG_EN                   BIT0
+
+/****************  Bit definition for DMA Channel CTRL register  ***********************/
+#define DMA_CHANNEL_CTRL_ITC            BIT31
+#define DMA_CHANNEL_CTRL_DI             BIT27
+#define DMA_CHANNEL_CTRL_SI             BIT26
+
+
+/****************  Bit definition for DMA Channel CONFIG register  ***********************/
+#define DMA_CHANNEL_CONFIG_DEST_PERIPH         (BIT19|BIT20|BIT21|BIT22|BIT23|BIT24)
+#define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS     (19)
+#define DMA_CHANNEL_CONFIG_HALT                 BIT18
+#define DMA_CHANNEL_CONFIG_ACTIVE               BIT17
+#define DMA_CHANNEL_CONFIG_LOCK                 BIT16
+#define DMA_CHANNEL_CONFIG_ITC                  BIT15
+#define DMA_CHANNEL_CONFIG_IE                   BIT14
+#define DMA_CHANNEL_CONFIG_FLOW_CTRL           (BIT11|BIT12|BIT13)
+#define DMA_CHANNEL_CONFIG_SRC_PERIPH          (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6)
+#define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS      (1)
+#define DMA_CHANNEL_CONFIG_EN                   BIT0
+
+/** @defgroup DMA_DATA_FLOW
+ *  @{
+ */
+#define    DMA_DATA_FLOW_M2M    (0x00000000)
+#define    DMA_DATA_FLOW_M2P    (0x00000800)
+#define    DMA_DATA_FLOW_P2M    (0x00001000)
+/**
+  * @}
+  */
+
+
+/** @defgroup REQUEST_ID
+ *  @{
+ */
+#define    REG_M2M                        (0)
+
+#define    REQ0_ADC                       (0)
+#define    REQ1_SPI1_SEND                 (1)
+#define    REQ2_SPI1_RECV                 (2)
+#define    REQ3_SPI2_SEND                 (3)
+#define    REQ4_SPI2_RECV                 (4)
+#define    REQ5_UART1_SEND                (5)
+#define    REQ6_UART1_RECV                (6)
+#define    REQ7_UART2_SEND                (7)
+#define    REQ8_UART2_RECV                (8)
+#define    REQ9_I2C1_SEND                 (9)
+#define    REQ10_I2C1_RECV                (10)
+#define    REQ11_I2C2_SEND                (11)
+#define    REQ12_I2C2_RECV                (12)
+#define    REQ13_TIM1_CH1                 (13)
+#define    REQ14_TIM1_CH2                 (14)
+#define    REQ15_TIM1_CH3                 (15)
+#define    REQ16_TIM1_CH4                 (16)
+#define    REQ17_TIM1_UP                  (17)
+#define    REQ18_TIM1_TRIG_COM            (18)
+#define    REQ19_TIM3_CH3                 (19)
+#define    REQ20_TIM3_CH4_OR_UP           (20)
+#define    REQ21_TIM3_CH1_OR_TRIG         (21)
+#define    REQ22_TIM3_CH2                 (22)
+#define    REQ23_TIM6_UP                  (23)
+#define    REQ24_TIM15_CH1_UP_TRIG_COM    (24)
+#define    REQ25_TIM15_CH2                (25)
+#define    REQ26_TIM16_CH1_UP             (26)
+#define    REQ27_TIM16_TRIG_COM           (27)
+#define    REQ27_UART3_SEND               (27)
+#define    REQ28_TIM17_CH1_UP             (28)
+#define    REQ29_TIM17_TRIG_COM           (29)
+#define    REQ29_UART3_RECV               (29)
+#define    REQ30_LPUART_SEND              (30)
+#define    REQ31_LPUART_RECV              (31)
+#define    REQ32_TIM2_CH3                 (32)
+#define    REQ33_TIM2_CH4                 (33)
+#define    REQ34_TIM2_CH1                 (34)
+#define    REQ35_TIM2_CH2                 (35)
+#define    REQ36_TIM7_UP                  (36)
+#define    REQ37_I2S1_TX                  (37)
+#define    REQ38_I2S1_RX                  (38)
+#define    REQ39_DAC1_CH1                 (39)
+#define    REQ40_DAC1_CH2                 (40)
+#define    REQ41_TIM4_CH3                 (41)
+#define    REQ42_TIM4_CH4                 (42)
+#define    REQ43_TIM4_CH1                 (43)
+#define    REQ44_TIM4_CH2                 (44)
+#define    REQ45_UART4_SEND               (45)
+#define    REQ46_UART4_RECV               (46)
+#define    REQ47_SPI3_SEND                (47)
+#define    REQ48_SPI3_RECV                (48)
+#define    REQ49_SPI4_SEND                (49)
+#define    REQ50_SPI4_RECV                (50)
+
+#define    REQ_MAX_LIMIT                  (51)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_SOURCE_ADDR_INCREASE
+ *  @{
+ */
+#define    DMA_SOURCE_ADDR_INCREASE_DISABLE    (0x00000000)
+#define    DMA_SOURCE_ADDR_INCREASE_ENABLE     (0x04000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_DST_ADDR_INCREASE
+ *  @{
+ */
+#define    DMA_DST_ADDR_INCREASE_DISABLE    (0x00000000)
+#define    DMA_DST_ADDR_INCREASE_ENABLE     (0x08000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_SRC_WIDTH
+ *  @{
+ */
+#define    DMA_SRC_WIDTH_BYTE         (0x00000000)    /*  8bit */
+#define    DMA_SRC_WIDTH_HALF_WORD    (0x00040000)    /* 16bit */
+#define    DMA_SRC_WIDTH_WORD         (0x00080000)    /* 36bit */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_DST_WIDTH
+ *  @{
+ */
+#define    DMA_DST_WIDTH_BYTE         (0x00000000)    /*  8bit */
+#define    DMA_DST_WIDTH_HALF_WORD    (0x00200000)    /* 16bit */
+#define    DMA_DST_WIDTH_WORD         (0x00400000)    /* 36bit */
+/**
+  * @}
+  */
+  
+ /** @defgroup DMA_MODE DMA MODE
+ *  @{
+ */
+#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
+#define DMA_CIRCULAR                  0x00000001U                  /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA burst length Structure definition
+  */
+typedef enum
+{
+    DMA_BURST_LENGTH_1   = 0,
+    DMA_BURST_LENGTH_4   = 1,
+    DMA_BURST_LENGTH_8   = 2,
+    DMA_BURST_LENGTH_16  = 3,
+    DMA_BURST_LENGTH_32  = 4,
+    DMA_BURST_LENGTH_64  = 5,
+    DMA_BURST_LENGTH_128 = 6,
+    DMA_BURST_LENGTH_256 = 7,
+}DMA_BURST_LENGTH;
+
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct 
+{
+    uint32_t Mode;                  /* This parameter can be a value of @ref DMA_MODE */
+
+    uint32_t Data_Flow;             /* This parameter can be a value of @ref DMA_DATA_FLOW */
+
+    uint32_t Request_ID;            /* This parameter can be a value of @ref REQUEST_ID */
+
+    uint32_t Source_Inc;            /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */
+
+    uint32_t Desination_Inc;        /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */
+
+    uint32_t Source_Width;          /* This parameter can be a value of @ref DMA_SRC_WIDTH */
+
+    uint32_t Desination_Width;      /* This parameter can be a value of @ref DMA_DST_WIDTH */
+
+}DMA_InitParaTypeDef;
+
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct 
+{
+    DMA_Channel_TypeDef    *Instance;    /* DMA registers base address */
+
+    DMA_InitParaTypeDef     Init;        /* DMA initialization parameters */
+
+    void (*DMA_ITC_Callback)(void);      /* DMA transfer complete callback */
+    
+    void (*DMA_IE_Callback)(void);       /* DMA error complete callback */
+    
+}DMA_HandleTypeDef;
+
+/**
+  * @brief  DMA Link List Item Structure
+  */
+typedef struct DMA_NextLink
+{
+    uint32_t SrcAddr;               /* source address */
+
+    uint32_t DstAddr;               /* desination address */
+
+    struct DMA_NextLink *Next;      /* Next Link */
+
+    uint32_t Control;               /* Control */
+
+}DMA_LLI_InitTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR)) 
+
+#define IS_DMA_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == DMA_Channel0) || \
+                                          ((INSTANCE) == DMA_Channel1) || \
+                                          ((INSTANCE) == DMA_Channel2) || \
+                                          ((INSTANCE) == DMA_Channel3) || \
+                                          ((INSTANCE) == DMA_Channel4) || \
+                                          ((INSTANCE) == DMA_Channel5) || \
+                                          ((INSTANCE) == DMA_Channel6) || \
+                                          ((INSTANCE) == DMA_Channel7))
+
+#define IS_DMA_DATA_FLOW(DATA_FLOW)     (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \
+                                         ((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \
+                                         ((DATA_FLOW) == DMA_DATA_FLOW_P2M))
+
+#define IS_DMA_REQUEST_ID(REQUEST_ID)    ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false)
+
+#define IS_DMA_SRC_WIDTH(WIDTH)     (((WIDTH) == DMA_SRC_WIDTH_BYTE)      || \
+                                     ((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \
+                                     ((WIDTH) == DMA_SRC_WIDTH_WORD))
+
+#define IS_DMA_DST_WIDTH(WIDTH)     (((WIDTH) == DMA_DST_WIDTH_BYTE)      || \
+                                     ((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \
+                                     ((WIDTH) == DMA_DST_WIDTH_WORD))
+                                     
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+#define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_)    (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_)
+
+/* HAL_DMA_IRQHandler */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_Init */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_DeInit */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_Start */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
+
+/* HAL_DMA_Start */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
+
+/* HAL_DMA_Abort */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_GetState */
+HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash.h

@@ -0,0 +1,45 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EFlash HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_H__
+#define __HAL_EFlash_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define EFLASH_PAGE_SIZE    (512UL)
+
+#define HAL_EFLASH_READ_WORD(Addr)        (*(volatile uint32_t *)(Addr))    // Read By Word
+#define HAL_EFLASH_READ_HALFWORD(Addr)    (*(volatile uint16_t *)(Addr))    // Read By Half Word
+#define HAL_EFLASH_READ_BYTE(Addr)        (*(volatile uint8_t *)(Addr))     // Read By Byte
+
+/********************  Bit definition for EFC_CTRL register  ******************/
+#define EFC_CTRL_CHIP_ERASE_MODE        (1 << 2)
+#define EFC_CTRL_PAGE_ERASE_MODE        (1 << 1)
+#define EFC_CTRL_PROGRAM_MODE           (1 << 0)
+
+/********************  Bit definition for EFC_STATUS register  ***************/
+#define EFC_STATUS_NVR4_LOCK            (1 << 4)
+#define EFC_STATUS_NVR3_LOCK            (1 << 3)
+#define EFC_STATUS_NVR2_LOCK            (1 << 2)
+#define EFC_STATUS_NVR1_LOCK            (1 << 1)
+#define EFC_STATUS_EFLASH_RDY           (1 << 0)
+
+#define RD_WAIT_ENSURE_OK   8 
+#define SET_EFC_RD_WAIT(wait)     {EFC->CTRL   = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);}     
+
+/* Exported functions --------------------------------------------------------*/  
+
+/* HAL_EFlash_Init */  
+void HAL_EFlash_Init(uint32_t fu32_freq);  
+/* HAL_EFlash_ErasePage */
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word */
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h

@@ -0,0 +1,26 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash_EX.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of EFlash extention module   
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_EX_H__
+#define __HAL_EFlash_EX_H__
+
+#include "stdint.h"
+
+/* HAL_EFlash_Return_To_Boot */
+void HAL_EFlash_Return_to_Boot(void);
+
+/* HAL_EFlash_Init_Para */ 
+void HAL_EFlash_Init_Para(uint32_t fu32_freq);   
+
+/* HAL_EFlash_ErasePage_EX */   
+void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);  
+
+/* HAL_EFlash_Program_Word_EX */     
+void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);  
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h

@@ -0,0 +1,166 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EXTI.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EXTI_H__
+#define __HAL_EXTI_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                (0x000001)
+#define EXTI_LINE_1                (0x000002)
+#define EXTI_LINE_2                (0x000004)
+#define EXTI_LINE_3                (0x000008)
+#define EXTI_LINE_4                (0x000010)
+#define EXTI_LINE_5                (0x000020)
+#define EXTI_LINE_6                (0x000040)
+#define EXTI_LINE_7                (0x000080)
+#define EXTI_LINE_8                (0x000100)
+#define EXTI_LINE_9                (0x000200)
+#define EXTI_LINE_10               (0x000300)
+#define EXTI_LINE_11               (0x000400)
+#define EXTI_LINE_12               (0x001000)
+#define EXTI_LINE_13               (0x002000)
+#define EXTI_LINE_14               (0x004000)
+#define EXTI_LINE_15               (0x008000)
+#define EXTI_LINE_16               (0x010000)
+#define EXTI_LINE_17               (0x020000)
+#define EXTI_LINE_18               (0x040000)
+#define EXTI_LINE_19               (0x080000)
+#define EXTI_LINE_20               (0x100000)
+#define EXTI_LINE_21               (0x200000)
+#define EXTI_LINE_22               (0x400000)
+#define EXTI_LINE_23               (0x800000) 
+#define EXTI_LINE_MASK             (0xFFFFFFU)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_INTERRUPT         (0x00000001)
+#define EXTI_MODE_EVENT             (0x00000002)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_RISING                 (0x00000001)
+#define EXTI_TRIGGER_FALLING                (0x00000002)
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#define EXTI_GPIOD                          0x00000003u
+#define EXTI_GPIOE                          0x00000004u
+#define EXTI_GPIOF                          0x00000005u
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+    uint32_t u32_Line;        /*!< The Exti line to be configured. This parameter
+                                   can be a value of @ref EXTI_Line */
+    uint32_t u32_Mode;        /*!< The Exit Mode to be configured for a core.
+                                   This parameter can be a combination of @ref EXTI_Mode */
+    uint32_t u32_Trigger;     /*!< The Exti Trigger to be configured. This parameter
+                                   can be a value of @ref EXTI_Trigger */
+    uint32_t u32_GPIOSel;     /*!< The Exti GPIO multiplexer selection to be configured.
+                                   This parameter is only possible for line 0 to 15. It
+                                   can be a value of @ref EXTI_GPIOSel */
+}EXTI_HandleTypeDef;
+
+
+/** @defgroup  EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_ALL_LINE(LINE)    ( (LINE) | (EXTI_LINE_MASK) )      
+
+#define IS_EXTI_MODE(__MODE__)     (((__MODE__) == EXTI_MODE_INTERRUPT) || \
+                                    ((__MODE__) == EXTI_MODE_EVENT))
+
+#define IS_EXTI_TRIGGER(__TRIGGER__)     (((__TRIGGER__) == EXTI_TRIGGER_RISING)  || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_GPIOSEL(__GPIOSEL__)     (((__GPIOSEL__) == EXTI_GPIOA) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOB) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOC) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOD) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOE) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOF))
+/**
+  * @}
+  */
+
+/** @brief  __HAL_EXTI_LINE_IT_ENABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__)    (EXTI->IENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_IT_DISABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__)    (EXTI->IENR &= ~(__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_ENABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__)    (EXTI->EENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_DISABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__)    (EXTI->EENR &= ~(__LINE__))
+
+
+/* HAL_EXTI_IRQHandler */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart);
+
+/* HAL_EXTI_SetConfigLine */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_SoftTrigger */
+void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_GetPending */
+bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_ClearPending */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti);  
+
+/* HAL_EXTI_ClearAllPending */   
+void HAL_EXTI_ClearAllPending(void);  
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FAU.h

@@ -0,0 +1,170 @@
+
+#ifndef __FAU_H_
+#define __FAU_H_
+
+#define RANGE 2147483648U  //2^31
+#define CORDIC_F_31  0xD2C90A46 // CORDIC gain F
+
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 1 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_1(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 2 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_2(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 3 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_3(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 4 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_4(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 5 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_5(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 6 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_6(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 7 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_7(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 8 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_8(int angle_para, int* cos_data, int* sin_data);
+
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 1 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_1(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 2 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_2(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 3 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_3(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 4 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_4(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 5 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_5(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 6 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_6(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 7 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_7(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 8 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_8(int x, int y, int*sqrt_data, int* atan_data);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FSUSB.h

@@ -0,0 +1,105 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Uart.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_FSUSB_H__
+#define __HAL_FSUSB_H__  
+
+#include "ACM32Fxx_HAL.h"
+
+
+#define     HIGH_SPEED     1 
+#define     FULL_SPEED     0 
+
+#define     USB_EP0        0
+#define     USB_EP1        1        
+#define     USB_EP2        2      
+#define     USB_EP3        3        
+#define     USB_EP4        4   
+
+#define     USB_EP_IN      USB_EP1
+#define     USB_EP_OUT     USB_EP1
+
+#define     EP_DIR_IN      0x80  
+#define     EP_DIR_OUT     0x00   
+
+#define 	HID_REPORT_SIZE         1024
+
+#define     EP0_MAX_PACKET_SIZE     64
+#define     EPX_MAX_PACKET_SIZE     64
+//#define     EPX_MAX_PACKET_SIZE_HS     512
+//#define     EPX_MAX_PACKET_SIZE_FS     64
+
+#define     MASK_EPX_IN(x)		(1<<(6+3*x))   
+#define     MASK_EPX_OUT(x)     (1<<(7+3*x))   
+#define     MASK_EPX_ACK(x)     (1<<(8+3*x)) 
+#define     MASK_EPX_TIMEOUT(x) (1<< (25+x))
+
+typedef __PACKED_STRUCT _device_request
+{
+	uint8_t  bmRequestType;
+	uint8_t  bRequest;
+	uint16_t wValue;
+	uint16_t wIndex;
+	uint16_t wLength;
+} DEVICE_REQUEST;
+
+
+
+#define USB_BUS_RESET         	0x01
+#define USB_SUSPEND           	0x02
+#define USB_RESUME           	0x04
+#define USB_SOF            		0x08
+#define USB_SETUPTOK         	0x10
+#define USB_EP0_SETUP_PACKET  	0x20
+#define USB_EP0_IN		  		0x40
+#define USB_EP0_OUT_PACKET 		0x80
+#define USB_EP0_ACK  			0x100
+#define USB_EP1_IN		  		0x200
+#define USB_EP1_OUT_PACKET    	0x400
+#define USB_EP1_ACK		    	0x800
+#define USB_EP2_IN		  		0x1000
+#define USB_EP2_OUT_PACKET    	0x2000
+#define USB_EP2_ACK		    	0x4000
+#define USB_EP3_IN		  		0x8000
+#define USB_EP3_OUT_PACKET    	0x10000
+#define USB_EP3_ACK		    	0x20000
+#define USB_EP4_IN		  		0x40000
+#define USB_EP4_OUT_PACKET    	0x80000
+#define USB_EP4_ACK		    	0x100000
+#define USB_IN_TIMEOUT	    	0x200000
+#define USB_SETADDR		    	0x400000
+#define USB_CRC_ERR 	    	0x800000
+#define USB_MORETHAN_64     	0x1000000
+#define USB_EP0_IN_ERR      	0x2000000
+#define USB_EP1_IN_ERR      	0x4000000
+#define USB_EP2_IN_ERR      	0x8000000
+#define USB_EP3_IN_ERR      	0x10000000
+#define USB_EP4_IN_ERR      	0x20000000
+#define USB_NOEOP_ERR      		0x40000000
+#define USB_TOGGLE_ERR      	0x80000000
+
+
+
+#define ERROR_OUT_OUT            4  // received a same out packet 
+#define ERROR_IN_OUT             2  // received a pakcet when try to send packet   
+
+
+
+uint32_t HAL_FSUSB_Init(void);     
+void HAL_FSUSB_Read_EP_MEM8(uint8_t *dst, uint32_t length, uint32_t fifo_offset, uint8_t ep_index);  
+uint8_t HAL_FSUSB_Send_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index);   
+void HAL_FSUSB_Receive_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index);  
+uint16_t HAL_USB_Get_Stall_Status(uint8_t ep_index, uint8_t ep_dir);  
+void HAL_FSUSB_EP0_Send_Empty_Packet(void);  
+void HAL_FSUSB_EP0_Send_Stall(void);    
+void usb_clear_stall(uint8_t ep_index, uint8_t ep_dir);  
+void usb_send_stall(uint8_t ep_index, uint8_t ep_dir);
+uint16_t HAL_FSUSB_Get_FIFO_Length(uint8_t ep_index);      
+
+#endif  
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h

@@ -0,0 +1,214 @@
+/*
+  ******************************************************************************
+  * @file    HAL_GPIO.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_GPIO_H__
+#define __HAL_GPIO_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+
+#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_mode GPIO mode
+  * @{
+  */
+#define  GPIO_MODE_INPUT                    (0x00010000u)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                (0x00010001u)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                (0x00011002u)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                    (0x00000003u)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                    (0x00001004u)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_ANALOG                   (0x00000005u)   /*!< Analog Mode                           */
+#define  GPIO_MODE_IT_RISING                (0x10010000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING               (0x10010001u)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING        (0x10010002u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_IT_HIGH_LEVEL            (0x10010003u)   /*!< External Interrupt Mode with high level trigger detection  */
+#define  GPIO_MODE_IT_LOW_LEVEL             (0x10010004u)   /*!< External Interrupt Mode with low level trigger detection  */
+
+#define  GPIO_MODE_OD_MASK                  (0x00001000u)   /*!< OD Mode Mask                          */
+#define  GPIO_MODE_IO_MASK                  (0x00010000u)   /*!< Use GPIO Function Mask                */
+#define  GPIO_MODE_IT_MASK                  (0x10000000u)   /*!< GPIO interrupt Mask                */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_pull GPIO pull
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIOEx_function_selection GPIO pull
+  * @{
+  */
+#define  GPIO_FUNCTION_0        (0x00000000u)
+#define  GPIO_FUNCTION_1        (0x00000001u)
+#define  GPIO_FUNCTION_2        (0x00000002u)
+#define  GPIO_FUNCTION_3        (0x00000003u)
+#define  GPIO_FUNCTION_4        (0x00000004u)
+#define  GPIO_FUNCTION_5        (0x00000005u)
+#define  GPIO_FUNCTION_6        (0x00000006u)
+#define  GPIO_FUNCTION_7        (0x00000007u)
+#define  GPIO_FUNCTION_8        (0x00000008u)
+#define  GPIO_FUNCTION_9        (0x00000009u)
+/**
+  * @}
+  */
+
+
+
+/** @defgroup GPIOx Index
+  * @{
+  */
+typedef enum
+{
+    GPIOA,
+    GPIOB,
+    GPIOC,
+    GPIOD,
+    GPIOE,
+    GPIOF,
+}enum_GPIOx_t;
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO Bit SET and Bit RESET enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_PIN_CLEAR = 0u,
+  GPIO_PIN_SET   = 1u,
+}enum_PinState_t;
+/**
+  * @}
+  */
+
+
+
+/*
+ * @brief   GPIO Init structure definition
+ */
+typedef struct
+{
+    uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_pins */
+
+    uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_mode */
+
+    uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                              This parameter can be a value of @ref GPIO_pull */
+
+    uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
+                               This parameter can be a value of @ref GPIOEx_function_selection */
+} GPIO_InitTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_PIN(__PIN__)           ((((uint32_t)(__PIN__) &  GPIO_PIN_MASK) != 0x00u) &&\
+                                        (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
+
+
+#define IS_GPIO_MODE(__MODE__)         (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                        ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                        ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                        ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                        ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                        ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                        ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                        ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                        ((__MODE__) == GPIO_MODE_IT_HIGH_LEVEL)      ||\
+                                        ((__MODE__) == GPIO_MODE_IT_LOW_LEVEL)       ||\
+                                        ((__MODE__) == GPIO_MODE_ANALOG))
+
+
+
+
+#define IS_GPIO_PULL(__PULL__)         (((__PULL__) == GPIO_NOPULL)   ||\
+                                        ((__PULL__) == GPIO_PULLUP)   ||\
+                                        ((__PULL__) == GPIO_PULLDOWN))
+
+#define IS_GPIO_PIN_ACTION(ACTION)     (((ACTION) == GPIO_PIN_CLEAR) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_FUNCTION(__FUNCTION__)    (((__FUNCTION__) == GPIO_FUNCTION_0) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_1) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_2) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_3) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_4) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_5) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_6) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_7) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_8) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_9))
+                                     
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* HAL_GPIO_IRQHandler */
+void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin);
+
+/* HAL_GPIO_Init */
+void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init);
+
+/* HAL_GPIO_DeInit */
+void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin);
+
+/* HAL_GPIO_AnalogEnable */
+void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin);
+
+/* HAL_GPIO_WritePin */
+void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState);
+
+/* HAL_GPIO_ReadPin */
+enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h

@@ -0,0 +1,53 @@
+/***********************************************************************f
+ * Filename    : hrng.h
+ * Description : hrng header file
+ * Author(s)   : cc  
+ * version     : V1.0
+ * Modify date : 2021-03-24
+ ***********************************************************************/
+
+#ifndef __HRNG_H__
+#define __HRNG_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_Initial
+* Description    : initial hrng module
+* Input          : None
+* Output         : None
+* Return         : None
+*********************************************************************************/
+void HAL_HRNG_Initial(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng_8
+* Description    : get 8bit random number
+* Input          : None
+* Output         : None
+* Return         : 8 bit random number
+*********************************************************************************/
+UINT8 HAL_HRNG_GetHrng_8(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng_32
+* Description    : get 32bit random number
+* Input          : None
+* Output         : None
+* Return         : 32 bit random number
+*********************************************************************************/
+UINT32 HAL_HRNG_GetHrng_32(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng
+* Description    : get random number
+* Input          : byte_len :  the byte length of random number
+* Output         : *hdata   :  the start address of random number
+* Return         : 0: hrng data is ok; 1: hrng data is bad
+*********************************************************************************/
+UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len);
+
+#endif
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h

@@ -0,0 +1,253 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2C.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+*/
+
+#ifndef __HAL_I2C_H__
+#define __HAL_I2C_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Bit definition for I2C CR register  ********************/
+#define I2C_CR_STOPF_INTEN                  BIT20
+#define I2C_CR_RX_ADDR3_INTEN               BIT19
+#define I2C_CR_DMA_EN                       BIT18
+#define I2C_CR_TXE_SEL                      BIT17
+#define I2C_CR_MARLO_INTEN                  BIT16
+#define I2C_CR_TX_AUTO_EN                   BIT15
+#define I2C_CR_OD_MODE                      BIT14
+#define I2C_CR_RX_ADDR2_INT_EN              BIT12
+#define I2C_CR_OVR_INT_EN                   BIT11
+#define I2C_CR_RXNE_INT_EN                  BIT10
+#define I2C_CR_TXE_INT_EN                   BIT9
+#define I2C_CR_RX_ADDR1_INT_EN              BIT8
+#define I2C_CR_MTF_INT_EN                   BIT7
+#define I2C_CR_TACK                         BIT6
+#define I2C_CR_STOP                         BIT5
+#define I2C_CR_START                        BIT4
+#define I2C_CR_TX                           BIT3
+#define I2C_CR_MASTER                       BIT2
+#define I2C_CR_NOSTRETCH                    BIT1
+#define I2C_CR_MEN                          BIT0
+
+/****************  Bit definition for I2C SR register  ********************/
+#define I2C_SR_TIMEOUTBF                    BIT16
+#define I2C_SR_TIMEOUTAF                    BIT15
+#define I2C_SR_RX_ADDR3                     BIT14
+#define I2C_SR_RX_ADDR2                     BIT12
+#define I2C_SR_OVR                          BIT11
+#define I2C_SR_RXNE                         BIT10
+#define I2C_SR_TXE                          BIT9
+#define I2C_SR_RX_ADDR1                     BIT8
+#define I2C_SR_MTF                          BIT7
+#define I2C_SR_MARLO                        BIT6
+#define I2C_SR_TX_RX_FLAG                   BIT5
+#define I2C_SR_BUS_BUSY                     BIT4
+#define I2C_SR_SRW                          BIT3
+#define I2C_SR_STOPF                        BIT2
+#define I2C_SR_STARTF                       BIT1
+#define I2C_SR_RACK                         BIT0
+
+/**************  Bit definition for I2C SLAVE ADDR2/3 register  **************/
+#define I2C_ADDR3_EN                        BIT8
+#define I2C_ADDR2_EN                        BIT0
+
+/**************  Bit definition for I2C TIMEOUT register  **************/
+#define I2C_TIMEOUT_EXTEN                   BIT31
+#define I2C_TOUTB_INTEN                     BIT30
+#define I2C_EXT_MODE                        BIT29
+#define I2C_TIMEOUT_TIMOUTEN                BIT15
+#define I2C_TOUTA_INTEN                     BIT14
+
+/** @defgroup I2C_MODE
+ *  @{
+ */
+#define    I2C_MODE_SLAVE     (0U)
+#define    I2C_MODE_MASTER    (1U)
+/**
+  * @}
+  */
+
+/** @defgroup CLOCK_SPEED
+ *  @{
+ */
+#define    CLOCK_SPEED_STANDARD     (100000U)
+#define    CLOCK_SPEED_FAST         (400000U)
+#define    CLOCK_SPEED_FAST_PLUS    (1000000U)
+/**
+  * @}
+  */
+
+
+/** @defgroup TX_AUTO_EN
+ *  @{
+ */
+#define    TX_AUTO_EN_DISABLE    (0U)
+#define    TX_AUTO_EN_ENABLE     (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup NO_STRETCH_MODE
+ *  @{
+ */
+#define    NO_STRETCH_MODE_STRETCH      (0U)
+#define    NO_STRETCH_MODE_NOSTRETCH    (1U)
+/**
+  * @}
+  */
+
+/** @defgroup SLAVE State machine
+ *  @{
+ */
+#define    SLAVE_RX_STATE_IDLE         (0U)
+#define    SLAVE_RX_STATE_RECEIVING    (1U)
+#define    SLAVE_TX_STATE_IDLE         (0U)
+#define    SLAVE_TX_STATE_SENDING      (1U)
+/**
+  * @}
+  */
+  
+ /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0U)
+#define I2C_MEMADD_SIZE_16BIT           (1U)
+/**
+  * @}
+  */
+ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+  * @{
+  */
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+ 
+/**
+  * @brief  I2C Configuration Structure definition
+  */
+  
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->SR) & (__FLAG__))  == (__FLAG__) ) ? 1 : 0) 
+
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef struct
+{
+    uint32_t  I2C_Mode;               /* This parameter can be a value of @ref I2C_MODE */
+    
+    uint32_t  Tx_Auto_En;             /* This parameter can be a value of @ref TX_AUTO_EN */
+    
+    uint32_t  No_Stretch_Mode;        /* This parameter can be a value of @ref NO_STRETCH_MODE */
+    
+    uint32_t  Own_Address;            /* This parameter can be a 7-bit address */
+    
+    uint32_t  Clock_Speed;            /* This parameter can be a value of @ref CLOCK_SPEED */
+} I2C_InitTypeDef;
+
+/******************************** Check I2C Parameter *******************************/
+#define IS_I2C_ALL_MODE(I2C_MODE)    (((I2C_MODE) == I2C_MODE_SLAVE) || \
+                                      ((I2C_MODE) == I2C_MODE_MASTER))
+
+#define IS_I2C_CLOCK_SPEED(CLOCK_SPEED)    (((CLOCK_SPEED) > 0U) && ((CLOCK_SPEED) <=1000000U))
+
+#define IS_I2C_TX_AUTO_EN(TX_AUTO_EN)      (((TX_AUTO_EN) == TX_AUTO_EN_DISABLE) || \
+                                            ((TX_AUTO_EN) == TX_AUTO_EN_ENABLE))
+
+#define IS_I2C_STRETCH_EN(STRETCH_EN)    (((STRETCH_EN) == NO_STRETCH_MODE_STRETCH) || \
+                                          ((STRETCH_EN) == NO_STRETCH_MODE_NOSTRETCH))
+
+/**
+  * @brief  I2C handle Structure definition
+  */
+typedef struct
+{
+    I2C_TypeDef         *Instance;         /* I2C registers base address */
+
+    I2C_InitTypeDef      Init;             /* I2C communication parameters */
+    
+    uint32_t               Slave_RxState;    /* I2C Slave state machine */
+    uint32_t               Slave_TxState;    /* I2C Slave state machine */
+    
+    uint8_t               *Rx_Buffer;        /* I2C Rx Buffer */
+    uint8_t               *Tx_Buffer;        /* I2C Tx Buffer */
+    
+    uint32_t               Rx_Size;          /* I2C Rx Size */
+    uint32_t               Tx_Size;          /* I2C Tx Size */
+    
+    uint32_t               Rx_Count;         /* I2C Rx Count */
+    uint32_t               Tx_Count;         /* I2C Tx Count */
+
+    DMA_HandleTypeDef   *HDMA_Rx;          /* I2C Rx DMA handle parameters */
+    DMA_HandleTypeDef   *HDMA_Tx;          /* I2C Tx DMA handle parameters */
+
+    void (*I2C_STOPF_Callback)(void);      /* I2C STOP flag interrupt callback */
+
+}I2C_HandleTypeDef;
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
+
+/* Function : HAL_I2C_IRQHandler */
+void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_MspInit */
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_MspDeInit */
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_Init */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_DeInit */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_Master_Transmit */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Master_Receive */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Transmit */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Receive */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+ 
+/* Function : HAL_I2C_Slave_Transmit_IT */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+
+/* Function : HAL_I2C_Slave_Receive_IT */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Slave_Receive_DMA */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Slave_Transmit_DMA */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Mem_Write */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Mem_Read */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_GetSlaveRxState */
+uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_GetSlaveTxState */
+uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2S.h

@@ -0,0 +1,248 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2S.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+*/
+
+#ifndef __HAL_I2S_H__
+#define __HAL_I2S_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************************/
+/*                             Registers Bits Definition                            */
+/************************************************************************************/
+
+/****************  Bit definition for I2S CTL Register  ***********************/
+#define I2S_CTL_I2SEN               (BIT10)
+#define I2S_CTL_I2SOPMOD            (BIT9|BIT8)
+#define I2S_CTL_PCMSMOD             (BIT7)
+#define I2S_CTL_I2SSTD              (BIT5|BIT4)
+#define I2S_CTL_CKPL                (BIT3)
+#define I2S_CTL_DTLEN               (BIT2|BIT1)
+#define I2S_CTL_CHLEN               (BIT0)
+
+/****************  Bit definition for I2S PSC Register  ***********************/
+#define I2S_PSC_MCKOEN              (BIT10)
+#define I2S_PSC_OF                  (BIT9)
+#define I2S_PSC_DIV                 (0x1FF)
+
+/****************  Bit definition for I2S DIE Register  ***********************/
+#define I2S_DIE_TBEIE               (BIT7)
+#define I2S_DIE_RBNEIE              (BIT6)
+#define I2S_DIE_ERRIE               (BIT5)
+#define I2S_DIE_DMATEN              (BIT1)
+#define I2S_DIE_DMAREN              (BIT0)
+
+/****************  Bit definition for I2S STATUS Register  ***********************/
+#define I2S_STATUS_FERR             (BIT8)
+#define I2S_STATUS_TRANS            (BIT7)
+#define I2S_STATUS_RXORERR          (BIT6)
+#define I2S_STATUS_TXURERR          (BIT3)
+#define I2S_STATUS_I2SCH            (BIT2)
+#define I2S_STATUS_TXBE             (BIT1)
+#define I2S_STATUS_RXBNE            (BIT0)
+
+
+
+/** @defgroup I2S_Mode I2S Mode
+  * @{
+  */
+#define I2S_MODE_SLAVE_TX                (0x00000000)
+#define I2S_MODE_SLAVE_RX                (0x00000100)
+#define I2S_MODE_MASTER_TX               (0x00000200)
+#define I2S_MODE_MASTER_RX               (I2S_CTL_I2SOPMOD)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Standard I2S Standard
+  * @{
+  */
+#define I2S_STANDARD_PHILIPS             (0x00000000U)
+#define I2S_STANDARD_MSB                 (0x00000010U)
+#define I2S_STANDARD_LSB                 (0x00000020U)
+#define I2S_STANDARD_PCM_SHORT           (I2S_CTL_I2SSTD)
+#define I2S_STANDARD_PCM_LONG            (I2S_CTL_I2SSTD | I2S_CTL_PCMSMOD)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Data_Format I2S Data Format
+  * @{
+  */
+#define I2S_DATAFORMAT_16B               (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED      (I2S_CTL_CHLEN)
+#define I2S_DATAFORMAT_24B               (I2S_CTL_CHLEN | 0x02)
+#define I2S_DATAFORMAT_32B               (I2S_CTL_CHLEN | 0x04)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+  * @{
+  */
+#define I2S_MCLKOUTPUT_ENABLE            (I2S_PSC_MCKOEN)
+#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+  * @{
+  */
+#define I2S_CPOL_LOW                     (0x00000000U)
+#define I2S_CPOL_HIGH                    (I2S_CTL_CKPL)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Audio_FrequencyOF I2S Clock Frequency OF
+  * @{
+  */
+#define I2S_FREQ_OF_DISABLE              (0x00000000U)
+#define I2S_FREQ_OF_ENABLE               (I2S_PSC_OF)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+    HAL_I2S_STATE_RESET      = 0x00U,    /*!< I2S not yet initialized or disabled                */
+    HAL_I2S_STATE_READY      = 0x01U,    /*!< I2S initialized and ready for use                  */
+    HAL_I2S_STATE_BUSY       = 0x02U,    /*!< I2S internal process is ongoing                    */
+    HAL_I2S_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
+    HAL_I2S_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
+    HAL_I2S_STATE_TIMEOUT    = 0x06U,    /*!< I2S timeout state                                  */
+    HAL_I2S_STATE_ERROR      = 0x07U     /*!< I2S error state                                    */
+}enum_I2S_State;
+
+
+/**
+  * @brief I2S Init structure definition
+  */
+typedef struct
+{
+    uint32_t u32_Mode;            /*!< Specifies the I2S operating mode.
+                                       This parameter can be a value of @ref I2S_Mode */
+    
+    uint32_t u32_Standard;        /*!< Specifies the standard used for the I2S communication.
+                                       This parameter can be a value of @ref I2S_Standard */
+    
+    uint32_t u32_DataFormat;      /*!< Specifies the data format for the I2S communication.
+                                       This parameter can be a value of @ref I2S_Data_Format */
+    
+    uint32_t u32_MCLKOutput;      /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                       This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t u32_CPOL;            /*!< Specifies the idle state of the I2S clock.
+                                       This parameter can be a value of @ref I2S_Clock_Polarity */
+
+    uint32_t u32_FreqOF;          /*!< Specifies the frequency selected for the I2S communication.
+                                       This parameter can be a value of @ref I2S_Audio_FrequencyFO */
+
+    uint32_t u32_FreqDIV;         /*!< Specifies the frequency selected for the I2S communication.
+                                       This parameter must be a number between Min_Data = 0x001 and Max_Data = 0x1FF */
+}I2S_InitTypeDef;
+
+
+
+/**
+  * @brief I2S handle Structure definition
+  */
+typedef struct
+{
+    I2S_TypeDef           *Instance;     /*!< I2S registers base address */
+
+    I2S_InitTypeDef        Init;         /*!< I2S communication parameters */
+
+    enum_I2S_State         I2S_Status;
+
+    uint32_t              *u32_Rx_Buffer;        /* I2S Rx Buffer */
+    uint32_t              *u32_Tx_Buffer;        /* I2S Tx Buffer */
+    
+    uint32_t               u32_Rx_Size;          /* I2S Rx Size */
+    uint32_t               u32_Tx_Size;          /* I2S Tx Size */
+    
+    uint32_t               u32_Rx_Count;         /* I2S RX Count */
+    uint32_t               u32_Tx_Count;         /* I2S TX Count */
+
+    DMA_HandleTypeDef   *HDMA_Rx;          /* SPI Rx DMA handle parameters */
+    DMA_HandleTypeDef   *HDMA_Tx;          /* SPI Tx DMA handle parameters */
+
+}I2S_HandleTypeDef;
+
+
+/** @defgroup  RTC Private Macros
+  * @{
+  */
+#define IS_I2S_MODE(__MODE__)             (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
+                                           ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
+                                           ((__MODE__) == I2S_MODE_MASTER_TX) || \
+                                           ((__MODE__) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(__STANDARD__)     (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
+                                           ((__STANDARD__) == I2S_STANDARD_MSB)       || \
+                                           ((__STANDARD__) == I2S_STANDARD_LSB)       || \
+                                           ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+                                           ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+                                           
+#define IS_I2S_DATAFORMAT(__DATAFORMAT__)       (((__DATAFORMAT__) == I2S_DATAFORMAT_16B)           || \
+                                                 ((__DATAFORMAT__) == I2S_DATAFORMAT_16B_EXTENDED)  || \
+                                                 ((__DATAFORMAT__) == I2S_DATAFORMAT_24B)           || \
+                                                 ((__DATAFORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__MCLK_OUTPUT__)     (((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_ENABLE)  || \
+                                                 ((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_MCLK_CPOL(__CPOL__)              (((__CPOL__) == I2S_CPOL_LOW)  || \
+                                                 ((__CPOL__) == I2S_CPOL_HIGH))
+
+#define IS_I2S_OF(__OF__)                       (((__OF__) == I2S_FREQ_OF_DISABLE)  || \
+                                                 ((__OF__) == I2S_FREQ_OF_ENABLE))
+
+#define IS_I2S_DIV(__DIV__)                      ((__DIV__) >= 0x001 && (__DIV__) <= 0x1FF)
+/**
+  * @}
+  */
+
+/* HAL_I2S_IRQHandler */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* HAL_I2S_MspInit */
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hspi);
+
+/* HAL_I2S_Init */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+
+/* HAL_I2S_Transmit */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout);
+
+/* HAL_I2S_Receive */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout);
+
+/* HAL_I2S_Transmit_IT */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+/* HAL_I2S_Receive_IT */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+/* HAL_I2S_Transmit_DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+/* HAL_I2S_Receive_DMA */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h

@@ -0,0 +1,56 @@
+
+/***********************************************************************
+ * Filename    : HAL_IWDT.h
+ * Description : IHAL WDT driver header file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17  
+ ***********************************************************************/
+
+#ifndef __HAL_IWDT_H__
+#define __HAL_IWDT_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+/****************  Bit definition for IWDT register  ***********************/
+
+
+/*----------------------macro definition------------------------*/
+#define IWDT_ENABLE_COMMAND  (0xCCCCU)
+#define IWDT_WRITE_ENABLE_COMMAND  (0x5555U)  
+#define IWDT_WAKEUP_ENABLE_COMMAND  (0x6666U)  
+#define IWDT_WAKEUP_DISABLE_COMMAND  (0x9999U) 
+#define IWDT_RELOAD_COMMAND  (0xAAAAU)    
+
+#define IWDT_RELOAD_MAX_VALUE  (0x0FFFU)  
+
+/*----------------------type definition------------------------*/
+typedef enum _IWDT_CLOCK_PRESCALER{       
+    IWDT_CLOCK_PRESCALER_4   = 0, 
+    IWDT_CLOCK_PRESCALER_8   = 1,    
+    IWDT_CLOCK_PRESCALER_16  = 2,  
+    IWDT_CLOCK_PRESCALER_32  = 3,  
+    IWDT_CLOCK_PRESCALER_64  = 4,  
+    IWDT_CLOCK_PRESCALER_128 = 5,   
+    IWDT_CLOCK_PRESCALER_256 = 6,  
+}IWDT_CLOCK_PRESCALER;  
+
+typedef struct
+{
+    uint32_t Prescaler;                            
+    uint32_t Reload;                              
+    uint32_t Window;     
+    uint32_t Wakeup;  
+} IWDT_InitTypeDef;
+
+typedef struct
+{
+    IWDT_TypeDef                 *Instance;  /*!< Register base address    */  
+    IWDT_InitTypeDef             Init;       /*!< IWDT required parameters */
+} IWDT_HandleTypeDef;
+
+
+ HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt);  
+ HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt);   
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_LPUART.h

@@ -0,0 +1,173 @@
+/*
+  ******************************************************************************
+  * @file    HAL_LPUART.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_LPUART_H__
+#define __HAL_LPUART_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+#define IS_LPUART_INSTANCE(INSTANCE)          ((INSTANCE) == LPUART)
+
+#define LPUART_PEN_INDEX  0   
+#define LPUART_SPS_INDEX  1   
+#define LPUART_EPS_INDEX  2
+
+#define LPUART_IE_RX_INDEX         0  //has wakeup function 
+#define LPUART_IE_TX_FINISH_INDEX  1
+#define LPUART_IE_TX_EMPTY_INDEX   2
+
+#define LPUART_SR_RX_INDEX         0  
+#define LPUART_SR_TX_FINISH_INDEX  1
+#define LPUART_SR_TX_EMPTY_INDEX   2 
+#define LPUART_SR_RX_FULL_INDEX    6    
+#define LPUART_SR_MATCH_INDEX      8  //has wakeup function 
+#define LPUART_SR_START_INDEX      9  //has wakeup function    
+#define LPUART_SR_BITS_ALL         0x1FFU
+
+#define LPUART_WAKEUP_RX_BIT       BIT0              
+#define LPUART_WAKEUP_MATCH_BIT    BIT8
+#define LPUART_WAKEUP_START_BIT    BIT9
+
+#define LPUART_CR_RXE_INDEX  0  
+#define LPUART_CR_TXE_INDEX  1  
+#define LPUART_CR_DMA_EN_INDEX  2   
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */                      
+typedef enum
+{
+    LPUART_RXWKS_START = 0x00, 
+    LPUART_RXWKS_OneByte = 0x01,
+    LPUART_RXWKS_DataCompare = 0x02,     
+    LPUART_RXWKS_NoWake = 0x03,  
+} LPUART_RXWKS;  
+
+typedef enum
+{
+    LPUART_WKCK_Check = 0x00, 
+    LPUART_WKCK_NoCheck = 0x01,
+} LPUART_WKCK ;
+
+/**
+  * @}
+  */
+
+
+
+/*
+ * @brief  LPUART DATABITS  definition
+ */
+typedef enum
+{
+    LPUART_DATABITS_8 = 0x00, 
+    LPUART_DATABITS_7 = 0x01,   
+} LPUART_DATABITS;  
+
+/*
+ * @brief  LPUART STOPBITS  definition
+ */
+typedef enum
+{
+    LPUART_STOPBITS_ONE = 0x00U,  
+    LPUART_STOPBITS_TWO = 0x01U, 
+}LPUART_STOPBITS;  
+
+/*
+ * @brief  LPUART CLOCK_SOURCE  definition
+ */
+typedef enum
+{
+    LPUART_CLOCK_SOURCE_RC32K = 0x00U,  
+    LPUART_CLOCK_SOURCE_XTAL = 0x01U, 
+    LPUART_CLOCK_SOURCE_PLL_DIV = 0x02U, 
+}LPUART_CLOCK_SOURCE;  
+
+/*
+ * @brief  LPUART PARITY  definition
+ */
+typedef enum
+{
+    LPUART_PARITY_NONE = 0x00U,  
+    LPUART_PARITY_SELECT_ODD = 0x01U,  
+    LPUART_PARITY_SELECT_EVEN = 0x02U,             
+    LPUART_PARITY_SELECT_ONE = 0x03U,  
+    LPUART_PARITY_SELECT_ZERO = 0x04U,  
+}LPUART_PARITY_SELECT;  
+
+/** 
+  * @brief  LPUART  Config structure definition
+  */
+typedef struct
+{
+    uint8_t  WordLength;  // LPUART_DATABITS           
+    uint8_t  StopBits;    // LPUART_STOPBITS           
+    uint8_t  Parity;     // LPUART_PARITY_SELECT   
+    uint8_t  ClockSrc;   // LPUART_CLOCK_SOURCE   
+    uint32_t BaudRate;   
+}LPUART_ConfigParam;
+
+/** 
+  * @brief  LPUART  Config structure definition
+  */
+typedef struct
+{
+    uint8_t  Wakeup_Source;  // Wakeup_Source  
+    uint8_t  Wakeup_Check;  // Wakeup_Check 
+    uint8_t  Wakeup_Addr;  // Wakeup_Addr 
+ 
+}LPUART_StopWakeupDef;
+
+
+
+/** 
+  * @brief  LPUART  init structure definition
+  */
+typedef struct
+{
+    LPUART_TypeDef *Instance;
+    LPUART_ConfigParam ConfigParam;  
+    LPUART_StopWakeupDef StopWakeup;  
+    volatile uint8_t *rx_buffer;  
+    volatile uint16_t rx_buffer_size;  
+    volatile uint16_t rx_write_index;  
+    volatile uint16_t rx_read_index;    
+    volatile uint16_t tx_busy;   
+    DMA_HandleTypeDef *dma_rx_handler;  
+	DMA_HandleTypeDef *dma_tx_handler;  	
+}LPUART_HandleTypeDef;
+
+/* HAL_LPUART_Init */
+HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart);
+
+HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart);
+
+void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart);
+
+void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart);
+
+/* HAL_LPUART_Send_Bytes */
+void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);  
+
+/* HAL_LPUART_IRQHander */
+void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart); 
+
+/* HAL_LPUART_Receive_Bytes_Timeout */
+uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms);   
+
+/* HAL_LPUART_Receive_Bytes */
+uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length);
+
+/* HAL_LPUART_DMA_Send_Bytes */
+void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);  
+
+/* HAL_LPUART_Clear_Wakeup_Flags */
+void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits); 
+
+#endif