mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-08 06:55:38 +08:00
Merge branch 'RT-Thread:master' into hal
This commit is contained in:
Jianting (Meco) Man
@@ -35,7 +35,6 @@ jobs:
|
||||
- {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
- {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
- {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
- {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
dir_path:
|
||||
- libraries
|
||||
@@ -1,4 +1,4 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
mainmenu "RT-Thread Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
@@ -8,7 +8,7 @@ config BSP_DIR
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
default "../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
@@ -18,10 +18,5 @@ config PKGS_DIR
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
|
||||
config SOC_ES32F0271LT
|
||||
bool
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
source "$BSP_DIR/drivers/Kconfig"
|
||||
|
||||
source "drivers/Kconfig"
|
||||
@@ -0,0 +1,56 @@
|
||||
# acm32f0x0板级支持包
|
||||
|
||||
## 1. 简介
|
||||
|
||||
ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
|
||||
|
||||
|--------------------------|--------------------|
|
||||
| 硬件 | 描述 |
|
||||
| -------------------------|--------------------|
|
||||
|芯片型号 | ACM32F4XX系列 |
|
||||
|CPU | ARM Cortex-M33 |
|
||||
|主频 | 180MHz |
|
||||
|片内SRAM | 192K |
|
||||
|片内Flash | 512K |
|
||||
|--------------------------|--------------------|
|
||||
|
||||
具体型号及资源请参考上海航芯官方网站[ACM32F4](www.aisinochip.com/index.php/product/child1/id/219.html)。
|
||||
|
||||
## 2. 编译说明
|
||||
|
||||
推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f4xx-nucleo`目录中，运行以下命令：
|
||||
|
||||
`scons`
|
||||
|
||||
来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
|
||||
|
||||
也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。
|
||||
|
||||
## 3. 烧写及执行
|
||||
|
||||
开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
|
||||
|
||||
### 3.1 运行结果
|
||||
|
||||
如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
|
||||
|
||||
## 4. 驱动支持情况及计划
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| ------------- | ------------ | ------------------------------------- |
|
||||
| GPIO | 支持 | PA0, PA1... PF4 ---> PIN: 0, 1...83 |
|
||||
| UART | 支持 | UART1/UART2 |
|
||||
| LED | 支持 | LED1 |
|
||||
|
||||
## 5. 联系人信息
|
||||
|
||||
维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
|
||||
|
||||
## 6. 参考
|
||||
|
||||
* 板子[数据手册][2]
|
||||
* 芯片[数据手册][3]
|
||||
|
||||
[1]: https://www.rt-thread.org/page/download.html
|
||||
[2]: www.aisinochip.com/index.php/product/detail/id/50.html
|
||||
[3]: www.aisinochip.com/index.php/product/detail/id/50.html
|
||||
@@ -1,9 +1,9 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
cwd = str(Dir('#'))
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
@@ -0,0 +1,34 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
from building import *
|
||||
|
||||
TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT
|
||||
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
+3
-3
@@ -2,10 +2,10 @@ Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||
src = Glob('*.c')
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-09-17 AisinoChip the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include <drivers/pin.h>
|
||||
|
||||
#define LED_PIN_NUM 83 /* PF3 */
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_PIN_NUM, PIN_LOW);
|
||||
rt_thread_delay(RT_TICK_PER_SECOND / 2);
|
||||
rt_pin_write(LED_PIN_NUM, PIN_HIGH);
|
||||
rt_thread_delay(RT_TICK_PER_SECOND / 2);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,15 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
#remove other no use files
|
||||
#SrcRemove(src, '*.c')
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-25 AisinoChip first implementation
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define SOC_SRAM_END_ADDR (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
|
||||
|
||||
extern int rt_application_init(void);
|
||||
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#endif
|
||||
|
||||
extern void rt_hw_uart_init(void);
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial EVB board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* system init, clock, NVIC */
|
||||
System_Init();
|
||||
|
||||
/* Configure the SysTick */
|
||||
SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
|
||||
|
||||
rt_hw_uart_init();
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
|
||||
#elif __ICCARM__
|
||||
rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
|
||||
#else
|
||||
/* init memory system */
|
||||
rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
|
||||
#endif
|
||||
#endif /* RT_USING_HEAP */
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-09-22 AisinoCip add board.h to this bsp
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/*-------------------------- UART CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** After configuring corresponding UART or UART DMA, you can use it.
|
||||
*
|
||||
* STEP 1, define macro define related to the serial port opening based on the serial port number
|
||||
* such as #define BSP_USING_UATR1
|
||||
*
|
||||
* STEP 2, according to the corresponding pin of serial port, modify the related serial port information
|
||||
* such as #define UART1_TX_PORT GPIOX -> GPIOA
|
||||
* #define UART1_RX_PORT GPIOX -> GPIOA
|
||||
* #define UART1_TX_PIN GPIO_PIN_X -> GPIO_PIN_9
|
||||
* #define UART1_RX_PIN GPIO_PIN_X -> GPIO_PIN_10
|
||||
*
|
||||
* STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
|
||||
* RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
|
||||
*
|
||||
* STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
|
||||
* such as #define BSP_UART1_RX_USING_DMA
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define UART1_TX_PORT GPIOA
|
||||
#define UART1_RX_PORT GPIOA
|
||||
#define UART1_TX_PIN GPIO_PIN_9
|
||||
#define UART1_RX_PIN GPIO_PIN_10
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#define UART1_RX_DMA_INSTANCE DMA_Channel0
|
||||
#define UART1_RX_DMA_RCC BIT12
|
||||
#define UART1_RX_DMA_IRQ DMA_IRQn
|
||||
#define UART1_RX_DMA_CHANNEL 0
|
||||
#define UART1_RX_DMA_REQUEST REQ6_UART1_RECV
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#define UART1_TX_DMA_INSTANCE DMA_Channel1
|
||||
#define UART1_TX_DMA_RCC BIT12
|
||||
#define UART1_TX_DMA_IRQ DMA_IRQn
|
||||
#define UART1_TX_DMA_CHANNEL 1
|
||||
#define UART1_TX_DMA_REQUEST REQ5_UART1_SEND
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#define UART2_TX_PORT GPIOA
|
||||
#define UART2_RX_PORT GPIOA
|
||||
#define UART2_TX_PIN GPIO_PIN_2
|
||||
#define UART2_RX_PIN GPIO_PIN_3
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#define UART2_RX_DMA_INSTANCE DMA_Channel0
|
||||
#define UART2_RX_DMA_RCC BIT12
|
||||
#define UART2_RX_DMA_IRQ DMA_IRQn
|
||||
#define UART2_RX_DMA_CHANNEL 0
|
||||
#define UART2_RX_DMA_REQUEST REQ8_UART2_RECV
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#define UART2_TX_DMA_INSTANCE DMA_Channel1
|
||||
#define UART2_TX_DMA_RCC BIT12
|
||||
#define UART2_TX_DMA_IRQ DMA_IRQn
|
||||
#define UART2_TX_DMA_CHANNEL 1
|
||||
#define UART2_TX_DMA_REQUEST REQ7_UART2_SEND
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#define UART3_TX_PORT GPIOB
|
||||
#define UART3_RX_PORT GPIOB
|
||||
#define UART3_TX_PIN GPIO_PIN_10
|
||||
#define UART3_RX_PIN GPIO_PIN_11
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#define UART3_RX_DMA_INSTANCE DMA_Channel2
|
||||
#define UART3_RX_DMA_RCC BIT12
|
||||
#define UART3_RX_DMA_IRQ DMA_IRQn
|
||||
#define UART3_RX_DMA_CHANNEL 2
|
||||
#define UART3_RX_DMA_REQUEST REQ29_UART3_RECV
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#define UART3_TX_DMA_INSTANCE DMA_Channel3
|
||||
#define UART3_TX_DMA_RCC BIT12
|
||||
#define UART3_TX_DMA_IRQ DMA_IRQn
|
||||
#define UART3_TX_DMA_CHANNEL 3
|
||||
#define UART3_TX_DMA_REQUEST REQ27_UART3_SEND
|
||||
#endif /* BSP_UART3_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#define UART4_TX_PORT GPIOC
|
||||
#define UART4_RX_PORT GPIOC
|
||||
#define UART4_TX_PIN GPIO_PIN_10
|
||||
#define UART4_RX_PIN GPIO_PIN_11
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#define UART4_RX_DMA_INSTANCE DMA_Channel4
|
||||
#define UART4_RX_DMA_RCC BIT12
|
||||
#define UART4_RX_DMA_IRQ DMA_IRQn
|
||||
#define UART4_RX_DMA_CHANNEL 4
|
||||
#define UART4_RX_DMA_REQUEST REQ46_UART4_RECV
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#define UART4_TX_DMA_INSTANCE DMA_Channel5
|
||||
#define UART4_TX_DMA_RCC BIT12
|
||||
#define UART4_TX_DMA_IRQ DMA_IRQn
|
||||
#define UART4_TX_DMA_CHANNEL 5
|
||||
#define UART4_TX_DMA_REQUEST REQ45_UART4_SEND
|
||||
#endif /* BSP_UART4_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
/*-------------------------- UART CONFIG END --------------------------*/
|
||||
|
||||
/* board configuration */
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x0800;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
export symbol __ICFEDIT_region_RAM_start__;
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
|
||||
@@ -0,0 +1,156 @@
|
||||
/*
|
||||
* linker script for ACM32F4xx with GNU ld
|
||||
*/
|
||||
|
||||
/* describes the location and size of blocks of memory in the target. */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
|
||||
}
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x800;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > CODE
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > CODE
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
||||
+4
-3
@@ -2,13 +2,14 @@
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00020000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
|
||||
LR_IROM1 0x00000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00006000 { ; RW data
|
||||
RW_IRAM1 0x20000000 0x00030000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
+119
-552
File diff suppressed because it is too large
Load Diff
+23
-6
@@ -1,8 +1,8 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
@@ -35,9 +35,15 @@
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
@@ -115,8 +121,11 @@
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
@@ -187,6 +196,10 @@
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
@@ -255,6 +268,10 @@
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
+170
-81
File diff suppressed because it is too large
Load Diff
+80
-25
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -1,11 +1,11 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
* @version V5.0.3
|
||||
* @date 24. June 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -33,7 +33,7 @@
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
+124
-177
File diff suppressed because it is too large
Load Diff
+30
-17
@@ -1,11 +1,11 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -87,7 +87,7 @@
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Pos) | \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
@@ -101,6 +101,21 @@
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
@@ -114,20 +129,19 @@ typedef struct {
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
@@ -140,20 +154,19 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
@@ -267,7 +280,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
@@ -287,7 +300,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
@@ -295,7 +308,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
@@ -303,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file System_Accelerate.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief MCU Accelerate Peripheral Access Layer System header File.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __SYSTEM_ACCELERATE_H__
|
||||
#define __SYSTEM_ACCELERATE_H__
|
||||
|
||||
|
||||
|
||||
/* System_EnableIAccelerate */
|
||||
void System_EnableIAccelerate(void);
|
||||
|
||||
/* System_DisableIAccelerate */
|
||||
void System_DisableIAccelerate(void);
|
||||
|
||||
/* System_EnableDAccelerate */
|
||||
void System_EnableDAccelerate(void);
|
||||
|
||||
/* System_DisableDAccelerate */
|
||||
void System_DisableDAccelerate(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,94 @@
|
||||
/***********************************************************************
|
||||
* All rights reserved.
|
||||
* Filename : aes.h
|
||||
* Description : aes driver header file
|
||||
* Author(s) : Eric
|
||||
* version : V1.0
|
||||
* Modify date : 2016-03-24
|
||||
***********************************************************************/
|
||||
#ifndef __AES_H__
|
||||
#define __AES_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
#define AES_ENCRYPTION 1
|
||||
#define AES_DECRYPTION 0
|
||||
#define AES_ECB_MODE 0
|
||||
#define AES_CBC_MODE 1
|
||||
#define AES_SWAP_ENABLE 1
|
||||
#define AES_SWAP_DISABLE 0
|
||||
|
||||
#define AES_NORMAL_MODE 0x12345678
|
||||
#define AES_SECURITY_MODE 0
|
||||
|
||||
#define AES_KEY_128 0
|
||||
#define AES_KEY_192 1
|
||||
#define AES_KEY_256 2
|
||||
|
||||
#define AES_FAIL 0x00
|
||||
#define AES_PASS 0xa59ada68
|
||||
|
||||
#define BIT_AES (1<<28)
|
||||
|
||||
/************************************************************************
|
||||
* function : delay
|
||||
* Description: delay for a while.
|
||||
* input :
|
||||
* count: count to decrease
|
||||
* return: none
|
||||
************************************************************************/
|
||||
extern void delay(uint32_t count);
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Name: HAL_AES_SetKey
|
||||
* Function: set key of AES
|
||||
* Input:
|
||||
keyin -- pointer to buffer of key
|
||||
key_len -- select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256)
|
||||
swap_en -- AES_SWAP_ENABLE, AES_SWAP_DISABLE
|
||||
* Return: None
|
||||
*******************************************************************************/
|
||||
void HAL_AES_SetKey(UINT32 *keyin, UINT8 key_len, UINT8 swap_en);
|
||||
void HAL_AES_SetKey_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en);
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Name: HAL_AES_Crypt
|
||||
Function: Function for AES encryption and decryption
|
||||
Input:
|
||||
indata -- pointer to buffer of input
|
||||
outdata -- pointer to buffer of result
|
||||
block_len -- block(128bit) length for aes cryption
|
||||
operation -- AES_ENCRYPTION,AES_DECRYPTION
|
||||
mode -- AES_ECB_MODE, AES_CBC_MODE,
|
||||
iv -- initial vector for CBC mode
|
||||
security_mode -- AES_NORMAL_MODE, AES_SECURITY_MDOE£¬
|
||||
Return: None
|
||||
|
||||
*******************************************************************************/
|
||||
uint32_t HAL_AES_Crypt(
|
||||
uint32_t *indata,
|
||||
uint32_t *outdata,
|
||||
uint32_t block_len,
|
||||
uint8_t operation,
|
||||
uint8_t mode,
|
||||
uint32_t *iv,
|
||||
uint32_t security_mode
|
||||
);
|
||||
|
||||
|
||||
uint32_t HAL_AES_Crypt_U8(
|
||||
uint8_t *indata,
|
||||
uint8_t *outdata,
|
||||
uint32_t block_len,
|
||||
uint8_t operation,
|
||||
uint8_t mode,
|
||||
uint8_t *iv,
|
||||
uint32_t security_mode
|
||||
);
|
||||
|
||||
#endif
|
||||
/******************************************************************************
|
||||
* end of file
|
||||
*******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_CRC.h
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_CRC_H__
|
||||
#define __HAL_CRC_H__
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/** @defgroup CRC POLY Reverse
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLY_REV_EN (0x00000400U) /*!< Poly Reverse Enable */
|
||||
#define CRC_POLY_REV_DIS (0x00000000U) /*!< Poly Reverse Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC OUTXOR Reverse
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTXOR_REV_EN (0x00000200U) /*!< OUTXOR Reverse Enable */
|
||||
#define CRC_OUTXOR_REV_DIS (0x00000000U) /*!< OUTXOR Reverse Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC INIT Reverse
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INIT_REV_EN (0x00000100U) /*!< INIT Reverse Enable */
|
||||
#define CRC_INIT_REV_DIS (0x00000000U) /*!< INIT Reverse Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC RSLT Reverse
|
||||
* @{
|
||||
*/
|
||||
#define CRC_RSLT_REV_EN (0x00000080U) /*!< RSLT Reverse Enable */
|
||||
#define CRC_RSLT_REV_DIS (0x00000000U) /*!< RSLT Reverse Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC DATA Reverse
|
||||
* @{
|
||||
*/
|
||||
#define CRC_DATA_REV_DISABLE (0x00000000U) /*!< DATA Reverse Disable */
|
||||
#define CRC_DATA_REV_BY_BYTE (0x00000020U) /*!< DATA Reverse By Byte */
|
||||
#define CRC_DATA_REV_BY_HALFWORD (0x00000040U) /*!< DATA Reverse By HalfWord */
|
||||
#define CRC_DATA_REV_BY_WORD (0x00000060U) /*!< DATA Reverse By Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC Poly Len
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLTY_LEN_32 (0x00000000U) /*!< POLY len = 32bit */
|
||||
#define CRC_POLTY_LEN_16 (0x00000008U) /*!< POLY len = 16bit */
|
||||
#define CRC_POLTY_LEN_8 (0x00000010U) /*!< POLY len = 8bit */
|
||||
#define CRC_POLTY_LEN_7 (0x00000018U) /*!< POLY len = 7bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC Data Len
|
||||
* @{
|
||||
*/
|
||||
#define CRC_DATA_LEN_1B (0x00000000U) /*!< DATA len = 1 Byte */
|
||||
#define CRC_DATA_LEN_2B (0x00000002U) /*!< DATA len = 2 Byte */
|
||||
#define CRC_DATA_LEN_3B (0x00000004U) /*!< DATA len = 3 Byte */
|
||||
#define CRC_DATA_LEN_4B (0x00000006U) /*!< DATA len = 4 Byte */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC RST
|
||||
* @{
|
||||
*/
|
||||
#define CRC_RST_EN (0x00000001U) /*!< RST CRC_DATA To CRC_INIT */
|
||||
#define CRC_RST_DIS (0x00000000U) /*!< RST CRC_DATA To CRC_INIT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PolyRev; /*!< Specifies if the Poly is reversed in CRC
|
||||
This parameter can be a value of @ref CRC POLY Reverse. */
|
||||
uint32_t OutxorRev; /*!< Specifies if the Outxor is reversed in CRC
|
||||
This parameter can be a value of @ref CRC OUTXOR Reverse. */
|
||||
uint32_t InitRev; /*!< Specifies if the Init is reversed in CRC
|
||||
This parameter can be a value of @ref CRC INIT Reverse. */
|
||||
uint32_t RsltRev; /*!< Specifies if the Result is reversed in CRC
|
||||
This parameter can be a value of @ref CRC RSLT Reverse. */
|
||||
uint32_t DataRev; /*!< Specifies if the Data is reversed in CRC
|
||||
This parameter can be a value of @ref CRC DATA Reverse. */
|
||||
uint32_t PolyLen; /*!< Specifies the Poly Len in CRC
|
||||
This parameter can be a value of @ref CRC Poly Len. */
|
||||
uint32_t DataLen; /*!< Specifies the Data Len in CRC
|
||||
This parameter can be a value of @ref CRC Data Len. */
|
||||
uint32_t RST; /*!< Specifies if CRC is reset
|
||||
This parameter can be a value of @ref CRC RST. */
|
||||
|
||||
uint32_t InitData; /*!< This member configures the InitData. */
|
||||
|
||||
uint32_t OutXorData; /*!< This member configures the OutXorData. */
|
||||
|
||||
uint32_t PolyData; /*!< This member configures the PolyData. */
|
||||
|
||||
uint32_t FData; /*!< This member configures the FData. */
|
||||
|
||||
}CRC_InitTypeDef;
|
||||
|
||||
/*
|
||||
* @brief UART handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< CRC registers base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC calculate parameters */
|
||||
|
||||
uint8_t* CRC_Data_Buff; /*!< CRC databuff base address */
|
||||
|
||||
uint32_t CRC_Data_Len; /*!< amount of CRC data to be calculated */
|
||||
|
||||
}CRC_HandleTypeDef;
|
||||
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_CRC_Calculate
|
||||
* Description : Calculate the crc calue of input data.
|
||||
* Input : hcrc: CRC handle.
|
||||
* Output : CRC value
|
||||
* Author : cl Data : 2021
|
||||
**********************************************************************************/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_EFlash.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief Header file of EFlash HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_EFlash_H__
|
||||
#define __HAL_EFlash_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
#define EFLASH_PAGE_SIZE (512UL)
|
||||
|
||||
#define HAL_EFLASH_READ_WORD(Addr) (*(volatile uint32_t *)(Addr)) // Read By Word
|
||||
#define HAL_EFLASH_READ_HALFWORD(Addr) (*(volatile uint16_t *)(Addr)) // Read By Half Word
|
||||
#define HAL_EFLASH_READ_BYTE(Addr) (*(volatile uint8_t *)(Addr)) // Read By Byte
|
||||
|
||||
/******************** Bit definition for EFC_CTRL register ******************/
|
||||
#define EFC_CTRL_CHIP_ERASE_MODE (1 << 2)
|
||||
#define EFC_CTRL_PAGE_ERASE_MODE (1 << 1)
|
||||
#define EFC_CTRL_PROGRAM_MODE (1 << 0)
|
||||
|
||||
/******************** Bit definition for EFC_STATUS register ***************/
|
||||
#define EFC_STATUS_NVR4_LOCK (1 << 4)
|
||||
#define EFC_STATUS_NVR3_LOCK (1 << 3)
|
||||
#define EFC_STATUS_NVR2_LOCK (1 << 2)
|
||||
#define EFC_STATUS_NVR1_LOCK (1 << 1)
|
||||
#define EFC_STATUS_EFLASH_RDY (1 << 0)
|
||||
|
||||
#define RD_WAIT_ENSURE_OK 8
|
||||
#define SET_EFC_RD_WAIT(wait) {EFC->CTRL = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);}
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* HAL_EFlash_Init */
|
||||
void HAL_EFlash_Init(uint32_t fu32_freq);
|
||||
/* HAL_EFlash_ErasePage */
|
||||
bool HAL_EFlash_ErasePage(uint32_t fu32_Addr);
|
||||
|
||||
/* HAL_EFlash_Program_Word */
|
||||
bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_EFlash_EX.h
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of EFlash extention module
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_EFlash_EX_H__
|
||||
#define __HAL_EFlash_EX_H__
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
/* HAL_EFlash_Return_To_Boot */
|
||||
void HAL_EFlash_Return_to_Boot(void);
|
||||
|
||||
/* HAL_EFlash_Init_Para */
|
||||
void HAL_EFlash_Init_Para(uint32_t fu32_freq);
|
||||
|
||||
/* HAL_EFlash_ErasePage_EX */
|
||||
void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);
|
||||
|
||||
/* HAL_EFlash_Program_Word_EX */
|
||||
void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_EXTI.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_EXTI_H__
|
||||
#define __HAL_EXTI_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (0x000001)
|
||||
#define EXTI_LINE_1 (0x000002)
|
||||
#define EXTI_LINE_2 (0x000004)
|
||||
#define EXTI_LINE_3 (0x000008)
|
||||
#define EXTI_LINE_4 (0x000010)
|
||||
#define EXTI_LINE_5 (0x000020)
|
||||
#define EXTI_LINE_6 (0x000040)
|
||||
#define EXTI_LINE_7 (0x000080)
|
||||
#define EXTI_LINE_8 (0x000100)
|
||||
#define EXTI_LINE_9 (0x000200)
|
||||
#define EXTI_LINE_10 (0x000300)
|
||||
#define EXTI_LINE_11 (0x000400)
|
||||
#define EXTI_LINE_12 (0x001000)
|
||||
#define EXTI_LINE_13 (0x002000)
|
||||
#define EXTI_LINE_14 (0x004000)
|
||||
#define EXTI_LINE_15 (0x008000)
|
||||
#define EXTI_LINE_16 (0x010000)
|
||||
#define EXTI_LINE_17 (0x020000)
|
||||
#define EXTI_LINE_18 (0x040000)
|
||||
#define EXTI_LINE_19 (0x080000)
|
||||
#define EXTI_LINE_20 (0x100000)
|
||||
#define EXTI_LINE_21 (0x200000)
|
||||
#define EXTI_LINE_22 (0x400000)
|
||||
#define EXTI_LINE_23 (0x800000)
|
||||
#define EXTI_LINE_MASK (0xFFFFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_INTERRUPT (0x00000001)
|
||||
#define EXTI_MODE_EVENT (0x00000002)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_RISING (0x00000001)
|
||||
#define EXTI_TRIGGER_FALLING (0x00000002)
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32_Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t u32_Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t u32_Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t u32_GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
}EXTI_HandleTypeDef;
|
||||
|
||||
|
||||
/** @defgroup EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_ALL_LINE(LINE) ( (LINE) | (EXTI_LINE_MASK) )
|
||||
|
||||
#define IS_EXTI_MODE(__MODE__) (((__MODE__) == EXTI_MODE_INTERRUPT) || \
|
||||
((__MODE__) == EXTI_MODE_EVENT))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__TRIGGER__) (((__TRIGGER__) == EXTI_TRIGGER_RISING) || \
|
||||
((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \
|
||||
((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
#define IS_EXTI_GPIOSEL(__GPIOSEL__) (((__GPIOSEL__) == EXTI_GPIOA) || \
|
||||
((__GPIOSEL__) == EXTI_GPIOB) || \
|
||||
((__GPIOSEL__) == EXTI_GPIOC) || \
|
||||
((__GPIOSEL__) == EXTI_GPIOD) || \
|
||||
((__GPIOSEL__) == EXTI_GPIOE) || \
|
||||
((__GPIOSEL__) == EXTI_GPIOF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @brief __HAL_EXTI_LINE_IT_ENABLE
|
||||
* @param __LINE__: EXTI line.
|
||||
* This parameter can be a value of @ref EXTI_Line
|
||||
*/
|
||||
#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__) (EXTI->IENR |= (__LINE__))
|
||||
|
||||
/** @brief __HAL_EXTI_LINE_IT_DISABLE
|
||||
* @param __LINE__: EXTI line.
|
||||
* This parameter can be a value of @ref EXTI_Line
|
||||
*/
|
||||
#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__) (EXTI->IENR &= ~(__LINE__))
|
||||
|
||||
/** @brief __HAL_EXTI_LINE_EVENT_ENABLE
|
||||
* @param __LINE__: EXTI line.
|
||||
* This parameter can be a value of @ref EXTI_Line
|
||||
*/
|
||||
#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__) (EXTI->EENR |= (__LINE__))
|
||||
|
||||
/** @brief __HAL_EXTI_LINE_EVENT_DISABLE
|
||||
* @param __LINE__: EXTI line.
|
||||
* This parameter can be a value of @ref EXTI_Line
|
||||
*/
|
||||
#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__) (EXTI->EENR &= ~(__LINE__))
|
||||
|
||||
|
||||
/* HAL_EXTI_IRQHandler */
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart);
|
||||
|
||||
/* HAL_EXTI_SetConfigLine */
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/* HAL_EXTI_SoftTrigger */
|
||||
void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/* HAL_EXTI_GetPending */
|
||||
bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/* HAL_EXTI_ClearPending */
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/* HAL_EXTI_ClearAllPending */
|
||||
void HAL_EXTI_ClearAllPending(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,170 @@
|
||||
|
||||
#ifndef __FAU_H_
|
||||
#define __FAU_H_
|
||||
|
||||
#define RANGE 2147483648U //2^31
|
||||
#define CORDIC_F_31 0xD2C90A46 // CORDIC gain F
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 1 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_1(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 2 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_2(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 3 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_3(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 4 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_4(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 5 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_5(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 6 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_6(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 7 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_7(int angle_para, int* cos_data, int* sin_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_CosSin( precision 8 )
|
||||
* Description : calculate the sin & cos value of the input angle
|
||||
* Input : - angle_para : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
|
||||
* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format]
|
||||
- * sin_data : the sin value of the input angle[range[-1,1],Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_CosSin_8(int angle_para, int* cos_data, int* sin_data);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 1 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_1(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 2 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_2(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 3 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_3(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 4 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_4(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 5 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_5(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 6 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_6(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 7 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_7(int x, int y, int*sqrt_data, int* atan_data);
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_CORDIC_AtanSqrt( precision 8 )
|
||||
* Description : calculate the atan & sqrt value of the input x,y
|
||||
* Input : - x : input x data[range[-1,1],Q31 format];
|
||||
* : - y : input y data[range[-1,1],Q31 format];
|
||||
: - precision : the precison used in calculation
|
||||
* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format]
|
||||
- * atan_data : the atan value of the input x,y[Q31 format]
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_CORDIC_AtanSqrt_8(int x, int y, int*sqrt_data, int* atan_data);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_Uart.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief Header file of UART HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_FSUSB_H__
|
||||
#define __HAL_FSUSB_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
#define HIGH_SPEED 1
|
||||
#define FULL_SPEED 0
|
||||
|
||||
#define USB_EP0 0
|
||||
#define USB_EP1 1
|
||||
#define USB_EP2 2
|
||||
#define USB_EP3 3
|
||||
#define USB_EP4 4
|
||||
|
||||
#define USB_EP_IN USB_EP1
|
||||
#define USB_EP_OUT USB_EP1
|
||||
|
||||
#define EP_DIR_IN 0x80
|
||||
#define EP_DIR_OUT 0x00
|
||||
|
||||
#define HID_REPORT_SIZE 1024
|
||||
|
||||
#define EP0_MAX_PACKET_SIZE 64
|
||||
#define EPX_MAX_PACKET_SIZE 64
|
||||
//#define EPX_MAX_PACKET_SIZE_HS 512
|
||||
//#define EPX_MAX_PACKET_SIZE_FS 64
|
||||
|
||||
#define MASK_EPX_IN(x) (1<<(6+3*x))
|
||||
#define MASK_EPX_OUT(x) (1<<(7+3*x))
|
||||
#define MASK_EPX_ACK(x) (1<<(8+3*x))
|
||||
#define MASK_EPX_TIMEOUT(x) (1<< (25+x))
|
||||
|
||||
typedef __PACKED_STRUCT _device_request
|
||||
{
|
||||
uint8_t bmRequestType;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
} DEVICE_REQUEST;
|
||||
|
||||
|
||||
|
||||
#define USB_BUS_RESET 0x01
|
||||
#define USB_SUSPEND 0x02
|
||||
#define USB_RESUME 0x04
|
||||
#define USB_SOF 0x08
|
||||
#define USB_SETUPTOK 0x10
|
||||
#define USB_EP0_SETUP_PACKET 0x20
|
||||
#define USB_EP0_IN 0x40
|
||||
#define USB_EP0_OUT_PACKET 0x80
|
||||
#define USB_EP0_ACK 0x100
|
||||
#define USB_EP1_IN 0x200
|
||||
#define USB_EP1_OUT_PACKET 0x400
|
||||
#define USB_EP1_ACK 0x800
|
||||
#define USB_EP2_IN 0x1000
|
||||
#define USB_EP2_OUT_PACKET 0x2000
|
||||
#define USB_EP2_ACK 0x4000
|
||||
#define USB_EP3_IN 0x8000
|
||||
#define USB_EP3_OUT_PACKET 0x10000
|
||||
#define USB_EP3_ACK 0x20000
|
||||
#define USB_EP4_IN 0x40000
|
||||
#define USB_EP4_OUT_PACKET 0x80000
|
||||
#define USB_EP4_ACK 0x100000
|
||||
#define USB_IN_TIMEOUT 0x200000
|
||||
#define USB_SETADDR 0x400000
|
||||
#define USB_CRC_ERR 0x800000
|
||||
#define USB_MORETHAN_64 0x1000000
|
||||
#define USB_EP0_IN_ERR 0x2000000
|
||||
#define USB_EP1_IN_ERR 0x4000000
|
||||
#define USB_EP2_IN_ERR 0x8000000
|
||||
#define USB_EP3_IN_ERR 0x10000000
|
||||
#define USB_EP4_IN_ERR 0x20000000
|
||||
#define USB_NOEOP_ERR 0x40000000
|
||||
#define USB_TOGGLE_ERR 0x80000000
|
||||
|
||||
|
||||
|
||||
#define ERROR_OUT_OUT 4 // received a same out packet
|
||||
#define ERROR_IN_OUT 2 // received a pakcet when try to send packet
|
||||
|
||||
|
||||
|
||||
uint32_t HAL_FSUSB_Init(void);
|
||||
void HAL_FSUSB_Read_EP_MEM8(uint8_t *dst, uint32_t length, uint32_t fifo_offset, uint8_t ep_index);
|
||||
uint8_t HAL_FSUSB_Send_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index);
|
||||
void HAL_FSUSB_Receive_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index);
|
||||
uint16_t HAL_USB_Get_Stall_Status(uint8_t ep_index, uint8_t ep_dir);
|
||||
void HAL_FSUSB_EP0_Send_Empty_Packet(void);
|
||||
void HAL_FSUSB_EP0_Send_Stall(void);
|
||||
void usb_clear_stall(uint8_t ep_index, uint8_t ep_dir);
|
||||
void usb_send_stall(uint8_t ep_index, uint8_t ep_dir);
|
||||
uint16_t HAL_FSUSB_Get_FIFO_Length(uint8_t ep_index);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,53 @@
|
||||
/***********************************************************************f
|
||||
* Filename : hrng.h
|
||||
* Description : hrng header file
|
||||
* Author(s) : cc
|
||||
* version : V1.0
|
||||
* Modify date : 2021-03-24
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __HRNG_H__
|
||||
#define __HRNG_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/*********************************************************************************
|
||||
* Function Name : HAL_HRNG_Initial
|
||||
* Description : initial hrng module
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*********************************************************************************/
|
||||
void HAL_HRNG_Initial(void);
|
||||
|
||||
/*********************************************************************************
|
||||
* Function Name : HAL_HRNG_GetHrng_8
|
||||
* Description : get 8bit random number
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : 8 bit random number
|
||||
*********************************************************************************/
|
||||
UINT8 HAL_HRNG_GetHrng_8(void);
|
||||
|
||||
/*********************************************************************************
|
||||
* Function Name : HAL_HRNG_GetHrng_32
|
||||
* Description : get 32bit random number
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : 32 bit random number
|
||||
*********************************************************************************/
|
||||
UINT32 HAL_HRNG_GetHrng_32(void);
|
||||
|
||||
/*********************************************************************************
|
||||
* Function Name : HAL_HRNG_GetHrng
|
||||
* Description : get random number
|
||||
* Input : byte_len : the byte length of random number
|
||||
* Output : *hdata : the start address of random number
|
||||
* Return : 0: hrng data is ok; 1: hrng data is bad
|
||||
*********************************************************************************/
|
||||
UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,56 @@
|
||||
|
||||
/***********************************************************************
|
||||
* Filename : HAL_IWDT.h
|
||||
* Description : IHAL WDT driver header file
|
||||
* Author(s) : CWT
|
||||
* version : V1.0
|
||||
* Modify date : 2020-04-17
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __HAL_IWDT_H__
|
||||
#define __HAL_IWDT_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
/**************** Bit definition for IWDT register ***********************/
|
||||
|
||||
|
||||
/*----------------------macro definition------------------------*/
|
||||
#define IWDT_ENABLE_COMMAND (0xCCCCU)
|
||||
#define IWDT_WRITE_ENABLE_COMMAND (0x5555U)
|
||||
#define IWDT_WAKEUP_ENABLE_COMMAND (0x6666U)
|
||||
#define IWDT_WAKEUP_DISABLE_COMMAND (0x9999U)
|
||||
#define IWDT_RELOAD_COMMAND (0xAAAAU)
|
||||
|
||||
#define IWDT_RELOAD_MAX_VALUE (0x0FFFU)
|
||||
|
||||
/*----------------------type definition------------------------*/
|
||||
typedef enum _IWDT_CLOCK_PRESCALER{
|
||||
IWDT_CLOCK_PRESCALER_4 = 0,
|
||||
IWDT_CLOCK_PRESCALER_8 = 1,
|
||||
IWDT_CLOCK_PRESCALER_16 = 2,
|
||||
IWDT_CLOCK_PRESCALER_32 = 3,
|
||||
IWDT_CLOCK_PRESCALER_64 = 4,
|
||||
IWDT_CLOCK_PRESCALER_128 = 5,
|
||||
IWDT_CLOCK_PRESCALER_256 = 6,
|
||||
}IWDT_CLOCK_PRESCALER;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler;
|
||||
uint32_t Reload;
|
||||
uint32_t Window;
|
||||
uint32_t Wakeup;
|
||||
} IWDT_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
IWDT_TypeDef *Instance; /*!< Register base address */
|
||||
IWDT_InitTypeDef Init; /*!< IWDT required parameters */
|
||||
} IWDT_HandleTypeDef;
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt);
|
||||
HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt);
|
||||
#endif
|
||||
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_LPUART.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_LPUART_H__
|
||||
#define __HAL_LPUART_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART)
|
||||
|
||||
#define LPUART_PEN_INDEX 0
|
||||
#define LPUART_SPS_INDEX 1
|
||||
#define LPUART_EPS_INDEX 2
|
||||
|
||||
#define LPUART_IE_RX_INDEX 0 //has wakeup function
|
||||
#define LPUART_IE_TX_FINISH_INDEX 1
|
||||
#define LPUART_IE_TX_EMPTY_INDEX 2
|
||||
|
||||
#define LPUART_SR_RX_INDEX 0
|
||||
#define LPUART_SR_TX_FINISH_INDEX 1
|
||||
#define LPUART_SR_TX_EMPTY_INDEX 2
|
||||
#define LPUART_SR_RX_FULL_INDEX 6
|
||||
#define LPUART_SR_MATCH_INDEX 8 //has wakeup function
|
||||
#define LPUART_SR_START_INDEX 9 //has wakeup function
|
||||
#define LPUART_SR_BITS_ALL 0x1FFU
|
||||
|
||||
#define LPUART_WAKEUP_RX_BIT BIT0
|
||||
#define LPUART_WAKEUP_MATCH_BIT BIT8
|
||||
#define LPUART_WAKEUP_START_BIT BIT9
|
||||
|
||||
#define LPUART_CR_RXE_INDEX 0
|
||||
#define LPUART_CR_TXE_INDEX 1
|
||||
#define LPUART_CR_DMA_EN_INDEX 2
|
||||
|
||||
/** @defgroup GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LPUART_RXWKS_START = 0x00,
|
||||
LPUART_RXWKS_OneByte = 0x01,
|
||||
LPUART_RXWKS_DataCompare = 0x02,
|
||||
LPUART_RXWKS_NoWake = 0x03,
|
||||
} LPUART_RXWKS;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
LPUART_WKCK_Check = 0x00,
|
||||
LPUART_WKCK_NoCheck = 0x01,
|
||||
} LPUART_WKCK ;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* @brief LPUART DATABITS definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LPUART_DATABITS_8 = 0x00,
|
||||
LPUART_DATABITS_7 = 0x01,
|
||||
} LPUART_DATABITS;
|
||||
|
||||
/*
|
||||
* @brief LPUART STOPBITS definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LPUART_STOPBITS_ONE = 0x00U,
|
||||
LPUART_STOPBITS_TWO = 0x01U,
|
||||
}LPUART_STOPBITS;
|
||||
|
||||
/*
|
||||
* @brief LPUART CLOCK_SOURCE definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LPUART_CLOCK_SOURCE_RC32K = 0x00U,
|
||||
LPUART_CLOCK_SOURCE_XTAL = 0x01U,
|
||||
LPUART_CLOCK_SOURCE_PLL_DIV = 0x02U,
|
||||
}LPUART_CLOCK_SOURCE;
|
||||
|
||||
/*
|
||||
* @brief LPUART PARITY definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LPUART_PARITY_NONE = 0x00U,
|
||||
LPUART_PARITY_SELECT_ODD = 0x01U,
|
||||
LPUART_PARITY_SELECT_EVEN = 0x02U,
|
||||
LPUART_PARITY_SELECT_ONE = 0x03U,
|
||||
LPUART_PARITY_SELECT_ZERO = 0x04U,
|
||||
}LPUART_PARITY_SELECT;
|
||||
|
||||
/**
|
||||
* @brief LPUART Config structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WordLength; // LPUART_DATABITS
|
||||
uint8_t StopBits; // LPUART_STOPBITS
|
||||
uint8_t Parity; // LPUART_PARITY_SELECT
|
||||
uint8_t ClockSrc; // LPUART_CLOCK_SOURCE
|
||||
uint32_t BaudRate;
|
||||
}LPUART_ConfigParam;
|
||||
|
||||
/**
|
||||
* @brief LPUART Config structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Wakeup_Source; // Wakeup_Source
|
||||
uint8_t Wakeup_Check; // Wakeup_Check
|
||||
uint8_t Wakeup_Addr; // Wakeup_Addr
|
||||
|
||||
}LPUART_StopWakeupDef;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief LPUART init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPUART_TypeDef *Instance;
|
||||
LPUART_ConfigParam ConfigParam;
|
||||
LPUART_StopWakeupDef StopWakeup;
|
||||
volatile uint8_t *rx_buffer;
|
||||
volatile uint16_t rx_buffer_size;
|
||||
volatile uint16_t rx_write_index;
|
||||
volatile uint16_t rx_read_index;
|
||||
volatile uint16_t tx_busy;
|
||||
DMA_HandleTypeDef *dma_rx_handler;
|
||||
DMA_HandleTypeDef *dma_tx_handler;
|
||||
}LPUART_HandleTypeDef;
|
||||
|
||||
/* HAL_LPUART_Init */
|
||||
HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart);
|
||||
|
||||
HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart);
|
||||
|
||||
void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart);
|
||||
|
||||
void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart);
|
||||
|
||||
/* HAL_LPUART_Send_Bytes */
|
||||
void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);
|
||||
|
||||
/* HAL_LPUART_IRQHander */
|
||||
void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart);
|
||||
|
||||
/* HAL_LPUART_Receive_Bytes_Timeout */
|
||||
uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms);
|
||||
|
||||
/* HAL_LPUART_Receive_Bytes */
|
||||
uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length);
|
||||
|
||||
/* HAL_LPUART_DMA_Send_Bytes */
|
||||
void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);
|
||||
|
||||
/* HAL_LPUART_Clear_Wakeup_Flags */
|
||||
void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_OPA.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief Header file of OPA HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_OPA_H__
|
||||
#define __HAL_OPA_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/**************** Bit definition for OPA_CR1 and OPA_CR2 register **************************/
|
||||
#define OPA_CSR_LOCK (BIT31)
|
||||
#define OPA_CSR_HSM (BIT28)
|
||||
#define OPA_CSR_GAIN_SEL_POS (23U)
|
||||
#define OPA_CSR_GAIN_SEL_MASK (BIT27|BIT26|BIT25|BIT24|BIT23)
|
||||
#define OPA_CSR_POL_SEL_POS (21U)
|
||||
#define OPA_CSR_POL_SEL_MASK (BIT22|BIT21)
|
||||
#define OPA_CSR_VINM0_SEL_POS (BIT20)
|
||||
#define OPA_CSR_MODE_SEL_POS (18U)
|
||||
#define OPA_CSR_MODE_SEL_MASK (BIT19|BIT18)
|
||||
#define OPA_CSR_VINP_SEL_POS (16U)
|
||||
#define OPA_CSR_VINP_SEL_MASK (BIT17|BIT16)
|
||||
#define OPA_CSR_OUT_SEL_POS (14U)
|
||||
#define OPA_CSR_OUT_SEL_MASK (BIT14|BIT15)
|
||||
#define OPA_CSR_TRIM_OSN_POS (9U)
|
||||
#define OPA_CSR_TRIM_OSN_MASK (BIT13|BIT12|BIT11|BIT10|BIT9)
|
||||
#define OPA_CSR_TRIM_OSP_POS (4U)
|
||||
#define OPA_CSR_TRIM_OSP_MASK (BIT8|BIT7|BIT6|BIT5|BIT4)
|
||||
#define OPA_CSR_CAL_OUT (BIT3)
|
||||
#define OPA_CSR_CAL_NEN (BIT2)
|
||||
#define OPA_CSR_CAL_PEN (BIT1)
|
||||
#define OPA_CSR_EN (BIT0)
|
||||
|
||||
/** @defgroup OPAx Index
|
||||
* @{
|
||||
*/
|
||||
#define OPA1 (0x01)
|
||||
#define OPA2 (0x02)
|
||||
#define OPA3 (0x03)
|
||||
|
||||
/** @defgroup HSM driver mode
|
||||
* @{
|
||||
*/
|
||||
#define OPA_HSM_LOW (0u)
|
||||
#define OPA_HSM_HIGH (1u)
|
||||
|
||||
/** @defgroup OPA Gain select.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_GAIN_64_63 (0u)
|
||||
#define OPA_GAIN_32_31 (1u)
|
||||
#define OPA_GAIN_16_15 (2u)
|
||||
#define OPA_GAIN_8_7 (4u)
|
||||
#define OPA_GAIN_4_3 (8u)
|
||||
#define OPA_GAIN_2_1 (16u)
|
||||
|
||||
/** @defgroup Polarity select.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_POL_NONINVERT (0u)
|
||||
#define OPA_POL_INVERT (1u)
|
||||
|
||||
/** @defgroup OPA work mode select.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_MODE_SA (0u)
|
||||
#define OPA_MODE_UG (1u)
|
||||
#define OPA_MODE_PGA (2u)
|
||||
#define OPA_MODE_SA1 (3u)
|
||||
|
||||
/** @defgroup OPA VINP vin p select.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_VINP_0 (0u)
|
||||
#define OPA_VINP_1 (1u)
|
||||
#define OPA_VINP_2 (2u)
|
||||
#define OPA_VINP_3 (3u)
|
||||
|
||||
/** @defgroup OPA output select.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_OUT_GPIO (0u)
|
||||
#define OPA_OUT_INTERNAL (1u)
|
||||
|
||||
/** @defgroup OPA VINM0 enable.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_CSR_VINM0_DISABLE (0U)
|
||||
#define OPA_CSR_VINM0_ENABLE (1U)
|
||||
|
||||
/** @defgroup OPA trim enable.
|
||||
* @{
|
||||
*/
|
||||
#define OPA_CSR_TRIM_DISABLE (0U)
|
||||
#define OPA_CSR_TRIM_ENABLE (1U)
|
||||
|
||||
/**
|
||||
* @brief OPA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t OpaX; /*!< Specify witch opa be selected */
|
||||
uint8_t Hsm; /*!< Specify the opa HSM driver mode:OPA_HSM_LOW or OPA_HSM_HIGH */
|
||||
uint8_t Gain; /*!< Specify the opa gain select */
|
||||
uint8_t PolSel; /*!< Specify the opa Polarity select */
|
||||
uint8_t VinM0En; /*!< Specify the opa VinM0 enable */
|
||||
uint8_t OpaMode; /*!< Specify the opa work mode select */
|
||||
uint8_t VinPSel; /*!< Specify the opa VINP vin p select */
|
||||
uint8_t OutSel; /*!< Specify the opa output select */
|
||||
uint8_t TrimEn; /*!< Specify if the opa auto trim */
|
||||
}OPA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief OPA handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
OPA_TypeDef *Instance; /*!< Register base address */
|
||||
OPA_InitTypeDef Init; /*!< OPA required parameters */
|
||||
} OPA_HandleTypeDef;
|
||||
|
||||
/******************************** OPA Instances *******************************/
|
||||
#define IS_OPA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPA))
|
||||
|
||||
/******************************** OPA OPAX definition*******************************/
|
||||
#define IS_OPA_ALL_OPAX(_OPAX) (((_OPAX) == OPA1) || \
|
||||
((_OPAX) == OPA2) || \
|
||||
((_OPAX) == OPA3))
|
||||
|
||||
/******************************** OPA HSM definition*******************************/
|
||||
#define IS_OPA_ALL_HSM(_HSM) (((_HSM) == OPA_HSM_LOW) || \
|
||||
((_HSM) == OPA_HSM_HIGH))
|
||||
|
||||
/******************************** OPA GAIN definition*******************************/
|
||||
#define IS_OPA_ALL_GAIN(_GAIN) (((_GAIN) == OPA_GAIN_64_63) || \
|
||||
((_GAIN) == OPA_GAIN_32_31) || \
|
||||
((_GAIN) == OPA_GAIN_16_15) || \
|
||||
((_GAIN) == OPA_GAIN_8_7) || \
|
||||
((_GAIN) == OPA_GAIN_4_3) || \
|
||||
((_GAIN) == OPA_GAIN_2_1))
|
||||
|
||||
/******************************** OPA Polarity definition*******************************/
|
||||
#define IS_OPA_ALL_POL(_POL) (((_POL) == OPA_POL_NONINVERT) || \
|
||||
((_POL) == OPA_POL_INVERT))
|
||||
|
||||
/******************************** OPA work mode definition*******************************/
|
||||
#define IS_OPA_ALL_MODE(_MODE) (((_MODE) == OPA_MODE_SA) || \
|
||||
((_MODE) == OPA_MODE_UG) || \
|
||||
((_MODE) == OPA_MODE_PGA) || \
|
||||
((_MODE) == OPA_MODE_SA1))
|
||||
|
||||
/******************************** OPA VINP select definition*******************************/
|
||||
#define IS_OPA_ALL_VINP(_VINP) (((_VINP) == OPA_VINP_0) || \
|
||||
((_VINP) == OPA_VINP_1) || \
|
||||
((_VINP) == OPA_VINP_2) || \
|
||||
((_VINP) == OPA_VINP_3))
|
||||
|
||||
/******************************** OPA OUT select definition*******************************/
|
||||
#define IS_OPA_ALL_OUT(_OUT) (((_OUT) == OPA_OUT_GPIO) || \
|
||||
((_OUT) == OPA_OUT_INTERNAL))
|
||||
|
||||
/******************************** OPA VINM0 enable definition*******************************/
|
||||
#define IS_OPA_ALL_VINM0(_VINM0) (((_VINM0) == OPA_CSR_VINM0_DISABLE) || \
|
||||
((_VINM0) == OPA_CSR_VINM0_ENABLE))
|
||||
|
||||
/******************************** OPA trim enable definition*******************************/
|
||||
#define IS_OPA_ALL_TRIM(_TRIM) (((_TRIM) == OPA_CSR_TRIM_DISABLE) || \
|
||||
((_TRIM) == OPA_CSR_TRIM_ENABLE))
|
||||
|
||||
/* Function : HAL_OPA */
|
||||
void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa);
|
||||
void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa);
|
||||
HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa);
|
||||
HAL_StatusTypeDef HAL_OPA_DeInit(OPA_HandleTypeDef* hopa);
|
||||
HAL_StatusTypeDef HAL_OPA_Enable(OPA_HandleTypeDef* hopa);
|
||||
HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa);
|
||||
HAL_StatusTypeDef HAL_OPA_Lock(OPA_HandleTypeDef* hopa);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,77 @@
|
||||
/***********************************************************************
|
||||
* Filename : sha1.h
|
||||
* Description : sha1 header file
|
||||
* Author(s) : firmware team
|
||||
* version : V1.0
|
||||
* Modify date : 2020-07-29
|
||||
***********************************************************************/
|
||||
#ifndef __SHA1_H__
|
||||
#define __SHA1_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
/**********************************************************
|
||||
* structure
|
||||
**********************************************************/
|
||||
//SHA1 context
|
||||
typedef struct {
|
||||
UINT32 state[5]; //state (ABCD)
|
||||
UINT32 count[2]; // number of bits, modulo 2^64 (msb first)
|
||||
uint8_t buffer[64]; // input buffer
|
||||
} SHA1_CTX;
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA1_Init
|
||||
* Description : SHA1 initialization. Begins an SHA1 operation, writing a new context.
|
||||
* Input : None
|
||||
* Output : - *context : the point of sha1 context
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA1_Init(SHA1_CTX *context);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA1_Update
|
||||
* Description : SHA1 block update operation. Continues an SHA1 message-digest
|
||||
* : operation, processing another message block, and updating the
|
||||
* : context.
|
||||
* Input : - *context : context before transform
|
||||
* : - *input : input message
|
||||
* : - inputlen : the byte length of input message
|
||||
* Output : - *context : context after transform
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA1_Update(SHA1_CTX *context,uint8_t *input,UINT32 inputLen);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA1_Final
|
||||
* Description : SHA1 finalization. Ends an MD5 message-digest operation, writing the
|
||||
* : the message digest and zeroizing the context.
|
||||
* Input : - *context : context before transform
|
||||
* Output : - *digest : message digest
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA1_Final(uint8_t *digest, SHA1_CTX *context);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA1_Hash
|
||||
* Description : transform message to digest in SHA1 algorithm
|
||||
* Input : - *pDataIn : input message to be tranformed;
|
||||
: - DataLen : the byte length of message;
|
||||
* Output : - *pDigest : output the digest;
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA1_Hash(uint8_t *pDataIn,UINT32 DataLen,uint8_t *pDigest);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : SHA_encode
|
||||
* Description : Encodes input (UINT32) into output (unsigned char)[Big-Endian]
|
||||
* Input : - *input : input data to be tranformed;
|
||||
: - len : byte len of the input data(len is a multiple of 4);
|
||||
* Output : - *output : output data;
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void SHA_encode (uint8_t *output, UINT32 *input, UINT32 len);
|
||||
void SHA_memcpy (uint8_t *output,uint8_t *input, UINT32 len);
|
||||
void SHA_memset (uint8_t *output, int value, UINT32 len);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,77 @@
|
||||
/***********************************************************************
|
||||
* Filename : sha256.h
|
||||
* Description : sha256 header file
|
||||
* Author(s) : Eric
|
||||
* version : V1.0
|
||||
* Modify date : 2020-07-09
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __SHA256_H__
|
||||
#define __SHA256_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/**********************************************************
|
||||
* structure
|
||||
**********************************************************/
|
||||
//SHA256 context
|
||||
typedef struct {
|
||||
UINT32 state[8]; //state (ABCD)
|
||||
UINT32 count[2]; // number of bits, modulo 2^64 (msb first)
|
||||
uint8_t buffer[64]; // input buffer
|
||||
} SHA256_CTX;
|
||||
|
||||
/**********************************************************
|
||||
* extern functions
|
||||
***********************************************************/
|
||||
void SHA_memcpy (uint8_t *output,uint8_t *input, UINT32 len);
|
||||
void SHA_memset (uint8_t *output, int value, UINT32 len);
|
||||
void SHA_encode (uint8_t *output, UINT32 *input, UINT32 len);
|
||||
/**********************************************************
|
||||
* extern variable
|
||||
***********************************************************/
|
||||
extern const unsigned char PADDING[128];
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA256_Init
|
||||
* Description : SHA256 initialization. Begins an SHA1 operation, writing a new context.
|
||||
* Input : None
|
||||
* Output : - *context : the point of sha1 context
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA256_Init(SHA256_CTX *context);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA256_Update
|
||||
* Description : SHA256 block update operation. Continues an SHA1 message-digest
|
||||
* : operation, processing another message block, and updating the
|
||||
* : context.
|
||||
* Input : - *context : context before transform
|
||||
* : - *input : input message
|
||||
* : - inputlen : the byte length of input message
|
||||
* Output : - *context : context after transform
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA256_Update(SHA256_CTX *context, uint8_t *input,UINT32 inputLen);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA256_Final
|
||||
* Description : SHA256 finalization. Ends an SHA256 message-digest operation, writing the
|
||||
* : the message digest and zeroizing the context.
|
||||
* Input : - *context : context before transform
|
||||
* Output : - *digest : message digest
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA256_Final(uint8_t *digest, SHA256_CTX *context);
|
||||
|
||||
/**************************************************************************
|
||||
* Function Name : HAL_SHA256_Hash
|
||||
* Description : transform message to digest in SHA1 algorithm
|
||||
* Input : - *pDataIn : input message to be tranformed;
|
||||
: - DataLen : the byte length of message;
|
||||
* Output : - *pDigest : output the digest;
|
||||
* Return : None
|
||||
**************************************************************************/
|
||||
void HAL_SHA256_Hash(uint8_t *pDataIn,UINT32 DataLen,uint8_t *pDigest);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,128 @@
|
||||
/***********************************************************************
|
||||
* Filename : hal_timer_ex.h
|
||||
* Description : timer driver header file
|
||||
* Author(s) : xwl
|
||||
* version : V1.0
|
||||
* Modify date : 2021-03-24
|
||||
***********************************************************************/
|
||||
#ifndef __HAL_TIMER_EX_H__
|
||||
#define __HAL_TIMER_EX_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
#define TIM_BDTR_DTG_Pos (0U)
|
||||
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
|
||||
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
||||
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
|
||||
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
|
||||
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
|
||||
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
|
||||
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
|
||||
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
|
||||
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
|
||||
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
|
||||
|
||||
#define TIM_BDTR_LOCK_Pos (8U)
|
||||
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
|
||||
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
|
||||
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
|
||||
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
|
||||
|
||||
#define TIM_BDTR_OSSI_Pos (10U)
|
||||
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
|
||||
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
|
||||
#define TIM_BDTR_OSSR_Pos (11U)
|
||||
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
|
||||
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
|
||||
#define TIM_BDTR_BKE_Pos (12U)
|
||||
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
|
||||
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
|
||||
#define TIM_BDTR_BKP_Pos (13U)
|
||||
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
|
||||
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
|
||||
#define TIM_BDTR_AOE_Pos (14U)
|
||||
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
|
||||
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
|
||||
#define TIM_BDTR_MOE_Pos (15U)
|
||||
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
|
||||
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
|
||||
|
||||
#define TIM_BDTR_BKF_Pos (16U)
|
||||
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
|
||||
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
|
||||
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
|
||||
#define TIM_BREAKINPUT_BRK 0x00000001U
|
||||
|
||||
#define TIM1_AF1_BKINE_Pos (0U)
|
||||
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
|
||||
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
|
||||
#define TIM1_AF1_BKCMP1E_Pos (1U)
|
||||
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
|
||||
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
|
||||
#define TIM1_AF1_BKCMP2E_Pos (2U)
|
||||
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
|
||||
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
|
||||
#define TIM1_AF1_BKINP_Pos (9U)
|
||||
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
|
||||
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
|
||||
#define TIM1_AF1_BKCMP1P_Pos (10U)
|
||||
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
|
||||
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
|
||||
#define TIM1_AF1_BKCMP2P_Pos (11U)
|
||||
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
|
||||
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OffStateRunMode; // TIM off state in run mode
|
||||
uint32_t OffStateIDLEMode; // TIM off state in IDLE mode
|
||||
uint32_t LockLevel; // TIM Lock level
|
||||
uint32_t DeadTime; // TIM dead Time
|
||||
uint32_t BreakState; // TIM Break State
|
||||
uint32_t BreakPolarity; // TIM Break input polarity
|
||||
uint32_t BreakFilter; // Specifies the break input filter.
|
||||
uint32_t AutomaticOutput; // TIM Automatic Output Enable state
|
||||
} TIM_BreakDeadTimeConfigTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Specifies the source of the timer break input.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source */
|
||||
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
|
||||
uint32_t Polarity; /*!< Specifies the break input source polarity.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
|
||||
}
|
||||
TIMEx_BreakInputConfigTypeDef;
|
||||
|
||||
/******************* Bit definition for TIM_TISEL register *********************/
|
||||
#define TIM_TISEL_TI1SEL_Pos (0U)
|
||||
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
|
||||
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
|
||||
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
|
||||
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
|
||||
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
|
||||
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define TIM_TISEL_TI2SEL_Pos (8U)
|
||||
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
|
||||
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
|
||||
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
|
||||
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
|
||||
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
|
||||
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_UART_EX.h
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief Header file of UART EX HAL module.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_UART_EX_H__
|
||||
#define __HAL_UART_EX_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/**************** Bit definition for UART IE register ***********************/
|
||||
#define UART_EX_IE_BCNTI BIT12
|
||||
#define UART_EX_IE_LBDI BIT11
|
||||
|
||||
/**************** Bit definition for UART RIS register ***********************/
|
||||
#define UART_EX_RIS_BCNTI BIT12
|
||||
#define UART_EX_RIS_LBDI BIT11
|
||||
|
||||
/**************** Bit definition for UART BCNT register ***********************/
|
||||
#define UART_EX_BCNT_START BIT8
|
||||
#define UART_EX_BCNT_VALUE_POS (0U)
|
||||
#define UART_EX_BCNT_VALUE_MASK (0xFFU)
|
||||
|
||||
/**************** Definition of LIN BUS VERSION ***********************/
|
||||
#define UART_LIN_V1D3 0 //Lin bus version 1.3
|
||||
#define UART_LIN_V2DX 1 //Lin bus version 2.0/2.1/2.2
|
||||
|
||||
void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size);
|
||||
void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size);
|
||||
uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout);
|
||||
uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,118 @@
|
||||
|
||||
/***********************************************************************
|
||||
* Filename : HAL_WDT.h
|
||||
* Description : HAL WDT driver header file
|
||||
* Author(s) : CWT
|
||||
* version : V1.0
|
||||
* Modify date : 2020-04-17
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __HAL_WDT_H__
|
||||
#define __HAL_WDT_H__
|
||||
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
/**************** Bit definition for WDT CTRL register ********************/
|
||||
#define WDT_CTRL_EN BIT7
|
||||
#define WDT_CTRL_MODE BIT6
|
||||
#define WDT_CTRL_INTEN BIT4
|
||||
#define WDT_CTRL_DIVISOR (BIT0|BIT1|BIT2)
|
||||
|
||||
/**************** Bit definition for WDTRIS register ********************/
|
||||
#define WDT_WDTRIS BIT0
|
||||
|
||||
typedef enum
|
||||
{
|
||||
WDT_MODE_RST = 0x00U,
|
||||
WDT_MODE_INT = 0x01U,
|
||||
} WDT_MODE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
WDT_DIVISOR_NONE = 0x00U,
|
||||
WDT_DIVISOR_2 = 0x01U,
|
||||
WDT_DIVISOR_4 = 0x02U,
|
||||
WDT_DIVISOR_8 = 0x03U,
|
||||
WDT_DIVISOR_16 = 0x04U,
|
||||
WDT_DIVISOR_32 = 0x05U,
|
||||
WDT_DIVISOR_64 = 0x06U,
|
||||
WDT_DIVISOR_128 = 0x07U,
|
||||
} WDT_DIVISOR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
WDT_DIVISOR WDTDivisor;
|
||||
WDT_MODE WDTMode;
|
||||
uint32_t WDTLoad;
|
||||
uint32_t WDTINTCLRTIME;
|
||||
} WDT_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
WDT_TypeDef *Instance; /*!< WDT registers base address */
|
||||
WDT_InitTypeDef Init; /*!< WDT communication parameters */
|
||||
}WDT_HandleTypeDef;
|
||||
|
||||
#define WDT_ENABLE (0x01 << 7)
|
||||
#define WDT_DISABLE (~WDT_ENABLE)
|
||||
#define WDT_INT_ENABLE (0x01 << 4)
|
||||
#define WDT_INT_DISABLE (~WDT_INT_ENABLE)
|
||||
/************************************************************************
|
||||
* function : HAL_WDT_Feed
|
||||
* Description: WDT feed.
|
||||
* input :
|
||||
* none
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt);
|
||||
/************************************************************************
|
||||
* function : WDT_IRQHandler
|
||||
* Description: WDT interrupt service routine.
|
||||
* input :
|
||||
* none
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt);
|
||||
/************************************************************************
|
||||
* function : HAL_WDT_Init
|
||||
* Description: WDT initiation.
|
||||
* input :
|
||||
* pinit initiation parameters
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Init(WDT_HandleTypeDef* hwdt);
|
||||
/************************************************************************
|
||||
* function : WDT_Start
|
||||
* Description: WDT start
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Start(WDT_HandleTypeDef* hwdt);
|
||||
/************************************************************************
|
||||
* function : WDT_Stop
|
||||
* Description: WDT stop
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt);
|
||||
/************************************************************************
|
||||
* function : WDT_Int_Enable
|
||||
* Description: WDT int enable
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt);
|
||||
/************************************************************************
|
||||
* function : WDT_Int_Disable
|
||||
* Description: WDT int disable
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_Crc.c
|
||||
* @author Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
|
||||
* @ Initialization and de-initialization functions
|
||||
* @ IO operation functions
|
||||
* @ Peripheral Control functions
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_CRC_Init
|
||||
* Description : Initialize the CRC MSP.
|
||||
* Input : hcrc: CRC handle.
|
||||
* Output :
|
||||
* Author : cl Data : 2021
|
||||
**********************************************************************************/
|
||||
void HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
System_Module_Enable(EN_CRC);
|
||||
hcrc->Instance->CTRL = hcrc->Init.PolyRev | hcrc->Init.OutxorRev | hcrc->Init.InitRev | hcrc->Init.RsltRev |
|
||||
hcrc->Init.DataRev | hcrc->Init.PolyLen | hcrc->Init.DataLen;
|
||||
|
||||
hcrc->Instance->INIT = hcrc->Init.InitData;
|
||||
hcrc->Instance->OUTXOR = hcrc->Init.OutXorData;
|
||||
hcrc->Instance->POLY = hcrc->Init.PolyData;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_CRC_Calculate
|
||||
* Description : Calculate the crc calue of input data.
|
||||
* Input : hcrc: CRC handle.
|
||||
* Output : CRC value
|
||||
* Author : cl Data : 2021
|
||||
**********************************************************************************/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
HAL_CRC_Init(hcrc);
|
||||
|
||||
while(hcrc->CRC_Data_Len--)
|
||||
{
|
||||
hcrc->Instance->DATA = *hcrc->CRC_Data_Buff++;
|
||||
}
|
||||
|
||||
return (hcrc->Instance->DATA);
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_EFlash.c
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief EFlash HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* @ Program operations functions
|
||||
* @ Erase operations functions
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EFlash_Init
|
||||
* Description : Configure eflash parameter as system clock
|
||||
* Input : system clock frequency
|
||||
* Output : None
|
||||
* Author : Chris_Kyle
|
||||
**********************************************************************************/
|
||||
void HAL_EFlash_Init(uint32_t fu32_freq)
|
||||
{
|
||||
HAL_EFlash_Init_Para(fu32_freq);
|
||||
}
|
||||
|
||||
#if (__ACCELERATE_EH_PRESENT == 0)
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EFlash_Erase_Page
|
||||
* Description : Erase a Page, TERASE has been configured in System_Clock_Init()
|
||||
* Input :
|
||||
* Output : false: FAIL
|
||||
true: SUCCESS
|
||||
* Author : Chris_Kyle
|
||||
**********************************************************************************/
|
||||
bool HAL_EFlash_ErasePage(uint32_t fu32_Addr)
|
||||
{
|
||||
EFC->CTRL |= EFC_CTRL_PAGE_ERASE_MODE;
|
||||
|
||||
EFC->SEC = 0x55AAAA55;
|
||||
|
||||
*((volatile uint32_t *)fu32_Addr) = 0;
|
||||
|
||||
while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY));
|
||||
|
||||
EFC->CTRL &= ~EFC_CTRL_PAGE_ERASE_MODE;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EFlash_Programe
|
||||
* Description : Program a word, TPROG has been configured in System_Clock_Init()
|
||||
* Input :
|
||||
* Output : false: FAIL
|
||||
true: SUCCESS
|
||||
* Author : Chris_Kyle
|
||||
**********************************************************************************/
|
||||
bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data)
|
||||
{
|
||||
if (fu32_Addr % 4)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
EFC->CTRL |= EFC_CTRL_PROGRAM_MODE;
|
||||
|
||||
EFC->SEC = 0x55AAAA55;
|
||||
|
||||
*((volatile uint32_t *)fu32_Addr) = fu32_Data;
|
||||
|
||||
while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY));
|
||||
|
||||
EFC->CTRL &= ~EFC_CTRL_PROGRAM_MODE;
|
||||
|
||||
return true;
|
||||
}
|
||||
#else
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EFlash_Erase_Page
|
||||
* Description : Erase a Page, TERASE has been configured in System_Clock_Init()
|
||||
* Input :
|
||||
* Output : false: FAIL
|
||||
true: SUCCESS
|
||||
* Author : Chris_Kyle
|
||||
**********************************************************************************/
|
||||
bool HAL_EFlash_ErasePage(uint32_t fu32_Addr)
|
||||
{
|
||||
HAL_EFlash_ErasePage_EX(fu32_Addr);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EFlash_Programe
|
||||
* Description : Program a word, TPROG has been configured in System_Clock_Init()
|
||||
* Input :
|
||||
* Output : false: FAIL
|
||||
true: SUCCESS
|
||||
* Author : Chris_Kyle
|
||||
**********************************************************************************/
|
||||
bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data)
|
||||
{
|
||||
if (fu32_Addr % 4)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
HAL_EFlash_Program_Word_EX(fu32_Addr, fu32_Data);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file HAL_EXTI.c
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
|
||||
* + Initialization functions
|
||||
* + IO operation functions
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EXTI_IRQHandler
|
||||
* Description : Handle EXTI interrupt request.
|
||||
* Input : huart: EXTI handle.
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020��
|
||||
**********************************************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
if (EXTI->PDR & hexti->u32_Line)
|
||||
{
|
||||
EXTI->PDR = hexti->u32_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EXTI_SetConfigLine
|
||||
* Description :
|
||||
* Input :
|
||||
* Outpu :
|
||||
* Author : Chris_Kyle Data : 2020年
|
||||
**********************************************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t lu32_IndexLine;
|
||||
|
||||
#if (USE_FULL_ASSERT == 1)
|
||||
if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return HAL_ERROR;
|
||||
if (!IS_EXTI_MODE(hexti->u32_Mode)) return HAL_ERROR;
|
||||
if (!IS_EXTI_TRIGGER(hexti->u32_Trigger)) return HAL_ERROR;
|
||||
|
||||
/* Line0 ~ 15 trigger from GPIO */
|
||||
if (!(hexti->u32_Line >> 16))
|
||||
{
|
||||
if (!IS_EXTI_GPIOSEL(hexti->u32_GPIOSel)) return HAL_ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
lu32_IndexLine = hexti->u32_Line;
|
||||
|
||||
/* Interrupt Mode */
|
||||
if (hexti->u32_Mode == EXTI_MODE_INTERRUPT)
|
||||
{
|
||||
EXTI->IENR |= lu32_IndexLine;
|
||||
EXTI->EENR &= ~lu32_IndexLine;
|
||||
|
||||
NVIC_ClearPendingIRQ(EXTI_IRQn);
|
||||
NVIC_EnableIRQ(EXTI_IRQn);
|
||||
}
|
||||
/* Event Mode */
|
||||
else if (hexti->u32_Mode == EXTI_MODE_EVENT)
|
||||
{
|
||||
EXTI->EENR |= lu32_IndexLine;
|
||||
EXTI->IENR &= ~lu32_IndexLine;
|
||||
}
|
||||
|
||||
|
||||
if (hexti->u32_Trigger == EXTI_TRIGGER_RISING)
|
||||
{
|
||||
EXTI->RTENR |= lu32_IndexLine;
|
||||
EXTI->FTENR &= ~lu32_IndexLine;
|
||||
}
|
||||
else if (hexti->u32_Trigger == EXTI_TRIGGER_FALLING)
|
||||
{
|
||||
EXTI->FTENR |= lu32_IndexLine;
|
||||
EXTI->RTENR &= ~lu32_IndexLine;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTENR |= lu32_IndexLine;
|
||||
EXTI->RTENR |= lu32_IndexLine;
|
||||
}
|
||||
|
||||
/* Line0 ~ 15 trigger from GPIO */
|
||||
if (!(hexti->u32_Line >> 16))
|
||||
{
|
||||
lu32_IndexLine = 0;
|
||||
|
||||
while(hexti->u32_Line >> lu32_IndexLine != 0x01)
|
||||
{
|
||||
lu32_IndexLine++;
|
||||
}
|
||||
|
||||
/* Line0 ~ 7 */
|
||||
if (lu32_IndexLine < 8)
|
||||
{
|
||||
EXTI->EXTICR1 = (EXTI->EXTICR1 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4);
|
||||
}
|
||||
/* Line8 ~ 15 */
|
||||
else
|
||||
{
|
||||
lu32_IndexLine -= 8;
|
||||
|
||||
EXTI->EXTICR2 = (EXTI->EXTICR2 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4);
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EXTI_SoftTrigger
|
||||
* Description : Software trigger EXTI
|
||||
* Input :
|
||||
* Outpu :
|
||||
* Author : Chris_Kyle Data : 2020年
|
||||
**********************************************************************************/
|
||||
void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
#if (USE_FULL_ASSERT == 1)
|
||||
if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return;
|
||||
#endif
|
||||
|
||||
/* Set pending BIT */
|
||||
EXTI->SWIER |= hexti->u32_Line;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EXTI_GetPending
|
||||
* Description : Get interrupt pending bit of a dedicated line.
|
||||
* Input :
|
||||
* Outpu :
|
||||
* Author : Chris_Kyle Data : 2020年
|
||||
**********************************************************************************/
|
||||
bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
#if (USE_FULL_ASSERT == 1)
|
||||
if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return HAL_ERROR;
|
||||
#endif
|
||||
|
||||
if (hexti->u32_Line & EXTI->PDR)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EXTI_ClearPending
|
||||
* Description : Clear interrupt pending bit of a dedicated line.
|
||||
* Input :
|
||||
* Outpu :
|
||||
* Author : Chris_Kyle Data : 2020年
|
||||
**********************************************************************************/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
#if (USE_FULL_ASSERT == 1)
|
||||
if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return;
|
||||
#endif
|
||||
|
||||
/* Clear pending status */
|
||||
EXTI->PDR |= hexti->u32_Line;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_EXTI_ClearAllPending
|
||||
* Description : Clear all interrupt pending bit.
|
||||
* Input :
|
||||
* Outpu :
|
||||
* Author : xwl Data : 2021年
|
||||
**********************************************************************************/
|
||||
void HAL_EXTI_ClearAllPending(void)
|
||||
{
|
||||
/* Clear pending status */
|
||||
EXTI->PDR |= EXTI_LINE_MASK;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
|
||||
/***********************************************************************
|
||||
* Filename : HAL_IWDT.c
|
||||
* Description : HAL IWDT driver source file
|
||||
* Author(s) : CWT
|
||||
* version : V1.0
|
||||
* Modify date : 2020-04-17
|
||||
***********************************************************************/
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt)
|
||||
{
|
||||
if (hidt == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
System_Module_Enable(EN_IWDT);
|
||||
System_Delay(1);
|
||||
|
||||
System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);
|
||||
System_Enable_RC32K();
|
||||
System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_IWDT, FUNC_ENABLE);
|
||||
/*Enable IWDT */
|
||||
hidt->Instance->CMDR = IWDT_ENABLE_COMMAND;
|
||||
System_Delay(10);
|
||||
/*Enable Write */
|
||||
hidt->Instance->CMDR = IWDT_WRITE_ENABLE_COMMAND;
|
||||
System_Delay(10);
|
||||
|
||||
hidt->Instance->PR = hidt->Init.Prescaler;
|
||||
hidt->Instance->RLR = hidt->Init.Reload;
|
||||
hidt->Instance->WINR = hidt->Init.Window;
|
||||
hidt->Instance->WUTR = hidt->Init.Wakeup;
|
||||
System_Delay(1);
|
||||
while(hidt->Instance->SR & (0x0F)){}; // wait for configuration done
|
||||
|
||||
if (hidt->Init.Reload > hidt->Init.Wakeup)
|
||||
{
|
||||
/*Enable Wake up */
|
||||
hidt->Instance->CMDR = IWDT_WAKEUP_ENABLE_COMMAND;
|
||||
}
|
||||
|
||||
hidt->Instance->CMDR = IWDT_RELOAD_COMMAND;
|
||||
System_Delay(1);
|
||||
while(hidt->Instance->SR & (1 << 4)){};
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt)
|
||||
{
|
||||
hidt->Instance->CMDR = IWDT_RELOAD_COMMAND;
|
||||
System_Delay(1);
|
||||
while(hidt->Instance->SR & (1 << 4)){}; //wait for kick watchdog done
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,160 @@
|
||||
/***********************************************************************
|
||||
* Filename : hal_lpuart.c
|
||||
* Description : lpuart driver source file
|
||||
* Author(s) : xwl
|
||||
* version : V1.0
|
||||
* Modify date : 2021-04-02
|
||||
***********************************************************************/
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_TIMER_ConfigBreakDeadTime
|
||||
* Description : configure deadtime parameter
|
||||
* Input : timer handler, break and deadtime configuration
|
||||
* Output : none
|
||||
* Author : xwl
|
||||
**********************************************************************************/
|
||||
void HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
|
||||
{
|
||||
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
|
||||
uint32_t break_deadtime_reg = 0U;
|
||||
|
||||
/* Set the BDTR bits */
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
||||
MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
||||
|
||||
/* Set TIMx_BDTR */
|
||||
htim->Instance->BDTR = break_deadtime_reg;
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_TIMEx_ConfigBreakInput
|
||||
* Description : Configures the break input source.
|
||||
* Input :
|
||||
htim: timer handler
|
||||
BreakInput: TIM_BREAKINPUT_BRK
|
||||
sBreakInputConfig: Break input source configuration
|
||||
* Output :
|
||||
* Author : xwl
|
||||
**********************************************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
|
||||
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
|
||||
{
|
||||
uint32_t tmporx;
|
||||
uint32_t bkin_enable_mask;
|
||||
uint32_t bkin_polarity_mask;
|
||||
uint32_t bkin_enable_bitpos;
|
||||
uint32_t bkin_polarity_bitpos;
|
||||
|
||||
switch(sBreakInputConfig->Source)
|
||||
{
|
||||
case TIM_BREAKINPUTSOURCE_BKIN:
|
||||
{
|
||||
bkin_enable_mask = TIM1_AF1_BKINE;
|
||||
bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
|
||||
bkin_polarity_mask = TIM1_AF1_BKINP;
|
||||
bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
|
||||
break;
|
||||
}
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
case TIM_BREAKINPUTSOURCE_COMP1:
|
||||
{
|
||||
bkin_enable_mask = TIM1_AF1_BKCMP1E;
|
||||
bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
|
||||
bkin_polarity_mask = TIM1_AF1_BKCMP1P;
|
||||
bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
|
||||
break;
|
||||
}
|
||||
case TIM_BREAKINPUTSOURCE_COMP2:
|
||||
{
|
||||
bkin_enable_mask = TIM1_AF1_BKCMP2E;
|
||||
bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
|
||||
bkin_polarity_mask = TIM1_AF1_BKCMP2P;
|
||||
bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
|
||||
break;
|
||||
}
|
||||
#endif /* COMP1 && COMP2 */
|
||||
|
||||
default:
|
||||
{
|
||||
bkin_enable_mask = 0U;
|
||||
bkin_enable_bitpos = 0U;
|
||||
bkin_polarity_mask = 0U;
|
||||
bkin_polarity_bitpos = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
switch(BreakInput)
|
||||
{
|
||||
case TIM_BREAKINPUT_BRK:
|
||||
{
|
||||
/* Get the TIMx_AF1 register value */
|
||||
tmporx = htim->Instance->AF1;
|
||||
|
||||
/* Enable the break input */
|
||||
tmporx &= ~bkin_enable_mask;
|
||||
tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
|
||||
|
||||
/* Set the break input polarity */
|
||||
tmporx &= ~bkin_polarity_mask;
|
||||
tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
|
||||
|
||||
/* Set TIMx_AF1 */
|
||||
htim->Instance->AF1 = tmporx;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************************
|
||||
* Function : HAL_TIMEx_ConfigCommutEvent
|
||||
* Description : Configure the TIM commutation event sequence. This function is mandatory to use the commutation event
|
||||
in order to update the configuration at each commutation detection on the TRGI input of the Timer.
|
||||
* Input :
|
||||
htim: timer handler
|
||||
InputTrigger: TIM_TRIGGER_SOURCE_ITR0, TIM_TRIGGER_SOURCE_ITR1...
|
||||
CommutationSource: TIM_COMMUTATION_TRGI, TIM_COMMUTATION_SOFTWARE
|
||||
* Output :
|
||||
* Author : xwl
|
||||
**********************************************************************************/
|
||||
void HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
||||
{
|
||||
|
||||
if ((InputTrigger == TIM_TRIGGER_SOURCE_ITR0) || (InputTrigger == TIM_TRIGGER_SOURCE_ITR1) ||
|
||||
(InputTrigger == TIM_TRIGGER_SOURCE_ITR2) || (InputTrigger == TIM_TRIGGER_SOURCE_ITR3))
|
||||
{
|
||||
/* Select the Input trigger */
|
||||
htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6));
|
||||
htim->Instance->SMCR |= InputTrigger;
|
||||
}
|
||||
|
||||
/* Select the Capture Compare preload feature */
|
||||
htim->Instance->CR2 |= TIM_CR2_CCPC;
|
||||
/* Select the Commutation event source */
|
||||
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
||||
htim->Instance->CR2 |= CommutationSource;
|
||||
|
||||
/* Disable Commutation Interrupt */
|
||||
HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
|
||||
|
||||
/* Disable Commutation DMA request */
|
||||
HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
|
||||
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
/***********************************************************************
|
||||
* Filename : HAL_WDT.c
|
||||
* Description : HAL WDT driver source file
|
||||
* Author(s) : CWT
|
||||
* version : V1.0
|
||||
* Modify date : 2020-04-17
|
||||
***********************************************************************/
|
||||
#include "ACM32Fxx_HAL.h"
|
||||
|
||||
/************************************************************************
|
||||
* function : HAL_WDT_Feed
|
||||
* Description: WDT feed.
|
||||
* input :
|
||||
* none
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
hwdt->Instance->FEED = 0xAA55A55A;
|
||||
}
|
||||
/************************************************************************
|
||||
* function : HAL_WDT_IRQHandler
|
||||
* Description: WDT interrupt service routine.
|
||||
* input :
|
||||
* none
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
volatile uint32_t wdt_ris = 0;
|
||||
wdt_ris = hwdt->Instance->RIS;
|
||||
HAL_WDT_Feed(hwdt);
|
||||
NVIC_ClearPendingIRQ(WDT_IRQn);
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* function : HAL_WDT_Init
|
||||
* Description: WDT initiation.
|
||||
* input :
|
||||
* pinit initiation parameters
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Init(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
System_Module_Enable(EN_WDT);
|
||||
System_Delay(1);
|
||||
System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);
|
||||
System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_WDT, FUNC_ENABLE);
|
||||
|
||||
hwdt->Instance->LOAD = hwdt->Init.WDTLoad;
|
||||
hwdt->Instance->CTRL = (hwdt->Instance->CTRL & ~0x47) | (hwdt->Init.WDTDivisor) | (hwdt->Init.WDTMode << 6);
|
||||
|
||||
if (WDT_MODE_INT == hwdt->Init.WDTMode)
|
||||
{
|
||||
hwdt->Instance->INTCLRTIME = hwdt->Init.WDTINTCLRTIME;
|
||||
HAL_WDT_Int_Enable(hwdt);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* function : HAL_WDT_Start
|
||||
* Description: WDT start
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Start(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
hwdt->Instance->CTRL |= WDT_ENABLE;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* function : WDT_Stop
|
||||
* Description: WDT stop
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
hwdt->Instance->CTRL &= WDT_DISABLE;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* function : WDT_Int_Enable
|
||||
* Description: WDT int enable
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
hwdt->Instance->CTRL |= WDT_INT_ENABLE;
|
||||
NVIC_ClearPendingIRQ(WDT_IRQn);
|
||||
NVIC_EnableIRQ(WDT_IRQn);
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* function : WDT_Int_Disable
|
||||
* Description: WDT int disable
|
||||
* input : none
|
||||
*
|
||||
* return: none
|
||||
************************************************************************/
|
||||
void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt)
|
||||
{
|
||||
hwdt->Instance->CTRL &= WDT_INT_DISABLE;
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Split("""
|
||||
Device/System_ACM32F4.c
|
||||
HAL_Driver/Src/HAL_EFlash.c
|
||||
HAL_Driver/Src/HAL_DMA.c
|
||||
HAL_Driver/Src/HAL_GPIO.c
|
||||
HAL_Driver/Src/HAL_UART.c
|
||||
HAL_Driver/Src/HAL_EXTI.c
|
||||
""")
|
||||
|
||||
|
||||
libpath = ['.', cwd + '/Device', cwd + '/HAL_Driver/Src']
|
||||
libs = ['System_Accelerate', 'HAL_EFlash_EX']
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += ['Device/Startup_ACM32F4_gcc.s']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += ['Device/Startup_ACM32F4.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += ['Device/Startup_ACM32F4_iar.s']
|
||||
|
||||
path = [cwd + '/HAL_Driver/Inc',
|
||||
cwd + '/Device',
|
||||
cwd + '/CMSIS']
|
||||
|
||||
group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath)
|
||||
|
||||
Return('group')
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
/* RT-Thread Project Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
@@ -16,8 +16,13 @@
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_DEBUG
|
||||
#define RT_DEBUG_COLOR
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
@@ -36,16 +41,17 @@
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_DEVICE_OPS
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40002
|
||||
#define RT_VER_NUM 0x40004
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 256
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
@@ -54,17 +60,17 @@
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define RT_USING_MSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 2048
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_USING_MSH_ONLY
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
@@ -75,6 +81,8 @@
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
@@ -83,6 +91,8 @@
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||
|
||||
/* Network */
|
||||
|
||||
@@ -104,6 +114,9 @@
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
@@ -143,41 +156,60 @@
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
#define SOC_ES32F0271LT
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
#define SOC_ACM32F403RET7
|
||||
|
||||
/* PIN Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
|
||||
/* UART Drivers */
|
||||
|
||||
#define BSP_USING_UART1
|
||||
|
||||
/* SPI Drivers */
|
||||
|
||||
|
||||
/* I2C Drivers */
|
||||
|
||||
|
||||
/* HWtimer Drivers */
|
||||
|
||||
|
||||
/* PWM Drivers */
|
||||
|
||||
|
||||
/* RTC Drivers */
|
||||
|
||||
|
||||
/* ADC Drivers */
|
||||
/* ACM32F403RET7 */
|
||||
|
||||
#define SOC_SRAM_START_ADDR 0x20000000
|
||||
#define SOC_SRAM_SIZE 0xC0
|
||||
#define SOC_FLASH_START_ADDR 0x00000000
|
||||
#define SOC_FLASH_SIZE 0x8000
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* Offboard Peripheral Drivers */
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
/* Hardware GPIO */
|
||||
|
||||
#define BSP_USING_GPIO1
|
||||
#define BSP_USING_GPIO2
|
||||
#define BSP_USING_GPIO3
|
||||
|
||||
/* Hardware UART */
|
||||
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_USING_UART2
|
||||
#define BSP_UART2_RX_USING_DMA
|
||||
#define BSP_UART2_TX_USING_DMA
|
||||
#define BSP_USING_UART3
|
||||
#define BSP_UART3_RX_USING_DMA
|
||||
#define BSP_UART3_TX_USING_DMA
|
||||
#define BSP_USING_UART4
|
||||
#define BSP_UART4_RX_USING_DMA
|
||||
#define BSP_UART4_TX_USING_DMA
|
||||
|
||||
/* Hardware I2C */
|
||||
|
||||
|
||||
/* Hardware CAN */
|
||||
|
||||
|
||||
/* Hardware TIMER */
|
||||
|
||||
|
||||
/* Hardware WDT */
|
||||
|
||||
|
||||
/* Hardware SPI */
|
||||
|
||||
|
||||
/* Hardware CRYPTO */
|
||||
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,151 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m33'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'D:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
#BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armclang'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU
|
||||
CFLAGS = ' -xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c'
|
||||
CFLAGS += ' -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__MICROLIB -mlittle-endian -ffunction-sections'
|
||||
|
||||
AFLAGS = ' --cpu=Cortex-M33 --fpu=FPv5-SP --li --pd "__MICROLIB SETA 1" --pd "__UVISION_VERSION SETA 531" --pd "ARMCM33_DSP_FP SETA 1"'
|
||||
|
||||
LFLAGS = ' --cpu=Cortex-M33 --info sizes --info totals --info unused --info veneers --list ./build/ACM32F4.map --scatter ./build/ACM32F4.sct'
|
||||
LFLAGS += ' --library_type=microlib --strict'
|
||||
LFLAGS += ' --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols'
|
||||
|
||||
EXEC_PATH += '/ARM/ARMCLANG/bin'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -gdwarf-3 -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -gdwarf-3 -O1'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=' + CPU
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu ' + CPU
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,95 +0,0 @@
|
||||
# ES-PDS-ES32F0271 开发板 BSP 说明
|
||||
标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT
|
||||
|
||||
## 1. 简介
|
||||
|
||||
本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。
|
||||
通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
|
||||
|
||||
### 1.1 开发板介绍
|
||||
|
||||
主要内容如下：
|
||||
ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。
|
||||
|
||||
ES-PDS-ES32F0271-V1.1
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH
|
||||
- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
|
||||
- 常用外设
|
||||
- 可调电阻：1个，(PC03)
|
||||
- LED：2个，(PD03/PB08)
|
||||
- 五轴按键：
|
||||
- 常用接口：GPIO、UART、SPI、I2C
|
||||
- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
|
||||
|
||||
外设支持:
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :---------------- | :----------: | :------------------------------------|
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| GPIO | 支持 | GPIOs |
|
||||
| UART | 支持 | UART1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| I2C | 支持 | I2C1/2 |
|
||||
| PWM | 支持 | PWM1/2 |
|
||||
| TIMER | 支持 | TIMER1 |
|
||||
| RTC | 支持 | RTC |
|
||||
| ADC | 支持 | ADC |
|
||||
|
||||
### 1.2 注意事项
|
||||
|
||||
- 本BSP中，SPI2和PWM2不能同时使用
|
||||
|
||||
更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
|
||||
|
||||
## 2. 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
### 硬件连接
|
||||
|
||||
使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。
|
||||
|
||||
ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1
|
||||
|
||||
### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
|
||||
|
||||
### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.2 build Oct 31 2019
|
||||
2006 - 2019 Copyright by rt-thread team
|
||||
msh >
|
||||
```
|
||||
## 3. 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
|
||||
|
||||
## 4. 联系人信息
|
||||
|
||||
- [yuzr](https://github.com/essemi-yuzr)
|
||||
|
||||
## 5. 参考
|
||||
|
||||
- [ EastSoft 官网](http://www.essemi.com)
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
|
||||
objs = []
|
||||
cwd = str(Dir('#'))
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -1,39 +0,0 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define LED_PIN 61
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* LED pin configuration */
|
||||
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(1000);
|
||||
rt_pin_write(LED_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(1000);
|
||||
}
|
||||
}
|
||||
@@ -1,102 +0,0 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
menu "PIN Drivers"
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
endmenu
|
||||
|
||||
menu "UART Drivers"
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1 PB06/PB07(T/R)"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2 PA02/PA03(T/R)"
|
||||
select RT_USING_SERIAL
|
||||
default n
|
||||
|
||||
config BSP_USING_UART3
|
||||
bool "Enable UART3 PC06/PC07(T/R)"
|
||||
select RT_USING_SERIAL
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "SPI Drivers"
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
|
||||
select RT_USING_SPI
|
||||
select RT_USING_PIN
|
||||
default n
|
||||
|
||||
config BSP_USING_SPI2
|
||||
bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)"
|
||||
select RT_USING_SPI
|
||||
select RT_USING_PIN
|
||||
default n
|
||||
depends on !BSP_USING_PWM_GP16C2T4
|
||||
endmenu
|
||||
|
||||
menu "I2C Drivers"
|
||||
config BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)"
|
||||
select RT_USING_I2C
|
||||
default n
|
||||
|
||||
config BSP_USING_I2C2
|
||||
bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)"
|
||||
select RT_USING_I2C
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "HWtimer Drivers"
|
||||
|
||||
config BSP_USING_HWTIMER1
|
||||
bool "Using timer1"
|
||||
select RT_USING_HWTIMER
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "PWM Drivers"
|
||||
|
||||
config BSP_USING_PWM_GP16C2T1
|
||||
bool "Using PWM_1(GP16C2T1) PB01/PB02"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM_GP16C2T4
|
||||
bool "Using PWM2(GP16C2T4) PB12/PB14"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
depends on !BSP_USING_SPI2
|
||||
|
||||
endmenu
|
||||
|
||||
menu "RTC Drivers"
|
||||
config BSP_USING_RTC
|
||||
bool "Using RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "ADC Drivers"
|
||||
config BSP_USING_ADC
|
||||
bool "Using ADC"
|
||||
select RT_USING_ADC
|
||||
default n
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Offboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -1,45 +0,0 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
# add gpio code
|
||||
if GetDepend('RT_USING_PIN'):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
# add serial driver code
|
||||
if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
|
||||
src += ['drv_uart.c']
|
||||
|
||||
# add spi driver code
|
||||
if GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'):
|
||||
src += ['drv_spi.c']
|
||||
|
||||
# add i2c driver code
|
||||
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
|
||||
src += ['drv_i2c.c']
|
||||
|
||||
# add pwm driver code
|
||||
if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'):
|
||||
src += ['drv_pwm.c']
|
||||
|
||||
# add hwtimer driver code
|
||||
if GetDepend('BSP_USING_HWTIMER1'):
|
||||
src += ['drv_hwtimer.c']
|
||||
|
||||
# add rtc driver code
|
||||
if GetDepend(['BSP_USING_RTC']):
|
||||
src += ['drv_rtc.c']
|
||||
|
||||
# add adc driver code
|
||||
if GetDepend(['BSP_USING_ADC']):
|
||||
src += ['drv_adc.c']
|
||||
|
||||
CPPPATH = [cwd]
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -1,136 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "drv_gpio.h"
|
||||
#include "md_gpio.h"
|
||||
|
||||
/**
|
||||
* @addtogroup es32f0
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_Configuration
|
||||
* Description : Configures Vector Table base location.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SystemClock_Configuration
|
||||
* Description : Configures the System Clock.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
/*-------------------------Clock Config-------------------------/
|
||||
* Config system clock to 48MHz of which the clock source
|
||||
* is PLL0.
|
||||
*/
|
||||
|
||||
//
|
||||
// Open PLL0/HRC then wait it ready.
|
||||
//
|
||||
SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK);
|
||||
SET_BIT(RCU->CON, RCU_CON_HRCON_MSK);
|
||||
|
||||
/* Wait HRC clock steady. */
|
||||
while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK));
|
||||
|
||||
//
|
||||
// Change system clock source,PLL0,48MHz.
|
||||
//
|
||||
/* Chose PLL0 as system clock. */
|
||||
MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS));
|
||||
/* Config mul of PLL0. */
|
||||
MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS));
|
||||
|
||||
//
|
||||
// Start to change system clock and wait it ready.
|
||||
//
|
||||
/* Config flash read wait time. */
|
||||
MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS));
|
||||
/* Start to change. */
|
||||
SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK);
|
||||
|
||||
/* Wait system clock ready. */
|
||||
while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK));
|
||||
|
||||
//
|
||||
// Remember the system clock.
|
||||
//
|
||||
SystemCoreClock = 48000000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SysTick_Configuration
|
||||
* Description : Configures the SysTick for OS tick.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SysTick_Configuration(void)
|
||||
{
|
||||
/* ticks = sysclk / RT_TICK_PER_SECOND */
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/**
|
||||
* This function will initial ES32F0 board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
NVIC_Configuration();
|
||||
|
||||
/*System Clock Configuration */
|
||||
SystemClock_Config();
|
||||
|
||||
/* Configure the SysTick */
|
||||
SysTick_Configuration();
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "es32f0271.h"
|
||||
|
||||
#define ES32F0_SRAM_SIZE 0x2000
|
||||
#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE)
|
||||
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END ES32F0_SRAM_END
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,148 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
#include "drv_adc.h"
|
||||
#include "md_gpio.h"
|
||||
#include "md_adc.h"
|
||||
#include "md_rcu.h"
|
||||
#include "md_syscfg.h"
|
||||
|
||||
#ifdef RT_USING_ADC
|
||||
|
||||
#define BSP_ADC_CHANNEL_NUM 8
|
||||
|
||||
/* define adc instance */
|
||||
static struct rt_adc_device _device_adc0;
|
||||
|
||||
/* enable or disable adc */
|
||||
static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
if (enabled)
|
||||
{
|
||||
md_adc_enable_ssen_ss0en(ADC);
|
||||
}
|
||||
else
|
||||
{
|
||||
md_adc_disable_ssen_ss0en(ADC);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void _adc_channel_config(rt_uint32_t channel)
|
||||
{
|
||||
/* select gpio pin as adc function */
|
||||
switch (channel)
|
||||
{
|
||||
case 0:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 1:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 2:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 3:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 4:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 5:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 6:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 7:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
|
||||
{
|
||||
rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM];
|
||||
rt_uint32_t i;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(value != RT_NULL);
|
||||
|
||||
/* config adc channel */
|
||||
_adc_channel_config(channel);
|
||||
|
||||
md_adc_set_swtri_ss0(ADC);
|
||||
|
||||
while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0);
|
||||
|
||||
for (i=0; i<BSP_ADC_CHANNEL_NUM; i++)
|
||||
chn_data[i] = md_adc_get_ss0_data(ADC);
|
||||
|
||||
*value = chn_data[channel];
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_adc_ops es32f0_adc_ops =
|
||||
{
|
||||
es32f0_adc_enabled,
|
||||
es32f0_get_adc_value,
|
||||
};
|
||||
|
||||
int rt_hw_adc_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
|
||||
md_rcu_enable_apb2en_adcen(RCU);
|
||||
|
||||
md_syscfg_enable_cfg_currgen(SYSCFG);
|
||||
md_syscfg_enable_cfg_vrefen(SYSCFG);
|
||||
md_syscfg_set_cfg_vlrs(SYSCFG, 7);
|
||||
|
||||
md_adc_set_ss0_con_sel(ADC, MD_ADC_SS_CON_SEL_SW);
|
||||
md_adc_set_ss0_con_type(ADC, MD_ADC_SS_CON_TYPE_EDGE);
|
||||
md_adc_set_frf_ffrst(ADC);
|
||||
md_adc_set_ss0_mux0_mux7(ADC, MD_ADC_SS_MUX_ADIN7);
|
||||
md_adc_set_ss0_mux0_mux6(ADC, MD_ADC_SS_MUX_ADIN6);
|
||||
md_adc_set_ss0_mux0_mux5(ADC, MD_ADC_SS_MUX_ADIN5);
|
||||
md_adc_set_ss0_mux0_mux4(ADC, MD_ADC_SS_MUX_ADIN4);
|
||||
md_adc_set_ss0_mux0_mux3(ADC, MD_ADC_SS_MUX_ADIN3);
|
||||
md_adc_set_ss0_mux0_mux2(ADC, MD_ADC_SS_MUX_ADIN2);
|
||||
md_adc_set_ss0_mux0_mux1(ADC, MD_ADC_SS_MUX_ADIN1);
|
||||
md_adc_set_ss0_mux0_mux0(ADC, MD_ADC_SS_MUX_ADIN0);
|
||||
md_adc_enable_ier_ss0ie(ADC);
|
||||
md_adc_set_ss0_end_end(ADC, 7);
|
||||
md_adc_enable_ss0_end_ie7(ADC);
|
||||
md_adc_set_gainl_ch7pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch6pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch5pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch4pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch3pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch2pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch1pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch0pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_srate(ADC, MD_ADC_SRATE_CLKDIV1 | ADC_SRATE_CKEN_MSK);
|
||||
|
||||
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, ADC);
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_adc_init);
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user