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feat:[STM32][I2C]:Distinguish STM32 I2C timing semantics by IP generation

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This commit is contained in:
wdfk-prog
2026-04-13 17:52:38 +08:00
committed by Rbb666
parent bd53bbaa76
commit 141895ec82
4 changed files with 137 additions and 35 deletions
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bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h
+3
View File
@@ -22,6 +22,7 @@ extern "C" {
#define I2C1_BUS_CONFIG \
{ \
.Instance = I2C1, \
.timing = 100000, \
.timeout=0x1000, \
.name = "hwi2c1", \
.evirq_type = I2C1_EV_IRQn, \
@@ -57,6 +58,7 @@ extern "C" {
#define I2C2_BUS_CONFIG \
{ \
.Instance = I2C2, \
.timing = 100000, \
.timeout=0x1000, \
.name = "hwi2c2", \
.evirq_type = I2C2_EV_IRQn, \
@@ -92,6 +94,7 @@ extern "C" {
#define I2C3_BUS_CONFIG \
{ \
.Instance = I2C3, \
.timing = 100000, \
.timeout=0x1000, \
.name = "hwi2c3", \
.evirq_type = I2C3_EV_IRQn, \
bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h
+4 -4
View File
@@ -23,7 +23,7 @@ extern "C" {
#define I2C1_BUS_CONFIG \
{ \
.Instance = I2C1, \
.timing=0x10707DBC, \
.timing = 100000, \
.timeout=0x1000, \
.name = "hwi2c1", \
.evirq_type = I2C1_EV_IRQn, \
@@ -81,7 +81,7 @@ extern "C" {
#define I2C2_BUS_CONFIG \
{ \
.Instance = I2C2, \
.timing=0x10707DBC, \
.timing = 100000, \
.timeout=0x1000, \
.name = "hwi2c2", \
.evirq_type = I2C2_EV_IRQn, \
@@ -139,7 +139,7 @@ extern "C" {
#define I2C3_BUS_CONFIG \
{ \
.Instance = I2C3, \
.timing=0x10707DBC, \
.timing = 100000, \
.timeout=0x1000, \
.name = "hwi2c3", \
.evirq_type = I2C3_EV_IRQn, \
@@ -197,7 +197,7 @@ extern "C" {
#define I2C4_BUS_CONFIG \
{ \
.Instance = I2C4, \
.timing = 0x10707DBC, \
.timing = 100000, \
.timeout = 0x1000, \
.name = "hwi2c4", \
.evirq_type = I2C4_EV_IRQn, \
bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c
+98 -29
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File diff suppressed because it is too large Load Diff
bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h
+32 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -7,6 +7,7 @@
* Date Author Notes
* 2024-02-17 Dyyt587 first version
* 2024-06-23 wdfk-prog Add mode selection scaffolding
* 2024-06-23 wdfk-prog Distinguish STM32 I2C timing semantics by IP generation
*/
#ifndef __DRV_HARD_I2C_H__
@@ -97,10 +98,39 @@ extern "C"
#define BSP_I2C_USING_IRQ
#endif
/*
* timing semantics are intentionally split by I2C IP generation:
*
* - legacy I2C IP:
* use bus frequency in Hz (for example 100000/400000), because HAL
* configures the peripheral through ClockSpeed/DutyCycle.
*
* - TIMINGR-based I2C IP:
* keep using the raw TIMINGR register value for now. Exact timing
* generation depends on board-level inputs such as kernel clock,
* rise/fall time, digital/analog filter settings, and target bus mode,
* so this change does not convert TIMINGR platforms to a unified Hz API.
*/
#if defined(SOC_SERIES_STM32F1) \
|| defined(SOC_SERIES_STM32F2) \
|| defined(SOC_SERIES_STM32F4) \
|| defined(SOC_SERIES_STM32L1)
#define STM32_I2C_LEGACY_IP
#else
#define STM32_I2C_TIMINGR_IP
#endif
#define BSP_I2C_CTRL_SET_TIMING 0x40
struct stm32_i2c_config
{
const char *name;
I2C_TypeDef *Instance;
/*
* timing semantics depend on the I2C IP generation:
* - legacy IP (F1/F4): bus speed in Hz
* - TIMINGR IP (F7/H7): raw TIMINGR register value
*/
rt_uint32_t timing;
rt_uint32_t timeout;
IRQn_Type evirq_type;
@@ -139,4 +169,4 @@ struct stm32_i2c
}
#endif
#endif /* __DRV_I2C_H__ */
#endif /* __DRV_HARD_I2C_H__ */